Collection by 
about 17 hours ago
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VerilogEval: Evaluating Large Language Models for Verilog Code Generation
Paper • 2309.07544 • Published • 2 -
VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification
Paper • 2505.20302 • Published • 1 -
Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form
Paper • 2506.00005 • Published -
CodeV: Empowering LLMs for Verilog Generation through Multi-Level Summarization
Paper • 2407.10424 • Published • 12
