__global__ void kernelForMSSP(int *V, int *E, int *W, int *n, int *src, int *sn, bool *visit, int *dist, int *predist){
    int u=0, stInd=0, st=0, align=0, old=0;
    __shared__ int QuickExit;
    const int blockId  = blockIdx.z *(gridDim.x *  gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
    const int threadId = threadIdx.z*(blockDim.x * blockDim.y)+ threadIdx.y* blockDim.x+ threadIdx.x;
    const int blockSize= blockDim.x * blockDim.y * blockDim.z;
    const int gridSize = gridDim.x  * gridDim.y  *  gridDim.z;
    if(blockId >= (*sn)) return ;
    if(threadId >= (*n)) return ;
    stInd = blockId;
    st = src[stInd];
    while(stInd < (*sn))
    {
        align = (stInd * (*n));
        while(1){ /* this while can solve a sssp*/ 
            QuickExit = 0;
            u = threadId;
            while(u < (*n)){
                if(visit[u + align]){
                    visit[u + align]=0;
                    for(int adj = V[u]; adj<V[u+1]; adj++){
                        old=atomicMin( &predist[align + E[adj]] , dist[align + u] + W[adj]);
                    }
                }
                u+=blockSize;
            }
            __syncthreads();
            u=threadId;
            while(u < (*n)){
                if(predist[align + u] < dist[align + u]){
                    dist[align + u] = predist[align + u];
                    visit[align + u] = 1;
                    QuickExit = 1;
                }
                u+=blockSize;
            }
            __syncthreads();
            if(QuickExit==0){
                break;
            }
        }
        __syncthreads();
        stInd += gridSize;
    }
}
	.file	"tmpxft_0037fced_00000000-6_spfa.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z49__device_stub__Z13kernelForMSSPPiS_S_S_S_S_PbS_S_PiS_S_S_S_S_PbS_S_
	.type	_Z49__device_stub__Z13kernelForMSSPPiS_S_S_S_S_PbS_S_PiS_S_S_S_S_PbS_S_, @function
_Z49__device_stub__Z13kernelForMSSPPiS_S_S_S_S_PbS_S_PiS_S_S_S_S_PbS_S_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	240(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	96(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	248(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rax, 16(%rsp)
	movq	256(%rsp), %rax
	movq	%rcx, 48(%rsp)
	leaq	88(%rsp), %rcx
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 104(%rsp)
	movq	%rax, 144(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	88(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z13kernelForMSSPPiS_S_S_S_S_PbS_S_(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 256
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L2:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z49__device_stub__Z13kernelForMSSPPiS_S_S_S_S_PbS_S_PiS_S_S_S_S_PbS_S_, .-_Z49__device_stub__Z13kernelForMSSPPiS_S_S_S_S_PbS_S_PiS_S_S_S_S_PbS_S_
	.globl	_Z13kernelForMSSPPiS_S_S_S_S_PbS_S_
	.type	_Z13kernelForMSSPPiS_S_S_S_S_PbS_S_, @function
_Z13kernelForMSSPPiS_S_S_S_S_PbS_S_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z13kernelForMSSPPiS_S_S_S_S_PbS_S_PiS_S_S_S_S_PbS_S_
	.cfi_endproc
.LFE2033:
	.size	_Z13kernelForMSSPPiS_S_S_S_S_PbS_S_, .-_Z13kernelForMSSPPiS_S_S_S_S_PbS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z13kernelForMSSPPiS_S_S_S_S_PbS_S_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z13kernelForMSSPPiS_S_S_S_S_PbS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
__global__ void kernelForMSSP(int *V, int *E, int *W, int *n, int *src, int *sn, bool *visit, int *dist, int *predist){
    int u=0, stInd=0, st=0, align=0, old=0;
    __shared__ int QuickExit;
    const int blockId  = blockIdx.z *(gridDim.x *  gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
    const int threadId = threadIdx.z*(blockDim.x * blockDim.y)+ threadIdx.y* blockDim.x+ threadIdx.x;
    const int blockSize= blockDim.x * blockDim.y * blockDim.z;
    const int gridSize = gridDim.x  * gridDim.y  *  gridDim.z;
    if(blockId >= (*sn)) return ;
    if(threadId >= (*n)) return ;
    stInd = blockId;
    st = src[stInd];
    while(stInd < (*sn))
    {
        align = (stInd * (*n));
        while(1){ /* this while can solve a sssp*/ 
            QuickExit = 0;
            u = threadId;
            while(u < (*n)){
                if(visit[u + align]){
                    visit[u + align]=0;
                    for(int adj = V[u]; adj<V[u+1]; adj++){
                        old=atomicMin( &predist[align + E[adj]] , dist[align + u] + W[adj]);
                    }
                }
                u+=blockSize;
            }
            __syncthreads();
            u=threadId;
            while(u < (*n)){
                if(predist[align + u] < dist[align + u]){
                    dist[align + u] = predist[align + u];
                    visit[align + u] = 1;
                    QuickExit = 1;
                }
                u+=blockSize;
            }
            __syncthreads();
            if(QuickExit==0){
                break;
            }
        }
        __syncthreads();
        stInd += gridSize;
    }
}
	.text
	.file	"spfa.hip"
	.globl	_Z28__device_stub__kernelForMSSPPiS_S_S_S_S_PbS_S_ # -- Begin function _Z28__device_stub__kernelForMSSPPiS_S_S_S_S_PbS_S_
	.type	_Z28__device_stub__kernelForMSSPPiS_S_S_S_S_PbS_S_,@function
_Z28__device_stub__kernelForMSSPPiS_S_S_S_S_PbS_S_: # @_Z28__device_stub__kernelForMSSPPiS_S_S_S_S_PbS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13kernelForMSSPPiS_S_S_S_S_PbS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z28__device_stub__kernelForMSSPPiS_S_S_S_S_PbS_S_, .Lfunc_end0-_Z28__device_stub__kernelForMSSPPiS_S_S_S_S_PbS_S_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13kernelForMSSPPiS_S_S_S_S_PbS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z13kernelForMSSPPiS_S_S_S_S_PbS_S_,@object # @_Z13kernelForMSSPPiS_S_S_S_S_PbS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z13kernelForMSSPPiS_S_S_S_S_PbS_S_
	.p2align	3, 0x0
_Z13kernelForMSSPPiS_S_S_S_S_PbS_S_:
	.quad	_Z28__device_stub__kernelForMSSPPiS_S_S_S_S_PbS_S_
	.size	_Z13kernelForMSSPPiS_S_S_S_S_PbS_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z13kernelForMSSPPiS_S_S_S_S_PbS_S_"
	.size	.L__unnamed_1, 36

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__kernelForMSSPPiS_S_S_S_S_PbS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z13kernelForMSSPPiS_S_S_S_S_PbS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z13kernelForMSSPPiS_S_S_S_S_PbS_S_ ; -- Begin function _Z13kernelForMSSPPiS_S_S_S_S_PbS_S_
	.globl	_Z13kernelForMSSPPiS_S_S_S_S_PbS_S_
	.p2align	8
	.type	_Z13kernelForMSSPPiS_S_S_S_S_PbS_S_,@function
_Z13kernelForMSSPPiS_S_S_S_S_PbS_S_:    ; @_Z13kernelForMSSPPiS_S_S_S_S_PbS_S_
; %bb.0:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x28
	s_load_b64 s[16:17], s[0:1], 0x48
	s_add_u32 s2, s0, 0x48
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_load_b32 s12, s[4:5], 0x0
	s_mul_i32 s20, s17, s16
	s_mul_i32 s14, s16, s14
	s_mul_i32 s15, s20, s15
	s_add_i32 s13, s14, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s22, s13, s15
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_i32 s22, s12
	s_cbranch_scc1 .LBB0_20
; %bb.1:
	s_load_b256 s[12:19], s[0:1], 0x0
	s_load_b32 s21, s[2:3], 0xc
	v_bfe_u32 v1, v0, 20, 10
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_load_b32 s23, s[18:19], 0x0
	s_lshr_b32 s24, s21, 16
	s_and_b32 s25, s21, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mul_i32 s21, s24, s25
	v_mul_u32_u24_e32 v2, s25, v2
	v_mul_lo_u32 v1, s21, v1
	v_add3_u32 v14, v2, v0, v1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s23, v14
	s_and_saveexec_b32 s23, vcc_lo
	s_cbranch_execz .LBB0_20
; %bb.2:                                ; %.lr.ph98.preheader
	s_clause 0x1
	s_load_b32 s2, s[2:3], 0x10
	s_load_b32 s1, s[0:1], 0x50
	v_dual_mov_b32 v15, 0 :: v_dual_mov_b32 v16, 1
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s2, 0xffff
	s_mul_i32 s1, s1, s20
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s2, s21, s0
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[20:21], s[2:3], 2
.LBB0_3:                                ; %.lr.ph98
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;       Child Loop BB0_6 Depth 3
                                        ;         Child Loop BB0_9 Depth 4
                                        ;       Child Loop BB0_15 Depth 3
	global_load_b32 v0, v15, s[18:19]
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v17, v0, s22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v14, v17
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
.LBB0_4:                                ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_6 Depth 3
                                        ;         Child Loop BB0_9 Depth 4
                                        ;       Child Loop BB0_15 Depth 3
	global_load_b32 v13, v15, s[18:19]
	s_mov_b32 s23, exec_lo
	ds_store_b32 v15, v15
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v14, v13
	s_cbranch_execz .LBB0_13
; %bb.5:                                ; %.lr.ph92.preheader
                                        ;   in Loop: Header=BB0_4 Depth=2
	v_mov_b32_e32 v4, v14
	s_mov_b32 s24, 0
.LBB0_6:                                ; %.lr.ph92
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_9 Depth 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v9, v4, v17
	s_mov_b32 s25, exec_lo
	v_ashrrev_i32_e32 v10, 31, v9
	v_add_co_u32 v11, vcc_lo, s6, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v10, vcc_lo
	global_load_u8 v5, v[11:12], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u16_e32 0, v5
	s_cbranch_execz .LBB0_12
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=3
	v_ashrrev_i32_e32 v5, 31, v4
	s_mov_b32 s26, exec_lo
	global_store_b8 v[11:12], v15, off
	v_lshlrev_b64 v[5:6], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s12, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s13, v6, vcc_lo
	global_load_b64 v[7:8], v[5:6], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v7, v8
	s_cbranch_execz .LBB0_11
; %bb.8:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_6 Depth=3
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_mov_b32 s27, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[12:13], 2, v[7:8]
	v_add_co_u32 v8, vcc_lo, s8, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v10, vcc_lo
	v_add_co_u32 v10, vcc_lo, s14, v12
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v11, vcc_lo, s15, v13, vcc_lo
	v_add_co_u32 v12, vcc_lo, s16, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s17, v13, vcc_lo
.LBB0_9:                                ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ;       Parent Loop BB0_6 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	global_load_b32 v18, v[10:11], off
	global_load_b32 v20, v[8:9], off
	global_load_b32 v21, v[12:13], off
	v_add_nc_u32_e32 v7, 1, v7
	v_add_co_u32 v12, s0, v12, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v13, s0, 0, v13, s0
	s_waitcnt vmcnt(2)
	v_add_nc_u32_e32 v18, v18, v17
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v20, v21, v20
	v_ashrrev_i32_e32 v19, 31, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[18:19], 2, v[18:19]
	v_add_co_u32 v18, vcc_lo, s10, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v19, vcc_lo, s11, v19, vcc_lo
	v_add_co_u32 v10, vcc_lo, v10, 4
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
	global_atomic_min_i32 v[18:19], v20, off
	global_load_b32 v18, v[5:6], off offset:4
	s_waitcnt vmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, v7, v18
	s_or_b32 s27, vcc_lo, s27
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s27
	s_cbranch_execnz .LBB0_9
; %bb.10:                               ; %.loopexit.loopexit
                                        ;   in Loop: Header=BB0_6 Depth=3
	s_or_b32 exec_lo, exec_lo, s27
	global_load_b32 v13, v15, s[18:19]
.LBB0_11:                               ; %Flow145
                                        ;   in Loop: Header=BB0_6 Depth=3
	s_or_b32 exec_lo, exec_lo, s26
.LBB0_12:                               ; %.loopexit
                                        ;   in Loop: Header=BB0_6 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s25
	v_add_nc_u32_e32 v4, s2, v4
	s_waitcnt vmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, v4, v13
	s_or_b32 s24, vcc_lo, s24
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s24
	s_cbranch_execnz .LBB0_6
.LBB0_13:                               ; %Flow147
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	global_load_b32 v10, v15, s[18:19]
	s_mov_b32 s23, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v14, v10
	s_cbranch_execz .LBB0_18
; %bb.14:                               ; %.lr.ph95.preheader
                                        ;   in Loop: Header=BB0_4 Depth=2
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	v_dual_mov_b32 v7, v1 :: v_dual_mov_b32 v6, v0
	v_mov_b32_e32 v11, v14
	s_mov_b32 s24, 0
.LBB0_15:                               ; %.lr.ph95
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v12, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v13, vcc_lo, s11, v7, vcc_lo
	v_add_co_u32 v8, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v7, vcc_lo
	s_mov_b32 s0, exec_lo
	global_load_b32 v12, v[12:13], off
	global_load_b32 v13, v[8:9], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v12, v13
	s_cbranch_execz .LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_15 Depth=3
	global_store_b32 v[8:9], v12, off
	global_load_b32 v10, v15, s[18:19]
	global_store_b8 v[4:5], v16, off
	ds_store_b32 v15, v16
.LBB0_17:                               ;   in Loop: Header=BB0_15 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v11, s2, v11
	v_add_co_u32 v6, vcc_lo, v6, s20
	v_add_co_ci_u32_e32 v7, vcc_lo, s21, v7, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e32 vcc_lo, v11, v10
	v_add_co_u32 v4, s0, v4, s2
	v_add_co_ci_u32_e64 v5, s0, s3, v5, s0
	s_or_b32 s24, vcc_lo, s24
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s24
	s_cbranch_execnz .LBB0_15
.LBB0_18:                               ; %Flow144
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v4, v15
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	s_cbranch_vccnz .LBB0_4
; %bb.19:                               ;   in Loop: Header=BB0_3 Depth=1
	s_barrier
	buffer_gl0_inv
	global_load_b32 v0, v15, s[4:5]
	s_add_i32 s22, s22, s1
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, s22, v0
	s_cbranch_vccnz .LBB0_3
.LBB0_20:                               ; %.loopexit89
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13kernelForMSSPPiS_S_S_S_S_PbS_S_
		.amdhsa_group_segment_fixed_size 4
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 28
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z13kernelForMSSPPiS_S_S_S_S_PbS_S_, .Lfunc_end0-_Z13kernelForMSSPPiS_S_S_S_S_PbS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1072
; NumSgprs: 30
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 30
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         76
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         84
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         86
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         88
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         90
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         92
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         94
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         136
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 4
    .kernarg_segment_align: 8
    .kernarg_segment_size: 328
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13kernelForMSSPPiS_S_S_S_S_PbS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     30
    .sgpr_spill_count: 0
    .symbol:         _Z13kernelForMSSPPiS_S_S_S_S_PbS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
