extern "C" __global__
void cu_suppress_non_max(float* mag, float* deltaX, float* deltaY, float* nms,
                         long parser_length, long offset)
{
    const int SUPPRESSED = 0;
    long idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx >= 0 && idx < parser_length * offset)
    {
        float alpha;
        float mag1, mag2;
        // put zero all boundaries of image
        // TOP edge line of the image
        if((idx >= 0) && (idx <offset))
            nms[idx] = SUPPRESSED;
        // BOTTOM edge line of image
        else if((idx >= (parser_length-1)*offset) && (idx < (offset * parser_length)))
            nms[idx] = SUPPRESSED;
        // LEFT & RIGHT edge line
        else if(((idx % offset)==0) || ((idx % offset)==(offset - 1)))
        {
            nms[idx] = SUPPRESSED;
        }
        else // not the boundaries
        {
            // if magnitude = 0, no edge
            if(mag[idx] == 0)
                nms[idx] = SUPPRESSED;
            else{
                if(deltaX[idx] >= 0)
                {
                    if(deltaY[idx] >= 0)  // dx >= 0, dy >= 0
                    {
                        if((deltaX[idx] - deltaY[idx]) >= 0)       // direction 1 (SEE, South-East-East)
                        {
                            alpha = (float)deltaY[idx] / deltaX[idx];
                            mag1 = (1-alpha)*mag[idx+1] + alpha*mag[idx+offset+1];
                            mag2 = (1-alpha)*mag[idx-1] + alpha*mag[idx-offset-1];
                        }
                        else                                // direction 2 (SSE)
                        {
                            alpha = (float)deltaX[idx] / deltaY[idx];
                            mag1 = (1-alpha)*mag[idx+offset] + alpha*mag[idx+offset+1];
                            mag2 = (1-alpha)*mag[idx-offset] + alpha*mag[idx-offset-1];
                        }
                    }
                    else  // dx >= 0, dy < 0
                    {
                        if((deltaX[idx] + deltaY[idx]) >= 0)    // direction 8 (NEE)
                        {
                            alpha = (float)-deltaY[idx] / deltaX[idx];
                            mag1 = (1-alpha)*mag[idx+1] + alpha*mag[idx-offset+1];
                            mag2 = (1-alpha)*mag[idx-1] + alpha*mag[idx+offset-1];
                        }
                        else                                // direction 7 (NNE)
                        {
                            alpha = (float)deltaX[idx] / -deltaY[idx];
                            mag1 = (1-alpha)*mag[idx+offset] + alpha*mag[idx+offset-1];
                            mag2 = (1-alpha)*mag[idx-offset] + alpha*mag[idx-offset+1];
                        }
                    }
                }
                else
                {
                    if(deltaY[idx] >= 0) // dx < 0, dy >= 0
                    {
                        if((deltaX[idx] + deltaY[idx]) >= 0)    // direction 3 (SSW)
                        {
                            alpha = (float)-deltaX[idx] / deltaY[idx];
                            mag1 = (1-alpha)*mag[idx+offset] + alpha*mag[idx+offset-1];
                            mag2 = (1-alpha)*mag[idx-offset] + alpha*mag[idx-offset+1];
                        }
                        else                                // direction 4 (SWW)
                        {
                            alpha = (float)deltaY[idx] / -deltaX[idx];
                            mag1 = (1-alpha)*mag[idx-1] + alpha*mag[idx+offset-1];
                            mag2 = (1-alpha)*mag[idx+1] + alpha*mag[idx-offset+1];
                        }
                    }
                    else // dx < 0, dy < 0
                    {
                            if((-deltaX[idx] + deltaY[idx]) >= 0)   // direction 5 (NWW)
                            {
                                alpha = (float)deltaY[idx] / deltaX[idx];
                                mag1 = (1-alpha)*mag[idx-1] + alpha*mag[idx-offset-1];
                                mag2 = (1-alpha)*mag[idx+1] + alpha*mag[idx+offset+1];
                            }
                            else                                // direction 6 (NNW)
                            {
                                alpha = (float)deltaX[idx] / deltaY[idx];
                                mag1 = (1-alpha)*mag[idx-offset] + alpha*mag[idx-offset-1];
                                mag2 = (1-alpha)*mag[idx+offset] + alpha*mag[idx+offset+1];
                            }
                    }
                }
                // non-maximal suppression
                // compare mag1, mag2 and mag[t]
                // if mag[t] is smaller than one of the neighbours then suppress it
                if((mag[idx] < mag1) || (mag[idx] < mag2))
                        nms[idx] = SUPPRESSED;
                else
                {
                        nms[idx] = mag[idx];
                }
            } // END OF ELSE (mag != 0)
        } // END OF FOR(j)
    } // END OF FOR(i)
}
	.file	"tmpxft_0033ba41_00000000-6_cu_suppress_non_max.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z47__device_stub__Z19cu_suppress_non_maxPfS_S_S_llPfS_S_S_ll
	.type	_Z47__device_stub__Z19cu_suppress_non_maxPfS_S_S_llPfS_S_S_ll, @function
_Z47__device_stub__Z19cu_suppress_non_maxPfS_S_S_llPfS_S_S_ll:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	cu_suppress_non_max(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z47__device_stub__Z19cu_suppress_non_maxPfS_S_S_llPfS_S_S_ll, .-_Z47__device_stub__Z19cu_suppress_non_maxPfS_S_S_llPfS_S_S_ll
	.globl	cu_suppress_non_max
	.type	cu_suppress_non_max, @function
cu_suppress_non_max:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z19cu_suppress_non_maxPfS_S_S_llPfS_S_S_ll
	.cfi_endproc
.LFE2033:
	.size	cu_suppress_non_max, .-cu_suppress_non_max
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"cu_suppress_non_max"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	cu_suppress_non_max(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
extern "C" __global__
void cu_suppress_non_max(float* mag, float* deltaX, float* deltaY, float* nms,
                         long parser_length, long offset)
{
    const int SUPPRESSED = 0;
    long idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx >= 0 && idx < parser_length * offset)
    {
        float alpha;
        float mag1, mag2;
        // put zero all boundaries of image
        // TOP edge line of the image
        if((idx >= 0) && (idx <offset))
            nms[idx] = SUPPRESSED;
        // BOTTOM edge line of image
        else if((idx >= (parser_length-1)*offset) && (idx < (offset * parser_length)))
            nms[idx] = SUPPRESSED;
        // LEFT & RIGHT edge line
        else if(((idx % offset)==0) || ((idx % offset)==(offset - 1)))
        {
            nms[idx] = SUPPRESSED;
        }
        else // not the boundaries
        {
            // if magnitude = 0, no edge
            if(mag[idx] == 0)
                nms[idx] = SUPPRESSED;
            else{
                if(deltaX[idx] >= 0)
                {
                    if(deltaY[idx] >= 0)  // dx >= 0, dy >= 0
                    {
                        if((deltaX[idx] - deltaY[idx]) >= 0)       // direction 1 (SEE, South-East-East)
                        {
                            alpha = (float)deltaY[idx] / deltaX[idx];
                            mag1 = (1-alpha)*mag[idx+1] + alpha*mag[idx+offset+1];
                            mag2 = (1-alpha)*mag[idx-1] + alpha*mag[idx-offset-1];
                        }
                        else                                // direction 2 (SSE)
                        {
                            alpha = (float)deltaX[idx] / deltaY[idx];
                            mag1 = (1-alpha)*mag[idx+offset] + alpha*mag[idx+offset+1];
                            mag2 = (1-alpha)*mag[idx-offset] + alpha*mag[idx-offset-1];
                        }
                    }
                    else  // dx >= 0, dy < 0
                    {
                        if((deltaX[idx] + deltaY[idx]) >= 0)    // direction 8 (NEE)
                        {
                            alpha = (float)-deltaY[idx] / deltaX[idx];
                            mag1 = (1-alpha)*mag[idx+1] + alpha*mag[idx-offset+1];
                            mag2 = (1-alpha)*mag[idx-1] + alpha*mag[idx+offset-1];
                        }
                        else                                // direction 7 (NNE)
                        {
                            alpha = (float)deltaX[idx] / -deltaY[idx];
                            mag1 = (1-alpha)*mag[idx+offset] + alpha*mag[idx+offset-1];
                            mag2 = (1-alpha)*mag[idx-offset] + alpha*mag[idx-offset+1];
                        }
                    }
                }
                else
                {
                    if(deltaY[idx] >= 0) // dx < 0, dy >= 0
                    {
                        if((deltaX[idx] + deltaY[idx]) >= 0)    // direction 3 (SSW)
                        {
                            alpha = (float)-deltaX[idx] / deltaY[idx];
                            mag1 = (1-alpha)*mag[idx+offset] + alpha*mag[idx+offset-1];
                            mag2 = (1-alpha)*mag[idx-offset] + alpha*mag[idx-offset+1];
                        }
                        else                                // direction 4 (SWW)
                        {
                            alpha = (float)deltaY[idx] / -deltaX[idx];
                            mag1 = (1-alpha)*mag[idx-1] + alpha*mag[idx+offset-1];
                            mag2 = (1-alpha)*mag[idx+1] + alpha*mag[idx-offset+1];
                        }
                    }
                    else // dx < 0, dy < 0
                    {
                            if((-deltaX[idx] + deltaY[idx]) >= 0)   // direction 5 (NWW)
                            {
                                alpha = (float)deltaY[idx] / deltaX[idx];
                                mag1 = (1-alpha)*mag[idx-1] + alpha*mag[idx-offset-1];
                                mag2 = (1-alpha)*mag[idx+1] + alpha*mag[idx+offset+1];
                            }
                            else                                // direction 6 (NNW)
                            {
                                alpha = (float)deltaX[idx] / deltaY[idx];
                                mag1 = (1-alpha)*mag[idx-offset] + alpha*mag[idx-offset-1];
                                mag2 = (1-alpha)*mag[idx+offset] + alpha*mag[idx+offset+1];
                            }
                    }
                }
                // non-maximal suppression
                // compare mag1, mag2 and mag[t]
                // if mag[t] is smaller than one of the neighbours then suppress it
                if((mag[idx] < mag1) || (mag[idx] < mag2))
                        nms[idx] = SUPPRESSED;
                else
                {
                        nms[idx] = mag[idx];
                }
            } // END OF ELSE (mag != 0)
        } // END OF FOR(j)
    } // END OF FOR(i)
}
	.text
	.file	"cu_suppress_non_max.hip"
	.globl	__device_stub__cu_suppress_non_max # -- Begin function __device_stub__cu_suppress_non_max
	.type	__device_stub__cu_suppress_non_max,@function
__device_stub__cu_suppress_non_max:     # @__device_stub__cu_suppress_non_max
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cu_suppress_non_max, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__cu_suppress_non_max, .Lfunc_end0-__device_stub__cu_suppress_non_max
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cu_suppress_non_max, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	cu_suppress_non_max,@object     # @cu_suppress_non_max
	.section	.rodata,"a",@progbits
	.globl	cu_suppress_non_max
	.p2align	3, 0x0
cu_suppress_non_max:
	.quad	__device_stub__cu_suppress_non_max
	.size	cu_suppress_non_max, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"cu_suppress_non_max"
	.size	.L__unnamed_1, 20

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__cu_suppress_non_max
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym cu_suppress_non_max
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	cu_suppress_non_max     ; -- Begin function cu_suppress_non_max
	.globl	cu_suppress_non_max
	.p2align	8
	.type	cu_suppress_non_max,@function
cu_suppress_non_max:                    ; @cu_suppress_non_max
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b128 s[16:19], s[0:1], 0x20
	v_mov_b32_e32 v5, 0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_mul_i32 s3, s18, s17
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mul_hi_u32 s2, s18, s16
	v_mov_b32_e32 v2, v5
	s_add_i32 s2, s2, s3
	s_mul_i32 s3, s19, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s3, s2, s3
	s_mul_i32 s2, s18, s16
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_cmpx_gt_i64_e64 s[2:3], v[1:2]
	s_cbranch_execz .LBB0_38
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x0
	s_mov_b32 s1, exec_lo
	v_cmpx_le_i64_e64 s[18:19], v[1:2]
	s_cbranch_execz .LBB0_37
; %bb.2:
	v_mov_b32_e32 v5, 0
	s_sub_u32 s2, s2, s18
	s_subb_u32 s3, s3, s19
	s_mov_b32 s12, exec_lo
	v_cmpx_gt_i64_e64 s[2:3], v[1:2]
	s_cbranch_execz .LBB0_36
; %bb.3:
	s_ashr_i32 s2, s19, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_u32 s14, s18, s2
	s_mov_b32 s3, s2
	s_addc_u32 s15, s19, s2
	s_xor_b64 s[2:3], s[14:15], s[2:3]
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v0, s2
	v_cvt_f32_u32_e32 v3, s3
	s_sub_u32 s0, 0, s2
	s_subb_u32 s13, 0, s3
	v_fmamk_f32 v0, v3, 0x4f800000, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x5f7ffffc, v0
	v_mul_f32_e32 v3, 0x2f800000, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_trunc_f32_e32 v3, v3
	v_fmamk_f32 v0, v3, 0xcf800000, v0
	v_cvt_u32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v4, s0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, s0, v0
	v_mul_lo_u32 v6, s13, v0
	v_add_nc_u32_e32 v4, v5, v4
	v_mul_lo_u32 v5, s0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v4, v6
	v_mul_hi_u32 v6, v0, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v7, v0, v4
	v_mul_hi_u32 v8, v0, v4
	v_mul_hi_u32 v9, v3, v5
	v_mul_lo_u32 v5, v3, v5
	v_mul_hi_u32 v10, v3, v4
	v_mul_lo_u32 v4, v3, v4
	v_add_co_u32 v6, vcc_lo, v6, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v6, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, v7, v9, vcc_lo
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v5, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v4, s0, v0
	v_mul_lo_u32 v6, s13, v0
	v_mul_lo_u32 v5, s0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v4, v5
	v_mul_lo_u32 v5, s0, v0
	v_add_nc_u32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v0, v5
	v_mul_lo_u32 v7, v0, v4
	v_mul_hi_u32 v8, v0, v4
	v_mul_hi_u32 v9, v3, v5
	v_mul_lo_u32 v5, v3, v5
	v_mul_hi_u32 v10, v3, v4
	v_mul_lo_u32 v4, v3, v4
	v_add_co_u32 v6, vcc_lo, v6, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v6, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, v7, v9, vcc_lo
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v5, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, v3, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v10, v1, v0
	v_mad_u64_u32 v[5:6], null, 0, v0, 0
	v_mad_u64_u32 v[3:4], null, v1, v9, 0
	v_mad_u64_u32 v[7:8], null, 0, v9, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v10, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v5
	v_add_co_ci_u32_e32 v0, vcc_lo, v3, v6, vcc_lo
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v6, s3, v0
	v_mad_u64_u32 v[3:4], null, s2, v0, 0
	v_mul_lo_u32 v0, s2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v3, vcc_lo, v1, v3
	v_add3_u32 v0, v4, v0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, 0, v0
	v_subrev_co_ci_u32_e64 v4, s0, s3, v4, vcc_lo
	v_sub_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo
	v_sub_co_u32 v5, vcc_lo, v3, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v6, s0, 0, v4, vcc_lo
	v_cmp_le_u32_e64 s0, s2, v3
	v_subrev_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s3, v0
	v_cndmask_b32_e64 v7, 0, -1, s0
	v_cmp_le_u32_e64 s0, s2, v5
	v_cndmask_b32_e64 v10, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s3, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v8, 0, -1, s0
	v_cmp_le_u32_e64 s0, s3, v6
	v_cndmask_b32_e64 v9, 0, -1, s0
	v_cmp_eq_u32_e64 s0, s3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v8, v9, v8, vcc_lo
	v_sub_co_u32 v9, vcc_lo, v5, s2
	v_subrev_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v8
	v_cndmask_b32_e64 v7, v10, v7, s0
	s_add_u32 s2, s18, -1
	s_addc_u32 s3, s19, -1
	v_dual_cndmask_b32 v4, v6, v4 :: v_dual_cndmask_b32 v5, v5, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, 0, v7
	v_cndmask_b32_e32 v3, v3, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v5, 0 :: v_dual_cndmask_b32 v0, v0, v4
	v_sub_co_u32 v3, vcc_lo, v3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e32 v4, vcc_lo, 0, v0, vcc_lo
	v_cmp_ne_u64_e32 vcc_lo, 0, v[3:4]
	v_cmp_ne_u64_e64 s0, s[2:3], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB0_35
; %bb.4:
	v_lshlrev_b64 v[7:8], 2, v[1:2]
	v_mov_b32_e32 v5, 0
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v8, vcc_lo
	global_load_b32 v0, v[3:4], off
	s_waitcnt vmcnt(0)
	v_cmpx_neq_f32_e32 0, v0
	s_cbranch_execz .LBB0_34
; %bb.5:
	v_add_co_u32 v5, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v8, vcc_lo
	v_add_co_u32 v11, vcc_lo, s8, v7
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v8, vcc_lo
	s_mov_b32 s6, exec_lo
	global_load_b32 v10, v[5:6], off
	global_load_b32 v9, v[11:12], off
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr5_vgpr6
	s_waitcnt vmcnt(0)
	v_cmp_le_f32_e64 s0, 0, v9
	v_cmpx_le_f32_e32 0, v10
	s_xor_b32 s6, exec_lo, s6
	s_cbranch_execz .LBB0_19
; %bb.6:
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr5_vgpr6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s7, s0
	s_xor_b32 s7, exec_lo, s7
	s_cbranch_execz .LBB0_12
; %bb.7:
	v_sub_f32_e32 v5, v10, v9
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_f32_e32 vcc_lo, 0, v5
                                        ; implicit-def: $vgpr5_vgpr6
	s_and_saveexec_b32 s8, vcc_lo
	s_xor_b32 s8, exec_lo, s8
	s_cbranch_execz .LBB0_9
; %bb.8:
	s_lshl_b64 s[14:15], s[18:19], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v5, vcc_lo, v3, s14
	v_add_co_ci_u32_e32 v6, vcc_lo, s15, v4, vcc_lo
	v_div_scale_f32 v13, vcc_lo, v9, v10, v9
	s_not_b64 s[14:15], s[18:19]
	s_clause 0x2
	global_load_b32 v5, v[5:6], off offset:4
	global_load_b32 v6, v[3:4], off offset:-4
	global_load_b32 v3, v[3:4], off offset:4
	v_div_scale_f32 v4, null, v10, v10, v9
	s_lshl_b64 s[14:15], s[14:15], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_u32 s9, s4, s14
	v_rcp_f32_e32 v11, v4
	s_addc_u32 s13, s5, s15
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v4, v11, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, v12, v11
	v_mul_f32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, -v4, v12, v13
	v_fmac_f32_e32 v12, v14, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, -v4, v12, v13
	v_div_fmas_f32 v4, v4, v11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v11, v4, v10, v9
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr10
	v_sub_f32_e32 v4, 1.0, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v12, v11, v5 :: v_dual_mul_f32 v13, v4, v6
	v_add_co_u32 v5, vcc_lo, s9, v7
	v_add_co_ci_u32_e32 v6, vcc_lo, s13, v8, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v12, v4, v3
                                        ; implicit-def: $vgpr3
.LBB0_9:                                ; %Flow
	s_and_not1_saveexec_b32 s8, s8
	s_cbranch_execz .LBB0_11
; %bb.10:
	v_sub_co_u32 v5, s9, v1, s18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_co_ci_u32_e64 v6, null, 0, s19, s9
	s_lshl_b64 s[14:15], s[18:19], 2
	v_div_scale_f32 v8, null, v9, v9, v10
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v3, vcc_lo, v3, s14
	v_add_co_ci_u32_e32 v4, vcc_lo, s15, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v11, v8
	v_add_co_u32 v5, vcc_lo, s4, v5
	global_load_b64 v[3:4], v[3:4], off
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_div_scale_f32 v13, vcc_lo, v10, v9, v10
	global_load_b32 v7, v[5:6], off
	v_fma_f32 v12, -v8, v11, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, v12, v11
	v_mul_f32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, -v8, v12, v13
	v_fmac_f32_e32 v12, v14, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v8, v12, v13
	v_div_fmas_f32 v8, v8, v11, v12
	v_add_co_u32 v5, vcc_lo, v5, -4
	v_add_co_ci_u32_e32 v6, vcc_lo, -1, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v11, v8, v9, v10
	v_sub_f32_e32 v8, 1.0, v11
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v12, v11, v4 :: v_dual_mul_f32 v13, v8, v7
	v_fmac_f32_e32 v12, v8, v3
.LBB0_11:                               ; %Flow251
	s_or_b32 exec_lo, exec_lo, s8
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr3
.LBB0_12:                               ; %Flow254
	s_and_not1_saveexec_b32 s7, s7
	s_cbranch_execz .LBB0_18
; %bb.13:
	v_add_f32_e32 v5, v10, v9
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_f32_e32 vcc_lo, 0, v5
                                        ; implicit-def: $vgpr5_vgpr6
	s_and_saveexec_b32 s8, vcc_lo
	s_xor_b32 s8, exec_lo, s8
	s_cbranch_execz .LBB0_15
; %bb.14:
	v_sub_co_u32 v5, s9, v1, s18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_co_ci_u32_e64 v6, null, 0, s19, s9
	v_div_scale_f32 v8, null, v10, v10, -v9
	s_lshl_b64 s[14:15], s[18:19], 2
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v11, v8
	v_add_co_u32 v5, vcc_lo, s4, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_div_scale_f32 v13, vcc_lo, -v9, v10, -v9
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v8, v11, 1.0
	s_clause 0x2
	global_load_b32 v5, v[5:6], off offset:4
	global_load_b32 v6, v[3:4], off offset:-4
	global_load_b32 v7, v[3:4], off offset:4
	v_fmac_f32_e32 v11, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, v13, v11
	v_fma_f32 v14, -v8, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v14, v11
	v_fma_f32 v8, -v8, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v8, v8, v11, v12
	v_add_co_u32 v3, vcc_lo, v3, -4
	v_add_co_ci_u32_e32 v4, vcc_lo, -1, v4, vcc_lo
	v_div_fixup_f32 v11, v8, v10, -v9
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v8, 1.0, v11
	s_waitcnt vmcnt(1)
	v_dual_mul_f32 v12, v11, v5 :: v_dual_mul_f32 v13, v8, v6
	v_add_co_u32 v5, vcc_lo, v3, s14
	v_add_co_ci_u32_e32 v6, vcc_lo, s15, v4, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v12, v8, v7
                                        ; implicit-def: $vgpr3
.LBB0_15:                               ; %Flow252
	s_and_not1_saveexec_b32 s8, s8
	s_cbranch_execz .LBB0_17
; %bb.16:
	v_sub_co_u32 v5, s9, v1, s18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_co_ci_u32_e64 v6, null, 0, s19, s9
	s_lshl_b64 s[14:15], s[18:19], 2
	v_div_scale_f32 v8, null, -v9, -v9, v10
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v3, vcc_lo, v3, s14
	v_add_co_ci_u32_e32 v4, vcc_lo, s15, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v11, v8
	v_add_co_u32 v5, vcc_lo, s4, v5
	global_load_b64 v[3:4], v[3:4], off offset:-4
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_div_scale_f32 v13, vcc_lo, v10, -v9, v10
	global_load_b32 v7, v[5:6], off
	v_fma_f32 v12, -v8, v11, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, v12, v11
	v_mul_f32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, -v8, v12, v13
	v_fmac_f32_e32 v12, v14, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v8, v12, v13
	v_div_fmas_f32 v8, v8, v11, v12
	v_add_co_u32 v5, vcc_lo, v5, 4
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v11, v8, -v9, v10
	v_sub_f32_e32 v8, 1.0, v11
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v12, v11, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v12, v8, v4
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v13, v8, v7
.LBB0_17:                               ; %Flow253
	s_or_b32 exec_lo, exec_lo, s8
.LBB0_18:                               ; %Flow255
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr7_vgpr8
.LBB0_19:                               ; %Flow264
	s_and_not1_saveexec_b32 s6, s6
	s_cbranch_execz .LBB0_33
; %bb.20:
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr5_vgpr6
	s_and_saveexec_b32 s7, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s7
	s_cbranch_execz .LBB0_26
; %bb.21:
	v_add_f32_e32 v5, v10, v9
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_f32_e32 vcc_lo, 0, v5
                                        ; implicit-def: $vgpr5_vgpr6
	s_and_saveexec_b32 s7, vcc_lo
	s_xor_b32 s7, exec_lo, s7
	s_cbranch_execz .LBB0_23
; %bb.22:
	v_sub_co_u32 v5, s13, v1, s18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_co_ci_u32_e64 v6, null, 0, s19, s13
	s_lshl_b64 s[8:9], s[18:19], 2
	v_div_scale_f32 v8, null, v9, v9, -v10
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v3, vcc_lo, v3, s8
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v11, v8
	v_add_co_u32 v5, vcc_lo, s4, v5
	global_load_b64 v[3:4], v[3:4], off offset:-4
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_div_scale_f32 v13, vcc_lo, -v10, v9, -v10
	global_load_b32 v7, v[5:6], off
	v_fma_f32 v12, -v8, v11, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, v12, v11
	v_mul_f32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, -v8, v12, v13
	v_fmac_f32_e32 v12, v14, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v8, v12, v13
	v_div_fmas_f32 v8, v8, v11, v12
	v_add_co_u32 v5, vcc_lo, v5, 4
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v11, v8, v9, -v10
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr9
	v_sub_f32_e32 v8, 1.0, v11
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v12, v11, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v12, v8, v4
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v13, v8, v7
                                        ; implicit-def: $vgpr3_vgpr4
.LBB0_23:                               ; %Flow257
	s_and_not1_saveexec_b32 s7, s7
	s_cbranch_execz .LBB0_25
; %bb.24:
	s_lshl_b64 s[8:9], s[18:19], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v5, vcc_lo, v3, s8
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
	v_div_scale_f32 v11, vcc_lo, v9, -v10, v9
	s_clause 0x2
	global_load_b32 v5, v[5:6], off offset:-4
	global_load_b32 v6, v[3:4], off offset:4
	global_load_b32 v7, v[3:4], off offset:-4
	v_div_scale_f32 v3, null, -v10, -v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, -v3, v4, 1.0
	v_fmac_f32_e32 v4, v8, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v8, v11, v4
	v_fma_f32 v12, -v3, v8, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, v12, v4
	v_fma_f32 v3, -v3, v8, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v8, v3, v4, v8
	v_sub_co_u32 v3, s8, v1, s18
	v_sub_co_ci_u32_e64 v4, null, 0, s19, s8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v11, v8, -v10, v9
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v8, 1.0, v11
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_waitcnt vmcnt(1)
	v_dual_mul_f32 v12, v11, v5 :: v_dual_mul_f32 v13, v8, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, v3, 4
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v4, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v12, v8, v7
.LBB0_25:                               ; %Flow258
	s_or_b32 exec_lo, exec_lo, s7
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr7_vgpr8
.LBB0_26:                               ; %Flow262
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_32
; %bb.27:
	v_sub_f32_e32 v5, v9, v10
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_f32_e32 vcc_lo, 0, v5
                                        ; implicit-def: $vgpr5_vgpr6
	s_and_saveexec_b32 s7, vcc_lo
	s_xor_b32 s7, exec_lo, s7
	s_cbranch_execz .LBB0_29
; %bb.28:
	s_not_b64 s[8:9], s[18:19]
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[8:9], s[8:9], 2
	s_add_u32 s8, s4, s8
	s_addc_u32 s9, s5, s9
	v_add_co_u32 v5, vcc_lo, s8, v7
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v8, vcc_lo
	v_div_scale_f32 v8, null, v10, v10, v9
	v_div_scale_f32 v13, vcc_lo, v9, v10, v9
	s_clause 0x2
	global_load_b32 v5, v[5:6], off
	global_load_b32 v6, v[3:4], off offset:4
	global_load_b32 v7, v[3:4], off offset:-4
	v_rcp_f32_e32 v11, v8
	s_lshl_b64 s[8:9], s[18:19], 2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v8, v11, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, v12, v11
	v_mul_f32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, -v8, v12, v13
	v_fmac_f32_e32 v12, v14, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v8, v12, v13
	v_div_fmas_f32 v8, v8, v11, v12
	v_add_co_u32 v3, vcc_lo, v3, 4
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v11, v8, v10, v9
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr10
	v_sub_f32_e32 v8, 1.0, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v12, v11, v5 :: v_dual_mul_f32 v13, v8, v6
	v_add_co_u32 v5, vcc_lo, v3, s8
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v12, v8, v7
                                        ; implicit-def: $vgpr3
.LBB0_29:                               ; %Flow260
	s_and_not1_saveexec_b32 s7, s7
	s_cbranch_execz .LBB0_31
; %bb.30:
	v_sub_co_u32 v5, s8, v1, s18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_co_ci_u32_e64 v6, null, 0, s19, s8
	s_lshl_b64 s[8:9], s[18:19], 2
	v_div_scale_f32 v8, null, v9, v9, v10
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v11, v8
	v_add_co_u32 v5, vcc_lo, s4, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_add_co_u32 v3, vcc_lo, v3, s8
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v8, v11, 1.0
	s_clause 0x1
	global_load_b64 v[5:6], v[5:6], off offset:-4
	global_load_b32 v7, v[3:4], off
	v_div_scale_f32 v13, vcc_lo, v10, v9, v10
	v_fmac_f32_e32 v11, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, v13, v11
	v_fma_f32 v14, -v8, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v14, v11
	v_fma_f32 v8, -v8, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v8, v8, v11, v12
	v_div_fixup_f32 v11, v8, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v8, 1.0, v11
	s_waitcnt vmcnt(0)
	v_dual_mul_f32 v12, v11, v5 :: v_dual_mul_f32 v13, v8, v7
	v_add_co_u32 v5, vcc_lo, v3, 4
	s_delay_alu instid0(VALU_DEP_2)
	v_fmac_f32_e32 v12, v8, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v4, vcc_lo
.LBB0_31:                               ; %Flow261
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_32:                               ; %Flow263
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_33:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b32 v3, v[5:6], off
	s_waitcnt vmcnt(0)
	v_dual_max_f32 v4, v12, v12 :: v_dual_fmac_f32 v13, v11, v3
	v_max_f32_e32 v3, v4, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ngt_f32_e32 vcc_lo, v3, v0
	v_cndmask_b32_e32 v5, 0, v0, vcc_lo
.LBB0_34:                               ; %Flow265
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_35:                               ; %Flow266
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_36:                               ; %Flow267
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s12
.LBB0_37:                               ; %.sink.split
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s10, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	global_store_b32 v[0:1], v5, off
.LBB0_38:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cu_suppress_non_max
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	cu_suppress_non_max, .Lfunc_end0-cu_suppress_non_max
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3116
; NumSgprs: 22
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cu_suppress_non_max
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cu_suppress_non_max.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
