#include <stdio.h>

// A macro for checking the error codes of cuda runtime calls
#define CUDA_ERROR_CHECK(expr) \
  {                            \
    cudaError_t err = expr;    \
    if (err != cudaSuccess)    \
    {                          \
      printf("CUDA call failed!\n%s\n", cudaGetErrorString(err)); \
      exit(1);                 \
    }                          \
  }


__global__
void swapChannel_kernel(uchar3 * device_inputImage, uchar3 * device_outputImage, int rows, int cols)
{
  //----------------------------------------------------------------
  // TODO: Implement this Kernel
  //----------------------------------------------------------------

}

__global__
void blurImage_kernel(uchar3 * device_inputImage, uchar3 * device_outputImage, int rows, int cols)
{
  //----------------------------------------------------------------
  // TODO: Implement this Kernel
  //----------------------------------------------------------------
}

__global__
void inplaceFlip_kernel(uchar3 * device_outputImage, int rows, int cols)
{
  //----------------------------------------------------------------
  // TODO: Implement this Kernel
  //----------------------------------------------------------------

}

__global__
void creative_kernel(uchar3 * device_inputImage, uchar3 * device_outputImage, int rows, int cols)
{
  //----------------------------------------------------------------
  // TODO: Implement this Kernel
  //----------------------------------------------------------------

}


__host__
float filterImage(uchar3 *host_inputImage, uchar3 *host_outputImage, int rows, int cols, int filterNumber){

  int numPixels = rows * cols;

  //allocate memory on device (GPU)
  uchar3 *device_inputImage;
  uchar3 *device_outputImage;

  CUDA_ERROR_CHECK(cudaMalloc(&device_inputImage, sizeof(uchar3) * numPixels));
  CUDA_ERROR_CHECK(cudaMalloc(&device_outputImage, sizeof(uchar3) * numPixels));
  CUDA_ERROR_CHECK(cudaMemset(device_outputImage, 0,  sizeof(uchar3) * numPixels)); //make sure no memory is left laying around

  //copy input image to the device (GPU)
  CUDA_ERROR_CHECK(cudaMemcpy(device_inputImage, host_inputImage, sizeof(uchar3) * numPixels, cudaMemcpyHostToDevice));

  //start timing to measure length of kernel call
  cudaEvent_t start, stop;
  cudaEventCreate(&start);
  cudaEventCreate(&stop);
  cudaEventRecord(start);

  //----------------------------------------------------------------
  // TODO: Fill in the parameters for the kernel calls
  //----------------------------------------------------------------
  // Each of the parameters are as follows:
  //    1. Number of thread blocks, can be either int or dim3 (see CUDA manual)
  //    2. Number of threads per thread block, can be either int or dim3 (see CUDA manual)

  // Also note that you pass the pointers to the device memory to the kernel call

  int gridSize = 1;
  int blockSize = 1;

  switch(filterNumber){
    case 1:
      swapChannel_kernel<<<gridSize,blockSize>>>(device_inputImage, device_outputImage, rows, cols);
      break;
    case 2:
      blurImage_kernel<<<gridSize,blockSize>>>(device_inputImage, device_outputImage, rows, cols);
      break;
    case 3:
      inplaceFlip_kernel<<<gridSize,blockSize>>>(device_inputImage, rows, cols);
      break;
    case 4:
      creative_kernel<<<gridSize,blockSize>>>(device_inputImage, device_outputImage, rows, cols);
      break;
    default:
      break;
  }

  //----------------------------------------------------------------
  // END KERNEL CALLS - Do not modify code beyond this point!
  //----------------------------------------------------------------

  //stop timing
  cudaEventRecord(stop);

  cudaEventSynchronize(stop);

  float timeElapsedInMs = 0;
  cudaEventElapsedTime(&timeElapsedInMs, start, stop);

  //synchronize
  cudaDeviceSynchronize(); CUDA_ERROR_CHECK(cudaGetLastError());

  //copy device output image back to host output image
  //special case for filter swap - since it is in place, we actually copy the input image back to the host output
  if (filterNumber==3){
    CUDA_ERROR_CHECK(cudaMemcpy(host_outputImage, device_inputImage, sizeof(uchar3) * numPixels, cudaMemcpyDeviceToHost));
  }else{
    CUDA_ERROR_CHECK(cudaMemcpy(host_outputImage, device_outputImage, sizeof(uchar3) * numPixels, cudaMemcpyDeviceToHost));
  }


  //free Memory
  CUDA_ERROR_CHECK(cudaFree(device_inputImage));
  CUDA_ERROR_CHECK(cudaFree(device_outputImage));

  return timeElapsedInMs;
}

	.file	"tmpxft_00214cbe_00000000-6_imageFilter.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z49__device_stub__Z18swapChannel_kernelP6uchar3S0_iiP6uchar3S0_ii
	.type	_Z49__device_stub__Z18swapChannel_kernelP6uchar3S0_iiP6uchar3S0_ii, @function
_Z49__device_stub__Z18swapChannel_kernelP6uchar3S0_iiP6uchar3S0_ii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z18swapChannel_kernelP6uchar3S0_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z49__device_stub__Z18swapChannel_kernelP6uchar3S0_iiP6uchar3S0_ii, .-_Z49__device_stub__Z18swapChannel_kernelP6uchar3S0_iiP6uchar3S0_ii
	.globl	_Z18swapChannel_kernelP6uchar3S0_ii
	.type	_Z18swapChannel_kernelP6uchar3S0_ii, @function
_Z18swapChannel_kernelP6uchar3S0_ii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z18swapChannel_kernelP6uchar3S0_iiP6uchar3S0_ii
	.cfi_endproc
.LFE2053:
	.size	_Z18swapChannel_kernelP6uchar3S0_ii, .-_Z18swapChannel_kernelP6uchar3S0_ii
	.globl	_Z47__device_stub__Z16blurImage_kernelP6uchar3S0_iiP6uchar3S0_ii
	.type	_Z47__device_stub__Z16blurImage_kernelP6uchar3S0_iiP6uchar3S0_ii, @function
_Z47__device_stub__Z16blurImage_kernelP6uchar3S0_iiP6uchar3S0_ii:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z16blurImage_kernelP6uchar3S0_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z47__device_stub__Z16blurImage_kernelP6uchar3S0_iiP6uchar3S0_ii, .-_Z47__device_stub__Z16blurImage_kernelP6uchar3S0_iiP6uchar3S0_ii
	.globl	_Z16blurImage_kernelP6uchar3S0_ii
	.type	_Z16blurImage_kernelP6uchar3S0_ii, @function
_Z16blurImage_kernelP6uchar3S0_ii:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z16blurImage_kernelP6uchar3S0_iiP6uchar3S0_ii
	.cfi_endproc
.LFE2055:
	.size	_Z16blurImage_kernelP6uchar3S0_ii, .-_Z16blurImage_kernelP6uchar3S0_ii
	.globl	_Z46__device_stub__Z18inplaceFlip_kernelP6uchar3iiP6uchar3ii
	.type	_Z46__device_stub__Z18inplaceFlip_kernelP6uchar3iiP6uchar3ii, @function
_Z46__device_stub__Z18inplaceFlip_kernelP6uchar3iiP6uchar3ii:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z18inplaceFlip_kernelP6uchar3ii(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L13:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z46__device_stub__Z18inplaceFlip_kernelP6uchar3iiP6uchar3ii, .-_Z46__device_stub__Z18inplaceFlip_kernelP6uchar3iiP6uchar3ii
	.globl	_Z18inplaceFlip_kernelP6uchar3ii
	.type	_Z18inplaceFlip_kernelP6uchar3ii, @function
_Z18inplaceFlip_kernelP6uchar3ii:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z18inplaceFlip_kernelP6uchar3iiP6uchar3ii
	.cfi_endproc
.LFE2057:
	.size	_Z18inplaceFlip_kernelP6uchar3ii, .-_Z18inplaceFlip_kernelP6uchar3ii
	.globl	_Z46__device_stub__Z15creative_kernelP6uchar3S0_iiP6uchar3S0_ii
	.type	_Z46__device_stub__Z15creative_kernelP6uchar3S0_iiP6uchar3S0_ii, @function
_Z46__device_stub__Z15creative_kernelP6uchar3S0_iiP6uchar3S0_ii:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z15creative_kernelP6uchar3S0_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L18:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z46__device_stub__Z15creative_kernelP6uchar3S0_iiP6uchar3S0_ii, .-_Z46__device_stub__Z15creative_kernelP6uchar3S0_iiP6uchar3S0_ii
	.globl	_Z15creative_kernelP6uchar3S0_ii
	.type	_Z15creative_kernelP6uchar3S0_ii, @function
_Z15creative_kernelP6uchar3S0_ii:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z15creative_kernelP6uchar3S0_iiP6uchar3S0_ii
	.cfi_endproc
.LFE2059:
	.size	_Z15creative_kernelP6uchar3S0_ii, .-_Z15creative_kernelP6uchar3S0_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA call failed!\n%s\n"
	.text
	.globl	_Z11filterImageP6uchar3S0_iii
	.type	_Z11filterImageP6uchar3S0_iii, @function
_Z11filterImageP6uchar3S0_iii:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%ecx, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%edx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%r8d, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edx, %ebx
	imull	%ecx, %ebx
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	movslq	%ebx, %rbx
	movq	%rsp, %rdi
	leaq	(%rbx,%rbx,2), %rbx
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	jne	.L53
	leaq	8(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	jne	.L53
	movq	8(%rsp), %rdi
	movq	%rbx, %rdx
	xorl	%esi, %esi
	call	cudaMemset@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	jne	.L53
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rdx
	movq	%r15, %rsi
	call	cudaMemcpy@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	jne	.L53
	leaq	16(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	24(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	cmpl	$3, %ebp
	je	.L28
	jg	.L29
	cmpl	$1, %ebp
	je	.L30
	cmpl	$2, %ebp
	je	.L31
	jmp	.L32
.L29:
	cmpl	$4, %ebp
	je	.L33
	jmp	.L32
.L30:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movl	$1, 52(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 44(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	%r13d, %ecx
	movl	%r12d, %edx
	call	_Z49__device_stub__Z18swapChannel_kernelP6uchar3S0_iiP6uchar3S0_ii
	jmp	.L32
.L31:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movl	$1, 52(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 44(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	%r13d, %ecx
	movl	%r12d, %edx
	call	_Z47__device_stub__Z16blurImage_kernelP6uchar3S0_iiP6uchar3S0_ii
	jmp	.L32
.L28:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movl	$1, 52(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 44(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	movq	(%rsp), %rdi
	movl	%r13d, %edx
	movl	%r12d, %esi
	call	_Z46__device_stub__Z18inplaceFlip_kernelP6uchar3iiP6uchar3ii
	jmp	.L32
.L33:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movl	$1, 52(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 44(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	%r13d, %ecx
	movl	%r12d, %edx
	call	_Z46__device_stub__Z15creative_kernelP6uchar3S0_iiP6uchar3S0_ii
.L32:
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	24(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	leaq	44(%rsp), %rdi
	movl	$0x00000000, 44(%rsp)
	call	cudaEventElapsedTime@PLT
	call	cudaDeviceSynchronize@PLT
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	jne	.L53
	movq	(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdx
	cmpl	$3, %ebp
	je	.L55
	movq	8(%rsp), %rsi
.L55:
	movq	%r14, %rdi
	call	cudaMemcpy@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	jne	.L53
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	jne	.L53
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L42
.L53:
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L42:
	movss	44(%rsp), %xmm0
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L43
	call	__stack_chk_fail@PLT
.L43:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z11filterImageP6uchar3S0_iii, .-_Z11filterImageP6uchar3S0_iii
	.section	.rodata.str1.1
.LC2:
	.string	"_Z15creative_kernelP6uchar3S0_ii"
.LC3:
	.string	"_Z18inplaceFlip_kernelP6uchar3ii"
.LC4:
	.string	"_Z16blurImage_kernelP6uchar3S0_ii"
.LC5:
	.string	"_Z18swapChannel_kernelP6uchar3S0_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z15creative_kernelP6uchar3S0_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z18inplaceFlip_kernelP6uchar3ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z16blurImage_kernelP6uchar3S0_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z18swapChannel_kernelP6uchar3S0_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2061:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>

// A macro for checking the error codes of cuda runtime calls
#define CUDA_ERROR_CHECK(expr) \
  {                            \
    hipError_t err = expr;    \
    if (err != hipSuccess)    \
    {                          \
      printf("CUDA call failed!\n%s\n", hipGetErrorString(err)); \
      exit(1);                 \
    }                          \
  }


__global__
void swapChannel_kernel(uchar3 * device_inputImage, uchar3 * device_outputImage, int rows, int cols)
{
  //----------------------------------------------------------------
  // TODO: Implement this Kernel
  //----------------------------------------------------------------

}

__global__
void blurImage_kernel(uchar3 * device_inputImage, uchar3 * device_outputImage, int rows, int cols)
{
  //----------------------------------------------------------------
  // TODO: Implement this Kernel
  //----------------------------------------------------------------
}

__global__
void inplaceFlip_kernel(uchar3 * device_outputImage, int rows, int cols)
{
  //----------------------------------------------------------------
  // TODO: Implement this Kernel
  //----------------------------------------------------------------

}

__global__
void creative_kernel(uchar3 * device_inputImage, uchar3 * device_outputImage, int rows, int cols)
{
  //----------------------------------------------------------------
  // TODO: Implement this Kernel
  //----------------------------------------------------------------

}


__host__
float filterImage(uchar3 *host_inputImage, uchar3 *host_outputImage, int rows, int cols, int filterNumber){

  int numPixels = rows * cols;

  //allocate memory on device (GPU)
  uchar3 *device_inputImage;
  uchar3 *device_outputImage;

  CUDA_ERROR_CHECK(hipMalloc(&device_inputImage, sizeof(uchar3) * numPixels));
  CUDA_ERROR_CHECK(hipMalloc(&device_outputImage, sizeof(uchar3) * numPixels));
  CUDA_ERROR_CHECK(hipMemset(device_outputImage, 0,  sizeof(uchar3) * numPixels)); //make sure no memory is left laying around

  //copy input image to the device (GPU)
  CUDA_ERROR_CHECK(hipMemcpy(device_inputImage, host_inputImage, sizeof(uchar3) * numPixels, hipMemcpyHostToDevice));

  //start timing to measure length of kernel call
  hipEvent_t start, stop;
  hipEventCreate(&start);
  hipEventCreate(&stop);
  hipEventRecord(start);

  //----------------------------------------------------------------
  // TODO: Fill in the parameters for the kernel calls
  //----------------------------------------------------------------
  // Each of the parameters are as follows:
  //    1. Number of thread blocks, can be either int or dim3 (see CUDA manual)
  //    2. Number of threads per thread block, can be either int or dim3 (see CUDA manual)

  // Also note that you pass the pointers to the device memory to the kernel call

  int gridSize = 1;
  int blockSize = 1;

  switch(filterNumber){
    case 1:
      swapChannel_kernel<<<gridSize,blockSize>>>(device_inputImage, device_outputImage, rows, cols);
      break;
    case 2:
      blurImage_kernel<<<gridSize,blockSize>>>(device_inputImage, device_outputImage, rows, cols);
      break;
    case 3:
      inplaceFlip_kernel<<<gridSize,blockSize>>>(device_inputImage, rows, cols);
      break;
    case 4:
      creative_kernel<<<gridSize,blockSize>>>(device_inputImage, device_outputImage, rows, cols);
      break;
    default:
      break;
  }

  //----------------------------------------------------------------
  // END KERNEL CALLS - Do not modify code beyond this point!
  //----------------------------------------------------------------

  //stop timing
  hipEventRecord(stop);

  hipEventSynchronize(stop);

  float timeElapsedInMs = 0;
  hipEventElapsedTime(&timeElapsedInMs, start, stop);

  //synchronize
  hipDeviceSynchronize(); CUDA_ERROR_CHECK(hipGetLastError());

  //copy device output image back to host output image
  //special case for filter swap - since it is in place, we actually copy the input image back to the host output
  if (filterNumber==3){
    CUDA_ERROR_CHECK(hipMemcpy(host_outputImage, device_inputImage, sizeof(uchar3) * numPixels, hipMemcpyDeviceToHost));
  }else{
    CUDA_ERROR_CHECK(hipMemcpy(host_outputImage, device_outputImage, sizeof(uchar3) * numPixels, hipMemcpyDeviceToHost));
  }


  //free Memory
  CUDA_ERROR_CHECK(hipFree(device_inputImage));
  CUDA_ERROR_CHECK(hipFree(device_outputImage));

  return timeElapsedInMs;
}

	.text
	.file	"imageFilter.hip"
	.globl	_Z33__device_stub__swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii # -- Begin function _Z33__device_stub__swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii
	.type	_Z33__device_stub__swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii,@function
_Z33__device_stub__swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii: # @_Z33__device_stub__swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii, .Lfunc_end0-_Z33__device_stub__swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z31__device_stub__blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii # -- Begin function _Z31__device_stub__blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii
	.type	_Z31__device_stub__blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii,@function
_Z31__device_stub__blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii: # @_Z31__device_stub__blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z31__device_stub__blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii, .Lfunc_end1-_Z31__device_stub__blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii # -- Begin function _Z33__device_stub__inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii
	.type	_Z33__device_stub__inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii,@function
_Z33__device_stub__inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii: # @_Z33__device_stub__inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z33__device_stub__inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii, .Lfunc_end2-_Z33__device_stub__inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__creative_kernelP15HIP_vector_typeIhLj3EES1_ii # -- Begin function _Z30__device_stub__creative_kernelP15HIP_vector_typeIhLj3EES1_ii
	.type	_Z30__device_stub__creative_kernelP15HIP_vector_typeIhLj3EES1_ii,@function
_Z30__device_stub__creative_kernelP15HIP_vector_typeIhLj3EES1_ii: # @_Z30__device_stub__creative_kernelP15HIP_vector_typeIhLj3EES1_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15creative_kernelP15HIP_vector_typeIhLj3EES1_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z30__device_stub__creative_kernelP15HIP_vector_typeIhLj3EES1_ii, .Lfunc_end3-_Z30__device_stub__creative_kernelP15HIP_vector_typeIhLj3EES1_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z11filterImageP15HIP_vector_typeIhLj3EES1_iii # -- Begin function _Z11filterImageP15HIP_vector_typeIhLj3EES1_iii
	.type	_Z11filterImageP15HIP_vector_typeIhLj3EES1_iii,@function
_Z11filterImageP15HIP_vector_typeIhLj3EES1_iii: # @_Z11filterImageP15HIP_vector_typeIhLj3EES1_iii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r8d, %r15d
	movl	%ecx, %ebp
	movl	%edx, %r12d
	movq	%rsi, %rbx
	movq	%rdi, %r13
	movl	%ecx, %eax
	imull	%edx, %eax
	cltq
	leaq	(%rax,%rax,2), %r14
	movq	%rsp, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB4_18
# %bb.1:
	leaq	8(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB4_18
# %bb.2:
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	movq	%r14, %rdx
	callq	hipMemset
	testl	%eax, %eax
	jne	.LBB4_18
# %bb.3:
	movq	(%rsp), %rdi
	movq	%r13, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB4_18
# %bb.4:
	leaq	32(%rsp), %r13
	movq	%r13, %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	movq	(%r13), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	leal	-1(%r15), %eax
	cmpl	$3, %eax
	ja	.LBB4_14
# %bb.5:
	jmpq	*.LJTI4_0(,%rax,8)
.LBB4_6:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_14
# %bb.7:
	movq	(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	%r12d, %edx
	movl	%ebp, %ecx
	callq	_Z33__device_stub__swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii
	jmp	.LBB4_14
.LBB4_10:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_14
# %bb.11:
	movq	(%rsp), %rdi
	movl	%r12d, %esi
	movl	%ebp, %edx
	callq	_Z33__device_stub__inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii
	jmp	.LBB4_14
.LBB4_12:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_14
# %bb.13:
	movq	(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	%r12d, %edx
	movl	%ebp, %ecx
	callq	_Z30__device_stub__creative_kernelP15HIP_vector_typeIhLj3EES1_ii
	jmp	.LBB4_14
.LBB4_8:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_14
# %bb.9:
	movq	(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	%r12d, %edx
	movl	%ebp, %ecx
	callq	_Z31__device_stub__blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii
.LBB4_14:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	leaq	28(%rsp), %rdi
	movl	$0, (%rdi)
	movq	32(%rsp), %rsi
	movq	16(%rsp), %rdx
	callq	hipEventElapsedTime
	callq	hipDeviceSynchronize
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB4_18
# %bb.15:
	cmpl	$3, %r15d
	jne	.LBB4_19
# %bb.16:
	movq	(%rsp), %rsi
	jmp	.LBB4_17
.LBB4_19:
	movq	8(%rsp), %rsi
.LBB4_17:
	movq	%rbx, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB4_18
# %bb.20:
	movq	(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB4_18
# %bb.21:
	movq	8(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB4_18
# %bb.22:
	movss	28(%rsp), %xmm0                 # xmm0 = mem[0],zero,zero,zero
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB4_18:
	.cfi_def_cfa_offset 96
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end4:
	.size	_Z11filterImageP15HIP_vector_typeIhLj3EES1_iii, .Lfunc_end4-_Z11filterImageP15HIP_vector_typeIhLj3EES1_iii
	.cfi_endproc
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
.LJTI4_0:
	.quad	.LBB4_6
	.quad	.LBB4_8
	.quad	.LBB4_10
	.quad	.LBB4_12
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15creative_kernelP15HIP_vector_typeIhLj3EES1_ii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii,@object # @_Z18swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii
	.section	.rodata,"a",@progbits
	.globl	_Z18swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii
	.p2align	3, 0x0
_Z18swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii:
	.quad	_Z33__device_stub__swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii
	.size	_Z18swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii, 8

	.type	_Z16blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii,@object # @_Z16blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii
	.globl	_Z16blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii
	.p2align	3, 0x0
_Z16blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii:
	.quad	_Z31__device_stub__blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii
	.size	_Z16blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii, 8

	.type	_Z18inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii,@object # @_Z18inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii
	.globl	_Z18inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii
	.p2align	3, 0x0
_Z18inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii:
	.quad	_Z33__device_stub__inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii
	.size	_Z18inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii, 8

	.type	_Z15creative_kernelP15HIP_vector_typeIhLj3EES1_ii,@object # @_Z15creative_kernelP15HIP_vector_typeIhLj3EES1_ii
	.globl	_Z15creative_kernelP15HIP_vector_typeIhLj3EES1_ii
	.p2align	3, 0x0
_Z15creative_kernelP15HIP_vector_typeIhLj3EES1_ii:
	.quad	_Z30__device_stub__creative_kernelP15HIP_vector_typeIhLj3EES1_ii
	.size	_Z15creative_kernelP15HIP_vector_typeIhLj3EES1_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA call failed!\n%s\n"
	.size	.L.str, 22

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z18swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii"
	.size	.L__unnamed_1, 53

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z16blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii"
	.size	.L__unnamed_2, 51

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z18inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii"
	.size	.L__unnamed_3, 50

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z15creative_kernelP15HIP_vector_typeIhLj3EES1_ii"
	.size	.L__unnamed_4, 50

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii
	.addrsig_sym _Z31__device_stub__blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii
	.addrsig_sym _Z33__device_stub__inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii
	.addrsig_sym _Z30__device_stub__creative_kernelP15HIP_vector_typeIhLj3EES1_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii
	.addrsig_sym _Z16blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii
	.addrsig_sym _Z18inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii
	.addrsig_sym _Z15creative_kernelP15HIP_vector_typeIhLj3EES1_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii ; -- Begin function _Z18swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii
	.globl	_Z18swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii
	.p2align	8
	.type	_Z18swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii,@function
_Z18swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii: ; @_Z18swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii
; %bb.0:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 1
		.amdhsa_next_free_sgpr 1
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii, .Lfunc_end0-_Z18swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4
; NumSgprs: 0
; NumVgprs: 0
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 1
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z16blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii ; -- Begin function _Z16blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii
	.globl	_Z16blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii
	.p2align	8
	.type	_Z16blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii,@function
_Z16blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii: ; @_Z16blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii
; %bb.0:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 1
		.amdhsa_next_free_sgpr 1
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z16blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii, .Lfunc_end1-_Z16blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4
; NumSgprs: 0
; NumVgprs: 0
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 1
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z18inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii ; -- Begin function _Z18inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii
	.globl	_Z18inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii
	.p2align	8
	.type	_Z18inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii,@function
_Z18inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii: ; @_Z18inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii
; %bb.0:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 1
		.amdhsa_next_free_sgpr 1
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z18inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii, .Lfunc_end2-_Z18inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4
; NumSgprs: 0
; NumVgprs: 0
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 1
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z15creative_kernelP15HIP_vector_typeIhLj3EES1_ii ; -- Begin function _Z15creative_kernelP15HIP_vector_typeIhLj3EES1_ii
	.globl	_Z15creative_kernelP15HIP_vector_typeIhLj3EES1_ii
	.p2align	8
	.type	_Z15creative_kernelP15HIP_vector_typeIhLj3EES1_ii,@function
_Z15creative_kernelP15HIP_vector_typeIhLj3EES1_ii: ; @_Z15creative_kernelP15HIP_vector_typeIhLj3EES1_ii
; %bb.0:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15creative_kernelP15HIP_vector_typeIhLj3EES1_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 1
		.amdhsa_next_free_sgpr 1
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z15creative_kernelP15HIP_vector_typeIhLj3EES1_ii, .Lfunc_end3-_Z15creative_kernelP15HIP_vector_typeIhLj3EES1_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4
; NumSgprs: 0
; NumVgprs: 0
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 1
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     0
    .sgpr_spill_count: 0
    .symbol:         _Z18swapChannel_kernelP15HIP_vector_typeIhLj3EES1_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     0
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     0
    .sgpr_spill_count: 0
    .symbol:         _Z16blurImage_kernelP15HIP_vector_typeIhLj3EES1_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     0
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii
    .private_segment_fixed_size: 0
    .sgpr_count:     0
    .sgpr_spill_count: 0
    .symbol:         _Z18inplaceFlip_kernelP15HIP_vector_typeIhLj3EEii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     0
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15creative_kernelP15HIP_vector_typeIhLj3EES1_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     0
    .sgpr_spill_count: 0
    .symbol:         _Z15creative_kernelP15HIP_vector_typeIhLj3EES1_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     0
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
