#include <iostream>
#include <fstream>
#include <math.h>
#include <cstdio>
#include <ctime>
#include <assert.h>     /* assert */
using namespace std;
//0 3 6 
//1 4 7
//2 5 8
// row idx: i
// col idx: j
__global__
void _mask_conv(float diag_coef_1, float diag_coef_2, float side_coef_1, float side_coef_2, int N, float *input_tensor, float *mask_tensor, float *output_tensor)
{

	float diag_coef_diff = diag_coef_1 - diag_coef_2;
	float side_coef_diff = side_coef_1 - side_coef_2;

	int index_x = blockIdx.x * blockDim.x + threadIdx.x;
	int index_y = blockIdx.y * blockDim.y + threadIdx.y;

	int stride_x = blockDim.x * gridDim.x;
	int stride_y = blockDim.y * gridDim.y;
	for (int i = index_x+1; i < N-1; i += stride_x)
	{
		for (int j = index_y+1; j < N-1; j += stride_y)
		{
/*
			// this one is 10% faster, but has some hidden bug...
			int output_index = N*(i-1) + (j-1);

			int input_index_0 = N*(i-1) + j-1;
			int input_index_1 = N*(i) + j-1;
			int input_index_2 = N*(i+1) + j-1;
			int input_index_3 = N*(i-1) + j;
			int input_index_5 = N*(i+1) + j;
			int input_index_6 = N*(i-1) + j+1;
			int input_index_7 = N*(i) + j+1;
			int input_index_8 = N*(i+1) + j+1;

			int mask_index_0 = (N-1)*(i-1) + j-1;
			int mask_index_1 = (N-1)*(i) + j-1;
			int mask_index_3 = (N-1)*(i-1) + j;
			int mask_index_4 = (N-1)*(i) + j;
			
			float mask_conv_diag = input_tensor[input_index_0] * mask_tensor[mask_index_0] 
							     + input_tensor[input_index_6] * mask_tensor[mask_index_3]
								 + input_tensor[input_index_2] * mask_tensor[mask_index_1] 
						  	 	 + input_tensor[input_index_8] * mask_tensor[mask_index_4];
			float mask_conv_side = input_tensor[input_index_3] * (mask_tensor[mask_index_0]+mask_tensor[mask_index_3])
  							 	 + input_tensor[input_index_1] * (mask_tensor[mask_index_0]+mask_tensor[mask_index_1])
  							 	 + input_tensor[input_index_7] * (mask_tensor[mask_index_3]+mask_tensor[mask_index_4])
  							 	 + input_tensor[input_index_5] * (mask_tensor[mask_index_1]+mask_tensor[mask_index_4]);
			float sum_resp_diag = input_tensor[input_index_0] + input_tensor[input_index_6] + input_tensor[input_index_2] + input_tensor[input_index_8];
			float sum_resp_side = input_tensor[input_index_3] + input_tensor[input_index_1] + input_tensor[input_index_7] + input_tensor[input_index_5];

			output_tensor[output_index] = mask_conv_diag *diag_coef_diff
										+ mask_conv_side *side_coef_diff/2
										+ sum_resp_diag * diag_coef_2
										+ sum_resp_side * diag_coef_2;
*/	
            output_tensor[(i-1) *N+ j-1]  = input_tensor[(i-1)*N+ j-1] * mask_tensor[(i-1) *N+ j-1] *diag_coef_1 
                                 + input_tensor[(i-1) *N+ j+1] * mask_tensor[(i-1) *N+ j] *diag_coef_1 
                                 + input_tensor[(i+1) *N+ j-1] * mask_tensor[(i) *N+ j-1] *diag_coef_1 
                                 + input_tensor[(i+1) *N+ j+1] * mask_tensor[(i) *N+ j] *diag_coef_1
                                 
                                 + input_tensor[(i-1) *N+ j] * (mask_tensor[(i-1) *N+ j-1] + mask_tensor[(i-1) *N+ j]) / 2. *side_coef_1 
                                 + input_tensor[(i) *N+ j-1] * (mask_tensor[(i-1) *N+ j-1] + mask_tensor[(i) *N+ j-1]) / 2. *side_coef_1
                                 + input_tensor[(i) *N+ j + 1] * (mask_tensor[(i-1) *N+ j] + mask_tensor[(i) *N+ j]) / 2. *side_coef_1
                                 + input_tensor[(i+1), j] * (mask_tensor[(i) *N+ j-1] + mask_tensor[(i) *N+ j]) / 2. *side_coef_1
             
                                 + input_tensor[(i-1) *N+ j-1] * (1-mask_tensor[(i-1) *N+ j-1]) *diag_coef_2 
                                 + input_tensor[(i-1) *N+ j+1] * (1-mask_tensor[(i-1) *N+ j])*diag_coef_2 
                                 + input_tensor[(i+1) *N+ j-1] * (1-mask_tensor[(i) *N+ j-1]) *diag_coef_2 
                                 + input_tensor[(i+1) *N+ j+1] * (1-mask_tensor[(i) *N+ j]) *diag_coef_2
            
                                 + input_tensor[(i-1) *N+ j] * (2-mask_tensor[(i-1) *N+ j-1] - mask_tensor[(i-1) *N+ j]) / 2. *side_coef_2 
                                 + input_tensor[(i) *N+ j-1] * (2-mask_tensor[(i-1) *N+ j-1] - mask_tensor[(i) *N+ j-1]) / 2. *side_coef_2
                                 + input_tensor[(i) *N+ j + 1] * (2-mask_tensor[(i-1) *N+ j] - mask_tensor[(i) *N+ j]) / 2. *side_coef_2
                                 + input_tensor[(i+1) *N+ j] * (2-mask_tensor[(i) *N+ j-1] - mask_tensor[(i) *N+ j]) / 2. *side_coef_2;
						
		}
	}
}
             
void mask_conv_gpu(int mat_row_num,  float *input_tensor, float *weights_tensor, float *output_tensor) {
	float diag_coef_1 = 16;
	float side_coef_1 = 16;
	float diag_coef_2 = 1;
	float side_coef_2 = 1;
	dim3 blocksize( 32, 32 );
	int bx = (mat_row_num+blocksize.x-1)/blocksize.x ;
	int by = (mat_row_num+blocksize.y-1)/blocksize.y ;
	dim3 gridsize(bx, by);
    _mask_conv<<<gridsize,blocksize>>>(diag_coef_1, diag_coef_2, side_coef_1, side_coef_2, mat_row_num, input_tensor, weights_tensor, output_tensor);
    cudaDeviceSynchronize();
}


void mask_conv_cpu(int N, float *input_tensor, float *weights_tensor, float * output_tensor)
{
	float diag_coef_1 = 16;
	float side_coef_1 = 16;
	float diag_coef_2 = 1;
	float side_coef_2 = 1;
	float diag_coef_diff = diag_coef_1 - diag_coef_2;
	float side_coef_diff = side_coef_1 - side_coef_2;

    for (int i = 1; i < N-1; i++) {
        for (int j = 1; j < N-1; j++) {

            output_tensor[(i-1) *N+ j-1]  = input_tensor[(i-1)*N+ j-1] * weights_tensor[(i-1) *N+ j-1] *diag_coef_1 
                                 + input_tensor[(i-1) *N+ j+1] * weights_tensor[(i-1) *N+ j] *diag_coef_1 
                                 + input_tensor[(i+1) *N+ j-1] * weights_tensor[(i) *N+ j-1] *diag_coef_1 
                                 + input_tensor[(i+1) *N+ j+1] * weights_tensor[(i) *N+ j] *diag_coef_1
                                 
                                 + input_tensor[(i-1) *N+ j] * (weights_tensor[(i-1) *N+ j-1] + weights_tensor[(i-1) *N+ j]) / 2. *side_coef_1 
                                 + input_tensor[(i) *N+ j-1] * (weights_tensor[(i-1) *N+ j-1] + weights_tensor[(i) *N+ j-1]) / 2. *side_coef_1
                                 + input_tensor[(i) *N+ j + 1] * (weights_tensor[(i-1) *N+ j] + weights_tensor[(i) *N+ j]) / 2. *side_coef_1
                                 + input_tensor[(i+1), j] * (weights_tensor[(i) *N+ j-1] + weights_tensor[(i) *N+ j]) / 2. *side_coef_1
             
                                 + input_tensor[(i-1) *N+ j-1] * (1-weights_tensor[(i-1) *N+ j-1]) *diag_coef_2 
                                 + input_tensor[(i-1) *N+ j+1] * (1-weights_tensor[(i-1) *N+ j])*diag_coef_2 
                                 + input_tensor[(i+1) *N+ j-1] * (1-weights_tensor[(i) *N+ j-1]) *diag_coef_2 
                                 + input_tensor[(i+1) *N+ j+1] * (1-weights_tensor[(i) *N+ j]) *diag_coef_2
            
                                 + input_tensor[(i-1) *N+ j] * (2-weights_tensor[(i-1) *N+ j-1] - weights_tensor[(i-1) *N+ j]) / 2. *side_coef_2 
                                 + input_tensor[(i) *N+ j-1] * (2-weights_tensor[(i-1) *N+ j-1] - weights_tensor[(i) *N+ j-1]) / 2. *side_coef_2
                                 + input_tensor[(i) *N+ j + 1] * (2-weights_tensor[(i-1) *N+ j] - weights_tensor[(i) *N+ j]) / 2. *side_coef_2
                                 + input_tensor[(i+1) *N+ j] * (2-weights_tensor[(i) *N+ j-1] - weights_tensor[(i) *N+ j]) / 2. *side_coef_2;
        }
   }
}


int main(void)
{
	int N = 2048;  
	float *resp, *mask, *load_gpu;
	float * load_cpu =  (float*) malloc(N*N * sizeof(float));

	// Allocate Unified Memory – accessible from CPU or GPU
	cudaMallocManaged(&resp, N*N*sizeof(float));
	cudaMallocManaged(&mask, (N-1)*(N-1)*sizeof(float));
	cudaMallocManaged(&load_gpu, N*N*sizeof(float));

	// assume they are row first stored
	for (int i = 0; i < N; i++) {
		for (int j = 0; j < N; j++) {
			resp[i*N+j] = 1.0;
			if (i<N-1 & j<N-1){
				if (i<N/2)
					mask[i*N+j] = 1.0;
				else
					mask[i*N+j] = 0.0;
			}
		}
	}

	// Run kernel on CPU
    std::clock_t start = std::clock();
	mask_conv_cpu(N, resp, mask, load_cpu);
    double duration = ( std::clock() - start ) / (double) CLOCKS_PER_SEC;
	std::cout<<"CPU time cost: "<<duration<<std::endl;

	// Run kernel on GPU
    start = std::clock();
	mask_conv_gpu(N, resp, mask, load_gpu);
    duration = ( std::clock() - start ) / (double) CLOCKS_PER_SEC;
	std::cout<<"GPU time cost: "<<duration<<std::endl;

/*
	// check results
	ofstream myfile_cpu, myfile_gpu;
	myfile_cpu.open ("cpu.txt");
	myfile_gpu.open ("gpu.txt");
	for (int i = 0; i < N-2; i++){
		for (int j=0; j< N-2; j++){
			myfile_cpu <<load_cpu[N*i+j]<<" ";
			myfile_gpu <<load_gpu[N*i+j]<<" ";
		}
		myfile_cpu << std::endl;
		myfile_gpu << std::endl;
	}
	myfile_cpu.close();
	myfile_gpu.close();
*/
	// Free memory
	cudaFree(resp);
	cudaFree(mask);
	cudaFree(load_cpu);
	cudaFree(load_gpu);

	return 0;
}

//nvcc -arch=sm_61 -O3 mask_conv.cu -o mask_conv
/*
   			cpu 		gpu
256		0.001611	2.9e-05
1028 	0.037622	4.2e-05
*/

//nvcc mask_conv.cu -o mask_conv.cu.o 




	.file	"tmpxft_0035448c_00000000-6_mask_conv.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3771:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3771:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z13mask_conv_cpuiPfS_S_
	.type	_Z13mask_conv_cpuiPfS_S_, @function
_Z13mask_conv_cpuiPfS_S_:
.LFB3767:
	.cfi_startproc
	endbr64
	movslq	%edi, %rax
	movss	.LC1(%rip), %xmm6
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movq	%rdx, %r8
	movss	.LC0(%rip), %xmm9
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	decl	%edi
	leaq	0(,%rax,4), %r13
	movsd	.LC2(%rip), %xmm1
	movsd	.LC3(%rip), %xmm7
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	leaq	(%rsi,%rax,8), %r12
	movss	.LC4(%rip), %xmm8
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	xorl	%eax, %eax
	movq	%rcx, %rbx
	movl	$1, %r11d
.L3:
	cmpl	%r11d, %edi
	jle	.L9
	leaq	0(%r13,%rax), %rbp
	incl	%r11d
	leaq	(%r12,%rax), %r9
	movl	$1, %r10d
	movq	%rbp, %rcx
.L4:
	movss	(%rsi,%rax), %xmm14
	movss	(%r8,%rax), %xmm5
	movaps	%xmm9, %xmm10
	addq	$4, %r9
	movss	8(%rsi,%rax), %xmm13
	movss	4(%r8,%rax), %xmm4
	movaps	%xmm14, %xmm0
	movss	-4(%r9), %xmm12
	movss	(%r8,%rcx), %xmm3
	subss	%xmm5, %xmm10
	mulss	%xmm5, %xmm0
	movaps	%xmm13, %xmm15
	movss	4(%r9), %xmm11
	movss	4(%r8,%rcx), %xmm2
	mulss	%xmm4, %xmm15
	mulss	%xmm6, %xmm0
	mulss	%xmm6, %xmm15
	addss	%xmm0, %xmm15
	movaps	%xmm12, %xmm0
	mulss	%xmm3, %xmm0
	mulss	%xmm6, %xmm0
	addss	%xmm15, %xmm0
	movaps	%xmm11, %xmm15
	mulss	%xmm2, %xmm15
	mulss	%xmm6, %xmm15
	addss	%xmm15, %xmm0
	movaps	%xmm5, %xmm15
	addss	%xmm4, %xmm15
	mulss	4(%rsi,%rax), %xmm15
	cvtss2sd	%xmm0, %xmm0
	cvtss2sd	%xmm15, %xmm15
	mulsd	%xmm1, %xmm15
	mulsd	%xmm7, %xmm15
	addsd	%xmm0, %xmm15
	movaps	%xmm5, %xmm0
	addss	%xmm3, %xmm0
	mulss	(%rsi,%rcx), %xmm0
	cvtss2sd	%xmm0, %xmm0
	mulsd	%xmm1, %xmm0
	mulsd	%xmm7, %xmm0
	addsd	%xmm15, %xmm0
	movaps	%xmm4, %xmm15
	addss	%xmm2, %xmm15
	mulss	8(%rsi,%rcx), %xmm15
	cvtss2sd	%xmm15, %xmm15
	mulsd	%xmm1, %xmm15
	mulsd	%xmm7, %xmm15
	addsd	%xmm0, %xmm15
	movaps	%xmm3, %xmm0
	addss	%xmm2, %xmm0
	mulss	(%rsi,%r10,4), %xmm0
	incq	%r10
	cvtss2sd	%xmm0, %xmm0
	mulsd	%xmm1, %xmm0
	mulsd	%xmm7, %xmm0
	addsd	%xmm15, %xmm0
	movaps	%xmm8, %xmm15
	subss	%xmm5, %xmm15
	movaps	%xmm8, %xmm5
	subss	%xmm4, %xmm5
	mulss	%xmm14, %xmm15
	mulss	%xmm13, %xmm5
	cvtss2sd	%xmm15, %xmm15
	addsd	%xmm0, %xmm15
	cvtss2sd	%xmm5, %xmm0
	movaps	%xmm8, %xmm5
	subss	%xmm3, %xmm5
	addsd	%xmm15, %xmm0
	mulss	%xmm12, %xmm5
	cvtss2sd	%xmm5, %xmm5
	addsd	%xmm5, %xmm0
	movaps	%xmm8, %xmm5
	subss	%xmm2, %xmm5
	mulss	%xmm11, %xmm5
	cvtss2sd	%xmm5, %xmm5
	addsd	%xmm5, %xmm0
	movaps	%xmm10, %xmm5
	subss	%xmm4, %xmm5
	mulss	4(%rsi,%rax), %xmm5
	cvtss2sd	%xmm5, %xmm5
	mulsd	%xmm1, %xmm5
	addsd	%xmm5, %xmm0
	movaps	%xmm10, %xmm5
	subss	%xmm3, %xmm5
	mulss	(%rsi,%rcx), %xmm5
	cvtss2sd	%xmm5, %xmm5
	mulsd	%xmm1, %xmm5
	addsd	%xmm5, %xmm0
	movaps	%xmm9, %xmm5
	subss	%xmm4, %xmm5
	movaps	%xmm5, %xmm4
	subss	%xmm2, %xmm4
	mulss	8(%rsi,%rcx), %xmm4
	addq	$4, %rcx
	cvtss2sd	%xmm4, %xmm4
	mulsd	%xmm1, %xmm4
	addsd	%xmm4, %xmm0
	movaps	%xmm9, %xmm4
	subss	%xmm3, %xmm4
	movaps	%xmm4, %xmm3
	subss	%xmm2, %xmm3
	mulss	(%r9), %xmm3
	cvtss2sd	%xmm3, %xmm2
	mulsd	%xmm1, %xmm2
	addsd	%xmm2, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%rbx,%rax)
	addq	$4, %rax
	cmpl	%r10d, %edi
	jg	.L4
	movq	%rbp, %rax
	jmp	.L3
.L9:
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3767:
	.size	_Z13mask_conv_cpuiPfS_S_, .-_Z13mask_conv_cpuiPfS_S_
	.globl	_Z39__device_stub__Z10_mask_convffffiPfS_S_ffffiPfS_S_
	.type	_Z39__device_stub__Z10_mask_convffffiPfS_S_ffffiPfS_S_, @function
_Z39__device_stub__Z10_mask_convffffiPfS_S_ffffiPfS_S_:
.LFB3793:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movl	%edi, 28(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	64(%rsp), %rcx
	movss	%xmm0, 44(%rsp)
	movss	%xmm1, 40(%rsp)
	movss	%xmm2, 36(%rsp)
	movss	%xmm3, 32(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	%rsp, %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z10_mask_convffffiPfS_S_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L10:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3793:
	.size	_Z39__device_stub__Z10_mask_convffffiPfS_S_ffffiPfS_S_, .-_Z39__device_stub__Z10_mask_convffffiPfS_S_ffffiPfS_S_
	.globl	_Z10_mask_convffffiPfS_S_
	.type	_Z10_mask_convffffiPfS_S_, @function
_Z10_mask_convffffiPfS_S_:
.LFB3794:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z10_mask_convffffiPfS_S_ffffiPfS_S_
	.cfi_endproc
.LFE3794:
	.size	_Z10_mask_convffffiPfS_S_, .-_Z10_mask_convffffiPfS_S_
	.globl	_Z13mask_conv_gpuiPfS_S_
	.type	_Z13mask_conv_gpuiPfS_S_, @function
_Z13mask_conv_gpuiPfS_S_:
.LFB3766:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	leal	31(%rdi), %eax
	movq	%rcx, %r13
	xorl	%r9d, %r9d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	shrl	$5, %eax
	movq	%rdx, %r12
	xorl	%r8d, %r8d
	movabsq	$137438953504, %rdx
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	$1, %ecx
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	%edi, %ebx
	movl	$1, %esi
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	movl	%eax, 20(%rsp)
	movl	%eax, 24(%rsp)
	movq	20(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	movss	.LC4(%rip), %xmm3
	movq	%r13, %rcx
	movq	%r12, %rdx
	movl	%ebx, %edi
	movss	.LC1(%rip), %xmm2
	movq	%rbp, %rsi
	movaps	%xmm3, %xmm1
	movaps	%xmm2, %xmm0
	call	_Z39__device_stub__Z10_mask_convffffiPfS_S_ffffiPfS_S_
.L16:
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	cudaDeviceSynchronize@PLT
	.cfi_endproc
.LFE3766:
	.size	_Z13mask_conv_gpuiPfS_S_, .-_Z13mask_conv_gpuiPfS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC7:
	.string	"CPU time cost: "
.LC8:
	.string	"GPU time cost: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3768:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$16777216, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$48, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	leaq	16(%rsp), %rdi
	movl	$1, %edx
	movl	$16777216, %esi
	movq	%rax, %rbx
	call	cudaMallocManaged@PLT
	leaq	24(%rsp), %rdi
	movl	$1, %edx
	movl	$16760836, %esi
	call	cudaMallocManaged@PLT
	leaq	32(%rsp), %rdi
	movl	$1, %edx
	movl	$16777216, %esi
	call	cudaMallocManaged@PLT
	movq	16(%rsp), %r8
	movq	24(%rsp), %rdi
	xorl	%eax, %eax
	movss	.LC4(%rip), %xmm0
.L19:
	movq	%rax, %rcx
	movl	%eax, %esi
	xorl	%edx, %edx
	salq	$13, %rcx
.L22:
	cmpl	%esi, %edx
	movl	%esi, %r9d
	movss	%xmm0, (%r8,%rcx)
	cmovge	%edx, %r9d
	cmpl	$2047, %r9d
	je	.L20
	cmpq	$1023, %rax
	ja	.L21
	movss	%xmm0, (%rdi,%rcx)
	jmp	.L20
.L21:
	movl	$0x00000000, (%rdi,%rcx)
.L20:
	incl	%edx
	addq	$4, %rcx
	cmpl	$2048, %edx
	jne	.L22
	incq	%rax
	cmpq	$2048, %rax
	jne	.L19
	call	clock@PLT
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	%rbx, %rcx
	movl	$2048, %edi
	movq	%rax, %rbp
	call	_Z13mask_conv_cpuiPfS_S_
	call	clock@PLT
	leaq	.LC7(%rip), %rsi
	subq	%rbp, %rax
	leaq	_ZSt4cout(%rip), %rbp
	movq	%rbp, %rdi
	cvtsi2sdq	%rax, %xmm0
	divsd	.LC6(%rip), %xmm0
	movsd	%xmm0, 8(%rsp)
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	8(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	call	clock@PLT
	movq	32(%rsp), %rcx
	movq	24(%rsp), %rdx
	movl	$2048, %edi
	movq	16(%rsp), %rsi
	movq	%rax, %r12
	call	_Z13mask_conv_gpuiPfS_S_
	call	clock@PLT
	leaq	.LC8(%rip), %rsi
	movq	%rbp, %rdi
	subq	%r12, %rax
	cvtsi2sdq	%rax, %xmm0
	divsd	.LC6(%rip), %xmm0
	movsd	%xmm0, 8(%rsp)
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	8(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$48, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3768:
	.size	main, .-main
	.section	.rodata.str1.1
.LC9:
	.string	"_Z10_mask_convffffiPfS_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3796:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10_mask_convffffiPfS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3796:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1073741824
	.align 4
.LC1:
	.long	1098907648
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC2:
	.long	0
	.long	1071644672
	.align 8
.LC3:
	.long	0
	.long	1076887552
	.section	.rodata.cst4
	.align 4
.LC4:
	.long	1065353216
	.section	.rodata.cst8
	.align 8
.LC6:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <math.h>
#include <cstdio>
#include <ctime>
#include <assert.h>     /* assert */
using namespace std;
//0 3 6 
//1 4 7
//2 5 8
// row idx: i
// col idx: j
__global__
void _mask_conv(float diag_coef_1, float diag_coef_2, float side_coef_1, float side_coef_2, int N, float *input_tensor, float *mask_tensor, float *output_tensor)
{

	float diag_coef_diff = diag_coef_1 - diag_coef_2;
	float side_coef_diff = side_coef_1 - side_coef_2;

	int index_x = blockIdx.x * blockDim.x + threadIdx.x;
	int index_y = blockIdx.y * blockDim.y + threadIdx.y;

	int stride_x = blockDim.x * gridDim.x;
	int stride_y = blockDim.y * gridDim.y;
	for (int i = index_x+1; i < N-1; i += stride_x)
	{
		for (int j = index_y+1; j < N-1; j += stride_y)
		{
/*
			// this one is 10% faster, but has some hidden bug...
			int output_index = N*(i-1) + (j-1);

			int input_index_0 = N*(i-1) + j-1;
			int input_index_1 = N*(i) + j-1;
			int input_index_2 = N*(i+1) + j-1;
			int input_index_3 = N*(i-1) + j;
			int input_index_5 = N*(i+1) + j;
			int input_index_6 = N*(i-1) + j+1;
			int input_index_7 = N*(i) + j+1;
			int input_index_8 = N*(i+1) + j+1;

			int mask_index_0 = (N-1)*(i-1) + j-1;
			int mask_index_1 = (N-1)*(i) + j-1;
			int mask_index_3 = (N-1)*(i-1) + j;
			int mask_index_4 = (N-1)*(i) + j;
			
			float mask_conv_diag = input_tensor[input_index_0] * mask_tensor[mask_index_0] 
							     + input_tensor[input_index_6] * mask_tensor[mask_index_3]
								 + input_tensor[input_index_2] * mask_tensor[mask_index_1] 
						  	 	 + input_tensor[input_index_8] * mask_tensor[mask_index_4];
			float mask_conv_side = input_tensor[input_index_3] * (mask_tensor[mask_index_0]+mask_tensor[mask_index_3])
  							 	 + input_tensor[input_index_1] * (mask_tensor[mask_index_0]+mask_tensor[mask_index_1])
  							 	 + input_tensor[input_index_7] * (mask_tensor[mask_index_3]+mask_tensor[mask_index_4])
  							 	 + input_tensor[input_index_5] * (mask_tensor[mask_index_1]+mask_tensor[mask_index_4]);
			float sum_resp_diag = input_tensor[input_index_0] + input_tensor[input_index_6] + input_tensor[input_index_2] + input_tensor[input_index_8];
			float sum_resp_side = input_tensor[input_index_3] + input_tensor[input_index_1] + input_tensor[input_index_7] + input_tensor[input_index_5];

			output_tensor[output_index] = mask_conv_diag *diag_coef_diff
										+ mask_conv_side *side_coef_diff/2
										+ sum_resp_diag * diag_coef_2
										+ sum_resp_side * diag_coef_2;
*/	
            output_tensor[(i-1) *N+ j-1]  = input_tensor[(i-1)*N+ j-1] * mask_tensor[(i-1) *N+ j-1] *diag_coef_1 
                                 + input_tensor[(i-1) *N+ j+1] * mask_tensor[(i-1) *N+ j] *diag_coef_1 
                                 + input_tensor[(i+1) *N+ j-1] * mask_tensor[(i) *N+ j-1] *diag_coef_1 
                                 + input_tensor[(i+1) *N+ j+1] * mask_tensor[(i) *N+ j] *diag_coef_1
                                 
                                 + input_tensor[(i-1) *N+ j] * (mask_tensor[(i-1) *N+ j-1] + mask_tensor[(i-1) *N+ j]) / 2. *side_coef_1 
                                 + input_tensor[(i) *N+ j-1] * (mask_tensor[(i-1) *N+ j-1] + mask_tensor[(i) *N+ j-1]) / 2. *side_coef_1
                                 + input_tensor[(i) *N+ j + 1] * (mask_tensor[(i-1) *N+ j] + mask_tensor[(i) *N+ j]) / 2. *side_coef_1
                                 + input_tensor[(i+1), j] * (mask_tensor[(i) *N+ j-1] + mask_tensor[(i) *N+ j]) / 2. *side_coef_1
             
                                 + input_tensor[(i-1) *N+ j-1] * (1-mask_tensor[(i-1) *N+ j-1]) *diag_coef_2 
                                 + input_tensor[(i-1) *N+ j+1] * (1-mask_tensor[(i-1) *N+ j])*diag_coef_2 
                                 + input_tensor[(i+1) *N+ j-1] * (1-mask_tensor[(i) *N+ j-1]) *diag_coef_2 
                                 + input_tensor[(i+1) *N+ j+1] * (1-mask_tensor[(i) *N+ j]) *diag_coef_2
            
                                 + input_tensor[(i-1) *N+ j] * (2-mask_tensor[(i-1) *N+ j-1] - mask_tensor[(i-1) *N+ j]) / 2. *side_coef_2 
                                 + input_tensor[(i) *N+ j-1] * (2-mask_tensor[(i-1) *N+ j-1] - mask_tensor[(i) *N+ j-1]) / 2. *side_coef_2
                                 + input_tensor[(i) *N+ j + 1] * (2-mask_tensor[(i-1) *N+ j] - mask_tensor[(i) *N+ j]) / 2. *side_coef_2
                                 + input_tensor[(i+1) *N+ j] * (2-mask_tensor[(i) *N+ j-1] - mask_tensor[(i) *N+ j]) / 2. *side_coef_2;
						
		}
	}
}
             
void mask_conv_gpu(int mat_row_num,  float *input_tensor, float *weights_tensor, float *output_tensor) {
	float diag_coef_1 = 16;
	float side_coef_1 = 16;
	float diag_coef_2 = 1;
	float side_coef_2 = 1;
	dim3 blocksize( 32, 32 );
	int bx = (mat_row_num+blocksize.x-1)/blocksize.x ;
	int by = (mat_row_num+blocksize.y-1)/blocksize.y ;
	dim3 gridsize(bx, by);
    _mask_conv<<<gridsize,blocksize>>>(diag_coef_1, diag_coef_2, side_coef_1, side_coef_2, mat_row_num, input_tensor, weights_tensor, output_tensor);
    hipDeviceSynchronize();
}


void mask_conv_cpu(int N, float *input_tensor, float *weights_tensor, float * output_tensor)
{
	float diag_coef_1 = 16;
	float side_coef_1 = 16;
	float diag_coef_2 = 1;
	float side_coef_2 = 1;
	float diag_coef_diff = diag_coef_1 - diag_coef_2;
	float side_coef_diff = side_coef_1 - side_coef_2;

    for (int i = 1; i < N-1; i++) {
        for (int j = 1; j < N-1; j++) {

            output_tensor[(i-1) *N+ j-1]  = input_tensor[(i-1)*N+ j-1] * weights_tensor[(i-1) *N+ j-1] *diag_coef_1 
                                 + input_tensor[(i-1) *N+ j+1] * weights_tensor[(i-1) *N+ j] *diag_coef_1 
                                 + input_tensor[(i+1) *N+ j-1] * weights_tensor[(i) *N+ j-1] *diag_coef_1 
                                 + input_tensor[(i+1) *N+ j+1] * weights_tensor[(i) *N+ j] *diag_coef_1
                                 
                                 + input_tensor[(i-1) *N+ j] * (weights_tensor[(i-1) *N+ j-1] + weights_tensor[(i-1) *N+ j]) / 2. *side_coef_1 
                                 + input_tensor[(i) *N+ j-1] * (weights_tensor[(i-1) *N+ j-1] + weights_tensor[(i) *N+ j-1]) / 2. *side_coef_1
                                 + input_tensor[(i) *N+ j + 1] * (weights_tensor[(i-1) *N+ j] + weights_tensor[(i) *N+ j]) / 2. *side_coef_1
                                 + input_tensor[(i+1), j] * (weights_tensor[(i) *N+ j-1] + weights_tensor[(i) *N+ j]) / 2. *side_coef_1
             
                                 + input_tensor[(i-1) *N+ j-1] * (1-weights_tensor[(i-1) *N+ j-1]) *diag_coef_2 
                                 + input_tensor[(i-1) *N+ j+1] * (1-weights_tensor[(i-1) *N+ j])*diag_coef_2 
                                 + input_tensor[(i+1) *N+ j-1] * (1-weights_tensor[(i) *N+ j-1]) *diag_coef_2 
                                 + input_tensor[(i+1) *N+ j+1] * (1-weights_tensor[(i) *N+ j]) *diag_coef_2
            
                                 + input_tensor[(i-1) *N+ j] * (2-weights_tensor[(i-1) *N+ j-1] - weights_tensor[(i-1) *N+ j]) / 2. *side_coef_2 
                                 + input_tensor[(i) *N+ j-1] * (2-weights_tensor[(i-1) *N+ j-1] - weights_tensor[(i) *N+ j-1]) / 2. *side_coef_2
                                 + input_tensor[(i) *N+ j + 1] * (2-weights_tensor[(i-1) *N+ j] - weights_tensor[(i) *N+ j]) / 2. *side_coef_2
                                 + input_tensor[(i+1) *N+ j] * (2-weights_tensor[(i) *N+ j-1] - weights_tensor[(i) *N+ j]) / 2. *side_coef_2;
        }
   }
}


int main(void)
{
	int N = 2048;  
	float *resp, *mask, *load_gpu;
	float * load_cpu =  (float*) malloc(N*N * sizeof(float));

	// Allocate Unified Memory – accessible from CPU or GPU
	hipMallocManaged(&resp, N*N*sizeof(float));
	hipMallocManaged(&mask, (N-1)*(N-1)*sizeof(float));
	hipMallocManaged(&load_gpu, N*N*sizeof(float));

	// assume they are row first stored
	for (int i = 0; i < N; i++) {
		for (int j = 0; j < N; j++) {
			resp[i*N+j] = 1.0;
			if (i<N-1 & j<N-1){
				if (i<N/2)
					mask[i*N+j] = 1.0;
				else
					mask[i*N+j] = 0.0;
			}
		}
	}

	// Run kernel on CPU
    std::clock_t start = std::clock();
	mask_conv_cpu(N, resp, mask, load_cpu);
    double duration = ( std::clock() - start ) / (double) CLOCKS_PER_SEC;
	std::cout<<"CPU time cost: "<<duration<<std::endl;

	// Run kernel on GPU
    start = std::clock();
	mask_conv_gpu(N, resp, mask, load_gpu);
    duration = ( std::clock() - start ) / (double) CLOCKS_PER_SEC;
	std::cout<<"GPU time cost: "<<duration<<std::endl;

/*
	// check results
	ofstream myfile_cpu, myfile_gpu;
	myfile_cpu.open ("cpu.txt");
	myfile_gpu.open ("gpu.txt");
	for (int i = 0; i < N-2; i++){
		for (int j=0; j< N-2; j++){
			myfile_cpu <<load_cpu[N*i+j]<<" ";
			myfile_gpu <<load_gpu[N*i+j]<<" ";
		}
		myfile_cpu << std::endl;
		myfile_gpu << std::endl;
	}
	myfile_cpu.close();
	myfile_gpu.close();
*/
	// Free memory
	hipFree(resp);
	hipFree(mask);
	hipFree(load_cpu);
	hipFree(load_gpu);

	return 0;
}

//nvcc -arch=sm_61 -O3 mask_conv.cu -o mask_conv
/*
   			cpu 		gpu
256		0.001611	2.9e-05
1028 	0.037622	4.2e-05
*/

//nvcc mask_conv.cu -o mask_conv.cu.o 




	.text
	.file	"mask_conv.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z25__device_stub___mask_convffffiPfS_S_ # -- Begin function _Z25__device_stub___mask_convffffiPfS_S_
	.type	_Z25__device_stub___mask_convffffiPfS_S_,@function
_Z25__device_stub___mask_convffffiPfS_S_: # @_Z25__device_stub___mask_convffffiPfS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movss	%xmm0, (%rax)
	leaq	16(%rsp), %r8
	movss	%xmm1, (%r8)
	leaq	12(%rsp), %r9
	movss	%xmm2, (%r9)
	leaq	8(%rsp), %r10
	movss	%xmm3, (%r10)
	leaq	4(%rsp), %r11
	movl	%edi, (%r11)
	leaq	56(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%r8, 8(%rbx)
	movq	%r9, 16(%rbx)
	movq	%r10, 24(%rbx)
	movq	%r11, 32(%rbx)
	movq	%rdi, 40(%rbx)
	movq	%rsi, 48(%rbx)
	movq	%rdx, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10_mask_convffffiPfS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub___mask_convffffiPfS_S_, .Lfunc_end0-_Z25__device_stub___mask_convffffiPfS_S_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z13mask_conv_gpuiPfS_S_
.LCPI1_0:
	.long	0x41800000                      # float 16
.LCPI1_1:
	.long	0x3f800000                      # float 1
	.text
	.globl	_Z13mask_conv_gpuiPfS_S_
	.type	_Z13mask_conv_gpuiPfS_S_,@function
_Z13mask_conv_gpuiPfS_S_:               # @_Z13mask_conv_gpuiPfS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rcx, %rbx
	movq	%rdx, %r14
	movq	%rsi, %r15
	movl	%edi, %r12d
	leal	31(%r12), %eax
	shrl	$5, %eax
	movq	%rax, %rdi
	shlq	$32, %rdi
	orq	%rax, %rdi
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movss	.LCPI1_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movss	.LCPI1_1(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	movaps	%xmm0, %xmm2
	movaps	%xmm1, %xmm3
	movl	%r12d, %edi
	movq	%r15, %rsi
	movq	%r14, %rdx
	movq	%rbx, %rcx
	callq	_Z25__device_stub___mask_convffffiPfS_S_
.LBB1_2:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	hipDeviceSynchronize            # TAILCALL
.Lfunc_end1:
	.size	_Z13mask_conv_gpuiPfS_S_, .Lfunc_end1-_Z13mask_conv_gpuiPfS_S_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z13mask_conv_cpuiPfS_S_
.LCPI2_0:
	.long	0x41800000                      # float 16
.LCPI2_3:
	.long	0x3f800000                      # float 1
.LCPI2_4:
	.long	0x40000000                      # float 2
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI2_1:
	.quad	0x3fe0000000000000              # double 0.5
.LCPI2_2:
	.quad	0x4030000000000000              # double 16
	.text
	.globl	_Z13mask_conv_cpuiPfS_S_
	.type	_Z13mask_conv_cpuiPfS_S_,@function
_Z13mask_conv_cpuiPfS_S_:               # @_Z13mask_conv_cpuiPfS_S_
	.cfi_startproc
# %bb.0:
                                        # kill: def $edi killed $edi def $rdi
	cmpl	$3, %edi
	jl	.LBB2_6
# %bb.1:                                # %.preheader.lr.ph
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%edi, %r10d
	decl	%edi
	leaq	(%rsi,%r10,8), %rax
	addq	$8, %rax
	leaq	(,%r10,4), %r8
	leaq	(%rsi,%r10,4), %r9
	addq	$8, %r9
	leaq	(%rdx,%r10,4), %r10
	addq	$4, %r10
	leaq	8(%rsi), %r11
	addq	$4, %rdx
	leaq	-4(,%rdi,4), %rbx
	movl	$1, %r14d
	movss	.LCPI2_0(%rip), %xmm2           # xmm2 = mem[0],zero,zero,zero
	movsd	.LCPI2_1(%rip), %xmm3           # xmm3 = mem[0],zero
	movsd	.LCPI2_2(%rip), %xmm5           # xmm5 = mem[0],zero
	movss	.LCPI2_3(%rip), %xmm11          # xmm11 = mem[0],zero,zero,zero
	movss	.LCPI2_4(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
.LBB2_2:                                # %.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_3 Depth 2
	incq	%r14
	xorl	%r15d, %r15d
.LBB2_3:                                #   Parent Loop BB2_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	-4(%rdx,%r15), %xmm7            # xmm7 = mem[0],zero,zero,zero
	movss	(%rdx,%r15), %xmm6              # xmm6 = mem[0],zero,zero,zero
	movss	-8(%r11,%r15), %xmm8            # xmm8 = mem[0],zero,zero,zero
	movss	-4(%r11,%r15), %xmm15           # xmm15 = mem[0],zero,zero,zero
	movss	%xmm15, -4(%rsp)                # 4-byte Spill
	movaps	%xmm11, %xmm9
	subss	%xmm7, %xmm9
	mulss	%xmm8, %xmm9
	mulss	%xmm7, %xmm8
	mulss	%xmm2, %xmm8
	movss	(%r11,%r15), %xmm0              # xmm0 = mem[0],zero,zero,zero
	movaps	%xmm11, %xmm10
	subss	%xmm6, %xmm10
	mulss	%xmm0, %xmm10
	mulss	%xmm6, %xmm0
	mulss	%xmm2, %xmm0
	addss	%xmm8, %xmm0
	movss	-8(%rax,%r15), %xmm4            # xmm4 = mem[0],zero,zero,zero
	movss	(%rax,%r15), %xmm14             # xmm14 = mem[0],zero,zero,zero
	movss	-4(%r10,%r15), %xmm12           # xmm12 = mem[0],zero,zero,zero
	movss	(%r10,%r15), %xmm8              # xmm8 = mem[0],zero,zero,zero
	subss	%xmm12, %xmm11
	mulss	%xmm4, %xmm11
	mulss	%xmm12, %xmm4
	mulss	%xmm2, %xmm4
	addss	%xmm0, %xmm4
	movss	.LCPI2_3(%rip), %xmm13          # xmm13 = mem[0],zero,zero,zero
	subss	%xmm8, %xmm13
	mulss	%xmm14, %xmm13
	mulss	%xmm8, %xmm14
	mulss	%xmm2, %xmm14
	addss	%xmm4, %xmm14
	xorps	%xmm0, %xmm0
	cvtss2sd	%xmm14, %xmm0
	movaps	%xmm7, %xmm4
	movaps	%xmm1, %xmm14
	subss	%xmm7, %xmm14
	addss	%xmm6, %xmm7
	mulss	%xmm15, %xmm7
	xorps	%xmm2, %xmm2
	cvtss2sd	%xmm7, %xmm2
	mulsd	%xmm3, %xmm2
	movapd	%xmm5, %xmm7
	mulsd	%xmm5, %xmm2
	addsd	%xmm0, %xmm2
	addss	%xmm12, %xmm4
	movss	-8(%r9,%r15), %xmm0             # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, -8(%rsp)                 # 4-byte Spill
	movss	(%r9,%r15), %xmm5               # xmm5 = mem[0],zero,zero,zero
	mulss	%xmm0, %xmm4
	movaps	%xmm1, %xmm15
	movapd	%xmm3, %xmm1
	xorps	%xmm3, %xmm3
	cvtss2sd	%xmm4, %xmm3
	mulsd	%xmm1, %xmm3
	mulsd	%xmm7, %xmm3
	addsd	%xmm2, %xmm3
	movaps	%xmm14, %xmm4
	subss	%xmm6, %xmm4
	movaps	%xmm15, %xmm0
	subss	%xmm6, %xmm0
	addss	%xmm8, %xmm6
	mulss	%xmm5, %xmm6
	xorps	%xmm2, %xmm2
	cvtss2sd	%xmm6, %xmm2
	mulsd	%xmm1, %xmm2
	mulsd	%xmm7, %xmm2
	addsd	%xmm3, %xmm2
	subss	%xmm12, %xmm14
	movaps	%xmm15, %xmm6
	subss	%xmm12, %xmm6
	addss	%xmm8, %xmm12
	mulss	4(%rsi,%r15), %xmm12
	xorps	%xmm3, %xmm3
	cvtss2sd	%xmm12, %xmm3
	mulsd	%xmm1, %xmm3
	mulsd	%xmm7, %xmm3
	addsd	%xmm2, %xmm3
	xorps	%xmm2, %xmm2
	cvtss2sd	%xmm9, %xmm2
	addsd	%xmm3, %xmm2
	xorps	%xmm3, %xmm3
	cvtss2sd	%xmm10, %xmm3
	addsd	%xmm2, %xmm3
	xorps	%xmm2, %xmm2
	cvtss2sd	%xmm11, %xmm2
	addsd	%xmm3, %xmm2
	xorps	%xmm3, %xmm3
	cvtss2sd	%xmm13, %xmm3
	movss	.LCPI2_3(%rip), %xmm11          # xmm11 = mem[0],zero,zero,zero
	addsd	%xmm2, %xmm3
	mulss	-4(%rsp), %xmm4                 # 4-byte Folded Reload
	xorps	%xmm2, %xmm2
	cvtss2sd	%xmm4, %xmm2
	mulsd	%xmm1, %xmm2
	addsd	%xmm3, %xmm2
	mulss	-8(%rsp), %xmm14                # 4-byte Folded Reload
	xorps	%xmm3, %xmm3
	cvtss2sd	%xmm14, %xmm3
	mulsd	%xmm1, %xmm3
	addsd	%xmm2, %xmm3
	subss	%xmm8, %xmm0
	mulss	%xmm5, %xmm0
	cvtss2sd	%xmm0, %xmm0
	mulsd	%xmm1, %xmm0
	addsd	%xmm3, %xmm0
	movapd	%xmm1, %xmm3
	movapd	%xmm7, %xmm5
	movaps	%xmm15, %xmm1
	subss	%xmm8, %xmm6
	mulss	-4(%rax,%r15), %xmm6
	xorps	%xmm2, %xmm2
	cvtss2sd	%xmm6, %xmm2
	mulsd	%xmm3, %xmm2
	addsd	%xmm0, %xmm2
	xorps	%xmm0, %xmm0
	cvtsd2ss	%xmm2, %xmm0
	movss	.LCPI2_0(%rip), %xmm2           # xmm2 = mem[0],zero,zero,zero
	movss	%xmm0, (%rcx,%r15)
	addq	$4, %r15
	cmpq	%r15, %rbx
	jne	.LBB2_3
# %bb.4:                                # %._crit_edge
                                        #   in Loop: Header=BB2_2 Depth=1
	addq	%r8, %rax
	addq	%r8, %r9
	addq	%r8, %r10
	addq	%r8, %r11
	addq	%r8, %rdx
	addq	%r8, %rcx
	cmpq	%rdi, %r14
	jne	.LBB2_2
# %bb.5:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r14
	.cfi_restore %r15
.LBB2_6:                                # %._crit_edge192
	retq
.Lfunc_end2:
	.size	_Z13mask_conv_cpuiPfS_S_, .Lfunc_end2-_Z13mask_conv_cpuiPfS_S_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI3_0:
	.long	0x3f800000                      # float 1
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI3_1:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$40, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	$16777216, %edi                 # imm = 0x1000000
	callq	malloc
	movq	%rax, %rbx
	leaq	24(%rsp), %r14
	movl	$16777216, %esi                 # imm = 0x1000000
	movq	%r14, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	8(%rsp), %rdi
	movl	$16760836, %esi                 # imm = 0xFFC004
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	32(%rsp), %rdi
	movl	$16777216, %esi                 # imm = 0x1000000
	movl	$1, %edx
	callq	hipMallocManaged
	xorl	%eax, %eax
	movq	(%r14), %rcx
	movss	.LCPI3_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movl	$8192, %edx                     # imm = 0x2000
	xorl	%esi, %esi
.LBB3_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_4 Depth 2
	movaps	%xmm0, %xmm1
	cmpq	$1024, %rsi                     # imm = 0x400
	jb	.LBB3_3
# %bb.2:                                # %.preheader
                                        #   in Loop: Header=BB3_1 Depth=1
	xorps	%xmm1, %xmm1
.LBB3_3:                                # %.preheader
                                        #   in Loop: Header=BB3_1 Depth=1
	movq	8(%rsp), %rdi
	addq	%rax, %rdi
	xorl	%r8d, %r8d
.LBB3_4:                                #   Parent Loop BB3_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$1065353216, (%rcx,%r8,4)       # imm = 0x3F800000
	cmpq	$2047, %rsi                     # imm = 0x7FF
	je	.LBB3_7
# %bb.5:                                #   in Loop: Header=BB3_4 Depth=2
	cmpq	$2047, %r8                      # imm = 0x7FF
	je	.LBB3_7
# %bb.6:                                # %.sink.split
                                        #   in Loop: Header=BB3_4 Depth=2
	movss	%xmm1, (%rdi,%r8,4)
.LBB3_7:                                #   in Loop: Header=BB3_4 Depth=2
	incq	%r8
	cmpq	$2048, %r8                      # imm = 0x800
	jne	.LBB3_4
# %bb.8:                                #   in Loop: Header=BB3_1 Depth=1
	incq	%rsi
	addq	%rdx, %rax
	addq	%rdx, %rcx
	cmpq	$2048, %rsi                     # imm = 0x800
	jne	.LBB3_1
# %bb.9:
	callq	clock
	movq	%rax, %r14
	movq	24(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	$2048, %edi                     # imm = 0x800
	movq	%rbx, %rcx
	callq	_Z13mask_conv_cpuiPfS_S_
	callq	clock
	subq	%r14, %rax
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI3_1(%rip), %xmm0
	movsd	%xmm0, 16(%rsp)                 # 8-byte Spill
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$15, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movsd	16(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r14
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	callq	clock
	movq	%rax, %r14
	movq	24(%rsp), %rsi
	movq	8(%rsp), %rdx
	movq	32(%rsp), %rcx
	movl	$2048, %edi                     # imm = 0x800
	callq	_Z13mask_conv_gpuiPfS_S_
	callq	clock
	subq	%r14, %rax
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI3_1(%rip), %xmm0
	movsd	%xmm0, 16(%rsp)                 # 8-byte Spill
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$15, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movsd	16(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r14
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10_mask_convffffiPfS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10_mask_convffffiPfS_S_,@object # @_Z10_mask_convffffiPfS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z10_mask_convffffiPfS_S_
	.p2align	3, 0x0
_Z10_mask_convffffiPfS_S_:
	.quad	_Z25__device_stub___mask_convffffiPfS_S_
	.size	_Z10_mask_convffffiPfS_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CPU time cost: "
	.size	.L.str, 16

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"GPU time cost: "
	.size	.L.str.1, 16

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10_mask_convffffiPfS_S_"
	.size	.L__unnamed_1, 26

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub___mask_convffffiPfS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10_mask_convffffiPfS_S_
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10_mask_convffffiPfS_S_ ; -- Begin function _Z10_mask_convffffiPfS_S_
	.globl	_Z10_mask_convffffiPfS_S_
	.p2align	8
	.type	_Z10_mask_convffffiPfS_S_,@function
_Z10_mask_convffffiPfS_S_:              ; @_Z10_mask_convffffiPfS_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s17, s[0:1], 0x3c
	s_load_b32 s16, s[0:1], 0x10
	s_add_u32 s2, s0, 48
	v_and_b32_e32 v6, 0x3ff, v0
	s_addc_u32 s3, s1, 0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s13, s17, 0xffff
	s_add_i32 s12, s16, -1
	s_mul_i32 s14, s14, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v6, s14, 1
	v_cmpx_gt_i32_e64 s12, v9
	s_cbranch_execz .LBB0_6
; %bb.1:                                ; %.lr.ph205
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[2:3], 0x0
	s_load_b128 s[8:11], s[0:1], 0x18
	v_bfe_u32 v4, v0, 10, 10
	s_lshr_b32 s17, s17, 16
	s_load_b64 s[18:19], s[0:1], 0x28
	s_mul_i32 s15, s15, s17
	v_add_nc_u32_e32 v12, s14, v6
	v_add3_u32 v4, v4, s15, 1
	s_mov_b32 s20, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v13, 2, v12
	v_ashrrev_i32_e32 v5, 31, v4
	v_cmp_gt_i32_e32 vcc_lo, s12, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b64 v[7:8], 2, v[4:5]
	v_mad_u64_u32 v[5:6], null, s16, v9, v[4:5]
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[0:1], s6
	v_cvt_f64_f32_e32 v[2:3], s7
	s_mul_i32 s13, s2, s13
	s_mul_i32 s2, s3, s17
	v_add_co_u32 v10, s0, s8, v7
	s_ashr_i32 s3, s2, 31
	v_add_co_ci_u32_e64 v11, s0, s9, v8, s0
	s_lshl_b64 s[6:7], s[2:3], 2
	v_mad_u64_u32 v[7:8], null, s16, v12, v[4:5]
	v_mul_lo_u32 v12, s16, v13
	s_add_u32 s3, s8, 4
	s_addc_u32 s14, s9, 0
	s_mul_i32 s15, s13, s16
	s_add_u32 s16, s10, -4
	s_addc_u32 s17, s11, -1
	s_add_u32 s18, s18, -4
	s_addc_u32 s19, s19, -1
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
	s_and_saveexec_b32 s21, vcc_lo
	s_cbranch_execz .LBB0_5
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_ashrrev_i32_e32 v6, 31, v5
	v_ashrrev_i32_e32 v8, 31, v7
	v_mov_b32_e32 v21, v4
	s_mov_b64 s[10:11], 0
	s_mov_b32 s22, 0
	v_lshlrev_b64 v[17:18], 2, v[5:6]
	v_lshlrev_b64 v[19:20], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, s0, s3, v17
	v_add_co_ci_u32_e64 v8, s0, s14, v18, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v13, s0, s3, v19
	v_add_co_ci_u32_e64 v14, s0, s14, v20, s0
	v_add_co_u32 v15, s0, s16, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v16, s0, s17, v20, s0
	v_add_co_u32 v17, s0, s16, v17
	v_add_co_ci_u32_e64 v18, s0, s17, v18, s0
	v_add_co_u32 v19, s0, s18, v19
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v20, s0, s19, v20, s0
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_co_u32 v22, s0, v15, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v23, s0, s11, v16, s0
	v_add_co_u32 v24, s0, v13, s10
	v_add_co_ci_u32_e64 v25, s0, s11, v14, s0
	v_add_co_u32 v30, s0, v17, s10
	global_load_b64 v[28:29], v[22:23], off
	global_load_b96 v[22:24], v[24:25], off offset:-8
	v_add_co_ci_u32_e64 v31, s0, s11, v18, s0
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v34, v24, v29
	v_add_nc_u32_e32 v25, v12, v21
	v_mul_f32_e32 v35, v22, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v36, s4, v34 :: v_dual_add_nc_u32 v21, s2, v21
	v_ashrrev_i32_e32 v26, 31, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_i32_e64 s1, s12, v21
	v_lshlrev_b64 v[25:26], 2, v[25:26]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v25, s0, s8, v25
	v_add_co_ci_u32_e64 v26, s0, s9, v26, s0
	global_load_b64 v[30:31], v[30:31], off
	global_load_b96 v[25:27], v[25:26], off offset:-4
	v_add_co_u32 v32, s0, v6, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v33, s0, s11, v8, s0
	s_clause 0x1
	global_load_b32 v40, v[32:33], off offset:-8
	global_load_b32 v41, v[32:33], off
	v_add_co_u32 v32, s0, v10, s10
	v_add_co_ci_u32_e64 v33, s0, s11, v11, s0
	v_fmac_f32_e32 v36, s4, v35
	global_load_b32 v42, v[32:33], off
	v_add_f32_e32 v32, v28, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v32, v32, v23
	v_cvt_f64_f32_e32 v[32:33], v32
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[32:33], v[32:33], 0.5
	s_waitcnt vmcnt(4)
	v_add_f32_e32 v35, v28, v30
	s_waitcnt vmcnt(3)
	v_dual_mul_f32 v34, v25, v30 :: v_dual_mul_f32 v37, v27, v31
	v_add_f32_e32 v38, v29, v31
	s_delay_alu instid0(VALU_DEP_2)
	v_fmac_f32_e32 v36, s4, v34
	s_waitcnt vmcnt(2)
	v_mul_f32_e32 v34, v35, v40
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v38, v38, v41
	v_fmac_f32_e32 v36, s4, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f64_f32_e32 v[34:35], v34
	v_cvt_f64_f32_e32 v[38:39], v38
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f64_f32_e32 v[36:37], v36
	v_mul_f64 v[34:35], v[34:35], 0.5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[38:39], v[38:39], 0.5
	v_fma_f64 v[32:33], v[32:33], v[0:1], v[36:37]
	v_add_f32_e32 v36, v30, v31
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v36, v36, v42
	v_cvt_f64_f32_e32 v[36:37], v36
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[32:33], v[34:35], v[0:1], v[32:33]
	v_mul_f64 v[34:35], v[36:37], 0.5
	v_sub_f32_e32 v36, 1.0, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v22, v22, v36
	v_mul_f32_e32 v22, s5, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[36:37], v22
	v_sub_f32_e32 v22, 1.0, v29
	v_mul_f32_e32 v22, v24, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v22, s5, v22
	v_fma_f64 v[32:33], v[38:39], v[0:1], v[32:33]
	v_fma_f64 v[32:33], v[34:35], v[0:1], v[32:33]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[34:35], v22
	v_sub_f32_e32 v22, 1.0, v30
	v_mul_f32_e32 v22, v25, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v22, s5, v22
	v_cvt_f64_f32_e32 v[24:25], v22
	v_sub_f32_e32 v22, 1.0, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v22, v27, v22
	v_mul_f32_e32 v27, s5, v22
	v_add_f64 v[32:33], v[32:33], v[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[32:33], v[32:33], v[34:35]
	v_sub_f32_e32 v34, 2.0, v28
	v_sub_f32_e32 v28, v34, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v23, v28, v23
	v_cvt_f64_f32_e32 v[27:28], v27
	v_cvt_f64_f32_e32 v[22:23], v23
	v_add_f64 v[24:25], v[32:33], v[24:25]
	v_sub_f32_e32 v32, v34, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v32, v32, v40
	v_cvt_f64_f32_e32 v[32:33], v32
	v_mul_f64 v[22:23], v[22:23], 0.5
	v_add_f64 v[24:25], v[24:25], v[27:28]
	v_sub_f32_e32 v27, 2.0, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v27, v27, v31
	v_mul_f32_e32 v27, v27, v41
	v_mul_f64 v[32:33], v[32:33], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[27:28], v27
	v_fma_f64 v[22:23], v[22:23], v[2:3], v[24:25]
	v_sub_f32_e32 v24, 2.0, v30
	v_sub_f32_e32 v24, v24, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v24, v26
	v_cvt_f64_f32_e32 v[24:25], v24
	v_mul_f64 v[26:27], v[27:28], 0.5
	v_fma_f64 v[22:23], v[32:33], v[2:3], v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[24:25], v[24:25], 0.5
	v_fma_f64 v[22:23], v[26:27], v[2:3], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[24:25], v[2:3], v[22:23]
	v_cvt_f32_f64_e32 v24, v[22:23]
	v_add_co_u32 v22, s0, v19, s10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v23, s0, s11, v20, s0
	s_add_u32 s10, s10, s6
	s_addc_u32 s11, s11, s7
	s_or_b32 s22, s1, s22
	global_store_b32 v[22:23], v24, off
	s_and_not1_b32 exec_lo, exec_lo, s22
	s_cbranch_execnz .LBB0_4
.LBB0_5:                                ; %Flow264
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	v_add_nc_u32_e32 v9, s13, v9
	v_add_nc_u32_e32 v5, s15, v5
	v_add_nc_u32_e32 v7, s15, v7
	v_add_nc_u32_e32 v12, s15, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_i32_e64 s0, s12, v9
	s_or_b32 s20, s0, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s20
	s_cbranch_execnz .LBB0_2
.LBB0_6:                                ; %Flow266
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10_mask_convffffiPfS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 43
		.amdhsa_next_free_sgpr 23
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10_mask_convffffiPfS_S_, .Lfunc_end0-_Z10_mask_convffffiPfS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1208
; NumSgprs: 25
; NumVgprs: 43
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 25
; NumVGPRsForWavesPerEU: 43
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10_mask_convffffiPfS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     25
    .sgpr_spill_count: 0
    .symbol:         _Z10_mask_convffffiPfS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     43
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
