#include <cuda_runtime.h>
#include <cufft.h>

__global__ void unpack_data_dual_channel(const unsigned char* const raw_data, cufftReal* const chan_a, cufftReal* const chan_b, const size_t num_bytes) {
	const size_t idx = blockIdx.x * blockDim.x + threadIdx.x;

	// Make sure we are at the start of a new sample (every 3 bytes is a sample
	// from each channel) and that we are not at the end of our data
	if (idx % 3 != 0 || idx + 2 >= num_bytes) {
		return;
	}

	// The data is stored in three bytes on the card
	const unsigned char b0 = raw_data[idx + 0];
	const unsigned char b1 = raw_data[idx + 1];
	const unsigned char b2 = raw_data[idx + 2];

	// The data from the card is stored in little endian:
	// Data on card: AB CD EF
	// Var name:     b0 b1 b2
	// Channel A:    0D AB
	// Channel B:    0E FC
	const unsigned int a_data = ((b1 & 0x0F) << 8) | b0;
	const unsigned int b_data = ((b2 << 8) | (b1 & 0xF0)) >> 4;

	// We also want to convert it to a float (a cufftReal type)
	// TODO: Pass the value of 400 mV to this function
	chan_a[(idx / 3)] = ((static_cast<float>(a_data) / 4096.f) - 0.5f) * 2.f * 0.400f; // 400 mV
	chan_b[(idx / 3)] = ((static_cast<float>(b_data) / 4096.f) - 0.5f) * 2.f * 0.400f; // 400 mV
}


__global__ void unpack_data_single_channel(const unsigned char* const raw_data, cufftReal* const chan, const size_t num_bytes) {
	const size_t idx = blockIdx.x * blockDim.x + threadIdx.x;

	// Make sure we are at the start of a new sample (every 3 bytes is a sample
	// from each channel) and that we are not at the end of our data
	if (idx % 3 != 0 || idx + 2 >= num_bytes) {
		return;
	}

	// The data is stored in three bytes on the card
	const unsigned char b0 = raw_data[idx + 0];
	const unsigned char b1 = raw_data[idx + 1];
	const unsigned char b2 = raw_data[idx + 2];

	// The data from the card is stored in little endian:
	// Data on card: AB CD EF
	// Var name:     b0 b1 b2
	// Channel A:    0D AB
	// Channel B:    0E FC
	const unsigned int a_data = ((b1 & 0x0F) << 8) | b0;
	const unsigned int b_data = ((b2 << 8) | (b1 & 0xF0)) >> 4;

	// We also want to convert it to a float (a cufftReal type)
	// TODO: Pass the value of 400 mV to this function
	chan[(idx / 3)] = ((static_cast<float>(a_data) / 4096.f) - 0.5f) * 2.f * 0.400f; // 400 mV
	chan[(idx / 3) + 1] = ((static_cast<float>(b_data) / 4096.f) - 0.5f) * 2.f * 0.400f; // 400 mV
}

void gpu_unpack_data_dual_channel(const unsigned char* const raw_data, cufftReal* const chan_a, cufftReal* const chan_b, const size_t num_bytes, const cudaStream_t stream) {
	constexpr const unsigned threads_per_block = 1024; // Max size afforded by the GTX Quadro 4000
	const unsigned num_blocks = static_cast<unsigned>(ceil(static_cast<double>(num_bytes) / static_cast<double>(threads_per_block)));

	unpack_data_dual_channel<<<num_blocks, threads_per_block, 0, stream>>>(raw_data, chan_a, chan_b, num_bytes);
}

void gpu_unpack_data_single_channel(const unsigned char* const raw_data, cufftReal* const chan, const size_t num_bytes, const cudaStream_t stream) {
	constexpr const unsigned threads_per_block = 1024; // Max size afforded by the GTX Quadro 4000
	const unsigned num_blocks = static_cast<unsigned>(ceil(static_cast<double>(num_bytes) / static_cast<double>(threads_per_block)));

	unpack_data_single_channel<<<num_blocks, threads_per_block, 0, stream>>>(raw_data, chan, num_bytes);
}
	.file	"tmpxft_002e6e73_00000000-6_UnpackKernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2035:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z51__device_stub__Z24unpack_data_dual_channelPKhPfS1_mPKhPfS1_m
	.type	_Z51__device_stub__Z24unpack_data_dual_channelPKhPfS1_mPKhPfS1_m, @function
_Z51__device_stub__Z24unpack_data_dual_channelPKhPfS1_mPKhPfS1_m:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z24unpack_data_dual_channelPKhPfS1_m(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z51__device_stub__Z24unpack_data_dual_channelPKhPfS1_mPKhPfS1_m, .-_Z51__device_stub__Z24unpack_data_dual_channelPKhPfS1_mPKhPfS1_m
	.globl	_Z24unpack_data_dual_channelPKhPfS1_m
	.type	_Z24unpack_data_dual_channelPKhPfS1_m, @function
_Z24unpack_data_dual_channelPKhPfS1_m:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z51__device_stub__Z24unpack_data_dual_channelPKhPfS1_mPKhPfS1_m
	.cfi_endproc
.LFE2058:
	.size	_Z24unpack_data_dual_channelPKhPfS1_m, .-_Z24unpack_data_dual_channelPKhPfS1_m
	.globl	_Z28gpu_unpack_data_dual_channelPKhPfS1_mP11CUstream_st
	.type	_Z28gpu_unpack_data_dual_channelPKhPfS1_mP11CUstream_st, @function
_Z28gpu_unpack_data_dual_channelPKhPfS1_mP11CUstream_st:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movq	%r8, %r9
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rsi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movq	%rcx, %rbx
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	testq	%rcx, %rcx
	js	.L9
	cvtsi2sdq	%rcx, %xmm0
	jmp	.L10
.L9:
	movq	%rcx, %rax
	movq	%rcx, %rdx
	shrq	%rax
	andl	$1, %edx
	orq	%rdx, %rax
	cvtsi2sdq	%rax, %xmm0
	addsd	%xmm0, %xmm0
.L10:
	mulsd	.LC0(%rip), %xmm0
	movq	%r9, 8(%rsp)
	call	ceil@PLT
	movl	$4194305, %edx
	movq	8(%rsp), %r9
	xorl	%r8d, %r8d
	cvttsd2siq	%xmm0, %rax
	salq	$10, %rdx
	movl	$1, %ecx
	movl	%eax, 24(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 28(%rsp)
	movq	24(%rsp), %rdi
	movl	32(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movq	%rbx, %rcx
	movq	%r13, %rdx
	movq	%r12, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movq	%rbp, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_Z51__device_stub__Z24unpack_data_dual_channelPKhPfS1_mPKhPfS1_m
.L8:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2031:
	.size	_Z28gpu_unpack_data_dual_channelPKhPfS1_mP11CUstream_st, .-_Z28gpu_unpack_data_dual_channelPKhPfS1_mP11CUstream_st
	.globl	_Z50__device_stub__Z26unpack_data_single_channelPKhPfmPKhPfm
	.type	_Z50__device_stub__Z26unpack_data_single_channelPKhPfmPKhPfm, @function
_Z50__device_stub__Z26unpack_data_single_channelPKhPfmPKhPfm:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z26unpack_data_single_channelPKhPfm(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L13:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z50__device_stub__Z26unpack_data_single_channelPKhPfmPKhPfm, .-_Z50__device_stub__Z26unpack_data_single_channelPKhPfmPKhPfm
	.globl	_Z26unpack_data_single_channelPKhPfm
	.type	_Z26unpack_data_single_channelPKhPfm, @function
_Z26unpack_data_single_channelPKhPfm:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z26unpack_data_single_channelPKhPfmPKhPfm
	.cfi_endproc
.LFE2060:
	.size	_Z26unpack_data_single_channelPKhPfm, .-_Z26unpack_data_single_channelPKhPfm
	.globl	_Z30gpu_unpack_data_single_channelPKhPfmP11CUstream_st
	.type	_Z30gpu_unpack_data_single_channelPKhPfmP11CUstream_st, @function
_Z30gpu_unpack_data_single_channelPKhPfmP11CUstream_st:
.LFB2032:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movq	%rcx, %r9
	movq	%rsi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movq	%rdx, %rbx
	subq	$48, %rsp
	.cfi_def_cfa_offset 80
	testq	%rdx, %rdx
	js	.L19
	cvtsi2sdq	%rdx, %xmm0
	jmp	.L20
.L19:
	movq	%rdx, %rax
	andl	$1, %edx
	shrq	%rax
	orq	%rdx, %rax
	cvtsi2sdq	%rax, %xmm0
	addsd	%xmm0, %xmm0
.L20:
	mulsd	.LC0(%rip), %xmm0
	movq	%r9, 8(%rsp)
	call	ceil@PLT
	movl	$4194305, %edx
	movq	8(%rsp), %r9
	xorl	%r8d, %r8d
	cvttsd2siq	%xmm0, %rax
	salq	$10, %rdx
	movl	$1, %ecx
	movl	%eax, 24(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 28(%rsp)
	movq	24(%rsp), %rdi
	movl	32(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	addq	$48, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbx, %rdx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z50__device_stub__Z26unpack_data_single_channelPKhPfmPKhPfm
.L18:
	.cfi_restore_state
	addq	$48, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z30gpu_unpack_data_single_channelPKhPfmP11CUstream_st, .-_Z30gpu_unpack_data_single_channelPKhPfmP11CUstream_st
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"_Z26unpack_data_single_channelPKhPfm"
.LC2:
	.string	"_Z24unpack_data_dual_channelPKhPfS1_m"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z26unpack_data_single_channelPKhPfm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z24unpack_data_dual_channelPKhPfS1_m(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2062:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	0
	.long	1062207488
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>

__global__ void unpack_data_dual_channel(const unsigned char* const raw_data, hipfftReal* const chan_a, hipfftReal* const chan_b, const size_t num_bytes) {
	const size_t idx = blockIdx.x * blockDim.x + threadIdx.x;

	// Make sure we are at the start of a new sample (every 3 bytes is a sample
	// from each channel) and that we are not at the end of our data
	if (idx % 3 != 0 || idx + 2 >= num_bytes) {
		return;
	}

	// The data is stored in three bytes on the card
	const unsigned char b0 = raw_data[idx + 0];
	const unsigned char b1 = raw_data[idx + 1];
	const unsigned char b2 = raw_data[idx + 2];

	// The data from the card is stored in little endian:
	// Data on card: AB CD EF
	// Var name:     b0 b1 b2
	// Channel A:    0D AB
	// Channel B:    0E FC
	const unsigned int a_data = ((b1 & 0x0F) << 8) | b0;
	const unsigned int b_data = ((b2 << 8) | (b1 & 0xF0)) >> 4;

	// We also want to convert it to a float (a cufftReal type)
	// TODO: Pass the value of 400 mV to this function
	chan_a[(idx / 3)] = ((static_cast<float>(a_data) / 4096.f) - 0.5f) * 2.f * 0.400f; // 400 mV
	chan_b[(idx / 3)] = ((static_cast<float>(b_data) / 4096.f) - 0.5f) * 2.f * 0.400f; // 400 mV
}


__global__ void unpack_data_single_channel(const unsigned char* const raw_data, hipfftReal* const chan, const size_t num_bytes) {
	const size_t idx = blockIdx.x * blockDim.x + threadIdx.x;

	// Make sure we are at the start of a new sample (every 3 bytes is a sample
	// from each channel) and that we are not at the end of our data
	if (idx % 3 != 0 || idx + 2 >= num_bytes) {
		return;
	}

	// The data is stored in three bytes on the card
	const unsigned char b0 = raw_data[idx + 0];
	const unsigned char b1 = raw_data[idx + 1];
	const unsigned char b2 = raw_data[idx + 2];

	// The data from the card is stored in little endian:
	// Data on card: AB CD EF
	// Var name:     b0 b1 b2
	// Channel A:    0D AB
	// Channel B:    0E FC
	const unsigned int a_data = ((b1 & 0x0F) << 8) | b0;
	const unsigned int b_data = ((b2 << 8) | (b1 & 0xF0)) >> 4;

	// We also want to convert it to a float (a cufftReal type)
	// TODO: Pass the value of 400 mV to this function
	chan[(idx / 3)] = ((static_cast<float>(a_data) / 4096.f) - 0.5f) * 2.f * 0.400f; // 400 mV
	chan[(idx / 3) + 1] = ((static_cast<float>(b_data) / 4096.f) - 0.5f) * 2.f * 0.400f; // 400 mV
}

void gpu_unpack_data_dual_channel(const unsigned char* const raw_data, hipfftReal* const chan_a, hipfftReal* const chan_b, const size_t num_bytes, const hipStream_t stream) {
	constexpr const unsigned threads_per_block = 1024; // Max size afforded by the GTX Quadro 4000
	const unsigned num_blocks = static_cast<unsigned>(ceil(static_cast<double>(num_bytes) / static_cast<double>(threads_per_block)));

	unpack_data_dual_channel<<<num_blocks, threads_per_block, 0, stream>>>(raw_data, chan_a, chan_b, num_bytes);
}

void gpu_unpack_data_single_channel(const unsigned char* const raw_data, hipfftReal* const chan, const size_t num_bytes, const hipStream_t stream) {
	constexpr const unsigned threads_per_block = 1024; // Max size afforded by the GTX Quadro 4000
	const unsigned num_blocks = static_cast<unsigned>(ceil(static_cast<double>(num_bytes) / static_cast<double>(threads_per_block)));

	unpack_data_single_channel<<<num_blocks, threads_per_block, 0, stream>>>(raw_data, chan, num_bytes);
}
	.text
	.file	"UnpackKernel.hip"
	.globl	_Z39__device_stub__unpack_data_dual_channelPKhPfS1_m # -- Begin function _Z39__device_stub__unpack_data_dual_channelPKhPfS1_m
	.type	_Z39__device_stub__unpack_data_dual_channelPKhPfS1_m,@function
_Z39__device_stub__unpack_data_dual_channelPKhPfS1_m: # @_Z39__device_stub__unpack_data_dual_channelPKhPfS1_m
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24unpack_data_dual_channelPKhPfS1_m, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z39__device_stub__unpack_data_dual_channelPKhPfS1_m, .Lfunc_end0-_Z39__device_stub__unpack_data_dual_channelPKhPfS1_m
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__unpack_data_single_channelPKhPfm # -- Begin function _Z41__device_stub__unpack_data_single_channelPKhPfm
	.type	_Z41__device_stub__unpack_data_single_channelPKhPfm,@function
_Z41__device_stub__unpack_data_single_channelPKhPfm: # @_Z41__device_stub__unpack_data_single_channelPKhPfm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26unpack_data_single_channelPKhPfm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z41__device_stub__unpack_data_single_channelPKhPfm, .Lfunc_end1-_Z41__device_stub__unpack_data_single_channelPKhPfm
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z28gpu_unpack_data_dual_channelPKhPfS1_mP12ihipStream_t
.LCPI2_0:
	.long	1127219200                      # 0x43300000
	.long	1160773632                      # 0x45300000
	.long	0                               # 0x0
	.long	0                               # 0x0
.LCPI2_1:
	.quad	0x4330000000000000              # double 4503599627370496
	.quad	0x4530000000000000              # double 1.9342813113834067E+25
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI2_2:
	.quad	0x3f50000000000000              # double 9.765625E-4
	.text
	.globl	_Z28gpu_unpack_data_dual_channelPKhPfS1_mP12ihipStream_t
	.type	_Z28gpu_unpack_data_dual_channelPKhPfS1_mP12ihipStream_t,@function
_Z28gpu_unpack_data_dual_channelPKhPfS1_mP12ihipStream_t: # @_Z28gpu_unpack_data_dual_channelPKhPfS1_mP12ihipStream_t
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%r8, %r13
	movq	%rcx, %rbx
	movq	%rdx, %r14
	movq	%rsi, %r15
	movq	%rcx, %xmm1
	punpckldq	.LCPI2_0(%rip), %xmm1   # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
	movq	%rdi, %r12
	subpd	.LCPI2_1(%rip), %xmm1
	movapd	%xmm1, %xmm0
	unpckhpd	%xmm1, %xmm0                    # xmm0 = xmm0[1],xmm1[1]
	addsd	%xmm1, %xmm0
	mulsd	.LCPI2_2(%rip), %xmm0
	callq	ceil@PLT
	cvttsd2si	%xmm0, %rax
	movl	%eax, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	movq	%r13, %r9
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB2_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB2_2:
	.cfi_def_cfa_offset 48
	movq	%r12, %rdi
	movq	%r15, %rsi
	movq	%r14, %rdx
	movq	%rbx, %rcx
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z39__device_stub__unpack_data_dual_channelPKhPfS1_m # TAILCALL
.Lfunc_end2:
	.size	_Z28gpu_unpack_data_dual_channelPKhPfS1_mP12ihipStream_t, .Lfunc_end2-_Z28gpu_unpack_data_dual_channelPKhPfS1_mP12ihipStream_t
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z30gpu_unpack_data_single_channelPKhPfmP12ihipStream_t
.LCPI3_0:
	.long	1127219200                      # 0x43300000
	.long	1160773632                      # 0x45300000
	.long	0                               # 0x0
	.long	0                               # 0x0
.LCPI3_1:
	.quad	0x4330000000000000              # double 4503599627370496
	.quad	0x4530000000000000              # double 1.9342813113834067E+25
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI3_2:
	.quad	0x3f50000000000000              # double 9.765625E-4
	.text
	.globl	_Z30gpu_unpack_data_single_channelPKhPfmP12ihipStream_t
	.type	_Z30gpu_unpack_data_single_channelPKhPfmP12ihipStream_t,@function
_Z30gpu_unpack_data_single_channelPKhPfmP12ihipStream_t: # @_Z30gpu_unpack_data_single_channelPKhPfmP12ihipStream_t
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rcx, %r12
	movq	%rdx, %rbx
	movq	%rsi, %r14
	movq	%rdx, %xmm1
	punpckldq	.LCPI3_0(%rip), %xmm1   # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
	movq	%rdi, %r15
	subpd	.LCPI3_1(%rip), %xmm1
	movapd	%xmm1, %xmm0
	unpckhpd	%xmm1, %xmm0                    # xmm0 = xmm0[1],xmm1[1]
	addsd	%xmm1, %xmm0
	mulsd	.LCPI3_2(%rip), %xmm0
	callq	ceil@PLT
	cvttsd2si	%xmm0, %rax
	movl	%eax, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	movq	%r12, %r9
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB3_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB3_2:
	.cfi_def_cfa_offset 48
	movq	%r15, %rdi
	movq	%r14, %rsi
	movq	%rbx, %rdx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z41__device_stub__unpack_data_single_channelPKhPfm # TAILCALL
.Lfunc_end3:
	.size	_Z30gpu_unpack_data_single_channelPKhPfmP12ihipStream_t, .Lfunc_end3-_Z30gpu_unpack_data_single_channelPKhPfmP12ihipStream_t
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24unpack_data_dual_channelPKhPfS1_m, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26unpack_data_single_channelPKhPfm, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z24unpack_data_dual_channelPKhPfS1_m,@object # @_Z24unpack_data_dual_channelPKhPfS1_m
	.section	.rodata,"a",@progbits
	.globl	_Z24unpack_data_dual_channelPKhPfS1_m
	.p2align	3, 0x0
_Z24unpack_data_dual_channelPKhPfS1_m:
	.quad	_Z39__device_stub__unpack_data_dual_channelPKhPfS1_m
	.size	_Z24unpack_data_dual_channelPKhPfS1_m, 8

	.type	_Z26unpack_data_single_channelPKhPfm,@object # @_Z26unpack_data_single_channelPKhPfm
	.globl	_Z26unpack_data_single_channelPKhPfm
	.p2align	3, 0x0
_Z26unpack_data_single_channelPKhPfm:
	.quad	_Z41__device_stub__unpack_data_single_channelPKhPfm
	.size	_Z26unpack_data_single_channelPKhPfm, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z24unpack_data_dual_channelPKhPfS1_m"
	.size	.L__unnamed_1, 38

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z26unpack_data_single_channelPKhPfm"
	.size	.L__unnamed_2, 37

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z39__device_stub__unpack_data_dual_channelPKhPfS1_m
	.addrsig_sym _Z41__device_stub__unpack_data_single_channelPKhPfm
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z24unpack_data_dual_channelPKhPfS1_m
	.addrsig_sym _Z26unpack_data_single_channelPKhPfm
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z24unpack_data_dual_channelPKhPfS1_m ; -- Begin function _Z24unpack_data_dual_channelPKhPfS1_m
	.globl	_Z24unpack_data_dual_channelPKhPfS1_m
	.p2align	8
	.type	_Z24unpack_data_dual_channelPKhPfS1_m,@function
_Z24unpack_data_dual_channelPKhPfS1_m:  ; @_Z24unpack_data_dual_channelPKhPfS1_m
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b256 s[4:11], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
	v_mul_hi_u32 v0, 0xaaaaaaab, v2
	v_add_co_u32 v3, s0, v2, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v4, null, 0, 0, s0
	v_cmp_gt_u64_e32 vcc_lo, s[10:11], v[3:4]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v0, 1, v0
	v_lshl_add_u32 v1, v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v2, v1
	v_cmp_eq_u32_e64 s0, 0, v1
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, vcc_lo
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_add_co_u32 v2, s0, s4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, null, s5, 0, s0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_clause 0x1
	global_load_u16 v4, v[2:3], off
	global_load_u8 v2, v[2:3], off offset:2
	s_waitcnt vmcnt(1)
	v_lshrrev_b32_e32 v3, 12, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_or_b32 v2, v2, 4, v3
	v_cvt_f32_u32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, 0x39800000, v2, -0.5
	v_dual_add_f32 v5, v2, v2 :: v_dual_and_b32 v4, 0xfff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cvt_f32_u32_e32 v3, v4
	v_add_co_u32 v2, vcc_lo, s6, v0
	v_mul_f32_e32 v5, 0x3ecccccd, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, 0x39800000, v3, -0.5
	v_add_f32_e32 v4, v3, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s8, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v4, 0x3ecccccd, v4
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[2:3], v4, off
	global_store_b32 v[0:1], v5, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24unpack_data_dual_channelPKhPfS1_m
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z24unpack_data_dual_channelPKhPfS1_m, .Lfunc_end0-_Z24unpack_data_dual_channelPKhPfS1_m
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 336
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z26unpack_data_single_channelPKhPfm ; -- Begin function _Z26unpack_data_single_channelPKhPfm
	.globl	_Z26unpack_data_single_channelPKhPfm
	.p2align	8
	.type	_Z26unpack_data_single_channelPKhPfm,@function
_Z26unpack_data_single_channelPKhPfm:   ; @_Z26unpack_data_single_channelPKhPfm
; %bb.0:
	s_load_b32 s2, s[0:1], 0x24
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
	s_load_b64 s[2:3], s[0:1], 0x10
	v_mul_hi_u32 v0, 0xaaaaaaab, v2
	v_add_co_u32 v3, s4, v2, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v4, null, 0, 0, s4
	v_lshrrev_b32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v1, v0, 1, v0
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v2, v1
	v_cmp_eq_u32_e64 s2, 0, v1
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, vcc_lo
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v3, null, s1, 0, s0
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_clause 0x1
	global_load_u16 v4, v[2:3], off
	global_load_u8 v2, v[2:3], off offset:2
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, 0xfff, v4
	v_lshrrev_b32_e32 v4, 12, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v3, v3
	s_waitcnt vmcnt(0)
	v_lshl_or_b32 v2, v2, 4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v3, 0x39800000, v3, -0.5
	v_cvt_f32_u32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v3, v3, v3
	v_fma_f32 v4, 0x39800000, v2, -0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v2, 0x3ecccccd, v3 :: v_dual_add_f32 v3, v4, v4
	v_mul_f32_e32 v3, 0x3ecccccd, v3
	global_store_b64 v[0:1], v[2:3], off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26unpack_data_single_channelPKhPfm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z26unpack_data_single_channelPKhPfm, .Lfunc_end1-_Z26unpack_data_single_channelPKhPfm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 328
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z24unpack_data_dual_channelPKhPfS1_m
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z24unpack_data_dual_channelPKhPfS1_m.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z26unpack_data_single_channelPKhPfm
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z26unpack_data_single_channelPKhPfm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
