#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "curand.h"
#include <stdio.h>

#define _USE_MATH_DEFINES
#include <math.h>
#include <iostream>

__device__ __host__ __inline__ float N(float x)
{
    return 0.5 + 0.5 * erf(x * M_SQRT1_2);
}

__device__ __host__ void price(float k, float s, float t, float r, float v, float *c, float *p)
{
    float srt = v * sqrtf(t);
    float d1 = (logf(s/k) + (r+0.5*v*v)*t) / srt;
    float d2 = d1 - srt;
    float kert = k * expf(-r * t);
    *c = N(d1)*s - N(d2)*kert;
    *p = kert - s + *c;
}

__global__ void price(float *k, float *s, float *t, float *r, float *v, float *c, float *p)
{
    int tid = threadIdx.x;
    price(k[tid], s[tid], t[tid], r[tid], v[tid], &c[tid], &p[tid]);
}

int main()
{
    const int count = 512;
    size_t size = count * sizeof(float);
    float *args[5];
    curandGenerator_t gen;
    curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_MTGP32);
    for (int i=0; i<5; ++i)
    {
        cudaMalloc(&args[i], size);
    }
    float *dc, *dp;
    //XXX: check cuda error
    cudaMalloc(&dc, size);
    cudaMalloc(&dp, size);
    //linear grid
    //It's a gather pattern, so the layout of the grid/block doesn't matter here.
    price<<<1, count>>> (args[0], args[1], args[2], args[3], args[4], dc, dp);
    cudaFree(dc);
    cudaFree(dp);
    float *hc = (float*)malloc(size);
    cudaMemcpy(hc, dc, size, cudaMemcpyDeviceToHost);

    for (int i=0; i<10; ++i)
    {
        std::cout << hc[i] << std::endl;
    }
    free(hc);

}
	.file	"tmpxft_0021903d_00000000-6_black_shoe.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3640:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3640:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z5pricefffffPfS_
	.type	_Z5pricefffffPfS_, @function
_Z5pricefffffPfS_:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movq	%rdi, %rbx
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	movss	%xmm0, 8(%rsp)
	movaps	%xmm2, %xmm0
	movss	%xmm1, 4(%rsp)
	movss	%xmm3, 28(%rsp)
	movss	%xmm4, 20(%rsp)
	movss	%xmm2, 24(%rsp)
	call	sqrtf@PLT
	mulss	20(%rsp), %xmm0
	movss	%xmm0, 16(%rsp)
	movss	4(%rsp), %xmm0
	divss	8(%rsp), %xmm0
	call	logf@PLT
	movsd	.LC0(%rip), %xmm4
	cvtss2sd	20(%rsp), %xmm5
	movaps	%xmm5, %xmm1
	movss	28(%rsp), %xmm3
	movss	24(%rsp), %xmm2
	cvtss2sd	%xmm0, %xmm0
	mulsd	%xmm4, %xmm1
	mulsd	%xmm5, %xmm1
	cvtss2sd	%xmm3, %xmm5
	xorps	.LC1(%rip), %xmm3
	mulss	%xmm2, %xmm3
	addsd	%xmm5, %xmm1
	cvtss2sd	%xmm2, %xmm5
	mulsd	%xmm5, %xmm1
	addsd	%xmm0, %xmm1
	cvtss2sd	16(%rsp), %xmm0
	divsd	%xmm0, %xmm1
	movaps	%xmm3, %xmm0
	cvtsd2ss	%xmm1, %xmm6
	movd	%xmm6, %r14d
	call	expf@PLT
	movss	8(%rsp), %xmm2
	movd	%r14d, %xmm6
	mulss	%xmm0, %xmm2
	cvtss2sd	%xmm6, %xmm0
	mulsd	.LC2(%rip), %xmm0
	movss	%xmm2, 20(%rsp)
	call	erf@PLT
	movsd	%xmm0, 8(%rsp)
	movd	%r14d, %xmm0
	subss	16(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	mulsd	.LC2(%rip), %xmm0
	call	erf@PLT
	movsd	.LC0(%rip), %xmm4
	movsd	8(%rsp), %xmm1
	movss	20(%rsp), %xmm2
	mulsd	%xmm4, %xmm1
	mulsd	%xmm4, %xmm0
	addsd	%xmm4, %xmm1
	addsd	%xmm4, %xmm0
	cvtsd2ss	%xmm1, %xmm1
	mulss	4(%rsp), %xmm1
	cvtsd2ss	%xmm0, %xmm0
	mulss	%xmm2, %xmm0
	subss	4(%rsp), %xmm2
	subss	%xmm0, %xmm1
	addss	%xmm1, %xmm2
	movss	%xmm1, (%rbx)
	movss	%xmm2, 0(%rbp)
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	_Z5pricefffffPfS_, .-_Z5pricefffffPfS_
	.globl	_Z36__device_stub__Z5pricePfS_S_S_S_S_S_PfS_S_S_S_S_S_
	.type	_Z36__device_stub__Z5pricePfS_S_S_S_S_S_PfS_S_S_S_S_S_, @function
_Z36__device_stub__Z5pricePfS_S_S_S_S_S_PfS_S_S_S_S_S_:
.LFB3662:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	72(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z5pricePfS_S_S_S_S_S_(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 224
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L4:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3662:
	.size	_Z36__device_stub__Z5pricePfS_S_S_S_S_S_PfS_S_S_S_S_S_, .-_Z36__device_stub__Z5pricePfS_S_S_S_S_S_PfS_S_S_S_S_S_
	.globl	_Z5pricePfS_S_S_S_S_S_
	.type	_Z5pricePfS_S_S_S_S_S_, @function
_Z5pricePfS_S_S_S_S_S_:
.LFB3663:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z5pricePfS_S_S_S_S_S_PfS_S_S_S_S_S_
	.cfi_endproc
.LFE3663:
	.size	_Z5pricePfS_S_S_S_S_S_, .-_Z5pricePfS_S_S_S_S_S_
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3637:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$141, %esi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$96, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	leaq	48(%rsp), %rbx
	leaq	88(%rsp), %rbp
	call	curandCreateGenerator@PLT
.L11:
	movq	%rbx, %rdi
	movl	$2048, %esi
	addq	$8, %rbx
	call	cudaMalloc@PLT
	cmpq	%rbp, %rbx
	jne	.L11
	leaq	8(%rsp), %rdi
	movl	$2048, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$2048, %esi
	call	cudaMalloc@PLT
	movl	$8388609, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$9, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	%rax
	.cfi_def_cfa_offset 136
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	24(%rsp), %r9
	movq	96(%rsp), %r8
	movq	88(%rsp), %rcx
	movq	80(%rsp), %rdx
	movq	72(%rsp), %rsi
	movq	64(%rsp), %rdi
	call	_Z36__device_stub__Z5pricePfS_S_S_S_S_S_PfS_S_S_S_S_S_
	popq	%rdx
	.cfi_def_cfa_offset 136
	popq	%rcx
	.cfi_def_cfa_offset 128
.L12:
	movq	8(%rsp), %rdi
	xorl	%ebp, %ebp
	leaq	_ZSt4cout(%rip), %r12
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movl	$2048, %edi
	call	malloc@PLT
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movl	$2048, %edx
	movq	%rax, %rdi
	movq	%rax, %rbx
	call	cudaMemcpy@PLT
.L13:
	movq	%r12, %rdi
	cvtss2sd	(%rbx,%rbp,4), %xmm0
	incq	%rbp
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	cmpq	$10, %rbp
	jne	.L13
	movq	%rbx, %rdi
	call	free@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$96, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3637:
	.size	main, .-main
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC3:
	.string	"_Z5pricePfS_S_S_S_S_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3665:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z5pricePfS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3665:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	0
	.long	1071644672
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC1:
	.long	-2147483648
	.long	0
	.long	0
	.long	0
	.section	.rodata.cst8
	.align 8
.LC2:
	.long	1719614413
	.long	1072079006
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include "hip/hip_runtime.h"

#include "hiprand/hiprand.h"
#include <stdio.h>

#define _USE_MATH_DEFINES
#include <math.h>
#include <iostream>

__device__ __host__ __inline__ float N(float x)
{
    return 0.5 + 0.5 * erf(x * M_SQRT1_2);
}

__device__ __host__ void price(float k, float s, float t, float r, float v, float *c, float *p)
{
    float srt = v * sqrtf(t);
    float d1 = (logf(s/k) + (r+0.5*v*v)*t) / srt;
    float d2 = d1 - srt;
    float kert = k * expf(-r * t);
    *c = N(d1)*s - N(d2)*kert;
    *p = kert - s + *c;
}

__global__ void price(float *k, float *s, float *t, float *r, float *v, float *c, float *p)
{
    int tid = threadIdx.x;
    price(k[tid], s[tid], t[tid], r[tid], v[tid], &c[tid], &p[tid]);
}

int main()
{
    const int count = 512;
    size_t size = count * sizeof(float);
    float *args[5];
    hiprandGenerator_t gen;
    hiprandCreateGenerator(&gen, HIPRAND_RNG_PSEUDO_MTGP32);
    for (int i=0; i<5; ++i)
    {
        hipMalloc(&args[i], size);
    }
    float *dc, *dp;
    //XXX: check cuda error
    hipMalloc(&dc, size);
    hipMalloc(&dp, size);
    //linear grid
    //It's a gather pattern, so the layout of the grid/block doesn't matter here.
    price<<<1, count>>> (args[0], args[1], args[2], args[3], args[4], dc, dp);
    hipFree(dc);
    hipFree(dp);
    float *hc = (float*)malloc(size);
    hipMemcpy(hc, dc, size, hipMemcpyDeviceToHost);

    for (int i=0; i<10; ++i)
    {
        std::cout << hc[i] << std::endl;
    }
    free(hc);

}
	.text
	.file	"black_shoe.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z5pricefffffPfS_
.LCPI0_0:
	.quad	0x3fe0000000000000              # double 0.5
.LCPI0_2:
	.quad	0x3fe6a09e667f3bcd              # double 0.70710678118654757
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0
.LCPI0_1:
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.text
	.globl	_Z5pricefffffPfS_
	.type	_Z5pricefffffPfS_,@function
_Z5pricefffffPfS_:                      # @_Z5pricefffffPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$56, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	%rsi, %rbx
	movq	%rdi, %r14
	movss	%xmm4, 8(%rsp)                  # 4-byte Spill
	movaps	%xmm3, 32(%rsp)                 # 16-byte Spill
	movss	%xmm1, 16(%rsp)                 # 4-byte Spill
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	xorps	%xmm0, %xmm0
	ucomiss	%xmm0, %xmm2
	movss	%xmm2, 28(%rsp)                 # 4-byte Spill
	jb	.LBB0_2
# %bb.1:
	xorps	%xmm0, %xmm0
	sqrtss	%xmm2, %xmm0
	jmp	.LBB0_3
.LBB0_2:                                # %call.sqrt
	movaps	%xmm2, %xmm0
	callq	sqrtf
.LBB0_3:                                # %.split
	mulss	8(%rsp), %xmm0                  # 4-byte Folded Reload
	movss	%xmm0, 24(%rsp)                 # 4-byte Spill
	movss	16(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	divss	12(%rsp), %xmm0                 # 4-byte Folded Reload
	callq	logf
	xorps	%xmm4, %xmm4
	cvtss2sd	%xmm0, %xmm4
	movaps	32(%rsp), %xmm0                 # 16-byte Reload
	xorps	%xmm1, %xmm1
	cvtss2sd	%xmm0, %xmm1
	xorps	%xmm2, %xmm2
	cvtss2sd	8(%rsp), %xmm2                  # 4-byte Folded Reload
	movaps	%xmm2, %xmm3
	mulsd	.LCPI0_0(%rip), %xmm3
	mulsd	%xmm2, %xmm3
	addsd	%xmm1, %xmm3
	movss	28(%rsp), %xmm5                 # 4-byte Reload
                                        # xmm5 = mem[0],zero,zero,zero
	xorps	%xmm1, %xmm1
	cvtss2sd	%xmm5, %xmm1
	mulsd	%xmm3, %xmm1
	addsd	%xmm4, %xmm1
	movss	24(%rsp), %xmm3                 # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	xorps	%xmm2, %xmm2
	cvtss2sd	%xmm3, %xmm2
	divsd	%xmm2, %xmm1
	cvtsd2ss	%xmm1, %xmm1
	movss	%xmm1, 20(%rsp)                 # 4-byte Spill
	subss	%xmm3, %xmm1
	movss	%xmm1, 8(%rsp)                  # 4-byte Spill
	xorps	.LCPI0_1(%rip), %xmm0
	mulss	%xmm5, %xmm0
	callq	expf
	mulss	12(%rsp), %xmm0                 # 4-byte Folded Reload
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	xorps	%xmm0, %xmm0
	cvtss2sd	20(%rsp), %xmm0                 # 4-byte Folded Reload
	mulsd	.LCPI0_2(%rip), %xmm0
	callq	erf
	movsd	.LCPI0_0(%rip), %xmm1           # xmm1 = mem[0],zero
	mulsd	%xmm1, %xmm0
	addsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	mulss	16(%rsp), %xmm0                 # 4-byte Folded Reload
	movss	%xmm0, 32(%rsp)                 # 4-byte Spill
	xorps	%xmm0, %xmm0
	cvtss2sd	8(%rsp), %xmm0                  # 4-byte Folded Reload
	mulsd	.LCPI0_2(%rip), %xmm0
	callq	erf
	movsd	.LCPI0_0(%rip), %xmm1           # xmm1 = mem[0],zero
	mulsd	%xmm1, %xmm0
	addsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	12(%rsp), %xmm1                 # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	mulss	%xmm1, %xmm0
	movss	32(%rsp), %xmm2                 # 4-byte Reload
                                        # xmm2 = mem[0],zero,zero,zero
	subss	%xmm0, %xmm2
	movss	%xmm2, (%r14)
	subss	16(%rsp), %xmm1                 # 4-byte Folded Reload
	addss	%xmm2, %xmm1
	movss	%xmm1, (%rbx)
	addq	$56, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z5pricefffffPfS_, .Lfunc_end0-_Z5pricefffffPfS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z20__device_stub__pricePfS_S_S_S_S_S_ # -- Begin function _Z20__device_stub__pricePfS_S_S_S_S_S_
	.type	_Z20__device_stub__pricePfS_S_S_S_S_S_,@function
_Z20__device_stub__pricePfS_S_S_S_S_S_: # @_Z20__device_stub__pricePfS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5pricePfS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z20__device_stub__pricePfS_S_S_S_S_S_, .Lfunc_end1-_Z20__device_stub__pricePfS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$80, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rdi
	movl	$403, %esi                      # imm = 0x193
	callq	hiprandCreateGenerator
	xorl	%ebx, %ebx
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	leaq	(%rsp,%rbx), %rdi
	addq	$32, %rdi
	movl	$2048, %esi                     # imm = 0x800
	callq	hipMalloc
	addq	$8, %rbx
	cmpq	$40, %rbx
	jne	.LBB2_1
# %bb.2:
	leaq	16(%rsp), %rdi
	movl	$2048, %esi                     # imm = 0x800
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$2048, %esi                     # imm = 0x800
	callq	hipMalloc
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	511(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_4
# %bb.3:
	movq	32(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	48(%rsp), %rdx
	movq	56(%rsp), %rcx
	movq	64(%rsp), %r8
	movq	16(%rsp), %r9
	movq	24(%rsp), %rax
	movq	%rax, (%rsp)
	callq	_Z20__device_stub__pricePfS_S_S_S_S_S_
.LBB2_4:
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movl	$2048, %edi                     # imm = 0x800
	callq	malloc
	movq	%rax, %rbx
	movq	16(%rsp), %rsi
	movl	$2048, %edx                     # imm = 0x800
	movq	%rax, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%r15d, %r15d
.LBB2_5:                                # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx,%r15,4), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r14
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	incq	%r15
	cmpq	$10, %r15
	jne	.LBB2_5
# %bb.6:
	movq	%rbx, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$80, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5pricePfS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z5pricePfS_S_S_S_S_S_,@object  # @_Z5pricePfS_S_S_S_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z5pricePfS_S_S_S_S_S_
	.p2align	3, 0x0
_Z5pricePfS_S_S_S_S_S_:
	.quad	_Z20__device_stub__pricePfS_S_S_S_S_S_
	.size	_Z5pricePfS_S_S_S_S_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z5pricePfS_S_S_S_S_S_"
	.size	.L__unnamed_1, 23

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__pricePfS_S_S_S_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z5pricePfS_S_S_S_S_S_
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z5pricePfS_S_S_S_S_S_  ; -- Begin function _Z5pricePfS_S_S_S_S_S_
	.globl	_Z5pricePfS_S_S_S_S_S_
	.p2align	8
	.type	_Z5pricePfS_S_S_S_S_S_,@function
_Z5pricePfS_S_S_S_S_S_:                 ; @_Z5pricePfS_S_S_S_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_lshlrev_b32_e32 v8, 2, v0
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b32 v9, v8, s[4:5]
	global_load_b32 v10, v8, s[6:7]
	s_load_b128 s[4:7], s[0:1], 0x20
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v2, null, v9, v9, v10
	v_div_scale_f32 v4, vcc_lo, v10, v9, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v0, -v2, v3, 1.0
	v_fmac_f32_e32 v3, v0, v3
	s_waitcnt lgkmcnt(0)
	s_clause 0x2
	global_load_b32 v13, v8, s[4:5]
	global_load_b32 v11, v8, s[10:11]
	global_load_b32 v12, v8, s[8:9]
	v_mul_f32_e32 v5, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, -v2, v5, v4
	v_fmac_f32_e32 v5, v6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v2, v5, v4
	v_div_fmas_f32 v2, v2, v3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v2, v2, v9, v10
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v2
	v_cndmask_b32_e64 v3, 1.0, 0x4f800000, vcc_lo
	v_cndmask_b32_e64 v16, 0, 0x41b17218, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v2, v3
	v_log_f32_e32 v6, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v7, 0x3f317217, v6
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v6|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, 0x3f317217, v6, -v7
	v_fmamk_f32 v14, v6, 0x3377d1cf, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v7, v14
	v_cndmask_b32_e32 v6, v6, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_f32_e32 v16, v6, v16
	s_waitcnt vmcnt(2)
	v_cvt_f64_f32_e32 v[0:1], v13
	s_waitcnt vmcnt(1)
	v_cvt_f64_f32_e32 v[2:3], v11
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v15, 0x4f800000, v12
	v_cmp_gt_f32_e64 s2, 0xf800000, v12
	v_cvt_f64_f32_e32 v[6:7], v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v15, v12, v15, s2
	v_sqrt_f32_e32 v14, v15
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v17, -1, v14
	v_add_nc_u32_e32 v18, 1, v14
	v_mul_f64 v[4:5], v[0:1], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[0:1], v[4:5], v[0:1], v[2:3]
	v_fma_f32 v4, -v17, v14, v15
	v_cvt_f64_f32_e32 v[2:3], v16
	v_fma_f32 v5, -v18, v14, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_ge_f32_e32 vcc_lo, 0, v4
	v_cndmask_b32_e32 v4, v14, v17, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, 0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, v4, v18, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v15, 0x260
	v_mul_f32_e32 v5, 0x37800000, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v4, v4, v5, s2
	s_mov_b32 s2, 0x667f3bcd
	s_mov_b32 s3, 0x3fe6a09e
	v_cndmask_b32_e32 v4, v4, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v4, v4, v13
	v_fma_f64 v[0:1], v[0:1], v[6:7], v[2:3]
	v_cvt_f64_f32_e32 v[13:14], v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[2:3], null, v[13:14], v[13:14], v[0:1]
	v_rcp_f64_e32 v[5:6], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[15:16], -v[2:3], v[5:6], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], v[15:16], v[5:6]
	v_fma_f64 v[15:16], -v[2:3], v[5:6], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], v[15:16], v[5:6]
	v_div_scale_f64 v[15:16], vcc_lo, v[0:1], v[13:14], v[0:1]
	v_mul_f64 v[17:18], v[15:16], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], -v[2:3], v[17:18], v[15:16]
	v_div_fmas_f64 v[2:3], v[2:3], v[5:6], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[2:3], v[13:14], v[0:1]
                                        ; implicit-def: $vgpr2_vgpr3
	v_cvt_f32_f64_e32 v5, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[0:1], v5
	v_mul_f64 v[0:1], v[0:1], s[2:3]
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_nlt_f64_e64 |v[0:1]|, 1.0
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_mov_b32 s4, 0x502a41cd
	s_mov_b32 s8, 0xc14b24be
	s_mov_b32 s5, 0xbcc145a3
	s_mov_b32 s9, 0x3c598d37
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], |v[0:1]|, s[8:9], s[4:5]
	s_mov_b32 s4, 0xd735f9ec
	s_mov_b32 s5, 0x3d162dee
	s_mov_b32 s8, 0x6a5dcb37
	s_mov_b32 s9, 0x3e5ade15
	v_fma_f64 v[2:3], |v[0:1]|, v[2:3], s[4:5]
	s_mov_b32 s4, 0x5552ca22
	s_mov_b32 s5, 0xbd61ffe5
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], |v[0:1]|, v[2:3], s[4:5]
	s_mov_b32 s4, 0x7074b644
	s_mov_b32 s5, 0x3da4b9ba
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], |v[0:1]|, v[2:3], s[4:5]
	s_mov_b32 s4, 0xa78ce240
	s_mov_b32 s5, 0xbde20345
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], |v[0:1]|, v[2:3], s[4:5]
	s_mov_b32 s4, 0xcefddd8
	s_mov_b32 s5, 0x3e188b7a
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], |v[0:1]|, v[2:3], s[4:5]
	s_mov_b32 s4, 0x8c94b617
	s_mov_b32 s5, 0xbe4aded4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], |v[0:1]|, v[2:3], s[4:5]
	s_mov_b32 s4, 0x312306d0
	s_mov_b32 s5, 0x3e7803aa
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], |v[0:1]|, v[2:3], s[4:5]
	s_mov_b32 s4, 0x6f4c5a9b
	s_mov_b32 s5, 0xbea1b010
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], |v[0:1]|, v[2:3], s[4:5]
	s_mov_b32 s4, 0x7cfd79ae
	s_mov_b32 s5, 0x3ec58c0e
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], |v[0:1]|, v[2:3], s[4:5]
	s_mov_b32 s4, 0x6410fdf7
	s_mov_b32 s5, 0xbee59e38
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], |v[0:1]|, v[2:3], s[4:5]
	s_mov_b32 s4, 0x1f9b1786
	s_mov_b32 s5, 0x3f0192fc
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], |v[0:1]|, v[2:3], s[4:5]
	s_mov_b32 s4, 0xf4634b2e
	s_mov_b32 s5, 0xbf162cf3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], |v[0:1]|, v[2:3], s[4:5]
	s_mov_b32 s4, 0xb42f7e4b
	s_mov_b32 s5, 0x3f2314df
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], |v[0:1]|, v[2:3], s[4:5]
	s_mov_b32 s4, 0xc047288a
	s_mov_b32 s5, 0xbf12cb68
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], |v[0:1]|, v[2:3], s[4:5]
	s_mov_b32 s4, 0x7bbcce25
	s_mov_b32 s5, 0xbf4038ff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], |v[0:1]|, v[2:3], s[4:5]
	s_mov_b32 s4, 0xae1babae
	s_mov_b32 s5, 0x3f5a9466
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], |v[0:1]|, v[2:3], s[4:5]
	s_mov_b32 s4, 0xe65a6063
	s_mov_b32 s5, 0xbf258be1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], |v[0:1]|, v[2:3], s[4:5]
	s_mov_b32 s4, 0x6738ee3a
	s_mov_b32 s5, 0xbf939bc1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], |v[0:1]|, v[2:3], s[4:5]
	s_mov_b32 s4, 0x28146b69
	s_mov_b32 s5, 0x3fba4fbc
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], |v[0:1]|, v[2:3], s[4:5]
	s_mov_b32 s4, 0xa69750c4
	s_mov_b32 s5, 0x3fe45f2d
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], |v[0:1]|, v[2:3], s[4:5]
	s_mov_b32 s4, 0x919fcca8
	s_mov_b32 s5, 0x3fc06ebb
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], |v[0:1]|, v[2:3], s[4:5]
	s_mov_b32 s4, 0x652b82fe
	s_mov_b32 s5, 0xbff71547
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], |v[0:1]|, v[2:3], |v[0:1]|
	v_mul_f64 v[6:7], v[2:3], s[4:5]
	s_mov_b32 s4, 0xfefa39ef
	s_mov_b32 s5, 0xbfe62e42
	v_cmp_ngt_f64_e32 vcc_lo, 0xc0900000, v[2:3]
	v_cmp_nlt_f64_e64 s2, 0x4090cc00, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[6:7], v[6:7]
	v_fma_f64 v[13:14], v[6:7], s[4:5], -v[2:3]
	s_mov_b32 s4, 0x3b39803f
	s_mov_b32 s5, 0xbc7abc9e
	v_cvt_i32_f64_e32 v17, v[6:7]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[13:14], v[6:7], s[4:5], v[13:14]
	s_mov_b32 s4, 0xfca7ab0c
	s_mov_b32 s5, 0x3e928af3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], s[8:9], s[4:5]
	s_mov_b32 s4, 0x623fde64
	s_mov_b32 s5, 0x3ec71dee
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[4:5]
	s_mov_b32 s4, 0x7c89e6b0
	s_mov_b32 s5, 0x3efa0199
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[4:5]
	s_mov_b32 s4, 0x14761f6e
	s_mov_b32 s5, 0x3f2a01a0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[4:5]
	s_mov_b32 s4, 0x1852b7b0
	s_mov_b32 s5, 0x3f56c16c
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[4:5]
	s_mov_b32 s4, 0x11122322
	s_mov_b32 s5, 0x3f811111
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[4:5]
	s_mov_b32 s4, 0x555502a1
	s_mov_b32 s5, 0x3fa55555
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[4:5]
	s_mov_b32 s4, 0x55555511
	s_mov_b32 s5, 0x3fc55555
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[4:5]
	s_mov_b32 s4, 11
	s_mov_b32 s5, 0x3fe00000
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], 1.0
	v_fma_f64 v[6:7], v[13:14], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[6:7], v[6:7], v17
	v_add_f64 v[6:7], -v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v7, 0xfff00000, v7, vcc_lo
	s_and_b32 vcc_lo, s2, vcc_lo
	v_cndmask_b32_e32 v2, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v3, 0x3ff00000, v7, s2
.LBB0_2:                                ; %Flow40
	s_or_saveexec_b32 s2, s3
	s_load_b128 s[8:11], s[0:1], 0x30
	s_xor_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_4
; %bb.3:
	v_mul_f64 v[2:3], v[0:1], v[0:1]
	s_mov_b32 s0, 0xdfeb1f49
	s_mov_b32 s4, 0x51d2ebeb
	s_mov_b32 s1, 0x3e4d6e3d
	s_mov_b32 s5, 0xbe0ab15c
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], v[2:3], s[4:5], s[0:1]
	s_mov_b32 s0, 0x63844720
	s_mov_b32 s1, 0xbe85bfe7
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], v[2:3], v[6:7], s[0:1]
	s_mov_b32 s0, 0x4280cfb9
	s_mov_b32 s1, 0x3ebb97e4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], v[2:3], v[6:7], s[0:1]
	s_mov_b32 s0, 0x4c771c5
	s_mov_b32 s1, 0xbeef4ca2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], v[2:3], v[6:7], s[0:1]
	s_mov_b32 s0, 0x75531772
	s_mov_b32 s1, 0x3f1f9a2b
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], v[2:3], v[6:7], s[0:1]
	s_mov_b32 s0, 0x149d904
	s_mov_b32 s1, 0xbf4c02db
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], v[2:3], v[6:7], s[0:1]
	s_mov_b32 s0, 0xcf7e2856
	s_mov_b32 s1, 0x3f7565bc
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], v[2:3], v[6:7], s[0:1]
	s_mov_b32 s0, 0x311ee09b
	s_mov_b32 s1, 0xbf9b82ce
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], v[2:3], v[6:7], s[0:1]
	s_mov_b32 s0, 0x1a0408d1
	s_mov_b32 s1, 0x3fbce2f2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], v[2:3], v[6:7], s[0:1]
	s_mov_b32 s0, 0x6b0379b2
	s_mov_b32 s1, 0xbfd81274
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], v[2:3], v[6:7], s[0:1]
	s_mov_b32 s0, 0x8214db68
	s_mov_b32 s1, 0x3fc06eba
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], v[2:3], v[6:7], s[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[2:3], |v[0:1]|, v[2:3], |v[0:1]|
.LBB0_4:                                ; %_Z1Nf.exit.i
	s_or_b32 exec_lo, exec_lo, s2
	v_sub_f32_e32 v0, v5, v4
	s_mov_b32 s0, 0x667f3bcd
	s_mov_b32 s1, 0x3fe6a09e
                                        ; implicit-def: $vgpr6_vgpr7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[4:5], v0
	v_mul_f64 v[4:5], v[4:5], s[0:1]
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_nlt_f64_e64 |v[4:5]|, 1.0
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_6
; %bb.5:
	s_mov_b32 s2, 0x502a41cd
	s_mov_b32 s4, 0xc14b24be
	s_mov_b32 s3, 0xbcc145a3
	s_mov_b32 s5, 0x3c598d37
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], |v[4:5]|, s[4:5], s[2:3]
	s_mov_b32 s2, 0xd735f9ec
	s_mov_b32 s3, 0x3d162dee
	s_mov_b32 s4, 0x6a5dcb37
	s_mov_b32 s5, 0x3e5ade15
	v_fma_f64 v[6:7], |v[4:5]|, v[6:7], s[2:3]
	s_mov_b32 s2, 0x5552ca22
	s_mov_b32 s3, 0xbd61ffe5
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], |v[4:5]|, v[6:7], s[2:3]
	s_mov_b32 s2, 0x7074b644
	s_mov_b32 s3, 0x3da4b9ba
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], |v[4:5]|, v[6:7], s[2:3]
	s_mov_b32 s2, 0xa78ce240
	s_mov_b32 s3, 0xbde20345
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], |v[4:5]|, v[6:7], s[2:3]
	s_mov_b32 s2, 0xcefddd8
	s_mov_b32 s3, 0x3e188b7a
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], |v[4:5]|, v[6:7], s[2:3]
	s_mov_b32 s2, 0x8c94b617
	s_mov_b32 s3, 0xbe4aded4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], |v[4:5]|, v[6:7], s[2:3]
	s_mov_b32 s2, 0x312306d0
	s_mov_b32 s3, 0x3e7803aa
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], |v[4:5]|, v[6:7], s[2:3]
	s_mov_b32 s2, 0x6f4c5a9b
	s_mov_b32 s3, 0xbea1b010
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], |v[4:5]|, v[6:7], s[2:3]
	s_mov_b32 s2, 0x7cfd79ae
	s_mov_b32 s3, 0x3ec58c0e
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], |v[4:5]|, v[6:7], s[2:3]
	s_mov_b32 s2, 0x6410fdf7
	s_mov_b32 s3, 0xbee59e38
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], |v[4:5]|, v[6:7], s[2:3]
	s_mov_b32 s2, 0x1f9b1786
	s_mov_b32 s3, 0x3f0192fc
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], |v[4:5]|, v[6:7], s[2:3]
	s_mov_b32 s2, 0xf4634b2e
	s_mov_b32 s3, 0xbf162cf3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], |v[4:5]|, v[6:7], s[2:3]
	s_mov_b32 s2, 0xb42f7e4b
	s_mov_b32 s3, 0x3f2314df
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], |v[4:5]|, v[6:7], s[2:3]
	s_mov_b32 s2, 0xc047288a
	s_mov_b32 s3, 0xbf12cb68
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], |v[4:5]|, v[6:7], s[2:3]
	s_mov_b32 s2, 0x7bbcce25
	s_mov_b32 s3, 0xbf4038ff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], |v[4:5]|, v[6:7], s[2:3]
	s_mov_b32 s2, 0xae1babae
	s_mov_b32 s3, 0x3f5a9466
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], |v[4:5]|, v[6:7], s[2:3]
	s_mov_b32 s2, 0xe65a6063
	s_mov_b32 s3, 0xbf258be1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], |v[4:5]|, v[6:7], s[2:3]
	s_mov_b32 s2, 0x6738ee3a
	s_mov_b32 s3, 0xbf939bc1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], |v[4:5]|, v[6:7], s[2:3]
	s_mov_b32 s2, 0x28146b69
	s_mov_b32 s3, 0x3fba4fbc
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], |v[4:5]|, v[6:7], s[2:3]
	s_mov_b32 s2, 0xa69750c4
	s_mov_b32 s3, 0x3fe45f2d
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], |v[4:5]|, v[6:7], s[2:3]
	s_mov_b32 s2, 0x919fcca8
	s_mov_b32 s3, 0x3fc06ebb
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], |v[4:5]|, v[6:7], s[2:3]
	s_mov_b32 s2, 0x652b82fe
	s_mov_b32 s3, 0xbff71547
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], |v[4:5]|, v[6:7], |v[4:5]|
	v_mul_f64 v[13:14], v[6:7], s[2:3]
	s_mov_b32 s2, 0xfefa39ef
	s_mov_b32 s3, 0xbfe62e42
	v_cmp_ngt_f64_e32 vcc_lo, 0xc0900000, v[6:7]
	v_cmp_nlt_f64_e64 s0, 0x4090cc00, v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[13:14], v[13:14]
	v_fma_f64 v[15:16], v[13:14], s[2:3], -v[6:7]
	s_mov_b32 s2, 0x3b39803f
	s_mov_b32 s3, 0xbc7abc9e
	v_cvt_i32_f64_e32 v0, v[13:14]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[15:16], v[13:14], s[2:3], v[15:16]
	s_mov_b32 s2, 0xfca7ab0c
	s_mov_b32 s3, 0x3e928af3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[17:18], v[15:16], s[4:5], s[2:3]
	s_mov_b32 s2, 0x623fde64
	s_mov_b32 s3, 0x3ec71dee
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[2:3]
	s_mov_b32 s2, 0x7c89e6b0
	s_mov_b32 s3, 0x3efa0199
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[2:3]
	s_mov_b32 s2, 0x14761f6e
	s_mov_b32 s3, 0x3f2a01a0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[2:3]
	s_mov_b32 s2, 0x1852b7b0
	s_mov_b32 s3, 0x3f56c16c
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[2:3]
	s_mov_b32 s2, 0x11122322
	s_mov_b32 s3, 0x3f811111
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[2:3]
	s_mov_b32 s2, 0x555502a1
	s_mov_b32 s3, 0x3fa55555
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[2:3]
	s_mov_b32 s2, 0x55555511
	s_mov_b32 s3, 0x3fc55555
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[2:3]
	s_mov_b32 s2, 11
	s_mov_b32 s3, 0x3fe00000
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], 1.0
	v_fma_f64 v[13:14], v[15:16], v[17:18], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[13:14], v[13:14], v0
	v_add_f64 v[13:14], -v[13:14], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, 0xfff00000, v14, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e32 v6, 0, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v7, 0x3ff00000, v0, s0
.LBB0_6:                                ; %Flow
	s_and_not1_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_8
; %bb.7:
	v_mul_f64 v[6:7], v[4:5], v[4:5]
	s_mov_b32 s2, 0xdfeb1f49
	s_mov_b32 s4, 0x51d2ebeb
	s_mov_b32 s3, 0x3e4d6e3d
	s_mov_b32 s5, 0xbe0ab15c
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[13:14], v[6:7], s[4:5], s[2:3]
	s_mov_b32 s2, 0x63844720
	s_mov_b32 s3, 0xbe85bfe7
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[13:14], v[6:7], v[13:14], s[2:3]
	s_mov_b32 s2, 0x4280cfb9
	s_mov_b32 s3, 0x3ebb97e4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[13:14], v[6:7], v[13:14], s[2:3]
	s_mov_b32 s2, 0x4c771c5
	s_mov_b32 s3, 0xbeef4ca2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[13:14], v[6:7], v[13:14], s[2:3]
	s_mov_b32 s2, 0x75531772
	s_mov_b32 s3, 0x3f1f9a2b
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[13:14], v[6:7], v[13:14], s[2:3]
	s_mov_b32 s2, 0x149d904
	s_mov_b32 s3, 0xbf4c02db
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[13:14], v[6:7], v[13:14], s[2:3]
	s_mov_b32 s2, 0xcf7e2856
	s_mov_b32 s3, 0x3f7565bc
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[13:14], v[6:7], v[13:14], s[2:3]
	s_mov_b32 s2, 0x311ee09b
	s_mov_b32 s3, 0xbf9b82ce
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[13:14], v[6:7], v[13:14], s[2:3]
	s_mov_b32 s2, 0x1a0408d1
	s_mov_b32 s3, 0x3fbce2f2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[13:14], v[6:7], v[13:14], s[2:3]
	s_mov_b32 s2, 0x6b0379b2
	s_mov_b32 s3, 0xbfd81274
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[13:14], v[6:7], v[13:14], s[2:3]
	s_mov_b32 s2, 0x8214db68
	s_mov_b32 s3, 0x3fc06eba
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], v[6:7], v[13:14], s[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[6:7], |v[4:5]|, v[6:7], |v[4:5]|
.LBB0_8:                                ; %_Z5pricefffffPfS_.exit
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_bfi_b32 v7, 0x7fffffff, v7, v5
	v_bfi_b32 v3, 0x7fffffff, v3, v1
	v_mul_f32_e64 v4, v12, -v11
	v_fma_f64 v[0:1], v[6:7], 0.5, 0.5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[2:3], v[2:3], 0.5, 0.5
	v_mul_f32_e32 v5, 0x3fb8aa3b, v4
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v6, 0x3fb8aa3b, v4, -v5
	v_rndne_f32_e32 v7, v5
	v_dual_fmamk_f32 v6, v4, 0x32a5705f, v6 :: v_dual_sub_f32 v5, v5, v7
	v_cvt_f32_f64_e32 v0, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v1, v5, v6
	v_cvt_f32_f64_e32 v2, v[2:3]
	v_cvt_i32_f32_e32 v3, v7
	v_exp_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v4
	v_cndmask_b32_e32 v1, 0x7f800000, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v3, v9, v1
	v_fma_f32 v1, v9, v1, -v10
	v_mul_f32_e32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v0, v10, v2, -v0
	v_add_f32_e32 v1, v1, v0
	global_store_b32 v8, v0, s[6:7]
	s_waitcnt lgkmcnt(0)
	global_store_b32 v8, v1, s[8:9]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5pricePfS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 12
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z5pricePfS_S_S_S_S_S_, .Lfunc_end0-_Z5pricePfS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3836
; NumSgprs: 14
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 14
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 56
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5pricePfS_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     14
    .sgpr_spill_count: 0
    .symbol:         _Z5pricePfS_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     19
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
