#define COALESCED_NUM 16
#define blockDimX 256
#define blockDimY 1
#define gridDimX (gridDim.x)
#define gridDimY (gridDim.y)
#define idx (blockIdx.x*blockDimX+threadIdx.x)
#define idy (blockIdx.y*blockDimY+threadIdx.y)
#define bidy (blockIdx.y)
#define bidx (blockIdx.x)
#define tidx (threadIdx.x)
#define tidy (threadIdx.y)
#define merger_y 4
#define coalesced_idy (bidy/(COALESCED_NUM/(merger_y*blockDimY))*COALESCED_NUM)
#define A(y,x) A[(y)*WIDTH_A+(x)]
#define B(y,x) B[(y)*WIDTH_B+(x)]
#define C(y,x) C[(y)*WIDTH_C+(x)]
#define WIDTH_C 2048
#define WIDTH_B 16
#define WIDTH_A (2048+16)
__global__ void conv(float * A, float * B, float * C, int width, int height, int w, int h)
{
	__shared__ float shared_1[16][5];
	__shared__ float shared_0[272];
	int j;
	float sum_0 = 0;
	float sum_1 = 0;
	float sum_2 = 0;
	float sum_3 = 0;
	int it_2;
	for (j=0; j<(h-3); j=(j+1))
	{
		int it_2;
		if ((tidx<16))
		{
			shared_0[(tidx+0)]=A((((idy*4)+(( - 1)*j))+h), (idx+(( - 1)*0)));
		}
		shared_0[(tidx+16)]=A((((idy*4)+(( - 1)*j))+h), ((idx+(( - 1)*0))+16));
		__syncthreads();
		if ((tidx<16))
		{
			shared_1[(tidx+0)][0]=B((j+0), (0+tidx));
			shared_1[(tidx+0)][1]=B((j+1), (0+tidx));
			shared_1[(tidx+0)][2]=B((j+2), (0+tidx));
			shared_1[(tidx+0)][3]=B((j+3), (0+tidx));
		}
		__syncthreads();
		#pragma unroll 
		for (it_2=0; it_2<16; it_2=(it_2+1))
		{
			float a;
			float b_0;
			float b_1;
			float b_2;
			float b_3;
			a=shared_0[((tidx+(( - 1)*(it_2+0)))+16)];
			b_0=shared_1[it_2][0];
			b_1=shared_1[it_2][1];
			b_2=shared_1[it_2][2];
			b_3=shared_1[it_2][3];
			sum_0+=(a*b_0);
			sum_1+=(a*b_1);
			sum_2+=(a*b_2);
			sum_3+=(a*b_3);
		}
		__syncthreads();
		__syncthreads();
	}
	if ((tidx<16))
	{
		{
			shared_0[(tidx+0)]=A((((idy*4)+(( - 1)*(h-1)))+h), (idx+(( - 1)*0)));
		}
	}
	{
		shared_0[(tidx+16)]=A((((idy*4)+(( - 1)*(h-1)))+h), ((idx+(( - 1)*0))+16));
	}
	__syncthreads();
	if ((tidx<16))
	{
		{
			shared_1[(tidx+0)][0]=B((h-1), (0+tidx));
		}
	}
	__syncthreads();
	#pragma unroll 
	for (it_2=0; it_2<16; it_2=(it_2+1))
	{
		float a;
		float b_0;
		a=shared_0[((tidx+(( - 1)*(it_2+0)))+16)];
		b_0=shared_1[it_2][0];
		sum_0+=(a*b_0);
	}
	__syncthreads();
	__syncthreads();
	if ((tidx<16))
	{
		{
			shared_0[(tidx+0)]=A((((idy*4)+(( - 1)*(h-2)))+h), (idx+(( - 1)*0)));
		}
	}
	{
		shared_0[(tidx+16)]=A((((idy*4)+(( - 1)*(h-2)))+h), ((idx+(( - 1)*0))+16));
	}
	__syncthreads();
	if ((tidx<16))
	{
		{
			shared_1[(tidx+0)][0]=B((h-2), (0+tidx));
		}
		{
			shared_1[(tidx+0)][1]=B((h-1), (0+tidx));
		}
	}
	__syncthreads();
	#pragma unroll 
	for (it_2=0; it_2<16; it_2=(it_2+1))
	{
		float a;
		float b_0;
		float b_1;
		a=shared_0[((tidx+(( - 1)*(it_2+0)))+16)];
		b_0=shared_1[it_2][0];
		b_1=shared_1[it_2][1];
		sum_0+=(a*b_0);
		sum_1+=(a*b_1);
	}
	__syncthreads();
	__syncthreads();
	if ((tidx<16))
	{
		{
			shared_0[(tidx+0)]=A((((idy*4)+(( - 1)*(h-3)))+h), (idx+(( - 1)*0)));
		}
	}
	{
		shared_0[(tidx+16)]=A((((idy*4)+(( - 1)*(h-3)))+h), ((idx+(( - 1)*0))+16));
	}
	__syncthreads();
	if ((tidx<16))
	{
		{
			shared_1[(tidx+0)][0]=B((h-3), (0+tidx));
		}
		{
			shared_1[(tidx+0)][1]=B((h-2), (0+tidx));
		}
		{
			shared_1[(tidx+0)][2]=B((h-1), (0+tidx));
		}
	}
	__syncthreads();
	#pragma unroll 
	for (it_2=0; it_2<16; it_2=(it_2+1))
	{
		float a;
		float b_0;
		float b_1;
		float b_2;
		a=shared_0[((tidx+(( - 1)*(it_2+0)))+16)];
		b_0=shared_1[it_2][0];
		b_1=shared_1[it_2][1];
		b_2=shared_1[it_2][2];
		sum_0+=(a*b_0);
		sum_1+=(a*b_1);
		sum_2+=(a*b_2);
	}
	C(((idy*4)+0), idx)=sum_0;
	__syncthreads();
	__syncthreads();
	if ((tidx<16))
	{
		{
			shared_0[(tidx+0)]=A((((idy*4)+(( - 1)*(0-1)))+h), (idx+(( - 1)*0)));
		}
	}
	{
		shared_0[(tidx+16)]=A((((idy*4)+(( - 1)*(0-1)))+h), ((idx+(( - 1)*0))+16));
	}
	__syncthreads();
	if ((tidx<16))
	{
		{
			shared_1[(tidx+0)][1]=B(0, (0+tidx));
		}
		{
			shared_1[(tidx+0)][2]=B(1, (0+tidx));
		}
		{
			shared_1[(tidx+0)][3]=B(2, (0+tidx));
		}
	}
	__syncthreads();
	#pragma unroll 
	for (it_2=0; it_2<16; it_2=(it_2+1))
	{
		float a;
		float b_1;
		float b_2;
		float b_3;
		a=shared_0[((tidx+(( - 1)*(it_2+0)))+16)];
		b_1=shared_1[it_2][1];
		b_2=shared_1[it_2][2];
		b_3=shared_1[it_2][3];
		sum_1+=(a*b_1);
		sum_2+=(a*b_2);
		sum_3+=(a*b_3);
	}
	C(((idy*4)+1), idx)=sum_1;
	__syncthreads();
	__syncthreads();
	if ((tidx<16))
	{
		{
			shared_0[(tidx+0)]=A((((idy*4)+(( - 1)*(0-2)))+h), (idx+(( - 1)*0)));
		}
	}
	{
		shared_0[(tidx+16)]=A((((idy*4)+(( - 1)*(0-2)))+h), ((idx+(( - 1)*0))+16));
	}
	__syncthreads();
	if ((tidx<16))
	{
		{
			shared_1[(tidx+0)][2]=B(0, (0+tidx));
		}
		{
			shared_1[(tidx+0)][3]=B(1, (0+tidx));
		}
	}
	__syncthreads();
	#pragma unroll 
	for (it_2=0; it_2<16; it_2=(it_2+1))
	{
		float a;
		float b_2;
		float b_3;
		a=shared_0[((tidx+(( - 1)*(it_2+0)))+16)];
		b_2=shared_1[it_2][2];
		b_3=shared_1[it_2][3];
		sum_2+=(a*b_2);
		sum_3+=(a*b_3);
	}
	C(((idy*4)+2), idx)=sum_2;
	__syncthreads();
	__syncthreads();
	if ((tidx<16))
	{
		{
			shared_0[(tidx+0)]=A((((idy*4)+(( - 1)*(0-3)))+h), (idx+(( - 1)*0)));
		}
	}
	{
		shared_0[(tidx+16)]=A((((idy*4)+(( - 1)*(0-3)))+h), ((idx+(( - 1)*0))+16));
	}
	__syncthreads();
	if ((tidx<16))
	{
		{
			shared_1[(tidx+0)][3]=B(0, (0+tidx));
		}
	}
	__syncthreads();
	#pragma unroll 
	for (it_2=0; it_2<16; it_2=(it_2+1))
	{
		float a;
		float b_3;
		a=shared_0[((tidx+(( - 1)*(it_2+0)))+16)];
		b_3=shared_1[it_2][3];
		sum_3+=(a*b_3);
	}
	C(((idy*4)+3), idx)=sum_3;
	__syncthreads();
	__syncthreads();
	{
		
	}
	{
		
	}
	{
		
	}
	{
		
	}
}

	.file	"tmpxft_00290def_00000000-6_gcompiler_conv_IteratorPass_THREAD_Y_4_.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z31__device_stub__Z4convPfS_S_iiiiPfS_S_iiii
	.type	_Z31__device_stub__Z4convPfS_S_iiiiPfS_S_iiii, @function
_Z31__device_stub__Z4convPfS_S_iiiiPfS_S_iiii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z4convPfS_S_iiii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z31__device_stub__Z4convPfS_S_iiiiPfS_S_iiii, .-_Z31__device_stub__Z4convPfS_S_iiiiPfS_S_iiii
	.globl	_Z4convPfS_S_iiii
	.type	_Z4convPfS_S_iiii, @function
_Z4convPfS_S_iiii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z4convPfS_S_iiiiPfS_S_iiii
	.cfi_endproc
.LFE2033:
	.size	_Z4convPfS_S_iiii, .-_Z4convPfS_S_iiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z4convPfS_S_iiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z4convPfS_S_iiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#define COALESCED_NUM 16
#define blockDimX 256
#define blockDimY 1
#define gridDimX (gridDim.x)
#define gridDimY (gridDim.y)
#define idx (blockIdx.x*blockDimX+threadIdx.x)
#define idy (blockIdx.y*blockDimY+threadIdx.y)
#define bidy (blockIdx.y)
#define bidx (blockIdx.x)
#define tidx (threadIdx.x)
#define tidy (threadIdx.y)
#define merger_y 4
#define coalesced_idy (bidy/(COALESCED_NUM/(merger_y*blockDimY))*COALESCED_NUM)
#define A(y,x) A[(y)*WIDTH_A+(x)]
#define B(y,x) B[(y)*WIDTH_B+(x)]
#define C(y,x) C[(y)*WIDTH_C+(x)]
#define WIDTH_C 2048
#define WIDTH_B 16
#define WIDTH_A (2048+16)
__global__ void conv(float * A, float * B, float * C, int width, int height, int w, int h)
{
	__shared__ float shared_1[16][5];
	__shared__ float shared_0[272];
	int j;
	float sum_0 = 0;
	float sum_1 = 0;
	float sum_2 = 0;
	float sum_3 = 0;
	int it_2;
	for (j=0; j<(h-3); j=(j+1))
	{
		int it_2;
		if ((tidx<16))
		{
			shared_0[(tidx+0)]=A((((idy*4)+(( - 1)*j))+h), (idx+(( - 1)*0)));
		}
		shared_0[(tidx+16)]=A((((idy*4)+(( - 1)*j))+h), ((idx+(( - 1)*0))+16));
		__syncthreads();
		if ((tidx<16))
		{
			shared_1[(tidx+0)][0]=B((j+0), (0+tidx));
			shared_1[(tidx+0)][1]=B((j+1), (0+tidx));
			shared_1[(tidx+0)][2]=B((j+2), (0+tidx));
			shared_1[(tidx+0)][3]=B((j+3), (0+tidx));
		}
		__syncthreads();
		#pragma unroll 
		for (it_2=0; it_2<16; it_2=(it_2+1))
		{
			float a;
			float b_0;
			float b_1;
			float b_2;
			float b_3;
			a=shared_0[((tidx+(( - 1)*(it_2+0)))+16)];
			b_0=shared_1[it_2][0];
			b_1=shared_1[it_2][1];
			b_2=shared_1[it_2][2];
			b_3=shared_1[it_2][3];
			sum_0+=(a*b_0);
			sum_1+=(a*b_1);
			sum_2+=(a*b_2);
			sum_3+=(a*b_3);
		}
		__syncthreads();
		__syncthreads();
	}
	if ((tidx<16))
	{
		{
			shared_0[(tidx+0)]=A((((idy*4)+(( - 1)*(h-1)))+h), (idx+(( - 1)*0)));
		}
	}
	{
		shared_0[(tidx+16)]=A((((idy*4)+(( - 1)*(h-1)))+h), ((idx+(( - 1)*0))+16));
	}
	__syncthreads();
	if ((tidx<16))
	{
		{
			shared_1[(tidx+0)][0]=B((h-1), (0+tidx));
		}
	}
	__syncthreads();
	#pragma unroll 
	for (it_2=0; it_2<16; it_2=(it_2+1))
	{
		float a;
		float b_0;
		a=shared_0[((tidx+(( - 1)*(it_2+0)))+16)];
		b_0=shared_1[it_2][0];
		sum_0+=(a*b_0);
	}
	__syncthreads();
	__syncthreads();
	if ((tidx<16))
	{
		{
			shared_0[(tidx+0)]=A((((idy*4)+(( - 1)*(h-2)))+h), (idx+(( - 1)*0)));
		}
	}
	{
		shared_0[(tidx+16)]=A((((idy*4)+(( - 1)*(h-2)))+h), ((idx+(( - 1)*0))+16));
	}
	__syncthreads();
	if ((tidx<16))
	{
		{
			shared_1[(tidx+0)][0]=B((h-2), (0+tidx));
		}
		{
			shared_1[(tidx+0)][1]=B((h-1), (0+tidx));
		}
	}
	__syncthreads();
	#pragma unroll 
	for (it_2=0; it_2<16; it_2=(it_2+1))
	{
		float a;
		float b_0;
		float b_1;
		a=shared_0[((tidx+(( - 1)*(it_2+0)))+16)];
		b_0=shared_1[it_2][0];
		b_1=shared_1[it_2][1];
		sum_0+=(a*b_0);
		sum_1+=(a*b_1);
	}
	__syncthreads();
	__syncthreads();
	if ((tidx<16))
	{
		{
			shared_0[(tidx+0)]=A((((idy*4)+(( - 1)*(h-3)))+h), (idx+(( - 1)*0)));
		}
	}
	{
		shared_0[(tidx+16)]=A((((idy*4)+(( - 1)*(h-3)))+h), ((idx+(( - 1)*0))+16));
	}
	__syncthreads();
	if ((tidx<16))
	{
		{
			shared_1[(tidx+0)][0]=B((h-3), (0+tidx));
		}
		{
			shared_1[(tidx+0)][1]=B((h-2), (0+tidx));
		}
		{
			shared_1[(tidx+0)][2]=B((h-1), (0+tidx));
		}
	}
	__syncthreads();
	#pragma unroll 
	for (it_2=0; it_2<16; it_2=(it_2+1))
	{
		float a;
		float b_0;
		float b_1;
		float b_2;
		a=shared_0[((tidx+(( - 1)*(it_2+0)))+16)];
		b_0=shared_1[it_2][0];
		b_1=shared_1[it_2][1];
		b_2=shared_1[it_2][2];
		sum_0+=(a*b_0);
		sum_1+=(a*b_1);
		sum_2+=(a*b_2);
	}
	C(((idy*4)+0), idx)=sum_0;
	__syncthreads();
	__syncthreads();
	if ((tidx<16))
	{
		{
			shared_0[(tidx+0)]=A((((idy*4)+(( - 1)*(0-1)))+h), (idx+(( - 1)*0)));
		}
	}
	{
		shared_0[(tidx+16)]=A((((idy*4)+(( - 1)*(0-1)))+h), ((idx+(( - 1)*0))+16));
	}
	__syncthreads();
	if ((tidx<16))
	{
		{
			shared_1[(tidx+0)][1]=B(0, (0+tidx));
		}
		{
			shared_1[(tidx+0)][2]=B(1, (0+tidx));
		}
		{
			shared_1[(tidx+0)][3]=B(2, (0+tidx));
		}
	}
	__syncthreads();
	#pragma unroll 
	for (it_2=0; it_2<16; it_2=(it_2+1))
	{
		float a;
		float b_1;
		float b_2;
		float b_3;
		a=shared_0[((tidx+(( - 1)*(it_2+0)))+16)];
		b_1=shared_1[it_2][1];
		b_2=shared_1[it_2][2];
		b_3=shared_1[it_2][3];
		sum_1+=(a*b_1);
		sum_2+=(a*b_2);
		sum_3+=(a*b_3);
	}
	C(((idy*4)+1), idx)=sum_1;
	__syncthreads();
	__syncthreads();
	if ((tidx<16))
	{
		{
			shared_0[(tidx+0)]=A((((idy*4)+(( - 1)*(0-2)))+h), (idx+(( - 1)*0)));
		}
	}
	{
		shared_0[(tidx+16)]=A((((idy*4)+(( - 1)*(0-2)))+h), ((idx+(( - 1)*0))+16));
	}
	__syncthreads();
	if ((tidx<16))
	{
		{
			shared_1[(tidx+0)][2]=B(0, (0+tidx));
		}
		{
			shared_1[(tidx+0)][3]=B(1, (0+tidx));
		}
	}
	__syncthreads();
	#pragma unroll 
	for (it_2=0; it_2<16; it_2=(it_2+1))
	{
		float a;
		float b_2;
		float b_3;
		a=shared_0[((tidx+(( - 1)*(it_2+0)))+16)];
		b_2=shared_1[it_2][2];
		b_3=shared_1[it_2][3];
		sum_2+=(a*b_2);
		sum_3+=(a*b_3);
	}
	C(((idy*4)+2), idx)=sum_2;
	__syncthreads();
	__syncthreads();
	if ((tidx<16))
	{
		{
			shared_0[(tidx+0)]=A((((idy*4)+(( - 1)*(0-3)))+h), (idx+(( - 1)*0)));
		}
	}
	{
		shared_0[(tidx+16)]=A((((idy*4)+(( - 1)*(0-3)))+h), ((idx+(( - 1)*0))+16));
	}
	__syncthreads();
	if ((tidx<16))
	{
		{
			shared_1[(tidx+0)][3]=B(0, (0+tidx));
		}
	}
	__syncthreads();
	#pragma unroll 
	for (it_2=0; it_2<16; it_2=(it_2+1))
	{
		float a;
		float b_3;
		a=shared_0[((tidx+(( - 1)*(it_2+0)))+16)];
		b_3=shared_1[it_2][3];
		sum_3+=(a*b_3);
	}
	C(((idy*4)+3), idx)=sum_3;
	__syncthreads();
	__syncthreads();
	{
		
	}
	{
		
	}
	{
		
	}
	{
		
	}
}

	.text
	.file	"gcompiler_conv_IteratorPass_THREAD_Y_4_.hip"
	.globl	_Z19__device_stub__convPfS_S_iiii # -- Begin function _Z19__device_stub__convPfS_S_iiii
	.type	_Z19__device_stub__convPfS_S_iiii,@function
_Z19__device_stub__convPfS_S_iiii:      # @_Z19__device_stub__convPfS_S_iiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4convPfS_S_iiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z19__device_stub__convPfS_S_iiii, .Lfunc_end0-_Z19__device_stub__convPfS_S_iiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4convPfS_S_iiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z4convPfS_S_iiii,@object       # @_Z4convPfS_S_iiii
	.section	.rodata,"a",@progbits
	.globl	_Z4convPfS_S_iiii
	.p2align	3, 0x0
_Z4convPfS_S_iiii:
	.quad	_Z19__device_stub__convPfS_S_iiii
	.size	_Z4convPfS_S_iiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z4convPfS_S_iiii"
	.size	.L__unnamed_1, 18

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z19__device_stub__convPfS_S_iiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z4convPfS_S_iiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z4convPfS_S_iiii       ; -- Begin function _Z4convPfS_S_iiii
	.globl	_Z4convPfS_S_iiii
	.p2align	8
	.type	_Z4convPfS_S_iiii,@function
_Z4convPfS_S_iiii:                      ; @_Z4convPfS_S_iiii
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_dual_mov_b32 v107, 0 :: v_dual_and_b32 v108, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	v_mov_b32_e32 v112, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_mov_b32 v110, 0 :: v_dual_lshlrev_b32 v105, 2, v108
	v_cmp_gt_u32_e32 vcc_lo, 16, v108
	v_add_nc_u32_e32 v88, s15, v0
	v_mad_u32_u24 v70, v108, 20, 0x440
	v_mov_b32_e32 v106, 0
	s_mov_b32 s9, 0
	s_waitcnt lgkmcnt(0)
	s_add_i32 s1, s8, -3
	s_cmp_lt_i32 s8, 4
	s_cbranch_scc1 .LBB0_7
; %bb.1:                                ; %.lr.ph
	v_mul_lo_u32 v0, 0x2040, v88
	s_lshl_b32 s0, s14, 8
	s_mul_i32 s10, s8, 0x810
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 0x454
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v6, 0x47c
	v_dual_mov_b32 v5, 0x45c :: v_dual_mov_b32 v112, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_add3_u32 v7, s0, s10, v0
	v_dual_mov_b32 v8, 0x484 :: v_dual_mov_b32 v107, 0
	v_dual_mov_b32 v9, 0x4a4 :: v_dual_mov_b32 v110, 0
	v_mov_b32_e32 v10, 0x4ac
	v_dual_mov_b32 v11, 0x4cc :: v_dual_mov_b32 v106, 0
	v_mov_b32_e32 v12, 0x4d4
	v_mov_b32_e32 v13, 0x4f4
	v_mov_b32_e32 v14, 0x4fc
	v_mov_b32_e32 v15, 0x51c
	v_mov_b32_e32 v16, 0x524
	v_mov_b32_e32 v17, 0x544
	v_mov_b32_e32 v18, 0x54c
	v_mov_b32_e32 v19, 0x56c
	v_mov_b32_e32 v20, 0x574
	s_mov_b32 s10, s1
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_and_saveexec_b32 s11, vcc_lo
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v2, v108, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[21:22], 2, v[2:3]
	v_add_co_u32 v21, s0, s4, v21
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v22, s0, s5, v22, s0
	global_load_b32 v0, v[21:22], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v105, v0
.LBB0_4:                                ; %._crit_edge240
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	v_add3_u32 v2, v108, v7, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[21:22], 2, v[2:3]
	v_add_co_u32 v21, s0, s4, v21
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v22, s0, s5, v22, s0
	global_load_b32 v0, v[21:22], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v105, v0 offset:64
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s11, vcc_lo
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v0, s9, v108
	v_mov_b32_e32 v22, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_mov_b32 v24, v1 :: v_dual_add_nc_u32 v23, 32, v0
	v_add_nc_u32_e32 v21, 16, v0
	v_lshlrev_b64 v[25:26], 2, v[0:1]
	v_add_nc_u32_e32 v0, 48, v0
	v_lshlrev_b64 v[23:24], 2, v[23:24]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[21:22], 2, v[21:22]
	v_add_co_u32 v25, s0, s6, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v26, s0, s7, v26, s0
	v_add_co_u32 v21, s0, s6, v21
	v_lshlrev_b64 v[27:28], 2, v[0:1]
	v_add_co_ci_u32_e64 v22, s0, s7, v22, s0
	v_add_co_u32 v23, s0, s6, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v24, s0, s7, v24, s0
	v_add_co_u32 v27, s0, s6, v27
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v28, s0, s7, v28, s0
	s_clause 0x3
	global_load_b32 v0, v[25:26], off
	global_load_b32 v2, v[21:22], off
	global_load_b32 v21, v[23:24], off
	global_load_b32 v22, v[27:28], off
	s_waitcnt vmcnt(2)
	ds_store_2addr_b32 v70, v0, v2 offset1:1
	s_waitcnt vmcnt(0)
	ds_store_2addr_b32 v70, v21, v22 offset0:2 offset1:3
.LBB0_6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[37:38], v105 offset0:15 offset1:16
	ds_load_b128 v[21:24], v3 offset:1088
	ds_load_2addr_b32 v[39:40], v4 offset1:1
	ds_load_2addr_b32 v[41:42], v5 offset1:1
	ds_load_2addr_b32 v[43:44], v105 offset0:13 offset1:14
	ds_load_2addr_b64 v[25:28], v3 offset0:141 offset1:142
	ds_load_2addr_b32 v[45:46], v6 offset1:1
	ds_load_2addr_b32 v[47:48], v8 offset1:1
	ds_load_2addr_b32 v[49:50], v105 offset0:11 offset1:12
	ds_load_2addr_b32 v[51:52], v105 offset0:9 offset1:10
	ds_load_b128 v[29:32], v3 offset:1168
	ds_load_2addr_b64 v[33:36], v3 offset0:151 offset1:152
	s_add_i32 s10, s10, -1
	s_add_i32 s9, s9, 16
	s_cmp_lg_u32 s10, 0
	v_add_nc_u32_e32 v7, 0xfffff7f0, v7
	s_waitcnt lgkmcnt(10)
	v_fmac_f32_e32 v107, v38, v23
	s_waitcnt lgkmcnt(8)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v110, v38, v22 :: v_dual_fmac_f32 v107, v37, v41
	v_fmac_f32_e32 v112, v38, v21
	s_waitcnt lgkmcnt(6)
	v_dual_fmac_f32 v110, v37, v40 :: v_dual_fmac_f32 v107, v44, v27
	v_fmac_f32_e32 v106, v38, v24
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v112, v37, v39
	ds_load_2addr_b32 v[38:39], v9 offset1:1
	ds_load_2addr_b32 v[53:54], v10 offset1:1
	ds_load_2addr_b32 v[55:56], v11 offset1:1
	ds_load_2addr_b32 v[57:58], v12 offset1:1
	ds_load_b128 v[21:24], v3 offset:1248
	s_waitcnt lgkmcnt(9)
	v_dual_fmac_f32 v107, v43, v47 :: v_dual_fmac_f32 v106, v37, v42
	s_waitcnt lgkmcnt(6)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v107, v50, v31 :: v_dual_fmac_f32 v110, v44, v26
	v_fmac_f32_e32 v106, v44, v28
	s_waitcnt lgkmcnt(3)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v106, v43, v48 :: v_dual_fmac_f32 v107, v49, v53
	v_fmac_f32_e32 v110, v43, v46
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v106, v50, v32 :: v_dual_fmac_f32 v107, v52, v35
	v_fmac_f32_e32 v110, v50, v30
	s_waitcnt lgkmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v106, v49, v54 :: v_dual_fmac_f32 v107, v51, v57
	v_fmac_f32_e32 v112, v44, v25
	v_fmac_f32_e32 v110, v49, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v106, v52, v36
	v_fmac_f32_e32 v112, v43, v45
	ds_load_2addr_b32 v[40:41], v13 offset1:1
	ds_load_2addr_b32 v[44:45], v14 offset1:1
	ds_load_2addr_b32 v[42:43], v105 offset0:5 offset1:6
	ds_load_2addr_b64 v[25:28], v3 offset0:161 offset1:162
	v_fmac_f32_e32 v110, v52, v34
	v_fmac_f32_e32 v112, v50, v29
	ds_load_2addr_b32 v[29:30], v105 offset0:7 offset1:8
	v_fmac_f32_e32 v106, v51, v58
	v_fmac_f32_e32 v110, v51, v56
	v_fmac_f32_e32 v112, v49, v38
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v112, v52, v33
	ds_load_2addr_b32 v[33:34], v15 offset1:1
	ds_load_2addr_b32 v[35:36], v16 offset1:1
	ds_load_2addr_b32 v[37:38], v105 offset0:3 offset1:4
	v_fmac_f32_e32 v112, v51, v55
	s_waitcnt lgkmcnt(3)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v112, v30, v21
	v_fmac_f32_e32 v110, v30, v22
	v_fmac_f32_e32 v107, v30, v23
	v_fmac_f32_e32 v106, v30, v24
	ds_load_b128 v[21:24], v3 offset:1328
	v_fmac_f32_e32 v112, v29, v40
	ds_load_2addr_b32 v[39:40], v17 offset1:1
	v_fmac_f32_e32 v110, v29, v41
	v_fmac_f32_e32 v107, v29, v44
	v_fmac_f32_e32 v106, v29, v45
	ds_load_2addr_b32 v[44:45], v18 offset1:1
	v_fmac_f32_e32 v112, v43, v25
	v_fmac_f32_e32 v110, v43, v26
	ds_load_2addr_b32 v[25:26], v105 offset0:1 offset1:2
	ds_load_2addr_b64 v[29:32], v3 offset0:171 offset1:172
	v_fmac_f32_e32 v107, v43, v27
	v_fmac_f32_e32 v106, v43, v28
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v112, v42, v33
	v_fmac_f32_e32 v110, v42, v34
	ds_load_2addr_b32 v[27:28], v19 offset1:1
	ds_load_2addr_b32 v[33:34], v20 offset1:1
	s_waitcnt lgkmcnt(8)
	v_fmac_f32_e32 v107, v42, v35
	v_fmac_f32_e32 v106, v42, v36
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_fmac_f32_e32 v112, v38, v21
	v_fmac_f32_e32 v110, v38, v22
	v_fmac_f32_e32 v107, v38, v23
	v_fmac_f32_e32 v106, v38, v24
	buffer_gl0_inv
	v_fmac_f32_e32 v112, v37, v39
	v_fmac_f32_e32 v110, v37, v40
	v_fmac_f32_e32 v107, v37, v44
	v_fmac_f32_e32 v106, v37, v45
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v112, v26, v29
	v_fmac_f32_e32 v110, v26, v30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v107, v26, v31
	v_fmac_f32_e32 v106, v26, v32
	s_barrier
	v_fmac_f32_e32 v112, v25, v27
	v_fmac_f32_e32 v110, v25, v28
	v_fmac_f32_e32 v107, v25, v33
	v_fmac_f32_e32 v106, v25, v34
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_2
.LBB0_7:                                ; %._crit_edge
	v_mul_lo_u32 v0, 0x2040, v88
	s_lshl_b32 s0, s14, 8
	v_cmp_gt_u32_e32 vcc_lo, 16, v108
	v_add_nc_u32_e32 v109, s0, v108
	s_and_saveexec_b32 s9, vcc_lo
	s_cbranch_execz .LBB0_9
; %bb.8:
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v109, v0, 0x810
	v_mov_b32_e32 v2, 0
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v1, s0, s4, v1
	v_add_co_ci_u32_e64 v2, s0, s5, v2, s0
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v105, v1
.LBB0_9:                                ; %._crit_edge._crit_edge
	s_or_b32 exec_lo, exec_lo, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v75, v0, v109
	v_mov_b32_e32 v17, 0
	v_mul_u32_u24_e32 v111, 20, v108
	v_add_nc_u32_e32 v16, 0x820, v75
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[16:17]
	v_add_co_u32 v0, s0, s4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v1, s0, s5, v1, s0
	s_add_i32 s0, s8, -1
	v_lshl_or_b32 v16, s0, 4, v108
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v105, v0 offset:64
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s9, vcc_lo
	s_cbranch_execz .LBB0_11
; %bb.10:
	v_lshlrev_b64 v[0:1], 2, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, s0, s6, v0
	v_add_co_ci_u32_e64 v1, s0, s7, v1, s0
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v111, v0 offset:1088
.LBB0_11:
	s_or_b32 exec_lo, exec_lo, s9
	v_add_nc_u32_e64 v0, 0x400, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[79:80], v0 offset0:16 offset1:21
	ds_load_2addr_b32 v[44:45], v0 offset0:26 offset1:31
	ds_load_2addr_b32 v[40:41], v0 offset0:36 offset1:41
	ds_load_2addr_b32 v[83:84], v105 offset0:15 offset1:16
	ds_load_2addr_b32 v[81:82], v105 offset0:13 offset1:14
	ds_load_2addr_b32 v[73:74], v105 offset0:11 offset1:12
	ds_load_2addr_b32 v[38:39], v105 offset0:9 offset1:10
	ds_load_2addr_b32 v[46:47], v0 offset0:46 offset1:51
	ds_load_2addr_b32 v[36:37], v0 offset0:56 offset1:61
	ds_load_2addr_b32 v[24:25], v0 offset0:66 offset1:71
	ds_load_2addr_b32 v[20:21], v0 offset0:76 offset1:81
	ds_load_2addr_b32 v[77:78], v105 offset0:7 offset1:8
	ds_load_2addr_b32 v[42:43], v105 offset0:5 offset1:6
	ds_load_2addr_b32 v[26:27], v105 offset0:3 offset1:4
	ds_load_2addr_b32 v[18:19], v105 offset0:1 offset1:2
	ds_load_2addr_b32 v[22:23], v0 offset0:86 offset1:91
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s9, vcc_lo
	s_cbranch_execz .LBB0_13
; %bb.12:
	v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, 0x1020, v75
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, s0, s4, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v1, s0, s5, v1, s0
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v105, v0
.LBB0_13:
	s_or_b32 exec_lo, exec_lo, s9
	v_dual_mov_b32 v86, 0 :: v_dual_add_nc_u32 v85, 0x1030, v75
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[85:86]
	v_add_co_u32 v0, s0, s4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v1, s0, s5, v1, s0
	s_add_i32 s0, s8, -2
	v_lshl_or_b32 v85, s0, 4, v108
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v105, v0 offset:64
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s9, vcc_lo
	s_cbranch_execz .LBB0_15
; %bb.14:
	v_mov_b32_e32 v17, v86
	v_lshlrev_b64 v[0:1], 2, v[85:86]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[16:17]
	v_add_co_u32 v0, s0, s6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v1, s0, s7, v1, s0
	v_add_co_u32 v2, s0, s6, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, s7, v3, s0
	s_clause 0x1
	global_load_b32 v0, v[0:1], off
	global_load_b32 v1, v[2:3], off
	s_waitcnt vmcnt(0)
	ds_store_2addr_b32 v70, v0, v1 offset1:1
.LBB0_15:
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v8, 0x454
	v_mov_b32_e32 v9, 0x47c
	v_mov_b32_e32 v10, 0x4a4
	v_mov_b32_e32 v11, 0x4cc
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b64 v[0:3], v86 offset0:136 offset1:141
	ds_load_2addr_b64 v[4:7], v86 offset0:146 offset1:151
	ds_load_2addr_b32 v[50:51], v105 offset0:15 offset1:16
	ds_load_2addr_b32 v[34:35], v105 offset0:13 offset1:14
	ds_load_2addr_b32 v[30:31], v105 offset0:11 offset1:12
	ds_load_2addr_b32 v[28:29], v105 offset0:9 offset1:10
	ds_load_2addr_b32 v[58:59], v8 offset1:1
	ds_load_2addr_b32 v[54:55], v9 offset1:1
	ds_load_2addr_b32 v[48:49], v10 offset1:1
	ds_load_2addr_b32 v[32:33], v11 offset1:1
	ds_load_2addr_b64 v[8:11], v86 offset0:156 offset1:161
	v_mov_b32_e32 v17, 0x4f4
	v_mov_b32_e32 v60, 0x51c
	v_mov_b32_e32 v61, 0x544
	ds_load_2addr_b64 v[12:15], v86 offset0:166 offset1:171
	v_mov_b32_e32 v76, 0x56c
	ds_load_2addr_b32 v[66:67], v105 offset0:7 offset1:8
	ds_load_2addr_b32 v[62:63], v105 offset0:5 offset1:6
	ds_load_2addr_b32 v[56:57], v105 offset0:3 offset1:4
	ds_load_2addr_b32 v[52:53], v105 offset0:1 offset1:2
	ds_load_2addr_b32 v[71:72], v17 offset1:1
	ds_load_2addr_b32 v[68:69], v60 offset1:1
	ds_load_2addr_b32 v[64:65], v61 offset1:1
	ds_load_2addr_b32 v[60:61], v76 offset1:1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s9, vcc_lo
	s_cbranch_execz .LBB0_17
; %bb.16:
	v_dual_mov_b32 v87, 0 :: v_dual_add_nc_u32 v86, 0x1830, v75
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[86:87], 2, v[86:87]
	v_add_co_u32 v86, s0, s4, v86
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v87, s0, s5, v87, s0
	global_load_b32 v17, v[86:87], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v105, v17
.LBB0_17:
	s_or_b32 exec_lo, exec_lo, s9
	v_dual_mov_b32 v76, 0 :: v_dual_add_nc_u32 v75, 0x1840, v75
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[86:87], 2, v[75:76]
	v_add_co_u32 v86, s0, s4, v86
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v87, s0, s5, v87, s0
	global_load_b32 v17, v[86:87], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v105, v17 offset:64
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s9, vcc_lo
	s_cbranch_execz .LBB0_19
; %bb.18:
	v_lshl_or_b32 v75, s1, 4, v108
	v_mov_b32_e32 v86, v76
	v_mov_b32_e32 v17, v76
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[89:90], 2, v[75:76]
	v_lshlrev_b64 v[85:86], 2, v[85:86]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	v_add_co_u32 v89, s0, s6, v89
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v90, s0, s7, v90, s0
	v_add_co_u32 v85, s0, s6, v85
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v86, s0, s7, v86, s0
	v_add_co_u32 v16, s0, s6, v16
	v_add_co_ci_u32_e64 v17, s0, s7, v17, s0
	s_clause 0x2
	global_load_b32 v75, v[89:90], off
	global_load_b32 v85, v[85:86], off
	global_load_b32 v16, v[16:17], off
	s_waitcnt vmcnt(1)
	ds_store_2addr_b32 v70, v75, v85 offset1:1
	s_waitcnt vmcnt(0)
	ds_store_b32 v111, v16 offset:1096
.LBB0_19:
	s_or_b32 exec_lo, exec_lo, s9
	v_fmac_f32_e32 v112, v84, v79
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_fmac_f32_e32 v112, v83, v80
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v112, v82, v44
	v_fmac_f32_e32 v112, v81, v45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v112, v74, v40
	v_fmac_f32_e32 v112, v73, v41
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v112, v39, v46
	v_fmac_f32_e32 v112, v38, v47
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v112, v78, v36
	v_fmac_f32_e32 v112, v77, v37
	ds_load_2addr_b32 v[37:38], v105 offset0:15 offset1:16
	v_fmac_f32_e32 v112, v43, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v112, v42, v25
	v_fmac_f32_e32 v112, v27, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v112, v26, v21
	v_fmac_f32_e32 v112, v19, v22
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v112, v18, v23
	ds_load_b96 v[16:18], v76 offset:1088
	v_fmac_f32_e32 v112, v51, v0
	v_mov_b32_e32 v0, 0x454
	ds_load_2addr_b32 v[82:83], v0 offset1:1
	ds_load_2addr_b32 v[39:40], v105 offset0:13 offset1:14
	v_fmac_f32_e32 v112, v50, v58
	ds_load_b64 v[84:85], v76 offset:1128
	ds_load_b32 v113, v76 offset:1116
	v_mov_b32_e32 v0, 0x47c
	ds_load_2addr_b32 v[86:87], v0 offset1:1
	ds_load_2addr_b32 v[41:42], v105 offset0:11 offset1:12
	v_fmac_f32_e32 v112, v35, v2
	v_mov_b32_e32 v0, 0x4a4
	v_mov_b32_e32 v2, 0x4cc
	ds_load_b96 v[19:21], v76 offset:1168
	ds_load_2addr_b32 v[92:93], v0 offset1:1
	ds_load_2addr_b32 v[90:91], v2 offset1:1
	v_fmac_f32_e32 v112, v34, v54
	ds_load_2addr_b32 v[43:44], v105 offset0:9 offset1:10
	ds_load_b64 v[94:95], v76 offset:1208
	ds_load_b32 v114, v76 offset:1196
	ds_load_b96 v[22:24], v76 offset:1248
	ds_load_2addr_b32 v[45:46], v105 offset0:7 offset1:8
	v_fmac_f32_e32 v112, v31, v4
	v_mov_b32_e32 v0, 0x4f4
	v_mov_b32_e32 v2, 0x56c
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v112, v30, v48
	ds_load_2addr_b32 v[98:99], v0 offset1:1
	ds_load_2addr_b32 v[47:48], v105 offset0:5 offset1:6
	ds_load_b64 v[101:102], v76 offset:1288
	v_mov_b32_e32 v0, 0x51c
	ds_load_b32 v115, v76 offset:1276
	ds_load_2addr_b32 v[96:97], v0 offset1:1
	v_fmac_f32_e32 v112, v29, v6
	v_mov_b32_e32 v0, 0x544
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v112, v28, v32
	v_fmac_f32_e32 v112, v67, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v112, v66, v71
	v_fmac_f32_e32 v112, v63, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v112, v62, v68
	v_fmac_f32_e32 v112, v57, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v112, v56, v64
	v_fmac_f32_e32 v112, v53, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v112, v52, v60
	s_waitcnt lgkmcnt(19)
	v_fmac_f32_e32 v112, v38, v16
	s_waitcnt lgkmcnt(18)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v112, v37, v82
	s_waitcnt lgkmcnt(16)
	v_fmac_f32_e32 v112, v40, v84
	s_waitcnt lgkmcnt(14)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v112, v39, v86
	s_waitcnt lgkmcnt(12)
	v_fmac_f32_e32 v112, v42, v19
	s_waitcnt lgkmcnt(11)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v112, v41, v92
	s_waitcnt lgkmcnt(8)
	v_fmac_f32_e32 v112, v44, v94
	v_lshlrev_b32_e32 v94, 13, v88
	s_delay_alu instid0(VALU_DEP_2)
	v_fmac_f32_e32 v112, v43, v90
	ds_load_2addr_b32 v[70:71], v105 offset0:3 offset1:4
	ds_load_b96 v[25:27], v76 offset:1328
	ds_load_2addr_b32 v[103:104], v0 offset1:1
	ds_load_2addr_b32 v[89:90], v2 offset1:1
	v_add_nc_u32_e32 v75, v94, v109
	v_add_nc_u32_e64 v0, 0x400, 0
	v_lshlrev_b32_e32 v2, 2, v88
	s_waitcnt lgkmcnt(9)
	v_fmac_f32_e32 v112, v46, v22
	s_waitcnt lgkmcnt(8)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v112, v45, v98
	v_add_nc_u32_e32 v98, s8, v2
	s_waitcnt lgkmcnt(6)
	v_fmac_f32_e32 v112, v48, v101
	ds_load_2addr_b32 v[73:74], v105 offset0:1 offset1:2
	ds_load_b64 v[100:101], v76 offset:1368
	ds_load_b32 v116, v76 offset:1356
	v_lshlrev_b64 v[75:76], 2, v[75:76]
	ds_load_2addr_b32 v[81:82], v0 offset0:28 offset1:33
	ds_load_2addr_b32 v[79:80], v0 offset0:48 offset1:53
	s_waitcnt lgkmcnt(9)
	v_fmac_f32_e32 v112, v47, v96
	v_add_co_u32 v75, s0, s2, v75
	s_waitcnt lgkmcnt(7)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v112, v71, v25
	v_add_co_ci_u32_e64 v76, s0, s3, v76, s0
	s_movk_i32 s0, 0x810
	s_waitcnt lgkmcnt(6)
	v_fmac_f32_e32 v112, v70, v103
	s_waitcnt lgkmcnt(3)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v112, v74, v100
	v_fmac_f32_e32 v112, v73, v89
	v_mad_u64_u32 v[88:89], null, v98, s0, 0x810
	global_store_b32 v[75:76], v112, off
	ds_load_2addr_b32 v[77:78], v0 offset0:68 offset1:73
	ds_load_2addr_b32 v[75:76], v0 offset0:88 offset1:93
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB0_21
; %bb.20:
	v_dual_mov_b32 v118, 0 :: v_dual_add_nc_u32 v117, v88, v109
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[117:118], 2, v[117:118]
	v_add_co_u32 v117, s0, s4, v117
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v118, s0, s5, v118, s0
	global_load_b32 v0, v[117:118], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v105, v0
.LBB0_21:                               ; %._crit_edge239
	s_or_b32 exec_lo, exec_lo, s1
	v_dual_mov_b32 v89, 0 :: v_dual_add_nc_u32 v96, 16, v109
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v88, v88, v96
	v_lshlrev_b64 v[117:118], 2, v[88:89]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v117, s0, s4, v117
	v_add_co_ci_u32_e64 v118, s0, s5, v118, s0
	global_load_b32 v0, v[117:118], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v105, v0 offset:64
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_23
; %bb.22:
	s_clause 0x2
	global_load_b32 v0, v105, s[6:7]
	global_load_b32 v2, v105, s[6:7] offset:64
	global_load_b32 v4, v105, s[6:7] offset:128
	v_mad_u32_u24 v6, v108, 20, 0x444
	s_waitcnt vmcnt(1)
	ds_store_2addr_b32 v6, v0, v2 offset1:1
	s_waitcnt vmcnt(0)
	ds_store_b32 v111, v4 offset:1100
.LBB0_23:
	s_or_b32 exec_lo, exec_lo, s0
	v_fmac_f32_e32 v110, v51, v1
	v_mov_b32_e32 v0, 0x444
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_fmac_f32_e32 v110, v50, v59
	v_mov_b32_e32 v4, 0x46c
	v_mov_b32_e32 v6, 0x494
	v_add3_u32 v88, v109, v94, 0x800
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v110, v35, v3
	v_fmac_f32_e32 v110, v34, v55
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v110, v31, v5
	v_fmac_f32_e32 v110, v30, v49
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v110, v29, v7 :: v_dual_mov_b32 v7, 0x4bc
	v_fmac_f32_e32 v110, v28, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v110, v67, v9
	v_fmac_f32_e32 v110, v66, v72
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v110, v63, v11
	v_fmac_f32_e32 v110, v62, v69
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v110, v57, v13
	v_fmac_f32_e32 v110, v56, v65
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v110, v53, v15
	v_fmac_f32_e32 v110, v52, v61
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v110, v38, v17
	v_fmac_f32_e32 v110, v37, v83
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v110, v40, v85
	v_fmac_f32_e32 v110, v39, v87
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v110, v42, v20
	ds_load_2addr_b32 v[19:20], v105 offset0:15 offset1:16
	ds_load_2addr_b32 v[0:1], v0 offset1:1
	ds_load_b64 v[2:3], v89 offset:1112
	v_fmac_f32_e32 v110, v41, v93
	v_fmac_f32_e32 v110, v44, v95
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v110, v43, v91
	v_fmac_f32_e32 v110, v46, v23
	ds_load_2addr_b32 v[22:23], v105 offset0:13 offset1:14
	ds_load_2addr_b32 v[4:5], v4 offset1:1
	ds_load_b96 v[14:16], v89 offset:1152
	ds_load_2addr_b32 v[8:9], v6 offset1:1
	ds_load_2addr_b32 v[6:7], v7 offset1:1
	v_fmac_f32_e32 v110, v45, v99
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v110, v48, v102
	v_fmac_f32_e32 v110, v47, v97
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v110, v71, v26
	ds_load_2addr_b32 v[25:26], v105 offset0:11 offset1:12
	ds_load_b32 v87, v89 offset:1180
	ds_load_b64 v[10:11], v89 offset:1192
	ds_load_2addr_b32 v[49:50], v105 offset0:9 offset1:10
	ds_load_b96 v[28:30], v89 offset:1232
	ds_load_2addr_b32 v[51:52], v105 offset0:7 offset1:8
	v_fmac_f32_e32 v110, v70, v104
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v110, v74, v101
	v_fmac_f32_e32 v110, v73, v90
	s_waitcnt lgkmcnt(12)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v110, v20, v0
	v_mov_b32_e32 v0, 0x4e4
	ds_load_2addr_b32 v[68:69], v0 offset1:1
	ds_load_b32 v95, v89 offset:1260
	ds_load_b64 v[83:84], v89 offset:1272
	s_waitcnt lgkmcnt(14)
	v_fmac_f32_e32 v110, v19, v2
	v_mov_b32_e32 v0, 0x50c
	v_mov_b32_e32 v2, 0x55c
	s_waitcnt lgkmcnt(12)
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v110, v23, v4
	ds_load_2addr_b32 v[85:86], v0 offset1:1
	ds_load_2addr_b32 v[53:54], v105 offset0:5 offset1:6
	ds_load_b96 v[31:33], v89 offset:1312
	v_mov_b32_e32 v0, 0x534
	ds_load_2addr_b32 v[55:56], v105 offset0:3 offset1:4
	ds_load_2addr_b32 v[90:91], v0 offset1:1
	ds_load_2addr_b32 v[12:13], v2 offset1:1
	s_waitcnt lgkmcnt(17)
	v_fmac_f32_e32 v110, v22, v14
	ds_load_b64 v[92:93], v89 offset:1352
	ds_load_2addr_b32 v[57:58], v105 offset0:1 offset1:2
	v_add_nc_u32_e64 v0, 0x400, 0
	s_waitcnt lgkmcnt(16)
	v_fmac_f32_e32 v110, v26, v8
	s_waitcnt lgkmcnt(14)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v110, v25, v10
	s_waitcnt lgkmcnt(13)
	v_fmac_f32_e32 v110, v50, v6
	s_waitcnt lgkmcnt(12)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v110, v49, v28
	s_waitcnt lgkmcnt(10)
	v_fmac_f32_e32 v110, v52, v68
	v_lshlrev_b64 v[67:68], 2, v[88:89]
	s_waitcnt lgkmcnt(8)
	s_delay_alu instid0(VALU_DEP_2)
	v_fmac_f32_e32 v110, v51, v83
	ds_load_b32 v83, v89 offset:1340
	ds_load_b96 v[34:36], v89 offset:1392
	v_add_co_u32 v88, s0, s2, v67
	s_waitcnt lgkmcnt(8)
	v_fmac_f32_e32 v110, v54, v85
	ds_load_b32 v85, v89 offset:1100
	ds_load_2addr_b32 v[65:66], v0 offset0:24 offset1:29
	ds_load_2addr_b32 v[63:64], v0 offset0:44 offset1:49
	ds_load_2addr_b32 v[61:62], v0 offset0:64 offset1:69
	ds_load_2addr_b32 v[59:60], v0 offset0:84 offset1:89
	v_add_co_ci_u32_e64 v89, s0, s3, v68, s0
	s_waitcnt lgkmcnt(12)
	v_fmac_f32_e32 v110, v53, v31
	s_movk_i32 s0, 0x810
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[67:68], null, v98, s0, 0x1020
	s_waitcnt lgkmcnt(10)
	v_fmac_f32_e32 v110, v56, v90
	s_waitcnt lgkmcnt(8)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v110, v55, v92
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v110, v58, v12
	s_waitcnt lgkmcnt(5)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v110, v57, v34
	global_store_b32 v[88:89], v110, off
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB0_25
; %bb.24:
	v_dual_mov_b32 v89, 0 :: v_dual_add_nc_u32 v88, v67, v109
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[88:89], 2, v[88:89]
	v_add_co_u32 v88, s0, s4, v88
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v89, s0, s5, v89, s0
	global_load_b32 v0, v[88:89], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v105, v0
.LBB0_25:                               ; %._crit_edge238
	s_or_b32 exec_lo, exec_lo, s1
	v_dual_mov_b32 v68, 0 :: v_dual_add_nc_u32 v67, v67, v96
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[88:89], 2, v[67:68]
	v_add_co_u32 v88, s0, s4, v88
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v89, s0, s5, v89, s0
	global_load_b32 v0, v[88:89], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v105, v0 offset:64
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_27
; %bb.26:
	s_clause 0x1
	global_load_b32 v0, v105, s[6:7]
	global_load_b32 v2, v105, s[6:7] offset:64
	v_mad_u32_u24 v4, v108, 20, 0x448
	s_waitcnt vmcnt(0)
	ds_store_2addr_b32 v4, v0, v2 offset1:1
.LBB0_27:
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_fmac_f32 v107, v38, v18 :: v_dual_mov_b32 v4, 0x45c
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_fmac_f32_e32 v107, v37, v113
	v_add3_u32 v67, v109, v94, 0x1000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v8, 0x4ac :: v_dual_fmac_f32 v107, v40, v81
	v_fmac_f32_e32 v107, v39, v82
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v107, v42, v21
	v_fmac_f32_e32 v107, v41, v114
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v107, v44, v79
	v_fmac_f32_e32 v107, v43, v80
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v107, v46, v24
	v_fmac_f32_e32 v107, v45, v115
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v107, v48, v77
	v_fmac_f32_e32 v107, v47, v78
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v107, v71, v27
	v_fmac_f32_e32 v107, v70, v116
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v107, v74, v75
	v_fmac_f32_e32 v107, v73, v76
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v107, v20, v1
	v_fmac_f32_e32 v107, v19, v3
	ds_load_2addr_b64 v[0:3], v68 offset0:137 offset1:142
	ds_load_2addr_b32 v[17:18], v105 offset0:15 offset1:16
	ds_load_2addr_b32 v[27:28], v4 offset1:1
	v_dual_mov_b32 v4, 0x484 :: v_dual_fmac_f32 v107, v23, v5
	ds_load_2addr_b32 v[37:38], v4 offset1:1
	v_fmac_f32_e32 v107, v22, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v107, v26, v9
	v_mov_b32_e32 v9, 0x4d4
	v_fmac_f32_e32 v107, v25, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v107, v50, v7
	v_fmac_f32_e32 v107, v49, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v107, v52, v69
	v_fmac_f32_e32 v107, v51, v84
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v107, v54, v86
	v_fmac_f32_e32 v107, v53, v32
	ds_load_2addr_b32 v[31:32], v105 offset0:13 offset1:14
	v_fmac_f32_e32 v107, v56, v91
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v107, v55, v93
	v_fmac_f32_e32 v107, v58, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v107, v57, v35
	ds_load_2addr_b32 v[34:35], v105 offset0:11 offset1:12
	ds_load_2addr_b64 v[4:7], v68 offset0:147 offset1:152
	ds_load_2addr_b32 v[46:47], v8 offset1:1
	ds_load_2addr_b32 v[41:42], v9 offset1:1
	ds_load_2addr_b32 v[69:70], v105 offset0:9 offset1:10
	ds_load_2addr_b64 v[12:15], v68 offset0:157 offset1:162
	s_waitcnt lgkmcnt(9)
	v_dual_fmac_f32 v107, v18, v0 :: v_dual_mov_b32 v0, 0x4fc
	ds_load_2addr_b32 v[77:78], v105 offset0:7 offset1:8
	ds_load_2addr_b32 v[79:80], v0 offset1:1
	s_waitcnt lgkmcnt(10)
	v_fmac_f32_e32 v107, v17, v27
	ds_load_2addr_b32 v[39:40], v105 offset0:5 offset1:6
	s_waitcnt lgkmcnt(9)
	v_dual_mov_b32 v0, 0x524 :: v_dual_fmac_f32 v107, v32, v2
	v_mov_b32_e32 v2, 0x574
	ds_load_2addr_b32 v[71:72], v0 offset1:1
	ds_load_2addr_b32 v[43:44], v105 offset0:3 offset1:4
	ds_load_2addr_b64 v[8:11], v68 offset0:167 offset1:172
	v_dual_mov_b32 v0, 0x54c :: v_dual_fmac_f32 v107, v31, v37
	ds_load_2addr_b32 v[81:82], v0 offset1:1
	ds_load_2addr_b32 v[73:74], v2 offset1:1
	s_waitcnt lgkmcnt(12)
	v_fmac_f32_e32 v107, v35, v4
	ds_load_2addr_b32 v[75:76], v105 offset0:1 offset1:2
	s_waitcnt lgkmcnt(12)
	v_fmac_f32_e32 v107, v34, v46
	v_lshlrev_b64 v[45:46], 2, v[67:68]
	s_waitcnt lgkmcnt(10)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v107, v70, v6
	v_add_co_u32 v67, s0, s2, v45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v68, s0, s3, v46, s0
	v_fmac_f32_e32 v107, v69, v41
	s_movk_i32 s0, 0x810
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[45:46], null, v98, s0, 0x1830
	s_waitcnt lgkmcnt(8)
	v_fmac_f32_e32 v107, v78, v12
	s_waitcnt lgkmcnt(7)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v107, v77, v79
	s_waitcnt lgkmcnt(6)
	v_fmac_f32_e32 v107, v40, v14
	s_waitcnt lgkmcnt(5)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v107, v39, v71
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v107, v44, v8
	s_waitcnt lgkmcnt(2)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v107, v43, v81
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v107, v76, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v107, v75, v73
	global_store_b32 v[67:68], v107, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB0_29
; %bb.28:
	v_dual_mov_b32 v68, 0 :: v_dual_add_nc_u32 v67, v45, v109
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[67:68], 2, v[67:68]
	v_add_co_u32 v67, s0, s4, v67
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v68, s0, s5, v68, s0
	global_load_b32 v0, v[67:68], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v105, v0
.LBB0_29:                               ; %._crit_edge237
	s_or_b32 exec_lo, exec_lo, s1
	v_dual_mov_b32 v46, 0 :: v_dual_add_nc_u32 v45, v45, v96
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[67:68], 2, v[45:46]
	v_add_co_u32 v67, s0, s4, v67
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v68, s0, s5, v68, s0
	global_load_b32 v0, v[67:68], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v105, v0 offset:64
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_31
; %bb.30:
	global_load_b32 v0, v105, s[6:7]
	s_waitcnt vmcnt(0)
	ds_store_b32 v111, v0 offset:1100
.LBB0_31:
	s_or_b32 exec_lo, exec_lo, s0
	v_fmac_f32_e32 v106, v20, v85
	v_add_nc_u32_e64 v12, 0x400, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_fmac_f32_e32 v106, v19, v65
	v_add3_u32 v45, v109, v94, 0x1800
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v106, v23, v66
	v_fmac_f32_e32 v106, v22, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v106, v26, v87
	v_fmac_f32_e32 v106, v25, v63
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v106, v50, v64
	v_fmac_f32_e32 v106, v49, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v106, v52, v95
	v_fmac_f32_e32 v106, v51, v61
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v106, v54, v62
	v_fmac_f32_e32 v106, v53, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v106, v56, v83
	v_fmac_f32_e32 v106, v55, v59
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v106, v58, v60
	v_fmac_f32_e32 v106, v57, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v106, v18, v1
	ds_load_2addr_b32 v[0:1], v12 offset0:19 offset1:24
	v_fmac_f32_e32 v106, v17, v28
	v_fmac_f32_e32 v106, v32, v3
	ds_load_2addr_b32 v[2:3], v105 offset0:15 offset1:16
	v_fmac_f32_e32 v106, v31, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v106, v35, v5
	ds_load_2addr_b32 v[4:5], v12 offset0:29 offset1:34
	v_fmac_f32_e32 v106, v34, v47
	v_fmac_f32_e32 v106, v70, v7
	ds_load_2addr_b32 v[6:7], v105 offset0:13 offset1:14
	v_fmac_f32_e32 v106, v69, v42
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v106, v78, v13
	v_fmac_f32_e32 v106, v77, v80
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v106, v40, v15
	v_fmac_f32_e32 v106, v39, v72
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v106, v44, v9
	ds_load_2addr_b32 v[8:9], v12 offset0:39 offset1:44
	v_fmac_f32_e32 v106, v43, v82
	v_fmac_f32_e32 v106, v76, v11
	ds_load_2addr_b32 v[10:11], v105 offset0:11 offset1:12
	v_fmac_f32_e32 v106, v75, v74
	s_waitcnt lgkmcnt(4)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v106, v3, v0
	v_fmac_f32_e32 v106, v2, v1
	ds_load_2addr_b32 v[0:1], v105 offset0:9 offset1:10
	ds_load_2addr_b32 v[2:3], v12 offset0:49 offset1:54
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v106, v7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v106, v6, v5
	ds_load_2addr_b32 v[6:7], v105 offset0:7 offset1:8
	ds_load_2addr_b32 v[4:5], v12 offset0:59 offset1:64
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v106, v11, v8
	v_fmac_f32_e32 v106, v10, v9
	ds_load_2addr_b32 v[8:9], v12 offset0:69 offset1:74
	ds_load_2addr_b32 v[10:11], v12 offset0:79 offset1:84
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v106, v1, v2
	ds_load_2addr_b32 v[1:2], v105 offset0:5 offset1:6
	v_fmac_f32_e32 v106, v0, v3
	s_waitcnt lgkmcnt(3)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v106, v7, v4
	ds_load_2addr_b32 v[3:4], v105 offset0:3 offset1:4
	v_fmac_f32_e32 v106, v6, v5
	ds_load_2addr_b32 v[5:6], v105 offset0:1 offset1:2
	ds_load_2addr_b32 v[12:13], v12 offset0:89 offset1:94
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v106, v2, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v106, v1, v9
	v_lshlrev_b64 v[0:1], 2, v[45:46]
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v106, v4, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v106, v3, v11
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v106, v6, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v106, v5, v13
	global_store_b32 v[0:1], v106, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4convPfS_S_iiii
		.amdhsa_group_segment_fixed_size 1408
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 119
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z4convPfS_S_iiii, .Lfunc_end0-_Z4convPfS_S_iiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5992
; NumSgprs: 18
; NumVgprs: 119
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1408 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 14
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 119
; Occupancy: 12
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 1408
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4convPfS_S_iiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z4convPfS_S_iiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     119
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
