#include <stdio.h>

//////////////////////////float3////////////////////////////////

inline __device__ float3 operator+(float3 a, float b)
{
	return make_float3(a.x + b, a.y + b, a.z + b);
}

inline __device__ float3 operator-(float3 a, float b)
{
	return make_float3(a.x - b, a.y - b, a.z - b);
}

inline __device__ float3 operator+(float3 a, float3 b)
{
	return make_float3(a.x + b.x, a.y + b.y, a.z + b.z);
}

inline __device__ float3 operator-(float3 a, float3 b)
{
	return make_float3(a.x - b.x, a.y - b.y, a.z - b.z);
}

inline __device__ void operator+=(float3 &a, float3 b)
{
	a.x += b.x;
	a.y += b.y;
	a.z += b.z;
}

inline __device__ void operator-=(float3 &a, float3 b)
{
	a.x -= b.x;
	a.y -= b.y;
	a.z -= b.z;
}

inline __device__ float3 operator/(float3 a, float3 b)
{
	return make_float3(a.x/b.x, a.y/b.y, a.z/b.z);
}

inline __device__ float3 operator*(float3 a, float b)
{
	return make_float3(a.x*b, a.y*b, a.z*b);
}

inline __device__ float3 operator*(float a, float3 b)
{
	return make_float3(a*b.x, a*b.y, a*b.z);
}

inline __device__ float3 operator*(float3 a, float3 b)
{
	return make_float3(a.x*b.x, a.y*b.y, a.z*b.z);
}

inline __device__ float3 operator*(float3 a, int3 b)
{
	return make_float3(a.x*b.x, a.y*b.y, a.z*b.z);
}

///////////////////////////int3/////////////////////////////////

inline __device__ int3 operator+(int3 a, int3 b)
{
	return make_int3(a.x + b.x, a.y + b.y, a.z + b.z);
}

inline __device__ int3 operator-(int3 a, int3 b)
{
	return make_int3(a.x - b.x, a.y - b.y, a.z - b.z);
}

inline __device__ int3 operator+(int3 a, int b)
{
	return make_int3(a.x + b, a.y + b, a.z + b);
}

inline __device__ int3 operator-(int3 a, int b)
{
	return make_int3(a.x - b, a.y - b, a.z - b);
}

inline __device__ int3 operator+(int a, int3 b)
{
	return make_int3(a + b.x, a + b.y, a + b.z);
}

inline __device__ int3 operator-(int a, int3 b)
{
	return make_int3(a - b.x, a - b.y, a - b.z);
}

////////////////////////////////////////////////////////////////

inline __device__ int3 clamp(int3 x, int a, int3 b)
{
	return make_int3(max(a, min(x.x, b.x)), max(a, min(x.y, b.y)), max(a, min(x.z, b.z)));
}

inline __device__ int3 clamp(int3 x, int3 a, int b)
{
	return make_int3(max(a.x, min(x.x, b)), max(a.y, min(x.y, b)), max(a.z, min(x.z, b)));
}

inline __device__ int3 floorf(float3 v)
{
	return make_int3(floorf(v.x), floorf(v.y), floorf(v.z));
}

inline __device__ float3 round(float3 v)
{
	return make_float3(round(v.x), round(v.y), round(v.z));
}

inline __device__ int dot(int3 a, int3 b)
{
	return a.x*b.x + a.y*b.y + a.z*b.z;
}

inline __device__ float dot(float3 a, float3 b)
{
	return a.x*b.x + a.y*b.y + a.z*b.z;
}

inline __device__ int mod(int a, int b)
{
	int k = a % b;

	return (k < 0) ? (k + b) : k;
}

inline __device__ int3 mod(int3 a, int3 b)
{
	return make_int3(mod(a.x,b.x), mod(a.y,b.y), mod(a.z,b.z));
}

////////////////////////////////////////////////////////////////

struct BinStep
{
	int3 positive, negative;
};

inline __device__ int3 getLocalBinIndex(float3 coordinate, float3 binLength, int3 binDim)
{
	return clamp(floorf(coordinate/binLength), 0, binDim - 1);
}

inline __device__ int getBinIndex(int3 localBinIndex, int3 binDim)
{
	return dot(localBinIndex, make_int3(1, binDim.x, binDim.x*binDim.y));
}

inline __device__ void stepLimit(int &positive, int &negative, int binDim)
{
	if (positive - negative > binDim - 1)
	{
		if (positive > -negative)
		{
			positive = negative + binDim - 1;
		}
		else
		{
			negative = positive - binDim + 1;
		}
	}
}

inline __device__ void lennardJones(float3 &ljF, float &ljU, float3 R, float r2, float eps, float sig)
{
	float sr = sig*sig/r2;
	sr = sr*sr*sr;

	ljF += eps/r2*(2.0f*sr*sr - sr)*R;
	ljU += eps*(sr*sr - sr);
}

__device__ BinStep getBinStep(float3 coordinate, float3 binLength, int3 binDim, int3 localBinIndex, float cutoff)
{
	struct BinStep binStep;

	binStep.positive = clamp(floorf((coordinate + cutoff)/binLength) - localBinIndex, 0, binDim - 1);
	binStep.negative = clamp(floorf((coordinate - cutoff)/binLength) - localBinIndex, 1 - binDim, 0);

	stepLimit(binStep.positive.x, binStep.negative.x, binDim.x);
	stepLimit(binStep.positive.y, binStep.negative.y, binDim.y);
	stepLimit(binStep.positive.z, binStep.negative.z, binDim.z);

	return binStep;
}

////////////////////////////////////////////////////////////////

extern "C"
__global__ void fillBins(float3 *coordinate, int *binIndex, unsigned int *binCount,
		float3 binLength, int3 binDim, unsigned int arraySize)
{
	unsigned int idg = blockIdx.x*blockDim.x + threadIdx.x;

	if (idg < arraySize)
	{
		int idB = getBinIndex(getLocalBinIndex(coordinate[idg], binLength, binDim), binDim);

		binIndex[idg] = idB;
		atomicInc(&binCount[idB], arraySize);
	}
}

extern "C"
__global__ void countingSort(int *binIndex, unsigned int *prefixSum,
		float3 *coordinate, float3 *velocity,
		float3 *coordinateSorted, float3 *velocitySorted,
		unsigned int arraySize)
{
	unsigned int idg = blockIdx.x*blockDim.x + threadIdx.x;

	if (idg < arraySize)
	{
		unsigned int idgSorted = atomicDec(&prefixSum[binIndex[idg]], arraySize) - 1u;

		coordinateSorted[idgSorted] = coordinate[idg];
		velocitySorted[idgSorted] = velocity[idg];
	}
}

extern "C"
__global__ void ljForce(float3 *coordinateSorted, float3 *force,
		float *potentialEnergy, unsigned int *binCount, unsigned int *prefixSum,
		float3 boxSize, float3 binLength, int3 binDim, float cutoff, float eps, float sig,
		unsigned int arraySize)
{
	unsigned int idg = blockIdx.x*blockDim.x + threadIdx.x;

	if (idg < arraySize)
	{
		float3 R;
		float r2;
		int binIndexNeighbour;
		unsigned int ionCount, offset;

		float3 coordinate = coordinateSorted[idg];
		int3 localBinIndex = getLocalBinIndex(coordinate, binLength, binDim);
		struct BinStep binStep = getBinStep(coordinate, binLength, binDim, localBinIndex, cutoff);

		float3 ljF = make_float3(0.0f,0.0f,0.0f);
		float cutoff2 = cutoff*cutoff;
		float ljU = 0.0f;

		for (int dz = binStep.negative.z; dz <= binStep.positive.z; ++dz)
		{
			for (int dy = binStep.negative.y; dy <= binStep.positive.y; ++dy)
			{
				for (int dx = binStep.negative.x; dx <= binStep.positive.x; ++dx)
				{
					binIndexNeighbour = getBinIndex(mod(localBinIndex + make_int3(dx,dy,dz), binDim), binDim);
					ionCount = binCount[binIndexNeighbour];

					if (ionCount == 0u)
					{
						continue;
					}
					offset = prefixSum[binIndexNeighbour];

					for (unsigned int i = offset; i < offset + ionCount; ++i)
					{
						if (i == idg)
						{
							continue;
						}

						R = coordinate - coordinateSorted[i];
						r2 = dot(R, R);

						if (r2 < cutoff2)
						{
							lennardJones(ljF, ljU, R, r2, eps, sig);
							continue;
						}

						R -= boxSize*round(R/boxSize);
						r2 = dot(R, R);

						if (r2 < cutoff2)
						{
							lennardJones(ljF, ljU, R, r2, eps, sig);
						}
					}
				}
			}
		}
		force[idg] = 24.0f*ljF;
		potentialEnergy[idg] = 2.0f*ljU;
	}
}

extern "C"
__global__ void verletPre(float3 *coordinate, float3 *velocity,
		float3 *coordinateSorted, float3 *velocitySorted,
		float3 *force, float3 boxSize, float mass, float dt, unsigned int arraySize)
{
	unsigned int idg = blockIdx.x*blockDim.x + threadIdx.x;

	if (idg < arraySize)
	{
		float3 coord, vel;

		vel = velocitySorted[idg];
		coord = coordinateSorted[idg];

		vel += 0.00482426665f*dt/mass*force[idg]; // 0.00964853329 * 0.5
		coord += dt*vel;

		velocity[idg] = vel;
		coordinate[idg] = coord - boxSize*floorf(coord/boxSize);
	}
}

extern "C"
__global__ void verletPos(float3 *velocitySorted, float3 *force, float *kineticEnergy,
		float mass, float dt, unsigned int arraySize)
{
	unsigned int idg = blockIdx.x*blockDim.x + threadIdx.x;

	if (idg < arraySize)
	{
		float3 vel = velocitySorted[idg];

		vel += 0.00482426665f*dt/mass*force[idg]; // 0.00964853329 * 0.5

		kineticEnergy[idg] = 51.8213479f*mass*dot(vel, vel);
		velocitySorted[idg] = vel;
	}
}




	.file	"tmpxft_00353d67_00000000-6_lj_force.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2059:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z10getBinStep6float3S_4int3S0_f
	.type	_Z10getBinStep6float3S_4int3S0_f, @function
_Z10getBinStep6float3S_4int3S0_f:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movl	$1, 76(%rsp)
	movl	76(%rsp), %edi
	movq	%rsi, 16(%rsp)
	movl	%edx, 24(%rsp)
	movq	%rcx, (%rsp)
	movl	%r8d, 8(%rsp)
	movq	%xmm0, 48(%rsp)
	movss	%xmm1, 56(%rsp)
	movq	%xmm2, 32(%rsp)
	movss	%xmm3, 40(%rsp)
	call	exit@PLT
	.cfi_endproc
.LFE2056:
	.size	_Z10getBinStep6float3S_4int3S0_f, .-_Z10getBinStep6float3S_4int3S0_f
	.globl	_Z45__device_stub__Z8fillBinsP6float3PiPjS_4int3jP6float3PiPjRS_R4int3j
	.type	_Z45__device_stub__Z8fillBinsP6float3PiPjS_4int3jP6float3PiPjRS_R4int3j, @function
_Z45__device_stub__Z8fillBinsP6float3PiPjS_4int3jP6float3PiPjRS_R4int3j:
.LFB2081:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%rcx, 128(%rsp)
	leaq	48(%rsp), %rcx
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%r8, 136(%rsp)
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	48(%rsp)
	.cfi_def_cfa_offset 184
	leaq	fillBins(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 192
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L4:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2081:
	.size	_Z45__device_stub__Z8fillBinsP6float3PiPjS_4int3jP6float3PiPjRS_R4int3j, .-_Z45__device_stub__Z8fillBinsP6float3PiPjS_4int3jP6float3PiPjRS_R4int3j
	.globl	fillBins
	.type	fillBins, @function
fillBins:
.LFB2082:
	.cfi_startproc
	endbr64
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	%rcx, (%rsp)
	leaq	16(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movq	%rsp, %r8
	movq	%xmm0, 16(%rsp)
	movss	%xmm1, 24(%rsp)
	call	_Z45__device_stub__Z8fillBinsP6float3PiPjS_4int3jP6float3PiPjRS_R4int3j
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2082:
	.size	fillBins, .-fillBins
	.globl	_Z52__device_stub__Z12countingSortPiPjP6float3S2_S2_S2_jPiPjP6float3S2_S2_S2_j
	.type	_Z52__device_stub__Z12countingSortPiPjP6float3S2_S2_S2_jPiPjP6float3S2_S2_S2_j, @function
_Z52__device_stub__Z12countingSortPiPjP6float3S2_S2_S2_jPiPjP6float3S2_S2_S2_j:
.LFB2083:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movq	%rsp, %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	countingSort(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L11:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2083:
	.size	_Z52__device_stub__Z12countingSortPiPjP6float3S2_S2_S2_jPiPjP6float3S2_S2_S2_j, .-_Z52__device_stub__Z12countingSortPiPjP6float3S2_S2_S2_jPiPjP6float3S2_S2_S2_j
	.globl	countingSort
	.type	countingSort, @function
countingSort:
.LFB2084:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__Z12countingSortPiPjP6float3S2_S2_S2_jPiPjP6float3S2_S2_S2_j
	.cfi_endproc
.LFE2084:
	.size	countingSort, .-countingSort
	.globl	_Z55__device_stub__Z7ljForceP6float3S0_PfPjS2_S_S_4int3fffjP6float3S0_PfPjS2_RS_S3_R4int3fffj
	.type	_Z55__device_stub__Z7ljForceP6float3S0_PfPjS2_S_S_4int3fffjP6float3S0_PfPjS2_RS_S3_R4int3fffj, @function
_Z55__device_stub__Z7ljForceP6float3S0_PfPjS2_S_S_4int3fffjP6float3S0_PfPjS2_RS_S3_R4int3fffj:
.LFB2085:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movss	%xmm0, 20(%rsp)
	movss	%xmm1, 16(%rsp)
	movss	%xmm2, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movq	%r9, 176(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	256(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 184(%rsp)
	movq	264(%rsp), %rax
	movl	$1, 108(%rsp)
	movq	%rax, 192(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	80(%rsp)
	.cfi_def_cfa_offset 264
	leaq	ljForce(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 272
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L16:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2085:
	.size	_Z55__device_stub__Z7ljForceP6float3S0_PfPjS2_S_S_4int3fffjP6float3S0_PfPjS2_RS_S3_R4int3fffj, .-_Z55__device_stub__Z7ljForceP6float3S0_PfPjS2_S_S_4int3fffjP6float3S0_PfPjS2_RS_S3_R4int3fffj
	.globl	ljForce
	.type	ljForce, @function
ljForce:
.LFB2086:
	.cfi_startproc
	endbr64
	subq	$48, %rsp
	.cfi_def_cfa_offset 56
	movaps	%xmm0, %xmm7
	movaps	%xmm4, %xmm0
	movss	%xmm1, 32(%rsp)
	movaps	%xmm5, %xmm1
	movq	%xmm2, 8(%rsp)
	movaps	%xmm6, %xmm2
	movq	%xmm7, 24(%rsp)
	movss	%xmm3, 16(%rsp)
	pushq	%r9
	.cfi_def_cfa_offset 64
	leaq	64(%rsp), %rax
	pushq	%rax
	.cfi_def_cfa_offset 72
	leaq	24(%rsp), %rax
	pushq	%rax
	.cfi_def_cfa_offset 80
	leaq	48(%rsp), %r9
	call	_Z55__device_stub__Z7ljForceP6float3S0_PfPjS2_S_S_4int3fffjP6float3S0_PfPjS2_RS_S3_R4int3fffj
	addq	$72, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2086:
	.size	ljForce, .-ljForce
	.globl	_Z51__device_stub__Z9verletPreP6float3S0_S0_S0_S0_S_ffjP6float3S0_S0_S0_S0_RS_ffj
	.type	_Z51__device_stub__Z9verletPreP6float3S0_S0_S0_S0_S_ffjP6float3S0_S0_S0_S0_RS_ffj, @function
_Z51__device_stub__Z9verletPreP6float3S0_S0_S0_S0_S_ffjP6float3S0_S0_S0_S0_RS_ffj:
.LFB2087:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movss	%xmm0, 4(%rsp)
	movss	%xmm1, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movq	%r9, 152(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 160(%rsp)
	movq	%rsp, %rax
	movq	%rax, 168(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	pushq	56(%rsp)
	.cfi_def_cfa_offset 216
	leaq	verletPre(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 224
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L22:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2087:
	.size	_Z51__device_stub__Z9verletPreP6float3S0_S0_S0_S0_S_ffjP6float3S0_S0_S0_S0_RS_ffj, .-_Z51__device_stub__Z9verletPreP6float3S0_S0_S0_S0_S_ffjP6float3S0_S0_S0_S0_RS_ffj
	.globl	verletPre
	.type	verletPre, @function
verletPre:
.LFB2088:
	.cfi_startproc
	endbr64
	subq	$32, %rsp
	.cfi_def_cfa_offset 40
	movaps	%xmm0, %xmm4
	movaps	%xmm2, %xmm0
	movss	%xmm1, 16(%rsp)
	movaps	%xmm3, %xmm1
	movq	%xmm4, 8(%rsp)
	pushq	%r9
	.cfi_def_cfa_offset 48
	leaq	16(%rsp), %r9
	call	_Z51__device_stub__Z9verletPreP6float3S0_S0_S0_S0_S_ffjP6float3S0_S0_S0_S0_RS_ffj
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2088:
	.size	verletPre, .-verletPre
	.globl	_Z42__device_stub__Z9verletPosP6float3S0_PfffjP6float3S0_Pfffj
	.type	_Z42__device_stub__Z9verletPosP6float3S0_PfffjP6float3S0_Pfffj, @function
_Z42__device_stub__Z9verletPosP6float3S0_PfffjP6float3S0_Pfffj:
.LFB2089:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	64(%rsp), %rcx
	movss	%xmm0, 20(%rsp)
	movss	%xmm1, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	verletPos(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L28:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2089:
	.size	_Z42__device_stub__Z9verletPosP6float3S0_PfffjP6float3S0_Pfffj, .-_Z42__device_stub__Z9verletPosP6float3S0_PfffjP6float3S0_Pfffj
	.globl	verletPos
	.type	verletPos, @function
verletPos:
.LFB2090:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z9verletPosP6float3S0_PfffjP6float3S0_Pfffj
	.cfi_endproc
.LFE2090:
	.size	verletPos, .-verletPos
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"verletPos"
.LC1:
	.string	"verletPre"
.LC2:
	.string	"ljForce"
.LC3:
	.string	"countingSort"
.LC4:
	.string	"fillBins"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	verletPos(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	verletPre(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	ljForce(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	countingSort(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	fillBins(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2092:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>

//////////////////////////float3////////////////////////////////

inline __device__ float3 operator+(float3 a, float b)
{
	return make_float3(a.x + b, a.y + b, a.z + b);
}

inline __device__ float3 operator-(float3 a, float b)
{
	return make_float3(a.x - b, a.y - b, a.z - b);
}

inline __device__ float3 operator+(float3 a, float3 b)
{
	return make_float3(a.x + b.x, a.y + b.y, a.z + b.z);
}

inline __device__ float3 operator-(float3 a, float3 b)
{
	return make_float3(a.x - b.x, a.y - b.y, a.z - b.z);
}

inline __device__ void operator+=(float3 &a, float3 b)
{
	a.x += b.x;
	a.y += b.y;
	a.z += b.z;
}

inline __device__ void operator-=(float3 &a, float3 b)
{
	a.x -= b.x;
	a.y -= b.y;
	a.z -= b.z;
}

inline __device__ float3 operator/(float3 a, float3 b)
{
	return make_float3(a.x/b.x, a.y/b.y, a.z/b.z);
}

inline __device__ float3 operator*(float3 a, float b)
{
	return make_float3(a.x*b, a.y*b, a.z*b);
}

inline __device__ float3 operator*(float a, float3 b)
{
	return make_float3(a*b.x, a*b.y, a*b.z);
}

inline __device__ float3 operator*(float3 a, float3 b)
{
	return make_float3(a.x*b.x, a.y*b.y, a.z*b.z);
}

inline __device__ float3 operator*(float3 a, int3 b)
{
	return make_float3(a.x*b.x, a.y*b.y, a.z*b.z);
}

///////////////////////////int3/////////////////////////////////

inline __device__ int3 operator+(int3 a, int3 b)
{
	return make_int3(a.x + b.x, a.y + b.y, a.z + b.z);
}

inline __device__ int3 operator-(int3 a, int3 b)
{
	return make_int3(a.x - b.x, a.y - b.y, a.z - b.z);
}

inline __device__ int3 operator+(int3 a, int b)
{
	return make_int3(a.x + b, a.y + b, a.z + b);
}

inline __device__ int3 operator-(int3 a, int b)
{
	return make_int3(a.x - b, a.y - b, a.z - b);
}

inline __device__ int3 operator+(int a, int3 b)
{
	return make_int3(a + b.x, a + b.y, a + b.z);
}

inline __device__ int3 operator-(int a, int3 b)
{
	return make_int3(a - b.x, a - b.y, a - b.z);
}

////////////////////////////////////////////////////////////////

inline __device__ int3 clamp(int3 x, int a, int3 b)
{
	return make_int3(max(a, min(x.x, b.x)), max(a, min(x.y, b.y)), max(a, min(x.z, b.z)));
}

inline __device__ int3 clamp(int3 x, int3 a, int b)
{
	return make_int3(max(a.x, min(x.x, b)), max(a.y, min(x.y, b)), max(a.z, min(x.z, b)));
}

inline __device__ int3 floorf(float3 v)
{
	return make_int3(floorf(v.x), floorf(v.y), floorf(v.z));
}

inline __device__ float3 round(float3 v)
{
	return make_float3(round(v.x), round(v.y), round(v.z));
}

inline __device__ int dot(int3 a, int3 b)
{
	return a.x*b.x + a.y*b.y + a.z*b.z;
}

inline __device__ float dot(float3 a, float3 b)
{
	return a.x*b.x + a.y*b.y + a.z*b.z;
}

inline __device__ int mod(int a, int b)
{
	int k = a % b;

	return (k < 0) ? (k + b) : k;
}

inline __device__ int3 mod(int3 a, int3 b)
{
	return make_int3(mod(a.x,b.x), mod(a.y,b.y), mod(a.z,b.z));
}

////////////////////////////////////////////////////////////////

struct BinStep
{
	int3 positive, negative;
};

inline __device__ int3 getLocalBinIndex(float3 coordinate, float3 binLength, int3 binDim)
{
	return clamp(floorf(coordinate/binLength), 0, binDim - 1);
}

inline __device__ int getBinIndex(int3 localBinIndex, int3 binDim)
{
	return dot(localBinIndex, make_int3(1, binDim.x, binDim.x*binDim.y));
}

inline __device__ void stepLimit(int &positive, int &negative, int binDim)
{
	if (positive - negative > binDim - 1)
	{
		if (positive > -negative)
		{
			positive = negative + binDim - 1;
		}
		else
		{
			negative = positive - binDim + 1;
		}
	}
}

inline __device__ void lennardJones(float3 &ljF, float &ljU, float3 R, float r2, float eps, float sig)
{
	float sr = sig*sig/r2;
	sr = sr*sr*sr;

	ljF += eps/r2*(2.0f*sr*sr - sr)*R;
	ljU += eps*(sr*sr - sr);
}

__device__ BinStep getBinStep(float3 coordinate, float3 binLength, int3 binDim, int3 localBinIndex, float cutoff)
{
	struct BinStep binStep;

	binStep.positive = clamp(floorf((coordinate + cutoff)/binLength) - localBinIndex, 0, binDim - 1);
	binStep.negative = clamp(floorf((coordinate - cutoff)/binLength) - localBinIndex, 1 - binDim, 0);

	stepLimit(binStep.positive.x, binStep.negative.x, binDim.x);
	stepLimit(binStep.positive.y, binStep.negative.y, binDim.y);
	stepLimit(binStep.positive.z, binStep.negative.z, binDim.z);

	return binStep;
}

////////////////////////////////////////////////////////////////

extern "C"
__global__ void fillBins(float3 *coordinate, int *binIndex, unsigned int *binCount,
		float3 binLength, int3 binDim, unsigned int arraySize)
{
	unsigned int idg = blockIdx.x*blockDim.x + threadIdx.x;

	if (idg < arraySize)
	{
		int idB = getBinIndex(getLocalBinIndex(coordinate[idg], binLength, binDim), binDim);

		binIndex[idg] = idB;
		atomicInc(&binCount[idB], arraySize);
	}
}

extern "C"
__global__ void countingSort(int *binIndex, unsigned int *prefixSum,
		float3 *coordinate, float3 *velocity,
		float3 *coordinateSorted, float3 *velocitySorted,
		unsigned int arraySize)
{
	unsigned int idg = blockIdx.x*blockDim.x + threadIdx.x;

	if (idg < arraySize)
	{
		unsigned int idgSorted = atomicDec(&prefixSum[binIndex[idg]], arraySize) - 1u;

		coordinateSorted[idgSorted] = coordinate[idg];
		velocitySorted[idgSorted] = velocity[idg];
	}
}

extern "C"
__global__ void ljForce(float3 *coordinateSorted, float3 *force,
		float *potentialEnergy, unsigned int *binCount, unsigned int *prefixSum,
		float3 boxSize, float3 binLength, int3 binDim, float cutoff, float eps, float sig,
		unsigned int arraySize)
{
	unsigned int idg = blockIdx.x*blockDim.x + threadIdx.x;

	if (idg < arraySize)
	{
		float3 R;
		float r2;
		int binIndexNeighbour;
		unsigned int ionCount, offset;

		float3 coordinate = coordinateSorted[idg];
		int3 localBinIndex = getLocalBinIndex(coordinate, binLength, binDim);
		struct BinStep binStep = getBinStep(coordinate, binLength, binDim, localBinIndex, cutoff);

		float3 ljF = make_float3(0.0f,0.0f,0.0f);
		float cutoff2 = cutoff*cutoff;
		float ljU = 0.0f;

		for (int dz = binStep.negative.z; dz <= binStep.positive.z; ++dz)
		{
			for (int dy = binStep.negative.y; dy <= binStep.positive.y; ++dy)
			{
				for (int dx = binStep.negative.x; dx <= binStep.positive.x; ++dx)
				{
					binIndexNeighbour = getBinIndex(mod(localBinIndex + make_int3(dx,dy,dz), binDim), binDim);
					ionCount = binCount[binIndexNeighbour];

					if (ionCount == 0u)
					{
						continue;
					}
					offset = prefixSum[binIndexNeighbour];

					for (unsigned int i = offset; i < offset + ionCount; ++i)
					{
						if (i == idg)
						{
							continue;
						}

						R = coordinate - coordinateSorted[i];
						r2 = dot(R, R);

						if (r2 < cutoff2)
						{
							lennardJones(ljF, ljU, R, r2, eps, sig);
							continue;
						}

						R -= boxSize*round(R/boxSize);
						r2 = dot(R, R);

						if (r2 < cutoff2)
						{
							lennardJones(ljF, ljU, R, r2, eps, sig);
						}
					}
				}
			}
		}
		force[idg] = 24.0f*ljF;
		potentialEnergy[idg] = 2.0f*ljU;
	}
}

extern "C"
__global__ void verletPre(float3 *coordinate, float3 *velocity,
		float3 *coordinateSorted, float3 *velocitySorted,
		float3 *force, float3 boxSize, float mass, float dt, unsigned int arraySize)
{
	unsigned int idg = blockIdx.x*blockDim.x + threadIdx.x;

	if (idg < arraySize)
	{
		float3 coord, vel;

		vel = velocitySorted[idg];
		coord = coordinateSorted[idg];

		vel += 0.00482426665f*dt/mass*force[idg]; // 0.00964853329 * 0.5
		coord += dt*vel;

		velocity[idg] = vel;
		coordinate[idg] = coord - boxSize*floorf(coord/boxSize);
	}
}

extern "C"
__global__ void verletPos(float3 *velocitySorted, float3 *force, float *kineticEnergy,
		float mass, float dt, unsigned int arraySize)
{
	unsigned int idg = blockIdx.x*blockDim.x + threadIdx.x;

	if (idg < arraySize)
	{
		float3 vel = velocitySorted[idg];

		vel += 0.00482426665f*dt/mass*force[idg]; // 0.00964853329 * 0.5

		kineticEnergy[idg] = 51.8213479f*mass*dot(vel, vel);
		velocitySorted[idg] = vel;
	}
}




	.text
	.file	"lj_force.hip"
	.globl	__device_stub__fillBins         # -- Begin function __device_stub__fillBins
	.type	__device_stub__fillBins,@function
__device_stub__fillBins:                # @__device_stub__fillBins
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	96(%rsp), %rax
	movlps	%xmm0, (%rax)
	movss	%xmm1, 8(%rax)
	leaq	80(%rsp), %r10
	movq	%rcx, (%r10)
	movl	%r8d, 8(%r10)
	leaq	40(%rsp), %rcx
	movq	%rdi, (%rcx)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%r9d, (%rdx)
	leaq	112(%rsp), %rbx
	movq	%rcx, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rax, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rdx, 40(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$fillBins, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__fillBins, .Lfunc_end0-__device_stub__fillBins
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__countingSort     # -- Begin function __device_stub__countingSort
	.type	__device_stub__countingSort,@function
__device_stub__countingSort:            # @__device_stub__countingSort
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$countingSort, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	__device_stub__countingSort, .Lfunc_end1-__device_stub__countingSort
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__ljForce          # -- Begin function __device_stub__ljForce
	.type	__device_stub__ljForce,@function
__device_stub__ljForce:                 # @__device_stub__ljForce
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$240, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	128(%rsp), %rax
	movlps	%xmm0, (%rax)
	movss	%xmm1, 8(%rax)
	leaq	112(%rsp), %r10
	movlps	%xmm2, (%r10)
	movss	%xmm3, 8(%r10)
	leaq	72(%rsp), %r11
	movq	%rdi, (%r11)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	20(%rsp), %r8
	movss	%xmm4, (%r8)
	leaq	16(%rsp), %r14
	movss	%xmm5, (%r14)
	leaq	12(%rsp), %r15
	movss	%xmm6, (%r15)
	leaq	8(%rsp), %r12
	movl	%r9d, (%r12)
	leaq	144(%rsp), %rbx
	movq	%r11, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%rax, 40(%rbx)
	movq	%r10, 48(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 56(%rbx)
	movq	%r8, 64(%rbx)
	movq	%r14, 72(%rbx)
	movq	%r15, 80(%rbx)
	movq	%r12, 88(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$ljForce, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$256, %rsp                      # imm = 0x100
	.cfi_adjust_cfa_offset -256
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	__device_stub__ljForce, .Lfunc_end2-__device_stub__ljForce
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__verletPre        # -- Begin function __device_stub__verletPre
	.type	__device_stub__verletPre,@function
__device_stub__verletPre:               # @__device_stub__verletPre
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	112(%rsp), %rax
	movlps	%xmm0, (%rax)
	movss	%xmm1, 8(%rax)
	leaq	72(%rsp), %r10
	movq	%rdi, (%r10)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	20(%rsp), %r8
	movss	%xmm2, (%r8)
	leaq	16(%rsp), %r11
	movss	%xmm3, (%r11)
	leaq	12(%rsp), %r14
	movl	%r9d, (%r14)
	leaq	128(%rsp), %rbx
	movq	%r10, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%rax, 40(%rbx)
	movq	%r8, 48(%rbx)
	movq	%r11, 56(%rbx)
	movq	%r14, 64(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$verletPre, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	__device_stub__verletPre, .Lfunc_end3-__device_stub__verletPre
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__verletPos        # -- Begin function __device_stub__verletPos
	.type	__device_stub__verletPos,@function
__device_stub__verletPos:               # @__device_stub__verletPos
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	16(%rsp), %r8
	movss	%xmm1, (%r8)
	leaq	12(%rsp), %r9
	movl	%ecx, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r8, 32(%rbx)
	movq	%r9, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$verletPos, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	__device_stub__verletPos, .Lfunc_end4-__device_stub__verletPos
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$fillBins, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$countingSort, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$ljForce, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$verletPre, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$verletPos, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	fillBins,@object                # @fillBins
	.section	.rodata,"a",@progbits
	.globl	fillBins
	.p2align	3, 0x0
fillBins:
	.quad	__device_stub__fillBins
	.size	fillBins, 8

	.type	countingSort,@object            # @countingSort
	.globl	countingSort
	.p2align	3, 0x0
countingSort:
	.quad	__device_stub__countingSort
	.size	countingSort, 8

	.type	ljForce,@object                 # @ljForce
	.globl	ljForce
	.p2align	3, 0x0
ljForce:
	.quad	__device_stub__ljForce
	.size	ljForce, 8

	.type	verletPre,@object               # @verletPre
	.globl	verletPre
	.p2align	3, 0x0
verletPre:
	.quad	__device_stub__verletPre
	.size	verletPre, 8

	.type	verletPos,@object               # @verletPos
	.globl	verletPos
	.p2align	3, 0x0
verletPos:
	.quad	__device_stub__verletPos
	.size	verletPos, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"fillBins"
	.size	.L__unnamed_1, 9

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"countingSort"
	.size	.L__unnamed_2, 13

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"ljForce"
	.size	.L__unnamed_3, 8

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"verletPre"
	.size	.L__unnamed_4, 10

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"verletPos"
	.size	.L__unnamed_5, 10

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__fillBins
	.addrsig_sym __device_stub__countingSort
	.addrsig_sym __device_stub__ljForce
	.addrsig_sym __device_stub__verletPre
	.addrsig_sym __device_stub__verletPos
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym fillBins
	.addrsig_sym countingSort
	.addrsig_sym ljForce
	.addrsig_sym verletPre
	.addrsig_sym verletPos
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	fillBins                ; -- Begin function fillBins
	.globl	fillBins
	.p2align	8
	.type	fillBins,@function
fillBins:                               ; @fillBins
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x44
	s_load_b32 s12, s[0:1], 0x30
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s12, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[2:3], null, v1, 12, s[4:5]
	global_load_b96 v[2:4], v[2:3], off
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x18
	s_load_b64 s[4:5], s[0:1], 0x28
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_div_scale_f32 v0, null, s8, s8, v2
	v_div_scale_f32 v5, null, s9, s9, v3
	v_div_scale_f32 v6, null, s10, s10, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v7, v0
	v_rcp_f32_e32 v8, v5
	v_div_scale_f32 v10, vcc_lo, v2, s8, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(TRANS32_DEP_3)
	v_rcp_f32_e32 v9, v6
	v_div_scale_f32 v11, s0, v3, s9, v3
	v_div_scale_f32 v15, s1, v4, s10, v4
	v_fma_f32 v12, -v0, v7, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v13, -v5, v8, 1.0
	v_fma_f32 v14, -v6, v9, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v7, v12, v7 :: v_dual_fmac_f32 v8, v13, v8
	v_dual_mul_f32 v12, v10, v7 :: v_dual_mul_f32 v13, v11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v16, -v0, v12, v10
	v_fmac_f32_e32 v9, v14, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v17, -v5, v13, v11
	v_fmac_f32_e32 v12, v16, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v14, v15, v9 :: v_dual_fmac_f32 v13, v17, v8
	v_fma_f32 v0, -v0, v12, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v18, -v6, v14, v15
	v_fma_f32 v5, -v5, v13, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v0, v0, v7, v12
	v_fmac_f32_e32 v14, v18, v9
	s_mov_b32 vcc_lo, s0
	s_add_i32 s0, s4, -1
	v_div_fmas_f32 v5, v5, v8, v13
	s_mov_b32 vcc_lo, s1
	v_fma_f32 v6, -v6, v14, v15
	v_div_fixup_f32 v0, v0, s8, v2
	s_add_i32 s1, s5, -1
	v_div_fixup_f32 v3, v5, s9, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v6, v6, v9, v14
	v_floor_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v4, v6, s10, v4
	v_cvt_i32_f32_e32 v2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_floor_f32_e32 v4, v4
	v_cvt_i32_f32_e32 v3, v4
	v_floor_f32_e32 v4, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_minmax_i32 v0, v2, s0, 0
	s_add_i32 s0, s11, -1
	v_minmax_i32 v5, v3, s1, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v4, v4
	v_mad_u64_u32 v[2:3], null, v5, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_minmax_i32 v0, v4, s0, 0
	v_mad_u64_u32 v[3:4], null, v2, s11, v[0:1]
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_ashrrev_i32_e32 v4, 31, v3
	v_mov_b32_e32 v2, s12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_lshlrev_b64 v[4:5], 2, v[3:4]
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	global_store_b32 v[0:1], v3, off
	global_atomic_inc_u32 v[4:5], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel fillBins
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	fillBins, .Lfunc_end0-fillBins
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 576
; NumSgprs: 18
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	countingSort            ; -- Begin function countingSort
	.globl	countingSort
	.p2align	8
	.type	countingSort,@function
countingSort:                           ; @countingSort
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x44
	s_load_b32 s2, s[0:1], 0x30
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e64 s2, v1
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v0, s2
	s_load_b128 s[0:3], s[0:1], 0x20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	global_atomic_dec_u32 v0, v[2:3], v0, off glc
	v_mad_u64_u32 v[2:3], null, v1, 12, s[8:9]
	global_load_b32 v6, v[2:3], off offset:8
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v8, -1, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v8, 12, s[0:1]
	s_waitcnt vmcnt(0)
	global_store_b32 v[4:5], v6, off offset:8
	global_load_b64 v[2:3], v[2:3], off
	v_mad_u64_u32 v[6:7], null, v1, 12, s[10:11]
	v_mad_u64_u32 v[0:1], null, v8, 12, s[2:3]
	s_waitcnt vmcnt(0)
	global_store_b64 v[4:5], v[2:3], off
	global_load_b32 v2, v[6:7], off offset:8
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off offset:8
	global_load_b64 v[2:3], v[6:7], off
	s_waitcnt vmcnt(0)
	global_store_b64 v[0:1], v[2:3], off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel countingSort
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	countingSort, .Lfunc_end1-countingSort
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 300
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	ljForce                 ; -- Begin function ljForce
	.globl	ljForce
	.p2align	8
	.type	ljForce,@function
ljForce:                                ; @ljForce
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x6c
	s_load_b128 s[16:19], s[0:1], 0x4c
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s19, v6
	s_cbranch_execz .LBB2_46
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[0:1], null, v6, 12, s[4:5]
	global_load_b96 v[0:2], v[0:1], off
	s_clause 0x1
	s_load_b128 s[12:15], s[0:1], 0x34
	s_load_b64 s[24:25], s[0:1], 0x44
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_div_scale_f32 v3, null, s12, s12, v0
	v_div_scale_f32 v13, vcc_lo, v0, s12, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v7, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v3, v7, 1.0
	v_dual_add_f32 v4, s16, v0 :: v_dual_fmac_f32 v7, v12, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f32 v8, null, s12, s12, v4
	v_div_scale_f32 v14, s2, v4, s12, v4
	v_mul_f32_e32 v17, v13, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v10, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v8, v10, 1.0
	v_dual_subrev_f32 v5, s16, v0 :: v_dual_fmac_f32 v10, v12, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_scale_f32 v9, null, s12, s12, v5
	v_div_scale_f32 v16, s3, v5, s12, v5
	v_fma_f32 v12, -v3, v17, v13
	v_rcp_f32_e32 v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v12, v7
	v_fma_f32 v3, -v3, v17, v13
	s_waitcnt_depctr 0xfff
	v_fma_f32 v15, -v9, v11, 1.0
	v_div_fmas_f32 v3, v3, v7, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_fmac_f32_e32 v11, v15, v11
	v_mul_f32_e32 v15, v14, v10
	s_mov_b32 vcc_lo, s2
	s_add_i32 s2, s15, -1
	v_div_fixup_f32 v3, v3, s12, v0
	v_mul_f32_e32 v18, v16, v11
	v_fma_f32 v12, -v8, v15, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_floor_f32_e32 v3, v3
	v_fma_f32 v19, -v9, v18, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v15, v12, v10
	v_cvt_i32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v18, v19, v11
	v_fma_f32 v7, -v8, v15, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v8, -v9, v18, v16
	v_div_fmas_f32 v7, v7, v10, v15
	s_mov_b32 vcc_lo, s3
	s_sub_i32 s3, 1, s15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v8, v8, v11, v18
	v_div_fixup_f32 v4, v7, s12, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v5, v8, s12, v5
	v_floor_f32_e32 v4, v4
	v_minmax_i32 v8, v3, s2, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_floor_f32_e32 v5, v5
	v_cvt_i32_f32_e32 v3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v4, v5
	v_sub_nc_u32_e32 v3, v3, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v4, v8
	v_minmax_i32 v9, v3, s2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_minmax_i32 v10, v4, 0, s3
	s_mov_b32 s3, exec_lo
	v_sub_nc_u32_e32 v3, v9, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_le_i32_e64 s15, v3
	s_cbranch_execz .LBB2_7
; %bb.2:
	v_sub_nc_u32_e32 v3, 0, v10
	s_mov_b32 s12, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_le_i32_e64 v9, v3
	s_xor_b32 s12, exec_lo, s12
; %bb.3:
	v_subrev_nc_u32_e32 v3, s15, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v10, 1, v3
; %bb.4:                                ; %Flow523
	s_and_not1_saveexec_b32 s12, s12
; %bb.5:
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v9, s2, v10
; %bb.6:                                ; %Flow524
	s_or_b32 exec_lo, exec_lo, s12
.LBB2_7:                                ; %_Z9stepLimitRiS_i.exit.i
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s3
	v_div_scale_f32 v3, null, s13, s13, v1
	v_div_scale_f32 v16, vcc_lo, v1, s13, v1
	v_rcp_f32_e32 v7, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v15, -v3, v7, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v4, s16, v1 :: v_dual_fmac_f32 v7, v15, v7
	v_subrev_f32_e32 v5, s16, v1
	v_div_scale_f32 v11, null, s13, s13, v4
	v_div_scale_f32 v17, s2, v4, s13, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v20, v16, v7
	v_div_scale_f32 v12, null, s13, s13, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v13, v11
	v_div_scale_f32 v19, s3, v5, s13, v5
	v_rcp_f32_e32 v14, v12
	s_waitcnt_depctr 0xfff
	v_fma_f32 v15, -v11, v13, 1.0
	v_fma_f32 v18, -v12, v14, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v13, v15, v13
	v_fma_f32 v15, -v3, v20, v16
	v_fmac_f32_e32 v14, v18, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v18, v17, v13 :: v_dual_mul_f32 v21, v19, v14
	v_fma_f32 v22, -v12, v21, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v20, v15, v7
	v_fma_f32 v15, -v11, v18, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v21, v22, v14
	v_fma_f32 v3, -v3, v20, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v18, v15, v13
	v_div_fmas_f32 v3, v3, v7, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f32 v7, -v11, v18, v17
	v_fma_f32 v11, -v12, v21, v19
	s_mov_b32 vcc_lo, s2
	s_add_i32 s2, s24, -1
	v_div_fixup_f32 v3, v3, s13, v1
	v_div_fmas_f32 v7, v7, v13, v18
	s_mov_b32 vcc_lo, s3
	s_sub_i32 s3, 1, s24
	v_div_fmas_f32 v11, v11, v14, v21
	v_floor_f32_e32 v3, v3
	v_div_fixup_f32 v4, v7, s13, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v5, v11, s13, v5
	v_cvt_i32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_floor_f32_e32 v4, v4
	s_load_b64 s[12:13], s[0:1], 0x20
	v_floor_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_minmax_i32 v11, v3, s2, 0
	v_cvt_i32_f32_e32 v3, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v4, v5
	v_sub_nc_u32_e32 v3, v3, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v4, v11
	v_minmax_i32 v12, v3, s2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_minmax_i32 v13, v4, 0, s3
	s_mov_b32 s3, exec_lo
	v_sub_nc_u32_e32 v3, v12, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_le_i32_e64 s24, v3
	s_cbranch_execz .LBB2_13
; %bb.8:
	v_sub_nc_u32_e32 v3, 0, v13
	s_mov_b32 s19, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_le_i32_e64 v12, v3
	s_xor_b32 s19, exec_lo, s19
; %bb.9:
	v_subrev_nc_u32_e32 v3, s24, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v13, 1, v3
; %bb.10:                               ; %Flow521
	s_and_not1_saveexec_b32 s19, s19
; %bb.11:
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v12, s2, v13
; %bb.12:                               ; %Flow522
	s_or_b32 exec_lo, exec_lo, s19
.LBB2_13:                               ; %_Z9stepLimitRiS_i.exit279.i
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s3
	v_div_scale_f32 v3, null, s14, s14, v2
	v_div_scale_f32 v19, vcc_lo, v2, s14, v2
	v_rcp_f32_e32 v7, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v18, -v3, v7, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v4, s16, v2 :: v_dual_fmac_f32 v7, v18, v7
	v_div_scale_f32 v14, null, s14, s14, v4
	v_div_scale_f32 v20, s2, v4, s14, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v16, v14
	s_waitcnt_depctr 0xfff
	v_fma_f32 v18, -v14, v16, 1.0
	v_dual_subrev_f32 v5, s16, v2 :: v_dual_fmac_f32 v16, v18, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v15, null, s14, s14, v5
	v_div_scale_f32 v22, s3, v5, s14, v5
	v_rcp_f32_e32 v17, v15
	s_waitcnt_depctr 0xfff
	v_fma_f32 v21, -v15, v17, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v21, v17
	v_dual_mul_f32 v23, v19, v7 :: v_dual_mul_f32 v24, v22, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v18, -v3, v23, v19
	v_fma_f32 v25, -v15, v24, v22
	v_mul_f32_e32 v21, v20, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v23, v18, v7 :: v_dual_fmac_f32 v24, v25, v17
	v_fma_f32 v18, -v14, v21, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v3, -v3, v23, v19
	v_fmac_f32_e32 v21, v18, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v3, v3, v7, v23
	s_mov_b32 vcc_lo, s2
	s_add_i32 s2, s25, -1
	v_fma_f32 v7, -v14, v21, v20
	v_fma_f32 v14, -v15, v24, v22
	v_div_fixup_f32 v3, v3, s14, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v7, v7, v16, v21
	s_mov_b32 vcc_lo, s3
	v_floor_f32_e32 v3, v3
	v_div_fmas_f32 v14, v14, v17, v24
	s_sub_i32 s3, 1, s25
	v_div_fixup_f32 v4, v7, s14, v4
	v_mov_b32_e32 v7, 0
	v_cvt_i32_f32_e32 v3, v3
	v_div_fixup_f32 v5, v14, s14, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_floor_f32_e32 v4, v4
	v_minmax_i32 v14, v3, s2, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_floor_f32_e32 v5, v5
	v_cvt_i32_f32_e32 v3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v4, v5
	v_sub_nc_u32_e32 v3, v3, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v4, v14
	v_minmax_i32 v15, v3, s2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_minmax_i32 v16, v4, 0, s3
	s_mov_b32 s3, exec_lo
	v_sub_nc_u32_e32 v3, v15, v16
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_le_i32_e64 s25, v3
	s_cbranch_execz .LBB2_19
; %bb.14:
	v_sub_nc_u32_e32 v3, 0, v16
	s_mov_b32 s14, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_le_i32_e64 v15, v3
	s_xor_b32 s14, exec_lo, s14
; %bb.15:
	v_subrev_nc_u32_e32 v3, s25, v15
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v16, 1, v3
; %bb.16:                               ; %Flow519
	s_and_not1_saveexec_b32 s14, s14
; %bb.17:
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v15, s2, v16
; %bb.18:                               ; %Flow520
	s_or_b32 exec_lo, exec_lo, s14
.LBB2_19:                               ; %_Z10getBinStep15HIP_vector_typeIfLj3EES0_S_IiLj3EES1_f.exit
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v17, v7
	v_mov_b32_e32 v3, v7
	v_mov_b32_e32 v4, v7
	v_mov_b32_e32 v5, v7
	s_mov_b32 s19, 0
	s_mov_b32 s14, exec_lo
	v_cmpx_le_i32_e64 v16, v15
	s_cbranch_execz .LBB2_45
; %bb.20:                               ; %.preheader411.lr.ph
	s_ashr_i32 s2, s24, 31
	s_ashr_i32 s3, s25, 31
	s_add_i32 s20, s24, s2
	s_ashr_i32 s21, s15, 31
	s_xor_b32 s26, s20, s2
	s_add_i32 s2, s25, s3
	v_cvt_f32_u32_e32 v3, s26
	s_xor_b32 s27, s2, s3
	s_add_i32 s20, s15, s21
	v_cvt_f32_u32_e32 v4, s27
	s_xor_b32 s28, s20, s21
	v_rcp_iflag_f32_e32 v3, v3
	v_cvt_f32_u32_e32 v5, s28
	s_sub_i32 s3, 0, s27
	v_rcp_iflag_f32_e32 v4, v4
	s_sub_i32 s2, 0, s26
	s_sub_i32 s20, 0, s28
	v_rcp_iflag_f32_e32 v5, v5
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
	s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v20, 0 :: v_dual_mul_f32 v3, 0x4f7ffffe, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x4f7ffffe, v4
	v_cvt_u32_f32_e32 v3, v3
	v_mul_f32_e32 v5, 0x4f7ffffe, v5
	v_cvt_u32_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v17, s2, v3
	v_mul_lo_u32 v18, s3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v22, v3, v17
	v_mul_f32_e64 v17, s18, s18
	v_mul_hi_u32 v23, v4, v18
	v_mov_b32_e32 v18, 0
	v_cvt_u32_f32_e32 v21, v5
	v_mul_f32_e64 v5, s16, s16
	v_add_nc_u32_e32 v22, v3, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v19, s20, v21
	s_load_b128 s[20:23], s[0:1], 0x28
	v_cmp_le_i32_e64 s0, v13, v12
	v_cmp_le_i32_e64 s1, v10, v9
	v_add_nc_u32_e32 v23, v4, v23
	v_mul_hi_u32 v24, v21, v19
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v19, 0 :: v_dual_add_nc_u32 v24, v21, v24
	v_mov_b32_e32 v21, 0
.LBB2_21:                               ; %.preheader411
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_23 Depth 2
                                        ;       Child Loop BB2_25 Depth 3
                                        ;         Child Loop BB2_28 Depth 4
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB2_43
; %bb.22:                               ; %.preheader.lr.ph
                                        ;   in Loop: Header=BB2_21 Depth=1
	v_dual_mov_b32 v26, v13 :: v_dual_add_nc_u32 v3, v16, v14
	s_mov_b32 s18, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_add_nc_u32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v3, v4
	v_mul_hi_u32 v25, v3, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v25, v25, s27
	v_sub_nc_u32_e32 v3, v3, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v25, s27, v3
	v_cmp_le_u32_e32 vcc_lo, s27, v3
	v_cndmask_b32_e32 v3, v3, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v25, s27, v3
	v_cmp_le_u32_e32 vcc_lo, s27, v3
	v_cndmask_b32_e32 v3, v3, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v3, v4
	v_sub_nc_u32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_and_b32_e32 v4, s25, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v4, v3
	v_mul_lo_u32 v25, v3, s24
.LBB2_23:                               ; %.preheader
                                        ;   Parent Loop BB2_21 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB2_25 Depth 3
                                        ;         Child Loop BB2_28 Depth 4
	s_waitcnt lgkmcnt(0)
	s_and_saveexec_b32 s23, s1
	s_cbranch_execz .LBB2_41
; %bb.24:                               ; %.lr.ph426
                                        ;   in Loop: Header=BB2_23 Depth=2
	v_add_nc_u32_e32 v3, v26, v11
	s_mov_b32 s29, 0
	v_mov_b32_e32 v28, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_add_nc_u32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v3, v4
	v_mul_hi_u32 v27, v3, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v27, v27, s26
	v_sub_nc_u32_e32 v3, v3, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v27, s26, v3
	v_cmp_le_u32_e32 vcc_lo, s26, v3
	v_cndmask_b32_e32 v3, v3, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v27, s26, v3
	v_cmp_le_u32_e32 vcc_lo, s26, v3
	v_cndmask_b32_e32 v3, v3, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v3, v4
	v_sub_nc_u32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_and_b32_e32 v4, s24, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v4, v3, v25
	v_mul_lo_u32 v27, v3, s15
.LBB2_25:                               ;   Parent Loop BB2_21 Depth=1
                                        ;     Parent Loop BB2_23 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB2_28 Depth 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v28, v8
	s_mov_b32 s30, exec_lo
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v3, v4
	v_xor_b32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v29, v3, v24
	v_mul_lo_u32 v29, v29, s28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v29
	v_subrev_nc_u32_e32 v29, s28, v3
	v_cmp_le_u32_e32 vcc_lo, s28, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v29, vcc_lo
	v_subrev_nc_u32_e32 v29, s28, v3
	v_cmp_le_u32_e32 vcc_lo, s28, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v29, vcc_lo
	v_xor_b32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v4
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, s15, v4
	v_add3_u32 v3, v4, v3, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v29, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v30, vcc_lo, s11, v4, vcc_lo
	global_load_b32 v29, v[29:30], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 0, v29
	s_cbranch_execz .LBB2_39
; %bb.26:                               ;   in Loop: Header=BB2_25 Depth=3
	v_add_co_u32 v3, vcc_lo, s12, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v4, vcc_lo
	s_mov_b32 s31, exec_lo
	global_load_b32 v30, v[3:4], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, v30, v29
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_u32_e64 v30, v3
	s_cbranch_execz .LBB2_38
; %bb.27:                               ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB2_25 Depth=3
	v_mad_u64_u32 v[3:4], null, v30, 12, s[4:5]
	v_sub_nc_u32_e32 v30, v6, v30
	s_mov_b32 s33, 0
.LBB2_28:                               ; %.lr.ph
                                        ;   Parent Loop BB2_21 Depth=1
                                        ;     Parent Loop BB2_23 Depth=2
                                        ;       Parent Loop BB2_25 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_mov_b32 s34, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v30
	s_cbranch_execz .LBB2_36
; %bb.29:                               ;   in Loop: Header=BB2_28 Depth=4
	global_load_b96 v[31:33], v[3:4], off offset:-4
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v32, v1, v32 :: v_dual_sub_f32 v31, v0, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v33, v2, v33 :: v_dual_mul_f32 v34, v32, v32
	v_fmac_f32_e32 v34, v31, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v34, v33, v33
	v_cmpx_nlt_f32_e32 v34, v5
	s_xor_b32 s35, exec_lo, s2
	s_cbranch_execz .LBB2_33
; %bb.30:                               ;   in Loop: Header=BB2_28 Depth=4
	v_div_scale_f32 v34, null, s20, s20, v31
	v_div_scale_f32 v35, null, s21, s21, v32
	v_div_scale_f32 v37, null, s22, s22, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v36, v34
	v_rcp_f32_e32 v38, v35
	v_div_scale_f32 v41, vcc_lo, v31, s20, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_3)
	v_rcp_f32_e32 v39, v37
	v_div_scale_f32 v43, s2, v32, s21, v32
	v_fma_f32 v40, -v34, v36, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v42, -v35, v38, 1.0
	v_fmac_f32_e32 v36, v40, v36
	v_fma_f32 v40, -v37, v39, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v38, v42, v38
	v_div_scale_f32 v42, s3, v33, s22, v33
	v_dual_mul_f32 v44, v41, v36 :: v_dual_fmac_f32 v39, v40, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v40, v43, v38
	v_fma_f32 v45, -v34, v44, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v46, v42, v39
	v_fma_f32 v47, -v35, v40, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v44, v45, v36
	v_fma_f32 v45, -v37, v46, v42
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v40, v47, v38
	v_fma_f32 v34, -v34, v44, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v46, v45, v39
	v_fma_f32 v35, -v35, v40, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v34, v34, v36, v44
	s_mov_b32 vcc_lo, s2
	v_fma_f32 v36, -v37, v46, v42
	s_delay_alu instid0(VALU_DEP_3)
	v_div_fmas_f32 v35, v35, v38, v40
	s_mov_b32 vcc_lo, s3
	v_div_fixup_f32 v34, v34, s20, v31
	s_mov_b32 s3, exec_lo
	v_div_fmas_f32 v36, v36, v39, v46
	v_div_fixup_f32 v35, v35, s21, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_trunc_f32_e32 v38, v34
	v_div_fixup_f32 v36, v36, s22, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_trunc_f32_e32 v37, v35
	v_sub_f32_e32 v41, v34, v38
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_trunc_f32_e32 v40, v36
	v_dual_sub_f32 v39, v35, v37 :: v_dual_sub_f32 v42, v36, v40
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s2, |v39|, 0.5
	v_cndmask_b32_e64 v39, 0, 1.0, s2
	v_cmp_ge_f32_e64 s2, |v41|, 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_bfi_b32 v35, 0x7fffffff, v39, v35
	v_cndmask_b32_e64 v41, 0, 1.0, s2
	v_cmp_ge_f32_e64 s2, |v42|, 0.5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v35, v37, v35
	v_bfi_b32 v34, 0x7fffffff, v41, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v39, 0, 1.0, s2
	v_fma_f32 v32, -s21, v35, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v34, v38, v34
	v_bfi_b32 v36, 0x7fffffff, v39, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v31, -s20, v34, v31
	v_add_f32_e32 v35, v40, v36
	v_mul_f32_e32 v34, v32, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v33, -s22, v35, v33
	v_fmac_f32_e32 v34, v31, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v34, v33, v33
	v_cmpx_lt_f32_e32 v34, v5
	s_cbranch_execz .LBB2_32
; %bb.31:                               ;   in Loop: Header=BB2_28 Depth=4
	v_div_scale_f32 v35, null, v34, v34, v17
	v_div_scale_f32 v38, null, v34, v34, s17
	v_div_scale_f32 v39, vcc_lo, v17, v34, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v36, v35
	s_waitcnt_depctr 0xfff
	v_fma_f32 v37, -v35, v36, 1.0
	v_fmac_f32_e32 v36, v37, v36
	v_rcp_f32_e32 v37, v38
	s_waitcnt_depctr 0xfff
	v_fma_f32 v42, -v38, v37, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v37, v42, v37 :: v_dual_mul_f32 v40, v39, v36
	v_fma_f32 v41, -v35, v40, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v40, v41, v36
	v_div_scale_f32 v41, s2, s17, v34, s17
	v_fma_f32 v35, -v35, v40, v39
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v39, v41, v37
	v_div_fmas_f32 v35, v35, v36, v40
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v36, -v38, v39, v41
	s_mov_b32 vcc_lo, s2
	v_div_fixup_f32 v35, v35, v34, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v39, v36, v37 :: v_dual_mul_f32 v36, v35, v35
	v_fma_f32 v38, -v38, v39, v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v35, v35, v36
	v_div_fmas_f32 v36, v38, v37, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v34, v36, v34, s17
	v_add_f32_e32 v37, v35, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v36, v35, v37, -v35
	v_mul_f32_e32 v34, v34, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v20, v32, v34
	v_fma_f32 v35, v35, v35, -v35
	v_fmac_f32_e32 v19, v31, v34
	v_dual_fmac_f32 v21, v33, v34 :: v_dual_fmac_f32 v18, s17, v35
.LBB2_32:                               ; %Flow
                                        ;   in Loop: Header=BB2_28 Depth=4
	s_or_b32 exec_lo, exec_lo, s3
                                        ; implicit-def: $vgpr34
                                        ; implicit-def: $vgpr31
                                        ; implicit-def: $vgpr32
                                        ; implicit-def: $vgpr33
.LBB2_33:                               ; %Flow510
                                        ;   in Loop: Header=BB2_28 Depth=4
	s_and_not1_saveexec_b32 s3, s35
	s_cbranch_execz .LBB2_35
; %bb.34:                               ;   in Loop: Header=BB2_28 Depth=4
	v_div_scale_f32 v35, null, v34, v34, v17
	v_div_scale_f32 v38, null, v34, v34, s17
	v_div_scale_f32 v39, vcc_lo, v17, v34, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v36, v35
	s_waitcnt_depctr 0xfff
	v_fma_f32 v37, -v35, v36, 1.0
	v_fmac_f32_e32 v36, v37, v36
	v_rcp_f32_e32 v37, v38
	s_waitcnt_depctr 0xfff
	v_fma_f32 v42, -v38, v37, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v37, v42, v37 :: v_dual_mul_f32 v40, v39, v36
	v_fma_f32 v41, -v35, v40, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v40, v41, v36
	v_div_scale_f32 v41, s2, s17, v34, s17
	v_fma_f32 v35, -v35, v40, v39
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v39, v41, v37
	v_div_fmas_f32 v35, v35, v36, v40
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v36, -v38, v39, v41
	s_mov_b32 vcc_lo, s2
	v_div_fixup_f32 v35, v35, v34, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v39, v36, v37 :: v_dual_mul_f32 v36, v35, v35
	v_fma_f32 v38, -v38, v39, v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v35, v35, v36
	v_div_fmas_f32 v36, v38, v37, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v34, v36, v34, s17
	v_add_f32_e32 v37, v35, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v36, v35, v37, -v35
	v_mul_f32_e32 v34, v34, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v20, v32, v34
	v_fma_f32 v35, v35, v35, -v35
	v_fmac_f32_e32 v19, v31, v34
	v_dual_fmac_f32 v21, v33, v34 :: v_dual_fmac_f32 v18, s17, v35
.LBB2_35:                               ; %Flow511
                                        ;   in Loop: Header=BB2_28 Depth=4
	s_or_b32 exec_lo, exec_lo, s3
.LBB2_36:                               ;   in Loop: Header=BB2_28 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	s_or_b32 exec_lo, exec_lo, s34
	v_add_nc_u32_e32 v29, -1, v29
	v_add_co_u32 v3, s2, v3, 12
	v_add_nc_u32_e32 v30, -1, v30
	v_add_co_ci_u32_e64 v4, s2, 0, v4, s2
	v_cmp_eq_u32_e32 vcc_lo, 0, v29
	s_or_b32 s33, vcc_lo, s33
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s33
	s_cbranch_execnz .LBB2_28
; %bb.37:                               ; %Flow512
                                        ;   in Loop: Header=BB2_25 Depth=3
	s_or_b32 exec_lo, exec_lo, s33
.LBB2_38:                               ; %Flow513
                                        ;   in Loop: Header=BB2_25 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s31
.LBB2_39:                               ; %.loopexit
                                        ;   in Loop: Header=BB2_25 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s30
	v_add_nc_u32_e32 v3, 1, v28
	v_cmp_ge_i32_e32 vcc_lo, v28, v9
	v_mov_b32_e32 v28, v3
	s_or_b32 s29, vcc_lo, s29
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s29
	s_cbranch_execnz .LBB2_25
; %bb.40:                               ; %Flow514
                                        ;   in Loop: Header=BB2_23 Depth=2
	s_or_b32 exec_lo, exec_lo, s29
.LBB2_41:                               ; %Flow515
                                        ;   in Loop: Header=BB2_23 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s23
	v_add_nc_u32_e32 v3, 1, v26
	v_cmp_ge_i32_e32 vcc_lo, v26, v12
	v_mov_b32_e32 v26, v3
	s_or_b32 s18, vcc_lo, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s18
	s_cbranch_execnz .LBB2_23
; %bb.42:                               ; %Flow516
                                        ;   in Loop: Header=BB2_21 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
.LBB2_43:                               ; %Flow517
                                        ;   in Loop: Header=BB2_21 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s16
	v_add_nc_u32_e32 v3, 1, v16
	v_cmp_ge_i32_e32 vcc_lo, v16, v15
	v_mov_b32_e32 v16, v3
	s_or_b32 s19, vcc_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s19
	s_cbranch_execnz .LBB2_21
; %bb.44:                               ; %._crit_edge448.loopexit
	s_or_b32 exec_lo, exec_lo, s19
	v_dual_mul_f32 v3, 0x41c00000, v19 :: v_dual_mul_f32 v4, 0x41c00000, v20
	v_mul_f32_e32 v5, 0x41c00000, v21
	v_add_f32_e32 v17, v18, v18
.LBB2_45:                               ; %Flow518
	s_or_b32 exec_lo, exec_lo, s14
	v_lshlrev_b64 v[0:1], 2, v[6:7]
	v_mad_u64_u32 v[7:8], null, v6, 12, s[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b96 v[7:8], v[3:5], off
	global_store_b32 v[0:1], v17, off
.LBB2_46:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel ljForce
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 352
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 48
		.amdhsa_next_free_sgpr 36
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	ljForce, .Lfunc_end2-ljForce
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3616
; NumSgprs: 38
; NumVgprs: 48
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 38
; NumVGPRsForWavesPerEU: 48
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	verletPre               ; -- Begin function verletPre
	.globl	verletPre
	.p2align	8
	.type	verletPre,@function
verletPre:                              ; @verletPre
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b128 s[16:19], s[0:1], 0x34
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s18, v1
	s_cbranch_execz .LBB3_2
; %bb.1:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x20
	v_mad_u64_u32 v[9:10], null, v1, 12, 0
	v_mul_f32_e64 v11, 0x3b9e14e2, s17
	s_load_b128 s[12:15], s[0:1], 0x28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v12, null, s16, s16, v11
	v_rcp_f32_e32 v13, v12
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s10, v9
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v10, vcc_lo
	v_add_co_u32 v3, vcc_lo, s2, v9
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v10, vcc_lo
	v_add_co_u32 v6, vcc_lo, s8, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v10, vcc_lo
	global_load_b96 v[0:2], v[0:1], off
	global_load_b96 v[3:5], v[3:4], off
	global_load_b96 v[6:8], v[6:7], off
	v_fma_f32 v14, -v12, v13, 1.0
	v_div_scale_f32 v15, vcc_lo, v11, s16, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v14, v13
	v_mul_f32_e32 v14, v15, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v16, -v12, v14, v15
	v_fmac_f32_e32 v14, v16, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, -v12, v14, v15
	v_div_fmas_f32 v12, v12, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v11, v12, s16, v11
	s_waitcnt vmcnt(1)
	v_fma_f32 v1, v11, v4, v1
	v_fma_f32 v0, v11, v3, v0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v4, s17, v1, v7
	v_fma_f32 v3, s17, v0, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f32 v6, null, s13, s13, v4
	v_div_scale_f32 v15, s0, v4, s13, v4
	v_div_scale_f32 v14, vcc_lo, v3, s12, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v12, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v17, -v6, v12, 1.0
	v_fmac_f32_e32 v12, v17, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, v15, v12
	v_fma_f32 v21, -v6, v17, v15
	v_fmac_f32_e32 v2, v11, v5
	v_div_scale_f32 v5, null, s12, s12, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v17, v21, v12 :: v_dual_fmac_f32 v8, s17, v2
	v_rcp_f32_e32 v11, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v6, -v6, v17, v15
	v_div_scale_f32 v7, null, s14, s14, v8
	v_div_scale_f32 v19, s1, v8, s14, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v13, v7
	s_waitcnt_depctr 0xfff
	v_fma_f32 v16, -v5, v11, 1.0
	v_fmac_f32_e32 v11, v16, v11
	v_fma_f32 v18, -v7, v13, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v16, v14, v11
	v_fmac_f32_e32 v13, v18, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v20, -v5, v16, v14
	v_mul_f32_e32 v18, v19, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v16, v20, v11
	v_fma_f32 v22, -v7, v18, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v5, -v5, v16, v14
	v_fmac_f32_e32 v18, v22, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v5, v5, v11, v16
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f32 v6, v6, v12, v17
	v_fma_f32 v7, -v7, v18, v19
	s_mov_b32 vcc_lo, s1
	v_div_fixup_f32 v5, v5, s12, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v6, v6, s13, v4
	v_div_fmas_f32 v7, v7, v13, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_floor_f32_e32 v5, v5
	v_floor_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v7, v7, s14, v8
	v_cvt_i32_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v6, v6
	v_floor_f32_e32 v7, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_i32_e32 v5, v5
	v_cvt_f32_i32_e32 v11, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cvt_i32_f32_e32 v7, v7
	v_add_co_u32 v6, vcc_lo, s6, v9
	v_fma_f32 v3, -s12, v5, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v4, -s13, v11, v4
	v_cvt_f32_i32_e32 v12, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f32 v5, -s14, v12, v8
	v_add_co_u32 v8, vcc_lo, s4, v9
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v10, vcc_lo
	global_store_b96 v[6:7], v[0:2], off
	global_store_b96 v[8:9], v[3:5], off
.LBB3_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel verletPre
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 23
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	verletPre, .Lfunc_end3-verletPre
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 740
; NumSgprs: 22
; NumVgprs: 23
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 23
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	verletPos               ; -- Begin function verletPos
	.globl	verletPos
	.p2align	8
	.type	verletPos,@function
verletPos:                              ; @verletPos
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s6, v1
	s_cbranch_execz .LBB4_2
; %bb.1:
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_mul_f32_e64 v0, 0x3b9e14e2, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v2, null, s4, s4, v0
	v_div_scale_f32 v13, vcc_lo, v0, s4, v0
	v_rcp_f32_e32 v11, v2
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[9:10], null, v1, 12, s[8:9]
	v_mad_u64_u32 v[6:7], null, v1, 12, s[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v2, v11, 1.0
	global_load_b96 v[3:5], v[9:10], off
	global_load_b96 v[6:8], v[6:7], off
	v_fmac_f32_e32 v11, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, v13, v11
	v_fma_f32 v14, -v2, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v14, v11
	v_fma_f32 v2, -v2, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v2, v2, v11, v12
	v_div_fixup_f32 v0, v2, s4, v0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v2, 0 :: v_dual_fmac_f32 v5, v0, v8
	v_fma_f32 v4, v0, v7, v4
	v_fma_f32 v3, v0, v6, v3
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_mul_f32_e64 v2, 0x424f490f, s4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v6, v4, v4
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v6, v3, v3
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	v_fmac_f32_e32 v6, v5, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v2, v2, v6
	global_store_b32 v[0:1], v2, off
	global_store_b96 v[9:10], v[3:5], off
.LBB4_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel verletPos
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	verletPos, .Lfunc_end4-verletPos
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 340
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           12
        .value_kind:     by_value
      - .offset:         36
        .size:           12
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
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amdhsa.version:
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...

	.end_amdgpu_metadata
