# include <stdio.h>
# include <math.h>

__global__ void Add( int n, float *A, float *B, float *C, float S1, float S2, int steps) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
	if(idx < n){
		for (int i = 0; i < steps; i++){
			C[steps*idx+i]=(powf(S1,3.0)- 3*B[steps*idx+i])/(A[steps*idx+i] + S2); //powf(S1,3.0)
		}
	}
}


int main ( int argc, char * argv [] ) {

	if (argc != 4){
		printf("To few args\n");
		return 1;
	}

	int n = atoi(argv[1]);
	printf("n = %d\n", n);

	int steps;
	float *hA, *hB, *hC;
	// float hS1, hS2;
	float *devA, *devB, *devC;
	float devS1, devS2, elapsedTime;
	cudaEvent_t start, stop;

	cudaEventCreate(&start);
	cudaEventCreate(&stop);
	elapsedTime = 0.0f;
	cudaEventRecord(start, 0);

	hA = (float *) malloc(n*sizeof(float));
	hB = (float *) malloc(n*sizeof(float));
	hC = (float *) malloc(n*sizeof(float));


	cudaMalloc ( &devA, n*sizeof(float));
	cudaMalloc ( &devB, n*sizeof(float));
	cudaMalloc ( &devC, n*sizeof(float));

	// cudaMalloc (&devS1, sizeof(float));
	// cudaMalloc (&devS2, sizeof(float));

	for (int i = 0; i < n; i++) {
		hA[i] = i;
		hB[i] = n-i;
	}
	devS1 = 15.4;
	devS2 = 4.4;


	// blocks=4; blocksize=64;
	dim3 block(atoi(argv[3]));
	dim3 grid(atoi(argv[2]));
	steps=(int)n/(atoi(argv[3])*atoi(argv[2]));

	// dim3 block(512);
	// dim3 grid((n-1)/512 + 1);

	printf("block = %d, grid = %d, threads = %d, steps = %d\n", block.x, grid.x, block.x*grid.x, steps);




	cudaMemcpy ( devA, hA, n*sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy ( devB, hB, n*sizeof(float), cudaMemcpyHostToDevice);


	Add<<<grid, block>>> ( n, devA, devB, devC, devS1, devS2, steps);

	cudaMemcpy ( hC, devC, n*sizeof(float), cudaMemcpyDeviceToHost );


	for (int i = n-10; i < n; i++) printf("devC[%d] = %.3f\n", i, hC[i]);

	cudaFree (devC);
	cudaFree (devA);
	cudaFree (devB);
	free(hA);
	free(hB);
	free(hC);



	cudaEventRecord(stop, 0);
	cudaEventSynchronize(stop);
	cudaEventElapsedTime(&elapsedTime, start, stop);

	printf("\n\ntime = %.5f millisec\n", elapsedTime);

	return 0;
}

// Yi =(S1^m - 3Bi)/(Ai + S2)
	.file	"tmpxft_00201590_00000000-6_lab3GPU.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z30__device_stub__Z3AddiPfS_S_ffiiPfS_S_ffi
	.type	_Z30__device_stub__Z3AddiPfS_S_ffiiPfS_S_ffi, @function
_Z30__device_stub__Z3AddiPfS_S_ffiiPfS_S_ffi:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edi, 44(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movss	%xmm0, 40(%rsp)
	movss	%xmm1, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z3AddiPfS_S_ffi(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z30__device_stub__Z3AddiPfS_S_ffiiPfS_S_ffi, .-_Z30__device_stub__Z3AddiPfS_S_ffiiPfS_S_ffi
	.globl	_Z3AddiPfS_S_ffi
	.type	_Z3AddiPfS_S_ffi, @function
_Z3AddiPfS_S_ffi:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z3AddiPfS_S_ffiiPfS_S_ffi
	.cfi_endproc
.LFE2053:
	.size	_Z3AddiPfS_S_ffi, .-_Z3AddiPfS_S_ffi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"To few args\n"
.LC1:
	.string	"n = %d\n"
.LC3:
	.string	"block = %d, grid = %d, threads = %d, steps = %d\n"
.LC6:
	.string	"devC[%d] = %.3f\n"
.LC7:
	.string	"\n\ntime = %.5f millisec\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	cmpl	$4, %edi
	je	.L9
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	$1, %eax
	jmp	.L8
.L9:
	movq	8(%rsi), %rdi
	movq	%rsi, %r12
	call	atoi@PLT
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	movslq	%eax, %r13
	xorl	%eax, %eax
	movl	%r13d, %edx
	movq	%r13, %rbx
	call	__printf_chk@PLT
	leaq	80(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	88(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	80(%rsp), %rdi
	xorl	%esi, %esi
	movl	$0x00000000, 52(%rsp)
	call	cudaEventRecord@PLT
	leaq	0(,%r13,4), %rax
	movq	%rax, %rdi
	movq	%rax, 8(%rsp)
	call	malloc@PLT
	leaq	0(,%r13,4), %rdi
	movq	%rax, 16(%rsp)
	call	malloc@PLT
	leaq	0(,%r13,4), %rdi
	movq	%rax, 24(%rsp)
	call	malloc@PLT
	movq	8(%rsp), %rsi
	leaq	56(%rsp), %rdi
	movq	%rax, %r14
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	leaq	64(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	leaq	72(%rsp), %rdi
	call	cudaMalloc@PLT
	xorl	%eax, %eax
.L11:
	cmpl	%eax, %ebx
	jle	.L18
	cvtsi2ssl	%eax, %xmm0
	movq	16(%rsp), %rcx
	movl	%ebx, %edx
	subl	%eax, %edx
	movss	%xmm0, (%rcx,%rax,4)
	cvtsi2ssl	%edx, %xmm0
	movq	24(%rsp), %rcx
	movss	%xmm0, (%rcx,%rax,4)
	incq	%rax
	jmp	.L11
.L18:
	movabsq	$4294967297, %r15
	movq	24(%r12), %rax
	movq	%rax, %rdi
	movq	%rax, 32(%rsp)
	call	atoi@PLT
	movq	%r15, 100(%rsp)
	movl	%eax, %ebp
	movq	16(%r12), %rax
	movq	%rax, %rdi
	movq	%rax, 40(%rsp)
	call	atoi@PLT
	movq	32(%rsp), %rdi
	movq	%r15, 112(%rsp)
	movl	%eax, %r12d
	call	atoi@PLT
	movq	40(%rsp), %rdi
	movl	%eax, %r15d
	call	atoi@PLT
	movl	%r15d, %ecx
	movl	%ebp, %r8d
	movl	$2, %edi
	imull	%eax, %ecx
	movl	%ebx, %eax
	leaq	.LC3(%rip), %rsi
	cltd
	imull	%r12d, %r8d
	idivl	%ecx
	movl	%r12d, %ecx
	movl	%ebp, %edx
	movl	%eax, %r9d
	movl	%eax, %r15d
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	8(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	movq	56(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	24(%rsp), %rsi
	movl	$1, %ecx
	movq	64(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	%r12d, 108(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	104(%rsp), %ecx
	movq	108(%rsp), %rdi
	movl	%ebp, 96(%rsp)
	movl	116(%rsp), %esi
	movq	96(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	movq	72(%rsp), %rcx
	movq	64(%rsp), %rdx
	movl	%r15d, %r8d
	movl	%ebx, %edi
	movss	.LC4(%rip), %xmm1
	movss	.LC5(%rip), %xmm0
	movq	56(%rsp), %rsi
	call	_Z30__device_stub__Z3AddiPfS_S_ffiiPfS_S_ffi
.L13:
	movq	8(%rsp), %rdx
	movq	72(%rsp), %rsi
	movq	%r14, %rdi
	subl	$10, %ebx
	movl	$2, %ecx
	movslq	%ebx, %rbx
	leaq	.LC6(%rip), %rbp
	call	cudaMemcpy@PLT
.L14:
	movl	%ebx, %edx
	cvtss2sd	(%r14,%rbx,4), %xmm0
	movq	%rbp, %rsi
	movb	$1, %al
	movl	$2, %edi
	incq	%rbx
	call	__printf_chk@PLT
	cmpq	%rbx, %r13
	jne	.L14
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	free@PLT
	movq	24(%rsp), %rdi
	call	free@PLT
	movq	%r14, %rdi
	call	free@PLT
	movq	88(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	88(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	88(%rsp), %rdx
	movq	80(%rsp), %rsi
	leaq	52(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	52(%rsp), %xmm0
	call	__printf_chk@PLT
	xorl	%eax, %eax
.L8:
	movq	120(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC8:
	.string	"_Z3AddiPfS_S_ffi"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z3AddiPfS_S_ffi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC4:
	.long	1082969293
	.align 4
.LC5:
	.long	1098278502
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
# include <stdio.h>
# include <math.h>

__global__ void Add( int n, float *A, float *B, float *C, float S1, float S2, int steps) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
	if(idx < n){
		for (int i = 0; i < steps; i++){
			C[steps*idx+i]=(powf(S1,3.0)- 3*B[steps*idx+i])/(A[steps*idx+i] + S2); //powf(S1,3.0)
		}
	}
}


int main ( int argc, char * argv [] ) {

	if (argc != 4){
		printf("To few args\n");
		return 1;
	}

	int n = atoi(argv[1]);
	printf("n = %d\n", n);

	int steps;
	float *hA, *hB, *hC;
	// float hS1, hS2;
	float *devA, *devB, *devC;
	float devS1, devS2, elapsedTime;
	hipEvent_t start, stop;

	hipEventCreate(&start);
	hipEventCreate(&stop);
	elapsedTime = 0.0f;
	hipEventRecord(start, 0);

	hA = (float *) malloc(n*sizeof(float));
	hB = (float *) malloc(n*sizeof(float));
	hC = (float *) malloc(n*sizeof(float));


	hipMalloc ( &devA, n*sizeof(float));
	hipMalloc ( &devB, n*sizeof(float));
	hipMalloc ( &devC, n*sizeof(float));

	// cudaMalloc (&devS1, sizeof(float));
	// cudaMalloc (&devS2, sizeof(float));

	for (int i = 0; i < n; i++) {
		hA[i] = i;
		hB[i] = n-i;
	}
	devS1 = 15.4;
	devS2 = 4.4;


	// blocks=4; blocksize=64;
	dim3 block(atoi(argv[3]));
	dim3 grid(atoi(argv[2]));
	steps=(int)n/(atoi(argv[3])*atoi(argv[2]));

	// dim3 block(512);
	// dim3 grid((n-1)/512 + 1);

	printf("block = %d, grid = %d, threads = %d, steps = %d\n", block.x, grid.x, block.x*grid.x, steps);




	hipMemcpy ( devA, hA, n*sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy ( devB, hB, n*sizeof(float), hipMemcpyHostToDevice);


	Add<<<grid, block>>> ( n, devA, devB, devC, devS1, devS2, steps);

	hipMemcpy ( hC, devC, n*sizeof(float), hipMemcpyDeviceToHost );


	for (int i = n-10; i < n; i++) printf("devC[%d] = %.3f\n", i, hC[i]);

	hipFree (devC);
	hipFree (devA);
	hipFree (devB);
	free(hA);
	free(hB);
	free(hC);



	hipEventRecord(stop, 0);
	hipEventSynchronize(stop);
	hipEventElapsedTime(&elapsedTime, start, stop);

	printf("\n\ntime = %.5f millisec\n", elapsedTime);

	return 0;
}

// Yi =(S1^m - 3Bi)/(Ai + S2)
	.text
	.file	"lab3GPU.hip"
	.globl	_Z18__device_stub__AddiPfS_S_ffi # -- Begin function _Z18__device_stub__AddiPfS_S_ffi
	.type	_Z18__device_stub__AddiPfS_S_ffi,@function
_Z18__device_stub__AddiPfS_S_ffi:       # @_Z18__device_stub__AddiPfS_S_ffi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	16(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	12(%rsp), %r9
	movss	%xmm1, (%r9)
	leaq	8(%rsp), %r10
	movl	%r8d, (%r10)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r9, 40(%rbx)
	movq	%r10, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3AddiPfS_S_ffi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z18__device_stub__AddiPfS_S_ffi, .Lfunc_end0-_Z18__device_stub__AddiPfS_S_ffi
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x41766666                      # float 15.3999996
.LCPI1_1:
	.long	0x408ccccd                      # float 4.4000001
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	cmpl	$4, %edi
	jne	.LBB1_1
# %bb.2:
	movq	%rsi, 16(%rsp)                  # 8-byte Spill
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %r12d
	movl	$.L.str.1, %edi
	movl	%eax, %esi
	xorl	%eax, %eax
	callq	printf
	leaq	80(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventCreate
	leaq	24(%rsp), %rdi
	callq	hipEventCreate
	movl	$0, 60(%rsp)
	movq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movslq	%r12d, %rbp
	leaq	(,%rbp,4), %r13
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, %rbx
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, %r14
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, %r15
	leaq	48(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movq	%r13, 72(%rsp)                  # 8-byte Spill
	movq	%r13, %rsi
	callq	hipMalloc
	testl	%ebp, %ebp
	jle	.LBB1_5
# %bb.3:                                # %.lr.ph.preheader
	movl	%r12d, %eax
	xorl	%ecx, %ecx
.LBB1_4:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2ss	%ecx, %xmm0
	xorps	%xmm1, %xmm1
	cvtsi2ss	%eax, %xmm1
	movss	%xmm0, (%rbx,%rcx,4)
	movss	%xmm1, (%r14,%rcx,4)
	incq	%rcx
	decq	%rax
	jne	.LBB1_4
.LBB1_5:                                # %._crit_edge
	movl	%r12d, 12(%rsp)                 # 4-byte Spill
	movq	16(%rsp), %r12                  # 8-byte Reload
	movq	24(%r12), %rdi
	callq	atoi
	movl	%eax, %r13d
	movl	%eax, %eax
	btsq	$32, %rax
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movq	16(%r12), %rdi
	callq	atoi
	movl	%eax, %r8d
	movl	%eax, %r12d
	btsq	$32, %r12
	movl	%eax, %ecx
	imull	%r13d, %ecx
	movl	12(%rsp), %eax                  # 4-byte Reload
	cltd
	idivl	%ecx
	movl	$.L.str.2, %edi
	movl	%r13d, %esi
	movl	%r8d, %edx
	movl	%eax, 16(%rsp)                  # 4-byte Spill
	movl	%eax, %r8d
	xorl	%eax, %eax
	callq	printf
	movq	48(%rsp), %rdi
	movq	%rbx, %rsi
	movq	72(%rsp), %r13                  # 8-byte Reload
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rdi
	movq	%r14, %rsi
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r12, %rdi
	movl	12(%rsp), %r12d                 # 4-byte Reload
	movl	$1, %esi
	movq	64(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_7
# %bb.6:
	movq	48(%rsp), %rsi
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rcx
	movss	.LCPI1_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movss	.LCPI1_1(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	movl	%r12d, %edi
	movl	16(%rsp), %r8d                  # 4-byte Reload
	callq	_Z18__device_stub__AddiPfS_S_ffi
.LBB1_7:
	movq	32(%rsp), %rsi
	movq	%r15, %rdi
	movq	%r13, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	addl	$-10, %r12d
	movslq	%r12d, %r12
.LBB1_8:                                # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r15,%r12,4), %xmm0
	movl	$.L.str.3, %edi
	movl	%r12d, %esi
	movb	$1, %al
	callq	printf
	incq	%r12
	cmpq	%rbp, %r12
	jl	.LBB1_8
# %bb.9:
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	24(%rsp), %rdi
	xorl	%ebx, %ebx
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	24(%rsp), %rdi
	callq	hipEventSynchronize
	movq	80(%rsp), %rsi
	movq	24(%rsp), %rdx
	leaq	60(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r14), %xmm0
	movl	$.L.str.4, %edi
	movb	$1, %al
	callq	printf
	jmp	.LBB1_10
.LBB1_1:
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$1, %ebx
.LBB1_10:
	movl	%ebx, %eax
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3AddiPfS_S_ffi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z3AddiPfS_S_ffi,@object        # @_Z3AddiPfS_S_ffi
	.section	.rodata,"a",@progbits
	.globl	_Z3AddiPfS_S_ffi
	.p2align	3, 0x0
_Z3AddiPfS_S_ffi:
	.quad	_Z18__device_stub__AddiPfS_S_ffi
	.size	_Z3AddiPfS_S_ffi, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"n = %d\n"
	.size	.L.str.1, 8

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"block = %d, grid = %d, threads = %d, steps = %d\n"
	.size	.L.str.2, 49

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"devC[%d] = %.3f\n"
	.size	.L.str.3, 17

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"\n\ntime = %.5f millisec\n"
	.size	.L.str.4, 24

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z3AddiPfS_S_ffi"
	.size	.L__unnamed_1, 17

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"To few args"
	.size	.Lstr, 12

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z18__device_stub__AddiPfS_S_ffi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z3AddiPfS_S_ffi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z3AddiPfS_S_ffi        ; -- Begin function _Z3AddiPfS_S_ffi
	.globl	_Z3AddiPfS_S_ffi
	.p2align	8
	.type	_Z3AddiPfS_S_ffi,@function
_Z3AddiPfS_S_ffi:                       ; @_Z3AddiPfS_S_ffi
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b32 s3, s[0:1], 0x0
	s_load_b128 s[4:7], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_cmp_gt_i32 s6, 0
	s_cselect_b32 s2, -1, 0
	v_cmp_gt_i32_e32 vcc_lo, s3, v1
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph
	v_frexp_mant_f32_e64 v0, |s4|
	s_mov_b32 s2, 0x3e76c4e1
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x8
	s_load_b64 s[0:1], s[0:1], 0x18
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v0
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v0, v0, v2
	v_add_f32_e32 v4, -1.0, v0
	v_add_f32_e32 v2, 1.0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, v4, v3
	v_dual_mul_f32 v7, v2, v5 :: v_dual_add_f32 v6, -1.0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v2, v5, v2, -v7
	v_sub_f32_e32 v0, v0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, v5, v0
	v_add_f32_e32 v0, v7, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v6, v4, v0
	v_sub_f32_e32 v7, v0, v7
	v_sub_f32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v2, v7, v2
	v_sub_f32_e32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v2, v0
	v_add_f32_e32 v0, v6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, v3, v0
	v_add_f32_e32 v2, v5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v3, v2, v5
	v_mul_f32_e32 v4, v2, v2
	v_sub_f32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v3, v2, v2, -v4
	v_add_f32_e32 v5, v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v2, v5
	v_add_f32_e32 v5, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmaak_f32 v6, s2, v5, 0x3e91f4c4
	v_dual_sub_f32 v4, v5, v4 :: v_dual_mul_f32 v9, v2, v5
	v_cmp_eq_f32_e64 s2, s4, 1.0
	v_dual_fmaak_f32 v6, v5, v6, 0x3ecccdef :: v_dual_sub_f32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v10, v5, v2, -v9
	v_mul_f32_e32 v7, v5, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v10, v5, v0
	v_ldexp_f32 v0, v0, 1
	v_fma_f32 v4, v5, v6, -v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, v3, v2
	v_fmac_f32_e32 v4, v3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v5, v9, v10 :: v_dual_add_f32 v6, v7, v4
	v_dual_sub_f32 v7, v6, v7 :: v_dual_add_f32 v8, 0x3f2aaaaa, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v4, v4, v7 :: v_dual_add_f32 v7, 0xbf2aaaaa, v8
	v_add_f32_e32 v4, 0x31739010, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v6, v6, v7
	v_add_f32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v8, v4
	v_sub_f32_e32 v6, v8, v3
	v_mul_f32_e32 v7, v5, v3
	v_sub_f32_e32 v8, v5, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v4, v4, v6
	v_fma_f32 v6, v5, v3, -v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v8, v10, v8
	v_fmac_f32_e32 v6, v5, v4
	v_frexp_exp_i32_f32_e32 v4, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v6, v8, v3
	v_subrev_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v4, v7, v6
	v_cvt_f32_i32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v7, v4, v7
	v_mul_f32_e32 v8, 0x3f317218, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v6, v6, v7
	v_fma_f32 v7, 0x3f317218, v3, -v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_add_f32 v0, v0, v6 :: v_dual_fmamk_f32 v3, v3, 0xb102e308, v7
	v_ldexp_f32 v2, v2, 1
	v_add_f32_e32 v5, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v2, v5, v2
	v_sub_f32_e32 v2, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v0, v0, v2
	v_add_f32_e32 v2, v8, v3
	v_add_f32_e32 v4, v5, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v8, v2, v8
	v_dual_add_f32 v6, v2, v4 :: v_dual_sub_f32 v5, v4, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v3, v3, v8
	v_dual_sub_f32 v7, v6, v2 :: v_dual_sub_f32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v9, v6, v7
	v_dual_sub_f32 v4, v4, v7 :: v_dual_add_f32 v5, v3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v2, v2, v9
	v_add_f32_e32 v2, v4, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v4, v5, v3
	v_add_f32_e32 v2, v5, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v5, v5, v4
	v_dual_sub_f32 v0, v0, v4 :: v_dual_add_f32 v7, v6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v3, v3, v5
	v_sub_f32_e32 v4, v7, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v0, v0, v3
	v_cndmask_b32_e64 v3, 0x40400000, 1.0, s2
	v_sub_f32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v0, v2
	v_add_f32_e32 v2, v7, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v4, v2, v7 :: v_dual_mul_f32 v5, v3, v2
	v_sub_f32_e32 v0, v0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v2, v3, v2, -v5
	v_cmp_class_f32_e64 vcc_lo, v5, 0x204
	v_fmac_f32_e32 v2, v3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v5, v2
	v_cndmask_b32_e32 v4, v0, v5, vcc_lo
	v_sub_f32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v4
	v_sub_f32_e32 v0, v2, v0
	v_cndmask_b32_e64 v6, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v4|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v7, v4, v6 :: v_dual_cndmask_b32 v0, 0, v0
	v_trunc_f32_e32 v4, v3
	v_mul_f32_e32 v8, 0x3fb8aa3b, v7
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v0, v6, v0
	v_fma_f32 v9, 0x3fb8aa3b, v7, -v8
	v_rndne_f32_e32 v10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmamk_f32 v9, v7, 0x32a5705f, v9 :: v_dual_sub_f32 v8, v8, v10
	v_cvt_i32_f32_e32 v5, v10
	v_add_f32_e32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v8, v8
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v2, v8, v5
	v_dual_mul_f32 v5, 0.5, v3 :: v_dual_cndmask_b32 v2, 0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_trunc_f32_e32 v8, v5
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v7
	v_cmp_neq_f32_e64 s2, v8, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, 0x7f800000, v2, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, v4, v3
	v_fma_f32 v3, v2, v0, v2
	s_delay_alu instid0(VALU_DEP_4)
	s_and_b32 s3, vcc_lo, s2
	v_cmp_eq_f32_e64 s2, 0x7f800000, v2
	v_mul_lo_u32 v0, v1, s6
	v_cndmask_b32_e64 v4, 1.0, s4, s3
	v_cndmask_b32_e64 v6, 0, s4, s3
	v_cmp_class_f32_e64 s3, s4, 0x204
	v_cndmask_b32_e64 v2, v3, v2, s2
	v_cmp_eq_f32_e64 s2, s4, 0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v2, 0x7fffffff, v2, v4
	v_cndmask_b32_e64 v3, 0x7f800000, 0, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	v_cndmask_b32_e32 v7, 0x7fc00000, v2, vcc_lo
	v_cmp_lt_f32_e64 vcc_lo, s4, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v3, 0x7fffffff, v3, v6
	v_cndmask_b32_e32 v2, v2, v7, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v5, vcc_lo
	s_or_b32 vcc_lo, s2, s3
	v_cndmask_b32_e32 v6, v2, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v5, vcc_lo
	v_cmp_o_f32_e64 vcc_lo, s4, s4
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e32 v6, 0x7fc00000, v6, vcc_lo
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v7, v[0:1], off
	global_load_b32 v8, v[2:3], off
	v_add_co_u32 v0, vcc_lo, v0, 4
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_add_i32 s6, s6, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s6, 0
	s_waitcnt vmcnt(0)
	v_dual_fmamk_f32 v7, v7, 0xc0400000, v6 :: v_dual_add_f32 v8, s5, v8
	v_div_scale_f32 v9, null, v8, v8, v7
	v_div_scale_f32 v11, vcc_lo, v7, v8, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v10, v9
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v9, v10, 1.0
	v_fmac_f32_e32 v10, v12, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, v11, v10
	v_fma_f32 v13, -v9, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v13, v10
	v_fma_f32 v9, -v9, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v9, v9, v10, v12
	v_div_fixup_f32 v7, v9, v8, v7
	global_store_b32 v[4:5], v7, off
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_cbranch_scc1 .LBB0_2
.LBB0_3:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3AddiPfS_S_ffi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z3AddiPfS_S_ffi, .Lfunc_end0-_Z3AddiPfS_S_ffi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1428
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z3AddiPfS_S_ffi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z3AddiPfS_S_ffi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
