#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include<iostream>
#include<limits.h>

#define NUM_NODES 5

using namespace std;

__global__ void CUDA_SSSP_KERNEL1(int *Va, int *Ea, int *Wa, bool *Ma, int *Ca, int *Ua, bool *done)
{
	int id = threadIdx.x + blockIdx.x * blockDim.x;
	if(id>NUM_NODES)
	{
		*done = false;
	}
	if(Ma[id]==true)
	{
		Ma[id] = false;
		__syncthreads(); 
		int start = Va[id];
		int end = Va[id+1];
		for(int i=start;i<end;i++) 
		{
			int nid = Ea[i];

			if(Ua[nid]>(Ca[nid]+Wa[nid]))
			{
				Ua[nid] = Ca[id] + Wa[nid];
			}
		}
	}
}
__global__ void CUDA_SSSP_KERNEL2(int *Va, int *Ea, int *Wa, bool *Ma, int *Ca, int *Ua, bool *done)
{
	int id = threadIdx.x + blockIdx.x * blockDim.x;
	if(id>NUM_NODES)
	{
		*done = false;
	}
	if(Ca[id]>Ua[id])
	{
		Ca[id] = Ua[id];
		Ma[id] = true;
		*done = false;
	}
	Ua[id] = Ca[id];
}

int main(int argc, char** argv)
{
	int** graph = new int* [NUM_NODES];
	int edges = 0;
    for(int i=0;i<NUM_NODES;i++)
    {
        graph[i] = new int[NUM_NODES];
    }
    for(int i=0;i<NUM_NODES;i++)
    {
        for(int j=i+1;j<NUM_NODES;j++)
        {
			int x = rand()%100;
            if(x!=0)
            {
				edges+=1;
                graph[i][j] = x;
                graph[j][i] = x;
            }
        }
    }
	
	int* v = new int[NUM_NODES+1];
	int* e = new int[2*edges];
	int* w = new int[2*edges];
	int x = 0;
	for(int i=0;i<NUM_NODES;i++)
	{
		v[i] = x;
		for(int j=0;j<NUM_NODES;j++)
		{
			if(graph[i][j]!=0)
			{
				e[x] = j;
				w[x] = graph[i][j];
				x+=1;
			}
		}
	}
	v[NUM_NODES] = x;
	bool mask[NUM_NODES] = { false };
	int cost[NUM_NODES] = { INT_MAX };
	int updated[NUM_NODES] = { INT_MAX };

	int source = 0;
	mask[source] = true;
	updated[source] = 0;
	cost[source] = 0;

	int* Va;
	cudaMalloc(&Va, sizeof(int)*(NUM_NODES+1));
	cudaMemcpy(Va, v, sizeof(int)*(NUM_NODES+1), cudaMemcpyHostToDevice);

	int* Ea;
	cudaMalloc(&Ea, sizeof(int)*(2*edges));
	cudaMemcpy(Ea, e, sizeof(int)*(2*edges), cudaMemcpyHostToDevice);

	int* Wa;
	cudaMalloc(&Wa, sizeof(int)*(2*edges));
	cudaMemcpy(Wa, w, sizeof(int)*(2*edges), cudaMemcpyHostToDevice);

	bool* Ma;
	cudaMalloc(&Ma, sizeof(bool)*NUM_NODES);
	cudaMemcpy(Ma, mask, sizeof(bool)*NUM_NODES, cudaMemcpyHostToDevice);

	int* Ua;
	cudaMalloc(&Ua, sizeof(int)*NUM_NODES);
	cudaMemcpy(Ua, updated, sizeof(int)*NUM_NODES, cudaMemcpyHostToDevice);

	int* Ca;
	cudaMalloc(&Ca, sizeof(int)*NUM_NODES);
	cudaMemcpy(Ca, cost, sizeof(int)*NUM_NODES, cudaMemcpyHostToDevice);

	int num_blks = 1;
	int threads = 5;

	bool done;
	bool* d_done;
	cudaMalloc((void**)&d_done, sizeof(bool));
	
	do {
		done = true;
		cudaMemcpy(d_done, &done, sizeof(bool), cudaMemcpyHostToDevice);
		CUDA_SSSP_KERNEL1<<<num_blks, threads>>>(Va, Ea, Wa, Ma, Ca, Ua, d_done);
		CUDA_SSSP_KERNEL2<<<num_blks, threads>>>(Va, Ea, Wa, Ma, Ca, Ua, d_done);
		cudaMemcpy(&done, d_done , sizeof(bool), cudaMemcpyDeviceToHost);
	} while (!done);

	cudaMemcpy(cost, Ca, sizeof(int)*NUM_NODES, cudaMemcpyDeviceToHost);
	
	cout<<"Cost: "<<endl;
	for(int i=0;i<NUM_NODES;i++)
	{
		cout<<cost[i]<<" ";
	}
	cout<<endl;
	return 0;
}


	.file	"tmpxft_00299da8_00000000-6_sssp.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z50__device_stub__Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_PiS_S_PbS_S_S0_
	.type	_Z50__device_stub__Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_PiS_S_PbS_S_S0_, @function
_Z50__device_stub__Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_PiS_S_PbS_S_S0_:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	72(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 224
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z50__device_stub__Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_PiS_S_PbS_S_S0_, .-_Z50__device_stub__Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_PiS_S_PbS_S_S0_
	.globl	_Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_
	.type	_Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_, @function
_Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_PiS_S_PbS_S_S0_
	.cfi_endproc
.LFE3661:
	.size	_Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_, .-_Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_
	.globl	_Z50__device_stub__Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_PiS_S_PbS_S_S0_
	.type	_Z50__device_stub__Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_PiS_S_PbS_S_S0_, @function
_Z50__device_stub__Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_PiS_S_PbS_S_S0_:
.LFB3662:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	72(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 224
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L8:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3662:
	.size	_Z50__device_stub__Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_PiS_S_PbS_S_S0_, .-_Z50__device_stub__Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_PiS_S_PbS_S_S0_
	.globl	_Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_
	.type	_Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_, @function
_Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_:
.LFB3663:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_PiS_S_PbS_S_S0_
	.cfi_endproc
.LFE3663:
	.size	_Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_, .-_Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Cost: "
.LC1:
	.string	" "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$40, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	xorl	%ebx, %ebx
	subq	$152, %rsp
	.cfi_def_cfa_offset 208
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	movq	%rax, %rbp
.L14:
	movl	$20, %edi
	call	_Znam@PLT
	movq	%rax, 0(%rbp,%rbx,8)
	incq	%rbx
	cmpq	$5, %rbx
	jne	.L14
	movl	$1, %r12d
	xorl	%ebx, %ebx
	movl	$100, %r14d
.L18:
	leaq	-4(,%r12,4), %r15
	movq	%r12, %r13
.L15:
	cmpl	$5, %r13d
	je	.L43
	call	rand@PLT
	cltd
	idivl	%r14d
	testl	%edx, %edx
	je	.L16
	movq	-8(%rbp,%r12,8), %rax
	incl	%ebx
	movl	%edx, (%rax,%r13,4)
	movq	0(%rbp,%r13,8), %rax
	movl	%edx, (%rax,%r15)
.L16:
	incq	%r13
	jmp	.L15
.L43:
	incq	%r12
	cmpq	$6, %r12
	jne	.L18
	movl	$24, %edi
	addl	%ebx, %ebx
	call	_Znam@PLT
	movslq	%ebx, %rbx
	movq	%rax, %r12
	movabsq	$2305843009213693950, %rax
	cmpq	%rbx, %rax
	jb	.L19
	salq	$2, %rbx
	movq	%rbx, %rdi
	call	_Znam@PLT
	movq	%rbx, %rdi
	movq	%rax, %r13
	call	_Znam@PLT
	xorl	%edx, %edx
	movq	%rax, %r14
	xorl	%eax, %eax
	jmp	.L20
.L19:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L42
	call	__cxa_throw_bad_array_new_length@PLT
.L20:
	movl	%eax, (%r12,%rdx,4)
	movq	0(%rbp,%rdx,8), %r8
	xorl	%ecx, %ecx
.L23:
	movl	(%r8,%rcx,4), %edi
	testl	%edi, %edi
	je	.L22
	movslq	%eax, %rsi
	incl	%eax
	movl	%ecx, 0(%r13,%rsi,4)
	movl	%edi, (%r14,%rsi,4)
.L22:
	incq	%rcx
	cmpq	$5, %rcx
	jne	.L23
	incq	%rdx
	cmpq	$5, %rdx
	jne	.L20
	movl	%eax, 20(%r12)
	xorps	%xmm0, %xmm0
	xorl	%r10d, %r10d
	xorl	%r9d, %r9d
	leaq	8(%rsp), %rdi
	movl	$24, %esi
	movl	%r9d, 92(%rsp)
	movabsq	$4294967297, %rbp
	movl	%r10d, 116(%rsp)
	movl	%r10d, 96(%rsp)
	movups	%xmm0, 100(%rsp)
	movups	%xmm0, 120(%rsp)
	movb	$1, 91(%rsp)
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$24, %edx
	leaq	96(%rsp), %r12
	call	cudaMemcpy@PLT
	movq	%rbx, %rsi
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	%rbx, %rsi
	leaq	24(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	24(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r14, %rsi
	movabsq	$4294967301, %rbx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leaq	32(%rsp), %rdi
	movl	$5, %esi
	call	cudaMalloc@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movl	$5, %edx
	leaq	91(%rsp), %rsi
	call	cudaMemcpy@PLT
	leaq	40(%rsp), %rdi
	movl	$20, %esi
	call	cudaMalloc@PLT
	movq	40(%rsp), %rdi
	movl	$1, %ecx
	movl	$20, %edx
	leaq	116(%rsp), %rsi
	call	cudaMemcpy@PLT
	leaq	48(%rsp), %rdi
	movl	$20, %esi
	call	cudaMalloc@PLT
	movq	48(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$20, %edx
	call	cudaMemcpy@PLT
	leaq	56(%rsp), %rdi
	movl	$1, %esi
	call	cudaMalloc@PLT
.L26:
	movq	56(%rsp), %rdi
	leaq	7(%rsp), %r13
	movl	$1, %ecx
	movl	$1, %edx
	movq	%r13, %rsi
	movb	$1, 7(%rsp)
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 76(%rsp)
	movl	$1, 84(%rsp)
	movq	%rbp, 64(%rsp)
	movl	$1, 72(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	%rsi
	.cfi_def_cfa_offset 216
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	56(%rsp), %r9
	movq	64(%rsp), %r8
	movq	48(%rsp), %rcx
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z50__device_stub__Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_PiS_S_PbS_S_S0_
	popq	%rdi
	.cfi_def_cfa_offset 216
	popq	%r8
	.cfi_def_cfa_offset 208
.L24:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 76(%rsp)
	movl	$1, 84(%rsp)
	movq	%rbp, 64(%rsp)
	movl	$1, 72(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	pushq	%rax
	.cfi_def_cfa_offset 216
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	56(%rsp), %r9
	movq	64(%rsp), %r8
	movq	48(%rsp), %rcx
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z50__device_stub__Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_PiS_S_PbS_S_S0_
	popq	%rdx
	.cfi_def_cfa_offset 216
	popq	%rcx
	.cfi_def_cfa_offset 208
.L25:
	movq	56(%rsp), %rsi
	movl	$2, %ecx
	movl	$1, %edx
	movq	%r13, %rdi
	call	cudaMemcpy@PLT
	cmpb	$0, 7(%rsp)
	je	.L26
	movq	48(%rsp), %rsi
	movl	$2, %ecx
	movq	%r12, %rdi
	xorl	%ebx, %ebx
	movl	$20, %edx
	leaq	_ZSt4cout(%rip), %rbp
	leaq	.LC1(%rip), %r13
	call	cudaMemcpy@PLT
	leaq	.LC0(%rip), %rsi
	movq	%rbp, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L27:
	movl	(%r12,%rbx,4), %esi
	movq	%rbp, %rdi
	incq	%rbx
	call	_ZNSolsEi@PLT
	movq	%r13, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cmpq	$5, %rbx
	jne	.L27
	movq	%rbp, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L28
.L42:
	call	__stack_chk_fail@PLT
.L28:
	addq	$152, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_"
.LC3:
	.string	"_Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3665:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3665:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include "hip/hip_runtime.h"

#include<iostream>
#include<limits.h>

#define NUM_NODES 5

using namespace std;

__global__ void CUDA_SSSP_KERNEL1(int *Va, int *Ea, int *Wa, bool *Ma, int *Ca, int *Ua, bool *done)
{
	int id = threadIdx.x + blockIdx.x * blockDim.x;
	if(id>NUM_NODES)
	{
		*done = false;
	}
	if(Ma[id]==true)
	{
		Ma[id] = false;
		__syncthreads(); 
		int start = Va[id];
		int end = Va[id+1];
		for(int i=start;i<end;i++) 
		{
			int nid = Ea[i];

			if(Ua[nid]>(Ca[nid]+Wa[nid]))
			{
				Ua[nid] = Ca[id] + Wa[nid];
			}
		}
	}
}
__global__ void CUDA_SSSP_KERNEL2(int *Va, int *Ea, int *Wa, bool *Ma, int *Ca, int *Ua, bool *done)
{
	int id = threadIdx.x + blockIdx.x * blockDim.x;
	if(id>NUM_NODES)
	{
		*done = false;
	}
	if(Ca[id]>Ua[id])
	{
		Ca[id] = Ua[id];
		Ma[id] = true;
		*done = false;
	}
	Ua[id] = Ca[id];
}

int main(int argc, char** argv)
{
	int** graph = new int* [NUM_NODES];
	int edges = 0;
    for(int i=0;i<NUM_NODES;i++)
    {
        graph[i] = new int[NUM_NODES];
    }
    for(int i=0;i<NUM_NODES;i++)
    {
        for(int j=i+1;j<NUM_NODES;j++)
        {
			int x = rand()%100;
            if(x!=0)
            {
				edges+=1;
                graph[i][j] = x;
                graph[j][i] = x;
            }
        }
    }
	
	int* v = new int[NUM_NODES+1];
	int* e = new int[2*edges];
	int* w = new int[2*edges];
	int x = 0;
	for(int i=0;i<NUM_NODES;i++)
	{
		v[i] = x;
		for(int j=0;j<NUM_NODES;j++)
		{
			if(graph[i][j]!=0)
			{
				e[x] = j;
				w[x] = graph[i][j];
				x+=1;
			}
		}
	}
	v[NUM_NODES] = x;
	bool mask[NUM_NODES] = { false };
	int cost[NUM_NODES] = { INT_MAX };
	int updated[NUM_NODES] = { INT_MAX };

	int source = 0;
	mask[source] = true;
	updated[source] = 0;
	cost[source] = 0;

	int* Va;
	hipMalloc(&Va, sizeof(int)*(NUM_NODES+1));
	hipMemcpy(Va, v, sizeof(int)*(NUM_NODES+1), hipMemcpyHostToDevice);

	int* Ea;
	hipMalloc(&Ea, sizeof(int)*(2*edges));
	hipMemcpy(Ea, e, sizeof(int)*(2*edges), hipMemcpyHostToDevice);

	int* Wa;
	hipMalloc(&Wa, sizeof(int)*(2*edges));
	hipMemcpy(Wa, w, sizeof(int)*(2*edges), hipMemcpyHostToDevice);

	bool* Ma;
	hipMalloc(&Ma, sizeof(bool)*NUM_NODES);
	hipMemcpy(Ma, mask, sizeof(bool)*NUM_NODES, hipMemcpyHostToDevice);

	int* Ua;
	hipMalloc(&Ua, sizeof(int)*NUM_NODES);
	hipMemcpy(Ua, updated, sizeof(int)*NUM_NODES, hipMemcpyHostToDevice);

	int* Ca;
	hipMalloc(&Ca, sizeof(int)*NUM_NODES);
	hipMemcpy(Ca, cost, sizeof(int)*NUM_NODES, hipMemcpyHostToDevice);

	int num_blks = 1;
	int threads = 5;

	bool done;
	bool* d_done;
	hipMalloc((void**)&d_done, sizeof(bool));
	
	do {
		done = true;
		hipMemcpy(d_done, &done, sizeof(bool), hipMemcpyHostToDevice);
		CUDA_SSSP_KERNEL1<<<num_blks, threads>>>(Va, Ea, Wa, Ma, Ca, Ua, d_done);
		CUDA_SSSP_KERNEL2<<<num_blks, threads>>>(Va, Ea, Wa, Ma, Ca, Ua, d_done);
		hipMemcpy(&done, d_done , sizeof(bool), hipMemcpyDeviceToHost);
	} while (!done);

	hipMemcpy(cost, Ca, sizeof(int)*NUM_NODES, hipMemcpyDeviceToHost);
	
	cout<<"Cost: "<<endl;
	for(int i=0;i<NUM_NODES;i++)
	{
		cout<<cost[i]<<" ";
	}
	cout<<endl;
	return 0;
}


	.text
	.file	"sssp.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z32__device_stub__CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_ # -- Begin function _Z32__device_stub__CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_
	.type	_Z32__device_stub__CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_,@function
_Z32__device_stub__CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_: # @_Z32__device_stub__CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z32__device_stub__CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_, .Lfunc_end0-_Z32__device_stub__CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_ # -- Begin function _Z32__device_stub__CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_
	.type	_Z32__device_stub__CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_,@function
_Z32__device_stub__CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_: # @_Z32__device_stub__CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z32__device_stub__CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_, .Lfunc_end1-_Z32__device_stub__CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$40, %edi
	callq	_Znam
	movq	%rax, %rbx
	xorl	%r14d, %r14d
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	movl	$20, %edi
	callq	_Znam
	movq	%rax, (%rbx,%r14,8)
	incq	%r14
	cmpq	$5, %r14
	jne	.LBB2_1
# %bb.2:                                # %.preheader.preheader
	xorl	%r14d, %r14d
	xorl	%r15d, %r15d
.LBB2_3:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_21 Depth 2
	cmpq	$3, %r14
	ja	.LBB2_4
# %bb.20:                               # %.lr.ph
                                        #   in Loop: Header=BB2_3 Depth=1
	movq	%r14, %r12
.LBB2_21:                               #   Parent Loop BB2_3 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	cltq
	imulq	$1374389535, %rax, %rcx         # imm = 0x51EB851F
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$37, %rcx
	addl	%edx, %ecx
	imull	$100, %ecx, %ecx
	subl	%ecx, %eax
	je	.LBB2_23
# %bb.22:                               #   in Loop: Header=BB2_21 Depth=2
	incl	%r15d
	movq	(%rbx,%r14,8), %rcx
	movl	%eax, 4(%rcx,%r12,4)
	movq	8(%rbx,%r12,8), %rcx
	movl	%eax, (%rcx,%r14,4)
.LBB2_23:                               #   in Loop: Header=BB2_21 Depth=2
	incq	%r12
	cmpq	$4, %r12
	jne	.LBB2_21
.LBB2_4:                                # %.loopexit
                                        #   in Loop: Header=BB2_3 Depth=1
	incq	%r14
	cmpq	$5, %r14
	jne	.LBB2_3
# %bb.5:
	movl	$24, %edi
	callq	_Znam
	movq	%rax, %r13
	leal	(%r15,%r15), %eax
	movslq	%eax, %r14
	shlq	$2, %r14
	testl	%r15d, %r15d
	movq	$-1, %r15
	cmovnsq	%r14, %r15
	movq	%r15, %rdi
	callq	_Znam
	movq	%rax, %rbp
	movq	%r15, %rdi
	callq	_Znam
	movq	%rax, %r15
	xorl	%eax, %eax
	xorl	%ecx, %ecx
.LBB2_6:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_7 Depth 2
	movl	%ecx, (%r13,%rax,4)
	movq	(%rbx,%rax,8), %rdx
	xorl	%esi, %esi
.LBB2_7:                                #   Parent Loop BB2_6 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%rdx,%rsi,4), %edi
	testl	%edi, %edi
	je	.LBB2_9
# %bb.8:                                #   in Loop: Header=BB2_7 Depth=2
	movslq	%ecx, %rcx
	movl	%esi, (%rbp,%rcx,4)
	movl	%edi, (%r15,%rcx,4)
	incl	%ecx
.LBB2_9:                                #   in Loop: Header=BB2_7 Depth=2
	incq	%rsi
	cmpq	$5, %rsi
	jne	.LBB2_7
# %bb.10:                               #   in Loop: Header=BB2_6 Depth=1
	incq	%rax
	cmpq	$5, %rax
	jne	.LBB2_6
# %bb.11:
	movabsq	$4294967297, %rbx               # imm = 0x100000001
	movl	%ecx, 20(%r13)
	xorl	%eax, %eax
	leaq	35(%rsp), %rsi
	movl	%eax, 1(%rsi)
	xorps	%xmm0, %xmm0
	leaq	80(%rsp), %rcx
	movups	%xmm0, 4(%rcx)
	leaq	112(%rsp), %rdx
	movups	%xmm0, 4(%rdx)
	movb	$1, (%rsi)
	movl	%eax, (%rdx)
	movl	%eax, (%rcx)
	leaq	72(%rsp), %r12
	movl	$24, %esi
	movq	%r12, %rdi
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$24, %edx
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	64(%rsp), %r12
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%r12), %rdi
	movq	%rbp, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	56(%rsp), %r12
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%r12), %rdi
	movq	%r15, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	48(%rsp), %r14
	movl	$5, %esi
	movq	%r14, %rdi
	callq	hipMalloc
	movq	(%r14), %rdi
	movl	$5, %edx
	leaq	35(%rsp), %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	40(%rsp), %r14
	movl	$20, %esi
	movq	%r14, %rdi
	callq	hipMalloc
	movq	(%r14), %rdi
	movl	$20, %edx
	leaq	112(%rsp), %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	24(%rsp), %r14
	movl	$20, %esi
	movq	%r14, %rdi
	callq	hipMalloc
	movq	(%r14), %rdi
	movl	$20, %edx
	leaq	80(%rsp), %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %rdi
	movl	$1, %esi
	callq	hipMalloc
	leaq	15(%rsp), %r14
	leaq	4(%rbx), %r15
.LBB2_12:                               # =>This Inner Loop Header: Depth=1
	movb	$1, 15(%rsp)
	movq	16(%rsp), %rdi
	movl	$1, %edx
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_14
# %bb.13:                               #   in Loop: Header=BB2_12 Depth=1
	movq	72(%rsp), %rdi
	movq	64(%rsp), %rsi
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rcx
	movq	24(%rsp), %r8
	movq	40(%rsp), %r9
	movq	16(%rsp), %rax
	movq	%rax, (%rsp)
	callq	_Z32__device_stub__CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_
.LBB2_14:                               #   in Loop: Header=BB2_12 Depth=1
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_16
# %bb.15:                               #   in Loop: Header=BB2_12 Depth=1
	movq	72(%rsp), %rdi
	movq	64(%rsp), %rsi
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rcx
	movq	24(%rsp), %r8
	movq	40(%rsp), %r9
	movq	16(%rsp), %rax
	movq	%rax, (%rsp)
	callq	_Z32__device_stub__CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_
.LBB2_16:                               #   in Loop: Header=BB2_12 Depth=1
	movq	16(%rsp), %rsi
	movl	$1, %edx
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	cmpb	$0, 15(%rsp)
	je	.LBB2_12
# %bb.17:
	movq	24(%rsp), %rsi
	leaq	80(%rsp), %rdi
	movl	$20, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$_ZSt4cout, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$6, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	xorl	%ebx, %ebx
.LBB2_18:                               # =>This Inner Loop Header: Depth=1
	movl	80(%rsp,%rbx,4), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movl	$.L.str.1, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%rbx
	cmpq	$5, %rbx
	jne	.LBB2_18
# %bb.19:
	movq	_ZSt4cout(%rip), %rax
	movl	$_ZSt4cout, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	xorl	%eax, %eax
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_,@object # @_Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_
	.section	.rodata,"a",@progbits
	.globl	_Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_
	.p2align	3, 0x0
_Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_:
	.quad	_Z32__device_stub__CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_
	.size	_Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_, 8

	.type	_Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_,@object # @_Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_
	.globl	_Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_
	.p2align	3, 0x0
_Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_:
	.quad	_Z32__device_stub__CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_
	.size	_Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Cost: "
	.size	.L.str, 7

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	" "
	.size	.L.str.1, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_"
	.size	.L__unnamed_1, 37

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_"
	.size	.L__unnamed_2, 37

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z32__device_stub__CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_
	.addrsig_sym _Z32__device_stub__CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_
	.addrsig_sym _Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_ ; -- Begin function _Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_
	.globl	_Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_
	.p2align	8
	.type	_Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_,@function
_Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_:   ; @_Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x44
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[16:23], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i32_e32 5, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_mov_b32_e32 v0, 0
	global_store_b8 v0, v0, s[20:21]
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s0
	v_ashrrev_i32_e32 v2, 31, v1
	v_add_co_u32 v4, vcc_lo, s10, v1
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v2, vcc_lo
	global_load_u8 v0, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u16_e32 0, v0
	s_cbranch_execz .LBB0_8
; %bb.3:
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_mov_b32_e32 v6, 0
	s_mov_b32 s1, 0
	global_store_b8 v[4:5], v6, off
	v_add_co_u32 v0, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	global_load_b64 v[0:1], v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, v0, v1
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_8
; %bb.4:                                ; %.lr.ph
	v_ashrrev_i32_e32 v5, 31, v0
	v_mov_b32_e32 v4, v0
	v_add_co_u32 v2, vcc_lo, s16, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s6, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
.LBB0_5:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v6, v[4:5], off
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_u32 v8, vcc_lo, s16, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v7, vcc_lo
	v_add_co_u32 v10, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, s18, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s19, v7, vcc_lo
	global_load_b32 v9, v[8:9], off
	global_load_b32 v8, v[10:11], off
	global_load_b32 v10, v[6:7], off
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v9, v8, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 v10, v9
	s_cbranch_execz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=1
	global_load_b32 v9, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v8, v9, v8
	global_store_b32 v[6:7], v8, off
.LBB0_7:                                ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v0, 1, v0
	v_add_co_u32 v4, s0, v4, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v5, s0, 0, v5, s0
	v_cmp_ge_i32_e32 vcc_lo, v0, v1
	s_or_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_5
.LBB0_8:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_, .Lfunc_end0-_Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 456
; NumSgprs: 26
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_ ; -- Begin function _Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_
	.globl	_Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_
	.p2align	8
	.type	_Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_,@function
_Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_:   ; @_Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x44
	s_load_b256 s[0:7], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s8, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	s_mov_b32 s8, exec_lo
	v_cmpx_lt_i32_e32 5, v1
	s_cbranch_execz .LBB1_2
; %bb.1:
	v_mov_b32_e32 v0, 0
	global_store_b8 v0, v0, s[6:7]
.LBB1_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_co_u32 v5, vcc_lo, s2, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_mov_b32 s2, exec_lo
	global_load_b32 v7, v[5:6], off
	global_load_b32 v0, v[3:4], off
	s_waitcnt vmcnt(0)
	v_cmpx_gt_i32_e64 v7, v0
	s_cbranch_execz .LBB1_4
; %bb.3:
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_mov_b32_e32 v7, v0
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	v_dual_mov_b32 v8, 1 :: v_dual_mov_b32 v9, 0
	global_store_b32 v[5:6], v0, off
	global_store_b8 v[1:2], v8, off
	global_store_b8 v9, v9, s[6:7]
.LBB1_4:
	s_or_b32 exec_lo, exec_lo, s2
	global_store_b32 v[3:4], v7, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_, .Lfunc_end1-_Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 224
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z17CUDA_SSSP_KERNEL1PiS_S_PbS_S_S0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z17CUDA_SSSP_KERNEL2PiS_S_PbS_S_S0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
