#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <vector>
using namespace std;


__global__ void global_get_flags(int* d_in, int* flags, int mask, int size) {
    //indices
    int myId = threadIdx.x + blockDim.x * blockIdx.x;

    //MAP 0s in d_in as 1 in flags array, vice versa
    if (myId < size && (mask & d_in[myId]) == 0) {
        flags[myId] = 1;
    }
    else {
        flags[myId] = 0;
    }
    //synch all threads
    __syncthreads();
}


__global__ void prescan(int* d_out, int* scan_store, int* flag, int size, bool store) {
    int myId = threadIdx.x + blockDim.x * blockIdx.x;
    int tid = threadIdx.x;
    //Blelloch scan that only works on powers of 2. this is mitigated by each block running
    //512 threads, and scan_store array is padded to powers of 2

    // load inputs into memory 
    d_out[myId] = flag[myId]; 
    __syncthreads();

    //terrible log math to index to parent and children vice versa
    //build up SUM
    for (int h = 1; h < size; h *= 2) {
        int index = h * 2 * tid + h * 2 - 1 + (size * blockIdx.x);
        if (index < (size * (blockIdx.x + 1))) { //check if myid +step is smaller than size
            d_out[index] += d_out[h * 2 * tid + h - 1 + (size * blockIdx.x)];
            //NEED TO PAD INPUT ARRAY
        }
        __syncthreads(); 
    }
    __syncthreads();
     //clear the last element
    if (tid == 0) {
        d_out[(size * (blockIdx.x+1)) - 1] = 0;
    }
    __syncthreads();

    //terrible log math to index to parent and children vice versa
    //Build down SCAN
    for (int h = size / 2; h > 0; h /= 2) {
        int index = h * 2 * tid + (h * 2) - 1 + (size * blockIdx.x);
        int right = h * 2 * tid + (h * 1) - 1 + (size * blockIdx.x);
        if (index < (size * (blockIdx.x+1))) {
            int leftVal = d_out[right];
            d_out[right] = d_out[index];
            d_out[index] += leftVal;
        }
        __syncthreads();
    }
    __syncthreads();
    //store the last element if thread 0 at block index
    if (tid == size -1 && store) {
        scan_store[blockIdx.x] = d_out[(size * (blockIdx.x + 1)) - 1] + flag[(size * (blockIdx.x + 1)-1)];
    }
    __syncthreads();
}

__global__ void combine(int* results, int* mini, int size, int* numFalse, int* scan) {
    int myId = threadIdx.x + blockDim.x * blockIdx.x;
    //shared value for each block to only do once
    __shared__ int presum;
    if (threadIdx.x == 0) {
        presum = mini[blockIdx.x];
    }
    __syncthreads();
    // add total scan of each block to each element
    if (myId < size) {
        results[myId] += presum;
    }
    __syncthreads();

    // store largest num in numFalse pointer location
    if (myId == size -1 ) {
        *numFalse = results[size - 1] + scan[size -1];
        //printf("num false cuda: %d\n", d_out[size - 1]);
    }
    __syncthreads();

}

__global__ void shuffle(int* d_out, int* d_in, int* scan, int* numFalse, int size, int mask) {
    //overlap at 1015 at end of cycle with storing indices
    int myId = threadIdx.x + blockDim.x * blockIdx.x;
    int t;
        if(myId<size)
            t = myId - scan[myId] + *numFalse; // true index for all
        __syncthreads();

        //use scan value if bit is 0, use t otherwise
        if (myId < size)
            if ((mask & d_in[myId]) == 0) d_out[scan[myId]] = d_in[myId];
            else d_out[t] = d_in[myId];
        __syncthreads();

    ////run next bit mask
}

__global__ void swap(int* d_in, int* d_out, int size) {
    //Stores each valid element from d_out to d_in, all in parallel
    int myId = threadIdx.x + blockDim.x * blockIdx.x;
    __syncthreads();
    if(myId < size) d_in[myId] = d_out[myId];
    __syncthreads();
}

int main() {
    //READING ONLY 8192 for simplicity, no padding
    /*
    TODO: Account for each thread taking care of 2 elements in prescan
    */
    vector<int> arr;
    string line;
    ifstream myfile("inp.txt");
    ofstream outfile2("q4.txt");
    if (myfile.is_open())
    {
        //gets next int
        //int numin = 0;
        while (getline(myfile, line, ','))
        {
            arr.push_back(stoi(line, nullptr));
            //arr.push_back(2); DEBUG
            //numin++;
        }
        myfile.close();
    }
    //size calculations plus padding
    int size = arr.size();
    //cout << arr.size() << endl;
    const int maxThreadsPerBlock = 1024;
    int threads = maxThreadsPerBlock;
    int blocks = (size / maxThreadsPerBlock);
    int padblocks = 1;
    int mod = size % threads;
    if (mod > 0) blocks++;
    //padding for block cudamalloc
    while (padblocks < blocks) padblocks *= 2;
    //bootleg push 2 for everything, try to not shuffle the end
    for (int i = 0; i < threads - mod; i++) {
        arr.push_back(2);
    }

    //allocate device memory
    int* d_in, * d_out, * scan, * flags, * scan_store, * scan_large, *numFalse;
    //int* h_false = (int*)malloc(sizeof(int));
    
    //allocate memory for full size of padded blocks, only write to actual values
    cudaMalloc((void**)&flags, arr.size() * sizeof(int));
    cudaMalloc((void**)&d_out, arr.size() * sizeof(int));
    cudaMalloc((void**)&scan, arr.size() * sizeof(int));
    cudaMalloc((void**)&scan_store, padblocks * sizeof(int));
    cudaMalloc((void**)&scan_large, padblocks * sizeof(int));
    cudaMalloc((void**)&numFalse, sizeof(int));
    // treat pointer to start of vector as array pointer
    cudaMalloc((void**)&d_in, arr.size() * sizeof(int));
    cudaMemcpy(d_in, &arr[0], arr.size() * sizeof(int), cudaMemcpyHostToDevice);
    

    ///////////////////////////////////////////////////////////////////////////
    //For each bit 0-999
    for (int i = 0, mask = 1; i < 10; i++, mask <<= 1) {
        //MAP 0's to flags array
        global_get_flags<<<blocks, threads>>>(d_in, flags, mask, size);
        cudaDeviceSynchronize();

        //do first scan on each block and store results in scan_store array
        prescan<<<blocks, threads>>>(scan, scan_store, flags, threads, true);
        cudaDeviceSynchronize();
        //DEBUG
        /*int* h_scan = (int*)malloc(sizeof(int) * blocks);
        cudaMemcpy(h_scan, scan_store, sizeof(int) * blocks, cudaMemcpyDeviceToHost);
        cout << "SCAN_STORE: " << h_scan[0];
        for (int j = 1; j < blocks; j++) {
            cout << "," << h_scan[j];
        }
        cout << endl;*/
        //////////////////////////

        //do secondary scan on array of scan results 
        prescan<<<1, blocks >>>(scan_large, NULL, scan_store, padblocks, false);
        cudaDeviceSynchronize();

        // Combine scans in parallel
        combine<<<blocks, threads>>>(scan, scan_large, size, numFalse, flags);
        cudaDeviceSynchronize();

        //DEBUG
        /*cudaMemcpy(h_false, numFalse, sizeof(int), cudaMemcpyDeviceToHost);
        printf("number of false: %d\n", h_false[0]);*/

        //shuffle to new values
        shuffle<<<blocks, threads>>>(d_out, d_in, scan, numFalse, size, mask);
        cudaDeviceSynchronize();

        ////move d_out to d_in to redo, must do in seperate kernel to avoid race conditions
        swap<<<blocks, threads>>>(d_in, d_out, size);
        cudaDeviceSynchronize();
    }

    /////////////////////////////////////////////////////////////////////////
    //Copy results to host from device
    int* ans_arr = (int*)malloc(sizeof(int) * (arr.size() + mod));
    cudaMemcpy(ans_arr, d_in, sizeof(int) * arr.size(), cudaMemcpyDeviceToHost);

    // output to file   
    if (outfile2.is_open())
    {       
        //avoid comma at end of string
        outfile2 << ans_arr[0];

        //append integers up to original input size
        for (int i = 1; i < size; i++) {
            outfile2 << "," << ans_arr[i];
        }

        outfile2.close();
    }

    //free mem
    cudaFree(d_in);
    cudaFree(d_out);
    cudaFree(scan);
    cudaFree(scan_store);
    cudaFree(scan_large);
    cudaFree(flags);
    cudaFree(numFalse);
    free(ans_arr);
}



	.file	"tmpxft_00241a53_00000000-6_q4.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4143:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4143:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z40__device_stub__Z16global_get_flagsPiS_iiPiS_ii
	.type	_Z40__device_stub__Z16global_get_flagsPiS_iiPiS_ii, @function
_Z40__device_stub__Z16global_get_flagsPiS_iiPiS_ii:
.LFB4165:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z16global_get_flagsPiS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4165:
	.size	_Z40__device_stub__Z16global_get_flagsPiS_iiPiS_ii, .-_Z40__device_stub__Z16global_get_flagsPiS_iiPiS_ii
	.globl	_Z16global_get_flagsPiS_ii
	.type	_Z16global_get_flagsPiS_ii, @function
_Z16global_get_flagsPiS_ii:
.LFB4166:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z16global_get_flagsPiS_iiPiS_ii
	.cfi_endproc
.LFE4166:
	.size	_Z16global_get_flagsPiS_ii, .-_Z16global_get_flagsPiS_ii
	.globl	_Z32__device_stub__Z7prescanPiS_S_ibPiS_S_ib
	.type	_Z32__device_stub__Z7prescanPiS_S_ibPiS_S_ib, @function
_Z32__device_stub__Z7prescanPiS_S_ibPiS_S_ib:
.LFB4167:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movb	%r8b, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z7prescanPiS_S_ib(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4167:
	.size	_Z32__device_stub__Z7prescanPiS_S_ibPiS_S_ib, .-_Z32__device_stub__Z7prescanPiS_S_ibPiS_S_ib
	.globl	_Z7prescanPiS_S_ib
	.type	_Z7prescanPiS_S_ib, @function
_Z7prescanPiS_S_ib:
.LFB4168:
	.cfi_startproc
	endbr64
	movzbl	%r8b, %r8d
	jmp	_Z32__device_stub__Z7prescanPiS_S_ibPiS_S_ib
	.cfi_endproc
.LFE4168:
	.size	_Z7prescanPiS_S_ib, .-_Z7prescanPiS_S_ib
	.globl	_Z33__device_stub__Z7combinePiS_iS_S_PiS_iS_S_
	.type	_Z33__device_stub__Z7combinePiS_iS_S_PiS_iS_S_, @function
_Z33__device_stub__Z7combinePiS_iS_S_PiS_iS_S_:
.LFB4169:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z7combinePiS_iS_S_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L13:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4169:
	.size	_Z33__device_stub__Z7combinePiS_iS_S_PiS_iS_S_, .-_Z33__device_stub__Z7combinePiS_iS_S_PiS_iS_S_
	.globl	_Z7combinePiS_iS_S_
	.type	_Z7combinePiS_iS_S_, @function
_Z7combinePiS_iS_S_:
.LFB4170:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z7combinePiS_iS_S_PiS_iS_S_
	.cfi_endproc
.LFE4170:
	.size	_Z7combinePiS_iS_S_, .-_Z7combinePiS_iS_S_
	.globl	_Z34__device_stub__Z7shufflePiS_S_S_iiPiS_S_S_ii
	.type	_Z34__device_stub__Z7shufflePiS_S_S_iiPiS_S_S_ii, @function
_Z34__device_stub__Z7shufflePiS_S_S_iiPiS_S_S_ii:
.LFB4171:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z7shufflePiS_S_S_ii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L18:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4171:
	.size	_Z34__device_stub__Z7shufflePiS_S_S_iiPiS_S_S_ii, .-_Z34__device_stub__Z7shufflePiS_S_S_iiPiS_S_S_ii
	.globl	_Z7shufflePiS_S_S_ii
	.type	_Z7shufflePiS_S_S_ii, @function
_Z7shufflePiS_S_S_ii:
.LFB4172:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z7shufflePiS_S_S_iiPiS_S_S_ii
	.cfi_endproc
.LFE4172:
	.size	_Z7shufflePiS_S_S_ii, .-_Z7shufflePiS_S_S_ii
	.globl	_Z26__device_stub__Z4swapPiS_iPiS_i
	.type	_Z26__device_stub__Z4swapPiS_iPiS_i, @function
_Z26__device_stub__Z4swapPiS_iPiS_i:
.LFB4173:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z4swapPiS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L23:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4173:
	.size	_Z26__device_stub__Z4swapPiS_iPiS_i, .-_Z26__device_stub__Z4swapPiS_iPiS_i
	.globl	_Z4swapPiS_i
	.type	_Z4swapPiS_i, @function
_Z4swapPiS_i:
.LFB4174:
	.cfi_startproc
	endbr64
	jmp	_Z26__device_stub__Z4swapPiS_iPiS_i
	.cfi_endproc
.LFE4174:
	.size	_Z4swapPiS_i, .-_Z4swapPiS_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z4swapPiS_i"
.LC1:
	.string	"_Z7shufflePiS_S_S_ii"
.LC2:
	.string	"_Z7combinePiS_iS_S_"
.LC3:
	.string	"_Z7prescanPiS_S_ib"
.LC4:
	.string	"_Z16global_get_flagsPiS_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4176:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z4swapPiS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7shufflePiS_S_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7combinePiS_iS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7prescanPiS_S_ib(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z16global_get_flagsPiS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4176:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.text._ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev,"axG",@progbits,_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD5Ev,comdat
	.align 2
	.weak	_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev
	.type	_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev, @function
_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev:
.LFB4255:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	%rdi, %rbx
	call	__errno_location@PLT
	cmpl	$0, (%rax)
	jne	.L30
	movl	(%rbx), %edx
	movl	%edx, (%rax)
.L30:
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4255:
	.size	_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev, .-_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev
	.weak	_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD1Ev
	.set	_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD1Ev,_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev
	.section	.text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
	.align 2
	.weak	_ZNSt6vectorIiSaIiEED2Ev
	.type	_ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4502:
	.cfi_startproc
	endbr64
	movq	(%rdi), %rax
	testq	%rax, %rax
	je	.L33
	movq	16(%rdi), %rsi
	movq	%rax, %rdi
	subq	%rax, %rsi
	jmp	_ZdlPvm@PLT
.L33:
	ret
	.cfi_endproc
.LFE4502:
	.size	_ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
	.weak	_ZNSt6vectorIiSaIiEED1Ev
	.set	_ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
	.section	.rodata._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_.str1.1,"aMS",@progbits,1
.LC5:
	.string	"vector::_M_realloc_insert"
	.section	.text._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,comdat
	.align 2
	.weak	_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
	.type	_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, @function
_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_:
.LFB4818:
	.cfi_startproc
	endbr64
	movabsq	$2305843009213693951, %rcx
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	movq	8(%rdi), %rax
	movq	(%rdi), %r14
	movq	%rax, %rbx
	movq	%rax, (%rsp)
	subq	%r14, %rbx
	sarq	$2, %rbx
	cmpq	%rcx, %rbx
	jne	.L36
	leaq	.LC5(%rip), %rdi
	call	_ZSt20__throw_length_errorPKc@PLT
.L36:
	cmpq	%r14, (%rsp)
	movl	$1, %eax
	movq	%rsi, %r15
	movq	%rdi, %r13
	cmovne	%rbx, %rax
	movq	%rsi, %rbp
	addq	%rax, %rbx
	setc	%al
	subq	%r14, %r15
	movzbl	%al, %eax
	testq	%rax, %rax
	jne	.L46
	xorl	%r12d, %r12d
	testq	%rbx, %rbx
	je	.L41
	movabsq	$2305843009213693951, %rax
	cmpq	%rax, %rbx
	cmova	%rax, %rbx
	jmp	.L40
.L46:
	movq	%rcx, %rbx
.L40:
	leaq	0(,%rbx,4), %rdi
	movq	%rdx, 8(%rsp)
	call	_Znwm@PLT
	movq	8(%rsp), %rdx
	movq	%rax, %r12
.L41:
	movl	(%rdx), %eax
	movl	%eax, (%r12,%r15)
	testq	%r15, %r15
	jle	.L42
	movq	%r15, %rdx
	movq	%r14, %rsi
	movq	%r12, %rdi
	call	memmove@PLT
.L42:
	movq	(%rsp), %rax
	leaq	4(%r12,%r15), %rdx
	subq	%rbp, %rax
	testq	%rax, %rax
	jle	.L43
	movq	%rdx, %rdi
	movq	%rbp, %rsi
	movq	%rax, %rcx
	rep movsb
.L43:
	leaq	(%rdx,%rax), %rbp
	testq	%r14, %r14
	je	.L44
	movq	16(%r13), %rsi
	movq	%r14, %rdi
	subq	%r14, %rsi
	call	_ZdlPvm@PLT
.L44:
	leaq	(%r12,%rbx,4), %rax
	movq	%r12, 0(%r13)
	movq	%rbp, 8(%r13)
	movq	%rax, 16(%r13)
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4818:
	.size	_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, .-_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
	.text
	.align 2
	.type	_ZNSt6vectorIiSaIiEE12emplace_backIJiEEERiDpOT_.isra.0, @function
_ZNSt6vectorIiSaIiEE12emplace_backIJiEEERiDpOT_.isra.0:
.LFB4959:
	.cfi_startproc
	movq	%rsi, %rdx
	movq	8(%rdi), %rsi
	cmpq	16(%rdi), %rsi
	je	.L54
	movl	(%rdx), %eax
	addq	$4, %rsi
	movl	%eax, -4(%rsi)
	movq	%rsi, 8(%rdi)
	ret
.L54:
	jmp	_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
	.cfi_endproc
.LFE4959:
	.size	_ZNSt6vectorIiSaIiEE12emplace_backIJiEEERiDpOT_.isra.0, .-_ZNSt6vectorIiSaIiEE12emplace_backIJiEEERiDpOT_.isra.0
	.section	.rodata.str1.1
.LC6:
	.string	"inp.txt"
.LC7:
	.string	"q4.txt"
.LC8:
	.string	"stoi"
.LC9:
	.string	","
	.section	.text.startup
	.globl	main
	.type	main, @function
main:
.LFB4129:
	.cfi_startproc
	.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
	.cfi_lsda 0x1b,.LLSDA4129
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	leaq	.LC6(%rip), %rsi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$1224, %rsp
	.cfi_def_cfa_offset 1280
	movq	%fs:40, %rax
	movq	%rax, 1208(%rsp)
	xorl	%eax, %eax
	leaq	160(%rsp), %rax
	movq	%rdx, 120(%rsp)
	movq	%rax, 144(%rsp)
	leaq	688(%rsp), %rax
	movq	%rdx, 128(%rsp)
	movq	%rax, %rdi
	movq	%rdx, 136(%rsp)
	movl	$8, %edx
	movq	%rcx, 152(%rsp)
	movb	$0, 160(%rsp)
	movq	%rax, 16(%rsp)
.LEHB0:
	call	_ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
	leaq	176(%rsp), %rax
	movl	$16, %edx
	leaq	.LC7(%rip), %rsi
	movq	%rax, %rdi
	movq	%rax, 24(%rsp)
.LEHB1:
	call	_ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE1:
	leaq	808(%rsp), %rdi
	movl	$2147483648, %r13d
	call	_ZNKSt12__basic_fileIcE7is_openEv@PLT
	testb	%al, %al
	jne	.L58
.L70:
	movq	128(%rsp), %rax
	subq	120(%rsp), %rax
	movl	$1024, %ecx
	sarq	$2, %rax
	cltd
	movl	%eax, 12(%rsp)
	idivl	%ecx
	movslq	%edx, %r12
	movl	%eax, %ebp
	testl	%r12d, %r12d
	jle	.L60
	incl	%ebp
	jmp	.L60
.L123:
	movq	(%rax), %rdx
	movq	-24(%rdx), %rdx
	testb	$5, 32(%rax,%rdx)
	jne	.L121
	call	__errno_location@PLT
	leaq	104(%rsp), %r12
	movl	$10, %edx
	movq	144(%rsp), %rbp
	movq	%rax, %rbx
	movl	(%rax), %eax
	movq	%r12, %rsi
	movq	%rbp, %rdi
	movl	%eax, 92(%rsp)
	xorl	%eax, %eax
	movl	%eax, (%rbx)
	call	__isoc23_strtol@PLT
	cmpq	104(%rsp), %rbp
	leaq	92(%rsp), %rbp
	movq	%rax, %r14
	je	.L122
	cmpl	$34, (%rbx)
	je	.L63
	leaq	(%rax,%r13), %rax
	movl	$4294967295, %edx
	cmpq	%rax, %rdx
	jb	.L63
	movq	%rbp, %rdi
	call	_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD1Ev
	leaq	120(%rsp), %rdi
	movq	%r12, %rsi
	movl	%r14d, 104(%rsp)
.LEHB2:
	call	_ZNSt6vectorIiSaIiEE12emplace_backIJiEEERiDpOT_.isra.0
.L58:
	movq	16(%rsp), %rdi
	leaq	144(%rsp), %rsi
	movl	$44, %edx
	call	_ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@PLT
.LEHE2:
	jmp	.L123
.L122:
	movq	1208(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L118
	leaq	.LC8(%rip), %rdi
.LEHB3:
	call	_ZSt24__throw_invalid_argumentPKc@PLT
.L63:
	movq	1208(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L118
	leaq	.LC8(%rip), %rdi
	call	_ZSt20__throw_out_of_rangePKc@PLT
.LEHE3:
.L106:
	endbr64
	movq	%rax, %rbx
.L67:
	movq	%rbp, %rdi
	call	_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD1Ev
	jmp	.L68
.L121:
	movq	16(%rsp), %rdi
.LEHB4:
	call	_ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@PLT
	jmp	.L70
.L60:
	movl	$1, %r13d
.L71:
	cmpl	%ebp, %r13d
	jge	.L124
	addl	%r13d, %r13d
	jmp	.L71
.L124:
	movl	$1024, %ebx
	xorl	%r14d, %r14d
	leaq	104(%rsp), %r15
	subl	%r12d, %ebx
.L73:
	leaq	120(%rsp), %rdi
	movq	%r15, %rsi
	movl	$2, 104(%rsp)
	call	_ZNSt6vectorIiSaIiEE12emplace_backIJiEEERiDpOT_.isra.0
	incl	%r14d
	cmpl	%ebx, %r14d
	jne	.L73
	movq	120(%rsp), %r14
	movq	128(%rsp), %rax
	leaq	56(%rsp), %rdi
	subq	%r14, %rax
	movq	%rax, %rsi
	movq	%rax, (%rsp)
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	leaq	40(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	leaq	48(%rsp), %rdi
	call	cudaMalloc@PLT
	movslq	%r13d, %rbx
	leaq	64(%rsp), %rdi
	salq	$2, %rbx
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	72(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	80(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	leaq	32(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdx
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movq	%r14, %rsi
	call	cudaMemcpy@PLT
	movl	$4194305, %ebx
	movl	$10, %r15d
	movl	$1, %r14d
	salq	$10, %rbx
.L92:
	movl	%ebp, 92(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movabsq	$4294967297, %rax
	movl	$1, %ecx
	movq	%rbx, 104(%rsp)
	movq	%rax, 96(%rsp)
	movq	92(%rsp), %rdi
	movl	100(%rsp), %esi
	movl	$1, 112(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	je	.L74
.L76:
	call	cudaDeviceSynchronize@PLT
	jmp	.L125
.L74:
	movl	12(%rsp), %ecx
	movq	56(%rsp), %rsi
	movl	%r14d, %edx
	movq	32(%rsp), %rdi
	call	_Z40__device_stub__Z16global_get_flagsPiS_iiPiS_ii
	jmp	.L76
.L125:
	movl	%ebp, 92(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movabsq	$4294967297, %rax
	movl	$1, %ecx
	movq	%rbx, 104(%rsp)
	movq	%rax, 96(%rsp)
	movq	92(%rsp), %rdi
	movl	100(%rsp), %esi
	movl	$1, 112(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	je	.L77
.L79:
	call	cudaDeviceSynchronize@PLT
	jmp	.L126
.L77:
	movq	56(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	$1024, %ecx
	movl	$1, %r8d
	movq	48(%rsp), %rdi
	call	_Z32__device_stub__Z7prescanPiS_S_ibPiS_S_ib
	jmp	.L79
.L126:
	movl	%ebp, 104(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movl	$1, 100(%rsp)
	movq	%rdi, 108(%rsp)
	movl	112(%rsp), %ecx
	movq	104(%rsp), %rdx
	movq	%rdi, 92(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	je	.L80
.L82:
	call	cudaDeviceSynchronize@PLT
	jmp	.L127
.L80:
	movq	64(%rsp), %rdx
	movq	72(%rsp), %rdi
	xorl	%r8d, %r8d
	movl	%r13d, %ecx
	xorl	%esi, %esi
	call	_Z32__device_stub__Z7prescanPiS_S_ibPiS_S_ib
	jmp	.L82
.L127:
	movl	%ebp, 92(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movabsq	$4294967297, %rax
	movl	$1, %ecx
	movq	%rbx, 104(%rsp)
	movq	%rax, 96(%rsp)
	movq	92(%rsp), %rdi
	movl	100(%rsp), %esi
	movl	$1, 112(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	je	.L83
.L85:
	call	cudaDeviceSynchronize@PLT
	jmp	.L128
.L83:
	movq	56(%rsp), %r8
	movq	80(%rsp), %rcx
	movl	12(%rsp), %edx
	movq	72(%rsp), %rsi
	movq	48(%rsp), %rdi
	call	_Z33__device_stub__Z7combinePiS_iS_S_PiS_iS_S_
	jmp	.L85
.L128:
	movl	%ebp, 92(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movabsq	$4294967297, %rax
	movl	$1, %ecx
	movq	%rbx, 104(%rsp)
	movq	%rax, 96(%rsp)
	movq	92(%rsp), %rdi
	movl	100(%rsp), %esi
	movl	$1, 112(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	je	.L86
.L88:
	call	cudaDeviceSynchronize@PLT
	jmp	.L129
.L86:
	movl	12(%rsp), %r8d
	movq	80(%rsp), %rcx
	movl	%r14d, %r9d
	movq	48(%rsp), %rdx
	movq	32(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z34__device_stub__Z7shufflePiS_S_S_iiPiS_S_S_ii
	jmp	.L88
.L129:
	movl	%ebp, 92(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movabsq	$4294967297, %rax
	movl	$1, %ecx
	movq	%rbx, 104(%rsp)
	movq	%rax, 96(%rsp)
	movq	92(%rsp), %rdi
	movl	100(%rsp), %esi
	movl	$1, 112(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	je	.L89
.L91:
	call	cudaDeviceSynchronize@PLT
	jmp	.L130
.L89:
	movl	12(%rsp), %edx
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_Z26__device_stub__Z4swapPiS_iPiS_i
	jmp	.L91
.L130:
	addl	%r14d, %r14d
	decl	%r15d
	jne	.L92
	movq	(%rsp), %rdi
	sarq	$2, %rdi
	addq	%r12, %rdi
	salq	$2, %rdi
	call	malloc@PLT
	movq	(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	$2, %ecx
	movq	%rax, %rdi
	movq	%rax, %rbx
	call	cudaMemcpy@PLT
	leaq	288(%rsp), %rdi
	leaq	176(%rsp), %rbp
	call	_ZNKSt12__basic_fileIcE7is_openEv@PLT
	testb	%al, %al
	jne	.L93
.L97:
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	jmp	.L131
.L93:
	movl	(%rbx), %esi
	movq	%rbp, %rdi
	call	_ZNSolsEi@PLT
	movl	$1, %r12d
	leaq	.LC9(%rip), %r13
.L95:
	cmpl	%r12d, 12(%rsp)
	jle	.L132
	movq	%r13, %rsi
	movq	%rbp, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	(%rbx,%r12,4), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	incq	%r12
	jmp	.L95
.L132:
	movq	%rbp, %rdi
	call	_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
	jmp	.L97
.L131:
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
.LEHE4:
	movq	%rbx, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	_ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
	leaq	688(%rsp), %rdi
	call	_ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
	leaq	144(%rsp), %rdi
	call	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
	leaq	120(%rsp), %rdi
	call	_ZNSt6vectorIiSaIiEED1Ev
	movq	1208(%rsp), %rax
	subq	%fs:40, %rax
	je	.L101
	jmp	.L118
.L105:
	endbr64
	movq	%rax, %rbx
.L68:
	movq	24(%rsp), %rdi
	call	_ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
	jmp	.L98
.L104:
	endbr64
	movq	%rax, %rbx
.L98:
	movq	16(%rsp), %rdi
	call	_ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
	jmp	.L99
.L103:
	endbr64
	movq	%rax, %rbx
.L99:
	leaq	144(%rsp), %rdi
	call	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
	leaq	120(%rsp), %rdi
	call	_ZNSt6vectorIiSaIiEED1Ev
	movq	1208(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L118
	movq	%rbx, %rdi
.LEHB5:
	call	_Unwind_Resume@PLT
.LEHE5:
.L118:
	call	__stack_chk_fail@PLT
.L101:
	addq	$1224, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4129:
	.globl	__gxx_personality_v0
	.section	.gcc_except_table,"a",@progbits
.LLSDA4129:
	.byte	0xff
	.byte	0xff
	.byte	0x1
	.uleb128 .LLSDACSE4129-.LLSDACSB4129
.LLSDACSB4129:
	.uleb128 .LEHB0-.LFB4129
	.uleb128 .LEHE0-.LEHB0
	.uleb128 .L103-.LFB4129
	.uleb128 0
	.uleb128 .LEHB1-.LFB4129
	.uleb128 .LEHE1-.LEHB1
	.uleb128 .L104-.LFB4129
	.uleb128 0
	.uleb128 .LEHB2-.LFB4129
	.uleb128 .LEHE2-.LEHB2
	.uleb128 .L105-.LFB4129
	.uleb128 0
	.uleb128 .LEHB3-.LFB4129
	.uleb128 .LEHE3-.LEHB3
	.uleb128 .L106-.LFB4129
	.uleb128 0
	.uleb128 .LEHB4-.LFB4129
	.uleb128 .LEHE4-.LEHB4
	.uleb128 .L105-.LFB4129
	.uleb128 0
	.uleb128 .LEHB5-.LFB4129
	.uleb128 .LEHE5-.LEHB5
	.uleb128 0
	.uleb128 0
.LLSDACSE4129:
	.section	.text.startup
	.size	main, .-main
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.hidden	DW.ref.__gxx_personality_v0
	.weak	DW.ref.__gxx_personality_v0
	.section	.data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
	.align 8
	.type	DW.ref.__gxx_personality_v0, @object
	.size	DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
	.quad	__gxx_personality_v0
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include "hip/hip_runtime.h"

#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <vector>
using namespace std;


__global__ void global_get_flags(int* d_in, int* flags, int mask, int size) {
    //indices
    int myId = threadIdx.x + blockDim.x * blockIdx.x;

    //MAP 0s in d_in as 1 in flags array, vice versa
    if (myId < size && (mask & d_in[myId]) == 0) {
        flags[myId] = 1;
    }
    else {
        flags[myId] = 0;
    }
    //synch all threads
    __syncthreads();
}


__global__ void prescan(int* d_out, int* scan_store, int* flag, int size, bool store) {
    int myId = threadIdx.x + blockDim.x * blockIdx.x;
    int tid = threadIdx.x;
    //Blelloch scan that only works on powers of 2. this is mitigated by each block running
    //512 threads, and scan_store array is padded to powers of 2

    // load inputs into memory 
    d_out[myId] = flag[myId]; 
    __syncthreads();

    //terrible log math to index to parent and children vice versa
    //build up SUM
    for (int h = 1; h < size; h *= 2) {
        int index = h * 2 * tid + h * 2 - 1 + (size * blockIdx.x);
        if (index < (size * (blockIdx.x + 1))) { //check if myid +step is smaller than size
            d_out[index] += d_out[h * 2 * tid + h - 1 + (size * blockIdx.x)];
            //NEED TO PAD INPUT ARRAY
        }
        __syncthreads(); 
    }
    __syncthreads();
     //clear the last element
    if (tid == 0) {
        d_out[(size * (blockIdx.x+1)) - 1] = 0;
    }
    __syncthreads();

    //terrible log math to index to parent and children vice versa
    //Build down SCAN
    for (int h = size / 2; h > 0; h /= 2) {
        int index = h * 2 * tid + (h * 2) - 1 + (size * blockIdx.x);
        int right = h * 2 * tid + (h * 1) - 1 + (size * blockIdx.x);
        if (index < (size * (blockIdx.x+1))) {
            int leftVal = d_out[right];
            d_out[right] = d_out[index];
            d_out[index] += leftVal;
        }
        __syncthreads();
    }
    __syncthreads();
    //store the last element if thread 0 at block index
    if (tid == size -1 && store) {
        scan_store[blockIdx.x] = d_out[(size * (blockIdx.x + 1)) - 1] + flag[(size * (blockIdx.x + 1)-1)];
    }
    __syncthreads();
}

__global__ void combine(int* results, int* mini, int size, int* numFalse, int* scan) {
    int myId = threadIdx.x + blockDim.x * blockIdx.x;
    //shared value for each block to only do once
    __shared__ int presum;
    if (threadIdx.x == 0) {
        presum = mini[blockIdx.x];
    }
    __syncthreads();
    // add total scan of each block to each element
    if (myId < size) {
        results[myId] += presum;
    }
    __syncthreads();

    // store largest num in numFalse pointer location
    if (myId == size -1 ) {
        *numFalse = results[size - 1] + scan[size -1];
        //printf("num false cuda: %d\n", d_out[size - 1]);
    }
    __syncthreads();

}

__global__ void shuffle(int* d_out, int* d_in, int* scan, int* numFalse, int size, int mask) {
    //overlap at 1015 at end of cycle with storing indices
    int myId = threadIdx.x + blockDim.x * blockIdx.x;
    int t;
        if(myId<size)
            t = myId - scan[myId] + *numFalse; // true index for all
        __syncthreads();

        //use scan value if bit is 0, use t otherwise
        if (myId < size)
            if ((mask & d_in[myId]) == 0) d_out[scan[myId]] = d_in[myId];
            else d_out[t] = d_in[myId];
        __syncthreads();

    ////run next bit mask
}

__global__ void swap(int* d_in, int* d_out, int size) {
    //Stores each valid element from d_out to d_in, all in parallel
    int myId = threadIdx.x + blockDim.x * blockIdx.x;
    __syncthreads();
    if(myId < size) d_in[myId] = d_out[myId];
    __syncthreads();
}

int main() {
    //READING ONLY 8192 for simplicity, no padding
    /*
    TODO: Account for each thread taking care of 2 elements in prescan
    */
    vector<int> arr;
    string line;
    ifstream myfile("inp.txt");
    ofstream outfile2("q4.txt");
    if (myfile.is_open())
    {
        //gets next int
        //int numin = 0;
        while (getline(myfile, line, ','))
        {
            arr.push_back(stoi(line, nullptr));
            //arr.push_back(2); DEBUG
            //numin++;
        }
        myfile.close();
    }
    //size calculations plus padding
    int size = arr.size();
    //cout << arr.size() << endl;
    const int maxThreadsPerBlock = 1024;
    int threads = maxThreadsPerBlock;
    int blocks = (size / maxThreadsPerBlock);
    int padblocks = 1;
    int mod = size % threads;
    if (mod > 0) blocks++;
    //padding for block cudamalloc
    while (padblocks < blocks) padblocks *= 2;
    //bootleg push 2 for everything, try to not shuffle the end
    for (int i = 0; i < threads - mod; i++) {
        arr.push_back(2);
    }

    //allocate device memory
    int* d_in, * d_out, * scan, * flags, * scan_store, * scan_large, *numFalse;
    //int* h_false = (int*)malloc(sizeof(int));
    
    //allocate memory for full size of padded blocks, only write to actual values
    hipMalloc((void**)&flags, arr.size() * sizeof(int));
    hipMalloc((void**)&d_out, arr.size() * sizeof(int));
    hipMalloc((void**)&scan, arr.size() * sizeof(int));
    hipMalloc((void**)&scan_store, padblocks * sizeof(int));
    hipMalloc((void**)&scan_large, padblocks * sizeof(int));
    hipMalloc((void**)&numFalse, sizeof(int));
    // treat pointer to start of vector as array pointer
    hipMalloc((void**)&d_in, arr.size() * sizeof(int));
    hipMemcpy(d_in, &arr[0], arr.size() * sizeof(int), hipMemcpyHostToDevice);
    

    ///////////////////////////////////////////////////////////////////////////
    //For each bit 0-999
    for (int i = 0, mask = 1; i < 10; i++, mask <<= 1) {
        //MAP 0's to flags array
        global_get_flags<<<blocks, threads>>>(d_in, flags, mask, size);
        hipDeviceSynchronize();

        //do first scan on each block and store results in scan_store array
        prescan<<<blocks, threads>>>(scan, scan_store, flags, threads, true);
        hipDeviceSynchronize();
        //DEBUG
        /*int* h_scan = (int*)malloc(sizeof(int) * blocks);
        cudaMemcpy(h_scan, scan_store, sizeof(int) * blocks, cudaMemcpyDeviceToHost);
        cout << "SCAN_STORE: " << h_scan[0];
        for (int j = 1; j < blocks; j++) {
            cout << "," << h_scan[j];
        }
        cout << endl;*/
        //////////////////////////

        //do secondary scan on array of scan results 
        prescan<<<1, blocks >>>(scan_large, NULL, scan_store, padblocks, false);
        hipDeviceSynchronize();

        // Combine scans in parallel
        combine<<<blocks, threads>>>(scan, scan_large, size, numFalse, flags);
        hipDeviceSynchronize();

        //DEBUG
        /*cudaMemcpy(h_false, numFalse, sizeof(int), cudaMemcpyDeviceToHost);
        printf("number of false: %d\n", h_false[0]);*/

        //shuffle to new values
        shuffle<<<blocks, threads>>>(d_out, d_in, scan, numFalse, size, mask);
        hipDeviceSynchronize();

        ////move d_out to d_in to redo, must do in seperate kernel to avoid race conditions
        swap<<<blocks, threads>>>(d_in, d_out, size);
        hipDeviceSynchronize();
    }

    /////////////////////////////////////////////////////////////////////////
    //Copy results to host from device
    int* ans_arr = (int*)malloc(sizeof(int) * (arr.size() + mod));
    hipMemcpy(ans_arr, d_in, sizeof(int) * arr.size(), hipMemcpyDeviceToHost);

    // output to file   
    if (outfile2.is_open())
    {       
        //avoid comma at end of string
        outfile2 << ans_arr[0];

        //append integers up to original input size
        for (int i = 1; i < size; i++) {
            outfile2 << "," << ans_arr[i];
        }

        outfile2.close();
    }

    //free mem
    hipFree(d_in);
    hipFree(d_out);
    hipFree(scan);
    hipFree(scan_store);
    hipFree(scan_large);
    hipFree(flags);
    hipFree(numFalse);
    free(ans_arr);
}



	.text
	.file	"q4.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z31__device_stub__global_get_flagsPiS_ii # -- Begin function _Z31__device_stub__global_get_flagsPiS_ii
	.type	_Z31__device_stub__global_get_flagsPiS_ii,@function
_Z31__device_stub__global_get_flagsPiS_ii: # @_Z31__device_stub__global_get_flagsPiS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16global_get_flagsPiS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z31__device_stub__global_get_flagsPiS_ii, .Lfunc_end0-_Z31__device_stub__global_get_flagsPiS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__prescanPiS_S_ib # -- Begin function _Z22__device_stub__prescanPiS_S_ib
	.type	_Z22__device_stub__prescanPiS_S_ib,@function
_Z22__device_stub__prescanPiS_S_ib:     # @_Z22__device_stub__prescanPiS_S_ib
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	3(%rsp), %rcx
	movb	%r8b, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7prescanPiS_S_ib, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z22__device_stub__prescanPiS_S_ib, .Lfunc_end1-_Z22__device_stub__prescanPiS_S_ib
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__combinePiS_iS_S_ # -- Begin function _Z22__device_stub__combinePiS_iS_S_
	.type	_Z22__device_stub__combinePiS_iS_S_,@function
_Z22__device_stub__combinePiS_iS_S_:    # @_Z22__device_stub__combinePiS_iS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7combinePiS_iS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z22__device_stub__combinePiS_iS_S_, .Lfunc_end2-_Z22__device_stub__combinePiS_iS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__shufflePiS_S_S_ii # -- Begin function _Z22__device_stub__shufflePiS_S_S_ii
	.type	_Z22__device_stub__shufflePiS_S_S_ii,@function
_Z22__device_stub__shufflePiS_S_S_ii:   # @_Z22__device_stub__shufflePiS_S_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7shufflePiS_S_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z22__device_stub__shufflePiS_S_S_ii, .Lfunc_end3-_Z22__device_stub__shufflePiS_S_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z19__device_stub__swapPiS_i    # -- Begin function _Z19__device_stub__swapPiS_i
	.type	_Z19__device_stub__swapPiS_i,@function
_Z19__device_stub__swapPiS_i:           # @_Z19__device_stub__swapPiS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4swapPiS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z19__device_stub__swapPiS_i, .Lfunc_end4-_Z19__device_stub__swapPiS_i
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
.Lfunc_begin0:
	.cfi_startproc
	.cfi_personality 3, __gxx_personality_v0
	.cfi_lsda 3, .Lexception0
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$1160, %rsp                     # imm = 0x488
	.cfi_def_cfa_offset 1216
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	xorps	%xmm0, %xmm0
	movaps	%xmm0, 16(%rsp)
	xorl	%eax, %eax
	movq	%rax, 32(%rsp)
	leaq	112(%rsp), %rcx
	movq	%rcx, -16(%rcx)
	movq	%rax, -8(%rcx)
	movb	$0, (%rcx)
.Ltmp0:
	leaq	640(%rsp), %rdi
	movl	$.L.str, %esi
	movl	$8, %edx
	callq	_ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.1:
.Ltmp3:
	leaq	128(%rsp), %rdi
	movl	$.L.str.1, %esi
	movl	$16, %edx
	callq	_ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp4:
# %bb.2:
	leaq	760(%rsp), %rdi
	callq	_ZNKSt12__basic_fileIcE7is_openEv
	testb	%al, %al
	je	.LBB5_26
# %bb.3:                                # %.preheader139
	leaq	640(%rsp), %rbx
	leaq	96(%rsp), %r14
	leaq	8(%rsp), %r15
.LBB5_4:                                # =>This Inner Loop Header: Depth=1
.Ltmp6:
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movl	$44, %edx
	callq	_ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_
.Ltmp7:
# %bb.5:                                #   in Loop: Header=BB5_4 Depth=1
	movq	(%rax), %rcx
	movq	-24(%rcx), %rcx
	testb	$5, 32(%rax,%rcx)
	jne	.LBB5_25
# %bb.6:                                #   in Loop: Header=BB5_4 Depth=1
	movq	96(%rsp), %r12
	callq	__errno_location
	movq	%rax, %rbp
	movl	(%rax), %r13d
	movl	$0, (%rax)
	movq	%r12, %rdi
	movq	%r15, %rsi
	movl	$10, %edx
	callq	__isoc23_strtol
	cmpq	%r12, 8(%rsp)
	je	.LBB5_7
# %bb.11:                               #   in Loop: Header=BB5_4 Depth=1
	movslq	%eax, %rcx
	cmpq	%rax, %rcx
	jne	.LBB5_13
# %bb.12:                               #   in Loop: Header=BB5_4 Depth=1
	movl	(%rbp), %ecx
	cmpl	$34, %ecx
	je	.LBB5_13
# %bb.15:                               #   in Loop: Header=BB5_4 Depth=1
	testl	%ecx, %ecx
	jne	.LBB5_17
# %bb.16:                               #   in Loop: Header=BB5_4 Depth=1
	movl	%r13d, (%rbp)
.LBB5_17:                               #   in Loop: Header=BB5_4 Depth=1
	movl	%eax, 40(%rsp)
	movq	24(%rsp), %rsi
	cmpq	32(%rsp), %rsi
	je	.LBB5_19
# %bb.18:                               #   in Loop: Header=BB5_4 Depth=1
	movl	%eax, (%rsi)
	addq	$4, %rsi
	movq	%rsi, 24(%rsp)
	jmp	.LBB5_4
.LBB5_19:                               #   in Loop: Header=BB5_4 Depth=1
.Ltmp95:
	leaq	16(%rsp), %rdi
	leaq	40(%rsp), %rdx
	callq	_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.Ltmp96:
	jmp	.LBB5_4
.LBB5_25:
.Ltmp9:
	leaq	640(%rsp), %rdi
	callq	_ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv
.Ltmp10:
.LBB5_26:
	movq	24(%rsp), %rbx
	subq	16(%rsp), %rbx
	shrq	$2, %rbx
	leal	1023(%rbx), %eax
	testl	%ebx, %ebx
	cmovnsl	%ebx, %eax
	movl	%eax, %ecx
	sarl	$10, %ecx
	andl	$-1024, %eax                    # imm = 0xFC00
	movl	%ebx, %edx
	subl	%eax, %edx
	xorl	%r13d, %r13d
	testl	%edx, %edx
	setg	%r13b
	addl	%ecx, %r13d
	movl	$1, %eax
.LBB5_27:                               # =>This Inner Loop Header: Depth=1
	movl	%eax, %r14d
	leal	(%r14,%r14), %eax
	cmpl	%r13d, %r14d
	jl	.LBB5_27
# %bb.28:                               # %.lr.ph
	movq	%rdx, 88(%rsp)                  # 8-byte Spill
	leal	-1024(%rdx), %ebp
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
.LBB5_29:                               # =>This Inner Loop Header: Depth=1
	movl	$2, 8(%rsp)
	movq	24(%rsp), %rsi
	cmpq	32(%rsp), %rsi
	je	.LBB5_31
# %bb.30:                               #   in Loop: Header=BB5_29 Depth=1
	movl	$2, (%rsi)
	addq	$4, %rsi
	movq	%rsi, 24(%rsp)
	jmp	.LBB5_32
.LBB5_31:                               #   in Loop: Header=BB5_29 Depth=1
.Ltmp12:
	movq	%r15, %rdi
	movq	%r12, %rdx
	callq	_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.Ltmp13:
.LBB5_32:                               # %_ZNSt6vectorIiSaIiEE9push_backEOi.exit97
                                        #   in Loop: Header=BB5_29 Depth=1
	incl	%ebp
	jne	.LBB5_29
# %bb.33:                               # %._crit_edge
	movq	24(%rsp), %rsi
	subq	16(%rsp), %rsi
.Ltmp15:
	leaq	48(%rsp), %rdi
	callq	hipMalloc
.Ltmp16:
# %bb.34:
	movq	24(%rsp), %rsi
	subq	16(%rsp), %rsi
.Ltmp17:
	leaq	40(%rsp), %rdi
	callq	hipMalloc
.Ltmp18:
# %bb.35:
	movq	24(%rsp), %rsi
	subq	16(%rsp), %rsi
.Ltmp19:
	leaq	56(%rsp), %rdi
	callq	hipMalloc
.Ltmp20:
# %bb.36:
	movl	%r14d, %r15d
	shlq	$2, %r15
.Ltmp21:
	leaq	80(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
.Ltmp22:
# %bb.37:
.Ltmp23:
	leaq	72(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
.Ltmp24:
# %bb.38:
.Ltmp25:
	leaq	64(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
.Ltmp26:
# %bb.39:
	movq	24(%rsp), %rsi
	subq	16(%rsp), %rsi
.Ltmp27:
	leaq	8(%rsp), %rdi
	callq	hipMalloc
.Ltmp28:
# %bb.40:
	movq	8(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	24(%rsp), %rdx
	subq	%rsi, %rdx
.Ltmp29:
	movl	$1, %ebp
	movl	$1, %ecx
	callq	hipMemcpy
.Ltmp30:
# %bb.41:                               # %.preheader137
	movl	%r13d, %r15d
	btsq	$32, %r15
	movl	$10, %r13d
	movabsq	$4294968320, %r12               # imm = 0x100000400
.LBB5_42:                               # =>This Inner Loop Header: Depth=1
.Ltmp32:
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp33:
# %bb.43:                               #   in Loop: Header=BB5_42 Depth=1
	testl	%eax, %eax
	jne	.LBB5_45
# %bb.44:                               #   in Loop: Header=BB5_42 Depth=1
	movq	8(%rsp), %rdi
	movq	48(%rsp), %rsi
.Ltmp34:
	movl	%ebp, %edx
	movl	%ebx, %ecx
	callq	_Z31__device_stub__global_get_flagsPiS_ii
.Ltmp35:
.LBB5_45:                               #   in Loop: Header=BB5_42 Depth=1
.Ltmp36:
	callq	hipDeviceSynchronize
.Ltmp37:
# %bb.46:                               #   in Loop: Header=BB5_42 Depth=1
.Ltmp38:
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp39:
# %bb.47:                               #   in Loop: Header=BB5_42 Depth=1
	testl	%eax, %eax
	jne	.LBB5_49
# %bb.48:                               #   in Loop: Header=BB5_42 Depth=1
	movq	56(%rsp), %rdi
	movq	80(%rsp), %rsi
	movq	48(%rsp), %rdx
.Ltmp40:
	movl	$1024, %ecx                     # imm = 0x400
	movl	$1, %r8d
	callq	_Z22__device_stub__prescanPiS_S_ib
.Ltmp41:
.LBB5_49:                               #   in Loop: Header=BB5_42 Depth=1
.Ltmp42:
	callq	hipDeviceSynchronize
.Ltmp43:
# %bb.50:                               #   in Loop: Header=BB5_42 Depth=1
.Ltmp44:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp45:
# %bb.51:                               #   in Loop: Header=BB5_42 Depth=1
	testl	%eax, %eax
	jne	.LBB5_53
# %bb.52:                               #   in Loop: Header=BB5_42 Depth=1
	movq	72(%rsp), %rdi
	movq	80(%rsp), %rdx
.Ltmp46:
	xorl	%esi, %esi
	movl	%r14d, %ecx
	xorl	%r8d, %r8d
	callq	_Z22__device_stub__prescanPiS_S_ib
.Ltmp47:
.LBB5_53:                               #   in Loop: Header=BB5_42 Depth=1
.Ltmp48:
	callq	hipDeviceSynchronize
.Ltmp49:
# %bb.54:                               #   in Loop: Header=BB5_42 Depth=1
.Ltmp50:
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp51:
# %bb.55:                               #   in Loop: Header=BB5_42 Depth=1
	testl	%eax, %eax
	jne	.LBB5_57
# %bb.56:                               #   in Loop: Header=BB5_42 Depth=1
	movq	56(%rsp), %rdi
	movq	72(%rsp), %rsi
	movq	64(%rsp), %rcx
	movq	48(%rsp), %r8
.Ltmp52:
	movl	%ebx, %edx
	callq	_Z22__device_stub__combinePiS_iS_S_
.Ltmp53:
.LBB5_57:                               #   in Loop: Header=BB5_42 Depth=1
.Ltmp54:
	callq	hipDeviceSynchronize
.Ltmp55:
# %bb.58:                               #   in Loop: Header=BB5_42 Depth=1
.Ltmp56:
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp57:
# %bb.59:                               #   in Loop: Header=BB5_42 Depth=1
	testl	%eax, %eax
	jne	.LBB5_61
# %bb.60:                               #   in Loop: Header=BB5_42 Depth=1
	movq	40(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	56(%rsp), %rdx
	movq	64(%rsp), %rcx
.Ltmp58:
	movl	%ebx, %r8d
	movl	%ebp, %r9d
	callq	_Z22__device_stub__shufflePiS_S_S_ii
.Ltmp59:
.LBB5_61:                               #   in Loop: Header=BB5_42 Depth=1
.Ltmp60:
	callq	hipDeviceSynchronize
.Ltmp61:
# %bb.62:                               #   in Loop: Header=BB5_42 Depth=1
.Ltmp62:
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp63:
# %bb.63:                               #   in Loop: Header=BB5_42 Depth=1
	testl	%eax, %eax
	jne	.LBB5_65
# %bb.64:                               #   in Loop: Header=BB5_42 Depth=1
	movq	8(%rsp), %rdi
	movq	40(%rsp), %rsi
.Ltmp64:
	movl	%ebx, %edx
	callq	_Z19__device_stub__swapPiS_i
.Ltmp65:
.LBB5_65:                               #   in Loop: Header=BB5_42 Depth=1
.Ltmp66:
	callq	hipDeviceSynchronize
.Ltmp67:
# %bb.66:                               #   in Loop: Header=BB5_42 Depth=1
	addl	%ebp, %ebp
	decl	%r13d
	jne	.LBB5_42
# %bb.67:
	movq	24(%rsp), %r15
	subq	16(%rsp), %r15
	movslq	88(%rsp), %rax                  # 4-byte Folded Reload
	leaq	(%r15,%rax,4), %rdi
	andq	$-4, %rdi
	callq	malloc
	movq	%rax, %r14
	movq	8(%rsp), %rsi
.Ltmp69:
	movq	%rax, %rdi
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
.Ltmp70:
# %bb.68:
	leaq	240(%rsp), %rdi
	callq	_ZNKSt12__basic_fileIcE7is_openEv
	testb	%al, %al
	je	.LBB5_76
# %bb.69:
	movl	(%r14), %esi
.Ltmp71:
	leaq	128(%rsp), %rdi
	callq	_ZNSolsEi
.Ltmp72:
# %bb.70:                               # %.preheader
	cmpl	$2, %ebx
	jl	.LBB5_75
# %bb.71:                               # %.lr.ph149.preheader
	movl	%ebx, %r15d
	movl	$1, %r12d
	leaq	128(%rsp), %rbx
.LBB5_72:                               # %.lr.ph149
                                        # =>This Inner Loop Header: Depth=1
.Ltmp73:
	movl	$.L.str.2, %esi
	movl	$1, %edx
	movq	%rbx, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp74:
# %bb.73:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
                                        #   in Loop: Header=BB5_72 Depth=1
	movl	(%r14,%r12,4), %esi
.Ltmp75:
	movq	%rbx, %rdi
	callq	_ZNSolsEi
.Ltmp76:
# %bb.74:                               #   in Loop: Header=BB5_72 Depth=1
	incq	%r12
	cmpq	%r12, %r15
	jne	.LBB5_72
.LBB5_75:                               # %._crit_edge150
.Ltmp78:
	leaq	128(%rsp), %rdi
	callq	_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv
.Ltmp79:
.LBB5_76:
	movq	8(%rsp), %rdi
.Ltmp80:
	callq	hipFree
.Ltmp81:
# %bb.77:
	movq	40(%rsp), %rdi
.Ltmp82:
	callq	hipFree
.Ltmp83:
# %bb.78:
	movq	56(%rsp), %rdi
.Ltmp84:
	callq	hipFree
.Ltmp85:
# %bb.79:
	movq	80(%rsp), %rdi
.Ltmp86:
	callq	hipFree
.Ltmp87:
# %bb.80:
	movq	72(%rsp), %rdi
.Ltmp88:
	callq	hipFree
.Ltmp89:
# %bb.81:
	movq	48(%rsp), %rdi
.Ltmp90:
	callq	hipFree
.Ltmp91:
# %bb.82:
	movq	64(%rsp), %rdi
.Ltmp92:
	callq	hipFree
.Ltmp93:
# %bb.83:
	movq	%r14, %rdi
	callq	free
	movq	_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
	leaq	136(%rsp), %rdi
	movq	%rax, -8(%rdi)
	movq	_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE+24(%rip), %rcx
	movq	-24(%rax), %rax
	movq	%rcx, 128(%rsp,%rax)
	callq	_ZNSt13basic_filebufIcSt11char_traitsIcEED2Ev
	leaq	376(%rsp), %rdi
	callq	_ZNSt8ios_baseD2Ev
	leaq	640(%rsp), %rdi
	callq	_ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev
	movq	96(%rsp), %rdi
	leaq	112(%rsp), %rax
	cmpq	%rax, %rdi
	je	.LBB5_85
# %bb.84:                               # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i
	callq	_ZdlPv
.LBB5_85:                               # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
	movq	16(%rsp), %rdi
	testq	%rdi, %rdi
	je	.LBB5_87
# %bb.86:
	callq	_ZdlPv
.LBB5_87:                               # %_ZNSt6vectorIiSaIiEED2Ev.exit
	xorl	%eax, %eax
	addq	$1160, %rsp                     # imm = 0x488
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB5_7:
	.cfi_def_cfa_offset 1216
.Ltmp100:
	movl	$.L.str.3, %edi
	callq	_ZSt24__throw_invalid_argumentPKc
.Ltmp101:
# %bb.8:
.LBB5_13:                               # %.critedge.i.i
.Ltmp98:
	movl	$.L.str.3, %edi
	callq	_ZSt20__throw_out_of_rangePKc
.Ltmp99:
# %bb.14:
.LBB5_23:                               # %.loopexit.split-lp
.Ltmp11:
	jmp	.LBB5_89
.LBB5_21:
.Ltmp5:
	movq	%rax, %rbx
	jmp	.LBB5_91
.LBB5_20:
.Ltmp2:
	movq	%rax, %rbx
	jmp	.LBB5_92
.LBB5_24:
.Ltmp97:
	jmp	.LBB5_89
.LBB5_88:
.Ltmp31:
	jmp	.LBB5_89
.LBB5_99:
.Ltmp94:
	jmp	.LBB5_89
.LBB5_97:
.Ltmp14:
	jmp	.LBB5_89
.LBB5_100:
.Ltmp77:
	jmp	.LBB5_89
.LBB5_22:                               # %.loopexit
.Ltmp8:
	jmp	.LBB5_89
.LBB5_9:
.Ltmp102:
	movq	%rax, %rbx
	cmpl	$0, (%rbp)
	jne	.LBB5_90
# %bb.10:
	movl	%r13d, (%rbp)
	jmp	.LBB5_90
.LBB5_98:
.Ltmp68:
.LBB5_89:
	movq	%rax, %rbx
.LBB5_90:
	leaq	128(%rsp), %rdi
	callq	_ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.LBB5_91:
	leaq	640(%rsp), %rdi
	callq	_ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev
.LBB5_92:
	movq	96(%rsp), %rdi
	leaq	112(%rsp), %rax
	cmpq	%rax, %rdi
	je	.LBB5_94
# %bb.93:                               # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i99
	callq	_ZdlPv
.LBB5_94:                               # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit101
	movq	16(%rsp), %rdi
	testq	%rdi, %rdi
	je	.LBB5_96
# %bb.95:
	callq	_ZdlPv
.LBB5_96:                               # %_ZNSt6vectorIiSaIiEED2Ev.exit103
	movq	%rbx, %rdi
	callq	_Unwind_Resume@PLT
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
	.section	.gcc_except_table,"a",@progbits
	.p2align	2, 0x0
GCC_except_table5:
.Lexception0:
	.byte	255                             # @LPStart Encoding = omit
	.byte	255                             # @TType Encoding = omit
	.byte	1                               # Call site Encoding = uleb128
	.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
	.uleb128 .Ltmp0-.Lfunc_begin0           # >> Call Site 1 <<
	.uleb128 .Ltmp1-.Ltmp0                  #   Call between .Ltmp0 and .Ltmp1
	.uleb128 .Ltmp2-.Lfunc_begin0           #     jumps to .Ltmp2
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp3-.Lfunc_begin0           # >> Call Site 2 <<
	.uleb128 .Ltmp4-.Ltmp3                  #   Call between .Ltmp3 and .Ltmp4
	.uleb128 .Ltmp5-.Lfunc_begin0           #     jumps to .Ltmp5
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp6-.Lfunc_begin0           # >> Call Site 3 <<
	.uleb128 .Ltmp7-.Ltmp6                  #   Call between .Ltmp6 and .Ltmp7
	.uleb128 .Ltmp8-.Lfunc_begin0           #     jumps to .Ltmp8
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp95-.Lfunc_begin0          # >> Call Site 4 <<
	.uleb128 .Ltmp96-.Ltmp95                #   Call between .Ltmp95 and .Ltmp96
	.uleb128 .Ltmp97-.Lfunc_begin0          #     jumps to .Ltmp97
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp9-.Lfunc_begin0           # >> Call Site 5 <<
	.uleb128 .Ltmp10-.Ltmp9                 #   Call between .Ltmp9 and .Ltmp10
	.uleb128 .Ltmp11-.Lfunc_begin0          #     jumps to .Ltmp11
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp12-.Lfunc_begin0          # >> Call Site 6 <<
	.uleb128 .Ltmp13-.Ltmp12                #   Call between .Ltmp12 and .Ltmp13
	.uleb128 .Ltmp14-.Lfunc_begin0          #     jumps to .Ltmp14
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp15-.Lfunc_begin0          # >> Call Site 7 <<
	.uleb128 .Ltmp30-.Ltmp15                #   Call between .Ltmp15 and .Ltmp30
	.uleb128 .Ltmp31-.Lfunc_begin0          #     jumps to .Ltmp31
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp32-.Lfunc_begin0          # >> Call Site 8 <<
	.uleb128 .Ltmp67-.Ltmp32                #   Call between .Ltmp32 and .Ltmp67
	.uleb128 .Ltmp68-.Lfunc_begin0          #     jumps to .Ltmp68
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp69-.Lfunc_begin0          # >> Call Site 9 <<
	.uleb128 .Ltmp72-.Ltmp69                #   Call between .Ltmp69 and .Ltmp72
	.uleb128 .Ltmp94-.Lfunc_begin0          #     jumps to .Ltmp94
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp73-.Lfunc_begin0          # >> Call Site 10 <<
	.uleb128 .Ltmp76-.Ltmp73                #   Call between .Ltmp73 and .Ltmp76
	.uleb128 .Ltmp77-.Lfunc_begin0          #     jumps to .Ltmp77
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp78-.Lfunc_begin0          # >> Call Site 11 <<
	.uleb128 .Ltmp93-.Ltmp78                #   Call between .Ltmp78 and .Ltmp93
	.uleb128 .Ltmp94-.Lfunc_begin0          #     jumps to .Ltmp94
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp100-.Lfunc_begin0         # >> Call Site 12 <<
	.uleb128 .Ltmp99-.Ltmp100               #   Call between .Ltmp100 and .Ltmp99
	.uleb128 .Ltmp102-.Lfunc_begin0         #     jumps to .Ltmp102
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp99-.Lfunc_begin0          # >> Call Site 13 <<
	.uleb128 .Lfunc_end5-.Ltmp99            #   Call between .Ltmp99 and .Lfunc_end5
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
.Lcst_end0:
	.p2align	2, 0x0
                                        # -- End function
	.section	.text._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,comdat
	.weak	_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_ # -- Begin function _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
	.p2align	1, 0x90
	.type	_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,@function
_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_: # @_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdx, (%rsp)                    # 8-byte Spill
	movq	%rsi, %r12
	movq	%rdi, %rbx
	movl	$1, %esi
	movl	$.L.str.4, %edx
	callq	_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc
	movq	(%rbx), %r13
	movq	8(%rbx), %r15
	movq	%r12, 8(%rsp)                   # 8-byte Spill
	subq	%r13, %r12
	movq	%r12, %r14
	sarq	$2, %r14
	testq	%rax, %rax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	je	.LBB6_1
# %bb.2:
	movq	%rbx, %rdi
	movq	%rax, %rsi
	xorl	%edx, %edx
	callq	_ZNSt15__new_allocatorIiE8allocateEmPKv
	movq	%rax, %rbp
	jmp	.LBB6_3
.LBB6_1:
	xorl	%ebp, %ebp
.LBB6_3:                                # %_ZNSt12_Vector_baseIiSaIiEE11_M_allocateEm.exit
	movq	(%rsp), %rax                    # 8-byte Reload
	movl	(%rax), %eax
	movl	%eax, (%rbp,%r14,4)
	testq	%r12, %r12
	jle	.LBB6_5
# %bb.4:
	movq	%rbp, %rdi
	movq	%r13, %rsi
	movq	%r12, %rdx
	callq	memmove@PLT
.LBB6_5:                                # %_ZNSt6vectorIiSaIiEE11_S_relocateEPiS2_S2_RS0_.exit
	addq	%rbp, %r12
	addq	$4, %r12
	movq	8(%rsp), %rsi                   # 8-byte Reload
	subq	%rsi, %r15
	testq	%r15, %r15
	jle	.LBB6_7
# %bb.6:
	movq	%r12, %rdi
	movq	%r15, %rdx
	callq	memmove@PLT
.LBB6_7:                                # %_ZNSt6vectorIiSaIiEE11_S_relocateEPiS2_S2_RS0_.exit16
	testq	%r13, %r13
	je	.LBB6_9
# %bb.8:
	movq	%r13, %rdi
	callq	_ZdlPv
.LBB6_9:                                # %_ZNSt12_Vector_baseIiSaIiEE13_M_deallocateEPim.exit
	addq	%r15, %r12
	movq	%rbp, (%rbx)
	movq	%r12, 8(%rbx)
	movq	16(%rsp), %rax                  # 8-byte Reload
	leaq	(,%rax,4), %rax
	addq	%rbp, %rax
	movq	%rax, 16(%rbx)
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, .Lfunc_end6-_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
	.cfi_endproc
                                        # -- End function
	.section	.text._ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc,"axG",@progbits,_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc,comdat
	.weak	_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc # -- Begin function _ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc
	.p2align	1, 0x90
	.type	_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc,@function
_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc: # @_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc
	.cfi_startproc
# %bb.0:
	movabsq	$2305843009213693951, %rcx      # imm = 0x1FFFFFFFFFFFFFFF
	movq	8(%rdi), %r8
	subq	(%rdi), %r8
	sarq	$2, %r8
	movq	%rcx, %rax
	subq	%r8, %rax
	cmpq	%rsi, %rax
	jb	.LBB7_2
# %bb.1:
	cmpq	%rsi, %r8
	cmovaq	%r8, %rsi
	leaq	(%rsi,%r8), %rax
	cmpq	%rcx, %rax
	cmovaeq	%rcx, %rax
	addq	%r8, %rsi
	cmovbq	%rcx, %rax
	retq
.LBB7_2:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movq	%rdx, %rdi
	callq	_ZSt20__throw_length_errorPKc
.Lfunc_end7:
	.size	_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc, .Lfunc_end7-_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc
	.cfi_endproc
                                        # -- End function
	.section	.text._ZNSt15__new_allocatorIiE8allocateEmPKv,"axG",@progbits,_ZNSt15__new_allocatorIiE8allocateEmPKv,comdat
	.weak	_ZNSt15__new_allocatorIiE8allocateEmPKv # -- Begin function _ZNSt15__new_allocatorIiE8allocateEmPKv
	.p2align	1, 0x90
	.type	_ZNSt15__new_allocatorIiE8allocateEmPKv,@function
_ZNSt15__new_allocatorIiE8allocateEmPKv: # @_ZNSt15__new_allocatorIiE8allocateEmPKv
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movq	%rsi, %rax
	shrq	$61, %rax
	jne	.LBB8_1
# %bb.3:
	shlq	$2, %rsi
	movq	%rsi, %rdi
	popq	%rax
	.cfi_def_cfa_offset 8
	jmp	_Znwm                           # TAILCALL
.LBB8_1:
	.cfi_def_cfa_offset 16
	shrq	$62, %rsi
	je	.LBB8_2
# %bb.4:
	callq	_ZSt28__throw_bad_array_new_lengthv
.LBB8_2:
	callq	_ZSt17__throw_bad_allocv
.Lfunc_end8:
	.size	_ZNSt15__new_allocatorIiE8allocateEmPKv, .Lfunc_end8-_ZNSt15__new_allocatorIiE8allocateEmPKv
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB9_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB9_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16global_get_flagsPiS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7prescanPiS_S_ib, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7combinePiS_iS_S_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7shufflePiS_S_S_ii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4swapPiS_i, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end9:
	.size	__hip_module_ctor, .Lfunc_end9-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB10_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB10_2:
	retq
.Lfunc_end10:
	.size	__hip_module_dtor, .Lfunc_end10-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z16global_get_flagsPiS_ii,@object # @_Z16global_get_flagsPiS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z16global_get_flagsPiS_ii
	.p2align	3, 0x0
_Z16global_get_flagsPiS_ii:
	.quad	_Z31__device_stub__global_get_flagsPiS_ii
	.size	_Z16global_get_flagsPiS_ii, 8

	.type	_Z7prescanPiS_S_ib,@object      # @_Z7prescanPiS_S_ib
	.globl	_Z7prescanPiS_S_ib
	.p2align	3, 0x0
_Z7prescanPiS_S_ib:
	.quad	_Z22__device_stub__prescanPiS_S_ib
	.size	_Z7prescanPiS_S_ib, 8

	.type	_Z7combinePiS_iS_S_,@object     # @_Z7combinePiS_iS_S_
	.globl	_Z7combinePiS_iS_S_
	.p2align	3, 0x0
_Z7combinePiS_iS_S_:
	.quad	_Z22__device_stub__combinePiS_iS_S_
	.size	_Z7combinePiS_iS_S_, 8

	.type	_Z7shufflePiS_S_S_ii,@object    # @_Z7shufflePiS_S_S_ii
	.globl	_Z7shufflePiS_S_S_ii
	.p2align	3, 0x0
_Z7shufflePiS_S_S_ii:
	.quad	_Z22__device_stub__shufflePiS_S_S_ii
	.size	_Z7shufflePiS_S_S_ii, 8

	.type	_Z4swapPiS_i,@object            # @_Z4swapPiS_i
	.globl	_Z4swapPiS_i
	.p2align	3, 0x0
_Z4swapPiS_i:
	.quad	_Z19__device_stub__swapPiS_i
	.size	_Z4swapPiS_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"inp.txt"
	.size	.L.str, 8

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"q4.txt"
	.size	.L.str.1, 7

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	","
	.size	.L.str.2, 2

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"stoi"
	.size	.L.str.3, 5

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"vector::_M_realloc_insert"
	.size	.L.str.4, 26

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z16global_get_flagsPiS_ii"
	.size	.L__unnamed_1, 27

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z7prescanPiS_S_ib"
	.size	.L__unnamed_2, 19

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z7combinePiS_iS_S_"
	.size	.L__unnamed_3, 20

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z7shufflePiS_S_S_ii"
	.size	.L__unnamed_4, 21

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z4swapPiS_i"
	.size	.L__unnamed_5, 13

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z31__device_stub__global_get_flagsPiS_ii
	.addrsig_sym _Z22__device_stub__prescanPiS_S_ib
	.addrsig_sym _Z22__device_stub__combinePiS_iS_S_
	.addrsig_sym _Z22__device_stub__shufflePiS_S_S_ii
	.addrsig_sym _Z19__device_stub__swapPiS_i
	.addrsig_sym __gxx_personality_v0
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Unwind_Resume
	.addrsig_sym _Z16global_get_flagsPiS_ii
	.addrsig_sym _Z7prescanPiS_S_ib
	.addrsig_sym _Z7combinePiS_iS_S_
	.addrsig_sym _Z7shufflePiS_S_S_ii
	.addrsig_sym _Z4swapPiS_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z16global_get_flagsPiS_ii ; -- Begin function _Z16global_get_flagsPiS_ii
	.globl	_Z16global_get_flagsPiS_ii
	.p2align	8
	.type	_Z16global_get_flagsPiS_ii,@function
_Z16global_get_flagsPiS_ii:             ; @_Z16global_get_flagsPiS_ii
; %bb.0:
	s_clause 0x2
	s_load_b32 s6, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s6, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	v_cmp_gt_i32_e32 vcc_lo, s5, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_mov_b32_e32 v2, 0
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v2, s4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
.LBB0_2:                                ; %._crit_edge
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16global_get_flagsPiS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z16global_get_flagsPiS_ii, .Lfunc_end0-_Z16global_get_flagsPiS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 180
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7prescanPiS_S_ib      ; -- Begin function _Z7prescanPiS_S_ib
	.globl	_Z7prescanPiS_S_ib
	.p2align	8
	.type	_Z7prescanPiS_S_ib,@function
_Z7prescanPiS_S_ib:                     ; @_Z7prescanPiS_S_ib
; %bb.0:
	s_clause 0x1
	s_load_b32 s9, s[0:1], 0x2c
	s_load_b256 s[0:7], s[0:1], 0x0
	s_mov_b32 s8, s15
	s_mov_b32 s13, 1
	s_waitcnt lgkmcnt(0)
	s_and_b32 s9, s9, 0xffff
	s_cmp_gt_i32 s6, 1
	v_mad_u64_u32 v[1:2], null, s8, s9, v[0:1]
	s_mul_i32 s9, s15, s6
	s_cselect_b32 s12, -1, 0
	s_cmp_lt_i32 s6, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[1:2], v3, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_5
; %bb.1:                                ; %.lr.ph
	v_mov_b32_e32 v2, 0
	s_add_i32 s10, s9, -1
	s_add_i32 s11, s9, s6
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_lshl_b32 s14, s13, 1
	s_mov_b32 s15, exec_lo
	v_mul_lo_u32 v1, s14, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, s10, s14, v1
	v_cmpx_gt_u32_e64 s11, v3
	s_cbranch_execz .LBB1_4
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	v_add3_u32 v1, s10, s13, v1
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_clause 0x1
	global_load_b32 v1, v[5:6], off
	global_load_b32 v5, v[3:4], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v1, v5, v1
	global_store_b32 v[3:4], v1, off
.LBB1_4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_cmp_ge_i32 s14, s6
	s_mov_b32 s13, s14
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB1_2
.LBB1_5:                                ; %._crit_edge
	s_mov_b32 s11, 0
	s_mov_b32 s13, exec_lo
	s_barrier
	buffer_gl0_inv
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_7
; %bb.6:
	s_add_i32 s10, s8, 1
	v_mov_b32_e32 v1, 0
	s_mul_i32 s10, s10, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s10, s10, -1
	s_lshl_b64 s[10:11], s[10:11], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s10, s0, s10
	s_addc_u32 s11, s1, s11
	global_store_b32 v1, v1, s[10:11]
.LBB1_7:
	s_or_b32 exec_lo, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB1_12
; %bb.8:                                ; %.lr.ph63
	s_add_i32 s10, s9, -1
	s_add_i32 s9, s9, s6
	s_mov_b32 s11, s6
.LBB1_9:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_and_b32 s12, s11, 0x7ffffffe
	s_mov_b32 s13, exec_lo
	v_mul_lo_u32 v2, s12, v0
	v_add3_u32 v1, s10, s12, v2
	s_lshr_b32 s12, s11, 1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s9, v1
	s_cbranch_execz .LBB1_11
; %bb.10:                               ;   in Loop: Header=BB1_9 Depth=1
	v_add3_u32 v3, s10, s12, v2
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v5, v[3:4], off
	global_load_b32 v6, v[1:2], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, v6, v5
	s_clause 0x1
	global_store_b32 v[3:4], v6, off
	global_store_b32 v[1:2], v5, off
.LBB1_11:                               ;   in Loop: Header=BB1_9 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_cmp_lt_u32 s11, 4
	s_mov_b32 s11, s12
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB1_9
.LBB1_12:                               ; %._crit_edge64
	s_bitcmp1_b32 s7, 0
	s_cselect_b32 s7, -1, 0
	s_add_i32 s9, s6, -1
	s_barrier
	v_cmp_eq_u32_e32 vcc_lo, s9, v0
	buffer_gl0_inv
	s_and_b32 s9, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s7, s9
	s_cbranch_execz .LBB1_14
; %bb.13:
	s_add_i32 s9, s8, 1
	s_mov_b32 s11, 0
	s_mul_i32 s6, s9, s6
	v_mov_b32_e32 v0, 0
	s_add_i32 s10, s6, -1
	s_mov_b32 s9, s11
	s_lshl_b64 s[12:13], s[10:11], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s0, s12
	s_addc_u32 s1, s1, s13
	s_add_u32 s4, s4, s12
	s_addc_u32 s5, s5, s13
	s_clause 0x1
	global_load_b32 v1, v0, s[0:1]
	global_load_b32 v2, v0, s[4:5]
	s_lshl_b64 s[0:1], s[8:9], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v1, v2, v1
	global_store_b32 v0, v1, s[0:1]
.LBB1_14:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7prescanPiS_S_ib
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z7prescanPiS_S_ib, .Lfunc_end1-_Z7prescanPiS_S_ib
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 816
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7combinePiS_iS_S_     ; -- Begin function _Z7combinePiS_iS_S_
	.globl	_Z7combinePiS_iS_S_
	.p2align	8
	.type	_Z7combinePiS_iS_S_,@function
_Z7combinePiS_iS_S_:                    ; @_Z7combinePiS_iS_S_
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s8, s[0:1], 0x34
	s_mov_b32 s2, s15
	s_mov_b32 s3, 0
	s_mov_b32 s9, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB2_2
; %bb.1:
	s_lshl_b64 s[10:11], s[2:3], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s6, s6, s10
	s_addc_u32 s7, s7, s11
	s_load_b32 s3, s[6:7], 0x0
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s3
	ds_store_b32 v1, v2
.LBB2_2:
	s_or_b32 exec_lo, exec_lo, s9
	s_load_b32 s3, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, 0xffff, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s2, s6, v[0:1]
	s_mov_b32 s2, exec_lo
	s_barrier
	buffer_gl0_inv
	v_ashrrev_i32_e32 v2, 31, v1
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB2_4
; %bb.3:
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_mov_b32_e32 v5, 0
	ds_load_b32 v5, v5
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v0, v[3:4], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v0, v0, v5
	global_store_b32 v[3:4], v0, off
.LBB2_4:
	s_or_b32 exec_lo, exec_lo, s2
	s_add_i32 s3, s3, -1
	s_mov_b32 s2, exec_lo
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmpx_eq_u32_e64 s3, v1
	s_cbranch_execz .LBB2_6
; %bb.5:
	s_load_b128 s[8:11], s[0:1], 0x18
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, v0, v2
	global_store_b32 v1, v0, s[8:9]
.LBB2_6:
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7combinePiS_iS_S_
		.amdhsa_group_segment_fixed_size 4
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z7combinePiS_iS_S_, .Lfunc_end2-_Z7combinePiS_iS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 360
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7shufflePiS_S_S_ii    ; -- Begin function _Z7shufflePiS_S_S_ii
	.globl	_Z7shufflePiS_S_S_ii
	.p2align	8
	.type	_Z7shufflePiS_S_S_ii,@function
_Z7shufflePiS_S_S_ii:                   ; @_Z7shufflePiS_S_S_ii
; %bb.0:
	s_clause 0x2
	s_load_b32 s12, s[0:1], 0x34
	s_load_b64 s[2:3], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s12, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[2:3], null, s15, s0, v[0:1]
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	v_cmp_gt_i32_e32 vcc_lo, s2, v2
	v_ashrrev_i32_e32 v3, 31, v2
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB3_2
; %bb.1:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_add_co_u32 v0, s0, s8, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v1, s0, s9, v1, s0
	s_load_b32 s0, s[10:11], 0x0
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	v_sub_nc_u32_e32 v0, v2, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, s0, v0
	v_ashrrev_i32_e32 v1, 31, v0
.LBB3_2:
	s_or_b32 exec_lo, exec_lo, s1
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB3_6
; %bb.3:
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v5, s3, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB3_5
; %bb.4:
	v_add_co_u32 v0, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v3, vcc_lo
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v1, 31, v0
.LBB3_5:                                ; %.sink.split
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_store_b32 v[0:1], v4, off
.LBB3_6:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7shufflePiS_S_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z7shufflePiS_S_S_ii, .Lfunc_end3-_Z7shufflePiS_S_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 320
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z4swapPiS_i            ; -- Begin function _Z4swapPiS_i
	.globl	_Z4swapPiS_i
	.p2align	8
	.type	_Z4swapPiS_i,@function
_Z4swapPiS_i:                           ; @_Z4swapPiS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s3, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB4_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off
.LBB4_2:
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4swapPiS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z4swapPiS_i, .Lfunc_end4-_Z4swapPiS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 172
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16global_get_flagsPiS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z16global_get_flagsPiS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           1
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
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        .size:           4
        .value_kind:     hidden_block_count_y
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        .size:           4
        .value_kind:     hidden_block_count_z
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        .size:           2
        .value_kind:     hidden_group_size_x
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        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7prescanPiS_S_ib
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7prescanPiS_S_ib.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
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        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 4
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7combinePiS_iS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7combinePiS_iS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
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        .size:           2
        .value_kind:     hidden_group_size_y
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        .size:           2
        .value_kind:     hidden_group_size_z
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        .size:           2
        .value_kind:     hidden_remainder_x
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        .size:           2
        .value_kind:     hidden_remainder_y
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        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7shufflePiS_S_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7shufflePiS_S_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
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      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
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        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4swapPiS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z4swapPiS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
