#include "includes.h"
__global__ void conv2genericrev(float *input, float *kernel, float *output, int input_n, int input_h, int input_w, int kernel_n, int kernel_h, int kernel_w, float alpha, int stride_h, int stride_w)
{
// output dimensions
int output_h = input_h - (kernel_h - 1) * stride_h;
int output_w = input_w - (kernel_w - 1) * stride_w;

// this thread only processes one output, defined by the block Ids
int kk = blockIdx.x;
int ii = blockIdx.y;

// batch id
int batch = threadIdx.z;

// kernel id
int kid = threadIdx.x;
int nkids = blockDim.x;

// thread ID
int tid = kid + batch*blockDim.x;
int nthreads = blockDim.x * blockDim.z;

// one thread only sees one output
output = output + (kk * input_n + ii) * output_h*output_w;

// put the output in shared memory
__shared__ float shared_output[CUDA_SHARED_MEM_SIZE];

// generate tid outputs in shared memory
float *output_s = shared_output + tid*output_w*output_h;

// convolution loop
int xx, yy, kx, ky;
yy = threadIdx.y;
float *output_p = output_s + yy * output_w;
for(xx=0; xx<output_w; xx++) {
// Dot product in two dimensions... (between input image and kernel)
float *input_p = input + (ii + batch*input_n)*input_h*input_w + yy*stride_h*input_w + xx*stride_w;
float *kernel_p = kernel + (kk + batch*kernel_n)*kernel_w*kernel_h;
float sum = 0;
for(ky=0; ky<kernel_h; ky++) {
for(kx=kid; kx<kernel_w; kx+=nkids) {
sum += input_p[kx]*kernel_p[kx];
}
input_p += input_w;
kernel_p += kernel_w;
}
*(output_p++) = sum;
}
__syncthreads();

// reduce and write back
if (yy == 0) {
// reduce outputs
for (int k=1; k<nthreads; k++) {
for (int i=tid; i<output_w*output_h; i+=nthreads) {
shared_output[i] += shared_output[k*output_h*output_w + i];
}
}
__syncthreads();

// add existing output, and write back
for (int i=tid; i<output_w*output_h; i+=nthreads) {
output[i] += alpha*shared_output[i];
}
}
}
	.file	"tmpxft_002d3c0e_00000000-6_conv2genericrev.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z48__device_stub__Z15conv2genericrevPfS_S_iiiiiifiiPfS_S_iiiiiifii
	.type	_Z48__device_stub__Z15conv2genericrevPfS_S_iiiiiifiiPfS_S_iiiiiifii, @function
_Z48__device_stub__Z15conv2genericrevPfS_S_iiiiiifiiPfS_S_iiiiiifii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movss	%xmm0, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z15conv2genericrevPfS_S_iiiiiifii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 256
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L2:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z48__device_stub__Z15conv2genericrevPfS_S_iiiiiifiiPfS_S_iiiiiifii, .-_Z48__device_stub__Z15conv2genericrevPfS_S_iiiiiifiiPfS_S_iiiiiifii
	.globl	_Z15conv2genericrevPfS_S_iiiiiifii
	.type	_Z15conv2genericrevPfS_S_iiiiiifii, @function
_Z15conv2genericrevPfS_S_iiiiiifii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z15conv2genericrevPfS_S_iiiiiifiiPfS_S_iiiiiifii
	.cfi_endproc
.LFE2033:
	.size	_Z15conv2genericrevPfS_S_iiiiiifii, .-_Z15conv2genericrevPfS_S_iiiiiifii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z15conv2genericrevPfS_S_iiiiiifii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z15conv2genericrevPfS_S_iiiiiifii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void conv2genericrev(float *input, float *kernel, float *output, int input_n, int input_h, int input_w, int kernel_n, int kernel_h, int kernel_w, float alpha, int stride_h, int stride_w)
{
// output dimensions
int output_h = input_h - (kernel_h - 1) * stride_h;
int output_w = input_w - (kernel_w - 1) * stride_w;

// this thread only processes one output, defined by the block Ids
int kk = blockIdx.x;
int ii = blockIdx.y;

// batch id
int batch = threadIdx.z;

// kernel id
int kid = threadIdx.x;
int nkids = blockDim.x;

// thread ID
int tid = kid + batch*blockDim.x;
int nthreads = blockDim.x * blockDim.z;

// one thread only sees one output
output = output + (kk * input_n + ii) * output_h*output_w;

// put the output in shared memory
__shared__ float shared_output[CUDA_SHARED_MEM_SIZE];

// generate tid outputs in shared memory
float *output_s = shared_output + tid*output_w*output_h;

// convolution loop
int xx, yy, kx, ky;
yy = threadIdx.y;
float *output_p = output_s + yy * output_w;
for(xx=0; xx<output_w; xx++) {
// Dot product in two dimensions... (between input image and kernel)
float *input_p = input + (ii + batch*input_n)*input_h*input_w + yy*stride_h*input_w + xx*stride_w;
float *kernel_p = kernel + (kk + batch*kernel_n)*kernel_w*kernel_h;
float sum = 0;
for(ky=0; ky<kernel_h; ky++) {
for(kx=kid; kx<kernel_w; kx+=nkids) {
sum += input_p[kx]*kernel_p[kx];
}
input_p += input_w;
kernel_p += kernel_w;
}
*(output_p++) = sum;
}
__syncthreads();

// reduce and write back
if (yy == 0) {
// reduce outputs
for (int k=1; k<nthreads; k++) {
for (int i=tid; i<output_w*output_h; i+=nthreads) {
shared_output[i] += shared_output[k*output_h*output_w + i];
}
}
__syncthreads();

// add existing output, and write back
for (int i=tid; i<output_w*output_h; i+=nthreads) {
output[i] += alpha*shared_output[i];
}
}
}
	.text
	.file	"conv2genericrev.hip"
	.globl	_Z30__device_stub__conv2genericrevPfS_S_iiiiiifii # -- Begin function _Z30__device_stub__conv2genericrevPfS_S_iiiiiifii
	.type	_Z30__device_stub__conv2genericrevPfS_S_iiiiiifii,@function
_Z30__device_stub__conv2genericrevPfS_S_iiiiiifii: # @_Z30__device_stub__conv2genericrevPfS_S_iiiiiifii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	8(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	movq	%r9, 72(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15conv2genericrevPfS_S_iiiiiifii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__conv2genericrevPfS_S_iiiiiifii, .Lfunc_end0-_Z30__device_stub__conv2genericrevPfS_S_iiiiiifii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15conv2genericrevPfS_S_iiiiiifii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15conv2genericrevPfS_S_iiiiiifii,@object # @_Z15conv2genericrevPfS_S_iiiiiifii
	.section	.rodata,"a",@progbits
	.globl	_Z15conv2genericrevPfS_S_iiiiiifii
	.p2align	3, 0x0
_Z15conv2genericrevPfS_S_iiiiiifii:
	.quad	_Z30__device_stub__conv2genericrevPfS_S_iiiiiifii
	.size	_Z15conv2genericrevPfS_S_iiiiiifii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z15conv2genericrevPfS_S_iiiiiifii"
	.size	.L__unnamed_1, 35

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__conv2genericrevPfS_S_iiiiiifii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15conv2genericrevPfS_S_iiiiiifii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15conv2genericrevPfS_S_iiiiiifii ; -- Begin function _Z15conv2genericrevPfS_S_iiiiiifii
	.globl	_Z15conv2genericrevPfS_S_iiiiiifii
	.p2align	8
	.type	_Z15conv2genericrevPfS_S_iiiiiifii,@function
_Z15conv2genericrevPfS_S_iiiiiifii:     ; @_Z15conv2genericrevPfS_S_iiiiiifii
; %bb.0:
	s_mov_b32 s2, s15
	s_clause 0x4
	s_load_b256 s[4:11], s[0:1], 0x18
	s_load_b64 s[20:21], s[0:1], 0x4c
	s_load_b32 s15, s[0:1], 0x38
	s_load_b128 s[16:19], s[0:1], 0x0
	s_load_b64 s[12:13], s[0:1], 0x10
	v_bfe_u32 v1, v0, 20, 10
	v_and_b32_e32 v5, 0x3ff, v0
	v_bfe_u32 v6, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_add_i32 s0, s8, -1
	s_add_i32 s1, s9, -1
	s_and_b32 s3, s20, 0xffff
	s_mul_i32 s0, s0, s11
	s_mul_i32 s1, s1, s15
	v_mad_u32_u24 v4, v1, s3, v5
	s_sub_i32 s20, s6, s1
	s_sub_i32 s0, s5, s0
	s_cmp_lt_i32 s20, 1
	s_mul_i32 s1, s20, s0
	s_cbranch_scc1 .LBB0_11
; %bb.1:                                ; %.lr.ph115
	v_mad_u64_u32 v[2:3], null, v1, s4, s[2:3]
	v_mul_lo_u32 v0, v6, s6
	v_mul_lo_u32 v11, s1, v4
	s_cmp_gt_i32 s8, 0
	v_cmp_gt_i32_e64 s0, s9, v5
	s_mov_b32 s24, s9
	s_mov_b32 s22, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v7, v2, s5
	v_mad_u64_u32 v[2:3], null, v1, s7, s[14:15]
	v_mul_lo_u32 v0, v0, s11
	s_mul_i32 s5, s9, s8
	v_mul_lo_u32 v3, s20, v6
	v_mul_lo_u32 v8, v7, s6
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v2, s5, v2
	v_lshlrev_b32_e32 v7, 2, v5
	v_ashrrev_i32_e32 v1, 31, v0
	s_cselect_b32 s5, -1, 0
	v_lshlrev_b32_e32 v12, 2, v3
	s_ashr_i32 s7, s6, 31
	s_ashr_i32 s25, s9, 31
	v_ashrrev_i32_e32 v9, 31, v8
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_lshl_b64 s[6:7], s[6:7], 2
	s_lshl_b32 s11, s3, 2
	v_lshlrev_b64 v[9:10], 2, v[8:9]
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_lshl_add_u32 v8, v11, 2, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v9, vcc_lo, v0, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, v1, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s18, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s19, v3, vcc_lo
	v_add_co_u32 v9, vcc_lo, s16, v9
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v10, vcc_lo, s17, v10, vcc_lo
	s_lshl_b64 s[16:17], s[24:25], 2
	s_mov_b32 s24, 0
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;       Child Loop BB0_6 Depth 3
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB0_9
; %bb.3:                                ; %.preheader103.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_ashr_i32 s23, s22, 31
	v_mov_b32_e32 v3, v1
	s_lshl_b64 s[18:19], s[22:23], 2
	v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v2, v0
	v_add_co_u32 v12, vcc_lo, v9, s18
	v_add_co_ci_u32_e32 v13, vcc_lo, s19, v10, vcc_lo
	s_mov_b32 s23, 0
.LBB0_4:                                ; %.preheader103
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_6 Depth 3
	s_and_saveexec_b32 s25, s0
	s_cbranch_execz .LBB0_8
; %bb.5:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_4 Depth=2
	v_add_co_u32 v14, vcc_lo, v12, v7
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v13, vcc_lo
	v_add_co_u32 v16, vcc_lo, v2, v7
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v3, vcc_lo
	v_mov_b32_e32 v18, v5
	s_mov_b64 s[18:19], 0
	s_mov_b32 s26, 0
.LBB0_6:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_add_co_u32 v19, vcc_lo, v14, s18
	v_add_co_ci_u32_e32 v20, vcc_lo, s19, v15, vcc_lo
	v_add_co_u32 v21, vcc_lo, v16, s18
	v_add_co_ci_u32_e32 v22, vcc_lo, s19, v17, vcc_lo
	s_add_u32 s18, s18, s11
	global_load_b32 v19, v[19:20], off
	global_load_b32 v20, v[21:22], off
	v_add_nc_u32_e32 v18, s3, v18
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v11, v19, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s9, v18
	s_or_b32 s26, vcc_lo, s26
	s_and_not1_b32 exec_lo, exec_lo, s26
	s_cbranch_execnz .LBB0_6
; %bb.7:                                ; %Flow190
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s26
.LBB0_8:                                ; %Flow191
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s25
	v_add_co_u32 v12, vcc_lo, v12, s6
	v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, s16
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v3, vcc_lo
	s_add_i32 s23, s23, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s23, s8
	s_cbranch_scc1 .LBB0_4
	s_branch .LBB0_10
.LBB0_9:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v11, 0
.LBB0_10:                               ; %._crit_edge110
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v2, 4, v8
	ds_store_b32 v8, v11
	s_add_i32 s24, s24, 1
	s_add_i32 s22, s22, s15
	s_cmp_lt_i32 s24, s20
	v_mov_b32_e32 v8, v2
	s_cbranch_scc1 .LBB0_2
.LBB0_11:                               ; %._crit_edge116
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB0_21
; %bb.12:                               ; %.preheader102
	s_and_b32 s0, 0xffff, s21
	v_cmp_gt_i32_e32 vcc_lo, s1, v4
	s_mul_i32 s6, s0, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s6, 2
	s_cbranch_scc1 .LBB0_18
; %bb.13:                               ; %.preheader.lr.ph
	v_add_lshl_u32 v0, v4, s1, 2
	v_lshlrev_b32_e32 v1, 2, v4
	s_lshl_b32 s3, s1, 2
	s_lshl_b32 s5, s6, 2
	s_mov_b32 s7, 1
.LBB0_14:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_16 Depth 2
	s_and_saveexec_b32 s8, vcc_lo
	s_cbranch_execz .LBB0_17
; %bb.15:                               ; %.lr.ph118
                                        ;   in Loop: Header=BB0_14 Depth=1
	v_mov_b32_e32 v2, v4
	s_mov_b32 s9, 0
	s_mov_b32 s11, 0
.LBB0_16:                               ;   Parent Loop BB0_14 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v3, s9, v0
	v_add_nc_u32_e32 v5, s9, v1
	v_add_nc_u32_e32 v2, s6, v2
	s_add_i32 s9, s9, s5
	ds_load_b32 v3, v3
	ds_load_b32 v6, v5
	v_cmp_le_i32_e64 s0, s1, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_or_b32 s11, s0, s11
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v3, v3, v6
	ds_store_b32 v5, v3
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_16
.LBB0_17:                               ; %Flow186
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v0, s3, v0
	s_add_i32 s7, s7, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s7, s6
	s_cbranch_scc0 .LBB0_14
.LBB0_18:                               ; %._crit_edge121
	v_cmp_gt_i32_e32 vcc_lo, s1, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_21
; %bb.19:                               ; %.lr.ph124.preheader
	s_mul_i32 s0, s14, s4
	v_lshlrev_b32_e32 v2, 2, v4
	s_add_i32 s0, s0, s2
	s_mov_b32 s5, 0
	s_mul_i32 s2, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s3, s2, 31
	s_lshl_b64 s[2:3], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_add_u32 s0, s12, s2
	s_addc_u32 s2, s13, s3
	v_add_co_u32 v0, s0, s0, v2
	v_add_co_ci_u32_e64 v1, null, s2, 0, s0
	s_ashr_i32 s7, s6, 31
	s_lshl_b32 s4, s6, 2
	s_lshl_b64 s[2:3], s[6:7], 2
.LBB0_20:                               ; %.lr.ph124
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v3, v[0:1], off
	ds_load_b32 v5, v2
	v_add_nc_u32_e32 v4, s6, v4
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_fmac_f32 v3, s10, v5 :: v_dual_add_nc_u32 v2, s4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_le_i32_e32 vcc_lo, s1, v4
	global_store_b32 v[0:1], v3, off
	v_add_co_u32 v0, s0, v0, s2
	v_add_co_ci_u32_e64 v1, s0, s3, v1, s0
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_20
.LBB0_21:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15conv2genericrevPfS_S_iiiiiifii
		.amdhsa_group_segment_fixed_size 49024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 23
		.amdhsa_next_free_sgpr 27
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15conv2genericrevPfS_S_iiiiiifii, .Lfunc_end0-_Z15conv2genericrevPfS_S_iiiiiifii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1008
; NumSgprs: 29
; NumVgprs: 23
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 49024 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 29
; NumVGPRsForWavesPerEU: 23
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 49024
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15conv2genericrevPfS_S_iiiiiifii
    .private_segment_fixed_size: 0
    .sgpr_count:     29
    .sgpr_spill_count: 0
    .symbol:         _Z15conv2genericrevPfS_S_iiiiiifii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     23
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
