/*#include <cuda_runtime.h>*/
#include <cuda.h>
#include <stdio.h>

__global__ void kernel_vecDotProduct(double* invSigmaMuDev, double* muDev, int fDim, int cbNum, double* resDev) {
	int cbIdx = blockDim.x * blockIdx.x + threadIdx.x;
	if (cbIdx < cbNum) {
		double t = 0;
		double* v1 = invSigmaMuDev + cbIdx * fDim;
		double* v2 = muDev + cbIdx * fDim;
		for (int i = 0; i < fDim; i++) {
			t += v1[i] * v2[i];
		}
		resDev[cbIdx] += t / 2;
	}
}

__global__ void kernel_batchedDgemv(double* invSigmaDev, double* muDev, int fDim, int cbNum, int shareNum, double* resDev) {
	extern __shared__ double sharedMu[];

	int N = blockDim.x;
	int vecLen = N * fDim;
	int maxIdx = cbNum * fDim;
	for (int i = 0; i < (vecLen + blockDim.x - 1) / blockDim.x; i++) {
		int sharedIdx = i * blockDim.x + threadIdx.x;
		int devIdx = blockIdx.x * vecLen + sharedIdx;
		
		if (devIdx < maxIdx)
			sharedMu[sharedIdx] = muDev[devIdx];
	}
	__syncthreads();

	int invSigmaLen = (fDim + 1) * fDim / 2;
	int cbIdx = N * blockIdx.x + threadIdx.x;
	if (cbIdx < cbNum) {
		double* r = resDev + cbIdx * fDim;
		double* v = sharedMu + threadIdx.x * fDim;
		double* A = invSigmaDev + (cbIdx / shareNum) * invSigmaLen;
		for (int i = 0; i < fDim; i++) {
			double t = 0;
			for (int j = 0; j < i; j++)
				t += A[i * (i + 1) / 2 + j] * v[j];

			for (int j = i + 1; j < fDim; j++) 
				t += A[j * (j + 1) / 2 + i] * v[j];

			t += A[i * (i + 1) / 2 + i] * 2 * v[i];

			r[i] = t;
		}
	}
}


__global__ void kernel_lse(int mixNum, double* allAlpha, double* seperateLh, double* combinedLh) {
	extern __shared__ double alpha[];

	for (int i = 0; i < (mixNum + blockDim.x - 1) / blockDim.x; i++) {
		if (i * blockDim.x + threadIdx.x < mixNum) {
			alpha[i * blockDim.x + threadIdx.x] = allAlpha[blockIdx.x * mixNum + blockDim.x * i + threadIdx.x];
		}
	}

	__syncthreads();


	double maxLh = 0;
 	int maxLhIdx = -1;
	for (int i = 0; i < mixNum; i++) {
		if (alpha[i] > 0) {
			int p = gridDim.x * mixNum * threadIdx.x + blockIdx.x * mixNum + i;
			double t = log(alpha[i]) + seperateLh[p];
			//printf("seperateLh[%d] = %f\n", p, seperateLh[p]);
			if (maxLhIdx == -1 || t > maxLh) {
				maxLh = t;
				maxLhIdx = i;
			}
			seperateLh[p] = t;
		}
	}



	for (int i = 0; i < mixNum; i++) {
		if (alpha[i] > 0) {
			int p = gridDim.x * mixNum * threadIdx.x + blockIdx.x * mixNum + i;
			seperateLh[p] -= maxLh;
		}
	}


	for (int i = 0; i < mixNum; i++) {
		if (alpha[i] > 0) {
			int p = gridDim.x * mixNum * threadIdx.x + blockIdx.x * mixNum + i;
			seperateLh[p] = exp(seperateLh[p]);	//ʱseperateLh[p]һС1
		}
	}
	
	double sumExp = 0;
	for (int i = 0; i < mixNum; i++) {
		if (alpha[i] > 0) {
			int p = gridDim.x * mixNum * threadIdx.x + blockIdx.x * mixNum + i;
			sumExp += seperateLh[p];
		}
	}

	double logSumExp = maxLh + log(sumExp);
	combinedLh[gridDim.x * threadIdx.x + blockIdx.x] = logSumExp;


}

extern "C" void logSumExpForGMM(int cbNum, int mixNum, int fNum, double* allAlpha, double* seperateLh, double* combinedLh) {
	int fStep = 128;
	int fExtendNum = ((fNum + fStep - 1) / fStep) * fStep;

	cudaError_t err;

	double* allAlphaDev;
	err = cudaMalloc((void**)&allAlphaDev, cbNum * mixNum * sizeof(double));
	err = cudaMemcpy(allAlphaDev, allAlpha, cbNum * mixNum * sizeof(double), cudaMemcpyHostToDevice);

	double* seperateLhDev;
	err = cudaMalloc((void**)&seperateLhDev, fExtendNum * mixNum * cbNum * sizeof(double));
	err = cudaMemset(seperateLhDev, 0, fExtendNum * mixNum * cbNum * sizeof(double));
	cudaMemcpy(seperateLhDev, seperateLh, cbNum * mixNum * fNum * sizeof(double), cudaMemcpyHostToDevice);

	double* combinedLhDev;
	err = cudaMalloc((void**)&combinedLhDev, fExtendNum * cbNum * sizeof(double));

	//int lastCpyFrameNum = fNum - (fExtendNum - fStep);
	for (int i = 0; i < fExtendNum / fStep; i++) {
		double* lhInDev = seperateLhDev + fStep * mixNum * cbNum * i;
		double* lhOutDev = combinedLhDev + fStep * cbNum * i;
		kernel_lse<<<cbNum, fStep, mixNum * sizeof(double)>>>(mixNum, allAlphaDev, lhInDev, lhOutDev);
		err = cudaDeviceSynchronize();
		if (err != CUDA_SUCCESS) {
			printf("kernel launch failed in LSE with error \"%s\".\n",
			cudaGetErrorString(err));
			exit(-1);
		}
	}

	err = cudaMemcpy(combinedLh, combinedLhDev, fNum * cbNum * sizeof(double), cudaMemcpyDeviceToHost);

//	free(allLogAlpha);
	cudaFree(combinedLhDev);
	cudaFree(seperateLhDev);
	cudaFree(allAlphaDev);
}


__global__ void kernel_mvn_share(int sigmaNum, int fDim, int shareNum, double* invSigma, double* feature, int fNum, double* resBuf)
{	

	extern __shared__ double memory[];

	double* sharedInvSigma = memory;
	int invSigmaLen = fDim * (fDim + 1) / 2;
	int fLen = fNum * fDim;

	double* sharedFt = sharedInvSigma + blockDim.y * invSigmaLen;
	//memset(sharedFt, 0, fDim * fNum * sizeof(double));

	double res = 0;
	int sigmaIdx = blockDim.y * blockIdx.x + threadIdx.y;
	int thIdx = threadIdx.x + threadIdx.y * blockDim.x;
	int thNum = blockDim.x * blockDim.y;

	if (sigmaIdx < sigmaNum)
	{
		for (int i = 0; i < (invSigmaLen + blockDim.x - 1) / blockDim.x; i++)
			if (i * blockDim.x + threadIdx.x < invSigmaLen)
				sharedInvSigma[threadIdx.y * invSigmaLen + i * blockDim.x + threadIdx.x] = invSigma[sigmaIdx * invSigmaLen + i * blockDim.x + threadIdx.x];
	}

	for (int i = 0; i < (fLen + thNum - 1) / thNum; i++)
		if (i * thNum + thIdx < fLen)
			sharedFt[i * thNum + thIdx] = feature[i * thNum + thIdx];

	__syncthreads();

	if (sigmaIdx < sigmaNum) {
		res = 0;
		int idx = 0;
		for (int j = 0; j < fDim; j++) {
			double t1 = sharedFt[threadIdx.x * fDim + j];
			double rest = 0;
			for (int k = 0; k < j; k++) {
				double t2 = sharedFt[threadIdx.x * fDim + k];
				rest += sharedInvSigma[threadIdx.y * invSigmaLen + idx++] * t2;
			}
			rest += sharedInvSigma[threadIdx.y * invSigmaLen + idx++] * t1;
			res += rest * t1;
		}

		int resIdxStart = (sigmaIdx + threadIdx.x * sigmaNum) * shareNum;
		for (int i = 0; i < shareNum; i++) {
			resBuf[resIdxStart + i] -= res;
		}
		//resBuf[resIdx] = -res;
	}
	__syncthreads();
}

__global__ void kernel_share_add_cst(int cbNum, int fNum, double* cst, double* res) {
	double* fVec = res + blockIdx.x * cbNum;
	for (int i = 0; i < (cbNum + blockDim.x - 1) / blockDim.x; i++)
		if (i * blockDim.x + threadIdx.x < cbNum)
			fVec[i * blockDim.x + threadIdx.x] -= cst[i * blockDim.x + threadIdx.x];
}

__global__ void kernel_vecdot2(int cbNum, int fNum, int fDim, double* invSigmaMu, double* fVec, double* resBuf) {
	extern __shared__ double memory[];
	double* sharedFeature = memory;
	double* sharedInvSigmaMu = sharedFeature + fNum * fDim;

	int cbIdx = blockDim.y * blockIdx.x + threadIdx.y;
	int thNum = blockDim.x * blockDim.y;
	int thIdx = threadIdx.y * blockDim.x + threadIdx.x;

	for (int i = 0; i < (fDim * fNum + thNum - 1) / thNum; i++)
		if (i * thNum + thIdx < fDim * fNum)
			sharedFeature[i * thNum + thIdx] = fVec[i * thNum + thIdx];

	if (cbIdx < cbNum) {
		for (int i = 0; i < (fDim + blockDim.x - 1) / blockDim.x; i++)
			if (i * blockDim.x + threadIdx.x < fDim)
				sharedInvSigmaMu[threadIdx.y * fDim + i * blockDim.x + threadIdx.x] = invSigmaMu[cbIdx * fDim + i * blockDim.x + threadIdx.x];
	}


	__syncthreads();

	if (cbIdx < cbNum) {
		int resIdx = threadIdx.x * cbNum + cbIdx;
		double* v1 = sharedFeature + threadIdx.x * fDim;
		double* v2 = sharedInvSigmaMu + threadIdx.y * fDim;
		double res = 0;
		for (int i = 0; i < fDim; i++) {
			res += v1[i] * v2[i];
		}
		resBuf[resIdx] += res;
	}
}

__global__ void kernel_mvn(int cbNum, int fDim, double* invSigma, double* invSigmaMu, double* cst, double* feature, int fNum, double* resBuf)
{	

	extern __shared__ double memory[];

	double* sharedInvSigma = memory;
	int invSigmaLen = fDim * (fDim + 1) / 2;
	int fLen = fNum * fDim;

	double* sharedInvSigmaMu = sharedInvSigma + blockDim.y * invSigmaLen;
	double* sharedCst = sharedInvSigmaMu + blockDim.y * fDim;
	double* sharedFt = sharedCst + blockDim.y;
	//memset(sharedFt, 0, fDim * fNum * sizeof(double));

	double res = 0;
	int cbIdx = blockDim.y * blockIdx.x + threadIdx.y;
	int thIdx = threadIdx.x + threadIdx.y * blockDim.x;
	int thNum = blockDim.x * blockDim.y;

	if (cbIdx < cbNum)
	{
		for (int i = 0; i < (invSigmaLen + blockDim.x - 1) / blockDim.x; i++)
			if (i * blockDim.x + threadIdx.x < invSigmaLen)
				sharedInvSigma[threadIdx.y * invSigmaLen + i * blockDim.x + threadIdx.x] = invSigma[cbIdx * invSigmaLen + i * blockDim.x + threadIdx.x];

		for (int i = 0; i < (fDim + blockDim.x - 1) / blockDim.x; i++)
			if (i * blockDim.x + threadIdx.x < fDim)
				sharedInvSigmaMu[threadIdx.y * fDim + i * blockDim.x + threadIdx.x] = invSigmaMu[cbIdx * fDim + i * blockDim.x + threadIdx.x];
		
		if (threadIdx.x == 0)
			sharedCst[threadIdx.y] = cst[cbIdx];
	}

	for (int i = 0; i < (fLen + thNum - 1) / thNum; i++)
		if (i * thNum + thIdx < fLen)
			sharedFt[i * thNum + thIdx] = feature[i * thNum + thIdx];

	__syncthreads();

	if (cbIdx < cbNum) {
		res = sharedCst[threadIdx.y];
		int idx = 0;
		for (int j = 0; j < fDim; j++) {
			double t1 = sharedFt[threadIdx.x * fDim + j];
			double rest = 0;
			for (int k = 0; k <= j; k++) {
				double t2 = sharedFt[threadIdx.x * fDim + k];
				rest += sharedInvSigma[threadIdx.y * invSigmaLen + idx++] * t2;
			}
			//rest += sharedInvSigma[threadIdx.y * invSigmaLen + idx++] * t1;
			rest -= sharedInvSigmaMu[threadIdx.y * fDim + j];
			res += rest * t1;
		}

		int resIdx = cbIdx + threadIdx.x * cbNum;
		resBuf[resIdx] = -res;
	}
	__syncthreads();
}
//kernel_share_add_cst(int cbNum, int fNum, double* cst, double* res)
extern "C" void kernelShareAddCstWrapper(int cbNum, int fNum, double* cstDev, double* resDev ,dim3 threads, dim3 blocks) {
	kernel_share_add_cst<<< blocks, threads>>>(cbNum, fNum, cstDev, resDev);
	cudaError_t err;
	err = cudaPeekAtLastError();

	if (err != CUDA_SUCCESS) {
		printf("kernel share_add_cst launch failed with error \"%s\".\n",
			cudaGetErrorString(err));
		exit(-1);
	}

	return;
}

extern "C" void kernelVecDotWrapper(double* invSigmaMuDev, double* muDev, int fDim, int cbNum, double* resDev , dim3 threads, dim3 blocks) {
	kernel_vecDotProduct<<< blocks, threads>>>(invSigmaMuDev, muDev, fDim, cbNum, resDev);
	cudaError_t err;
	err = cudaPeekAtLastError();

	if (err != CUDA_SUCCESS) {
		printf("kernel vecdot launch failed with error \"%s\".\n",
			cudaGetErrorString(err));
		exit(-1);
	}

	return;
}

extern "C" void kernelDgemvWrapper(double* invSigmaDev, double* muDev, int fDim, int cbNum, int shareNum, double* resDev , dim3 threads, dim3 blocks, int memSize) {

	kernel_batchedDgemv<<< blocks, threads, memSize>>>(invSigmaDev, muDev, fDim, cbNum, shareNum, resDev);
	
	cudaError_t err = cudaPeekAtLastError();

	if (err != CUDA_SUCCESS) {
		printf("kernel dgemv launch failed with error \"%s\".\n",
			cudaGetErrorString(err));
		exit(-1);
	}

	return;
}

extern "C" void kernelVecDot2Wrapper(double* invSigmaMuDev, double* featureDev, int fDim, int cbNum, int fNum, double* resDev , dim3 threads, dim3 blocks, int memSize) {
	//kernel_vecdot2(int cbNum, int fNum, int fDim, double* invSigmaMu, double* fVec, double* resBuf)
	kernel_vecdot2<<< blocks, threads, memSize>>>(cbNum, fNum, fDim, invSigmaMuDev, featureDev, resDev);
	cudaError_t err;
	err = cudaPeekAtLastError();

	if (err != CUDA_SUCCESS) {
		printf("kernel vecdot2 launch failed with error \"%s\".\n",
			cudaGetErrorString(err));
		exit(-1);
	}

	return;
}

extern "C" void kernelSharedMvnWrapper(int cbNum, int fDim, int mixNum, double* invSigmaDev, double* featureDev, int fNum, double* resBufDev, dim3 threads, dim3 blocks, int memSize) {
	
	kernel_mvn_share<<< blocks, threads, memSize >>>(cbNum / mixNum, fDim, mixNum, invSigmaDev, featureDev, fNum, resBufDev);
	cudaError_t err;
	err = cudaPeekAtLastError();
 	
	if (err != CUDA_SUCCESS) {
		printf("kernel launch failed with error \"%s\".\n",
		cudaGetErrorString(err));
		exit(-1);
	}
	cudaDeviceSynchronize();
	return;
}

extern "C" void kernelMvnWrapper(int cbNum, int fDim, double* invSigmaDev, double* invSigmaMuDev, double* cstDev, double* featureDev, int fNum, double* resBufDev, dim3 threads, dim3 blocks, int memSize) {
	//kernel_mvn(int cbNum, int fDim, double* invSigma, double* invSigmaMu, double* cst, double* feature, int fNum, double* resBuf)
	kernel_mvn<<< blocks, threads, memSize >>>(cbNum, fDim, invSigmaDev, invSigmaMuDev, cstDev, featureDev, fNum, resBufDev);
	cudaError_t err;
	err = cudaPeekAtLastError();

	if (err != CUDA_SUCCESS) {
		printf("kernel launch failed with error \"%s\".\n",
			cudaGetErrorString(err));
		exit(-1);
	}
	cudaDeviceSynchronize();
	return;
}


__global__ void kernel_diag_mvn(int cbNum, int fDim, double* invSigma, double* mu, double* cst, double* feature, int fNum, double* resBuf)
{	

	extern __shared__ double memory[];

	double* sharedInvSigma = memory;
	int fLen = fNum * fDim;

	double* sharedMu = sharedInvSigma + blockDim.y * fDim;
	double* sharedCst = sharedMu + blockDim.y * fDim;
	double* sharedFt = sharedCst + blockDim.y;

	int cbIdx = blockDim.y * blockIdx.x + threadIdx.y;
	int thIdx = threadIdx.x + threadIdx.y * blockDim.x;
	int thNum = blockDim.x * blockDim.y;

	if (cbIdx < cbNum)
	{
		for (int i = 0; i < (fDim + blockDim.x - 1) / blockDim.x; i++)
			if (i * blockDim.x + threadIdx.x < fDim)
				sharedInvSigma[threadIdx.y * fDim + i * blockDim.x + threadIdx.x] = invSigma[cbIdx * fDim + i * blockDim.x + threadIdx.x];

		for (int i = 0; i < (fDim + blockDim.x - 1) / blockDim.x; i++)
			if (i * blockDim.x + threadIdx.x < fDim)
				sharedMu[threadIdx.y * fDim + i * blockDim.x + threadIdx.x] = mu[cbIdx * fDim + i * blockDim.x + threadIdx.x];

		if (threadIdx.x == 0)
			sharedCst[threadIdx.y] = cst[cbIdx];
	}

	for (int i = 0; i < (fLen + thNum - 1) / thNum; i++)
		if (i * thNum + thIdx < fLen)
			sharedFt[i * thNum + thIdx] = feature[i * thNum + thIdx];

	__syncthreads();

	if (cbIdx < cbNum) {
		double res = 0;
		for (int j = 0; j < fDim; j++) {
			double xj = sharedFt[threadIdx.x * fDim + j] - sharedMu[threadIdx.y * fDim + j];
			res += xj * xj * sharedInvSigma[threadIdx.y * fDim + j];
		}
		res = -(sharedCst[threadIdx.y] + res / 2);

		int resIdx = cbIdx + threadIdx.x * cbNum;
		resBuf[resIdx] = res;
	}
	__syncthreads();
}

extern "C" void kernelDiagMvnWrapper(int cbNum, int fDim, double* invSigmaDev, double* muDev, double* cstDev, double* featureDev, int fNum, double* resBufDev, dim3 threads, dim3 blocks, int memSize) {

	
	kernel_diag_mvn<<< blocks, threads, memSize >>>(cbNum, fDim, invSigmaDev, muDev, cstDev, featureDev, fNum, resBufDev);
	cudaError_t err;
	err = cudaDeviceSynchronize();
	
	if (err != CUDA_SUCCESS) {
		printf("kernel launch failed with error \"%s\".\n",
			cudaGetErrorString(err));
		exit(-1);
	}
	
	return;
}
//__global__ void kernel_lse(int mixNum, double* allAlpha, double* seperateLh, double* combinedLh)
extern "C" void kernelLSEWrapper(int cbNum, int fStep, int mixNum, double* alphaDev, double* seperateLhDev, double* combineLhDev) {
	kernel_lse<<<cbNum, fStep, mixNum * sizeof(double)>>>(mixNum, alphaDev, seperateLhDev, combineLhDev);
	cudaError_t err;
	err = cudaDeviceSynchronize();

	if (err != CUDA_SUCCESS) {
		printf("kernel launch failed with error \"%s\".\n",
			cudaGetErrorString(err));
		exit(-1);
	}

	return;
}


	.file	"tmpxft_0034101c_00000000-6_kernels.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2038:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2038:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z46__device_stub__Z20kernel_vecDotProductPdS_iiS_PdS_iiS_
	.type	_Z46__device_stub__Z20kernel_vecDotProductPdS_iiS_PdS_iiS_, @function
_Z46__device_stub__Z20kernel_vecDotProductPdS_iiS_PdS_iiS_:
.LFB2060:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z20kernel_vecDotProductPdS_iiS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2060:
	.size	_Z46__device_stub__Z20kernel_vecDotProductPdS_iiS_PdS_iiS_, .-_Z46__device_stub__Z20kernel_vecDotProductPdS_iiS_PdS_iiS_
	.globl	_Z20kernel_vecDotProductPdS_iiS_
	.type	_Z20kernel_vecDotProductPdS_iiS_, @function
_Z20kernel_vecDotProductPdS_iiS_:
.LFB2061:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z20kernel_vecDotProductPdS_iiS_PdS_iiS_
	.cfi_endproc
.LFE2061:
	.size	_Z20kernel_vecDotProductPdS_iiS_, .-_Z20kernel_vecDotProductPdS_iiS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"kernel vecdot launch failed with error \"%s\".\n"
	.text
	.globl	kernelVecDotWrapper
	.type	kernelVecDotWrapper, @function
kernelVecDotWrapper:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	xorl	%r9d, %r9d
	movq	%r8, %r14
	xorl	%r8d, %r8d
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movl	%ecx, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movl	%edx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movq	%rdi, %rbx
	movl	56(%rsp), %ecx
	movq	48(%rsp), %rdx
	movq	64(%rsp), %rdi
	movl	72(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	movq	%r14, %r8
	movl	%r13d, %ecx
	movl	%r12d, %edx
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	call	_Z46__device_stub__Z20kernel_vecDotProductPdS_iiS_PdS_iiS_
.L9:
	call	cudaPeekAtLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L8
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L8:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	kernelVecDotWrapper, .-kernelVecDotWrapper
	.globl	_Z46__device_stub__Z19kernel_batchedDgemvPdS_iiiS_PdS_iiiS_
	.type	_Z46__device_stub__Z19kernel_batchedDgemvPdS_iiiS_PdS_iiiS_, @function
_Z46__device_stub__Z19kernel_batchedDgemvPdS_iiiS_PdS_iiiS_:
.LFB2062:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 24(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 20(%rsp)
	movq	%r9, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z19kernel_batchedDgemvPdS_iiiS_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L12:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2062:
	.size	_Z46__device_stub__Z19kernel_batchedDgemvPdS_iiiS_PdS_iiiS_, .-_Z46__device_stub__Z19kernel_batchedDgemvPdS_iiiS_PdS_iiiS_
	.globl	_Z19kernel_batchedDgemvPdS_iiiS_
	.type	_Z19kernel_batchedDgemvPdS_iiiS_, @function
_Z19kernel_batchedDgemvPdS_iiiS_:
.LFB2063:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z19kernel_batchedDgemvPdS_iiiS_PdS_iiiS_
	.cfi_endproc
.LFE2063:
	.size	_Z19kernel_batchedDgemvPdS_iiiS_, .-_Z19kernel_batchedDgemvPdS_iiiS_
	.section	.rodata.str1.1
.LC1:
	.string	"kernel dgemv launch failed with error \"%s\".\n"
	.text
	.globl	kernelDgemvWrapper
	.type	kernelDgemvWrapper, @function
kernelDgemvWrapper:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%r9, %r15
	xorl	%r9d, %r9d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%r8d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%ecx, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%edx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rdi, %rbx
	pushq	%r10
	.cfi_def_cfa_offset 64
	movl	72(%rsp), %ecx
	movslq	96(%rsp), %r8
	movq	64(%rsp), %rdx
	movq	80(%rsp), %rdi
	movl	88(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	movq	%r15, %r9
	movl	%r14d, %r8d
	movl	%r13d, %ecx
	movl	%r12d, %edx
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	call	_Z46__device_stub__Z19kernel_batchedDgemvPdS_iiiS_PdS_iiiS_
.L18:
	call	cudaPeekAtLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L17
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L17:
	popq	%rax
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	kernelDgemvWrapper, .-kernelDgemvWrapper
	.globl	_Z35__device_stub__Z10kernel_lseiPdS_S_iPdS_S_
	.type	_Z35__device_stub__Z10kernel_lseiPdS_S_iPdS_S_, @function
_Z35__device_stub__Z10kernel_lseiPdS_S_iPdS_S_:
.LFB2064:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10kernel_lseiPdS_S_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L21:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L23
	call	__stack_chk_fail@PLT
.L23:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2064:
	.size	_Z35__device_stub__Z10kernel_lseiPdS_S_iPdS_S_, .-_Z35__device_stub__Z10kernel_lseiPdS_S_iPdS_S_
	.globl	_Z10kernel_lseiPdS_S_
	.type	_Z10kernel_lseiPdS_S_, @function
_Z10kernel_lseiPdS_S_:
.LFB2065:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z10kernel_lseiPdS_S_iPdS_S_
	.cfi_endproc
.LFE2065:
	.size	_Z10kernel_lseiPdS_S_, .-_Z10kernel_lseiPdS_S_
	.section	.rodata.str1.1
.LC2:
	.string	"kernel launch failed in LSE with error \"%s\".\n"
	.text
	.globl	logSumExpForGMM
	.type	logSumExpForGMM, @function
logSumExpForGMM:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rcx, %r15
	movl	$128, %ecx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r8, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%esi, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	imull	%edi, %r13d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%edi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edx, %ebx
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movq	%r9, 32(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leal	127(%rdx), %eax
	cltd
	idivl	%ecx
	movslq	%r13d, %rdx
	salq	$3, %rdx
	movq	%rdx, %rsi
	movq	%rdx, 16(%rsp)
	movl	%eax, %r12d
	movl	%eax, 12(%rsp)
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdx
	movq	56(%rsp), %rdi
	movq	%r15, %rsi
	movl	$1, %ecx
	sall	$7, %r12d
	call	cudaMemcpy@PLT
	movl	8(%rsp), %r15d
	leaq	64(%rsp), %rdi
	imull	%r12d, %r15d
	imull	%ebp, %r12d
	imull	%ebp, %r15d
	movslq	%r15d, %r15
	salq	$3, %r15
	movq	%r15, %rsi
	call	cudaMalloc@PLT
	movq	64(%rsp), %rdi
	movq	%r15, %rdx
	xorl	%esi, %esi
	call	cudaMemset@PLT
	movl	%r13d, %edx
	movq	64(%rsp), %rdi
	movq	%r14, %rsi
	imull	%ebx, %edx
	movl	$1, %ecx
	sall	$7, %r13d
	xorl	%r14d, %r14d
	movslq	%edx, %rdx
	salq	$3, %rdx
	call	cudaMemcpy@PLT
	movslq	%r12d, %rsi
	leaq	72(%rsp), %rdi
	xorl	%r12d, %r12d
	salq	$3, %rsi
	call	cudaMalloc@PLT
	movslq	8(%rsp), %rax
	movl	%r13d, 28(%rsp)
	xorl	%r13d, %r13d
	salq	$3, %rax
	movq	%rax, 16(%rsp)
	movl	%ebp, %eax
	sall	$7, %eax
	movl	%eax, 24(%rsp)
.L27:
	movq	72(%rsp), %r15
	cmpl	%r12d, 12(%rsp)
	jle	.L33
	movq	64(%rsp), %r11
	movl	%ebp, 80(%rsp)
	movl	$33554433, %edx
	xorl	%r9d, %r9d
	movq	16(%rsp), %r8
	salq	$7, %rdx
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	movq	%rax, 84(%rsp)
	movq	80(%rsp), %rdi
	movl	88(%rsp), %esi
	movq	%r11, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	movq	40(%rsp), %r11
	testl	%eax, %eax
	jne	.L28
	movslq	%r13d, %rax
	movq	56(%rsp), %rsi
	movl	8(%rsp), %edi
	leaq	(%r15,%rax,8), %rcx
	movslq	%r14d, %rax
	leaq	(%r11,%rax,8), %rdx
	call	_Z35__device_stub__Z10kernel_lseiPdS_S_iPdS_S_
.L28:
	call	cudaDeviceSynchronize@PLT
	movl	%eax, %edi
	movl	24(%rsp), %eax
	addl	%eax, %r13d
	movl	28(%rsp), %eax
	addl	%eax, %r14d
	testl	%edi, %edi
	je	.L29
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L29:
	incl	%r12d
	jmp	.L27
.L33:
	imull	%ebp, %ebx
	movq	32(%rsp), %rdi
	movl	$2, %ecx
	movq	%r15, %rsi
	movslq	%ebx, %rdx
	salq	$3, %rdx
	call	cudaMemcpy@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	logSumExpForGMM, .-logSumExpForGMM
	.section	.rodata.str1.1
.LC3:
	.string	"kernel launch failed with error \"%s\".\n"
	.text
	.globl	kernelLSEWrapper
	.type	kernelLSEWrapper, @function
kernelLSEWrapper:
.LFB2035:
	.cfi_startproc
	endbr64
	movabsq	$4294967297, %rax
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movq	%r9, %r13
	xorl	%r9d, %r9d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%r8, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%rcx, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	%edx, %ebx
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	movq	%rax, 24(%rsp)
	movl	28(%rsp), %ecx
	movq	%rax, 12(%rsp)
	movslq	%edx, %rax
	movl	%esi, 20(%rsp)
	movl	16(%rsp), %esi
	leaq	0(,%rax,8), %r8
	movl	%edi, 8(%rsp)
	movq	20(%rsp), %rdx
	movq	8(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	movq	%r13, %rcx
	movq	%r12, %rdx
	movq	%rbp, %rsi
	movl	%ebx, %edi
	call	_Z35__device_stub__Z10kernel_lseiPdS_S_iPdS_S_
.L35:
	call	cudaDeviceSynchronize@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L34
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L34:
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	kernelLSEWrapper, .-kernelLSEWrapper
	.globl	_Z44__device_stub__Z16kernel_mvn_shareiiiPdS_iS_iiiPdS_iS_
	.type	_Z44__device_stub__Z16kernel_mvn_shareiiiPdS_iS_iiiPdS_iS_, @function
_Z44__device_stub__Z16kernel_mvn_shareiiiPdS_iS_iiiPdS_iS_:
.LFB2066:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movl	%edi, 44(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 36(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movl	%r9d, 32(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z16kernel_mvn_shareiiiPdS_iS_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L38:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L40
	call	__stack_chk_fail@PLT
.L40:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2066:
	.size	_Z44__device_stub__Z16kernel_mvn_shareiiiPdS_iS_iiiPdS_iS_, .-_Z44__device_stub__Z16kernel_mvn_shareiiiPdS_iS_iiiPdS_iS_
	.globl	_Z16kernel_mvn_shareiiiPdS_iS_
	.type	_Z16kernel_mvn_shareiiiPdS_iS_, @function
_Z16kernel_mvn_shareiiiPdS_iS_:
.LFB2067:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z16kernel_mvn_shareiiiPdS_iS_iiiPdS_iS_
	.cfi_endproc
.LFE2067:
	.size	_Z16kernel_mvn_shareiiiPdS_iS_, .-_Z16kernel_mvn_shareiiiPdS_iS_
	.globl	kernelSharedMvnWrapper
	.type	kernelSharedMvnWrapper, @function
kernelSharedMvnWrapper:
.LFB2032:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%r9d, %r15d
	xorl	%r9d, %r9d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r8, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rcx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%esi, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	movl	96(%rsp), %ecx
	movslq	120(%rsp), %r8
	movl	%edi, 12(%rsp)
	movq	88(%rsp), %rdx
	movq	104(%rsp), %rdi
	movl	112(%rsp), %esi
	movq	80(%rsp), %rbx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L44
	movl	12(%rsp), %eax
	movq	%r13, %rcx
	movl	%r15d, %r9d
	movq	%r14, %r8
	movl	%r12d, %esi
	cltd
	idivl	%ebp
	movl	%ebp, %edx
	movl	%eax, %edi
	pushq	%rax
	.cfi_def_cfa_offset 88
	pushq	%rbx
	.cfi_def_cfa_offset 96
	call	_Z44__device_stub__Z16kernel_mvn_shareiiiPdS_iS_iiiPdS_iS_
	popq	%rdx
	.cfi_def_cfa_offset 88
	popq	%rcx
	.cfi_def_cfa_offset 80
.L44:
	call	cudaPeekAtLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L45
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L45:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	cudaDeviceSynchronize@PLT
	.cfi_endproc
.LFE2032:
	.size	kernelSharedMvnWrapper, .-kernelSharedMvnWrapper
	.globl	_Z44__device_stub__Z20kernel_share_add_cstiiPdS_iiPdS_
	.type	_Z44__device_stub__Z20kernel_share_add_cstiiPdS_iiPdS_, @function
_Z44__device_stub__Z20kernel_share_add_cstiiPdS_iiPdS_:
.LFB2068:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 24(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L47
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z20kernel_share_add_cstiiPdS_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L47:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L49
	call	__stack_chk_fail@PLT
.L49:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2068:
	.size	_Z44__device_stub__Z20kernel_share_add_cstiiPdS_iiPdS_, .-_Z44__device_stub__Z20kernel_share_add_cstiiPdS_iiPdS_
	.globl	_Z20kernel_share_add_cstiiPdS_
	.type	_Z20kernel_share_add_cstiiPdS_, @function
_Z20kernel_share_add_cstiiPdS_:
.LFB2069:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z20kernel_share_add_cstiiPdS_iiPdS_
	.cfi_endproc
.LFE2069:
	.size	_Z20kernel_share_add_cstiiPdS_, .-_Z20kernel_share_add_cstiiPdS_
	.section	.rodata.str1.1
.LC4:
	.string	"kernel share_add_cst launch failed with error \"%s\".\n"
	.text
	.globl	kernelShareAddCstWrapper
	.type	kernelShareAddCstWrapper, @function
kernelShareAddCstWrapper:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movq	%rcx, %r13
	movl	%r9d, %ecx
	xorl	%r9d, %r9d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdx, %r12
	movq	%r8, %rdx
	xorl	%r8d, %r8d
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	%edi, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	movq	64(%rsp), %rdi
	movl	72(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L53
	movq	%r13, %rcx
	movq	%r12, %rdx
	movl	%ebp, %esi
	movl	%ebx, %edi
	call	_Z44__device_stub__Z20kernel_share_add_cstiiPdS_iiPdS_
.L53:
	call	cudaPeekAtLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L52
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	leaq	.LC4(%rip), %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L52:
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	kernelShareAddCstWrapper, .-kernelShareAddCstWrapper
	.globl	_Z41__device_stub__Z14kernel_vecdot2iiiPdS_S_iiiPdS_S_
	.type	_Z41__device_stub__Z14kernel_vecdot2iiiPdS_S_iiiPdS_S_, @function
_Z41__device_stub__Z14kernel_vecdot2iiiPdS_S_iiiPdS_S_:
.LFB2070:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 36(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L56
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z14kernel_vecdot2iiiPdS_S_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L56:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L58
	call	__stack_chk_fail@PLT
.L58:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2070:
	.size	_Z41__device_stub__Z14kernel_vecdot2iiiPdS_S_iiiPdS_S_, .-_Z41__device_stub__Z14kernel_vecdot2iiiPdS_S_iiiPdS_S_
	.globl	_Z14kernel_vecdot2iiiPdS_S_
	.type	_Z14kernel_vecdot2iiiPdS_S_, @function
_Z14kernel_vecdot2iiiPdS_S_:
.LFB2071:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z14kernel_vecdot2iiiPdS_S_iiiPdS_S_
	.cfi_endproc
.LFE2071:
	.size	_Z14kernel_vecdot2iiiPdS_S_, .-_Z14kernel_vecdot2iiiPdS_S_
	.section	.rodata.str1.1
.LC5:
	.string	"kernel vecdot2 launch failed with error \"%s\".\n"
	.text
	.globl	kernelVecDot2Wrapper
	.type	kernelVecDot2Wrapper, @function
kernelVecDot2Wrapper:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%r9, %r15
	xorl	%r9d, %r9d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%edx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%r8d, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%ecx, %ebx
	pushq	%r10
	.cfi_def_cfa_offset 64
	movl	72(%rsp), %ecx
	movslq	96(%rsp), %r8
	movq	64(%rsp), %rdx
	movq	80(%rsp), %rdi
	movl	88(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L62
	movq	%r15, %r9
	movq	%r14, %r8
	movq	%r13, %rcx
	movl	%r12d, %edx
	movl	%ebp, %esi
	movl	%ebx, %edi
	call	_Z41__device_stub__Z14kernel_vecdot2iiiPdS_S_iiiPdS_S_
.L62:
	call	cudaPeekAtLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L61
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	leaq	.LC5(%rip), %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L61:
	popq	%rax
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2031:
	.size	kernelVecDot2Wrapper, .-kernelVecDot2Wrapper
	.globl	_Z41__device_stub__Z10kernel_mvniiPdS_S_S_iS_iiPdS_S_S_iS_
	.type	_Z41__device_stub__Z10kernel_mvniiPdS_S_S_iS_iiPdS_S_S_iS_, @function
_Z41__device_stub__Z10kernel_mvniiPdS_S_S_iS_iiPdS_S_S_iS_:
.LFB2072:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	216(%rsp), %rax
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 32(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	%rsp, %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L65
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z10kernel_mvniiPdS_S_S_iS_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L65:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L67
	call	__stack_chk_fail@PLT
.L67:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2072:
	.size	_Z41__device_stub__Z10kernel_mvniiPdS_S_S_iS_iiPdS_S_S_iS_, .-_Z41__device_stub__Z10kernel_mvniiPdS_S_S_iS_iiPdS_S_S_iS_
	.globl	_Z10kernel_mvniiPdS_S_S_iS_
	.type	_Z10kernel_mvniiPdS_S_S_iS_, @function
_Z10kernel_mvniiPdS_S_S_iS_:
.LFB2073:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z10kernel_mvniiPdS_S_S_iS_iiPdS_S_S_iS_
	.cfi_endproc
.LFE2073:
	.size	_Z10kernel_mvniiPdS_S_S_iS_, .-_Z10kernel_mvniiPdS_S_S_iS_
	.globl	kernelMvnWrapper
	.type	kernelMvnWrapper, @function
kernelMvnWrapper:
.LFB2033:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%r9, %r15
	xorl	%r9d, %r9d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r8, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rcx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	movl	104(%rsp), %ecx
	movl	%edi, 8(%rsp)
	movslq	128(%rsp), %r8
	movq	96(%rsp), %rdx
	movl	%esi, 12(%rsp)
	movq	112(%rsp), %rdi
	movl	120(%rsp), %esi
	movl	80(%rsp), %ebx
	movq	88(%rsp), %rbp
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L71
	pushq	%rbp
	.cfi_def_cfa_offset 88
	movq	%r12, %rdx
	movq	%r15, %r9
	movq	%r14, %r8
	pushq	%rbx
	.cfi_def_cfa_offset 96
	movl	28(%rsp), %esi
	movq	%r13, %rcx
	movl	24(%rsp), %edi
	call	_Z41__device_stub__Z10kernel_mvniiPdS_S_S_iS_iiPdS_S_S_iS_
	popq	%rax
	.cfi_def_cfa_offset 88
	popq	%rdx
	.cfi_def_cfa_offset 80
.L71:
	call	cudaPeekAtLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L72
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L72:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	cudaDeviceSynchronize@PLT
	.cfi_endproc
.LFE2033:
	.size	kernelMvnWrapper, .-kernelMvnWrapper
	.globl	_Z46__device_stub__Z15kernel_diag_mvniiPdS_S_S_iS_iiPdS_S_S_iS_
	.type	_Z46__device_stub__Z15kernel_diag_mvniiPdS_S_S_iS_iiPdS_S_S_iS_, @function
_Z46__device_stub__Z15kernel_diag_mvniiPdS_S_S_iS_iiPdS_S_S_iS_:
.LFB2074:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	216(%rsp), %rax
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 32(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	%rsp, %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L74
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z15kernel_diag_mvniiPdS_S_S_iS_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L74:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L76
	call	__stack_chk_fail@PLT
.L76:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2074:
	.size	_Z46__device_stub__Z15kernel_diag_mvniiPdS_S_S_iS_iiPdS_S_S_iS_, .-_Z46__device_stub__Z15kernel_diag_mvniiPdS_S_S_iS_iiPdS_S_S_iS_
	.globl	_Z15kernel_diag_mvniiPdS_S_S_iS_
	.type	_Z15kernel_diag_mvniiPdS_S_S_iS_, @function
_Z15kernel_diag_mvniiPdS_S_S_iS_:
.LFB2075:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z15kernel_diag_mvniiPdS_S_S_iS_iiPdS_S_S_iS_
	.cfi_endproc
.LFE2075:
	.size	_Z15kernel_diag_mvniiPdS_S_S_iS_, .-_Z15kernel_diag_mvniiPdS_S_S_iS_
	.globl	kernelDiagMvnWrapper
	.type	kernelDiagMvnWrapper, @function
kernelDiagMvnWrapper:
.LFB2034:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%r9, %r15
	xorl	%r9d, %r9d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r8, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rcx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edi, %ebx
	pushq	%r10
	.cfi_def_cfa_offset 64
	movl	88(%rsp), %ecx
	movslq	112(%rsp), %r8
	movq	80(%rsp), %rdx
	movq	96(%rsp), %rdi
	movl	104(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L80
	pushq	72(%rsp)
	.cfi_def_cfa_offset 72
	movl	72(%rsp), %eax
	movq	%r13, %rcx
	movq	%r12, %rdx
	movq	%r15, %r9
	movq	%r14, %r8
	movl	%ebp, %esi
	movl	%ebx, %edi
	pushq	%rax
	.cfi_def_cfa_offset 80
	call	_Z46__device_stub__Z15kernel_diag_mvniiPdS_S_S_iS_iiPdS_S_S_iS_
	popq	%rdx
	.cfi_def_cfa_offset 72
	popq	%rcx
	.cfi_def_cfa_offset 64
.L80:
	call	cudaDeviceSynchronize@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L79
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L79:
	popq	%rax
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	kernelDiagMvnWrapper, .-kernelDiagMvnWrapper
	.section	.rodata.str1.1
.LC6:
	.string	"_Z15kernel_diag_mvniiPdS_S_S_iS_"
.LC7:
	.string	"_Z10kernel_mvniiPdS_S_S_iS_"
.LC8:
	.string	"_Z14kernel_vecdot2iiiPdS_S_"
.LC9:
	.string	"_Z20kernel_share_add_cstiiPdS_"
.LC10:
	.string	"_Z16kernel_mvn_shareiiiPdS_iS_"
.LC11:
	.string	"_Z10kernel_lseiPdS_S_"
.LC12:
	.string	"_Z19kernel_batchedDgemvPdS_iiiS_"
.LC13:
	.string	"_Z20kernel_vecDotProductPdS_iiS_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2077:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z15kernel_diag_mvniiPdS_S_S_iS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z10kernel_mvniiPdS_S_S_iS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z14kernel_vecdot2iiiPdS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z20kernel_share_add_cstiiPdS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z16kernel_mvn_shareiiiPdS_iS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z10kernel_lseiPdS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z19kernel_batchedDgemvPdS_iiiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z20kernel_vecDotProductPdS_iiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2077:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*#include <cuda_runtime.h>*/
#include <hip/hip_runtime.h>
#include <stdio.h>

__global__ void kernel_vecDotProduct(double* invSigmaMuDev, double* muDev, int fDim, int cbNum, double* resDev) {
	int cbIdx = blockDim.x * blockIdx.x + threadIdx.x;
	if (cbIdx < cbNum) {
		double t = 0;
		double* v1 = invSigmaMuDev + cbIdx * fDim;
		double* v2 = muDev + cbIdx * fDim;
		for (int i = 0; i < fDim; i++) {
			t += v1[i] * v2[i];
		}
		resDev[cbIdx] += t / 2;
	}
}

__global__ void kernel_batchedDgemv(double* invSigmaDev, double* muDev, int fDim, int cbNum, int shareNum, double* resDev) {
	extern __shared__ double sharedMu[];

	int N = blockDim.x;
	int vecLen = N * fDim;
	int maxIdx = cbNum * fDim;
	for (int i = 0; i < (vecLen + blockDim.x - 1) / blockDim.x; i++) {
		int sharedIdx = i * blockDim.x + threadIdx.x;
		int devIdx = blockIdx.x * vecLen + sharedIdx;
		
		if (devIdx < maxIdx)
			sharedMu[sharedIdx] = muDev[devIdx];
	}
	__syncthreads();

	int invSigmaLen = (fDim + 1) * fDim / 2;
	int cbIdx = N * blockIdx.x + threadIdx.x;
	if (cbIdx < cbNum) {
		double* r = resDev + cbIdx * fDim;
		double* v = sharedMu + threadIdx.x * fDim;
		double* A = invSigmaDev + (cbIdx / shareNum) * invSigmaLen;
		for (int i = 0; i < fDim; i++) {
			double t = 0;
			for (int j = 0; j < i; j++)
				t += A[i * (i + 1) / 2 + j] * v[j];

			for (int j = i + 1; j < fDim; j++) 
				t += A[j * (j + 1) / 2 + i] * v[j];

			t += A[i * (i + 1) / 2 + i] * 2 * v[i];

			r[i] = t;
		}
	}
}


__global__ void kernel_lse(int mixNum, double* allAlpha, double* seperateLh, double* combinedLh) {
	extern __shared__ double alpha[];

	for (int i = 0; i < (mixNum + blockDim.x - 1) / blockDim.x; i++) {
		if (i * blockDim.x + threadIdx.x < mixNum) {
			alpha[i * blockDim.x + threadIdx.x] = allAlpha[blockIdx.x * mixNum + blockDim.x * i + threadIdx.x];
		}
	}

	__syncthreads();


	double maxLh = 0;
 	int maxLhIdx = -1;
	for (int i = 0; i < mixNum; i++) {
		if (alpha[i] > 0) {
			int p = gridDim.x * mixNum * threadIdx.x + blockIdx.x * mixNum + i;
			double t = log(alpha[i]) + seperateLh[p];
			//printf("seperateLh[%d] = %f\n", p, seperateLh[p]);
			if (maxLhIdx == -1 || t > maxLh) {
				maxLh = t;
				maxLhIdx = i;
			}
			seperateLh[p] = t;
		}
	}



	for (int i = 0; i < mixNum; i++) {
		if (alpha[i] > 0) {
			int p = gridDim.x * mixNum * threadIdx.x + blockIdx.x * mixNum + i;
			seperateLh[p] -= maxLh;
		}
	}


	for (int i = 0; i < mixNum; i++) {
		if (alpha[i] > 0) {
			int p = gridDim.x * mixNum * threadIdx.x + blockIdx.x * mixNum + i;
			seperateLh[p] = exp(seperateLh[p]);	//ʱseperateLh[p]һС1
		}
	}
	
	double sumExp = 0;
	for (int i = 0; i < mixNum; i++) {
		if (alpha[i] > 0) {
			int p = gridDim.x * mixNum * threadIdx.x + blockIdx.x * mixNum + i;
			sumExp += seperateLh[p];
		}
	}

	double logSumExp = maxLh + log(sumExp);
	combinedLh[gridDim.x * threadIdx.x + blockIdx.x] = logSumExp;


}

extern "C" void logSumExpForGMM(int cbNum, int mixNum, int fNum, double* allAlpha, double* seperateLh, double* combinedLh) {
	int fStep = 128;
	int fExtendNum = ((fNum + fStep - 1) / fStep) * fStep;

	hipError_t err;

	double* allAlphaDev;
	err = hipMalloc((void**)&allAlphaDev, cbNum * mixNum * sizeof(double));
	err = hipMemcpy(allAlphaDev, allAlpha, cbNum * mixNum * sizeof(double), hipMemcpyHostToDevice);

	double* seperateLhDev;
	err = hipMalloc((void**)&seperateLhDev, fExtendNum * mixNum * cbNum * sizeof(double));
	err = hipMemset(seperateLhDev, 0, fExtendNum * mixNum * cbNum * sizeof(double));
	hipMemcpy(seperateLhDev, seperateLh, cbNum * mixNum * fNum * sizeof(double), hipMemcpyHostToDevice);

	double* combinedLhDev;
	err = hipMalloc((void**)&combinedLhDev, fExtendNum * cbNum * sizeof(double));

	//int lastCpyFrameNum = fNum - (fExtendNum - fStep);
	for (int i = 0; i < fExtendNum / fStep; i++) {
		double* lhInDev = seperateLhDev + fStep * mixNum * cbNum * i;
		double* lhOutDev = combinedLhDev + fStep * cbNum * i;
		kernel_lse<<<cbNum, fStep, mixNum * sizeof(double)>>>(mixNum, allAlphaDev, lhInDev, lhOutDev);
		err = hipDeviceSynchronize();
		if (err != hipSuccess) {
			printf("kernel launch failed in LSE with error \"%s\".\n",
			hipGetErrorString(err));
			exit(-1);
		}
	}

	err = hipMemcpy(combinedLh, combinedLhDev, fNum * cbNum * sizeof(double), hipMemcpyDeviceToHost);

//	free(allLogAlpha);
	hipFree(combinedLhDev);
	hipFree(seperateLhDev);
	hipFree(allAlphaDev);
}


__global__ void kernel_mvn_share(int sigmaNum, int fDim, int shareNum, double* invSigma, double* feature, int fNum, double* resBuf)
{	

	extern __shared__ double memory[];

	double* sharedInvSigma = memory;
	int invSigmaLen = fDim * (fDim + 1) / 2;
	int fLen = fNum * fDim;

	double* sharedFt = sharedInvSigma + blockDim.y * invSigmaLen;
	//memset(sharedFt, 0, fDim * fNum * sizeof(double));

	double res = 0;
	int sigmaIdx = blockDim.y * blockIdx.x + threadIdx.y;
	int thIdx = threadIdx.x + threadIdx.y * blockDim.x;
	int thNum = blockDim.x * blockDim.y;

	if (sigmaIdx < sigmaNum)
	{
		for (int i = 0; i < (invSigmaLen + blockDim.x - 1) / blockDim.x; i++)
			if (i * blockDim.x + threadIdx.x < invSigmaLen)
				sharedInvSigma[threadIdx.y * invSigmaLen + i * blockDim.x + threadIdx.x] = invSigma[sigmaIdx * invSigmaLen + i * blockDim.x + threadIdx.x];
	}

	for (int i = 0; i < (fLen + thNum - 1) / thNum; i++)
		if (i * thNum + thIdx < fLen)
			sharedFt[i * thNum + thIdx] = feature[i * thNum + thIdx];

	__syncthreads();

	if (sigmaIdx < sigmaNum) {
		res = 0;
		int idx = 0;
		for (int j = 0; j < fDim; j++) {
			double t1 = sharedFt[threadIdx.x * fDim + j];
			double rest = 0;
			for (int k = 0; k < j; k++) {
				double t2 = sharedFt[threadIdx.x * fDim + k];
				rest += sharedInvSigma[threadIdx.y * invSigmaLen + idx++] * t2;
			}
			rest += sharedInvSigma[threadIdx.y * invSigmaLen + idx++] * t1;
			res += rest * t1;
		}

		int resIdxStart = (sigmaIdx + threadIdx.x * sigmaNum) * shareNum;
		for (int i = 0; i < shareNum; i++) {
			resBuf[resIdxStart + i] -= res;
		}
		//resBuf[resIdx] = -res;
	}
	__syncthreads();
}

__global__ void kernel_share_add_cst(int cbNum, int fNum, double* cst, double* res) {
	double* fVec = res + blockIdx.x * cbNum;
	for (int i = 0; i < (cbNum + blockDim.x - 1) / blockDim.x; i++)
		if (i * blockDim.x + threadIdx.x < cbNum)
			fVec[i * blockDim.x + threadIdx.x] -= cst[i * blockDim.x + threadIdx.x];
}

__global__ void kernel_vecdot2(int cbNum, int fNum, int fDim, double* invSigmaMu, double* fVec, double* resBuf) {
	extern __shared__ double memory[];
	double* sharedFeature = memory;
	double* sharedInvSigmaMu = sharedFeature + fNum * fDim;

	int cbIdx = blockDim.y * blockIdx.x + threadIdx.y;
	int thNum = blockDim.x * blockDim.y;
	int thIdx = threadIdx.y * blockDim.x + threadIdx.x;

	for (int i = 0; i < (fDim * fNum + thNum - 1) / thNum; i++)
		if (i * thNum + thIdx < fDim * fNum)
			sharedFeature[i * thNum + thIdx] = fVec[i * thNum + thIdx];

	if (cbIdx < cbNum) {
		for (int i = 0; i < (fDim + blockDim.x - 1) / blockDim.x; i++)
			if (i * blockDim.x + threadIdx.x < fDim)
				sharedInvSigmaMu[threadIdx.y * fDim + i * blockDim.x + threadIdx.x] = invSigmaMu[cbIdx * fDim + i * blockDim.x + threadIdx.x];
	}


	__syncthreads();

	if (cbIdx < cbNum) {
		int resIdx = threadIdx.x * cbNum + cbIdx;
		double* v1 = sharedFeature + threadIdx.x * fDim;
		double* v2 = sharedInvSigmaMu + threadIdx.y * fDim;
		double res = 0;
		for (int i = 0; i < fDim; i++) {
			res += v1[i] * v2[i];
		}
		resBuf[resIdx] += res;
	}
}

__global__ void kernel_mvn(int cbNum, int fDim, double* invSigma, double* invSigmaMu, double* cst, double* feature, int fNum, double* resBuf)
{	

	extern __shared__ double memory[];

	double* sharedInvSigma = memory;
	int invSigmaLen = fDim * (fDim + 1) / 2;
	int fLen = fNum * fDim;

	double* sharedInvSigmaMu = sharedInvSigma + blockDim.y * invSigmaLen;
	double* sharedCst = sharedInvSigmaMu + blockDim.y * fDim;
	double* sharedFt = sharedCst + blockDim.y;
	//memset(sharedFt, 0, fDim * fNum * sizeof(double));

	double res = 0;
	int cbIdx = blockDim.y * blockIdx.x + threadIdx.y;
	int thIdx = threadIdx.x + threadIdx.y * blockDim.x;
	int thNum = blockDim.x * blockDim.y;

	if (cbIdx < cbNum)
	{
		for (int i = 0; i < (invSigmaLen + blockDim.x - 1) / blockDim.x; i++)
			if (i * blockDim.x + threadIdx.x < invSigmaLen)
				sharedInvSigma[threadIdx.y * invSigmaLen + i * blockDim.x + threadIdx.x] = invSigma[cbIdx * invSigmaLen + i * blockDim.x + threadIdx.x];

		for (int i = 0; i < (fDim + blockDim.x - 1) / blockDim.x; i++)
			if (i * blockDim.x + threadIdx.x < fDim)
				sharedInvSigmaMu[threadIdx.y * fDim + i * blockDim.x + threadIdx.x] = invSigmaMu[cbIdx * fDim + i * blockDim.x + threadIdx.x];
		
		if (threadIdx.x == 0)
			sharedCst[threadIdx.y] = cst[cbIdx];
	}

	for (int i = 0; i < (fLen + thNum - 1) / thNum; i++)
		if (i * thNum + thIdx < fLen)
			sharedFt[i * thNum + thIdx] = feature[i * thNum + thIdx];

	__syncthreads();

	if (cbIdx < cbNum) {
		res = sharedCst[threadIdx.y];
		int idx = 0;
		for (int j = 0; j < fDim; j++) {
			double t1 = sharedFt[threadIdx.x * fDim + j];
			double rest = 0;
			for (int k = 0; k <= j; k++) {
				double t2 = sharedFt[threadIdx.x * fDim + k];
				rest += sharedInvSigma[threadIdx.y * invSigmaLen + idx++] * t2;
			}
			//rest += sharedInvSigma[threadIdx.y * invSigmaLen + idx++] * t1;
			rest -= sharedInvSigmaMu[threadIdx.y * fDim + j];
			res += rest * t1;
		}

		int resIdx = cbIdx + threadIdx.x * cbNum;
		resBuf[resIdx] = -res;
	}
	__syncthreads();
}
//kernel_share_add_cst(int cbNum, int fNum, double* cst, double* res)
extern "C" void kernelShareAddCstWrapper(int cbNum, int fNum, double* cstDev, double* resDev ,dim3 threads, dim3 blocks) {
	kernel_share_add_cst<<< blocks, threads>>>(cbNum, fNum, cstDev, resDev);
	hipError_t err;
	err = hipPeekAtLastError();

	if (err != hipSuccess) {
		printf("kernel share_add_cst launch failed with error \"%s\".\n",
			hipGetErrorString(err));
		exit(-1);
	}

	return;
}

extern "C" void kernelVecDotWrapper(double* invSigmaMuDev, double* muDev, int fDim, int cbNum, double* resDev , dim3 threads, dim3 blocks) {
	kernel_vecDotProduct<<< blocks, threads>>>(invSigmaMuDev, muDev, fDim, cbNum, resDev);
	hipError_t err;
	err = hipPeekAtLastError();

	if (err != hipSuccess) {
		printf("kernel vecdot launch failed with error \"%s\".\n",
			hipGetErrorString(err));
		exit(-1);
	}

	return;
}

extern "C" void kernelDgemvWrapper(double* invSigmaDev, double* muDev, int fDim, int cbNum, int shareNum, double* resDev , dim3 threads, dim3 blocks, int memSize) {

	kernel_batchedDgemv<<< blocks, threads, memSize>>>(invSigmaDev, muDev, fDim, cbNum, shareNum, resDev);
	
	hipError_t err = hipPeekAtLastError();

	if (err != hipSuccess) {
		printf("kernel dgemv launch failed with error \"%s\".\n",
			hipGetErrorString(err));
		exit(-1);
	}

	return;
}

extern "C" void kernelVecDot2Wrapper(double* invSigmaMuDev, double* featureDev, int fDim, int cbNum, int fNum, double* resDev , dim3 threads, dim3 blocks, int memSize) {
	//kernel_vecdot2(int cbNum, int fNum, int fDim, double* invSigmaMu, double* fVec, double* resBuf)
	kernel_vecdot2<<< blocks, threads, memSize>>>(cbNum, fNum, fDim, invSigmaMuDev, featureDev, resDev);
	hipError_t err;
	err = hipPeekAtLastError();

	if (err != hipSuccess) {
		printf("kernel vecdot2 launch failed with error \"%s\".\n",
			hipGetErrorString(err));
		exit(-1);
	}

	return;
}

extern "C" void kernelSharedMvnWrapper(int cbNum, int fDim, int mixNum, double* invSigmaDev, double* featureDev, int fNum, double* resBufDev, dim3 threads, dim3 blocks, int memSize) {
	
	kernel_mvn_share<<< blocks, threads, memSize >>>(cbNum / mixNum, fDim, mixNum, invSigmaDev, featureDev, fNum, resBufDev);
	hipError_t err;
	err = hipPeekAtLastError();
 	
	if (err != hipSuccess) {
		printf("kernel launch failed with error \"%s\".\n",
		hipGetErrorString(err));
		exit(-1);
	}
	hipDeviceSynchronize();
	return;
}

extern "C" void kernelMvnWrapper(int cbNum, int fDim, double* invSigmaDev, double* invSigmaMuDev, double* cstDev, double* featureDev, int fNum, double* resBufDev, dim3 threads, dim3 blocks, int memSize) {
	//kernel_mvn(int cbNum, int fDim, double* invSigma, double* invSigmaMu, double* cst, double* feature, int fNum, double* resBuf)
	kernel_mvn<<< blocks, threads, memSize >>>(cbNum, fDim, invSigmaDev, invSigmaMuDev, cstDev, featureDev, fNum, resBufDev);
	hipError_t err;
	err = hipPeekAtLastError();

	if (err != hipSuccess) {
		printf("kernel launch failed with error \"%s\".\n",
			hipGetErrorString(err));
		exit(-1);
	}
	hipDeviceSynchronize();
	return;
}


__global__ void kernel_diag_mvn(int cbNum, int fDim, double* invSigma, double* mu, double* cst, double* feature, int fNum, double* resBuf)
{	

	extern __shared__ double memory[];

	double* sharedInvSigma = memory;
	int fLen = fNum * fDim;

	double* sharedMu = sharedInvSigma + blockDim.y * fDim;
	double* sharedCst = sharedMu + blockDim.y * fDim;
	double* sharedFt = sharedCst + blockDim.y;

	int cbIdx = blockDim.y * blockIdx.x + threadIdx.y;
	int thIdx = threadIdx.x + threadIdx.y * blockDim.x;
	int thNum = blockDim.x * blockDim.y;

	if (cbIdx < cbNum)
	{
		for (int i = 0; i < (fDim + blockDim.x - 1) / blockDim.x; i++)
			if (i * blockDim.x + threadIdx.x < fDim)
				sharedInvSigma[threadIdx.y * fDim + i * blockDim.x + threadIdx.x] = invSigma[cbIdx * fDim + i * blockDim.x + threadIdx.x];

		for (int i = 0; i < (fDim + blockDim.x - 1) / blockDim.x; i++)
			if (i * blockDim.x + threadIdx.x < fDim)
				sharedMu[threadIdx.y * fDim + i * blockDim.x + threadIdx.x] = mu[cbIdx * fDim + i * blockDim.x + threadIdx.x];

		if (threadIdx.x == 0)
			sharedCst[threadIdx.y] = cst[cbIdx];
	}

	for (int i = 0; i < (fLen + thNum - 1) / thNum; i++)
		if (i * thNum + thIdx < fLen)
			sharedFt[i * thNum + thIdx] = feature[i * thNum + thIdx];

	__syncthreads();

	if (cbIdx < cbNum) {
		double res = 0;
		for (int j = 0; j < fDim; j++) {
			double xj = sharedFt[threadIdx.x * fDim + j] - sharedMu[threadIdx.y * fDim + j];
			res += xj * xj * sharedInvSigma[threadIdx.y * fDim + j];
		}
		res = -(sharedCst[threadIdx.y] + res / 2);

		int resIdx = cbIdx + threadIdx.x * cbNum;
		resBuf[resIdx] = res;
	}
	__syncthreads();
}

extern "C" void kernelDiagMvnWrapper(int cbNum, int fDim, double* invSigmaDev, double* muDev, double* cstDev, double* featureDev, int fNum, double* resBufDev, dim3 threads, dim3 blocks, int memSize) {

	
	kernel_diag_mvn<<< blocks, threads, memSize >>>(cbNum, fDim, invSigmaDev, muDev, cstDev, featureDev, fNum, resBufDev);
	hipError_t err;
	err = hipDeviceSynchronize();
	
	if (err != hipSuccess) {
		printf("kernel launch failed with error \"%s\".\n",
			hipGetErrorString(err));
		exit(-1);
	}
	
	return;
}
//__global__ void kernel_lse(int mixNum, double* allAlpha, double* seperateLh, double* combinedLh)
extern "C" void kernelLSEWrapper(int cbNum, int fStep, int mixNum, double* alphaDev, double* seperateLhDev, double* combineLhDev) {
	kernel_lse<<<cbNum, fStep, mixNum * sizeof(double)>>>(mixNum, alphaDev, seperateLhDev, combineLhDev);
	hipError_t err;
	err = hipDeviceSynchronize();

	if (err != hipSuccess) {
		printf("kernel launch failed with error \"%s\".\n",
			hipGetErrorString(err));
		exit(-1);
	}

	return;
}


	.text
	.file	"kernels.hip"
	.globl	_Z35__device_stub__kernel_vecDotProductPdS_iiS_ # -- Begin function _Z35__device_stub__kernel_vecDotProductPdS_iiS_
	.type	_Z35__device_stub__kernel_vecDotProductPdS_iiS_,@function
_Z35__device_stub__kernel_vecDotProductPdS_iiS_: # @_Z35__device_stub__kernel_vecDotProductPdS_iiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	movq	%rsp, %rdx
	movl	%ecx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20kernel_vecDotProductPdS_iiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z35__device_stub__kernel_vecDotProductPdS_iiS_, .Lfunc_end0-_Z35__device_stub__kernel_vecDotProductPdS_iiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__kernel_batchedDgemvPdS_iiiS_ # -- Begin function _Z34__device_stub__kernel_batchedDgemvPdS_iiiS_
	.type	_Z34__device_stub__kernel_batchedDgemvPdS_iiiS_,@function
_Z34__device_stub__kernel_batchedDgemvPdS_iiiS_: # @_Z34__device_stub__kernel_batchedDgemvPdS_iiiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19kernel_batchedDgemvPdS_iiiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z34__device_stub__kernel_batchedDgemvPdS_iiiS_, .Lfunc_end1-_Z34__device_stub__kernel_batchedDgemvPdS_iiiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__kernel_lseiPdS_S_ # -- Begin function _Z25__device_stub__kernel_lseiPdS_S_
	.type	_Z25__device_stub__kernel_lseiPdS_S_,@function
_Z25__device_stub__kernel_lseiPdS_S_:   # @_Z25__device_stub__kernel_lseiPdS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10kernel_lseiPdS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z25__device_stub__kernel_lseiPdS_S_, .Lfunc_end2-_Z25__device_stub__kernel_lseiPdS_S_
	.cfi_endproc
                                        # -- End function
	.globl	logSumExpForGMM                 # -- Begin function logSumExpForGMM
	.type	logSumExpForGMM,@function
logSumExpForGMM:                        # @logSumExpForGMM
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 64(%rsp)                   # 8-byte Spill
	movq	%r8, 24(%rsp)                   # 8-byte Spill
	movq	%rcx, 16(%rsp)                  # 8-byte Spill
	movl	%edx, %r13d
	movl	%edi, 8(%rsp)                   # 4-byte Spill
	leal	127(%r13), %eax
	leal	254(%r13), %r15d
	testl	%eax, %eax
	cmovnsl	%eax, %r15d
	movl	%r15d, %ebx
	andl	$-128, %ebx
	movl	%esi, 12(%rsp)                  # 4-byte Spill
	movl	%esi, %ebp
	imull	%edi, %ebp
	movslq	%ebp, %r12
	shlq	$3, %r12
	leaq	48(%rsp), %r14
	movq	%r14, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	(%r14), %rdi
	movq	16(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%ebp, %eax
	imull	%ebx, %eax
	movslq	%eax, %r14
	shlq	$3, %r14
	leaq	40(%rsp), %r12
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%r12), %rdi
	xorl	%esi, %esi
	movq	%r14, %rdx
	callq	hipMemset
	movq	(%r12), %rdi
	movl	%ebp, %eax
	imull	%r13d, %eax
	movslq	%eax, %rdx
	shlq	$3, %rdx
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	imull	8(%rsp), %ebx                   # 4-byte Folded Reload
	movslq	%ebx, %rsi
	shlq	$3, %rsi
	leaq	32(%rsp), %rdi
	callq	hipMalloc
	movq	%r13, 56(%rsp)                  # 8-byte Spill
	testl	%r13d, %r13d
	jle	.LBB3_7
# %bb.1:                                # %.lr.ph
	sarl	$7, %r15d
	movabsq	$4294967296, %r13               # imm = 0x100000000
	movslq	12(%rsp), %rax                  # 4-byte Folded Reload
	shlq	$3, %rax
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	movl	8(%rsp), %eax                   # 4-byte Reload
	movl	%eax, %ecx
	btsq	$32, %rcx
	movq	%rcx, 16(%rsp)                  # 8-byte Spill
	shll	$7, %eax
	shll	$7, %ebp
	movslq	%ebp, %rcx
	movslq	%eax, %rdx
	cmpl	$2, %r15d
	movl	$1, %eax
	cmovll	%eax, %r15d
	shlq	$3, %rdx
	movq	%rdx, 72(%rsp)                  # 8-byte Spill
	shlq	$3, %rcx
	movq	%rcx, 80(%rsp)                  # 8-byte Spill
	xorl	%ebx, %ebx
	subq	$-128, %r13
	xorl	%r12d, %r12d
.LBB3_3:                                # =>This Inner Loop Header: Depth=1
	movq	40(%rsp), %r14
	movq	32(%rsp), %rbp
	movq	16(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	movq	24(%rsp), %r8                   # 8-byte Reload
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_5
# %bb.4:                                #   in Loop: Header=BB3_3 Depth=1
	addq	%r12, %rbp
	addq	%rbx, %r14
	movq	48(%rsp), %rsi
	movl	12(%rsp), %edi                  # 4-byte Reload
	movq	%r14, %rdx
	movq	%rbp, %rcx
	callq	_Z25__device_stub__kernel_lseiPdS_S_
.LBB3_5:                                #   in Loop: Header=BB3_3 Depth=1
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB3_6
# %bb.2:                                #   in Loop: Header=BB3_3 Depth=1
	addq	72(%rsp), %r12                  # 8-byte Folded Reload
	addq	80(%rsp), %rbx                  # 8-byte Folded Reload
	decq	%r15
	jne	.LBB3_3
.LBB3_7:                                # %._crit_edge
	movq	32(%rsp), %rsi
	movq	56(%rsp), %rax                  # 8-byte Reload
	imull	8(%rsp), %eax                   # 4-byte Folded Reload
	movslq	%eax, %rdx
	shlq	$3, %rdx
	movq	64(%rsp), %rdi                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB3_6:
	.cfi_def_cfa_offset 144
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
	movl	$-1, %edi
	callq	exit
.Lfunc_end3:
	.size	logSumExpForGMM, .Lfunc_end3-logSumExpForGMM
	.cfi_endproc
                                        # -- End function
	.globl	_Z31__device_stub__kernel_mvn_shareiiiPdS_iS_ # -- Begin function _Z31__device_stub__kernel_mvn_shareiiiPdS_iS_
	.type	_Z31__device_stub__kernel_mvn_shareiiiPdS_iS_,@function
_Z31__device_stub__kernel_mvn_shareiiiPdS_iS_: # @_Z31__device_stub__kernel_mvn_shareiiiPdS_iS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16kernel_mvn_shareiiiPdS_iS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z31__device_stub__kernel_mvn_shareiiiPdS_iS_, .Lfunc_end4-_Z31__device_stub__kernel_mvn_shareiiiPdS_iS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__kernel_share_add_cstiiPdS_ # -- Begin function _Z35__device_stub__kernel_share_add_cstiiPdS_
	.type	_Z35__device_stub__kernel_share_add_cstiiPdS_,@function
_Z35__device_stub__kernel_share_add_cstiiPdS_: # @_Z35__device_stub__kernel_share_add_cstiiPdS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20kernel_share_add_cstiiPdS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z35__device_stub__kernel_share_add_cstiiPdS_, .Lfunc_end5-_Z35__device_stub__kernel_share_add_cstiiPdS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__kernel_vecdot2iiiPdS_S_ # -- Begin function _Z29__device_stub__kernel_vecdot2iiiPdS_S_
	.type	_Z29__device_stub__kernel_vecdot2iiiPdS_S_,@function
_Z29__device_stub__kernel_vecdot2iiiPdS_S_: # @_Z29__device_stub__kernel_vecdot2iiiPdS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	56(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14kernel_vecdot2iiiPdS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z29__device_stub__kernel_vecdot2iiiPdS_S_, .Lfunc_end6-_Z29__device_stub__kernel_vecdot2iiiPdS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__kernel_mvniiPdS_S_S_iS_ # -- Begin function _Z25__device_stub__kernel_mvniiPdS_S_S_iS_
	.type	_Z25__device_stub__kernel_mvniiPdS_S_S_iS_,@function
_Z25__device_stub__kernel_mvniiPdS_S_S_iS_: # @_Z25__device_stub__kernel_mvniiPdS_S_S_iS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10kernel_mvniiPdS_S_S_iS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z25__device_stub__kernel_mvniiPdS_S_S_iS_, .Lfunc_end7-_Z25__device_stub__kernel_mvniiPdS_S_S_iS_
	.cfi_endproc
                                        # -- End function
	.globl	kernelShareAddCstWrapper        # -- Begin function kernelShareAddCstWrapper
	.type	kernelShareAddCstWrapper,@function
kernelShareAddCstWrapper:               # @kernelShareAddCstWrapper
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rcx, %rbx
	movq	%rdx, %r14
	movl	%esi, %ebp
	movl	%edi, %r15d
	movq	48(%rsp), %rdi
	movl	56(%rsp), %esi
	movq	%r8, %rdx
	movl	%r9d, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB8_2
# %bb.1:
	movl	%r15d, %edi
	movl	%ebp, %esi
	movq	%r14, %rdx
	movq	%rbx, %rcx
	callq	_Z35__device_stub__kernel_share_add_cstiiPdS_
.LBB8_2:
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB8_4
# %bb.3:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB8_4:
	.cfi_def_cfa_offset 48
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
	movl	$-1, %edi
	callq	exit
.Lfunc_end8:
	.size	kernelShareAddCstWrapper, .Lfunc_end8-kernelShareAddCstWrapper
	.cfi_endproc
                                        # -- End function
	.globl	kernelVecDotWrapper             # -- Begin function kernelVecDotWrapper
	.type	kernelVecDotWrapper,@function
kernelVecDotWrapper:                    # @kernelVecDotWrapper
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r8, %rbx
	movl	%ecx, %ebp
	movl	%edx, %r14d
	movq	%rsi, %r15
	movq	%rdi, %r12
	movq	64(%rsp), %rdi
	movl	72(%rsp), %esi
	movq	48(%rsp), %rdx
	movl	56(%rsp), %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB9_2
# %bb.1:
	movq	%r12, %rdi
	movq	%r15, %rsi
	movl	%r14d, %edx
	movl	%ebp, %ecx
	movq	%rbx, %r8
	callq	_Z35__device_stub__kernel_vecDotProductPdS_iiS_
.LBB9_2:
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB9_4
# %bb.3:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB9_4:
	.cfi_def_cfa_offset 48
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.2, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
	movl	$-1, %edi
	callq	exit
.Lfunc_end9:
	.size	kernelVecDotWrapper, .Lfunc_end9-kernelVecDotWrapper
	.cfi_endproc
                                        # -- End function
	.globl	kernelDgemvWrapper              # -- Begin function kernelDgemvWrapper
	.type	kernelDgemvWrapper,@function
kernelDgemvWrapper:                     # @kernelDgemvWrapper
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movl	%r8d, %ebp
	movl	%ecx, %r14d
	movl	%edx, %r15d
	movq	%rsi, %r12
	movq	%rdi, %r13
	movslq	96(%rsp), %r8
	movq	80(%rsp), %rdi
	movl	88(%rsp), %esi
	movq	64(%rsp), %rdx
	movl	72(%rsp), %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB10_2
# %bb.1:
	movq	%r13, %rdi
	movq	%r12, %rsi
	movl	%r15d, %edx
	movl	%r14d, %ecx
	movl	%ebp, %r8d
	movq	%rbx, %r9
	callq	_Z34__device_stub__kernel_batchedDgemvPdS_iiiS_
.LBB10_2:
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB10_4
# %bb.3:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB10_4:
	.cfi_def_cfa_offset 64
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.3, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
	movl	$-1, %edi
	callq	exit
.Lfunc_end10:
	.size	kernelDgemvWrapper, .Lfunc_end10-kernelDgemvWrapper
	.cfi_endproc
                                        # -- End function
	.globl	kernelVecDot2Wrapper            # -- Begin function kernelVecDot2Wrapper
	.type	kernelVecDot2Wrapper,@function
kernelVecDot2Wrapper:                   # @kernelVecDot2Wrapper
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movl	%r8d, %ebp
	movl	%ecx, %r13d
	movl	%edx, %r15d
	movq	%rsi, %r14
	movq	%rdi, %r12
	movslq	96(%rsp), %r8
	movq	80(%rsp), %rdi
	movl	88(%rsp), %esi
	movq	64(%rsp), %rdx
	movl	72(%rsp), %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_2
# %bb.1:
	movl	%r13d, %edi
	movl	%ebp, %esi
	movl	%r15d, %edx
	movq	%r12, %rcx
	movq	%r14, %r8
	movq	%rbx, %r9
	callq	_Z29__device_stub__kernel_vecdot2iiiPdS_S_
.LBB11_2:
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB11_4
# %bb.3:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB11_4:
	.cfi_def_cfa_offset 64
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.4, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
	movl	$-1, %edi
	callq	exit
.Lfunc_end11:
	.size	kernelVecDot2Wrapper, .Lfunc_end11-kernelVecDot2Wrapper
	.cfi_endproc
                                        # -- End function
	.globl	kernelSharedMvnWrapper          # -- Begin function kernelSharedMvnWrapper
	.type	kernelSharedMvnWrapper,@function
kernelSharedMvnWrapper:                 # @kernelSharedMvnWrapper
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, 20(%rsp)                  # 4-byte Spill
	movq	%r8, %r14
	movq	%rcx, %r15
	movl	%edx, %ebp
	movl	%esi, %r12d
	movl	%edi, %r13d
	movq	80(%rsp), %rbx
	movslq	120(%rsp), %r8
	movq	104(%rsp), %rdi
	movl	112(%rsp), %esi
	movq	88(%rsp), %rdx
	movl	96(%rsp), %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_2
# %bb.1:
	movl	%r13d, %eax
	cltd
	idivl	%ebp
	movq	%rbx, (%rsp)
	movl	%eax, %edi
	movl	%r12d, %esi
	movl	%ebp, %edx
	movq	%r15, %rcx
	movq	%r14, %r8
	movl	20(%rsp), %r9d                  # 4-byte Reload
	callq	_Z31__device_stub__kernel_mvn_shareiiiPdS_iS_
.LBB12_2:
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB12_3
# %bb.4:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	hipDeviceSynchronize            # TAILCALL
.LBB12_3:
	.cfi_def_cfa_offset 80
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
	movl	$-1, %edi
	callq	exit
.Lfunc_end12:
	.size	kernelSharedMvnWrapper, .Lfunc_end12-kernelSharedMvnWrapper
	.cfi_endproc
                                        # -- End function
	.globl	kernelMvnWrapper                # -- Begin function kernelMvnWrapper
	.type	kernelMvnWrapper,@function
kernelMvnWrapper:                       # @kernelMvnWrapper
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 16(%rsp)                   # 8-byte Spill
	movq	%r8, 8(%rsp)                    # 8-byte Spill
	movq	%rcx, %r15
	movq	%rdx, %r12
	movl	%esi, %ebp
	movl	%edi, %r13d
	movq	88(%rsp), %r14
	movl	80(%rsp), %ebx
	movslq	128(%rsp), %r8
	movq	112(%rsp), %rdi
	movl	120(%rsp), %esi
	movq	96(%rsp), %rdx
	movl	104(%rsp), %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB13_2
# %bb.1:
	movl	%r13d, %edi
	movl	%ebp, %esi
	movq	%r12, %rdx
	movq	%r15, %rcx
	movq	8(%rsp), %r8                    # 8-byte Reload
	movq	16(%rsp), %r9                   # 8-byte Reload
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	callq	_Z25__device_stub__kernel_mvniiPdS_S_S_iS_
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB13_2:
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB13_3
# %bb.4:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	hipDeviceSynchronize            # TAILCALL
.LBB13_3:
	.cfi_def_cfa_offset 80
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
	movl	$-1, %edi
	callq	exit
.Lfunc_end13:
	.size	kernelMvnWrapper, .Lfunc_end13-kernelMvnWrapper
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__kernel_diag_mvniiPdS_S_S_iS_ # -- Begin function _Z30__device_stub__kernel_diag_mvniiPdS_S_S_iS_
	.type	_Z30__device_stub__kernel_diag_mvniiPdS_S_S_iS_,@function
_Z30__device_stub__kernel_diag_mvniiPdS_S_S_iS_: # @_Z30__device_stub__kernel_diag_mvniiPdS_S_S_iS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15kernel_diag_mvniiPdS_S_S_iS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end14:
	.size	_Z30__device_stub__kernel_diag_mvniiPdS_S_S_iS_, .Lfunc_end14-_Z30__device_stub__kernel_diag_mvniiPdS_S_S_iS_
	.cfi_endproc
                                        # -- End function
	.globl	kernelDiagMvnWrapper            # -- Begin function kernelDiagMvnWrapper
	.type	kernelDiagMvnWrapper,@function
kernelDiagMvnWrapper:                   # @kernelDiagMvnWrapper
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movq	%r8, %r14
	movq	%rcx, %r15
	movq	%rdx, %r12
	movl	%esi, %ebp
	movl	%edi, %r13d
	movslq	112(%rsp), %r8
	movq	96(%rsp), %rdi
	movl	104(%rsp), %esi
	movq	80(%rsp), %rdx
	movl	88(%rsp), %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB15_2
# %bb.1:
	movl	64(%rsp), %eax
	movl	%r13d, %edi
	movl	%ebp, %esi
	movq	%r12, %rdx
	movq	%r15, %rcx
	movq	%r14, %r8
	movq	%rbx, %r9
	pushq	72(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	callq	_Z30__device_stub__kernel_diag_mvniiPdS_S_S_iS_
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB15_2:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB15_4
# %bb.3:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB15_4:
	.cfi_def_cfa_offset 64
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
	movl	$-1, %edi
	callq	exit
.Lfunc_end15:
	.size	kernelDiagMvnWrapper, .Lfunc_end15-kernelDiagMvnWrapper
	.cfi_endproc
                                        # -- End function
	.globl	kernelLSEWrapper                # -- Begin function kernelLSEWrapper
	.type	kernelLSEWrapper,@function
kernelLSEWrapper:                       # @kernelLSEWrapper
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movq	%r8, %r14
	movq	%rcx, %r15
	movl	%edx, %ebp
	movslq	%edx, %r8
	shlq	$3, %r8
	movl	%edi, %edi
	btsq	$32, %rdi
	movl	%esi, %edx
	btsq	$32, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB16_2
# %bb.1:
	movl	%ebp, %edi
	movq	%r15, %rsi
	movq	%r14, %rdx
	movq	%rbx, %rcx
	callq	_Z25__device_stub__kernel_lseiPdS_S_
.LBB16_2:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB16_4
# %bb.3:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB16_4:
	.cfi_def_cfa_offset 48
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
	movl	$-1, %edi
	callq	exit
.Lfunc_end16:
	.size	kernelLSEWrapper, .Lfunc_end16-kernelLSEWrapper
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB17_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB17_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20kernel_vecDotProductPdS_iiS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19kernel_batchedDgemvPdS_iiiS_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10kernel_lseiPdS_S_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16kernel_mvn_shareiiiPdS_iS_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20kernel_share_add_cstiiPdS_, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14kernel_vecdot2iiiPdS_S_, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10kernel_mvniiPdS_S_S_iS_, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15kernel_diag_mvniiPdS_S_S_iS_, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end17:
	.size	__hip_module_ctor, .Lfunc_end17-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB18_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB18_2:
	retq
.Lfunc_end18:
	.size	__hip_module_dtor, .Lfunc_end18-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z20kernel_vecDotProductPdS_iiS_,@object # @_Z20kernel_vecDotProductPdS_iiS_
	.section	.rodata,"a",@progbits
	.globl	_Z20kernel_vecDotProductPdS_iiS_
	.p2align	3, 0x0
_Z20kernel_vecDotProductPdS_iiS_:
	.quad	_Z35__device_stub__kernel_vecDotProductPdS_iiS_
	.size	_Z20kernel_vecDotProductPdS_iiS_, 8

	.type	_Z19kernel_batchedDgemvPdS_iiiS_,@object # @_Z19kernel_batchedDgemvPdS_iiiS_
	.globl	_Z19kernel_batchedDgemvPdS_iiiS_
	.p2align	3, 0x0
_Z19kernel_batchedDgemvPdS_iiiS_:
	.quad	_Z34__device_stub__kernel_batchedDgemvPdS_iiiS_
	.size	_Z19kernel_batchedDgemvPdS_iiiS_, 8

	.type	_Z10kernel_lseiPdS_S_,@object   # @_Z10kernel_lseiPdS_S_
	.globl	_Z10kernel_lseiPdS_S_
	.p2align	3, 0x0
_Z10kernel_lseiPdS_S_:
	.quad	_Z25__device_stub__kernel_lseiPdS_S_
	.size	_Z10kernel_lseiPdS_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"kernel launch failed in LSE with error \"%s\".\n"
	.size	.L.str, 46

	.type	_Z16kernel_mvn_shareiiiPdS_iS_,@object # @_Z16kernel_mvn_shareiiiPdS_iS_
	.section	.rodata,"a",@progbits
	.globl	_Z16kernel_mvn_shareiiiPdS_iS_
	.p2align	3, 0x0
_Z16kernel_mvn_shareiiiPdS_iS_:
	.quad	_Z31__device_stub__kernel_mvn_shareiiiPdS_iS_
	.size	_Z16kernel_mvn_shareiiiPdS_iS_, 8

	.type	_Z20kernel_share_add_cstiiPdS_,@object # @_Z20kernel_share_add_cstiiPdS_
	.globl	_Z20kernel_share_add_cstiiPdS_
	.p2align	3, 0x0
_Z20kernel_share_add_cstiiPdS_:
	.quad	_Z35__device_stub__kernel_share_add_cstiiPdS_
	.size	_Z20kernel_share_add_cstiiPdS_, 8

	.type	_Z14kernel_vecdot2iiiPdS_S_,@object # @_Z14kernel_vecdot2iiiPdS_S_
	.globl	_Z14kernel_vecdot2iiiPdS_S_
	.p2align	3, 0x0
_Z14kernel_vecdot2iiiPdS_S_:
	.quad	_Z29__device_stub__kernel_vecdot2iiiPdS_S_
	.size	_Z14kernel_vecdot2iiiPdS_S_, 8

	.type	_Z10kernel_mvniiPdS_S_S_iS_,@object # @_Z10kernel_mvniiPdS_S_S_iS_
	.globl	_Z10kernel_mvniiPdS_S_S_iS_
	.p2align	3, 0x0
_Z10kernel_mvniiPdS_S_S_iS_:
	.quad	_Z25__device_stub__kernel_mvniiPdS_S_S_iS_
	.size	_Z10kernel_mvniiPdS_S_S_iS_, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"kernel share_add_cst launch failed with error \"%s\".\n"
	.size	.L.str.1, 53

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"kernel vecdot launch failed with error \"%s\".\n"
	.size	.L.str.2, 46

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"kernel dgemv launch failed with error \"%s\".\n"
	.size	.L.str.3, 45

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"kernel vecdot2 launch failed with error \"%s\".\n"
	.size	.L.str.4, 47

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"kernel launch failed with error \"%s\".\n"
	.size	.L.str.5, 39

	.type	_Z15kernel_diag_mvniiPdS_S_S_iS_,@object # @_Z15kernel_diag_mvniiPdS_S_S_iS_
	.section	.rodata,"a",@progbits
	.globl	_Z15kernel_diag_mvniiPdS_S_S_iS_
	.p2align	3, 0x0
_Z15kernel_diag_mvniiPdS_S_S_iS_:
	.quad	_Z30__device_stub__kernel_diag_mvniiPdS_S_S_iS_
	.size	_Z15kernel_diag_mvniiPdS_S_S_iS_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z20kernel_vecDotProductPdS_iiS_"
	.size	.L__unnamed_1, 33

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z19kernel_batchedDgemvPdS_iiiS_"
	.size	.L__unnamed_2, 33

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z10kernel_lseiPdS_S_"
	.size	.L__unnamed_3, 22

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z16kernel_mvn_shareiiiPdS_iS_"
	.size	.L__unnamed_4, 31

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z20kernel_share_add_cstiiPdS_"
	.size	.L__unnamed_5, 31

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z14kernel_vecdot2iiiPdS_S_"
	.size	.L__unnamed_6, 28

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z10kernel_mvniiPdS_S_S_iS_"
	.size	.L__unnamed_7, 28

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z15kernel_diag_mvniiPdS_S_S_iS_"
	.size	.L__unnamed_8, 33

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z35__device_stub__kernel_vecDotProductPdS_iiS_
	.addrsig_sym _Z34__device_stub__kernel_batchedDgemvPdS_iiiS_
	.addrsig_sym _Z25__device_stub__kernel_lseiPdS_S_
	.addrsig_sym _Z31__device_stub__kernel_mvn_shareiiiPdS_iS_
	.addrsig_sym _Z35__device_stub__kernel_share_add_cstiiPdS_
	.addrsig_sym _Z29__device_stub__kernel_vecdot2iiiPdS_S_
	.addrsig_sym _Z25__device_stub__kernel_mvniiPdS_S_S_iS_
	.addrsig_sym _Z30__device_stub__kernel_diag_mvniiPdS_S_S_iS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z20kernel_vecDotProductPdS_iiS_
	.addrsig_sym _Z19kernel_batchedDgemvPdS_iiiS_
	.addrsig_sym _Z10kernel_lseiPdS_S_
	.addrsig_sym _Z16kernel_mvn_shareiiiPdS_iS_
	.addrsig_sym _Z20kernel_share_add_cstiiPdS_
	.addrsig_sym _Z14kernel_vecdot2iiiPdS_S_
	.addrsig_sym _Z10kernel_mvniiPdS_S_S_iS_
	.addrsig_sym _Z15kernel_diag_mvniiPdS_S_S_iS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z20kernel_vecDotProductPdS_iiS_ ; -- Begin function _Z20kernel_vecDotProductPdS_iiS_
	.globl	_Z20kernel_vecDotProductPdS_iiS_
	.p2align	8
	.type	_Z20kernel_vecDotProductPdS_iiS_,@function
_Z20kernel_vecDotProductPdS_iiS_:       ; @_Z20kernel_vecDotProductPdS_iiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s3, v1
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_7
; %bb.1:
	s_cmp_lt_i32 s2, 1
	s_cbranch_scc1 .LBB0_5
; %bb.2:                                ; %.lr.ph.preheader
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mul_lo_u32 v2, v1, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[6:7], 3, v[2:3]
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
.LBB0_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[8:9], v[4:5], off
	global_load_b64 v[10:11], v[6:7], off
	v_add_co_u32 v4, vcc_lo, v4, 8
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, v6, 8
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_add_i32 s2, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s2, 0
	s_waitcnt vmcnt(0)
	v_fma_f64 v[2:3], v[8:9], v[10:11], v[2:3]
	s_cbranch_scc0 .LBB0_3
; %bb.4:                                ; %._crit_edge.loopexit
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[3:4], v[2:3], 0.5
	s_branch .LBB0_6
.LBB0_5:
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
.LBB0_6:                                ; %Flow
	s_load_b64 s[0:1], s[0:1], 0x18
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b64 v[5:6], v[0:1], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[3:4], v[5:6]
	global_store_b64 v[0:1], v[2:3], off
.LBB0_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20kernel_vecDotProductPdS_iiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z20kernel_vecDotProductPdS_iiS_, .Lfunc_end0-_Z20kernel_vecDotProductPdS_iiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 312
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z19kernel_batchedDgemvPdS_iiiS_ ; -- Begin function _Z19kernel_batchedDgemvPdS_iiiS_
	.globl	_Z19kernel_batchedDgemvPdS_iiiS_
	.p2align	8
	.type	_Z19kernel_batchedDgemvPdS_iiiS_,@function
_Z19kernel_batchedDgemvPdS_iiiS_:       ; @_Z19kernel_batchedDgemvPdS_iiiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b256 s[4:11], s[0:1], 0x0
	s_mov_b32 s3, -1
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s11, s2, s8
	s_add_i32 s12, s2, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s12, s12, -1
	s_cmp_ge_u32 s12, s2
	s_cbranch_scc0 .LBB1_6
; %bb.1:                                ; %.lr.ph
	v_cvt_f32_u32_e32 v1, s2
	s_sub_i32 s13, 0, s2
	v_lshl_add_u32 v3, v0, 3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s3, v1
	v_mad_u64_u32 v[1:2], null, s11, s15, v[0:1]
	s_mul_i32 s13, s13, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s13, s3, s13
	s_add_i32 s3, s3, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s13, s12, s3
	s_mul_i32 s3, s9, s8
	s_mul_i32 s14, s13, s2
	s_sub_i32 s12, s12, s14
	s_add_i32 s14, s13, 1
	s_sub_i32 s16, s12, s2
	s_cmp_ge_u32 s12, s2
	s_cselect_b32 s13, s14, s13
	s_cselect_b32 s11, s16, s12
	s_add_i32 s12, s13, 1
	s_cmp_ge_u32 s11, s2
	s_mov_b32 s11, 0
	s_cselect_b32 s12, s12, s13
	s_lshl_b32 s13, s2, 3
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s14, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB1_4
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[1:2]
	v_add_co_u32 v4, vcc_lo, s6, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v3, v[4:5]
.LBB1_4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	v_add_nc_u32_e32 v3, s13, v3
	v_add_nc_u32_e32 v1, s2, v1
	s_add_i32 s11, s11, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s11, s12
	s_cbranch_scc0 .LBB1_2
; %bb.5:                                ; %Flow135
	s_mov_b32 s3, 0
.LBB1_6:                                ; %Flow136
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_and_b32 vcc_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s9, v1
	s_cbranch_execz .LBB1_16
; %bb.7:
	s_cmp_lt_i32 s8, 1
	s_cbranch_scc1 .LBB1_16
; %bb.8:                                ; %.preheader.preheader
	s_ashr_i32 s2, s10, 31
	v_ashrrev_i32_e32 v4, 31, v1
	s_add_i32 s3, s10, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s3, s3, s2
	v_cvt_f32_u32_e32 v2, s3
	s_sub_i32 s6, 0, s3
	v_add_nc_u32_e32 v5, v1, v4
	v_mul_lo_u32 v1, v1, s8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_iflag_f32_e32 v2, v2
	v_xor_b32_e32 v5, v5, v4
	v_xor_b32_e32 v4, s2, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v2, v2
	v_mul_lo_u32 v3, s6, v2
	s_add_i32 s6, s8, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v2, v3
	v_add_nc_u32_e32 v2, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v5, v2
	v_mul_lo_u32 v3, v2, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v5, v3
	v_add_nc_u32_e32 v5, 1, v2
	v_subrev_nc_u32_e32 v6, s3, v3
	v_cmp_le_u32_e32 vcc_lo, s3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v3, v3, v6 :: v_dual_cndmask_b32 v2, v2, v5
	v_cmp_le_u32_e32 vcc_lo, s3, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v5, 1, v2
	s_load_b64 s[2:3], s[0:1], 0x20
	s_mul_i32 s0, s6, s8
	v_mul_lo_u32 v3, v0, s8
	s_lshr_b32 s1, s0, 31
	v_cndmask_b32_e32 v2, v2, v5, vcc_lo
	s_add_i32 s0, s0, s1
	s_mov_b32 s1, 0
	s_ashr_i32 s0, s0, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v2, v4
	v_sub_nc_u32_e32 v2, v2, v4
	v_lshl_add_u32 v4, v3, 3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v2, s0
	v_add_nc_u32_e32 v9, 8, v4
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 3, v[5:6]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v1, vcc_lo
	s_mov_b32 s2, s1
	v_add_co_u32 v7, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s5, 2
	s_mov_b32 s4, 0
.LBB1_9:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_11 Depth 2
                                        ;     Child Loop BB1_14 Depth 2
	s_cmp_eq_u32 s2, 0
	s_cbranch_scc1 .LBB1_12
; %bb.10:                               ; %.lr.ph77
                                        ;   in Loop: Header=BB1_9 Depth=1
	s_lshr_b32 s0, s4, 1
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[6:7], s[0:1], 3
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v10, v4
	v_add_co_u32 v2, vcc_lo, v7, s6
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v8, vcc_lo
	s_add_i32 s6, s2, 1
	s_mov_b32 s0, 0
.LBB1_11:                               ;   Parent Loop BB1_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b64 v[11:12], v[2:3], off
	ds_load_b64 v[13:14], v10
	v_add_co_u32 v2, vcc_lo, v2, 8
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_add_nc_u32_e32 v10, 8, v10
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s0, s2
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[0:1], v[11:12], v[13:14], v[0:1]
	s_cbranch_scc0 .LBB1_11
	s_branch .LBB1_13
.LBB1_12:                               ;   in Loop: Header=BB1_9 Depth=1
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_mov_b32 s6, 1
.LBB1_13:                               ; %Flow132
                                        ;   in Loop: Header=BB1_9 Depth=1
	v_mov_b32_e32 v2, v9
	s_cmp_ge_i32 s6, s8
	s_mov_b32 s0, s6
	s_cbranch_scc1 .LBB1_15
.LBB1_14:                               ; %.lr.ph82
                                        ;   Parent Loop BB1_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_add_i32 s3, s0, 1
	ds_load_b64 v[12:13], v2
	s_mul_i32 s0, s3, s0
	v_add_nc_u32_e32 v2, 8, v2
	s_lshr_b32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s2
	s_lshl_b64 s[10:11], s[0:1], 3
	s_cmp_ge_i32 s3, s8
	v_add_co_u32 v10, vcc_lo, v7, s10
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v8, vcc_lo
	s_mov_b32 s0, s3
	global_load_b64 v[10:11], v[10:11], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[0:1], v[10:11], v[12:13], v[0:1]
	s_cbranch_scc0 .LBB1_14
.LBB1_15:                               ; %Flow130
                                        ;   in Loop: Header=BB1_9 Depth=1
	s_mul_i32 s0, s6, s2
	v_lshl_add_u32 v10, s2, 3, v4
	s_lshr_b32 s0, s0, 1
	s_mov_b32 s3, s1
	s_add_i32 s0, s0, s2
	s_lshl_b64 s[2:3], s[2:3], 3
	s_lshl_b64 s[10:11], s[0:1], 3
	ds_load_b64 v[10:11], v10
	v_add_co_u32 v2, vcc_lo, v7, s10
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v8, vcc_lo
	v_add_nc_u32_e32 v9, 8, v9
	s_add_i32 s0, s5, 2
	s_add_i32 s4, s4, s5
	global_load_b64 v[2:3], v[2:3], off
	s_cmp_eq_u32 s6, s8
	s_mov_b32 s5, s0
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], v[2:3], v[10:11], v[0:1]
	v_add_co_u32 v2, vcc_lo, v5, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v6, vcc_lo
	s_mov_b32 s2, s6
	global_store_b64 v[2:3], v[0:1], off
	s_cbranch_scc0 .LBB1_9
.LBB1_16:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19kernel_batchedDgemvPdS_iiiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 17
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z19kernel_batchedDgemvPdS_iiiS_, .Lfunc_end1-_Z19kernel_batchedDgemvPdS_iiiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1036
; NumSgprs: 19
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10kernel_lseiPdS_S_   ; -- Begin function _Z10kernel_lseiPdS_S_
	.globl	_Z10kernel_lseiPdS_S_
	.p2align	8
	.type	_Z10kernel_lseiPdS_S_,@function
_Z10kernel_lseiPdS_S_:                  ; @_Z10kernel_lseiPdS_S_
; %bb.0:
	s_clause 0x3
	s_load_b32 s9, s[0:1], 0x2c
	s_load_b32 s33, s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x8
	s_add_u32 s0, s0, 32
	s_addc_u32 s1, s1, 0
	s_mov_b32 s8, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s9, s9, 0xffff
	s_add_i32 s10, s33, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v1, s10, s10, s9
	s_and_b32 vcc_lo, exec_lo, s10
	s_delay_alu instid0(VALU_DEP_1)
	v_readfirstlane_b32 s11, v1
	s_cbranch_vccnz .LBB2_5
; %bb.1:                                ; %.lr.ph
	v_cvt_f32_u32_e32 v1, s9
	s_sub_i32 s12, 0, s9
	v_lshl_add_u32 v3, v0, 3, 0
	v_mov_b32_e32 v4, v0
	v_mov_b32_e32 v2, 0
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s10, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s12, s12, s10
	s_mul_hi_u32 s12, s10, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_i32 s12, s10, s12
	s_mov_b32 s10, 0
	s_mul_hi_u32 s12, s11, s12
	s_mul_i32 s13, s12, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s11, s11, s13
	s_add_i32 s13, s12, 1
	s_sub_i32 s14, s11, s9
	s_cmp_ge_u32 s11, s9
	s_cselect_b32 s12, s13, s12
	s_cselect_b32 s11, s14, s11
	s_add_i32 s13, s12, 1
	s_cmp_ge_u32 s11, s9
	s_mul_i32 s11, s8, s33
	s_cselect_b32 s12, s13, s12
	s_lshl_b32 s13, s9, 3
.LBB2_2:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s14, exec_lo
	v_cmpx_gt_u32_e64 s33, v4
	s_cbranch_execz .LBB2_4
; %bb.3:                                ;   in Loop: Header=BB2_2 Depth=1
	v_add_nc_u32_e32 v1, s11, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 3, v[1:2]
	v_add_co_u32 v5, vcc_lo, s4, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	global_load_b64 v[5:6], v[5:6], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v3, v[5:6]
.LBB2_4:                                ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	v_add_nc_u32_e32 v4, s9, v4
	v_add_nc_u32_e32 v3, s13, v3
	s_add_i32 s10, s10, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s10, s12
	s_cbranch_scc0 .LBB2_2
.LBB2_5:                                ; %._crit_edge
	s_load_b32 s9, s[0:1], 0x0
	s_cmp_lt_i32 s33, 1
	s_waitcnt lgkmcnt(0)
	s_cselect_b32 s1, -1, 0
	s_barrier
	s_and_b32 vcc_lo, exec_lo, s1
	buffer_gl0_inv
	s_cbranch_vccnz .LBB2_10
; %bb.6:                                ; %.lr.ph95
	v_mad_u64_u32 v[3:4], null, s9, v0, s[8:9]
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v6, -1
	v_mov_b32_e32 v2, 0
	s_mov_b32 s4, 0x55555555
	s_mov_b32 s10, 0x6b47b09a
	s_mov_b32 s12, 0xbf559e2b
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_lo_u32 v5, v3, s33
	s_mov_b32 s14, 0xd7f4df2e
	s_mov_b32 s16, 0x16291751
	s_mov_b32 s18, 0x9b27acf1
	s_mov_b32 s20, 0x998ef7b6
	s_mov_b32 s22, 0xfefa39ef
	s_mov_b32 s24, 0x3b39803f
	s_mov_b32 s5, 0x3fe55555
	s_mov_b32 s11, 0x3fc38538
	s_mov_b32 s13, 0x3fc3ab76
	s_mov_b32 s15, 0x3fc7474d
	s_mov_b32 s17, 0x3fcc71c0
	s_mov_b32 s19, 0x3fd24924
	s_mov_b32 s21, 0x3fd99999
	s_mov_b32 s23, 0x3fe62e42
	s_mov_b32 s25, 0x3c7abc9e
	s_mov_b32 s28, 0
	s_mov_b32 s29, 0
	s_mov_b32 s26, 0x55555780
.LBB2_7:                                ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v3, s29
	ds_load_b64 v[3:4], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f64_e32 vcc_lo, 0, v[3:4]
	s_cbranch_vccnz .LBB2_9
; %bb.8:                                ;   in Loop: Header=BB2_7 Depth=1
	v_frexp_mant_f64_e32 v[7:8], v[3:4]
	s_mov_b32 s27, s5
	v_cmp_eq_u32_e64 s0, -1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, s[4:5], v[7:8]
	v_cndmask_b32_e64 v9, 0, 1, vcc_lo
	v_ldexp_f64 v[7:8], v[7:8], v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[7:8], 1.0
	v_add_f64 v[15:16], v[7:8], -1.0
	v_rcp_f64_e32 v[11:12], v[9:10]
	v_add_f64 v[17:18], v[9:10], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], -v[17:18]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
	v_fma_f64 v[11:12], v[13:14], v[11:12], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
	v_fma_f64 v[11:12], v[13:14], v[11:12], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[13:14], v[15:16], v[11:12]
	v_mul_f64 v[19:20], v[9:10], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], v[13:14], v[9:10], -v[19:20]
	v_fma_f64 v[7:8], v[13:14], v[7:8], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[19:20], v[7:8]
	v_add_f64 v[17:18], v[15:16], -v[9:10]
	v_add_f64 v[19:20], v[9:10], -v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[15:16], -v[17:18]
	v_add_f64 v[7:8], v[19:20], -v[7:8]
	v_frexp_exp_i32_f64_e32 v19, v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[15:16], -v[9:10]
	v_add_f64 v[7:8], v[7:8], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[17:18], v[7:8]
	v_mul_f64 v[7:8], v[11:12], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[13:14], v[7:8]
	v_mul_f64 v[11:12], v[9:10], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], v[11:12], s[12:13], s[10:11]
	v_mul_f64 v[17:18], v[9:10], v[11:12]
	v_fma_f64 v[15:16], v[11:12], v[15:16], s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[11:12], v[15:16], s[16:17]
	v_fma_f64 v[15:16], v[11:12], v[15:16], s[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[11:12], v[15:16], s[20:21]
	v_fma_f64 v[11:12], v[11:12], v[15:16], s[26:27]
	v_ldexp_f64 v[15:16], v[9:10], 1
	v_add_f64 v[9:10], v[9:10], -v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[11:12], v[17:18], v[11:12]
	v_subrev_co_ci_u32_e32 v17, vcc_lo, 0, v19, vcc_lo
	v_add_f64 v[7:8], v[7:8], -v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_f64_i32_e32 v[17:18], v17
	v_add_f64 v[13:14], v[15:16], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[7:8], v[7:8], 1
	v_mul_f64 v[19:20], v[17:18], s[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[13:14], -v[15:16]
	v_fma_f64 v[15:16], v[17:18], s[22:23], -v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[11:12], -v[9:10]
	v_fma_f64 v[11:12], v[17:18], s[24:25], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[7:8], v[9:10]
	v_add_f64 v[9:10], v[19:20], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[13:14], v[7:8]
	v_add_f64 v[19:20], v[9:10], -v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[17:18], v[9:10], v[15:16]
	v_add_f64 v[13:14], v[15:16], -v[13:14]
	v_add_f64 v[11:12], v[11:12], -v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[17:18], -v[9:10]
	v_add_f64 v[7:8], v[7:8], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[23:24], v[17:18], -v[21:22]
	v_add_f64 v[13:14], v[15:16], -v[21:22]
	v_add_f64 v[15:16], v[11:12], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[9:10], -v[23:24]
	v_add_f64 v[9:10], v[13:14], v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[15:16], -v[11:12]
	v_add_f64 v[9:10], v[15:16], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[15:16], -v[13:14]
	v_add_f64 v[7:8], v[7:8], -v[13:14]
	v_add_f64 v[19:20], v[17:18], v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[11:12], -v[15:16]
	v_add_f64 v[13:14], v[19:20], -v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[7:8], v[11:12]
	v_add_f64 v[9:10], v[9:10], -v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], v[9:10]
	v_add_f64 v[7:8], v[19:20], v[7:8]
	v_add_nc_u32_e32 v25, s28, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v26, 31, v25
	v_lshlrev_b64 v[25:26], 3, v[25:26]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v25, vcc_lo, s6, v25
	v_add_co_ci_u32_e32 v26, vcc_lo, s7, v26, vcc_lo
	v_cmp_class_f64_e64 vcc_lo, v[3:4], 0x204
	global_load_b64 v[27:28], v[25:26], off
	v_dual_cndmask_b32 v8, v8, v4 :: v_dual_cndmask_b32 v7, v7, v3
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v8, 0x7ff80000, v8, vcc_lo
	v_cmp_nge_f64_e32 vcc_lo, 0, v[3:4]
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cmp_neq_f64_e32 vcc_lo, 0, v[3:4]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v8, 0xfff00000, v8, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[3:4], v[7:8], v[27:28]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, v[3:4], v[1:2]
	global_store_b64 v[25:26], v[3:4], off
	s_or_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e32 v2, v2, v4, vcc_lo
	v_cndmask_b32_e64 v6, v6, s28, vcc_lo
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
.LBB2_9:                                ;   in Loop: Header=BB2_7 Depth=1
	s_add_i32 s28, s28, 1
	s_add_i32 s29, s29, 8
	s_cmp_eq_u32 s33, s28
	s_cbranch_scc0 .LBB2_7
	s_branch .LBB2_11
.LBB2_10:
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
.LBB2_11:                               ; %.preheader88
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB2_13
; %bb.12:                               ; %.preheader.._crit_edge104_crit_edge
	v_mad_u64_u32 v[3:4], null, s9, v0, s[8:9]
	s_mov_b32 s4, 0
	s_mov_b64 s[0:1], 0
	s_branch .LBB2_14
.LBB2_13:
	s_mov_b32 s4, -1
                                        ; implicit-def: $sgpr0_sgpr1
                                        ; implicit-def: $vgpr3
.LBB2_14:                               ; %Flow147
	v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
	s_and_not1_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB2_27
; %bb.15:                               ; %.lr.ph98
	v_mad_u64_u32 v[3:4], null, s9, v0, s[8:9]
	s_mov_b32 s0, 0
	s_mov_b32 s1, s33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, v3, s33
	v_mov_b32_e32 v5, v4
.LBB2_16:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v0, s0
	ds_load_b64 v[6:7], v0
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f64_e32 vcc_lo, 0, v[6:7]
	s_cbranch_vccnz .LBB2_18
; %bb.17:                               ;   in Loop: Header=BB2_16 Depth=1
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[5:6]
	v_add_co_u32 v6, vcc_lo, s6, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	global_load_b64 v[8:9], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], v[8:9], -v[1:2]
	global_store_b64 v[6:7], v[8:9], off
.LBB2_18:                               ;   in Loop: Header=BB2_16 Depth=1
	v_add_nc_u32_e32 v5, 1, v5
	s_add_i32 s1, s1, -1
	s_add_i32 s0, s0, 8
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc0 .LBB2_16
; %bb.19:                               ; %.preheader87
	v_mov_b32_e32 v5, v4
	s_mov_b32 s4, 0x652b82fe
	s_mov_b32 s8, 0xfefa39ef
	s_mov_b32 s10, 0x3b39803f
	s_mov_b32 s12, 0xfca7ab0c
	s_mov_b32 s14, 0x6a5dcb37
	s_mov_b32 s16, 0x623fde64
	s_mov_b32 s18, 0x7c89e6b0
	s_mov_b32 s20, 0x14761f6e
	s_mov_b32 s22, 0x1852b7b0
	s_mov_b32 s24, 0x11122322
	s_mov_b32 s26, 0x555502a1
	s_mov_b32 s28, 0x55555511
	s_mov_b32 s30, 11
	s_mov_b32 s5, 0x3ff71547
	s_mov_b32 s9, 0xbfe62e42
	s_mov_b32 s11, 0xbc7abc9e
	s_mov_b32 s13, 0x3e928af3
	s_mov_b32 s15, 0x3e5ade15
	s_mov_b32 s17, 0x3ec71dee
	s_mov_b32 s19, 0x3efa0199
	s_mov_b32 s21, 0x3f2a01a0
	s_mov_b32 s23, 0x3f56c16c
	s_mov_b32 s25, 0x3f811111
	s_mov_b32 s27, 0x3fa55555
	s_mov_b32 s29, 0x3fc55555
	s_mov_b32 s31, 0x3fe00000
	s_mov_b32 s1, 0
	s_mov_b32 s34, s33
.LBB2_20:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v0, s1
	ds_load_b64 v[6:7], v0
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f64_e32 vcc_lo, 0, v[6:7]
	s_cbranch_vccnz .LBB2_22
; %bb.21:                               ;   in Loop: Header=BB2_20 Depth=1
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[5:6]
	v_add_co_u32 v6, vcc_lo, s6, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	global_load_b64 v[8:9], v[6:7], off
	s_waitcnt vmcnt(0)
	v_mul_f64 v[10:11], v[8:9], s[4:5]
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[8:9]
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[10:11], v[10:11]
	v_fma_f64 v[12:13], v[10:11], s[8:9], v[8:9]
	v_cvt_i32_f64_e32 v0, v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], s[10:11], v[12:13]
	v_fma_f64 v[14:15], v[12:13], s[14:15], s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[16:17]
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[20:21]
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[24:25]
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[28:29]
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[12:13], v[14:15], 1.0
	v_fma_f64 v[10:11], v[12:13], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[10:11], v[10:11], v0
	v_cndmask_b32_e32 v0, 0x7ff00000, v11, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v8, 0, v10, vcc_lo
	v_cndmask_b32_e64 v9, 0, v0, s0
	global_store_b64 v[6:7], v[8:9], off
.LBB2_22:                               ;   in Loop: Header=BB2_20 Depth=1
	v_add_nc_u32_e32 v5, 1, v5
	s_add_i32 s34, s34, -1
	s_add_i32 s1, s1, 8
	s_cmp_eq_u32 s34, 0
	s_cbranch_scc0 .LBB2_20
; %bb.23:                               ; %.preheader
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	s_mov_b32 s0, 0
.LBB2_24:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v0, s0
	ds_load_b64 v[8:9], v0
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f64_e32 vcc_lo, 0, v[8:9]
	s_cbranch_vccnz .LBB2_26
; %bb.25:                               ;   in Loop: Header=BB2_24 Depth=1
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 3, v[4:5]
	v_add_co_u32 v8, vcc_lo, s6, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
	global_load_b64 v[8:9], v[8:9], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[6:7], v[6:7], v[8:9]
.LBB2_26:                               ;   in Loop: Header=BB2_24 Depth=1
	v_add_nc_u32_e32 v4, 1, v4
	s_add_i32 s33, s33, -1
	s_add_i32 s0, s0, 8
	s_cmp_eq_u32 s33, 0
	s_cbranch_scc0 .LBB2_24
.LBB2_27:                               ; %._crit_edge104
	s_delay_alu instid0(VALU_DEP_1)
	v_frexp_mant_f64_e32 v[4:5], v[6:7]
	s_mov_b32 s1, 0x3fe55555
	s_mov_b32 s0, 0x55555555
	s_mov_b32 s4, 0x6b47b09a
	s_mov_b32 s6, 0xbf559e2b
	s_mov_b32 s5, 0x3fc38538
	s_mov_b32 s7, 0x3fc3ab76
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, s[0:1], v[4:5]
	s_mov_b32 s0, 0x55555780
	v_cndmask_b32_e64 v0, 0, 1, vcc_lo
	v_ldexp_f64 v[4:5], v[4:5], v0
	v_frexp_exp_i32_f64_e32 v0, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[8:9], v[4:5], 1.0
	v_add_f64 v[14:15], v[4:5], -1.0
	v_subrev_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo
	v_cmp_class_f64_e64 vcc_lo, v[6:7], 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[10:11], v[8:9]
	v_add_f64 v[16:17], v[8:9], -1.0
	v_add_f64 v[4:5], v[4:5], -v[16:17]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[12:13], v[10:11], v[10:11]
	v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[12:13], v[10:11], v[10:11]
	v_mul_f64 v[12:13], v[14:15], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[18:19], v[8:9], v[12:13]
	v_fma_f64 v[8:9], v[12:13], v[8:9], -v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[12:13], v[4:5], v[8:9]
	v_add_f64 v[8:9], v[18:19], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[14:15], -v[8:9]
	v_add_f64 v[18:19], v[8:9], -v[18:19]
	v_add_f64 v[14:15], v[14:15], -v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[18:19], -v[4:5]
	v_add_f64 v[8:9], v[14:15], -v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[4:5], v[8:9]
	v_add_f64 v[4:5], v[16:17], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[4:5], v[10:11], v[4:5]
	v_add_f64 v[8:9], v[12:13], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], v[8:9], v[8:9]
	v_fma_f64 v[14:15], v[10:11], s[6:7], s[4:5]
	s_mov_b32 s4, 0xd7f4df2e
	s_mov_b32 s5, 0x3fc7474d
	v_mul_f64 v[16:17], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[14:15], v[10:11], v[14:15], s[4:5]
	s_mov_b32 s4, 0x16291751
	s_mov_b32 s5, 0x3fcc71c0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[14:15], v[10:11], v[14:15], s[4:5]
	s_mov_b32 s4, 0x9b27acf1
	s_mov_b32 s5, 0x3fd24924
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[14:15], v[10:11], v[14:15], s[4:5]
	s_mov_b32 s4, 0x998ef7b6
	s_mov_b32 s5, 0x3fd99999
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[14:15], v[10:11], v[14:15], s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_fma_f64 v[10:11], v[10:11], v[14:15], s[0:1]
	v_ldexp_f64 v[14:15], v[8:9], 1
	v_add_f64 v[8:9], v[8:9], -v[12:13]
	s_mov_b32 s0, 0xfefa39ef
	s_mov_b32 s1, 0x3fe62e42
	v_mul_f64 v[10:11], v[16:17], v[10:11]
	v_cvt_f64_i32_e32 v[16:17], v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[4:5], v[4:5], -v[8:9]
	v_add_f64 v[12:13], v[14:15], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[18:19], v[16:17], s[0:1]
	v_ldexp_f64 v[4:5], v[4:5], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[8:9], v[12:13], -v[14:15]
	v_fma_f64 v[14:15], v[16:17], s[0:1], -v[18:19]
	s_mov_b32 s0, 0x3b39803f
	s_mov_b32 s1, 0x3c7abc9e
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[10:11], -v[8:9]
	v_fma_f64 v[10:11], v[16:17], s[0:1], v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], v[8:9]
	v_add_f64 v[8:9], v[18:19], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[14:15], v[12:13], v[4:5]
	v_add_f64 v[18:19], v[8:9], -v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[8:9], v[14:15]
	v_add_f64 v[12:13], v[14:15], -v[12:13]
	v_add_f64 v[10:11], v[10:11], -v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[16:17], -v[8:9]
	v_add_f64 v[4:5], v[4:5], -v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[22:23], v[16:17], -v[20:21]
	v_add_f64 v[12:13], v[14:15], -v[20:21]
	v_add_f64 v[14:15], v[10:11], v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[8:9], -v[22:23]
	v_add_f64 v[8:9], v[12:13], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[14:15], -v[10:11]
	v_add_f64 v[8:9], v[14:15], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[14:15], -v[12:13]
	v_add_f64 v[4:5], v[4:5], -v[12:13]
	v_add_f64 v[18:19], v[16:17], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[10:11], -v[14:15]
	v_add_f64 v[12:13], v[18:19], -v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], v[10:11]
	v_add_f64 v[8:9], v[8:9], -v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[4:5], v[8:9]
	v_add_f64 v[4:5], v[18:19], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v4, v6, vcc_lo
	v_cndmask_b32_e32 v4, v5, v7, vcc_lo
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v5, 0x7ff80000, v4, vcc_lo
	v_cmp_nge_f64_e32 vcc_lo, 0, v[6:7]
	v_cndmask_b32_e32 v4, 0, v0, vcc_lo
	v_cmp_neq_f64_e32 vcc_lo, 0, v[6:7]
	v_cndmask_b32_e32 v5, 0xfff00000, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[1:2], v[4:5]
	v_mov_b32_e32 v4, 0
	v_lshlrev_b64 v[2:3], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10kernel_lseiPdS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 29
		.amdhsa_next_free_sgpr 35
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z10kernel_lseiPdS_S_, .Lfunc_end2-_Z10kernel_lseiPdS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3252
; NumSgprs: 37
; NumVgprs: 29
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 37
; NumVGPRsForWavesPerEU: 29
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z16kernel_mvn_shareiiiPdS_iS_ ; -- Begin function _Z16kernel_mvn_shareiiiPdS_iS_
	.globl	_Z16kernel_mvn_shareiiiPdS_iS_
	.p2align	8
	.type	_Z16kernel_mvn_shareiiiPdS_iS_,@function
_Z16kernel_mvn_shareiiiPdS_iS_:         ; @_Z16kernel_mvn_shareiiiPdS_iS_
; %bb.0:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x3c
	v_bfe_u32 v3, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_add_i32 s2, s5, 1
	s_lshr_b32 s7, s12, 16
	s_mul_i32 s2, s2, s5
	v_mad_u64_u32 v[1:2], null, s15, s7, v[3:4]
	s_lshr_b32 s3, s2, 31
	s_and_b32 s12, s12, 0xffff
	s_add_i32 s3, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s3, s3, 1
	v_cmp_gt_i32_e64 s2, s4, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s13, s2
	s_cbranch_execz .LBB3_6
; %bb.1:                                ; %.preheader98
	s_add_i32 s14, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s15, s14, s12
	s_and_b32 vcc_lo, exec_lo, s15
	s_delay_alu instid0(VALU_DEP_1)
	v_readfirstlane_b32 s14, v2
	s_cbranch_vccnz .LBB3_6
; %bb.2:                                ; %.lr.ph
	v_cvt_f32_u32_e32 v2, s12
	s_sub_i32 s16, 0, s12
	v_mul_lo_u32 v4, s3, v3
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_rcp_iflag_f32_e32 v2, v2
	v_lshlrev_b32_e32 v7, 3, v0
	v_lshlrev_b32_e32 v4, 3, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_add3_u32 v7, 0, v4, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v2, v2
	v_readfirstlane_b32 s15, v2
	v_mul_lo_u32 v2, v1, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s16, s16, s15
	s_mul_hi_u32 s16, s15, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s15, s15, s16
	s_mul_hi_u32 s15, s14, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s16, s15, s12
	s_sub_i32 s14, s14, s16
	s_add_i32 s16, s15, 1
	s_sub_i32 s17, s14, s12
	s_cmp_ge_u32 s14, s12
	s_cselect_b32 s15, s16, s15
	s_cselect_b32 s14, s17, s14
	s_add_i32 s16, s15, 1
	s_cmp_ge_u32 s14, s12
	s_mov_b32 s14, 0
	s_cselect_b32 s15, s16, s15
	s_lshl_b32 s16, s12, 3
.LBB3_3:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u32_e64 s3, v6
	s_cbranch_execz .LBB3_5
; %bb.4:                                ;   in Loop: Header=BB3_3 Depth=1
	v_add_nc_u32_e32 v4, v2, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 3, v[4:5]
	v_add_co_u32 v8, vcc_lo, s8, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
	global_load_b64 v[8:9], v[8:9], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v7, v[8:9]
.LBB3_5:                                ;   in Loop: Header=BB3_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	v_add_nc_u32_e32 v7, s16, v7
	v_add_nc_u32_e32 v6, s12, v6
	s_add_i32 s14, s14, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_u32 s14, s15
	s_cbranch_scc1 .LBB3_3
.LBB3_6:                                ; %.loopexit99
	s_or_b32 exec_lo, exec_lo, s13
	s_mul_i32 s8, s12, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s13, s8, 31
	s_add_i32 s9, s8, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_xor_b32 s14, s9, s13
	s_load_b32 s9, s[0:1], 0x20
	v_cvt_f32_u32_e32 v2, s14
	s_sub_i32 s17, 0, s14
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s9, s9, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cvt_u32_f32_e32 v2, v2
	s_add_i32 s15, s9, s8
	s_add_i32 s15, s15, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s18, s15, 31
	v_readfirstlane_b32 s16, v2
	s_add_i32 s15, s15, s18
	s_xor_b32 s13, s18, s13
	s_xor_b32 s15, s15, s18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s17, s17, s16
	s_mul_hi_u32 s17, s16, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s16, s16, s17
	s_mul_hi_u32 s16, s15, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s17, s16, s14
	s_sub_i32 s15, s15, s17
	s_add_i32 s17, s16, 1
	s_sub_i32 s18, s15, s14
	s_cmp_ge_u32 s15, s14
	s_cselect_b32 s16, s17, s16
	s_cselect_b32 s15, s18, s15
	s_add_i32 s17, s16, 1
	s_cmp_ge_u32 s15, s14
	s_cselect_b32 s14, s17, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s14, s14, s13
	s_sub_i32 s14, s14, s13
	s_mul_i32 s13, s3, s7
	s_cmp_lt_i32 s14, 1
	s_cbranch_scc1 .LBB3_11
; %bb.7:                                ; %.lr.ph102.preheader
	v_mad_u32_u24 v4, v3, s12, v0
	s_lshl_b32 s7, s13, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v2, 3, v4
	v_add3_u32 v2, 0, s7, v2
	s_lshl_b32 s7, s8, 3
.LBB3_8:                                ; %.lr.ph102
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s12, exec_lo
	v_cmpx_gt_i32_e64 s9, v4
	s_cbranch_execz .LBB3_10
; %bb.9:                                ;   in Loop: Header=BB3_8 Depth=1
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 3, v[4:5]
	v_add_co_u32 v5, vcc_lo, s10, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	global_load_b64 v[5:6], v[5:6], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v2, v[5:6]
.LBB3_10:                               ;   in Loop: Header=BB3_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	v_add_nc_u32_e32 v2, s7, v2
	v_add_nc_u32_e32 v4, s8, v4
	s_add_i32 s14, s14, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc0 .LBB3_8
.LBB3_11:                               ; %._crit_edge
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s7, s2
	s_cbranch_execz .LBB3_24
; %bb.12:                               ; %.preheader
	s_cmp_lt_i32 s5, 1
	s_cbranch_scc1 .LBB3_20
; %bb.13:                               ; %.lr.ph113
	v_mul_lo_u32 v2, v0, s5
	v_mul_lo_u32 v3, s3, v3
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	s_lshl_b32 s2, s13, 3
	s_mov_b32 s3, 8
	s_mov_b32 s8, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b32_e32 v2, 3, v2
	v_lshl_add_u32 v10, v3, 3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add3_u32 v11, 0, s2, v2
	v_mov_b32_e32 v2, v4
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v3, v5
	s_mov_b32 s2, 0
.LBB3_14:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_16 Depth 2
	s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
	v_lshl_add_u32 v6, s2, 3, v11
	s_cmp_eq_u32 s2, 0
	ds_load_b64 v[6:7], v6
	s_cbranch_scc1 .LBB3_18
; %bb.15:                               ; %.lr.ph107.preheader
                                        ;   in Loop: Header=BB3_14 Depth=1
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v13, v12
	v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v14, v11
	s_mov_b32 s9, 0
.LBB3_16:                               ; %.lr.ph107
                                        ;   Parent Loop BB3_14 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ds_load_b64 v[15:16], v14
	ds_load_b64 v[17:18], v13
	v_add_nc_u32_e32 v14, 8, v14
	v_add_nc_u32_e32 v13, 8, v13
	s_add_i32 s9, s9, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s9, s2
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[8:9], v[15:16], v[17:18], v[8:9]
	s_cbranch_scc0 .LBB3_16
; %bb.17:                               ; %._crit_edge108.loopexit
                                        ;   in Loop: Header=BB3_14 Depth=1
	s_add_i32 s8, s8, s2
	s_branch .LBB3_19
.LBB3_18:                               ;   in Loop: Header=BB3_14 Depth=1
	v_dual_mov_b32 v9, v5 :: v_dual_mov_b32 v8, v4
.LBB3_19:                               ; %._crit_edge108
                                        ;   in Loop: Header=BB3_14 Depth=1
	v_lshl_add_u32 v13, s8, 3, v10
	v_add_nc_u32_e32 v12, s3, v12
	s_add_i32 s2, s2, 1
	s_add_i32 s8, s8, 1
	s_add_i32 s3, s3, 8
	ds_load_b64 v[13:14], v13
	s_cmp_eq_u32 s2, s5
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[8:9], v[6:7], v[13:14], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[2:3], v[6:7], v[8:9], v[2:3]
	s_cbranch_scc0 .LBB3_14
	s_branch .LBB3_21
.LBB3_20:
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
.LBB3_21:                               ; %._crit_edge114
	s_cmp_lt_i32 s6, 1
	s_cbranch_scc1 .LBB3_24
; %bb.22:                               ; %.lr.ph118.preheader
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v0, s4, v[1:2]
	s_load_b64 s[0:1], s[0:1], 0x28
	v_mul_lo_u32 v0, v4, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
.LBB3_23:                               ; %.lr.ph118
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[4:5], v[0:1], off
	s_add_i32 s6, s6, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s6, 0
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[4:5], -v[2:3]
	global_store_b64 v[0:1], v[4:5], off
	v_add_co_u32 v0, vcc_lo, v0, 8
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_cbranch_scc1 .LBB3_23
.LBB3_24:                               ; %Flow174
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16kernel_mvn_shareiiiPdS_iS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z16kernel_mvn_shareiiiPdS_iS_, .Lfunc_end3-_Z16kernel_mvn_shareiiiPdS_iS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1172
; NumSgprs: 21
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z20kernel_share_add_cstiiPdS_ ; -- Begin function _Z20kernel_share_add_cstiiPdS_
	.globl	_Z20kernel_share_add_cstiiPdS_
	.p2align	8
	.type	_Z20kernel_share_add_cstiiPdS_,@function
_Z20kernel_share_add_cstiiPdS_:         ; @_Z20kernel_share_add_cstiiPdS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s6, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s7, s2, 0xffff
	s_add_i32 s2, s6, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v1, s2, s2, s7
	s_and_b32 vcc_lo, exec_lo, s2
	s_delay_alu instid0(VALU_DEP_1)
	v_readfirstlane_b32 s8, v1
	s_cbranch_vccnz .LBB4_5
; %bb.1:                                ; %.lr.ph
	v_cvt_f32_u32_e32 v1, s7
	s_load_b128 s[0:3], s[0:1], 0x8
	s_mul_i32 s4, s15, s6
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_lshl_b64 s[10:11], s[4:5], 3
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s2, s10
	s_addc_u32 s3, s3, s11
	s_sub_i32 s9, 0, s7
	v_readfirstlane_b32 s4, v1
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s9, s9, s4
	s_mul_hi_u32 s9, s4, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s4, s4, s9
	s_mul_hi_u32 s4, s8, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s9, s4, s7
	s_sub_i32 s8, s8, s9
	s_add_i32 s9, s4, 1
	s_sub_i32 s10, s8, s7
	s_cmp_ge_u32 s8, s7
	s_cselect_b32 s4, s9, s4
	s_cselect_b32 s8, s10, s8
	s_add_i32 s9, s4, 1
	s_cmp_ge_u32 s8, s7
	s_cselect_b32 s4, s9, s4
.LBB4_2:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s8, exec_lo
	v_cmpx_gt_u32_e64 s6, v0
	s_cbranch_execz .LBB4_4
; %bb.3:                                ;   in Loop: Header=BB4_2 Depth=1
	v_lshlrev_b64 v[2:3], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	global_load_b64 v[6:7], v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[6:7], -v[4:5]
	global_store_b64 v[2:3], v[4:5], off
.LBB4_4:                                ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v0, s7, v0
	s_add_i32 s5, s5, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s5, s4
	s_cbranch_scc0 .LBB4_2
.LBB4_5:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20kernel_share_add_cstiiPdS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z20kernel_share_add_cstiiPdS_, .Lfunc_end4-_Z20kernel_share_add_cstiiPdS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 328
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z14kernel_vecdot2iiiPdS_S_ ; -- Begin function _Z14kernel_vecdot2iiiPdS_S_
	.globl	_Z14kernel_vecdot2iiiPdS_S_
	.p2align	8
	.type	_Z14kernel_vecdot2iiiPdS_S_,@function
_Z14kernel_vecdot2iiiPdS_S_:            ; @_Z14kernel_vecdot2iiiPdS_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v5, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s13, s2, 16
	s_and_b32 s12, s2, 0xffff
	s_mul_i32 s5, s6, s5
	s_mul_i32 s14, s12, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s16, s14, 31
	s_add_i32 s2, s14, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s17, s2, s16
	s_add_i32 s2, s5, s14
	v_cvt_f32_u32_e32 v1, s17
	s_add_i32 s2, s2, -1
	s_sub_i32 s7, 0, s17
	s_ashr_i32 s18, s2, 31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_add_i32 s2, s2, s18
	s_xor_b32 s19, s2, s18
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s3, v1
	v_bfe_u32 v1, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s7, s7, s3
	s_mul_hi_u32 s7, s3, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s3, s7
	s_mul_hi_u32 s7, s19, s3
	s_load_b64 s[2:3], s[0:1], 0x20
	s_mul_i32 s0, s7, s17
	s_xor_b32 s1, s18, s16
	s_sub_i32 s0, s19, s0
	s_add_i32 s16, s7, 1
	s_sub_i32 s18, s0, s17
	s_cmp_ge_u32 s0, s17
	s_cselect_b32 s7, s16, s7
	s_cselect_b32 s0, s18, s0
	s_add_i32 s16, s7, 1
	s_cmp_ge_u32 s0, s17
	s_cselect_b32 s0, s16, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s0, s0, s1
	s_sub_i32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s0, 1
	s_cbranch_scc1 .LBB5_5
; %bb.1:                                ; %.lr.ph.preheader
	v_mad_u32_u24 v2, v1, s12, v5
	s_lshl_b32 s1, s14, 3
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v0, v2, 3, 0
.LBB5_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_i32_e64 s5, v2
	s_cbranch_execz .LBB5_4
; %bb.3:                                ;   in Loop: Header=BB5_2 Depth=1
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[2:3]
	v_add_co_u32 v3, vcc_lo, s10, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v0, v[3:4]
.LBB5_4:                                ;   in Loop: Header=BB5_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_add_nc_u32_e32 v0, s1, v0
	v_add_nc_u32_e32 v2, s14, v2
	s_add_i32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 0
	s_cbranch_scc0 .LBB5_2
.LBB5_5:                                ; %._crit_edge
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s15, s13, v[1:2]
	s_lshl_b32 s1, s5, 3
	s_add_i32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s0, s4, v2
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB5_11
; %bb.6:                                ; %.preheader
	s_add_i32 s7, s6, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, s10, s7, s12
	s_and_b32 vcc_lo, exec_lo, s10
	s_delay_alu instid0(VALU_DEP_1)
	v_readfirstlane_b32 s7, v0
	s_cbranch_vccnz .LBB5_11
; %bb.7:                                ; %.lr.ph74
	v_cvt_f32_u32_e32 v0, s12
	s_sub_i32 s11, 0, s12
	v_mul_lo_u32 v3, v1, s6
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v6, v5
	v_rcp_iflag_f32_e32 v0, v0
	v_lshlrev_b32_e32 v7, 3, v5
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v0, 0x4f7ffffe, v0 :: v_dual_lshlrev_b32 v3, 3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v7, s1, v3, v7
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s10, v0
	v_mul_lo_u32 v0, v2, s6
	s_mul_i32 s11, s11, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s11, s10, s11
	s_add_i32 s10, s10, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s10, s7, s10
	s_mul_i32 s11, s10, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s7, s7, s11
	s_add_i32 s11, s10, 1
	s_sub_i32 s13, s7, s12
	s_cmp_ge_u32 s7, s12
	s_cselect_b32 s10, s11, s10
	s_cselect_b32 s7, s13, s7
	s_add_i32 s11, s10, 1
	s_cmp_ge_u32 s7, s12
	s_mov_b32 s7, 0
	s_cselect_b32 s10, s11, s10
	s_lshl_b32 s11, s12, 3
.LBB5_8:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s13, exec_lo
	v_cmpx_gt_u32_e64 s6, v6
	s_cbranch_execz .LBB5_10
; %bb.9:                                ;   in Loop: Header=BB5_8 Depth=1
	v_add_nc_u32_e32 v3, v0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 3, v[3:4]
	v_add_co_u32 v8, vcc_lo, s8, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
	global_load_b64 v[8:9], v[8:9], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v7, v[8:9]
.LBB5_10:                               ;   in Loop: Header=BB5_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	v_add_nc_u32_e32 v7, s11, v7
	v_add_nc_u32_e32 v6, s12, v6
	s_add_i32 s7, s7, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_u32 s7, s10
	s_cbranch_scc1 .LBB5_8
.LBB5_11:                               ; %.loopexit
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB5_17
; %bb.12:
	s_cmp_lt_i32 s6, 1
	s_cbranch_scc1 .LBB5_15
; %bb.13:                               ; %.lr.ph78.preheader
	v_mul_lo_u32 v3, v5, s6
	v_mul_lo_u32 v4, v1, s6
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshl_add_u32 v3, v3, 3, 0
	v_lshl_add_u32 v4, v4, 3, s1
.LBB5_14:                               ; %.lr.ph78
                                        ; =>This Inner Loop Header: Depth=1
	ds_load_b64 v[6:7], v3
	ds_load_b64 v[8:9], v4
	v_add_nc_u32_e32 v3, 8, v3
	v_add_nc_u32_e32 v4, 8, v4
	s_add_i32 s6, s6, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s6, 0
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[0:1], v[6:7], v[8:9], v[0:1]
	s_cbranch_scc0 .LBB5_14
	s_branch .LBB5_16
.LBB5_15:
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
.LBB5_16:                               ; %Flow114
	v_mad_u64_u32 v[3:4], null, v5, s4, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[2:3], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	global_load_b64 v[4:5], v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[0:1], v[4:5]
	global_store_b64 v[2:3], v[0:1], off
.LBB5_17:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14kernel_vecdot2iiiPdS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z14kernel_vecdot2iiiPdS_S_, .Lfunc_end5-_Z14kernel_vecdot2iiiPdS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 908
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z10kernel_mvniiPdS_S_S_iS_ ; -- Begin function _Z10kernel_mvniiPdS_S_S_iS_
	.globl	_Z10kernel_mvniiPdS_S_S_iS_
	.p2align	8
	.type	_Z10kernel_mvniiPdS_S_S_iS_,@function
_Z10kernel_mvniiPdS_S_S_iS_:            ; @_Z10kernel_mvniiPdS_S_S_iS_
; %bb.0:
	s_clause 0x2
	s_load_b64 s[12:13], s[0:1], 0x0
	s_load_b32 s2, s[0:1], 0x44
	s_load_b256 s[4:11], s[0:1], 0x8
	v_bfe_u32 v3, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_add_i32 s3, s13, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_mul_i32 s14, s3, s13
	s_lshr_b32 s3, s2, 16
	s_lshr_b32 s16, s14, 31
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_add_i32 s14, s14, s16
	s_ashr_i32 s15, s14, 1
	s_mul_i32 s14, s3, s13
	s_mul_i32 s16, s15, s3
	s_lshl_b32 s17, s14, 3
	s_lshl_b32 s14, s16, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s12, v1
	s_add_i32 s14, s14, 0
	s_add_i32 s16, s14, s17
	s_and_b32 s17, s2, 0xffff
	s_and_saveexec_b32 s18, vcc_lo
	s_cbranch_execz .LBB6_13
; %bb.1:                                ; %.preheader121
	v_cvt_f32_u32_e32 v2, s17
	s_sub_i32 s2, 0, s17
	s_add_i32 s20, s17, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s19, v2
	s_mul_i32 s2, s2, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_hi_u32 s21, s19, s2
	s_add_i32 s2, s20, s15
	s_add_i32 s19, s19, s21
	s_cmp_lt_u32 s2, s17
	s_cbranch_scc1 .LBB6_6
; %bb.2:                                ; %.lr.ph
	v_mul_lo_u32 v2, s15, v3
	s_mul_hi_u32 s21, s2, s19
	v_lshlrev_b32_e32 v4, 3, v0
	s_mul_i32 s22, s21, s17
	v_mov_b32_e32 v7, v0
	s_sub_i32 s2, s2, s22
	s_add_i32 s22, s21, 1
	s_sub_i32 s23, s2, s17
	v_lshlrev_b32_e32 v5, 3, v2
	s_cmp_ge_u32 s2, s17
	v_mul_lo_u32 v2, v1, s15
	s_cselect_b32 s21, s22, s21
	s_cselect_b32 s2, s23, s2
	s_add_i32 s22, s21, 1
	v_add3_u32 v6, 0, v5, v4
	v_mov_b32_e32 v5, 0
	s_cmp_ge_u32 s2, s17
	s_cselect_b32 s21, s22, s21
	s_mov_b32 s22, 0
	s_lshl_b32 s23, s17, 3
.LBB6_3:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s24, exec_lo
	v_cmpx_gt_u32_e64 s15, v7
	s_cbranch_execz .LBB6_5
; %bb.4:                                ;   in Loop: Header=BB6_3 Depth=1
	v_add_nc_u32_e32 v4, v2, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 3, v[4:5]
	v_add_co_u32 v8, s2, s4, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s2, s5, v9, s2
	global_load_b64 v[8:9], v[8:9], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v6, v[8:9]
.LBB6_5:                                ;   in Loop: Header=BB6_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s24
	v_add_nc_u32_e32 v6, s23, v6
	v_add_nc_u32_e32 v7, s17, v7
	s_add_i32 s22, s22, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s22, s21
	s_cbranch_scc0 .LBB6_3
.LBB6_6:                                ; %.preheader
	s_add_i32 s20, s20, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_u32 s20, s17
	s_cbranch_scc1 .LBB6_11
; %bb.7:                                ; %.lr.ph124
	v_mul_lo_u32 v2, v3, s13
	s_mul_hi_u32 s2, s20, s19
	v_lshlrev_b32_e32 v4, 3, v0
	s_mul_i32 s4, s2, s17
	s_add_i32 s5, s2, 1
	s_sub_i32 s4, s20, s4
	v_mov_b32_e32 v7, v0
	s_sub_i32 s19, s4, s17
	v_lshlrev_b32_e32 v5, 3, v2
	s_cmp_ge_u32 s4, s17
	v_mul_lo_u32 v2, v1, s13
	s_cselect_b32 s2, s5, s2
	s_cselect_b32 s4, s19, s4
	s_add_i32 s5, s2, 1
	v_add3_u32 v6, s14, v5, v4
	v_mov_b32_e32 v5, 0
	s_cmp_ge_u32 s4, s17
	s_mov_b32 s19, 0
	s_cselect_b32 s4, s5, s2
	s_lshl_b32 s5, s17, 3
.LBB6_8:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s20, exec_lo
	v_cmpx_gt_u32_e64 s13, v7
	s_cbranch_execz .LBB6_10
; %bb.9:                                ;   in Loop: Header=BB6_8 Depth=1
	v_add_nc_u32_e32 v4, v2, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 3, v[4:5]
	v_add_co_u32 v8, s2, s6, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s2, s7, v9, s2
	global_load_b64 v[8:9], v[8:9], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v6, v[8:9]
.LBB6_10:                               ;   in Loop: Header=BB6_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
	v_add_nc_u32_e32 v6, s5, v6
	v_add_nc_u32_e32 v7, s17, v7
	s_add_i32 s19, s19, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s19, s4
	s_cbranch_scc0 .LBB6_8
.LBB6_11:                               ; %._crit_edge
	v_cmp_eq_u32_e64 s2, 0, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB6_13
; %bb.12:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 3, v[1:2]
	v_lshl_add_u32 v2, v3, 3, s16
	v_add_co_u32 v4, s2, s8, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v5, s2, s9, v5, s2
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v2, v[4:5]
.LBB6_13:                               ; %Flow205
	s_or_b32 exec_lo, exec_lo, s18
	s_mul_i32 s4, s17, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s2, s4, 31
	s_add_i32 s5, s4, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_xor_b32 s6, s5, s2
	s_load_b32 s5, s[0:1], 0x28
	v_cvt_f32_u32_e32 v2, s6
	s_sub_i32 s9, 0, s6
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s5, s5, s13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cvt_u32_f32_e32 v2, v2
	s_add_i32 s7, s5, s4
	s_add_i32 s7, s7, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s18, s7, 31
	v_readfirstlane_b32 s8, v2
	s_add_i32 s7, s7, s18
	s_xor_b32 s2, s18, s2
	s_xor_b32 s7, s7, s18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s9, s9, s8
	s_mul_hi_u32 s9, s8, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s8, s8, s9
	s_mul_hi_u32 s8, s7, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s9, s8, s6
	s_sub_i32 s7, s7, s9
	s_add_i32 s9, s8, 1
	s_sub_i32 s18, s7, s6
	s_cmp_ge_u32 s7, s6
	s_cselect_b32 s8, s9, s8
	s_cselect_b32 s7, s18, s7
	s_add_i32 s9, s8, 1
	s_cmp_ge_u32 s7, s6
	s_cselect_b32 s6, s9, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s6, s6, s2
	s_sub_i32 s6, s6, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s6, 1
	s_cbranch_scc1 .LBB6_18
; %bb.14:                               ; %.lr.ph129.preheader
	v_mad_u32_u24 v4, v3, s17, v0
	s_lshl_b32 s2, s15, 3
	s_lshl_b32 s7, s13, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s2, s2, s7
	v_lshlrev_b32_e32 v2, 3, v4
	s_add_i32 s2, s2, 8
	s_lshl_b32 s7, s4, 3
	s_mul_i32 s2, s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add3_u32 v2, 0, s2, v2
.LBB6_15:                               ; %.lr.ph129
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s8, exec_lo
	v_cmpx_gt_i32_e64 s5, v4
	s_cbranch_execz .LBB6_17
; %bb.16:                               ;   in Loop: Header=BB6_15 Depth=1
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 3, v[4:5]
	v_add_co_u32 v5, s2, s10, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v6, s2, s11, v6, s2
	global_load_b64 v[5:6], v[5:6], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v2, v[5:6]
.LBB6_17:                               ;   in Loop: Header=BB6_15 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, s7, v2
	v_add_nc_u32_e32 v4, s4, v4
	s_add_i32 s6, s6, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s6, 0
	s_cbranch_scc0 .LBB6_15
.LBB6_18:                               ; %._crit_edge130
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB6_25
; %bb.19:
	v_lshl_add_u32 v2, v3, 3, s16
	s_cmp_lt_i32 s13, 1
	s_mov_b32 s4, 1
	ds_load_b64 v[4:5], v2
	s_cbranch_scc1 .LBB6_24
; %bb.20:                               ; %.lr.ph138
	v_mul_lo_u32 v2, v0, s13
	v_mul_lo_u32 v6, s15, v3
	v_mul_lo_u32 v3, v3, s13
	s_lshl_b32 s3, s3, 3
	s_mov_b32 s5, 8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v2, 3, v2
	v_lshl_add_u32 v8, v6, 3, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v10, v3, 3, s14
	v_add3_u32 v9, s16, s3, v2
	s_mov_b32 s3, 0
.LBB6_21:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB6_22 Depth 2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_lshl_add_u32 v2, s3, 3, v9
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v11, v8
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v12, v9
	ds_load_b64 v[2:3], v2
	s_mov_b32 s6, s4
.LBB6_22:                               ;   Parent Loop BB6_21 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ds_load_b64 v[13:14], v12
	ds_load_b64 v[15:16], v11
	v_add_nc_u32_e32 v12, 8, v12
	v_add_nc_u32_e32 v11, 8, v11
	s_add_i32 s6, s6, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s6, 0
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[6:7], v[13:14], v[15:16], v[6:7]
	s_cbranch_scc0 .LBB6_22
; %bb.23:                               ;   in Loop: Header=BB6_21 Depth=1
	v_lshl_add_u32 v11, s3, 3, v10
	v_add_nc_u32_e32 v8, s5, v8
	s_add_i32 s3, s3, 1
	s_add_i32 s4, s4, 1
	s_add_i32 s5, s5, 8
	ds_load_b64 v[11:12], v11
	s_cmp_eq_u32 s3, s13
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[6:7], v[6:7], -v[11:12]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[4:5], v[2:3], v[6:7], v[4:5]
	s_cbranch_scc0 .LBB6_21
.LBB6_24:                               ; %._crit_edge139
	s_load_b64 s[0:1], s[0:1], 0x30
	v_mad_u64_u32 v[2:3], null, v0, s12, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v5, 0x80000000, v5
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[2:3]
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[4:5], off
.LBB6_25:                               ; %Flow197
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10kernel_mvniiPdS_S_S_iS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 25
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z10kernel_mvniiPdS_S_S_iS_, .Lfunc_end6-_Z10kernel_mvniiPdS_S_S_iS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1416
; NumSgprs: 27
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 27
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z15kernel_diag_mvniiPdS_S_S_iS_ ; -- Begin function _Z15kernel_diag_mvniiPdS_S_S_iS_
	.globl	_Z15kernel_diag_mvniiPdS_S_S_iS_
	.p2align	8
	.type	_Z15kernel_diag_mvniiPdS_S_S_iS_,@function
_Z15kernel_diag_mvniiPdS_S_S_iS_:       ; @_Z15kernel_diag_mvniiPdS_S_S_iS_
; %bb.0:
	s_clause 0x2
	s_load_b32 s16, s[0:1], 0x44
	s_load_b64 s[12:13], s[0:1], 0x0
	s_load_b256 s[4:11], s[0:1], 0x8
	v_bfe_u32 v3, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s14, s16, 16
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s14, v[3:4]
	s_mul_i32 s2, s14, s13
	s_and_b32 s15, s16, 0xffff
	s_lshl_b32 s3, s2, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s17, s3, 0
	s_add_i32 s3, s17, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s12, v1
	s_and_saveexec_b32 s16, s2
	s_cbranch_execz .LBB7_12
; %bb.1:                                ; %.preheader107
	s_add_i32 s18, s13, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s19, s18, s15
	s_and_b32 vcc_lo, exec_lo, s19
	s_delay_alu instid0(VALU_DEP_1)
	v_readfirstlane_b32 s18, v2
	s_cbranch_vccnz .LBB7_10
; %bb.2:                                ; %.lr.ph
	v_cvt_f32_u32_e32 v2, s15
	s_sub_i32 s20, 0, s15
	v_mul_lo_u32 v4, v3, s13
	v_lshlrev_b32_e32 v6, 3, v0
	v_mov_b32_e32 v8, v0
	v_rcp_iflag_f32_e32 v2, v2
	v_mov_b32_e32 v5, 0
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v2, 0x4f7ffffe, v2 :: v_dual_lshlrev_b32 v7, 3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v9, 0, v7, v6
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s19, v2
	v_mul_lo_u32 v2, v1, s13
	s_mul_i32 s20, s20, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s20, s19, s20
	s_add_i32 s19, s19, s20
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s19, s18, s19
	s_mul_i32 s20, s19, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s18, s18, s20
	s_add_i32 s20, s19, 1
	s_sub_i32 s21, s18, s15
	s_cmp_ge_u32 s18, s15
	s_cselect_b32 s19, s20, s19
	s_cselect_b32 s18, s21, s18
	s_add_i32 s21, s19, 1
	s_cmp_ge_u32 s18, s15
	s_mov_b32 s20, 0
	s_cselect_b32 s18, s21, s19
	s_lshl_b32 s19, s15, 3
.LBB7_3:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s21, exec_lo
	v_cmpx_gt_u32_e64 s13, v8
	s_cbranch_execz .LBB7_5
; %bb.4:                                ;   in Loop: Header=BB7_3 Depth=1
	v_add_nc_u32_e32 v4, v2, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 3, v[4:5]
	v_add_co_u32 v10, vcc_lo, s4, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
	global_load_b64 v[10:11], v[10:11], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v9, v[10:11]
.LBB7_5:                                ;   in Loop: Header=BB7_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	v_add_nc_u32_e32 v9, s19, v9
	v_add_nc_u32_e32 v8, s15, v8
	s_add_i32 s20, s20, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s20, s18
	s_cbranch_scc0 .LBB7_3
; %bb.6:                                ; %.preheader106
	v_add3_u32 v6, s17, v7, v6
	v_mov_b32_e32 v5, 0
	v_mov_b32_e32 v7, v0
	s_mov_b32 s4, 0
.LBB7_7:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s13, v7
	s_cbranch_execz .LBB7_9
; %bb.8:                                ;   in Loop: Header=BB7_7 Depth=1
	v_add_nc_u32_e32 v4, v2, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 3, v[4:5]
	v_add_co_u32 v8, vcc_lo, s6, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
	global_load_b64 v[8:9], v[8:9], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v6, v[8:9]
.LBB7_9:                                ;   in Loop: Header=BB7_7 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v6, s19, v6
	v_add_nc_u32_e32 v7, s15, v7
	s_add_i32 s4, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s4, s18
	s_cbranch_scc0 .LBB7_7
.LBB7_10:                               ; %._crit_edge
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB7_12
; %bb.11:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 3, v[1:2]
	v_lshl_add_u32 v2, v3, 3, s3
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v2, v[4:5]
.LBB7_12:                               ; %Flow175
	s_or_b32 exec_lo, exec_lo, s16
	s_mul_i32 s4, s15, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s6, s4, 31
	s_add_i32 s5, s4, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_xor_b32 s7, s5, s6
	s_load_b32 s5, s[0:1], 0x28
	v_cvt_f32_u32_e32 v2, s7
	s_sub_i32 s16, 0, s7
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s5, s5, s13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cvt_u32_f32_e32 v2, v2
	s_add_i32 s8, s5, s4
	s_add_i32 s8, s8, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s17, s8, 31
	v_readfirstlane_b32 s9, v2
	s_add_i32 s8, s8, s17
	s_xor_b32 s6, s17, s6
	s_xor_b32 s8, s8, s17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s16, s16, s9
	s_mul_hi_u32 s16, s9, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s9, s9, s16
	s_mul_hi_u32 s9, s8, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s16, s9, s7
	s_sub_i32 s8, s8, s16
	s_add_i32 s16, s9, 1
	s_sub_i32 s17, s8, s7
	s_cmp_ge_u32 s8, s7
	s_cselect_b32 s9, s16, s9
	s_cselect_b32 s8, s17, s8
	s_add_i32 s16, s9, 1
	s_cmp_ge_u32 s8, s7
	s_cselect_b32 s7, s16, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s7, s7, s6
	s_sub_i32 s6, s7, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s6, 1
	s_cbranch_scc1 .LBB7_17
; %bb.13:                               ; %.lr.ph115.preheader
	v_mad_u32_u24 v4, v3, s15, v0
	s_lshl_b32 s7, s13, 4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s7, s7, 8
	s_mul_i32 s7, s7, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v2, 3, v4
	v_add3_u32 v2, 0, s7, v2
	s_lshl_b32 s7, s4, 3
.LBB7_14:                               ; %.lr.ph115
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s8, exec_lo
	v_cmpx_gt_i32_e64 s5, v4
	s_cbranch_execz .LBB7_16
; %bb.15:                               ;   in Loop: Header=BB7_14 Depth=1
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 3, v[4:5]
	v_add_co_u32 v5, vcc_lo, s10, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	global_load_b64 v[5:6], v[5:6], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v2, v[5:6]
.LBB7_16:                               ;   in Loop: Header=BB7_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, s7, v2
	v_add_nc_u32_e32 v4, s4, v4
	s_add_i32 s6, s6, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s6, 0
	s_cbranch_scc0 .LBB7_14
.LBB7_17:                               ; %._crit_edge116
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s4, s2
	s_cbranch_execz .LBB7_24
; %bb.18:                               ; %.preheader
	s_cmp_lt_i32 s13, 1
	s_cbranch_scc1 .LBB7_22
; %bb.19:                               ; %.lr.ph119
	v_mul_lo_u32 v2, v0, s13
	s_lshl_b32 s5, s14, 3
	v_mul_lo_u32 v7, v3, s13
	v_lshl_add_u32 v6, v3, 3, s5
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[4:5], null, s13, v6, s[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v2, 3, v2
	v_mov_b32_e32 v6, 0
	v_lshl_add_u32 v7, v7, 3, 0
	v_add3_u32 v2, s3, s5, v2
.LBB7_20:                               ; =>This Inner Loop Header: Depth=1
	ds_load_b64 v[8:9], v2
	ds_load_b64 v[10:11], v4
	v_add_nc_u32_e32 v4, 8, v4
	v_add_nc_u32_e32 v2, 8, v2
	s_add_i32 s13, s13, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s13, 0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[8:9], v[8:9], -v[10:11]
	ds_load_b64 v[10:11], v7
	v_add_nc_u32_e32 v7, 8, v7
	v_mul_f64 v[8:9], v[8:9], v[8:9]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[5:6], v[10:11], v[8:9], v[5:6]
	s_cbranch_scc0 .LBB7_20
; %bb.21:                               ; %._crit_edge120.loopexit
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[4:5], v[5:6], 0.5
	s_branch .LBB7_23
.LBB7_22:
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
.LBB7_23:                               ; %._crit_edge120
	v_lshl_add_u32 v2, v3, 3, s3
	s_load_b64 s[0:1], s[0:1], 0x30
	ds_load_b64 v[2:3], v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[4:5], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, v0, s12, v[1:2]
	v_xor_b32_e32 v3, 0x80000000, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[0:1], 3, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB7_24:                               ; %Flow169
	s_or_b32 exec_lo, exec_lo, s4
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15kernel_diag_mvniiPdS_S_S_iS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z15kernel_diag_mvniiPdS_S_S_iS_, .Lfunc_end7-_Z15kernel_diag_mvniiPdS_S_S_iS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1268
; NumSgprs: 24
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
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...

	.end_amdgpu_metadata
