__global__
void nekbone(double *w, double *u, double *g, double *d, const int N) {
  const int e_size = N * N * N;
  const int e_offset = e_size * blockIdx.x;

  __shared__ double ur[1024];
  __shared__ double us[1024];
  __shared__ double ut[1024];
  __shared__ double ul[1024];
  __shared__ double d_s[128];

  for (int it = threadIdx.x; it < e_size; it += blockDim.x) {
    ul[it] = u[e_offset + it];
  }
  
  if (threadIdx.x < 128) {
    d_s[threadIdx.x] = d[threadIdx.x];
  }

  __syncthreads();

  int i, j, k;
  for (int it = threadIdx.x; it < e_size; it += blockDim.x) {
    j = it / N;
    i = it - j * N;
    k = j / N;
    j -= k * N;
    double wr = 0.0;
    double ws = 0.0;
    double wt = 0.0;
    for (int n = 0; n < N; ++n) {
      wr += d_s[n * N + i] * ul[N * (j + k * N) + n];
      ws += d_s[n * N + j] * ul[N * (n + k * N) + i];
      wt += d_s[n * N + k] * ul[N * (j + n * N) + i];
    }
    int g_offset = 6 * (e_offset + it);
    ur[it] = g[g_offset + 0] * wr + g[g_offset + 1] * ws + g[g_offset + 2] * wt;
    us[it] = g[g_offset + 1] * wr + g[g_offset + 3] * ws + g[g_offset + 4] * wt;
    ut[it] = g[g_offset + 2] * wr + g[g_offset + 4] * ws + g[g_offset + 5] * wt;
  }

  __syncthreads();

  for (int it = threadIdx.x; it < e_size; it += blockDim.x) {
    j = it / N;
    i = it - j * N;
    k = j / N;
    j -= k * N;
    double s = 0.0;
    for (int n = 0; n < N; ++n) {
      s += d_s[i * N + n] * ur[N * (j + N * k) + n] +
        d_s[j * N + n] * us[N * (n + N * k) + i] +
        d_s[k * N + n] * ut[N * (j + N * n) + i];
    }
    w[e_offset + it] = s;
  }
}


	.file	"tmpxft_002f5452_00000000-6_cuda2.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z33__device_stub__Z7nekbonePdS_S_S_iPdS_S_S_i
	.type	_Z33__device_stub__Z7nekbonePdS_S_S_iPdS_S_S_i, @function
_Z33__device_stub__Z7nekbonePdS_S_S_iPdS_S_S_i:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z7nekbonePdS_S_S_i(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z33__device_stub__Z7nekbonePdS_S_S_iPdS_S_S_i, .-_Z33__device_stub__Z7nekbonePdS_S_S_iPdS_S_S_i
	.globl	_Z7nekbonePdS_S_S_i
	.type	_Z7nekbonePdS_S_S_i, @function
_Z7nekbonePdS_S_S_i:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z7nekbonePdS_S_S_iPdS_S_S_i
	.cfi_endproc
.LFE2033:
	.size	_Z7nekbonePdS_S_S_i, .-_Z7nekbonePdS_S_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z7nekbonePdS_S_S_i"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7nekbonePdS_S_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
__global__
void nekbone(double *w, double *u, double *g, double *d, const int N) {
  const int e_size = N * N * N;
  const int e_offset = e_size * blockIdx.x;

  __shared__ double ur[1024];
  __shared__ double us[1024];
  __shared__ double ut[1024];
  __shared__ double ul[1024];
  __shared__ double d_s[128];

  for (int it = threadIdx.x; it < e_size; it += blockDim.x) {
    ul[it] = u[e_offset + it];
  }
  
  if (threadIdx.x < 128) {
    d_s[threadIdx.x] = d[threadIdx.x];
  }

  __syncthreads();

  int i, j, k;
  for (int it = threadIdx.x; it < e_size; it += blockDim.x) {
    j = it / N;
    i = it - j * N;
    k = j / N;
    j -= k * N;
    double wr = 0.0;
    double ws = 0.0;
    double wt = 0.0;
    for (int n = 0; n < N; ++n) {
      wr += d_s[n * N + i] * ul[N * (j + k * N) + n];
      ws += d_s[n * N + j] * ul[N * (n + k * N) + i];
      wt += d_s[n * N + k] * ul[N * (j + n * N) + i];
    }
    int g_offset = 6 * (e_offset + it);
    ur[it] = g[g_offset + 0] * wr + g[g_offset + 1] * ws + g[g_offset + 2] * wt;
    us[it] = g[g_offset + 1] * wr + g[g_offset + 3] * ws + g[g_offset + 4] * wt;
    ut[it] = g[g_offset + 2] * wr + g[g_offset + 4] * ws + g[g_offset + 5] * wt;
  }

  __syncthreads();

  for (int it = threadIdx.x; it < e_size; it += blockDim.x) {
    j = it / N;
    i = it - j * N;
    k = j / N;
    j -= k * N;
    double s = 0.0;
    for (int n = 0; n < N; ++n) {
      s += d_s[i * N + n] * ur[N * (j + N * k) + n] +
        d_s[j * N + n] * us[N * (n + N * k) + i] +
        d_s[k * N + n] * ut[N * (j + N * n) + i];
    }
    w[e_offset + it] = s;
  }
}


	.text
	.file	"cuda2.hip"
	.globl	_Z22__device_stub__nekbonePdS_S_S_i # -- Begin function _Z22__device_stub__nekbonePdS_S_S_i
	.type	_Z22__device_stub__nekbonePdS_S_S_i,@function
_Z22__device_stub__nekbonePdS_S_S_i:    # @_Z22__device_stub__nekbonePdS_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7nekbonePdS_S_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__nekbonePdS_S_S_i, .Lfunc_end0-_Z22__device_stub__nekbonePdS_S_S_i
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7nekbonePdS_S_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7nekbonePdS_S_S_i,@object     # @_Z7nekbonePdS_S_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z7nekbonePdS_S_S_i
	.p2align	3, 0x0
_Z7nekbonePdS_S_S_i:
	.quad	_Z22__device_stub__nekbonePdS_S_S_i
	.size	_Z7nekbonePdS_S_S_i, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z7nekbonePdS_S_S_i"
	.size	.L__unnamed_1, 20

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__nekbonePdS_S_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7nekbonePdS_S_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7nekbonePdS_S_S_i     ; -- Begin function _Z7nekbonePdS_S_S_i
	.globl	_Z7nekbonePdS_S_S_i
	.p2align	8
	.type	_Z7nekbonePdS_S_S_i,@function
_Z7nekbonePdS_S_S_i:                    ; @_Z7nekbonePdS_S_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s14, s3, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s12, s14, s3
	v_cmp_gt_i32_e64 s2, s12, v0
	s_mul_i32 s13, s12, s15
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s15, s2
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph
	s_load_b32 s16, s[0:1], 0x34
	v_dual_mov_b32 v2, v0 :: v_dual_lshlrev_b32 v1, 3, v0
	s_mov_b32 s18, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s16, s16, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s17, s16, 3
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v3, s13, v2
	v_add_nc_u32_e32 v2, s16, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	v_cmp_le_i32_e32 vcc_lo, s12, v2
	global_load_b64 v[3:4], v[3:4], off
	s_or_b32 s18, vcc_lo, s18
	s_waitcnt vmcnt(0)
	ds_store_b64 v1, v[3:4]
	v_add_nc_u32_e32 v1, s17, v1
	s_and_not1_b32 exec_lo, exec_lo, s18
	s_cbranch_execnz .LBB0_2
.LBB0_3:                                ; %Flow264
	s_or_b32 exec_lo, exec_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s6, exec_lo
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB0_5
; %bb.4:
	v_lshlrev_b32_e32 v3, 3, v0
	global_load_b64 v[1:2], v3, s[10:11]
	s_waitcnt vmcnt(0)
	ds_store_b64 v3, v[1:2] offset:32768
.LBB0_5:
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s6, s2
	s_cbranch_execz .LBB0_11
; %bb.6:                                ; %.lr.ph157
	s_cmp_gt_i32 s3, 0
	s_load_b32 s17, s[0:1], 0x34
	s_cselect_b32 s7, -1, 0
	s_ashr_i32 s10, s3, 31
	s_lshl_b32 s16, s14, 3
	s_add_i32 s11, s3, s10
	s_lshl_b32 s19, s3, 3
	s_xor_b32 s11, s11, s10
	s_sub_i32 s20, 0, s16
	v_cvt_f32_u32_e32 v1, s11
	s_sub_i32 s15, 0, s11
	s_sub_i32 s21, 0, s19
	v_dual_mov_b32 v13, v0 :: v_dual_lshlrev_b32 v10, 3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	v_or_b32_e32 v11, 0x8000, v10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s17, s17, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_lshl_b32 s18, s17, 3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, s15, v2
	s_mov_b32 s15, 0
	v_mul_hi_u32 v3, v2, v1
	v_mov_b32_e32 v1, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v12, v2, v3
.LBB0_7:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_9 Depth 2
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_and_not1_b32 vcc_lo, exec_lo, s7
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v7, v3 :: v_dual_mov_b32 v6, v2
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_cbranch_vccnz .LBB0_10
; %bb.8:                                ; %.lr.ph151.preheader
                                        ;   in Loop: Header=BB0_7 Depth=1
	v_ashrrev_i32_e32 v2, 31, v13
	v_mov_b32_e32 v19, v10
	s_mov_b32 s22, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v13, v2
	v_xor_b32_e32 v3, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v3, v12
	v_mul_lo_u32 v5, v4, s11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v3, v5
	v_add_nc_u32_e32 v5, 1, v4
	v_cmp_le_u32_e32 vcc_lo, s11, v3
	v_subrev_nc_u32_e32 v6, s11, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	v_add_nc_u32_e32 v5, 1, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v6, vcc_lo
	v_xor_b32_e32 v6, s10, v2
	v_cmp_le_u32_e32 vcc_lo, s11, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, v4, v5, vcc_lo
	v_xor_b32_e32 v4, v2, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v4, v6
	v_ashrrev_i32_e32 v2, 31, v5
	v_mul_lo_u32 v14, s19, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v5, v2
	v_xor_b32_e32 v3, v3, v2
	v_xor_b32_e32 v2, s10, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v7, v3, v12
	v_mul_lo_u32 v8, v7, s11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v8
	v_subrev_nc_u32_e32 v9, s11, v3
	v_cmp_le_u32_e32 vcc_lo, s11, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v3, v3, v9 :: v_dual_add_nc_u32 v8, 1, v7
	v_cndmask_b32_e32 v7, v7, v8, vcc_lo
	v_lshlrev_b32_e32 v9, 3, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s11, v3
	v_add_nc_u32_e32 v8, 1, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v7, v8, vcc_lo
	v_xor_b32_e32 v3, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v7, v3, v2
	v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v15, 3, v3
	v_mov_b32_e32 v3, 0
	v_mul_lo_u32 v8, v7, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v9, v15, v9
	v_mul_lo_u32 v15, s21, v5
	v_mul_lo_u32 v16, s20, v7
	v_add_nc_u32_e32 v17, 0x8000, v9
	v_add_nc_u32_e32 v6, v6, v8
	v_sub_nc_u32_e32 v8, v5, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v6, v4
	v_lshl_add_u32 v18, v8, 3, 0x8000
	v_dual_mov_b32 v7, v3 :: v_dual_mov_b32 v6, v2
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_u64_u32 v[8:9], null, s19, v4, v[1:2]
	v_mov_b32_e32 v9, v11
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
.LBB0_9:                                ; %.lr.ph151
                                        ;   Parent Loop BB0_7 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v28, v15, v9
	v_add_nc_u32_e32 v30, v16, v19
	ds_load_b64 v[20:21], v14
	ds_load_b64 v[22:23], v8
	ds_load_b64 v[24:25], v17
	ds_load_b64 v[26:27], v18
	ds_load_b64 v[28:29], v28
	ds_load_b64 v[30:31], v30
	v_add_nc_u32_e32 v8, s19, v8
	v_add_nc_u32_e32 v14, 8, v14
	v_add_nc_u32_e32 v17, s19, v17
	v_add_nc_u32_e32 v19, s16, v19
	v_add_nc_u32_e32 v9, s19, v9
	v_add_nc_u32_e32 v18, s19, v18
	s_add_i32 s22, s22, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s22, 0
	s_waitcnt lgkmcnt(2)
	v_fma_f64 v[6:7], v[26:27], v[22:23], v[6:7]
	s_waitcnt lgkmcnt(1)
	v_fma_f64 v[4:5], v[28:29], v[20:21], v[4:5]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[2:3], v[24:25], v[30:31], v[2:3]
	s_cbranch_scc0 .LBB0_9
.LBB0_10:                               ; %._crit_edge152
                                        ;   in Loop: Header=BB0_7 Depth=1
	v_add_nc_u32_e32 v8, s13, v13
	v_add_nc_u32_e32 v1, s18, v1
	v_add_nc_u32_e32 v10, s18, v10
	v_add_nc_u32_e32 v11, s18, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v8, v8, 6
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	v_add_co_u32 v8, vcc_lo, s8, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
	s_clause 0x2
	global_load_b128 v[14:17], v[8:9], off
	global_load_b128 v[18:21], v[8:9], off offset:16
	global_load_b128 v[22:25], v[8:9], off offset:32
	s_waitcnt vmcnt(2)
	v_mul_f64 v[8:9], v[6:7], v[16:17]
	s_waitcnt vmcnt(1)
	v_mul_f64 v[20:21], v[6:7], v[20:21]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[6:7], v[6:7], v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[8:9], v[4:5], v[14:15], v[8:9]
	v_fma_f64 v[14:15], v[4:5], v[16:17], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[4:5], v[4:5], v[18:19], v[6:7]
	v_fma_f64 v[6:7], v[2:3], v[18:19], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[8:9], v[2:3], v[22:23], v[14:15]
	v_fma_f64 v[2:3], v[2:3], v[24:25], v[4:5]
	v_lshlrev_b32_e32 v4, 3, v13
	v_add_nc_u32_e32 v13, s17, v13
	ds_store_2addr_stride64_b64 v4, v[6:7], v[8:9] offset0:16 offset1:32
	ds_store_b64 v4, v[2:3] offset:24576
	v_cmp_le_i32_e32 vcc_lo, s12, v13
	s_or_b32 s15, vcc_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB0_7
.LBB0_11:                               ; %Flow262
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s6, s2
	s_cbranch_execz .LBB0_18
; %bb.12:                               ; %.lr.ph167
	s_cmp_gt_i32 s3, 0
	s_load_b32 s0, s[0:1], 0x34
	s_cselect_b32 s2, -1, 0
	s_ashr_i32 s6, s3, 31
	v_lshlrev_b32_e32 v3, 3, v0
	s_add_i32 s7, s3, s6
	s_lshl_b32 s9, s3, 3
	s_xor_b32 s7, s7, s6
	s_lshl_b32 s11, s14, 3
	v_cvt_f32_u32_e32 v1, s7
	s_sub_i32 s1, 0, s7
	v_or_b32_e32 v7, 0x6000, v3
	v_or_b32_e32 v8, 0x4000, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s0, 0xffff
	s_lshl_b32 s10, s8, 3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_mul_lo_u32 v2, s1, v1
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v1, v2
	v_add_nc_u32_e32 v9, v1, v2
.LBB0_13:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_15 Depth 2
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_16
; %bb.14:                               ; %.lr.ph162
                                        ;   in Loop: Header=BB0_13 Depth=1
	v_ashrrev_i32_e32 v1, 31, v0
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v0, v1
	v_xor_b32_e32 v2, v2, v1
	v_xor_b32_e32 v1, s6, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v2, v9
	v_mul_lo_u32 v4, v3, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v2, v4
	v_add_nc_u32_e32 v4, 1, v3
	v_subrev_nc_u32_e32 v5, s7, v2
	v_cmp_le_u32_e32 vcc_lo, s7, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v3, v3, v4 :: v_dual_cndmask_b32 v2, v2, v5
	v_add_nc_u32_e32 v4, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s7, v2
	v_cndmask_b32_e32 v2, v3, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v2, v1
	v_sub_nc_u32_e32 v5, v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v6, 31, v5
	v_mul_lo_u32 v10, v5, s3
	v_add_nc_u32_e32 v3, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v3, v6
	v_mul_hi_u32 v4, v3, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, v4, s7
	v_sub_nc_u32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v4, s7, v3
	v_cmp_le_u32_e32 vcc_lo, s7, v3
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v4, s7, v3
	v_cmp_le_u32_e32 vcc_lo, s7, v3
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v3, v6
	v_add_nc_u32_e32 v1, v3, v1
	v_sub_nc_u32_e32 v11, v3, v6
	v_sub_nc_u32_e32 v12, v6, v3
	v_mad_u64_u32 v[3:4], null, s9, v5, 0x2000
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v1, v1, v2
	v_sub_nc_u32_e32 v2, v0, v10
	v_sub_nc_u32_e32 v13, v5, v11
	v_mad_u64_u32 v[4:5], null, s9, v11, 0x8000
	v_sub_nc_u32_e32 v1, v1, v6
	v_mul_lo_u32 v10, s9, v12
	v_mad_u64_u32 v[5:6], null, s9, v2, 0x8000
	v_mov_b32_e32 v6, v8
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v12, s9, v1
	v_mov_b32_e32 v1, 0
	v_lshl_add_u32 v11, v13, 3, 0x8000
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v13, v7
.LBB0_15:                               ;   Parent Loop BB0_13 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v18, v10, v6
	v_add_nc_u32_e32 v6, s9, v6
	s_add_i32 s0, s0, -1
	ds_load_b64 v[14:15], v5
	ds_load_b64 v[16:17], v4
	ds_load_b64 v[18:19], v18
	ds_load_b64 v[20:21], v3
	v_add_nc_u32_e32 v4, 8, v4
	v_add_nc_u32_e32 v3, 8, v3
	v_add_nc_u32_e32 v5, 8, v5
	s_cmp_eq_u32 s0, 0
	s_waitcnt lgkmcnt(1)
	v_mul_f64 v[16:17], v[16:17], v[18:19]
	v_add_nc_u32_e32 v18, v12, v13
	v_add_nc_u32_e32 v13, s11, v13
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[14:15], v[14:15], v[20:21], v[16:17]
	ds_load_b64 v[16:17], v11
	ds_load_b64 v[18:19], v18
	v_add_nc_u32_e32 v11, 8, v11
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[14:15], v[16:17], v[18:19], v[14:15]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[1:2], v[1:2], v[14:15]
	s_cbranch_scc0 .LBB0_15
	s_branch .LBB0_17
.LBB0_16:                               ;   in Loop: Header=BB0_13 Depth=1
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
.LBB0_17:                               ; %._crit_edge163
                                        ;   in Loop: Header=BB0_13 Depth=1
	v_add_nc_u32_e32 v3, s13, v0
	v_add_nc_u32_e32 v0, s8, v0
	v_add_nc_u32_e32 v7, s10, v7
	v_add_nc_u32_e32 v8, s10, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v4, 31, v3
	v_cmp_le_i32_e32 vcc_lo, s12, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_or_b32 s1, vcc_lo, s1
	v_add_co_u32 v3, s0, s4, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v4, s0, s5, v4, s0
	global_store_b64 v[3:4], v[1:2], off
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_13
.LBB0_18:                               ; %Flow258
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7nekbonePdS_S_S_i
		.amdhsa_group_segment_fixed_size 33792
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 32
		.amdhsa_next_free_sgpr 23
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7nekbonePdS_S_S_i, .Lfunc_end0-_Z7nekbonePdS_S_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1876
; NumSgprs: 25
; NumVgprs: 32
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 33792 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 25
; NumVGPRsForWavesPerEU: 32
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 33792
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7nekbonePdS_S_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     25
    .sgpr_spill_count: 0
    .symbol:         _Z7nekbonePdS_S_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     32
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
