#include <stdio.h>

#define TILE_SIZE 32
#define KERNEL_RADIUS 8
#define KERNEL_LENGTH (2 * KERNEL_RADIUS + 1)

__constant__ float c_M[KERNEL_LENGTH][KERNEL_LENGTH];
const int Width = 3072;
const int Height = 3072;
const int nIter = 300;

float * h_Kernel,*h_Input,*h_Output;
float * d_Input, *d_Output;

//this optimization is not good.
__global__ void convolution_2D_tiled_kernel(float* P, float* N, int height, int width, int pitch, int Mask_Width){
    int tx = threadIdx.x;
    int ty = threadIdx.y;

    int row_o = blockIdx.y * TILE_SIZE + ty;
    int col_o = blockIdx.x * TILE_SIZE + tx;

    int row_i = row_o - Mask_Width/2;
    int col_i = col_o - Mask_Width/2;

    __shared__ float N_ds[TILE_SIZE + KERNEL_LENGTH - 1][TILE_SIZE + KERNEL_LENGTH - 1];
    if((row_i >= 0) && (row_i < height) && 
       (col_i >= 0) && (col_i < width)){
           N_ds[ty][tx] = N[row_i * pitch + col_i];
       }else{
           N_ds[ty][tx] = 0.0f;
       }
    
    __syncthreads();

    float output = 0.0f;
    if(ty < TILE_SIZE && tx < TILE_SIZE){
        for(int i = 0;i<Mask_Width;i++){
            for(int j = 0;j<Mask_Width;j++){
                output += c_M[i][j] * N_ds[i + ty][j + tx];
            }
        }
        if(row_o < height && col_o < width){
            P[row_o * width + col_o] = output;
        }
    }
}


void gpuRunTiledKernel(){

    dim3 blockDim(TILE_SIZE,TILE_SIZE);
    dim3 gridDim((Width + TILE_SIZE - 1)/TILE_SIZE,(Height + TILE_SIZE - 1)/TILE_SIZE);

    convolution_2D_tiled_kernel<<<gridDim,blockDim>>>(d_Output,d_Input,Height,Width,Width,KERNEL_LENGTH);
    
    cudaDeviceSynchronize();
    cudaEvent_t start;
    cudaEventCreate(&start);
    cudaEvent_t stop;
    cudaEventCreate(&stop);
    cudaEventRecord(start,NULL);

    for(int i = 0;i<nIter;i++){
        convolution_2D_tiled_kernel<<<gridDim,blockDim>>>(d_Output,d_Input,Height,Width,Width,KERNEL_LENGTH);
    }

    cudaEventRecord(stop, NULL);
    cudaDeviceSynchronize();
    float msecTotal = 0.0f;
    cudaEventElapsedTime(&msecTotal,start,stop);

    float gpuTime = (msecTotal / nIter) * 0.001;
    printf("Tiled Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
            (1.0e-6 * (Width*Height)/gpuTime),
            gpuTime,
            Width);

    cudaMemcpy(h_Output,d_Output,Width*Height* sizeof(float),cudaMemcpyDeviceToHost);

    bool correct = true;
    double eps = 1.e-6;
    for(int i = 0;i<Width*Height;i++){
        double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * KERNEL_LENGTH * 1.0);

        if (abs_err > eps)
        {
            //printf("Error! Index = %d,h_Output = %f,true value = %d\n", 
             //              i, h_Output[i], KERNEL_LENGTH*KERNEL_LENGTH);
            correct = false;
        }
    }
    printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}

int main(){
    h_Kernel = (float*)malloc(KERNEL_LENGTH * KERNEL_LENGTH * sizeof(float));
    h_Input  = (float*)malloc(Width * Height * sizeof(float));
    h_Output = (float*)malloc(Width * Height * sizeof(float));

    for(unsigned int i = 0;i<KERNEL_LENGTH*KERNEL_LENGTH;i++){
        h_Kernel[i] = 1.0f;
    }

    for(unsigned int i = 0;i<Width*Height;i++){
        h_Input[i] = 1.0f;
    }

    cudaMalloc((void**)&d_Input, Width * Height * sizeof(float));
    cudaMalloc((void**)&d_Output,Width * Height * sizeof(float));

    cudaMemcpy(d_Input,h_Input,Width * Height * sizeof(float),cudaMemcpyHostToDevice);
    cudaMemcpyToSymbol(c_M,h_Kernel,KERNEL_LENGTH * KERNEL_LENGTH * sizeof(float));

    printf("Running GPU convlution 2D ....\n");

    gpuRunTiledKernel();

    free(h_Input);
    free(h_Kernel);
    free(h_Output);
    cudaFree(d_Input);
    cudaFree(d_Output);
}
	.file	"tmpxft_0037972f_00000000-6_Conv2D.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z53__device_stub__Z27convolution_2D_tiled_kernelPfS_iiiiPfS_iiii
	.type	_Z53__device_stub__Z27convolution_2D_tiled_kernelPfS_iiiiPfS_iiii, @function
_Z53__device_stub__Z27convolution_2D_tiled_kernelPfS_iiiiPfS_iiii:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z27convolution_2D_tiled_kernelPfS_iiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 192
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z53__device_stub__Z27convolution_2D_tiled_kernelPfS_iiiiPfS_iiii, .-_Z53__device_stub__Z27convolution_2D_tiled_kernelPfS_iiiiPfS_iiii
	.globl	_Z27convolution_2D_tiled_kernelPfS_iiii
	.type	_Z27convolution_2D_tiled_kernelPfS_iiii, @function
_Z27convolution_2D_tiled_kernelPfS_iiii:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z27convolution_2D_tiled_kernelPfS_iiiiPfS_iiii
	.cfi_endproc
.LFE2054:
	.size	_Z27convolution_2D_tiled_kernelPfS_iiii, .-_Z27convolution_2D_tiled_kernelPfS_iiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Result = PASS"
.LC1:
	.string	"Result = FAIL"
.LC6:
	.string	"Tiled Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n"
.LC10:
	.string	"%s\n"
	.text
	.globl	_Z17gpuRunTiledKernelv
	.type	_Z17gpuRunTiledKernelv, @function
_Z17gpuRunTiledKernelv:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$137438953504, %rdx
	movl	$1, %esi
	movabsq	$412316860512, %rdi
	subq	$64, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	movq	%rdx, 32(%rsp)
	movl	$1, 40(%rsp)
	movq	%rdi, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	movl	$17, %r9d
	movl	$3072, %ecx
	movl	$3072, %edx
	movq	d_Input(%rip), %rsi
	movq	d_Output(%rip), %rdi
	movl	$3072, %r8d
	call	_Z53__device_stub__Z27convolution_2D_tiled_kernelPfS_iiiiPfS_iiii
.L9:
	call	cudaDeviceSynchronize@PLT
	leaq	16(%rsp), %rdi
	movl	$300, %ebx
	call	cudaEventCreate@PLT
	leaq	24(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
.L11:
	movl	40(%rsp), %ecx
	movq	32(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	44(%rsp), %rdi
	movl	52(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movl	$17, %r9d
	movl	$3072, %ecx
	movl	$3072, %edx
	movq	d_Input(%rip), %rsi
	movq	d_Output(%rip), %rdi
	movl	$3072, %r8d
	call	_Z53__device_stub__Z27convolution_2D_tiled_kernelPfS_iiiiPfS_iiii
.L10:
	decl	%ebx
	jne	.L11
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	call	cudaDeviceSynchronize@PLT
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	leaq	12(%rsp), %rdi
	movl	$0x00000000, 12(%rsp)
	call	cudaEventElapsedTime@PLT
	movss	12(%rsp), %xmm1
	movb	$2, %al
	divss	.LC3(%rip), %xmm1
	cvtss2sd	%xmm1, %xmm1
	mulsd	.LC4(%rip), %xmm1
	movsd	.LC5(%rip), %xmm0
	movl	$3072, %edx
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	cvtsd2ss	%xmm1, %xmm1
	cvtss2sd	%xmm1, %xmm1
	divsd	%xmm1, %xmm0
	call	__printf_chk@PLT
	movl	$2, %ecx
	movl	$37748736, %edx
	movq	d_Output(%rip), %rsi
	movq	h_Output(%rip), %rdi
	call	cudaMemcpy@PLT
	movq	h_Output(%rip), %rsi
	xorl	%eax, %eax
	movb	$1, %dl
	movsd	.LC7(%rip), %xmm3
	movq	.LC8(%rip), %xmm2
	xorl	%ecx, %ecx
	movsd	.LC9(%rip), %xmm1
.L13:
	cvtss2sd	(%rsi,%rax,4), %xmm0
	subsd	%xmm3, %xmm0
	andps	%xmm2, %xmm0
	ucomisd	%xmm1, %xmm0
	cmova	%ecx, %edx
	incq	%rax
	cmpq	$9437184, %rax
	jne	.L13
	testb	%dl, %dl
	leaq	.LC0(%rip), %rax
	movl	$2, %edi
	leaq	.LC1(%rip), %rdx
	leaq	.LC10(%rip), %rsi
	cmovne	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$64, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z17gpuRunTiledKernelv, .-_Z17gpuRunTiledKernelv
	.section	.rodata.str1.1
.LC12:
	.string	"Running GPU convlution 2D ....\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	$1156, %edi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	pushq	%rcx
	.cfi_def_cfa_offset 32
	call	malloc@PLT
	movl	$37748736, %edi
	movq	%rax, h_Kernel(%rip)
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$37748736, %edi
	movq	%rax, h_Input(%rip)
	movq	%rax, %rbx
	call	malloc@PLT
	movss	.LC11(%rip), %xmm0
	xorl	%edx, %edx
	movq	%rax, h_Output(%rip)
.L22:
	movss	%xmm0, 0(%rbp,%rdx,4)
	incq	%rdx
	cmpq	$289, %rdx
	jne	.L22
	xorl	%edx, %edx
.L23:
	movss	%xmm0, (%rbx,%rdx,4)
	incq	%rdx
	cmpq	$9437184, %rdx
	jne	.L23
	movl	$37748736, %esi
	leaq	d_Input(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$37748736, %esi
	leaq	d_Output(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$37748736, %edx
	movq	h_Input(%rip), %rsi
	movq	d_Input(%rip), %rdi
	call	cudaMemcpy@PLT
	movq	h_Kernel(%rip), %rsi
	movl	$1156, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	leaq	_ZL3c_M(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	leaq	.LC12(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	call	_Z17gpuRunTiledKernelv
	movq	h_Input(%rip), %rdi
	call	free@PLT
	movq	h_Kernel(%rip), %rdi
	call	free@PLT
	movq	h_Output(%rip), %rdi
	call	free@PLT
	movq	d_Input(%rip), %rdi
	call	cudaFree@PLT
	movq	d_Output(%rip), %rdi
	call	cudaFree@PLT
	popq	%rdx
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC13:
	.string	"_Z27convolution_2D_tiled_kernelPfS_iiii"
.LC14:
	.string	"c_M"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z27convolution_2D_tiled_kernelPfS_iiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC14(%rip), %rdx
	movl	$1156, %r9d
	leaq	_ZL3c_M(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	d_Output
	.bss
	.align 8
	.type	d_Output, @object
	.size	d_Output, 8
d_Output:
	.zero	8
	.globl	d_Input
	.align 8
	.type	d_Input, @object
	.size	d_Input, 8
d_Input:
	.zero	8
	.globl	h_Output
	.align 8
	.type	h_Output, @object
	.size	h_Output, 8
h_Output:
	.zero	8
	.globl	h_Input
	.align 8
	.type	h_Input, @object
	.size	h_Input, 8
h_Input:
	.zero	8
	.globl	h_Kernel
	.align 8
	.type	h_Kernel, @object
	.size	h_Kernel, 8
h_Kernel:
	.zero	8
	.local	_ZL3c_M
	.comm	_ZL3c_M,1156,32
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC3:
	.long	1133903872
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC4:
	.long	-755914244
	.long	1062232653
	.align 8
.LC5:
	.long	-1798526145
	.long	1076027350
	.align 8
.LC7:
	.long	0
	.long	1081217024
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC8:
	.long	-1
	.long	2147483647
	.long	0
	.long	0
	.section	.rodata.cst8
	.align 8
.LC9:
	.long	-1598689907
	.long	1051772663
	.section	.rodata.cst4
	.align 4
.LC11:
	.long	1065353216
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>

#define TILE_SIZE 32
#define KERNEL_RADIUS 8
#define KERNEL_LENGTH (2 * KERNEL_RADIUS + 1)

__constant__ float c_M[KERNEL_LENGTH][KERNEL_LENGTH];
const int Width = 3072;
const int Height = 3072;
const int nIter = 300;

float * h_Kernel,*h_Input,*h_Output;
float * d_Input, *d_Output;

//this optimization is not good.
__global__ void convolution_2D_tiled_kernel(float* P, float* N, int height, int width, int pitch, int Mask_Width){
    int tx = threadIdx.x;
    int ty = threadIdx.y;

    int row_o = blockIdx.y * TILE_SIZE + ty;
    int col_o = blockIdx.x * TILE_SIZE + tx;

    int row_i = row_o - Mask_Width/2;
    int col_i = col_o - Mask_Width/2;

    __shared__ float N_ds[TILE_SIZE + KERNEL_LENGTH - 1][TILE_SIZE + KERNEL_LENGTH - 1];
    if((row_i >= 0) && (row_i < height) && 
       (col_i >= 0) && (col_i < width)){
           N_ds[ty][tx] = N[row_i * pitch + col_i];
       }else{
           N_ds[ty][tx] = 0.0f;
       }
    
    __syncthreads();

    float output = 0.0f;
    if(ty < TILE_SIZE && tx < TILE_SIZE){
        for(int i = 0;i<Mask_Width;i++){
            for(int j = 0;j<Mask_Width;j++){
                output += c_M[i][j] * N_ds[i + ty][j + tx];
            }
        }
        if(row_o < height && col_o < width){
            P[row_o * width + col_o] = output;
        }
    }
}


void gpuRunTiledKernel(){

    dim3 blockDim(TILE_SIZE,TILE_SIZE);
    dim3 gridDim((Width + TILE_SIZE - 1)/TILE_SIZE,(Height + TILE_SIZE - 1)/TILE_SIZE);

    convolution_2D_tiled_kernel<<<gridDim,blockDim>>>(d_Output,d_Input,Height,Width,Width,KERNEL_LENGTH);
    
    hipDeviceSynchronize();
    hipEvent_t start;
    hipEventCreate(&start);
    hipEvent_t stop;
    hipEventCreate(&stop);
    hipEventRecord(start,NULL);

    for(int i = 0;i<nIter;i++){
        convolution_2D_tiled_kernel<<<gridDim,blockDim>>>(d_Output,d_Input,Height,Width,Width,KERNEL_LENGTH);
    }

    hipEventRecord(stop, NULL);
    hipDeviceSynchronize();
    float msecTotal = 0.0f;
    hipEventElapsedTime(&msecTotal,start,stop);

    float gpuTime = (msecTotal / nIter) * 0.001;
    printf("Tiled Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
            (1.0e-6 * (Width*Height)/gpuTime),
            gpuTime,
            Width);

    hipMemcpy(h_Output,d_Output,Width*Height* sizeof(float),hipMemcpyDeviceToHost);

    bool correct = true;
    double eps = 1.e-6;
    for(int i = 0;i<Width*Height;i++){
        double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * KERNEL_LENGTH * 1.0);

        if (abs_err > eps)
        {
            //printf("Error! Index = %d,h_Output = %f,true value = %d\n", 
             //              i, h_Output[i], KERNEL_LENGTH*KERNEL_LENGTH);
            correct = false;
        }
    }
    printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}

int main(){
    h_Kernel = (float*)malloc(KERNEL_LENGTH * KERNEL_LENGTH * sizeof(float));
    h_Input  = (float*)malloc(Width * Height * sizeof(float));
    h_Output = (float*)malloc(Width * Height * sizeof(float));

    for(unsigned int i = 0;i<KERNEL_LENGTH*KERNEL_LENGTH;i++){
        h_Kernel[i] = 1.0f;
    }

    for(unsigned int i = 0;i<Width*Height;i++){
        h_Input[i] = 1.0f;
    }

    hipMalloc((void**)&d_Input, Width * Height * sizeof(float));
    hipMalloc((void**)&d_Output,Width * Height * sizeof(float));

    hipMemcpy(d_Input,h_Input,Width * Height * sizeof(float),hipMemcpyHostToDevice);
    hipMemcpyToSymbol(HIP_SYMBOL(c_M),h_Kernel,KERNEL_LENGTH * KERNEL_LENGTH * sizeof(float));

    printf("Running GPU convlution 2D ....\n");

    gpuRunTiledKernel();

    free(h_Input);
    free(h_Kernel);
    free(h_Output);
    hipFree(d_Input);
    hipFree(d_Output);
}
	.text
	.file	"Conv2D.hip"
	.globl	_Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii # -- Begin function _Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii
	.type	_Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii,@function
_Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii: # @_Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27convolution_2D_tiled_kernelPfS_iiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii, .Lfunc_end0-_Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z17gpuRunTiledKernelv
.LCPI1_0:
	.long	0x43960000                      # float 300
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI1_1:
	.quad	0x3f50624dd2f1a9fc              # double 0.001
.LCPI1_2:
	.quad	0x4022dfd694ccab3f              # double 9.4371840000000002
.LCPI1_3:
	.quad	0xc072100000000000              # double -289
.LCPI1_5:
	.quad	0x3eb0c6f7a0b5ed8d              # double 9.9999999999999995E-7
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0
.LCPI1_4:
	.quad	0x7fffffffffffffff              # double NaN
	.quad	0x7fffffffffffffff              # double NaN
	.text
	.globl	_Z17gpuRunTiledKernelv
	.type	_Z17gpuRunTiledKernelv,@function
_Z17gpuRunTiledKernelv:                 # @_Z17gpuRunTiledKernelv
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movabsq	$412316860512, %rbx             # imm = 0x6000000060
	movabsq	$137438953504, %r14             # imm = 0x2000000020
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movq	d_Output(%rip), %rdi
	movq	d_Input(%rip), %rsi
	movl	$3072, %edx                     # imm = 0xC00
	movl	$3072, %ecx                     # imm = 0xC00
	movl	$3072, %r8d                     # imm = 0xC00
	movl	$17, %r9d
	callq	_Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii
.LBB1_2:
	callq	hipDeviceSynchronize
	leaq	8(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventCreate
	movq	%rsp, %rdi
	callq	hipEventCreate
	movq	(%r15), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	$300, %ebp                      # imm = 0x12C
.LBB1_3:                                # =>This Inner Loop Header: Depth=1
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_5
# %bb.4:                                #   in Loop: Header=BB1_3 Depth=1
	movq	d_Output(%rip), %rdi
	movq	d_Input(%rip), %rsi
	movl	$3072, %edx                     # imm = 0xC00
	movl	$3072, %ecx                     # imm = 0xC00
	movl	$3072, %r8d                     # imm = 0xC00
	movl	$17, %r9d
	callq	_Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii
.LBB1_5:                                #   in Loop: Header=BB1_3 Depth=1
	decl	%ebp
	jne	.LBB1_3
# %bb.6:
	movq	(%rsp), %rdi
	xorl	%r14d, %r14d
	xorl	%esi, %esi
	callq	hipEventRecord
	callq	hipDeviceSynchronize
	leaq	20(%rsp), %rbx
	movl	$0, (%rbx)
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movss	(%rbx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	divss	.LCPI1_0(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	mulsd	.LCPI1_1(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	cvtss2sd	%xmm0, %xmm1
	movsd	.LCPI1_2(%rip), %xmm0           # xmm0 = mem[0],zero
	divsd	%xmm1, %xmm0
	movl	$.L.str, %edi
	movl	$3072, %esi                     # imm = 0xC00
	movb	$2, %al
	callq	printf
	movq	h_Output(%rip), %rdi
	movq	d_Output(%rip), %rsi
	movl	$37748736, %edx                 # imm = 0x2400000
	movl	$2, %ecx
	callq	hipMemcpy
	movb	$1, %cl
	movq	h_Output(%rip), %rax
	movsd	.LCPI1_3(%rip), %xmm0           # xmm0 = mem[0],zero
	movapd	.LCPI1_4(%rip), %xmm1           # xmm1 = [NaN,NaN]
	movsd	.LCPI1_5(%rip), %xmm2           # xmm2 = mem[0],zero
.LBB1_7:                                # =>This Inner Loop Header: Depth=1
	xorps	%xmm3, %xmm3
	cvtss2sd	(%rax,%r14,4), %xmm3
	addsd	%xmm0, %xmm3
	andpd	%xmm1, %xmm3
	ucomisd	%xmm2, %xmm3
	movl	$0, %edx
	ja	.LBB1_9
# %bb.8:                                #   in Loop: Header=BB1_7 Depth=1
	movzbl	%cl, %edx
.LBB1_9:                                #   in Loop: Header=BB1_7 Depth=1
	movl	%edx, %ecx
	incq	%r14
	cmpq	$9437184, %r14                  # imm = 0x900000
	jne	.LBB1_7
# %bb.10:
	testb	$1, %cl
	movl	$.L.str.3, %eax
	movl	$.L.str.2, %edi
	cmoveq	%rax, %rdi
	callq	puts@PLT
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z17gpuRunTiledKernelv, .Lfunc_end1-_Z17gpuRunTiledKernelv
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	$1156, %edi                     # imm = 0x484
	callq	malloc
	movq	%rax, %r14
	movq	%rax, h_Kernel(%rip)
	movl	$37748736, %edi                 # imm = 0x2400000
	callq	malloc
	movq	%rax, %rbx
	movq	%rax, h_Input(%rip)
	movl	$37748736, %edi                 # imm = 0x2400000
	callq	malloc
	movq	%rax, h_Output(%rip)
	xorl	%eax, %eax
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	movl	$1065353216, (%r14,%rax,4)      # imm = 0x3F800000
	incq	%rax
	cmpq	$289, %rax                      # imm = 0x121
	jne	.LBB2_1
# %bb.2:                                # %.preheader.preheader
	xorl	%eax, %eax
.LBB2_3:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movl	$1065353216, (%rbx,%rax,4)      # imm = 0x3F800000
	incq	%rax
	cmpq	$9437184, %rax                  # imm = 0x900000
	jne	.LBB2_3
# %bb.4:
	movl	$d_Input, %edi
	movl	$37748736, %esi                 # imm = 0x2400000
	callq	hipMalloc
	movl	$d_Output, %edi
	movl	$37748736, %esi                 # imm = 0x2400000
	callq	hipMalloc
	movq	d_Input(%rip), %rdi
	movq	h_Input(%rip), %rsi
	movl	$37748736, %edx                 # imm = 0x2400000
	movl	$1, %ecx
	callq	hipMemcpy
	movq	h_Kernel(%rip), %rsi
	movl	$c_M, %edi
	movl	$1156, %edx                     # imm = 0x484
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	movl	$.Lstr, %edi
	callq	puts@PLT
	callq	_Z17gpuRunTiledKernelv
	movq	h_Input(%rip), %rdi
	callq	free
	movq	h_Kernel(%rip), %rdi
	callq	free
	movq	h_Output(%rip), %rdi
	callq	free
	movq	d_Input(%rip), %rdi
	callq	hipFree
	movq	d_Output(%rip), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27convolution_2D_tiled_kernelPfS_iiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$c_M, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$1156, %r9d                     # imm = 0x484
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	c_M,@object                     # @c_M
	.local	c_M
	.comm	c_M,1156,16
	.type	h_Kernel,@object                # @h_Kernel
	.bss
	.globl	h_Kernel
	.p2align	3, 0x0
h_Kernel:
	.quad	0
	.size	h_Kernel, 8

	.type	h_Input,@object                 # @h_Input
	.globl	h_Input
	.p2align	3, 0x0
h_Input:
	.quad	0
	.size	h_Input, 8

	.type	h_Output,@object                # @h_Output
	.globl	h_Output
	.p2align	3, 0x0
h_Output:
	.quad	0
	.size	h_Output, 8

	.type	d_Input,@object                 # @d_Input
	.globl	d_Input
	.p2align	3, 0x0
d_Input:
	.quad	0
	.size	d_Input, 8

	.type	d_Output,@object                # @d_Output
	.globl	d_Output
	.p2align	3, 0x0
d_Output:
	.quad	0
	.size	d_Output, 8

	.type	_Z27convolution_2D_tiled_kernelPfS_iiii,@object # @_Z27convolution_2D_tiled_kernelPfS_iiii
	.section	.rodata,"a",@progbits
	.globl	_Z27convolution_2D_tiled_kernelPfS_iiii
	.p2align	3, 0x0
_Z27convolution_2D_tiled_kernelPfS_iiii:
	.quad	_Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii
	.size	_Z27convolution_2D_tiled_kernelPfS_iiii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Tiled Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n"
	.size	.L.str, 78

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Result = PASS"
	.size	.L.str.2, 14

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Result = FAIL"
	.size	.L.str.3, 14

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z27convolution_2D_tiled_kernelPfS_iiii"
	.size	.L__unnamed_1, 40

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"c_M"
	.size	.L__unnamed_2, 4

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Running GPU convlution 2D ...."
	.size	.Lstr, 31

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z42__device_stub__convolution_2D_tiled_kernelPfS_iiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym c_M
	.addrsig_sym d_Input
	.addrsig_sym d_Output
	.addrsig_sym _Z27convolution_2D_tiled_kernelPfS_iiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z27convolution_2D_tiled_kernelPfS_iiii ; -- Begin function _Z27convolution_2D_tiled_kernelPfS_iiii
	.globl	_Z27convolution_2D_tiled_kernelPfS_iiii
	.p2align	8
	.type	_Z27convolution_2D_tiled_kernelPfS_iiii,@function
_Z27convolution_2D_tiled_kernelPfS_iiii: ; @_Z27convolution_2D_tiled_kernelPfS_iiii
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_bfe_u32 v3, v0, 10, 10
	v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v4, 0x3ff, v0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v2, s15, 5, v3
	v_lshl_add_u32 v0, s14, 5, v4
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s11, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s11, s0
	s_ashr_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v6, s0, v2
	v_cmpx_lt_i32_e32 -1, v6
	s_cbranch_execz .LBB0_4
; %bb.1:
	v_subrev_nc_u32_e32 v1, s0, v0
	v_cmp_gt_i32_e32 vcc_lo, s8, v6
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s0, s9, v1
	v_cmp_lt_i32_e64 s1, -1, v1
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_3
; %bb.2:
	v_mad_u64_u32 v[7:8], null, v6, s10, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[5:6], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s6, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	global_load_b32 v5, v[5:6], off
.LBB0_3:                                ; %Flow97
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_4:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s2
	v_lshlrev_b32_e32 v1, 2, v4
	v_or_b32_e32 v4, v3, v4
	s_mov_b32 s0, exec_lo
	v_mad_u32_u24 v3, 0xc0, v3, v1
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB0_13
; %bb.5:                                ; %.preheader60
	s_cmp_lt_i32 s11, 1
	s_cbranch_scc1 .LBB0_10
; %bb.6:                                ; %.preheader.preheader
	v_mov_b32_e32 v1, 0
	s_mov_b32 s6, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, c_M@rel32@lo+4
	s_addc_u32 s1, s1, c_M@rel32@hi+12
.LBB0_7:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_8 Depth 2
	v_mov_b32_e32 v4, v3
	s_mov_b64 s[2:3], s[0:1]
	s_mov_b32 s7, s11
.LBB0_8:                                ;   Parent Loop BB0_7 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_load_b32 s10, s[2:3], 0x0
	ds_load_b32 v5, v4
	s_add_i32 s7, s7, -1
	v_add_nc_u32_e32 v4, 4, v4
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s7, 0
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v1, s10, v5
	s_cbranch_scc0 .LBB0_8
; %bb.9:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_7 Depth=1
	s_add_i32 s6, s6, 1
	v_add_nc_u32_e32 v3, 0xc0, v3
	s_add_u32 s0, s0, 0x44
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s6, s11
	s_cbranch_scc0 .LBB0_7
	s_branch .LBB0_11
.LBB0_10:
	v_mov_b32_e32 v1, 0
.LBB0_11:                               ; %._crit_edge65
	v_cmp_gt_i32_e32 vcc_lo, s8, v2
	v_cmp_gt_i32_e64 s0, s9, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_13
; %bb.12:
	v_mad_u64_u32 v[3:4], null, v2, s9, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_store_b32 v[2:3], v1, off
.LBB0_13:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27convolution_2D_tiled_kernelPfS_iiii
		.amdhsa_group_segment_fixed_size 9216
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z27convolution_2D_tiled_kernelPfS_iiii, .Lfunc_end0-_Z27convolution_2D_tiled_kernelPfS_iiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 488
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 9216 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	c_M                     ; @c_M
	.type	c_M,@object
	.section	.bss,"aw",@nobits
	.globl	c_M
	.p2align	4, 0x0
c_M:
	.zero	1156
	.size	c_M, 1156

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym c_M
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 9216
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z27convolution_2D_tiled_kernelPfS_iiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z27convolution_2D_tiled_kernelPfS_iiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
