#include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define BLOCK_SIZE 32
#define WA 64   
#define HA 64     
#define HC 3     
#define WC 3
#define PAD 1
#define WB (WA+2*PAD - WC + 1)
#define HB (HA+2*PAD - HC + 1)
#define CHANNEL_SIZE 3

__device__ void flat_conv(float* Input, float* Kernel, float* Output,int* image_size, int* kernel_size, int* pad,int* out_w)
{
    //__shared__ float kernel_part[kernel_size[2]][kernel_size[3]][kernel_size[1]];
    //__shared__ float kernel_part[3][3][3];
    extern __shared__ float kernel_part[];
    

    int col_idx = blockIdx.x - pad[0] + threadIdx.x;
    int row_idx = blockIdx.y - pad[0] + threadIdx.y;
    int img_flat_size = image_size[1]*image_size[2];
    int kernel_flat_size = kernel_size[2]*kernel_size[3];
    if( image_size[2]>col_idx && col_idx >=0 && image_size[1]>row_idx && row_idx >=0)
    {
        kernel_part[(threadIdx.y * kernel_size[3]+threadIdx.x)*kernel_size[1]+threadIdx.z] 
            = Input[(col_idx * image_size[2] +row_idx) + img_flat_size*threadIdx.z]
            * Kernel[threadIdx.y*kernel_size[3] + threadIdx.x + kernel_flat_size*threadIdx.z];
    }
    else
    {
        kernel_part[(threadIdx.y * kernel_size[3]+threadIdx.x)*kernel_size[1]+threadIdx.z] = 0;
    }
    //__syncthreads;

    atomicAdd(&(Output[blockIdx.x * out_w[0] +blockIdx.y]), kernel_part[(threadIdx.y * kernel_size[3]+threadIdx.x)*kernel_size[1]+threadIdx.z]);
}


__global__ void conv(float* Input, float* Kernel, float* Output,int* image_size, int* kernel_size,int* pad)
{   
    int out_w = image_size[2]+2*pad[0] - kernel_size[3] + 1;
    int out_h = image_size[1]+2*pad[0] - kernel_size[2] + 1;
    int flat_kernel_size = kernel_size[3]*kernel_size[2]*kernel_size[1];
    int flat_img_size = out_w*out_h;
    flat_conv(Input, Kernel + flat_kernel_size*blockIdx.z , Output + flat_img_size*blockIdx.z, image_size, kernel_size, pad,&out_w);
}

void randomInit(float* data, int size)
{
    
	for (int i = 0; i < size; ++i)
		data[i] = (rand() / (float)RAND_MAX);
}
__host__ int main(void)
{

    // float h_a[3][64][64] ={0.0};
    // h_a[0][0][0] = 2.1;
    // h_a[1][0][0] = 2.1;
    // h_a[2][0][0] = 2.1;
    // float h_b[2][3][3][3] ={1.0,1.0,1.0,1.0,1.0,1.0,1.0,1.0,1.0,
    //                         1.0,1.0,1.0,1.0,1.0,1.0,1.0,1.0,1.0,
    //                         1.0,1.0,1.0,1.0,1.0,1.0,1.0,1.0,1.0,
    //                         2.0,2.0,2.0,2.0,2.0,2.0,2.0,2.0,2.0,
    //                         2.0,2.0,2.0,2.0,2.0,2.0,2.0,2.0,2.0,
    //                         2.0,2.0,2.0,2.0,2.0,2.0,2.0,2.0,2.0};

    // float h_c[2][64][64] ={0.0};
    int kernel_size[4] ={2,3,3,3}; //O I H W;
    int image_size[3] = {3,64,64}; //  O H W;

    float* h_a; float *h_b; float* h_c;

    int h_a_size = sizeof(float)*3*64*64;
    int h_b_size = sizeof(float)*3*64*64;
    int h_c_size = sizeof(float)*3*64*64;

    h_a = (float*)malloc(h_a_size);
    h_b = (float*)malloc(h_b_size);
    h_c = (float*)malloc(h_c_size);
    
    randomInit(h_a,3*64*64);
    randomInit(h_b,2*3*3*3);
    randomInit(h_c,2*64*64);

    int pad = 1;

    float *cimg;
    float *coimg;
    float *ckernel;
    int * cimg_size;
    int * ckernel_size;
    int * cpad;
    cudaMalloc((void***)&cimg,h_a_size);
    cudaMalloc((void***)&ckernel,h_b_size);
    cudaMalloc((void***)&coimg,h_c_size);
    cudaMalloc(&cimg_size,sizeof(image_size));
    cudaMalloc(&ckernel_size,sizeof(kernel_size));
    cudaMalloc(&cpad,sizeof(int));

    cudaMemcpy(cimg,h_a,h_a_size,cudaMemcpyHostToDevice);
    cudaMemcpy(ckernel,h_b,h_b_size,cudaMemcpyHostToDevice);
    cudaMemcpy(cimg_size,image_size,sizeof(image_size),cudaMemcpyHostToDevice);
    cudaMemcpy(ckernel_size,kernel_size,sizeof(kernel_size),cudaMemcpyHostToDevice);
    cudaMemcpy(cpad,&pad,sizeof(int),cudaMemcpyHostToDevice);

    dim3 threads(kernel_size[3], kernel_size[2], kernel_size[1]);
	dim3 grid(image_size[2],image_size[1],kernel_size[0]);
    clock_t start = clock(); 

    int flat_kernel_size = kernel_size[3]* kernel_size[2]* kernel_size[1]*sizeof(float);
    conv <<< grid,threads,flat_kernel_size>>>(cimg,ckernel,coimg,cimg_size,ckernel_size,cpad);
    //Convolution <<< grid,threads>>>(cimg,ckernel,coimg,cimg_size,ckernel_size);

    clock_t end = clock();
    cudaMemcpy(h_c,coimg,h_c_size,cudaMemcpyDeviceToHost);

    int cnt = 0;
    // for(int i = 0;i < 2; i++)
    // {
    //     for(int j =0; j < WB;j ++)
    //     {
    //         for(int k =0; k < WB;k ++)
    //         {
    //             printf("%.0f ",h_c[cnt]);
    //             cnt +=1;
    //         }
    //         printf("\n");   
    //     }
    //     printf("\n");
    // }

    cudaFree(cimg);
    cudaFree(ckernel);
    cudaFree(coimg);
    cudaFree(cimg_size);
    cudaFree(ckernel_size);
    cudaFree(cpad);
    
    
    printf("%f",(float)(end - start)/CLOCKS_PER_SEC);
}
	.file	"tmpxft_003ae033_00000000-6_conv_with_out_channel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z9flat_convPfS_S_PiS0_S0_S0_
	.type	_Z9flat_convPfS_S_PiS0_S0_S0_, @function
_Z9flat_convPfS_S_PiS0_S0_S0_:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z9flat_convPfS_S_PiS0_S0_S0_, .-_Z9flat_convPfS_S_PiS0_S0_S0_
	.globl	_Z10randomInitPfi
	.type	_Z10randomInitPfi, @function
_Z10randomInitPfi:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	xorl	%ebx, %ebx
.L5:
	cmpl	%ebx, %ebp
	jle	.L9
	call	rand@PLT
	cvtsi2ssl	%eax, %xmm0
	mulss	.LC0(%rip), %xmm0
	movss	%xmm0, (%r12,%rbx,4)
	incq	%rbx
	jmp	.L5
.L9:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z10randomInitPfi, .-_Z10randomInitPfi
	.globl	_Z35__device_stub__Z4convPfS_S_PiS0_S0_PfS_S_PiS0_S0_
	.type	_Z35__device_stub__Z4convPfS_S_PiS0_S0_PfS_S_PiS0_S0_, @function
_Z35__device_stub__Z4convPfS_S_PiS0_S0_PfS_S_PiS0_S0_:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z4convPfS_S_PiS0_S0_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L10:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z35__device_stub__Z4convPfS_S_PiS0_S0_PfS_S_PiS0_S0_, .-_Z35__device_stub__Z4convPfS_S_PiS0_S0_PfS_S_PiS0_S0_
	.globl	_Z4convPfS_S_PiS0_S0_
	.type	_Z4convPfS_S_PiS0_S0_, @function
_Z4convPfS_S_PiS0_S0_:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z4convPfS_S_PiS0_S0_PfS_S_PiS0_S0_
	.cfi_endproc
.LFE2055:
	.size	_Z4convPfS_S_PiS0_S0_, .-_Z4convPfS_S_PiS0_S0_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"%f"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$49152, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	addq	$-128, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	movabsq	$12884901890, %rax
	movl	$64, 100(%rsp)
	movq	%rax, 104(%rsp)
	incq	%rax
	movq	%rax, 112(%rsp)
	movabsq	$274877906947, %rax
	movq	%rax, 92(%rsp)
	call	malloc@PLT
	movl	$49152, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$49152, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$12288, %esi
	movq	%r12, %rdi
	movq	%rax, %rbx
	call	_Z10randomInitPfi
	movq	%rbp, %rdi
	movl	$54, %esi
	call	_Z10randomInitPfi
	movl	$8192, %esi
	movq	%rbx, %rdi
	call	_Z10randomInitPfi
	leaq	16(%rsp), %rdi
	movl	$49152, %esi
	movl	$1, 12(%rsp)
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$49152, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$49152, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$12, %esi
	call	cudaMalloc@PLT
	leaq	48(%rsp), %rdi
	movl	$16, %esi
	call	cudaMalloc@PLT
	leaq	56(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$49152, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movq	%rbp, %rsi
	movl	$1, %ecx
	movl	$49152, %edx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	leaq	92(%rsp), %rsi
	movl	$1, %ecx
	movl	$12, %edx
	call	cudaMemcpy@PLT
	movq	48(%rsp), %rdi
	leaq	104(%rsp), %rsi
	movl	$1, %ecx
	movl	$16, %edx
	call	cudaMemcpy@PLT
	movq	56(%rsp), %rdi
	leaq	12(%rsp), %rsi
	movl	$1, %ecx
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	116(%rsp), %eax
	movl	%eax, 68(%rsp)
	movl	112(%rsp), %eax
	movl	%eax, 72(%rsp)
	movl	108(%rsp), %eax
	movl	%eax, 76(%rsp)
	movl	100(%rsp), %eax
	movl	%eax, 80(%rsp)
	movl	96(%rsp), %eax
	movl	%eax, 84(%rsp)
	movl	104(%rsp), %eax
	movl	%eax, 88(%rsp)
	call	clock@PLT
	movl	76(%rsp), %ecx
	movl	88(%rsp), %esi
	xorl	%r9d, %r9d
	movl	116(%rsp), %r8d
	imull	112(%rsp), %r8d
	movq	%rax, %rbp
	imull	108(%rsp), %r8d
	movq	68(%rsp), %rdx
	movq	80(%rsp), %rdi
	sall	$2, %r8d
	movslq	%r8d, %r8
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	movq	56(%rsp), %r9
	movq	48(%rsp), %r8
	movq	40(%rsp), %rcx
	movq	24(%rsp), %rdx
	movq	32(%rsp), %rsi
	movq	16(%rsp), %rdi
	call	_Z35__device_stub__Z4convPfS_S_PiS0_S0_PfS_S_PiS0_S0_
.L16:
	call	clock@PLT
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$49152, %edx
	movq	%rax, %r12
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	subq	%rbp, %r12
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtsi2ssq	%r12, %xmm0
	divss	.LC1(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	subq	$-128, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z4convPfS_S_PiS0_S0_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z4convPfS_S_PiS0_S0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	805306368
	.align 4
.LC1:
	.long	1232348160
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>

#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define BLOCK_SIZE 32
#define WA 64   
#define HA 64     
#define HC 3     
#define WC 3
#define PAD 1
#define WB (WA+2*PAD - WC + 1)
#define HB (HA+2*PAD - HC + 1)
#define CHANNEL_SIZE 3

__device__ void flat_conv(float* Input, float* Kernel, float* Output,int* image_size, int* kernel_size, int* pad,int* out_w)
{
    //__shared__ float kernel_part[kernel_size[2]][kernel_size[3]][kernel_size[1]];
    //__shared__ float kernel_part[3][3][3];
    extern __shared__ float kernel_part[];
    

    int col_idx = blockIdx.x - pad[0] + threadIdx.x;
    int row_idx = blockIdx.y - pad[0] + threadIdx.y;
    int img_flat_size = image_size[1]*image_size[2];
    int kernel_flat_size = kernel_size[2]*kernel_size[3];
    if( image_size[2]>col_idx && col_idx >=0 && image_size[1]>row_idx && row_idx >=0)
    {
        kernel_part[(threadIdx.y * kernel_size[3]+threadIdx.x)*kernel_size[1]+threadIdx.z] 
            = Input[(col_idx * image_size[2] +row_idx) + img_flat_size*threadIdx.z]
            * Kernel[threadIdx.y*kernel_size[3] + threadIdx.x + kernel_flat_size*threadIdx.z];
    }
    else
    {
        kernel_part[(threadIdx.y * kernel_size[3]+threadIdx.x)*kernel_size[1]+threadIdx.z] = 0;
    }
    //__syncthreads;

    atomicAdd(&(Output[blockIdx.x * out_w[0] +blockIdx.y]), kernel_part[(threadIdx.y * kernel_size[3]+threadIdx.x)*kernel_size[1]+threadIdx.z]);
}


__global__ void conv(float* Input, float* Kernel, float* Output,int* image_size, int* kernel_size,int* pad)
{   
    int out_w = image_size[2]+2*pad[0] - kernel_size[3] + 1;
    int out_h = image_size[1]+2*pad[0] - kernel_size[2] + 1;
    int flat_kernel_size = kernel_size[3]*kernel_size[2]*kernel_size[1];
    int flat_img_size = out_w*out_h;
    flat_conv(Input, Kernel + flat_kernel_size*blockIdx.z , Output + flat_img_size*blockIdx.z, image_size, kernel_size, pad,&out_w);
}

void randomInit(float* data, int size)
{
    
	for (int i = 0; i < size; ++i)
		data[i] = (rand() / (float)RAND_MAX);
}
__host__ int main(void)
{

    // float h_a[3][64][64] ={0.0};
    // h_a[0][0][0] = 2.1;
    // h_a[1][0][0] = 2.1;
    // h_a[2][0][0] = 2.1;
    // float h_b[2][3][3][3] ={1.0,1.0,1.0,1.0,1.0,1.0,1.0,1.0,1.0,
    //                         1.0,1.0,1.0,1.0,1.0,1.0,1.0,1.0,1.0,
    //                         1.0,1.0,1.0,1.0,1.0,1.0,1.0,1.0,1.0,
    //                         2.0,2.0,2.0,2.0,2.0,2.0,2.0,2.0,2.0,
    //                         2.0,2.0,2.0,2.0,2.0,2.0,2.0,2.0,2.0,
    //                         2.0,2.0,2.0,2.0,2.0,2.0,2.0,2.0,2.0};

    // float h_c[2][64][64] ={0.0};
    int kernel_size[4] ={2,3,3,3}; //O I H W;
    int image_size[3] = {3,64,64}; //  O H W;

    float* h_a; float *h_b; float* h_c;

    int h_a_size = sizeof(float)*3*64*64;
    int h_b_size = sizeof(float)*3*64*64;
    int h_c_size = sizeof(float)*3*64*64;

    h_a = (float*)malloc(h_a_size);
    h_b = (float*)malloc(h_b_size);
    h_c = (float*)malloc(h_c_size);
    
    randomInit(h_a,3*64*64);
    randomInit(h_b,2*3*3*3);
    randomInit(h_c,2*64*64);

    int pad = 1;

    float *cimg;
    float *coimg;
    float *ckernel;
    int * cimg_size;
    int * ckernel_size;
    int * cpad;
    hipMalloc((void***)&cimg,h_a_size);
    hipMalloc((void***)&ckernel,h_b_size);
    hipMalloc((void***)&coimg,h_c_size);
    hipMalloc(&cimg_size,sizeof(image_size));
    hipMalloc(&ckernel_size,sizeof(kernel_size));
    hipMalloc(&cpad,sizeof(int));

    hipMemcpy(cimg,h_a,h_a_size,hipMemcpyHostToDevice);
    hipMemcpy(ckernel,h_b,h_b_size,hipMemcpyHostToDevice);
    hipMemcpy(cimg_size,image_size,sizeof(image_size),hipMemcpyHostToDevice);
    hipMemcpy(ckernel_size,kernel_size,sizeof(kernel_size),hipMemcpyHostToDevice);
    hipMemcpy(cpad,&pad,sizeof(int),hipMemcpyHostToDevice);

    dim3 threads(kernel_size[3], kernel_size[2], kernel_size[1]);
	dim3 grid(image_size[2],image_size[1],kernel_size[0]);
    clock_t start = clock(); 

    int flat_kernel_size = kernel_size[3]* kernel_size[2]* kernel_size[1]*sizeof(float);
    conv <<< grid,threads,flat_kernel_size>>>(cimg,ckernel,coimg,cimg_size,ckernel_size,cpad);
    //Convolution <<< grid,threads>>>(cimg,ckernel,coimg,cimg_size,ckernel_size);

    clock_t end = clock();
    hipMemcpy(h_c,coimg,h_c_size,hipMemcpyDeviceToHost);

    int cnt = 0;
    // for(int i = 0;i < 2; i++)
    // {
    //     for(int j =0; j < WB;j ++)
    //     {
    //         for(int k =0; k < WB;k ++)
    //         {
    //             printf("%.0f ",h_c[cnt]);
    //             cnt +=1;
    //         }
    //         printf("\n");   
    //     }
    //     printf("\n");
    // }

    hipFree(cimg);
    hipFree(ckernel);
    hipFree(coimg);
    hipFree(cimg_size);
    hipFree(ckernel_size);
    hipFree(cpad);
    
    
    printf("%f",(float)(end - start)/CLOCKS_PER_SEC);
}
	.text
	.file	"conv_with_out_channel.hip"
	.globl	_Z19__device_stub__convPfS_S_PiS0_S0_ # -- Begin function _Z19__device_stub__convPfS_S_PiS0_S0_
	.type	_Z19__device_stub__convPfS_S_PiS0_S0_,@function
_Z19__device_stub__convPfS_S_PiS0_S0_:  # @_Z19__device_stub__convPfS_S_PiS0_S0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4convPfS_S_PiS0_S0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z19__device_stub__convPfS_S_PiS0_S0_, .Lfunc_end0-_Z19__device_stub__convPfS_S_PiS0_S0_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z10randomInitPfi
.LCPI1_0:
	.long	0x30000000                      # float 4.65661287E-10
	.text
	.globl	_Z10randomInitPfi
	.type	_Z10randomInitPfi,@function
_Z10randomInitPfi:                      # @_Z10randomInitPfi
	.cfi_startproc
# %bb.0:
	testl	%esi, %esi
	jle	.LBB1_4
# %bb.1:                                # %.lr.ph.preheader
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %rbx
	movl	%esi, %r14d
	xorl	%r15d, %r15d
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	.LCPI1_0(%rip), %xmm0
	movss	%xmm0, (%rbx,%r15,4)
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB1_2
# %bb.3:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r14
	.cfi_restore %r15
.LBB1_4:                                # %._crit_edge
	retq
.Lfunc_end1:
	.size	_Z10randomInitPfi, .Lfunc_end1-_Z10randomInitPfi
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function main
.LCPI2_0:
	.long	2                               # 0x2
	.long	3                               # 0x3
	.long	3                               # 0x3
	.long	3                               # 0x3
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0
.LCPI2_1:
	.long	0x30000000                      # float 4.65661287E-10
.LCPI2_2:
	.long	0x49742400                      # float 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movaps	.LCPI2_0(%rip), %xmm0           # xmm0 = [2,3,3,3]
	movaps	%xmm0, 80(%rsp)
	movabsq	$274877906947, %rax             # imm = 0x4000000003
	movq	%rax, 68(%rsp)
	movl	$64, 76(%rsp)
	movl	$49152, %edi                    # imm = 0xC000
	callq	malloc
	movq	%rax, %r15
	movl	$49152, %edi                    # imm = 0xC000
	callq	malloc
	movq	%rax, %r14
	movl	$49152, %edi                    # imm = 0xC000
	callq	malloc
	movq	%rax, %rbx
	xorl	%r12d, %r12d
.LBB2_1:                                # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	movss	.LCPI2_1(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	%xmm1, %xmm0
	movss	%xmm0, (%r15,%r12,4)
	incq	%r12
	cmpq	$12288, %r12                    # imm = 0x3000
	jne	.LBB2_1
# %bb.2:                                # %.lr.ph.i24.preheader
	xorl	%r12d, %r12d
.LBB2_3:                                # %.lr.ph.i24
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	.LCPI2_1(%rip), %xmm0
	movss	%xmm0, (%r14,%r12,4)
	incq	%r12
	cmpq	$54, %r12
	jne	.LBB2_3
# %bb.4:                                # %.lr.ph.i29.preheader
	xorl	%r12d, %r12d
.LBB2_5:                                # %.lr.ph.i29
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	.LCPI2_1(%rip), %xmm0
	movss	%xmm0, (%rbx,%r12,4)
	incq	%r12
	cmpq	$8192, %r12                     # imm = 0x2000
	jne	.LBB2_5
# %bb.6:                                # %_Z10randomInitPfi.exit33
	leaq	28(%rsp), %rax
	movl	$1, (%rax)
	leaq	48(%rsp), %r13
	movl	$49152, %esi                    # imm = 0xC000
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$49152, %esi                    # imm = 0xC000
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$49152, %esi                    # imm = 0xC000
	callq	hipMalloc
	leaq	40(%rsp), %rbp
	movl	$12, %esi
	movq	%rbp, %rdi
	callq	hipMalloc
	leaq	32(%rsp), %r12
	movl	$16, %esi
	movq	%r12, %rdi
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$4, %esi
	callq	hipMalloc
	movq	(%r13), %rdi
	movl	$49152, %edx                    # imm = 0xC000
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rax
	movq	(%rax), %rdi
	movl	$49152, %edx                    # imm = 0xC000
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	leaq	68(%rsp), %r14
	movl	$12, %edx
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	leaq	80(%rsp), %r15
	movl	$16, %edx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rsp, %rax
	movq	(%rax), %rdi
	movl	$4, %edx
	leaq	28(%rsp), %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	12(%r15), %eax
	movl	(%r15), %r12d
	movl	4(%r15), %ebp
	movl	8(%r15), %r13d
	shlq	$32, %r13
	orq	%rax, %r13
	movq	%r14, %rax
	movl	4(%r14), %r14d
	movl	8(%rax), %eax
	shlq	$32, %r14
	orq	%rax, %r14
	callq	clock
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	movl	12(%r15), %eax
	imull	8(%r15), %eax
	imull	4(%r15), %eax
	shll	$2, %eax
	movslq	%eax, %r8
	movq	%r14, %rdi
	movl	%r12d, %esi
	movq	%r13, %rdx
	movl	%ebp, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_8
# %bb.7:
	movq	48(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	16(%rsp), %rdx
	movq	40(%rsp), %rcx
	movq	32(%rsp), %r8
	movq	(%rsp), %r9
	callq	_Z19__device_stub__convPfS_S_PiS0_S0_
.LBB2_8:
	callq	clock
	movq	%rax, %r15
	movq	16(%rsp), %rsi
	movl	$49152, %edx                    # imm = 0xC000
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	subq	56(%rsp), %r15                  # 8-byte Folded Reload
	cvtsi2ss	%r15, %xmm0
	divss	.LCPI2_2(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4convPfS_S_PiS0_S0_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z4convPfS_S_PiS0_S0_,@object   # @_Z4convPfS_S_PiS0_S0_
	.section	.rodata,"a",@progbits
	.globl	_Z4convPfS_S_PiS0_S0_
	.p2align	3, 0x0
_Z4convPfS_S_PiS0_S0_:
	.quad	_Z19__device_stub__convPfS_S_PiS0_S0_
	.size	_Z4convPfS_S_PiS0_S0_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%f"
	.size	.L.str, 3

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z4convPfS_S_PiS0_S0_"
	.size	.L__unnamed_1, 22

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z19__device_stub__convPfS_S_PiS0_S0_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z4convPfS_S_PiS0_S0_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z4convPfS_S_PiS0_S0_   ; -- Begin function _Z4convPfS_S_PiS0_S0_
	.globl	_Z4convPfS_S_PiS0_S0_
	.p2align	8
	.type	_Z4convPfS_S_PiS0_S0_,@function
_Z4convPfS_S_PiS0_S0_:                  ; @_Z4convPfS_S_PiS0_S0_
; %bb.0:
	s_clause 0x1
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v6, v0, 10, 10
                                        ; implicit-def: $vgpr2
	s_waitcnt lgkmcnt(0)
	s_load_b32 s12, s[18:19], 0x0
	s_load_b64 s[2:3], s[10:11], 0x4
	s_load_b64 s[10:11], s[16:17], 0x4
	s_mov_b32 s18, 0
	s_waitcnt lgkmcnt(0)
	s_sub_i32 s0, s13, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s0, v1
	v_cmp_gt_i32_e32 vcc_lo, s3, v3
	v_cmp_lt_i32_e64 s0, -1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_xor_b32 s1, s0, -1
	s_and_saveexec_b32 s19, s0
; %bb.1:
	s_sub_i32 s0, s14, s12
	s_and_not1_b32 s1, s1, exec_lo
	v_add_nc_u32_e32 v2, s0, v6
	s_mov_b32 s18, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_le_i32_e32 vcc_lo, s2, v2
	v_cmp_gt_i32_e64 s0, 0, v2
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s1, s1, s0
; %bb.2:                                ; %Flow42
	s_or_b32 exec_lo, exec_lo, s19
	s_load_b32 s0, s[16:17], 0xc
	v_bfe_u32 v0, v0, 20, 10
                                        ; implicit-def: $sgpr16
                                        ; implicit-def: $vgpr4
	s_and_saveexec_b32 s17, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s17
	s_cbranch_execz .LBB0_4
; %bb.3:
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[7:8], null, s0, v6, v[1:2]
	s_mov_b32 s16, 0
	s_and_not1_b32 s18, s18, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s10, v7, v[0:1]
.LBB0_4:                                ; %Flow43
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v5, s16
	s_and_saveexec_b32 s1, s18
	s_cbranch_execz .LBB0_6
; %bb.5:
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, s2, v0, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[7:8], null, s0, v6, v[1:2]
	s_mul_i32 s18, s11, s0
	s_mov_b32 s17, 0
	s_mul_i32 s16, s18, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_mul_i32 s16, s16, s10
	v_mad_u64_u32 v[5:6], null, v4, s3, v[2:3]
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s18, v0, v[7:8]
	s_lshl_b64 s[16:17], s[16:17], 2
	v_mov_b32_e32 v2, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[5:6]
	s_add_u32 s6, s6, s16
	s_addc_u32 s7, s7, s17
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_load_b32 v3, v[3:4], off
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, s10, v7, v[0:1]
	v_mul_f32_e32 v5, v3, v1
.LBB0_6:                                ; %_Z9flat_convPfS_S_PiS0_S0_S0_.exit
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_2)
	v_lshl_add_u32 v0, v4, 2, 0
	v_bfrev_b32_e32 v2, 1
	s_mov_b32 s1, exec_lo
	ds_store_b32 v0, v5
.LBB0_7:                                ; %ComputeLoop
                                        ; =>This Inner Loop Header: Depth=1
	s_ctz_i32_b32 s4, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_readlane_b32 s5, v5, s4
	s_lshl_b32 s4, 1, s4
	s_and_not1_b32 s1, s1, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s1, 0
	v_add_f32_e32 v2, s5, v2
	s_cbranch_scc1 .LBB0_7
; %bb.8:                                ; %ComputeEnd
	v_mbcnt_lo_u32_b32 v0, exec_lo, 0
	s_mov_b32 s1, 0
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB0_11
; %bb.9:
	s_lshl_b32 s4, s12, 1
	v_mov_b32_e32 v3, 0
	s_add_i32 s3, s3, s4
	s_add_i32 s2, s2, s4
	s_waitcnt lgkmcnt(0)
	s_sub_i32 s0, s3, s0
	s_sub_i32 s2, s2, s11
	s_add_i32 s4, s0, 1
	s_add_i32 s2, s2, 1
	s_mul_i32 s0, s4, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s0, s0, s2
	s_lshl_b64 s[2:3], s[0:1], 2
	s_mul_i32 s0, s4, s13
	s_add_u32 s4, s8, s2
	s_addc_u32 s5, s9, s3
	s_add_i32 s0, s0, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[2:3], s[0:1], 2
	s_add_u32 s2, s4, s2
	s_addc_u32 s3, s5, s3
	s_load_b32 s0, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v1, s0
.LBB0_10:                               ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v0, v1, v2
	global_atomic_cmpswap_b32 v0, v3, v[0:1], s[2:3] glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v0, v1
	v_mov_b32_e32 v1, v0
	s_or_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_10
.LBB0_11:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4convPfS_S_PiS0_S0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 48
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z4convPfS_S_PiS0_S0_, .Lfunc_end0-_Z4convPfS_S_PiS0_S0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 664
; NumSgprs: 22
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 48
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4convPfS_S_PiS0_S0_
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z4convPfS_S_PiS0_S0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
