#include "includes.h"
__device__ __forceinline__ size_t gpu_fieldn_index(unsigned int x, unsigned int y, unsigned int d)
{
return (NX*(NY*(d-1)+y)+x);
}
__global__ void gpu_stream(double *f0, double *f1, double *f2, double *h0, double *h1, double *h2)
{
unsigned int y = blockIdx.y;
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;

// streaming step

unsigned int xp1 = (x + 1) % NX;
unsigned int yp1 = (y + 1) % NY;
unsigned int xm1 = (NX + x - 1) % NX;
unsigned int ym1 = (NY + y - 1) % NY;

// direction numbering scheme
// 6 2 5
// 3 0 1
// 7 4 8

// load populations from adjacent nodes (ft is post-streaming population of f1)
f1[gpu_fieldn_index(x, y, 1)] = f2[gpu_fieldn_index(xm1, y, 1)];
f1[gpu_fieldn_index(x, y, 2)] = f2[gpu_fieldn_index(x, ym1, 2)];
f1[gpu_fieldn_index(x, y, 3)] = f2[gpu_fieldn_index(xp1, y, 3)];
f1[gpu_fieldn_index(x, y, 4)] = f2[gpu_fieldn_index(x, yp1, 4)];
f1[gpu_fieldn_index(x, y, 5)] = f2[gpu_fieldn_index(xm1, ym1, 5)];
f1[gpu_fieldn_index(x, y, 6)] = f2[gpu_fieldn_index(xp1, ym1, 6)];
f1[gpu_fieldn_index(x, y, 7)] = f2[gpu_fieldn_index(xp1, yp1, 7)];
f1[gpu_fieldn_index(x, y, 8)] = f2[gpu_fieldn_index(xm1, yp1, 8)];

h1[gpu_fieldn_index(x, y, 1)] = h2[gpu_fieldn_index(xm1, y, 1)];
h1[gpu_fieldn_index(x, y, 2)] = h2[gpu_fieldn_index(x, ym1, 2)];
h1[gpu_fieldn_index(x, y, 3)] = h2[gpu_fieldn_index(xp1, y, 3)];
h1[gpu_fieldn_index(x, y, 4)] = h2[gpu_fieldn_index(x, yp1, 4)];
h1[gpu_fieldn_index(x, y, 5)] = h2[gpu_fieldn_index(xm1, ym1, 5)];
h1[gpu_fieldn_index(x, y, 6)] = h2[gpu_fieldn_index(xp1, ym1, 6)];
h1[gpu_fieldn_index(x, y, 7)] = h2[gpu_fieldn_index(xp1, yp1, 7)];
h1[gpu_fieldn_index(x, y, 8)] = h2[gpu_fieldn_index(xm1, yp1, 8)];
}
	.file	"tmpxft_002c968f_00000000-6_gpu_stream.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z40__device_stub__Z10gpu_streamPdS_S_S_S_S_PdS_S_S_S_S_
	.type	_Z40__device_stub__Z10gpu_streamPdS_S_S_S_S_PdS_S_S_S_S_, @function
_Z40__device_stub__Z10gpu_streamPdS_S_S_S_S_PdS_S_S_S_S_:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z10gpu_streamPdS_S_S_S_S_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z40__device_stub__Z10gpu_streamPdS_S_S_S_S_PdS_S_S_S_S_, .-_Z40__device_stub__Z10gpu_streamPdS_S_S_S_S_PdS_S_S_S_S_
	.globl	_Z10gpu_streamPdS_S_S_S_S_
	.type	_Z10gpu_streamPdS_S_S_S_S_, @function
_Z10gpu_streamPdS_S_S_S_S_:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z10gpu_streamPdS_S_S_S_S_PdS_S_S_S_S_
	.cfi_endproc
.LFE2034:
	.size	_Z10gpu_streamPdS_S_S_S_S_, .-_Z10gpu_streamPdS_S_S_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z10gpu_streamPdS_S_S_S_S_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10gpu_streamPdS_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__device__ __forceinline__ size_t gpu_fieldn_index(unsigned int x, unsigned int y, unsigned int d)
{
return (NX*(NY*(d-1)+y)+x);
}
__global__ void gpu_stream(double *f0, double *f1, double *f2, double *h0, double *h1, double *h2)
{
unsigned int y = blockIdx.y;
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;

// streaming step

unsigned int xp1 = (x + 1) % NX;
unsigned int yp1 = (y + 1) % NY;
unsigned int xm1 = (NX + x - 1) % NX;
unsigned int ym1 = (NY + y - 1) % NY;

// direction numbering scheme
// 6 2 5
// 3 0 1
// 7 4 8

// load populations from adjacent nodes (ft is post-streaming population of f1)
f1[gpu_fieldn_index(x, y, 1)] = f2[gpu_fieldn_index(xm1, y, 1)];
f1[gpu_fieldn_index(x, y, 2)] = f2[gpu_fieldn_index(x, ym1, 2)];
f1[gpu_fieldn_index(x, y, 3)] = f2[gpu_fieldn_index(xp1, y, 3)];
f1[gpu_fieldn_index(x, y, 4)] = f2[gpu_fieldn_index(x, yp1, 4)];
f1[gpu_fieldn_index(x, y, 5)] = f2[gpu_fieldn_index(xm1, ym1, 5)];
f1[gpu_fieldn_index(x, y, 6)] = f2[gpu_fieldn_index(xp1, ym1, 6)];
f1[gpu_fieldn_index(x, y, 7)] = f2[gpu_fieldn_index(xp1, yp1, 7)];
f1[gpu_fieldn_index(x, y, 8)] = f2[gpu_fieldn_index(xm1, yp1, 8)];

h1[gpu_fieldn_index(x, y, 1)] = h2[gpu_fieldn_index(xm1, y, 1)];
h1[gpu_fieldn_index(x, y, 2)] = h2[gpu_fieldn_index(x, ym1, 2)];
h1[gpu_fieldn_index(x, y, 3)] = h2[gpu_fieldn_index(xp1, y, 3)];
h1[gpu_fieldn_index(x, y, 4)] = h2[gpu_fieldn_index(x, yp1, 4)];
h1[gpu_fieldn_index(x, y, 5)] = h2[gpu_fieldn_index(xm1, ym1, 5)];
h1[gpu_fieldn_index(x, y, 6)] = h2[gpu_fieldn_index(xp1, ym1, 6)];
h1[gpu_fieldn_index(x, y, 7)] = h2[gpu_fieldn_index(xp1, yp1, 7)];
h1[gpu_fieldn_index(x, y, 8)] = h2[gpu_fieldn_index(xm1, yp1, 8)];
}
	.text
	.file	"gpu_stream.hip"
	.globl	_Z25__device_stub__gpu_streamPdS_S_S_S_S_ # -- Begin function _Z25__device_stub__gpu_streamPdS_S_S_S_S_
	.type	_Z25__device_stub__gpu_streamPdS_S_S_S_S_,@function
_Z25__device_stub__gpu_streamPdS_S_S_S_S_: # @_Z25__device_stub__gpu_streamPdS_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10gpu_streamPdS_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__gpu_streamPdS_S_S_S_S_, .Lfunc_end0-_Z25__device_stub__gpu_streamPdS_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10gpu_streamPdS_S_S_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10gpu_streamPdS_S_S_S_S_,@object # @_Z10gpu_streamPdS_S_S_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z10gpu_streamPdS_S_S_S_S_
	.p2align	3, 0x0
_Z10gpu_streamPdS_S_S_S_S_:
	.quad	_Z25__device_stub__gpu_streamPdS_S_S_S_S_
	.size	_Z10gpu_streamPdS_S_S_S_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z10gpu_streamPdS_S_S_S_S_"
	.size	.L__unnamed_1, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__gpu_streamPdS_S_S_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10gpu_streamPdS_S_S_S_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10gpu_streamPdS_S_S_S_S_ ; -- Begin function _Z10gpu_streamPdS_S_S_S_S_
	.globl	_Z10gpu_streamPdS_S_S_S_S_
	.p2align	8
	.type	_Z10gpu_streamPdS_S_S_S_S_,@function
_Z10gpu_streamPdS_S_S_S_S_:             ; @_Z10gpu_streamPdS_S_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b128 s[4:7], s[0:1], 0x8
	s_mul_i32 s8, s15, 0x7a
	s_add_i32 s9, s15, 0x64
	s_add_i32 s15, s15, 1
	s_mul_hi_u32 s10, s9, 0x446f8657
	v_mov_b32_e32 v3, 0
	s_sub_i32 s11, s9, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s11, s11, 1
	s_add_i32 s11, s11, s10
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v9, v3
	s_lshr_b32 s10, s11, 6
	s_mul_hi_u32 s11, s15, 0x446f8657
	s_mulk_i32 s10, 0x65
	s_sub_i32 s12, s15, s11
	s_sub_i32 s9, s9, s10
	s_add_i32 s10, s8, 0x6044
	s_mulk_i32 s9, 0x7a
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_lshr_b32 s12, s12, 1
	v_mad_u64_u32 v[1:2], null, s14, s2, v[0:1]
	s_add_i32 s12, s12, s11
	s_load_b128 s[0:3], s[0:1], 0x20
	s_lshr_b32 s11, s12, 6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mulk_i32 s11, 0x65
	v_add_nc_u32_e32 v0, 0x79, v1
	v_add_nc_u32_e32 v22, 0x9066, v1
	s_sub_i32 s11, s15, s11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, 0x4325c53f, v0
	v_lshrrev_b32_e32 v2, 5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, 0x7a, v2
	v_sub_nc_u32_e32 v28, v0, v2
	v_add_nc_u32_e32 v0, 0x3022, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, s8, v28
	v_lshlrev_b64 v[4:5], 3, v[2:3]
	v_add_nc_u32_e32 v2, s8, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[10:11], 3, v[2:3]
	v_add_co_u32 v6, vcc_lo, s6, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo
	v_add_co_u32 v12, vcc_lo, s4, v10
	global_load_b64 v[6:7], v[6:7], off
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v11, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[12:13], v[6:7], off
	v_add_nc_u32_e32 v12, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v13, 0x4325c53f, v12
	v_lshrrev_b32_e32 v13, 5, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v13, 0x7a, v13
	v_sub_nc_u32_e32 v26, v12, v13
	v_dual_mov_b32 v13, v3 :: v_dual_add_nc_u32 v8, s9, v0
	v_add_nc_u32_e32 v12, s8, v0
	v_dual_mov_b32 v1, v3 :: v_dual_add_nc_u32 v0, s10, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	v_lshlrev_b64 v[12:13], 3, v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v14, vcc_lo, s6, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v15, vcc_lo, s7, v9, vcc_lo
	v_add_co_u32 v16, vcc_lo, s4, v12
	v_add_co_ci_u32_e32 v17, vcc_lo, s5, v13, vcc_lo
	global_load_b64 v[6:7], v[14:15], off
	v_dual_mov_b32 v15, v3 :: v_dual_add_nc_u32 v14, s10, v26
	s_mul_i32 s10, s11, 0x7a
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 3, v[14:15]
	v_add_co_u32 v18, vcc_lo, s6, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v19, vcc_lo, s7, v15, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[16:17], v[6:7], off
	global_load_b64 v[6:7], v[18:19], off
	v_dual_mov_b32 v17, v3 :: v_dual_add_nc_u32 v16, s10, v22
	v_add_co_u32 v18, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[16:17], 3, v[16:17]
	v_add_co_u32 v20, vcc_lo, s6, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v21, vcc_lo, s7, v17, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[18:19], v[6:7], off
	global_load_b64 v[6:7], v[20:21], off
	v_dual_mov_b32 v19, v3 :: v_dual_add_nc_u32 v18, s8, v22
	s_add_i32 s8, s9, 0xc088
	s_add_i32 s9, s9, 0xf0aa
	v_add_lshl_u32 v29, s8, v28, 3
	v_add_lshl_u32 v30, s9, v26, 3
	v_lshlrev_b64 v[18:19], 3, v[18:19]
	s_add_i32 s8, s10, 0x120cc
	s_add_i32 s10, s10, 0x150ee
	v_add_lshl_u32 v31, s8, v26, 3
	v_add_lshl_u32 v28, s10, v28, 3
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v20, vcc_lo, s4, v18
	v_add_co_ci_u32_e32 v21, vcc_lo, s5, v19, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[20:21], v[6:7], off
	v_mov_b32_e32 v21, v3
	global_load_b64 v[6:7], v29, s[6:7]
	v_add_nc_u32_e32 v20, 0xc088, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[20:21], 3, v[20:21]
	v_add_co_u32 v22, vcc_lo, s4, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v23, vcc_lo, s5, v21, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[22:23], v[6:7], off
	global_load_b64 v[6:7], v30, s[6:7]
	v_dual_mov_b32 v23, v3 :: v_dual_add_nc_u32 v22, 0xf0aa, v2
	v_lshlrev_b64 v[22:23], 3, v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v24, vcc_lo, s4, v22
	v_add_co_ci_u32_e32 v25, vcc_lo, s5, v23, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[24:25], v[6:7], off
	global_load_b64 v[6:7], v31, s[6:7]
	v_dual_mov_b32 v25, v3 :: v_dual_add_nc_u32 v24, 0x120cc, v2
	v_add_nc_u32_e32 v2, 0x150ee, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[24:25], 3, v[24:25]
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v26, vcc_lo, s4, v24
	v_add_co_ci_u32_e32 v27, vcc_lo, s5, v25, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[26:27], v[6:7], off
	global_load_b64 v[6:7], v28, s[6:7]
	v_add_co_u32 v26, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v27, vcc_lo, s5, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[26:27], v[6:7], off
	global_load_b64 v[4:5], v[4:5], off
	v_add_co_u32 v6, vcc_lo, s0, v10
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v11, vcc_lo
	v_add_co_u32 v8, vcc_lo, s2, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[6:7], v[4:5], off
	global_load_b64 v[4:5], v[8:9], off
	v_add_co_u32 v6, vcc_lo, s0, v12
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v13, vcc_lo
	v_add_co_u32 v8, vcc_lo, s2, v14
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v15, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[6:7], v[4:5], off
	global_load_b64 v[4:5], v[8:9], off
	v_add_co_u32 v6, vcc_lo, s2, v16
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v17, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[0:1], v[4:5], off
	global_load_b64 v[0:1], v[6:7], off
	v_add_co_u32 v4, vcc_lo, s0, v18
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v19, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[4:5], v[0:1], off
	global_load_b64 v[0:1], v29, s[2:3]
	v_add_co_u32 v4, vcc_lo, s0, v20
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v21, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[4:5], v[0:1], off
	global_load_b64 v[0:1], v30, s[2:3]
	v_add_co_u32 v4, vcc_lo, s0, v22
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v23, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[4:5], v[0:1], off
	global_load_b64 v[0:1], v31, s[2:3]
	v_add_co_u32 v4, vcc_lo, s0, v24
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v25, vcc_lo
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[4:5], v[0:1], off
	global_load_b64 v[0:1], v28, s[2:3]
	s_waitcnt vmcnt(0)
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10gpu_streamPdS_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 32
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10gpu_streamPdS_S_S_S_S_, .Lfunc_end0-_Z10gpu_streamPdS_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1224
; NumSgprs: 18
; NumVgprs: 32
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 32
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10gpu_streamPdS_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10gpu_streamPdS_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     32
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
