/*
The shared memory is allocated using the __shared__ memory space specifier. 
Shared memory is expected to be much faster than global memory.

The following code sample is a straightforward implementation of matrix multiplication
that does not take advantage of shared memory. Each thread reads one row of A and one 
column of B and computes the corresponding element of C. A is therefore read B.columns 
times from global memory and B is read A.rows times.

Example adapted from the nVIDIA CUDA 9.1 samples
*/
#include <iostream>
#include <memory>
#include <algorithm>


struct Matrix{
	int num_rows;
	int num_columns;
	float* elements;
};

__global__
void matrixMult(const Matrix a, const Matrix b, Matrix c){
	
	float accumulate = 0.f;
	int row    = blockDim.y * blockIdx.y + threadIdx.y;
	int column = blockDim.x * blockIdx.x + threadIdx.x;
	printf("\nthreadIdx(%d) threadIdy(%d)\n",threadIdx.x,threadIdx.y);

	for(int i = 0; i != a.num_rows; ++i){
		accumulate += a.elements[row * a.num_columns + i] * b.elements[i * c.num_columns + column];
	}

	c.elements[row * c.num_columns + column] = accumulate;
}

int main(){
	
	size_t dimension = 3;
	size_t dimension_matrix = dimension * dimension; 
	Matrix h_A, h_B, h_C;
	
	h_A.num_rows 	= h_B.num_rows 	  = h_C.num_rows 	= dimension;
	h_A.num_columns = h_B.num_columns = h_C.num_columns = dimension;

	h_A.elements = (float*)malloc(dimension_matrix * sizeof(float));
	h_B.elements = (float*)malloc(dimension_matrix * sizeof(float));
	h_C.elements = (float*)malloc(dimension_matrix * sizeof(float));
	
	auto generate_element = [n = 1.f]() mutable {return (float)++n;};

	std::generate(h_A.elements, h_A.elements + (dimension_matrix), generate_element);
	std::generate(h_B.elements, h_B.elements + (dimension_matrix), generate_element);

	Matrix d_A, d_B, d_C;
	size_t size_bytes = dimension_matrix * sizeof(float);

	d_A.num_rows 	= d_B.num_rows 	  = d_C.num_rows 	= dimension;
	d_A.num_columns = d_B.num_columns = d_C.num_columns = dimension;

	cudaMalloc(&d_A.elements, size_bytes);
	cudaMalloc(&d_B.elements, size_bytes);
	cudaMalloc(&d_C.elements, size_bytes);

	cudaMemcpy(d_A.elements, h_A.elements, size_bytes, cudaMemcpyHostToDevice);
	cudaMemcpy(d_B.elements, h_B.elements, size_bytes, cudaMemcpyHostToDevice);

	// Launching kernel 
	size_t threads_per_block = dimension;
	dim3 dimBlock(threads_per_block,threads_per_block);
	dim3 dimGrid(h_B.num_columns / dimBlock.x, h_A.num_rows / dimBlock.y);
	std::cout << "\nLaunching CUDA kernel matrixMult<<<" << dimGrid.x 
		<< ", " << dimBlock.x << ">>>" << '\n'; 
		
	matrixMult<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);

	cudaMemcpy(h_C.elements, d_C.elements, size_bytes, cudaMemcpyDeviceToHost);

	cudaFree(d_A.elements);
	cudaFree(d_B.elements);
	cudaFree(d_C.elements);
	
	// Check Results
	for(size_t i = 0; i != dimension; ++i){
		for(size_t j = 0; j  != dimension; ++j){
			int accumulator = 0;
			for(size_t k = 0; k  != dimension; ++k)
				accumulator += h_A.elements[i * h_A.num_columns + k] * h_B.elements[k * h_B.num_columns + j];
			if(accumulator != h_C.elements[i * h_A.num_columns + j]){
					std::cerr << "Mismatch found in position " << i <<", " << j
						<< ": Expected = " << accumulator
						<< "  Obtained = " << h_C.elements[i * h_A.num_columns + j] << '\n';
					free(h_A.elements);
					free(h_B.elements);
					free(h_C.elements);
					exit(EXIT_FAILURE);
			}
		}
	}

	free(h_A.elements);
	free(h_B.elements);
	free(h_C.elements);

	std::cout << "\nSUCCESSFULLY EXECUTED!\n" << std::endl;
	return 0;

}

	.file	"tmpxft_003b4e92_00000000-6_matrixMul.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4513:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4513:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.isra.0, @function
_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.isra.0:
.LFB5194:
	.cfi_startproc
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	(%rdi), %rax
	movb	%sil, 12(%rsp)
	movq	-24(%rax), %rax
	cmpq	$0, 16(%rdi,%rax)
	je	.L3
	leaq	12(%rsp), %rsi
	movl	$1, %edx
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	jmp	.L2
.L3:
	movsbl	12(%rsp), %esi
	call	_ZNSo3putEc@PLT
.L2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE5194:
	.size	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.isra.0, .-_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.isra.0
	.globl	_Z39__device_stub__Z10matrixMult6MatrixS_S_RK6MatrixS1_RS_
	.type	_Z39__device_stub__Z10matrixMult6MatrixS_S_RK6MatrixS1_RS_, @function
_Z39__device_stub__Z10matrixMult6MatrixS_S_RK6MatrixS1_RS_:
.LFB4535:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rcx
	movq	%rdi, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rsi, 72(%rsp)
	leaq	16(%rsp), %rdi
	leaq	28(%rsp), %rsi
	movq	%rdx, 80(%rsp)
	movq	%rsp, %rdx
	movq	%rax, 16(%rsp)
	movl	$1, 24(%rsp)
	movq	%rax, 28(%rsp)
	movl	$1, 36(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L7
	pushq	8(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z10matrixMult6MatrixS_S_(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 128
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L7:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4535:
	.size	_Z39__device_stub__Z10matrixMult6MatrixS_S_RK6MatrixS1_RS_, .-_Z39__device_stub__Z10matrixMult6MatrixS_S_RK6MatrixS1_RS_
	.globl	_Z10matrixMult6MatrixS_S_
	.type	_Z10matrixMult6MatrixS_S_, @function
_Z10matrixMult6MatrixS_S_:
.LFB4536:
	.cfi_startproc
	endbr64
	subq	$56, %rsp
	.cfi_def_cfa_offset 64
	movq	%rdi, 32(%rsp)
	leaq	32(%rsp), %rdi
	movq	%rsi, 40(%rsp)
	leaq	16(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	movq	%rsp, %rdx
	movq	%rcx, 24(%rsp)
	movq	%r8, (%rsp)
	movq	%r9, 8(%rsp)
	call	_Z39__device_stub__Z10matrixMult6MatrixS_S_RK6MatrixS1_RS_
	addq	$56, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4536:
	.size	_Z10matrixMult6MatrixS_S_, .-_Z10matrixMult6MatrixS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"\nLaunching CUDA kernel matrixMult<<<"
.LC2:
	.string	", "
.LC3:
	.string	">>>"
.LC4:
	.string	"Mismatch found in position "
.LC5:
	.string	": Expected = "
.LC6:
	.string	"  Obtained = "
.LC7:
	.string	"\nSUCCESSFULLY EXECUTED!\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB4509:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$36, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$152, %rsp
	.cfi_def_cfa_offset 208
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$36, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$36, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movss	.LC0(%rip), %xmm0
	movq	%rax, %r12
	xorl	%eax, %eax
	movaps	%xmm0, %xmm1
.L14:
	addss	%xmm1, %xmm0
	movss	%xmm0, 0(%rbp,%rax)
	addq	$4, %rax
	cmpq	$36, %rax
	jne	.L14
	movaps	%xmm1, %xmm0
	xorl	%eax, %eax
.L15:
	addss	%xmm1, %xmm0
	movss	%xmm0, (%rbx,%rax)
	addq	$4, %rax
	cmpq	$36, %rax
	jne	.L15
	movabsq	$12884901891, %r13
	leaq	48(%rsp), %rdi
	movl	$36, %esi
	movq	%r13, 72(%rsp)
	movq	%r13, 56(%rsp)
	movq	%r13, 40(%rsp)
	call	cudaMalloc@PLT
	leaq	64(%rsp), %rdi
	movl	$36, %esi
	call	cudaMalloc@PLT
	leaq	80(%rsp), %rdi
	movl	$36, %esi
	call	cudaMalloc@PLT
	movq	48(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$36, %edx
	call	cudaMemcpy@PLT
	movq	64(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$36, %edx
	call	cudaMemcpy@PLT
	leaq	.LC1(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$1, %esi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertImEERSoT_@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$3, %esi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertImEERSoT_@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$10, %esi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.isra.0
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r13, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	movups	40(%rsp), %xmm2
	movups	56(%rsp), %xmm3
	leaq	120(%rsp), %rdx
	leaq	104(%rsp), %rsi
	movups	72(%rsp), %xmm4
	leaq	88(%rsp), %rdi
	movups	%xmm2, 88(%rsp)
	movups	%xmm3, 104(%rsp)
	movups	%xmm4, 120(%rsp)
	call	_Z39__device_stub__Z10matrixMult6MatrixS_S_RK6MatrixS1_RS_
.L16:
	movq	80(%rsp), %rsi
	movl	$2, %ecx
	movq	%r12, %rdi
	xorl	%r15d, %r15d
	movl	$36, %edx
	call	cudaMemcpy@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	xorl	%eax, %eax
.L17:
	leaq	(%r12,%rax), %r14
	xorl	%r13d, %r13d
	leaq	0(%rbp,%rax), %r9
.L23:
	leaq	(%rbx,%r13,4), %rdi
	xorl	%esi, %esi
	xorl	%r8d, %r8d
.L18:
	movss	(%r9,%rsi,4), %xmm0
	mulss	(%rdi), %xmm0
	cvtsi2ssl	%r8d, %xmm1
	incq	%rsi
	addq	$12, %rdi
	addss	%xmm1, %xmm0
	cvttss2sil	%xmm0, %r8d
	cmpq	$3, %rsi
	jne	.L18
	cvtsi2ssl	%r8d, %xmm0
	ucomiss	(%r14), %xmm0
	jp	.L25
	je	.L19
.L25:
	leaq	.LC4(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	movl	%r8d, 12(%rsp)
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%r15, %rsi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertImEERSoT_@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%r13, %rsi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertImEERSoT_@PLT
	leaq	.LC5(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	12(%rsp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC6(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	(%r14), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movl	$10, %esi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.isra.0
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movl	$1, %edi
	call	exit@PLT
.L19:
	incq	%r13
	addq	$4, %r14
	cmpq	$3, %r13
	jne	.L23
	incq	%r15
	addq	$12, %rax
	cmpq	$3, %r15
	jne	.L17
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	leaq	_ZSt4cout(%rip), %rdi
	leaq	.LC7(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$152, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4509:
	.size	main, .-main
	.section	.rodata.str1.1
.LC8:
	.string	"_Z10matrixMult6MatrixS_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4538:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10matrixMult6MatrixS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4538:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1065353216
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
The shared memory is allocated using the __shared__ memory space specifier. 
Shared memory is expected to be much faster than global memory.

The following code sample is a straightforward implementation of matrix multiplication
that does not take advantage of shared memory. Each thread reads one row of A and one 
column of B and computes the corresponding element of C. A is therefore read B.columns 
times from global memory and B is read A.rows times.

Example adapted from the nVIDIA CUDA 9.1 samples
*/

#include <hip/hip_runtime.h>
#include <iostream>
#include <memory>
#include <algorithm>


struct Matrix{
	int num_rows;
	int num_columns;
	float* elements;
};

__global__
void matrixMult(const Matrix a, const Matrix b, Matrix c){
	
	float accumulate = 0.f;
	int row    = blockDim.y * blockIdx.y + threadIdx.y;
	int column = blockDim.x * blockIdx.x + threadIdx.x;
	printf("\nthreadIdx(%d) threadIdy(%d)\n",threadIdx.x,threadIdx.y);

	for(int i = 0; i != a.num_rows; ++i){
		accumulate += a.elements[row * a.num_columns + i] * b.elements[i * c.num_columns + column];
	}

	c.elements[row * c.num_columns + column] = accumulate;
}

int main(){
	
	size_t dimension = 3;
	size_t dimension_matrix = dimension * dimension; 
	Matrix h_A, h_B, h_C;
	
	h_A.num_rows 	= h_B.num_rows 	  = h_C.num_rows 	= dimension;
	h_A.num_columns = h_B.num_columns = h_C.num_columns = dimension;

	h_A.elements = (float*)malloc(dimension_matrix * sizeof(float));
	h_B.elements = (float*)malloc(dimension_matrix * sizeof(float));
	h_C.elements = (float*)malloc(dimension_matrix * sizeof(float));
	
	auto generate_element = [n = 1.f]() mutable {return (float)++n;};

	std::generate(h_A.elements, h_A.elements + (dimension_matrix), generate_element);
	std::generate(h_B.elements, h_B.elements + (dimension_matrix), generate_element);

	Matrix d_A, d_B, d_C;
	size_t size_bytes = dimension_matrix * sizeof(float);

	d_A.num_rows 	= d_B.num_rows 	  = d_C.num_rows 	= dimension;
	d_A.num_columns = d_B.num_columns = d_C.num_columns = dimension;

	hipMalloc(&d_A.elements, size_bytes);
	hipMalloc(&d_B.elements, size_bytes);
	hipMalloc(&d_C.elements, size_bytes);

	hipMemcpy(d_A.elements, h_A.elements, size_bytes, hipMemcpyHostToDevice);
	hipMemcpy(d_B.elements, h_B.elements, size_bytes, hipMemcpyHostToDevice);

	// Launching kernel 
	size_t threads_per_block = dimension;
	dim3 dimBlock(threads_per_block,threads_per_block);
	dim3 dimGrid(h_B.num_columns / dimBlock.x, h_A.num_rows / dimBlock.y);
	std::cout << "\nLaunching CUDA kernel matrixMult<<<" << dimGrid.x 
		<< ", " << dimBlock.x << ">>>" << '\n'; 
		
	matrixMult<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);

	hipMemcpy(h_C.elements, d_C.elements, size_bytes, hipMemcpyDeviceToHost);

	hipFree(d_A.elements);
	hipFree(d_B.elements);
	hipFree(d_C.elements);
	
	// Check Results
	for(size_t i = 0; i != dimension; ++i){
		for(size_t j = 0; j  != dimension; ++j){
			int accumulator = 0;
			for(size_t k = 0; k  != dimension; ++k)
				accumulator += h_A.elements[i * h_A.num_columns + k] * h_B.elements[k * h_B.num_columns + j];
			if(accumulator != h_C.elements[i * h_A.num_columns + j]){
					std::cerr << "Mismatch found in position " << i <<", " << j
						<< ": Expected = " << accumulator
						<< "  Obtained = " << h_C.elements[i * h_A.num_columns + j] << '\n';
					free(h_A.elements);
					free(h_B.elements);
					free(h_C.elements);
					exit(EXIT_FAILURE);
			}
		}
	}

	free(h_A.elements);
	free(h_B.elements);
	free(h_C.elements);

	std::cout << "\nSUCCESSFULLY EXECUTED!\n" << std::endl;
	return 0;

}

	.text
	.file	"matrixMul.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z25__device_stub__matrixMult6MatrixS_S_ # -- Begin function _Z25__device_stub__matrixMult6MatrixS_S_
	.type	_Z25__device_stub__matrixMult6MatrixS_S_,@function
_Z25__device_stub__matrixMult6MatrixS_S_: # @_Z25__device_stub__matrixMult6MatrixS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	80(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsi, 8(%rax)
	leaq	64(%rsp), %rsi
	movq	%rdx, (%rsi)
	movq	%rcx, 8(%rsi)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	movq	%r9, 8(%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rsi, 8(%rbx)
	movq	%rcx, 16(%rbx)
	leaq	32(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10matrixMult6MatrixS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__matrixMult6MatrixS_S_, .Lfunc_end0-_Z25__device_stub__matrixMult6MatrixS_S_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x3f800000                      # float 1
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$36, %edi
	callq	malloc
	movq	%rax, %r15
	movl	$36, %edi
	callq	malloc
	movq	%rax, %r14
	movl	$36, %edi
	callq	malloc
	movq	%rax, %rbx
	movss	.LCPI1_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	xorl	%ecx, %ecx
	movaps	%xmm0, %xmm1
.LBB1_1:                                # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	addss	%xmm0, %xmm1
	movss	%xmm1, (%r15,%rcx)
	addq	$4, %rcx
	cmpq	$36, %rcx
	jne	.LBB1_1
# %bb.2:                                # %.lr.ph.i87.preheader
	movss	.LCPI1_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	xorl	%eax, %eax
	movaps	%xmm0, %xmm1
.LBB1_3:                                # %.lr.ph.i87
                                        # =>This Inner Loop Header: Depth=1
	addss	%xmm0, %xmm1
	movss	%xmm1, (%r14,%rax)
	addq	$4, %rax
	cmpq	$36, %rax
	jne	.LBB1_3
# %bb.4:                                # %_ZSt8generateIPfZ4mainEUlvE_EvT_S2_T0_.exit91
	movabsq	$12884901891, %rax              # imm = 0x300000003
	leaq	24(%rsp), %r13
	movq	%rax, -8(%r13)
	leaq	48(%rsp), %r12
	movq	%rax, -8(%r12)
	leaq	64(%rsp), %rbp
	movq	%rax, -8(%rbp)
	movl	$36, %esi
	movq	%rbp, %rdi
	callq	hipMalloc
	movl	$36, %esi
	movq	%r12, %rdi
	callq	hipMalloc
	movl	$36, %esi
	movq	%r13, %rdi
	callq	hipMalloc
	movq	(%rbp), %rdi
	movl	$36, %edx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movl	$36, %edx
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$36, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$1, %esi
	callq	_ZNSo9_M_insertImEERSoT_
	movq	%rax, %r12
	movl	$.L.str.1, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$3, %esi
	movq	%r12, %rdi
	callq	_ZNSo9_M_insertImEERSoT_
	movq	%rax, %r12
	movl	$.L.str.2, %esi
	movl	$3, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movb	$10, 15(%rsp)
	movq	(%r12), %rax
	movq	-24(%rax), %rax
	cmpq	$0, 16(%r12,%rax)
	je	.LBB1_6
# %bb.5:
	leaq	15(%rsp), %rsi
	movl	$1, %edx
	movq	%r12, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_7
.LBB1_6:
	movq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNSo3putEc
.LBB1_7:                                # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movabsq	$12884901891, %rdx              # imm = 0x300000003
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_9
# %bb.8:
	movq	56(%rsp), %rdi
	movq	64(%rsp), %rsi
	movq	40(%rsp), %rdx
	movq	48(%rsp), %rcx
	movq	16(%rsp), %r8
	movq	24(%rsp), %r9
	callq	_Z25__device_stub__matrixMult6MatrixS_S_
.LBB1_9:
	movq	24(%rsp), %rsi
	movl	$36, %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	64(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	xorl	%r13d, %r13d
	movq	%r15, %rax
.LBB1_10:                               # %.preheader98
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_11 Depth 2
                                        #       Child Loop BB1_12 Depth 3
	leaq	(,%r13,2), %rcx
	addq	%r13, %rcx
	leaq	(%rdi,%rcx,4), %rbx
	movq	%r14, %rcx
	xorl	%r12d, %r12d
.LBB1_11:                               # %.preheader
                                        #   Parent Loop BB1_10 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB1_12 Depth 3
	xorl	%edx, %edx
	movq	%rcx, %rsi
	xorl	%ebp, %ebp
.LBB1_12:                               #   Parent Loop BB1_10 Depth=1
                                        #     Parent Loop BB1_11 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%rax,%rdx,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	mulss	(%rsi), %xmm0
	xorps	%xmm1, %xmm1
	cvtsi2ss	%ebp, %xmm1
	addss	%xmm0, %xmm1
	cvttss2si	%xmm1, %ebp
	incq	%rdx
	addq	$12, %rsi
	cmpq	$3, %rdx
	jne	.LBB1_12
# %bb.13:                               #   in Loop: Header=BB1_11 Depth=2
	xorps	%xmm0, %xmm0
	cvtsi2ss	%ebp, %xmm0
	movss	(%rbx,%r12,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	ucomiss	%xmm0, %xmm1
	jne	.LBB1_17
	jp	.LBB1_17
# %bb.14:                               #   in Loop: Header=BB1_11 Depth=2
	incq	%r12
	addq	$4, %rcx
	cmpq	$3, %r12
	jne	.LBB1_11
# %bb.15:                               #   in Loop: Header=BB1_10 Depth=1
	incq	%r13
	addq	$12, %rax
	cmpq	$3, %r13
	jne	.LBB1_10
# %bb.16:
	movq	%rdi, %rbx
	movq	%r15, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%rbx, %rdi
	callq	free
	movl	$_ZSt4cout, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str.6, %esi
	movl	$24, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	xorl	%eax, %eax
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_17:
	.cfi_def_cfa_offset 128
	movq	%rdi, 32(%rsp)                  # 8-byte Spill
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.3, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movq	%r13, %rsi
	callq	_ZNSolsEm
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movq	%r12, %rsi
	callq	_ZNSolsEm
	movl	$.L.str.4, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	%ebp, %esi
	callq	_ZNSolsEi
	movl	$.L.str.5, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movss	(%rbx,%r12,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	movq	%rax, %rdi
	callq	_ZNSolsEf
	movq	%rax, %rdi
	movl	$10, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c
	movq	%r15, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	32(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movl	$1, %edi
	callq	exit
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10matrixMult6MatrixS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10matrixMult6MatrixS_S_,@object # @_Z10matrixMult6MatrixS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z10matrixMult6MatrixS_S_
	.p2align	3, 0x0
_Z10matrixMult6MatrixS_S_:
	.quad	_Z25__device_stub__matrixMult6MatrixS_S_
	.size	_Z10matrixMult6MatrixS_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"\nLaunching CUDA kernel matrixMult<<<"
	.size	.L.str, 37

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	", "
	.size	.L.str.1, 3

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	">>>"
	.size	.L.str.2, 4

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Mismatch found in position "
	.size	.L.str.3, 28

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	": Expected = "
	.size	.L.str.4, 14

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"  Obtained = "
	.size	.L.str.5, 14

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"\nSUCCESSFULLY EXECUTED!\n"
	.size	.L.str.6, 25

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10matrixMult6MatrixS_S_"
	.size	.L__unnamed_1, 26

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__matrixMult6MatrixS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10matrixMult6MatrixS_S_
	.addrsig_sym _ZSt4cout
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10matrixMult6MatrixS_S_ ; -- Begin function _Z10matrixMult6MatrixS_S_
	.globl	_Z10matrixMult6MatrixS_S_
	.p2align	8
	.type	_Z10matrixMult6MatrixS_S_,@function
_Z10matrixMult6MatrixS_S_:              ; @_Z10matrixMult6MatrixS_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s24, s[0:1], 0x3c
	s_load_b64 s[8:9], s[0:1], 0x80
	v_mbcnt_lo_u32_b32 v27, -1, 0
	v_mov_b32_e32 v7, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v5, v27
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s2, s2, v5
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_6
; %bb.1:
	v_mov_b32_e32 v1, 0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[9:10], v1, s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[2:3], v1, s[8:9] offset:40
	global_load_b64 v[6:7], v1, s[8:9]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, v2, v9
	v_and_b32_e32 v3, v3, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v3, v3, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo
	global_load_b64 v[7:8], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[7:8], v1, v[7:10], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[7:8], v[9:10]
	s_cbranch_execz .LBB0_5
; %bb.2:                                ; %.preheader3.i.i.i.preheader
	s_mov_b32 s5, 0
.LBB0_3:                                ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[2:3], v1, s[8:9] offset:40
	global_load_b64 v[11:12], v1, s[8:9]
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v2, v9
	v_and_b32_e32 v8, v3, v10
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v2, 24, v[11:12]
	v_mov_b32_e32 v2, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, v8, 24, v[2:3]
	v_mov_b32_e32 v7, v3
	global_load_b64 v[7:8], v[6:7], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[7:8], v1, v[7:10], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_3
; %bb.4:                                ; %Flow404
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:                                ; %Flow406
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:                                ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v6, 0
	v_readfirstlane_b32 s16, v7
	v_readfirstlane_b32 s17, v8
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[9:10], v6, s[8:9] offset:40
	global_load_b128 v[1:4], v6, s[8:9]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v9
	v_readfirstlane_b32 s7, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[16:17], s[6:7]
	s_mul_i32 s3, s11, 24
	s_mul_hi_u32 s18, s10, 24
	s_mul_i32 s19, s10, 24
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB0_8
; %bb.7:
	v_dual_mov_b32 v7, s4 :: v_dual_mov_b32 v8, v6
	s_add_i32 s4, s18, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v1, s19
	v_add_co_ci_u32_e32 v12, vcc_lo, s4, v2, vcc_lo
	v_dual_mov_b32 v9, 2 :: v_dual_mov_b32 v10, 1
	global_store_b128 v[11:12], v[7:10], off offset:8
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s5
	s_lshl_b64 s[10:11], s[10:11], 12
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[12:13], s[0:1], 0x18
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v3, s10
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	s_load_b64 s[10:11], s[0:1], 0x28
	v_lshlrev_b64 v[7:8], 6, v[5:6]
	s_mov_b32 s20, 0
	v_mov_b32_e32 v5, 33
	s_mov_b32 s21, s20
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_add_co_u32 v9, vcc_lo, v3, v7
	v_add_co_ci_u32_e32 v10, vcc_lo, v4, v8, vcc_lo
	v_mov_b32_e32 v8, v6
	v_mov_b32_e32 v7, v6
	v_dual_mov_b32 v11, s20 :: v_dual_mov_b32 v14, s23
	v_dual_mov_b32 v12, s21 :: v_dual_mov_b32 v13, s22
	s_clause 0x3
	global_store_b128 v[9:10], v[5:8], off
	global_store_b128 v[9:10], v[11:14], off offset:16
	global_store_b128 v[9:10], v[11:14], off offset:32
	global_store_b128 v[9:10], v[11:14], off offset:48
	s_and_saveexec_b32 s20, s2
	s_cbranch_execz .LBB0_16
; %bb.9:
	v_mov_b32_e32 v11, 0
	s_mov_b32 s21, exec_lo
	s_clause 0x1
	global_load_b64 v[14:15], v11, s[8:9] offset:32 glc
	global_load_b64 v[3:4], v11, s[8:9] offset:40
	v_dual_mov_b32 v12, s16 :: v_dual_mov_b32 v13, s17
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, s17, v4
	v_and_b32_e32 v3, s16, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v5, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v5, v4
	v_add_co_u32 v7, vcc_lo, v1, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, v2, v4, vcc_lo
	global_store_b64 v[7:8], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v11, v[12:15], s[8:9] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[5:6], v[14:15]
	s_cbranch_execz .LBB0_12
; %bb.10:                               ; %.preheader1.i.i.i.preheader
	s_mov_b32 s22, 0
.LBB0_11:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v3, s16 :: v_dual_mov_b32 v4, s17
	s_sleep 1
	global_store_b64 v[7:8], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v11, v[3:6], s[8:9] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	s_or_b32 s22, vcc_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s22
	s_cbranch_execnz .LBB0_11
.LBB0_12:                               ; %Flow402
	s_or_b32 exec_lo, exec_lo, s21
	v_mov_b32_e32 v6, 0
	s_mov_b32 s22, exec_lo
	s_mov_b32 s21, exec_lo
	v_mbcnt_lo_u32_b32 v5, s22, 0
	global_load_b64 v[3:4], v6, s[8:9] offset:16
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_14
; %bb.13:
	s_bcnt1_i32_b32 s22, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s22
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[5:6], off offset:8
.LBB0_14:
	s_or_b32 exec_lo, exec_lo, s21
	s_waitcnt vmcnt(0)
	global_load_b64 v[5:6], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
	s_cbranch_vccnz .LBB0_16
; %bb.15:
	global_load_b32 v3, v[3:4], off offset:24
	v_mov_b32_e32 v4, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s21, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[5:6], v[3:4], off
	s_and_b32 m0, s21, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:                               ; %Flow403
	s_or_b32 exec_lo, exec_lo, s20
	s_load_b32 s25, s[0:1], 0x24
	s_add_i32 s18, s18, s3
	v_add_co_u32 v1, vcc_lo, v1, s19
	v_add_co_ci_u32_e32 v2, vcc_lo, s18, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
.LBB0_17:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v3, 1
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_19
; %bb.18:                               ;   in Loop: Header=BB0_17 Depth=1
	global_load_b32 v3, v[1:2], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v3, 1, v3
.LBB0_19:                               ;   in Loop: Header=BB0_17 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v3
	s_cmp_eq_u32 s0, 0
	s_cbranch_scc1 .LBB0_21
; %bb.20:                               ;   in Loop: Header=BB0_17 Depth=1
	s_mov_b32 s0, 0
	s_sleep 1
	s_branch .LBB0_22
.LBB0_21:                               ;   in Loop: Header=BB0_17 Depth=1
	s_mov_b32 s0, -1
.LBB0_22:                               ; %Flow397
                                        ;   in Loop: Header=BB0_17 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_17
; %bb.23:
	global_load_b64 v[5:6], v[9:10], off
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_27
; %bb.24:
	v_mov_b32_e32 v9, 0
	s_clause 0x2
	global_load_b64 v[3:4], v9, s[8:9] offset:40
	global_load_b64 v[10:11], v9, s[8:9] offset:24 glc
	global_load_b64 v[7:8], v9, s[8:9]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v12, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v12, s16
	v_add_co_ci_u32_e32 v2, vcc_lo, s17, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[1:2]
	v_dual_cndmask_b32 v2, v2, v13 :: v_dual_cndmask_b32 v1, v1, v12
	v_and_b32_e32 v4, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v1, v3
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v12, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v4, v12, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v7, v3
	v_mov_b32_e32 v3, v10
	v_add_co_ci_u32_e32 v8, vcc_lo, v8, v4, vcc_lo
	v_mov_b32_e32 v4, v11
	global_store_b64 v[7:8], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v9, v[1:4], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[3:4], v[10:11]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_27
; %bb.25:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s1, 0
.LBB0_26:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[7:8], v[3:4], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v9, v[1:4], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[3:4]
	v_dual_mov_b32 v3, v10 :: v_dual_mov_b32 v4, v11
	s_or_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_26
.LBB0_27:                               ; %__ockl_printf_begin.exit
	s_or_b32 exec_lo, exec_lo, s0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, .str@rel32@lo+4
	s_addc_u32 s3, s3, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[2:3], 0
	s_cbranch_scc0 .LBB0_113
; %bb.28:
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v29, 0 :: v_dual_and_b32 v30, 2, v5
	v_dual_mov_b32 v2, v6 :: v_dual_and_b32 v1, -3, v5
	v_dual_mov_b32 v9, 2 :: v_dual_mov_b32 v10, 1
	s_mov_b64 s[16:17], 30
.LBB0_29:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_32 Depth 2
                                        ;     Child Loop BB0_39 Depth 2
                                        ;     Child Loop BB0_47 Depth 2
                                        ;     Child Loop BB0_55 Depth 2
                                        ;     Child Loop BB0_63 Depth 2
                                        ;     Child Loop BB0_71 Depth 2
                                        ;     Child Loop BB0_79 Depth 2
                                        ;     Child Loop BB0_87 Depth 2
                                        ;     Child Loop BB0_95 Depth 2
                                        ;     Child Loop BB0_101 Depth 2
                                        ;     Child Loop BB0_110 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[16:17], 56
                                        ; implicit-def: $vgpr3_vgpr4
                                        ; implicit-def: $sgpr27
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s18, s16, 56
	s_cselect_b32 s19, s17, 0
	s_cmp_gt_u32 s18, 7
	s_mov_b32 s0, -1
	s_cbranch_scc1 .LBB0_34
; %bb.30:                               ;   in Loop: Header=BB0_29 Depth=1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	s_cmp_eq_u32 s18, 0
	s_cbranch_scc1 .LBB0_33
; %bb.31:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_lshl_b64 s[0:1], s[18:19], 3
	s_mov_b64 s[20:21], 0
	s_mov_b64 s[22:23], s[2:3]
.LBB0_32:                               ; %.preheader31.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v7, v29, s[22:23]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v28, 0xffff, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], s20, v[28:29]
	s_add_u32 s20, s20, 8
	s_addc_u32 s21, s21, 0
	s_add_u32 s22, s22, 1
	s_addc_u32 s23, s23, 0
	s_cmp_lg_u32 s0, s20
	v_or_b32_e32 v3, v7, v3
	v_or_b32_e32 v4, v8, v4
	s_cbranch_scc1 .LBB0_32
.LBB0_33:                               ; %Flow373
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s0, 0
	s_mov_b32 s27, 0
.LBB0_34:                               ; %Flow375
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[2:3]
	s_cbranch_vccnz .LBB0_36
; %bb.35:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[3:4], v29, s[2:3]
	s_add_i32 s27, s18, -8
	s_add_u32 s0, s2, 8
	s_addc_u32 s1, s3, 0
.LBB0_36:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_cmp_gt_u32 s27, 7
	s_cbranch_scc1 .LBB0_41
; %bb.37:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v11, 0
	v_mov_b32_e32 v12, 0
	s_cmp_eq_u32 s27, 0
	s_cbranch_scc1 .LBB0_40
; %bb.38:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b64 s[20:21], 0
	s_mov_b64 s[22:23], 0
.LBB0_39:                               ; %.preheader29.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s28, s0, s22
	s_addc_u32 s29, s1, s23
	s_add_u32 s22, s22, 1
	global_load_u8 v7, v29, s[28:29]
	s_addc_u32 s23, s23, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v28, 0xffff, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], s20, v[28:29]
	s_add_u32 s20, s20, 8
	s_addc_u32 s21, s21, 0
	s_cmp_lg_u32 s27, s22
	v_or_b32_e32 v11, v7, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v12, v8, v12
	s_cbranch_scc1 .LBB0_39
.LBB0_40:                               ; %Flow368
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s20, 0
	s_mov_b32 s26, 0
	s_branch .LBB0_42
.LBB0_41:                               ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s20, -1
                                        ; implicit-def: $vgpr11_vgpr12
                                        ; implicit-def: $sgpr26
.LBB0_42:                               ; %Flow370
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s20
	s_cbranch_vccnz .LBB0_44
; %bb.43:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[11:12], v29, s[0:1]
	s_add_i32 s26, s27, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_44:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_cmp_gt_u32 s26, 7
	s_cbranch_scc1 .LBB0_49
; %bb.45:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_cmp_eq_u32 s26, 0
	s_cbranch_scc1 .LBB0_48
; %bb.46:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b64 s[20:21], 0
	s_mov_b64 s[22:23], 0
.LBB0_47:                               ; %.preheader27.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s28, s0, s22
	s_addc_u32 s29, s1, s23
	s_add_u32 s22, s22, 1
	global_load_u8 v7, v29, s[28:29]
	s_addc_u32 s23, s23, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v28, 0xffff, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], s20, v[28:29]
	s_add_u32 s20, s20, 8
	s_addc_u32 s21, s21, 0
	s_cmp_lg_u32 s26, s22
	v_or_b32_e32 v13, v7, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v14, v8, v14
	s_cbranch_scc1 .LBB0_47
.LBB0_48:                               ; %Flow363
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s20, 0
	s_mov_b32 s27, 0
	s_branch .LBB0_50
.LBB0_49:                               ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s20, -1
                                        ; implicit-def: $sgpr27
.LBB0_50:                               ; %Flow365
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s20
	s_cbranch_vccnz .LBB0_52
; %bb.51:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[13:14], v29, s[0:1]
	s_add_i32 s27, s26, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_52:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_cmp_gt_u32 s27, 7
	s_cbranch_scc1 .LBB0_57
; %bb.53:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_cmp_eq_u32 s27, 0
	s_cbranch_scc1 .LBB0_56
; %bb.54:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b64 s[20:21], 0
	s_mov_b64 s[22:23], 0
.LBB0_55:                               ; %.preheader25.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s28, s0, s22
	s_addc_u32 s29, s1, s23
	s_add_u32 s22, s22, 1
	global_load_u8 v7, v29, s[28:29]
	s_addc_u32 s23, s23, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v28, 0xffff, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], s20, v[28:29]
	s_add_u32 s20, s20, 8
	s_addc_u32 s21, s21, 0
	s_cmp_lg_u32 s27, s22
	v_or_b32_e32 v15, v7, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v16, v8, v16
	s_cbranch_scc1 .LBB0_55
.LBB0_56:                               ; %Flow358
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s20, 0
	s_mov_b32 s26, 0
	s_branch .LBB0_58
.LBB0_57:                               ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s20, -1
                                        ; implicit-def: $vgpr15_vgpr16
                                        ; implicit-def: $sgpr26
.LBB0_58:                               ; %Flow360
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s20
	s_cbranch_vccnz .LBB0_60
; %bb.59:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[15:16], v29, s[0:1]
	s_add_i32 s26, s27, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_60:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_cmp_gt_u32 s26, 7
	s_cbranch_scc1 .LBB0_65
; %bb.61:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_cmp_eq_u32 s26, 0
	s_cbranch_scc1 .LBB0_64
; %bb.62:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b64 s[20:21], 0
	s_mov_b64 s[22:23], 0
.LBB0_63:                               ; %.preheader23.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s28, s0, s22
	s_addc_u32 s29, s1, s23
	s_add_u32 s22, s22, 1
	global_load_u8 v7, v29, s[28:29]
	s_addc_u32 s23, s23, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v28, 0xffff, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], s20, v[28:29]
	s_add_u32 s20, s20, 8
	s_addc_u32 s21, s21, 0
	s_cmp_lg_u32 s26, s22
	v_or_b32_e32 v17, v7, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v18, v8, v18
	s_cbranch_scc1 .LBB0_63
.LBB0_64:                               ; %Flow353
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s20, 0
	s_mov_b32 s27, 0
	s_branch .LBB0_66
.LBB0_65:                               ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s20, -1
                                        ; implicit-def: $sgpr27
.LBB0_66:                               ; %Flow355
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s20
	s_cbranch_vccnz .LBB0_68
; %bb.67:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[17:18], v29, s[0:1]
	s_add_i32 s27, s26, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_68:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_cmp_gt_u32 s27, 7
	s_cbranch_scc1 .LBB0_73
; %bb.69:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_cmp_eq_u32 s27, 0
	s_cbranch_scc1 .LBB0_72
; %bb.70:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b64 s[20:21], 0
	s_mov_b64 s[22:23], 0
.LBB0_71:                               ; %.preheader21.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s28, s0, s22
	s_addc_u32 s29, s1, s23
	s_add_u32 s22, s22, 1
	global_load_u8 v7, v29, s[28:29]
	s_addc_u32 s23, s23, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v28, 0xffff, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], s20, v[28:29]
	s_add_u32 s20, s20, 8
	s_addc_u32 s21, s21, 0
	s_cmp_lg_u32 s27, s22
	v_or_b32_e32 v19, v7, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v20, v8, v20
	s_cbranch_scc1 .LBB0_71
.LBB0_72:                               ; %Flow348
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s20, 0
	s_mov_b32 s26, 0
	s_branch .LBB0_74
.LBB0_73:                               ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s20, -1
                                        ; implicit-def: $vgpr19_vgpr20
                                        ; implicit-def: $sgpr26
.LBB0_74:                               ; %Flow350
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s20
	s_cbranch_vccnz .LBB0_76
; %bb.75:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[19:20], v29, s[0:1]
	s_add_i32 s26, s27, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_76:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_cmp_gt_u32 s26, 7
	s_cbranch_scc1 .LBB0_81
; %bb.77:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_cmp_eq_u32 s26, 0
	s_cbranch_scc1 .LBB0_80
; %bb.78:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b64 s[20:21], 0
	s_mov_b64 s[22:23], s[0:1]
.LBB0_79:                               ; %.preheader.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v7, v29, s[22:23]
	s_add_i32 s26, s26, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v28, 0xffff, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], s20, v[28:29]
	s_add_u32 s20, s20, 8
	s_addc_u32 s21, s21, 0
	s_add_u32 s22, s22, 1
	s_addc_u32 s23, s23, 0
	s_cmp_lg_u32 s26, 0
	v_or_b32_e32 v21, v7, v21
	v_or_b32_e32 v22, v8, v22
	s_cbranch_scc1 .LBB0_79
.LBB0_80:                               ; %Flow343
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s20, 0
	s_branch .LBB0_82
.LBB0_81:                               ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s20, -1
.LBB0_82:                               ; %Flow345
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s20
	s_cbranch_vccnz .LBB0_84
; %bb.83:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[21:22], v29, s[0:1]
.LBB0_84:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	v_dual_mov_b32 v28, v27 :: v_dual_mov_b32 v7, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v28
	v_mov_b32_e32 v8, 0
	v_cmp_eq_u32_e64 s0, s0, v28
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_90
; %bb.85:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[25:26], v29, s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[7:8], v29, s[8:9] offset:40
	global_load_b64 v[23:24], v29, s[8:9]
	s_mov_b32 s20, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v8, v8, v26
	v_and_b32_e32 v7, v7, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v8, v8, 24
	v_mul_hi_u32 v31, v7, 24
	v_mul_lo_u32 v7, v7, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v31, v8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v7, vcc_lo, v23, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, v24, v8, vcc_lo
	global_load_b64 v[23:24], v[7:8], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[7:8], v29, v[23:26], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[7:8], v[25:26]
	s_cbranch_execz .LBB0_89
; %bb.86:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s21, 0
.LBB0_87:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[23:24], v29, s[8:9] offset:40
	global_load_b64 v[31:32], v29, s[8:9]
	v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v25, v7
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v23, v23, v25
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[7:8], null, v23, 24, v[31:32]
	v_and_b32_e32 v31, v24, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[23:24], null, v31, 24, v[8:9]
	v_mov_b32_e32 v8, v23
	global_load_b64 v[23:24], v[7:8], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[7:8], v29, v[23:26], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[25:26]
	s_or_b32 s21, vcc_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s21
	s_cbranch_execnz .LBB0_87
; %bb.88:                               ; %Flow338
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
.LBB0_89:                               ; %Flow340
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s20
.LBB0_90:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[31:32], v29, s[8:9] offset:40
	global_load_b128 v[23:26], v29, s[8:9]
	v_readfirstlane_b32 s20, v7
	v_readfirstlane_b32 s21, v8
	s_mov_b32 s28, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s22, v31
	v_readfirstlane_b32 s23, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[22:23], s[20:21], s[22:23]
	s_mul_i32 s1, s23, 24
	s_mul_hi_u32 s26, s22, 24
	s_mul_i32 s27, s22, 24
	s_and_saveexec_b32 s29, s0
	s_cbranch_execz .LBB0_92
; %bb.91:                               ;   in Loop: Header=BB0_29 Depth=1
	v_dual_mov_b32 v7, s28 :: v_dual_mov_b32 v8, v29
	s_add_i32 s28, s26, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v31, vcc_lo, v23, s27
	v_add_co_ci_u32_e32 v32, vcc_lo, s28, v24, vcc_lo
	global_store_b128 v[31:32], v[7:10], off offset:8
.LBB0_92:                               ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s29
	v_cmp_gt_u64_e64 vcc_lo, s[16:17], 56
	v_or_b32_e32 v7, 0, v2
	v_or_b32_e32 v8, v1, v30
	s_lshl_b64 s[22:23], s[22:23], 12
	s_lshl_b32 s28, s18, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s28, s28, 28
	v_dual_cndmask_b32 v2, v7, v2 :: v_dual_cndmask_b32 v1, v8, v1
	v_lshlrev_b64 v[7:8], 6, v[28:29]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v25, vcc_lo, v25, s22
	v_add_co_ci_u32_e32 v26, vcc_lo, s23, v26, vcc_lo
	s_and_b32 s28, s28, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v25, v7
	v_and_or_b32 v1, 0xffffff1f, v1, s28
	v_add_co_ci_u32_e32 v8, vcc_lo, v26, v8, vcc_lo
	s_clause 0x3
	global_store_b128 v[7:8], v[1:4], off
	global_store_b128 v[7:8], v[11:14], off offset:16
	global_store_b128 v[7:8], v[15:18], off offset:32
	global_store_b128 v[7:8], v[19:22], off offset:48
	s_and_saveexec_b32 s22, s0
	s_cbranch_execz .LBB0_100
; %bb.93:                               ;   in Loop: Header=BB0_29 Depth=1
	s_clause 0x1
	global_load_b64 v[15:16], v29, s[8:9] offset:32 glc
	global_load_b64 v[1:2], v29, s[8:9] offset:40
	v_dual_mov_b32 v13, s20 :: v_dual_mov_b32 v14, s21
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s28, v1
	v_readfirstlane_b32 s29, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[28:29], s[28:29], s[20:21]
	s_mul_i32 s23, s29, 24
	s_mul_hi_u32 s29, s28, 24
	s_mul_i32 s28, s28, 24
	s_add_i32 s29, s29, s23
	v_add_co_u32 v11, vcc_lo, v23, s28
	v_add_co_ci_u32_e32 v12, vcc_lo, s29, v24, vcc_lo
	s_mov_b32 s23, exec_lo
	global_store_b64 v[11:12], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v29, v[13:16], s[8:9] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[3:4], v[15:16]
	s_cbranch_execz .LBB0_96
; %bb.94:                               ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s28, 0
.LBB0_95:                               ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v1, s20 :: v_dual_mov_b32 v2, s21
	s_sleep 1
	global_store_b64 v[11:12], v[3:4], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[1:2], v29, v[1:4], s[8:9] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[3:4]
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
	s_or_b32 s28, vcc_lo, s28
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s28
	s_cbranch_execnz .LBB0_95
.LBB0_96:                               ; %Flow336
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s23
	global_load_b64 v[1:2], v29, s[8:9] offset:16
	s_mov_b32 s28, exec_lo
	s_mov_b32 s23, exec_lo
	v_mbcnt_lo_u32_b32 v3, s28, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB0_98
; %bb.97:                               ;   in Loop: Header=BB0_29 Depth=1
	s_bcnt1_i32_b32 s28, s28
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v28, s28
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[1:2], v[28:29], off offset:8
.LBB0_98:                               ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s23
	s_waitcnt vmcnt(0)
	global_load_b64 v[3:4], v[1:2], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
	s_cbranch_vccnz .LBB0_100
; %bb.99:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b32 v28, v[1:2], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s23, v28
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[3:4], v[28:29], off
	s_and_b32 m0, s23, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_100:                              ; %Flow337
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_add_i32 s26, s26, s1
	v_add_co_u32 v1, vcc_lo, v23, s27
	v_add_co_ci_u32_e32 v2, vcc_lo, s26, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
.LBB0_101:                              ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v3, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_103
; %bb.102:                              ;   in Loop: Header=BB0_101 Depth=2
	global_load_b32 v3, v[1:2], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v3, 1, v3
.LBB0_103:                              ;   in Loop: Header=BB0_101 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v3
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_105
; %bb.104:                              ;   in Loop: Header=BB0_101 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_106
.LBB0_105:                              ;   in Loop: Header=BB0_101 Depth=2
	s_mov_b32 s1, -1
.LBB0_106:                              ; %Flow331
                                        ;   in Loop: Header=BB0_101 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_101
; %bb.107:                              ;   in Loop: Header=BB0_29 Depth=1
	global_load_b128 v[1:4], v[7:8], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_111
; %bb.108:                              ;   in Loop: Header=BB0_29 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v29, s[8:9] offset:40
	global_load_b64 v[7:8], v29, s[8:9] offset:24 glc
	global_load_b64 v[13:14], v29, s[8:9]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v15, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v15, s20
	v_add_co_ci_u32_e32 v12, vcc_lo, s21, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	v_dual_cndmask_b32 v12, v12, v16 :: v_dual_cndmask_b32 v11, v11, v15
	v_and_b32_e32 v4, v12, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, v11, v3
	v_mul_hi_u32 v15, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, vcc_lo, v13, v3
	v_mov_b32_e32 v13, v7
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v4, v15, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, v14, v4, vcc_lo
	v_mov_b32_e32 v14, v8
	global_store_b64 v[3:4], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v29, v[11:14], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[13:14], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_111
; %bb.109:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s0, 0
.LBB0_110:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v29, v[11:14], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[13:14]
	v_dual_mov_b32 v14, v8 :: v_dual_mov_b32 v13, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_110
.LBB0_111:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s16, s16, s18
	s_subb_u32 s17, s17, s19
	s_add_u32 s2, s2, s18
	s_addc_u32 s3, s3, s19
	s_cmp_lg_u64 s[16:17], 0
	s_cbranch_scc1 .LBB0_29
; %bb.112:                              ; %Flow376
	s_mov_b32 s0, 0
	s_branch .LBB0_114
.LBB0_113:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr1_vgpr2
.LBB0_114:                              ; %Flow391
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_143
; %bb.115:
	v_mov_b32_e32 v7, v27
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v10, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v7
	v_cmp_eq_u32_e64 s0, s0, v7
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_121
; %bb.116:
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v1, 0
	s_mov_b32 s2, exec_lo
	global_load_b64 v[11:12], v1, s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[2:3], v1, s[8:9] offset:40
	global_load_b64 v[8:9], v1, s[8:9]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, v2, v11
	v_and_b32_e32 v3, v3, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v3, v3, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v8, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v9, v3, vcc_lo
	global_load_b64 v[9:10], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v1, v[9:12], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[9:10], v[11:12]
	s_cbranch_execz .LBB0_120
; %bb.117:                              ; %.preheader3.i.i.i21.preheader
	s_mov_b32 s3, 0
.LBB0_118:                              ; %.preheader3.i.i.i21
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[2:3], v1, s[8:9] offset:40
	global_load_b64 v[13:14], v1, s[8:9]
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v11, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v2, v11
	v_and_b32_e32 v10, v3, v12
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v2, 24, v[13:14]
	v_mov_b32_e32 v2, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, v10, 24, v[2:3]
	v_mov_b32_e32 v9, v3
	global_load_b64 v[9:10], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v1, v[9:12], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[11:12]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_118
; %bb.119:                              ; %Flow388
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_120:                              ; %Flow390
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_121:                              ; %.loopexit4.i.i.i16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v8, 0
	v_readfirstlane_b32 s2, v9
	v_readfirstlane_b32 s3, v10
	s_mov_b32 s20, exec_lo
	s_clause 0x1
	global_load_b64 v[11:12], v8, s[8:9] offset:40
	global_load_b128 v[1:4], v8, s[8:9]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s16, v11
	v_readfirstlane_b32 s17, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[2:3], s[16:17]
	s_mul_i32 s1, s17, 24
	s_mul_hi_u32 s18, s16, 24
	s_mul_i32 s19, s16, 24
	s_and_saveexec_b32 s21, s0
	s_cbranch_execz .LBB0_123
; %bb.122:
	v_dual_mov_b32 v9, s20 :: v_dual_mov_b32 v10, v8
	s_add_i32 s20, s18, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v13, vcc_lo, v1, s19
	v_add_co_ci_u32_e32 v14, vcc_lo, s20, v2, vcc_lo
	v_dual_mov_b32 v11, 2 :: v_dual_mov_b32 v12, 1
	global_store_b128 v[13:14], v[9:12], off offset:8
.LBB0_123:
	s_or_b32 exec_lo, exec_lo, s21
	s_lshl_b64 s[16:17], s[16:17], 12
	v_lshlrev_b64 v[9:10], 6, v[7:8]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v3, s16
	v_add_co_ci_u32_e32 v4, vcc_lo, s17, v4, vcc_lo
	s_mov_b32 s20, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v3, v9
	s_mov_b32 s21, s20
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_or_b32 v5, 0xffffff1f, v5, 32
	v_add_co_ci_u32_e32 v10, vcc_lo, v4, v10, vcc_lo
	v_mov_b32_e32 v7, v8
	v_dual_mov_b32 v11, s20 :: v_dual_mov_b32 v14, s23
	v_dual_mov_b32 v12, s21 :: v_dual_mov_b32 v13, s22
	s_clause 0x3
	global_store_b128 v[9:10], v[5:8], off
	global_store_b128 v[9:10], v[11:14], off offset:16
	global_store_b128 v[9:10], v[11:14], off offset:32
	global_store_b128 v[9:10], v[11:14], off offset:48
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB0_131
; %bb.124:
	v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v12, s2
	v_mov_b32_e32 v13, s3
	s_clause 0x1
	global_load_b64 v[14:15], v11, s[8:9] offset:32 glc
	global_load_b64 v[3:4], v11, s[8:9] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s20, v3
	v_readfirstlane_b32 s21, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[20:21], s[20:21], s[2:3]
	s_mul_i32 s17, s21, 24
	s_mul_hi_u32 s21, s20, 24
	s_mul_i32 s20, s20, 24
	s_add_i32 s21, s21, s17
	v_add_co_u32 v7, vcc_lo, v1, s20
	v_add_co_ci_u32_e32 v8, vcc_lo, s21, v2, vcc_lo
	s_mov_b32 s17, exec_lo
	global_store_b64 v[7:8], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v11, v[12:15], s[8:9] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[5:6], v[14:15]
	s_cbranch_execz .LBB0_127
; %bb.125:                              ; %.preheader1.i.i.i19.preheader
	s_mov_b32 s20, 0
.LBB0_126:                              ; %.preheader1.i.i.i19
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s3
	s_sleep 1
	global_store_b64 v[7:8], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v11, v[3:6], s[8:9] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	s_or_b32 s20, vcc_lo, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s20
	s_cbranch_execnz .LBB0_126
.LBB0_127:                              ; %Flow386
	s_or_b32 exec_lo, exec_lo, s17
	v_mov_b32_e32 v6, 0
	s_mov_b32 s20, exec_lo
	s_mov_b32 s17, exec_lo
	v_mbcnt_lo_u32_b32 v5, s20, 0
	global_load_b64 v[3:4], v6, s[8:9] offset:16
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_129
; %bb.128:
	s_bcnt1_i32_b32 s20, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s20
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[5:6], off offset:8
.LBB0_129:
	s_or_b32 exec_lo, exec_lo, s17
	s_waitcnt vmcnt(0)
	global_load_b64 v[5:6], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
	s_cbranch_vccnz .LBB0_131
; %bb.130:
	global_load_b32 v3, v[3:4], off offset:24
	v_mov_b32_e32 v4, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s17, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[5:6], v[3:4], off
	s_and_b32 m0, s17, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_131:                              ; %Flow387
	s_or_b32 exec_lo, exec_lo, s16
	s_add_i32 s18, s18, s1
	v_add_co_u32 v1, vcc_lo, v1, s19
	v_add_co_ci_u32_e32 v2, vcc_lo, s18, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
.LBB0_132:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v3, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_134
; %bb.133:                              ;   in Loop: Header=BB0_132 Depth=1
	global_load_b32 v3, v[1:2], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v3, 1, v3
.LBB0_134:                              ;   in Loop: Header=BB0_132 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v3
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_136
; %bb.135:                              ;   in Loop: Header=BB0_132 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_137
.LBB0_136:                              ;   in Loop: Header=BB0_132 Depth=1
	s_mov_b32 s1, -1
.LBB0_137:                              ; %Flow381
                                        ;   in Loop: Header=BB0_132 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_132
; %bb.138:
	global_load_b128 v[1:4], v[9:10], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_142
; %bb.139:
	v_mov_b32_e32 v9, 0
	s_clause 0x2
	global_load_b64 v[5:6], v9, s[8:9] offset:40
	global_load_b64 v[10:11], v9, s[8:9] offset:24 glc
	global_load_b64 v[7:8], v9, s[8:9]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v12, vcc_lo, v5, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v12, s2
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
	v_dual_cndmask_b32 v4, v4, v13 :: v_dual_cndmask_b32 v3, v3, v12
	v_and_b32_e32 v6, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v5, v3, v5
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v12, v5, 24
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v6, v12, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v7, v5
	v_mov_b32_e32 v5, v10
	v_add_co_ci_u32_e32 v8, vcc_lo, v8, v6, vcc_lo
	v_mov_b32_e32 v6, v11
	global_store_b64 v[7:8], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v9, v[3:6], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[5:6], v[10:11]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_142
; %bb.140:                              ; %.preheader.i.i.i18.preheader
	s_mov_b32 s0, 0
.LBB0_141:                              ; %.preheader.i.i.i18
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[7:8], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v9, v[3:6], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[5:6]
	v_dual_mov_b32 v5, v10 :: v_dual_mov_b32 v6, v11
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_141
.LBB0_142:                              ; %__ockl_hostcall_preview.exit.i
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_143:                              ; %__ockl_printf_append_string_n.exit
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v3, v27
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v10, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v3
	v_cmp_eq_u32_e64 s0, s0, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_149
; %bb.144:
	v_mov_b32_e32 v4, 0
	s_mov_b32 s2, exec_lo
	global_load_b64 v[7:8], v4, s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[8:9] offset:40
	global_load_b64 v[9:10], v4, s[8:9]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v7
	v_and_b32_e32 v6, v6, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v5, 24
	v_mul_lo_u32 v6, v6, 24
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v11, v6
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v9, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, v10, v6, vcc_lo
	global_load_b64 v[5:6], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v4, v[5:8], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[9:10], v[7:8]
	s_cbranch_execz .LBB0_148
; %bb.145:                              ; %.preheader3.i.i.i28.preheader
	s_mov_b32 s3, 0
.LBB0_146:                              ; %.preheader3.i.i.i28
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[8:9] offset:40
	global_load_b64 v[11:12], v4, s[8:9]
	v_dual_mov_b32 v7, v9 :: v_dual_mov_b32 v8, v10
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v5, v5, v7
	v_and_b32_e32 v6, v6, v8
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v5, 24, v[11:12]
	v_mov_b32_e32 v5, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, v6, 24, v[5:6]
	global_load_b64 v[5:6], v[9:10], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v4, v[5:8], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[7:8]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_146
; %bb.147:                              ; %Flow324
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_148:                              ; %Flow326
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_149:                              ; %.loopexit4.i.i.i22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v4, 0
	v_readfirstlane_b32 s2, v9
	v_readfirstlane_b32 s3, v10
	s_mov_b32 s20, exec_lo
	s_clause 0x1
	global_load_b64 v[11:12], v4, s[8:9] offset:40
	global_load_b128 v[5:8], v4, s[8:9]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s16, v11
	v_readfirstlane_b32 s17, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[2:3], s[16:17]
	s_mul_i32 s1, s17, 24
	s_mul_hi_u32 s18, s16, 24
	s_mul_i32 s19, s16, 24
	s_and_saveexec_b32 s21, s0
	s_cbranch_execz .LBB0_151
; %bb.150:
	v_dual_mov_b32 v9, s20 :: v_dual_mov_b32 v10, v4
	s_add_i32 s20, s18, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v13, vcc_lo, v5, s19
	v_add_co_ci_u32_e32 v14, vcc_lo, s20, v6, vcc_lo
	v_dual_mov_b32 v11, 2 :: v_dual_mov_b32 v12, 1
	global_store_b128 v[13:14], v[9:12], off offset:8
.LBB0_151:
	s_or_b32 exec_lo, exec_lo, s21
	s_lshl_b64 s[16:17], s[16:17], 12
	v_lshlrev_b64 v[9:10], 6, v[3:4]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v7, vcc_lo, v7, s16
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v8, vcc_lo
	s_mov_b32 s20, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v7, v9
	s_mov_b32 s21, s20
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_b32_e32 v3, 0x3ff, v0
	v_and_or_b32 v1, 0xffffff1f, v1, 32
	v_add_co_ci_u32_e32 v12, vcc_lo, v8, v10, vcc_lo
	v_dual_mov_b32 v7, s20 :: v_dual_mov_b32 v10, s23
	v_dual_mov_b32 v8, s21 :: v_dual_mov_b32 v9, s22
	s_clause 0x3
	global_store_b128 v[11:12], v[1:4], off
	global_store_b128 v[11:12], v[7:10], off offset:16
	global_store_b128 v[11:12], v[7:10], off offset:32
	global_store_b128 v[11:12], v[7:10], off offset:48
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB0_159
; %bb.152:
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v13, s2
	v_mov_b32_e32 v14, s3
	s_clause 0x1
	global_load_b64 v[15:16], v4, s[8:9] offset:32 glc
	global_load_b64 v[1:2], v4, s[8:9] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s20, v1
	v_readfirstlane_b32 s21, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[20:21], s[20:21], s[2:3]
	s_mul_i32 s17, s21, 24
	s_mul_hi_u32 s21, s20, 24
	s_mul_i32 s20, s20, 24
	s_add_i32 s21, s21, s17
	v_add_co_u32 v1, vcc_lo, v5, s20
	v_add_co_ci_u32_e32 v2, vcc_lo, s21, v6, vcc_lo
	s_mov_b32 s17, exec_lo
	global_store_b64 v[1:2], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v4, v[13:16], s[8:9] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[9:10], v[15:16]
	s_cbranch_execz .LBB0_155
; %bb.153:                              ; %.preheader1.i.i.i26.preheader
	s_mov_b32 s20, 0
.LBB0_154:                              ; %.preheader1.i.i.i26
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v7, s2 :: v_dual_mov_b32 v8, s3
	s_sleep 1
	global_store_b64 v[1:2], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v4, v[7:10], s[8:9] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	s_or_b32 s20, vcc_lo, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s20
	s_cbranch_execnz .LBB0_154
.LBB0_155:                              ; %Flow322
	s_or_b32 exec_lo, exec_lo, s17
	v_mov_b32_e32 v8, 0
	s_mov_b32 s20, exec_lo
	s_mov_b32 s17, exec_lo
	v_mbcnt_lo_u32_b32 v4, s20, 0
	global_load_b64 v[1:2], v8, s[8:9] offset:16
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB0_157
; %bb.156:
	s_bcnt1_i32_b32 s20, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v7, s20
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[1:2], v[7:8], off offset:8
.LBB0_157:
	s_or_b32 exec_lo, exec_lo, s17
	s_waitcnt vmcnt(0)
	global_load_b64 v[7:8], v[1:2], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	s_cbranch_vccnz .LBB0_159
; %bb.158:
	global_load_b32 v1, v[1:2], off offset:24
	v_mov_b32_e32 v2, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s17, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[7:8], v[1:2], off
	s_and_b32 m0, s17, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_159:                              ; %Flow323
	s_or_b32 exec_lo, exec_lo, s16
	s_add_i32 s18, s18, s1
	v_add_co_u32 v1, vcc_lo, v5, s19
	v_add_co_ci_u32_e32 v2, vcc_lo, s18, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
.LBB0_160:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v4, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_162
; %bb.161:                              ;   in Loop: Header=BB0_160 Depth=1
	global_load_b32 v4, v[1:2], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v4, 1, v4
.LBB0_162:                              ;   in Loop: Header=BB0_160 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v4
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_164
; %bb.163:                              ;   in Loop: Header=BB0_160 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_165
.LBB0_164:                              ;   in Loop: Header=BB0_160 Depth=1
	s_mov_b32 s1, -1
.LBB0_165:                              ; %Flow317
                                        ;   in Loop: Header=BB0_160 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_160
; %bb.166:
	global_load_b64 v[4:5], v[11:12], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_170
; %bb.167:
	v_mov_b32_e32 v10, 0
	s_clause 0x2
	global_load_b64 v[1:2], v10, s[8:9] offset:40
	global_load_b64 v[11:12], v10, s[8:9] offset:24 glc
	global_load_b64 v[8:9], v10, s[8:9]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v13, vcc_lo, v1, 1
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v13, s2
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	v_dual_cndmask_b32 v7, v7, v14 :: v_dual_cndmask_b32 v6, v6, v13
	v_and_b32_e32 v2, v7, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v6, v1
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v13, v1, 24
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v2, v13, v2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, v8, v1
	v_mov_b32_e32 v8, v11
	v_add_co_ci_u32_e32 v2, vcc_lo, v9, v2, vcc_lo
	v_mov_b32_e32 v9, v12
	global_store_b64 v[1:2], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v10, v[6:9], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[8:9], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_170
; %bb.168:                              ; %.preheader.i.i.i25.preheader
	s_mov_b32 s0, 0
.LBB0_169:                              ; %.preheader.i.i.i25
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[1:2], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v10, v[6:9], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[8:9]
	v_dual_mov_b32 v8, v11 :: v_dual_mov_b32 v9, v12
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_169
.LBB0_170:                              ; %__ockl_printf_append_args.exit
	s_or_b32 exec_lo, exec_lo, s1
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v27
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v27
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_176
; %bb.171:
	v_mov_b32_e32 v6, 0
	s_mov_b32 s2, exec_lo
	global_load_b64 v[9:10], v6, s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v6, s[8:9] offset:40
	global_load_b64 v[7:8], v6, s[8:9]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v9
	v_and_b32_e32 v2, v2, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v1, 24
	v_mul_lo_u32 v2, v2, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v11, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v7, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v8, v2, vcc_lo
	global_load_b64 v[7:8], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v6, v[7:10], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[1:2], v[9:10]
	s_cbranch_execz .LBB0_175
; %bb.172:                              ; %.preheader3.i.i.i35.preheader
	s_mov_b32 s3, 0
.LBB0_173:                              ; %.preheader3.i.i.i35
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[8:9] offset:40
	global_load_b64 v[11:12], v6, s[8:9]
	v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v9, v1
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v9
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[1:2], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[2:3]
	v_mov_b32_e32 v2, v7
	global_load_b64 v[7:8], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v6, v[7:10], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[9:10]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_173
; %bb.174:                              ; %Flow310
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_175:                              ; %Flow312
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_176:                              ; %.loopexit4.i.i.i29
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v28, 0
	v_readfirstlane_b32 s2, v1
	v_readfirstlane_b32 s3, v2
	s_mov_b32 s20, exec_lo
	s_clause 0x1
	global_load_b64 v[6:7], v28, s[8:9] offset:40
	global_load_b128 v[8:11], v28, s[8:9]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s16, v6
	v_readfirstlane_b32 s17, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[2:3], s[16:17]
	s_mul_i32 s1, s17, 24
	s_mul_hi_u32 s18, s16, 24
	s_mul_i32 s19, s16, 24
	s_and_saveexec_b32 s21, s0
	s_cbranch_execz .LBB0_178
; %bb.177:
	v_dual_mov_b32 v12, s20 :: v_dual_mov_b32 v13, v28
	s_add_i32 s20, s18, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v8, s19
	v_add_co_ci_u32_e32 v2, vcc_lo, s20, v9, vcc_lo
	v_dual_mov_b32 v14, 2 :: v_dual_mov_b32 v15, 1
	global_store_b128 v[1:2], v[12:15], off offset:8
.LBB0_178:
	s_or_b32 exec_lo, exec_lo, s21
	s_lshl_b64 s[16:17], s[16:17], 12
	v_lshlrev_b64 v[1:2], 6, v[27:28]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v7, vcc_lo, v10, s16
	v_add_co_ci_u32_e32 v10, vcc_lo, s17, v11, vcc_lo
	s_mov_b32 s20, 0
	v_bfe_u32 v6, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v7, v1
	s_mov_b32 s21, s20
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_or_b32 v4, 0xffffff1d, v4, 34
	v_add_co_ci_u32_e32 v1, vcc_lo, v10, v2, vcc_lo
	v_dual_mov_b32 v7, v28 :: v_dual_mov_b32 v10, s20
	v_dual_mov_b32 v11, s21 :: v_dual_mov_b32 v12, s22
	v_mov_b32_e32 v13, s23
	s_clause 0x3
	global_store_b128 v[0:1], v[4:7], off
	global_store_b128 v[0:1], v[10:13], off offset:16
	global_store_b128 v[0:1], v[10:13], off offset:32
	global_store_b128 v[0:1], v[10:13], off offset:48
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB0_186
; %bb.179:
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v13, s3
	v_mov_b32_e32 v12, s2
	s_clause 0x1
	global_load_b64 v[14:15], v2, s[8:9] offset:32 glc
	global_load_b64 v[0:1], v2, s[8:9] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s20, v0
	v_readfirstlane_b32 s21, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[20:21], s[20:21], s[2:3]
	s_mul_i32 s17, s21, 24
	s_mul_hi_u32 s21, s20, 24
	s_mul_i32 s20, s20, 24
	s_add_i32 s21, s21, s17
	v_add_co_u32 v0, vcc_lo, v8, s20
	v_add_co_ci_u32_e32 v1, vcc_lo, s21, v9, vcc_lo
	s_mov_b32 s17, exec_lo
	global_store_b64 v[0:1], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v2, v[12:15], s[8:9] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[12:13], v[14:15]
	s_cbranch_execz .LBB0_182
; %bb.180:                              ; %.preheader1.i.i.i33.preheader
	s_mov_b32 s20, 0
.LBB0_181:                              ; %.preheader1.i.i.i33
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, s3
	s_sleep 1
	global_store_b64 v[0:1], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v2, v[10:13], s[8:9] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[12:13]
	v_dual_mov_b32 v13, v5 :: v_dual_mov_b32 v12, v4
	s_or_b32 s20, vcc_lo, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s20
	s_cbranch_execnz .LBB0_181
.LBB0_182:                              ; %Flow308
	s_or_b32 exec_lo, exec_lo, s17
	v_mov_b32_e32 v5, 0
	s_mov_b32 s20, exec_lo
	s_mov_b32 s17, exec_lo
	v_mbcnt_lo_u32_b32 v2, s20, 0
	global_load_b64 v[0:1], v5, s[8:9] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_184
; %bb.183:
	s_bcnt1_i32_b32 s20, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s20
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[4:5], off offset:8
.LBB0_184:
	s_or_b32 exec_lo, exec_lo, s17
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB0_186
; %bb.185:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s17, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[0:1], off
	s_and_b32 m0, s17, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_186:                              ; %Flow309
	s_or_b32 exec_lo, exec_lo, s16
	s_add_i32 s18, s18, s1
	v_add_co_u32 v0, vcc_lo, v8, s19
	v_add_co_ci_u32_e32 v1, vcc_lo, s18, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_187:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_189
; %bb.188:                              ;   in Loop: Header=BB0_187 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_189:                              ;   in Loop: Header=BB0_187 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_191
; %bb.190:                              ;   in Loop: Header=BB0_187 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_192
.LBB0_191:                              ;   in Loop: Header=BB0_187 Depth=1
	s_mov_b32 s1, -1
.LBB0_192:                              ; %Flow303
                                        ;   in Loop: Header=BB0_187 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_187
; %bb.193:
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_197
; %bb.194:
	v_mov_b32_e32 v2, 0
	s_clause 0x2
	global_load_b64 v[0:1], v2, s[8:9] offset:40
	global_load_b64 v[4:5], v2, s[8:9] offset:24 glc
	global_load_b64 v[9:10], v2, s[8:9]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v11, s2
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	v_cndmask_b32_e32 v7, v7, v11, vcc_lo
	v_and_b32_e32 v0, v7, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v0, 24
	v_cndmask_b32_e32 v8, v8, v12, vcc_lo
	v_mul_lo_u32 v0, v0, 24
	v_and_b32_e32 v1, v8, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v9, v0
	v_mul_lo_u32 v1, v1, 24
	v_mov_b32_e32 v9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, v11, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, v10, v1, vcc_lo
	v_mov_b32_e32 v10, v5
	global_store_b64 v[0:1], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[7:10], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[9:10], v[4:5]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_197
; %bb.195:                              ; %.preheader.i.i.i32.preheader
	s_mov_b32 s0, 0
.LBB0_196:                              ; %.preheader.i.i.i32
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v2, v[7:10], s[8:9] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[9:10]
	v_dual_mov_b32 v10, v5 :: v_dual_mov_b32 v9, v4
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_196
.LBB0_197:                              ; %__ockl_printf_append_args.exit36
	s_or_b32 exec_lo, exec_lo, s1
	s_lshr_b32 s0, s24, 16
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s15, s0, v[6:7]
	s_and_b32 s0, s24, 0xffff
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s4, 0
	v_mad_u64_u32 v[1:2], null, s14, s0, v[3:4]
	s_cbranch_scc1 .LBB0_200
; %bb.198:                              ; %.lr.ph
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v2, v0, s5
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v4, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
.LBB0_199:                              ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s4, s4, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s4, 0
	v_lshlrev_b64 v[7:8], 2, v[4:5]
	v_add_nc_u32_e32 v4, s25, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s12, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s13, v8, vcc_lo
	global_load_b32 v5, v[2:3], off
	global_load_b32 v7, v[7:8], off
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v6, v5, v7
	s_cbranch_scc0 .LBB0_199
	s_branch .LBB0_201
.LBB0_200:
	v_mov_b32_e32 v6, 0
.LBB0_201:                              ; %Flow299
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v0, s25, v[1:2]
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_add_co_u32 v0, vcc_lo, s10, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	global_store_b32 v[0:1], v6, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10matrixMult6MatrixS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 33
		.amdhsa_next_free_sgpr 30
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10matrixMult6MatrixS_S_, .Lfunc_end0-_Z10matrixMult6MatrixS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 8332
; NumSgprs: 32
; NumVgprs: 33
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 32
; NumVGPRsForWavesPerEU: 33
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"\nthreadIdx(%d) threadIdy(%d)\n"
	.size	.str, 30

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           16
        .value_kind:     by_value
      - .offset:         16
        .size:           16
        .value_kind:     by_value
      - .offset:         32
        .size:           16
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         128
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10matrixMult6MatrixS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     32
    .sgpr_spill_count: 0
    .symbol:         _Z10matrixMult6MatrixS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     33
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
