#include <cuda_runtime_api.h>
#include <cassert>
#include <cstdio>
#include <cstdlib>
#include <cmath>
#include <random>
#include <cooperative_groups.h>
/*

WRITE CUDA KERNEL FOR COUNT HERE

*/
__device__
int log_2(float x){
	int count = 0;
	while(x>1){
		x/=2;
		count++;

	}
	return count;
}

__global__
void parallel_implementation(int * data, int vals,int * tmp_data, int * output_data){
    int blocks = gridDim.x;
    int start_index = threadIdx.x + (vals*blockIdx.x)/blocks;
    int end_index = (vals*(blockIdx.x+1))/blocks;
    int layers = log_2(vals);
    //printf("Layers = %d",layers);
    //sync stuff
    //grid_group g = this_grid();

    //data works as previous layer holder
    //output_data works as current layer holder

    //Hillis-Steele Algorithm
    for(int layer = 0; layer < layers; layer++){
	//for each layer
	//if(blockIdx.x==0 && threadIdx.x==vals) printf("layer %d",layer);
	for(int i = start_index;i<end_index;i+=blockDim.x){//move in strides the size of the block
	    //for each element in the array
	    int neighbor_i = i-pow(2,layer); 
	    if(neighbor_i>=0){
		output_data[i]+=data[neighbor_i];//update output
		//tmp_data[i]+=data[i-pow(2,layer)];//update holder container
		//test removal tmp_data[i]=output_data[i];
	    }
	}
	__syncthreads();/*
	if(blockIdx.x==0 && threadIdx.x==0){//copy new array over to data
	    //swap new layers data int "data" for next round
	    //int * tmp = data;
	    //data = tmp_data;
	    //tmp_data = tmp;
	    for i 	
	}*/
	//if(blockIdx.x==0 && threadIdx.x==0) for (int i = 0; i<vals;i++) printf("%d\n",output_data[i]);	
	//prep for next layer
	for(int i = start_index;i<end_index;i+=blockDim.x){
	    data[i] = output_data[i];
	}
	__syncthreads();//sync threads across all blocks before next layer
    }
    //bug removal fix later
    __syncthreads();
    if(blockIdx.x==0 && threadIdx.x==0)for(int i = 2047; i<vals;i+=4096) output_data[i]-=data[0];

}
int * serial_implementation(int * data, int vals) {
    int * output = (int *)malloc(sizeof(int) * vals);
    
    output[0] = 0;
    for (int i = 1; i < vals; i++) {
        output[i] = output[i-1] + data[i-1];
    }
    
    return output;
}

int main(int argc, char ** argv) {
    
    assert(argc == 2);
    int values = atoi(argv[1]); // Values is guaranteed to be no more than 10000000
    int * data = (int *)malloc(sizeof(int) * values);

    // Generate "random" vector
    std::mt19937 gen(13); // Keep constant to maintain determinism between runs
    std::uniform_int_distribution<> dist(0, 50);
    for (int i = 0; i < values; i++) {
        data[i] = dist(gen);
    }

    cudaStream_t stream;
    cudaEvent_t begin, end;
    cudaStreamCreate(&stream);
    cudaEventCreate(&begin);
    cudaEventCreate(&end);

    int * h_output = (int *)malloc(sizeof(int) * (1+values)); // THIS VARIABLE SHOULD HOLD THE TOTAL COUNT BY THE END

    /*

    PERFORM NECESSARY VARIABLE DECLARATIONS HERE

    PERFORM NECESSARY DATA TRANSFER HERE

    */
	int * gpu_data;
	int * gpu_output_data;
	int * gpu_tmp_data;

	//Determine allocation size
	int array_size = sizeof(int)*values;

	//Allocate memory on GPU
	cudaMalloc(&gpu_data, array_size);
	cudaMalloc(&gpu_output_data, array_size);
	cudaMalloc(&gpu_tmp_data, array_size);
	
	//cudaMalloc(&gpu_data, array_size+sizeof(int));
        //cudaMalloc(&gpu_output_data, array_size+sizeof(int));
        //cudaMalloc(&gpu_tmp_data, array_size+sizeof(int));


	//Copy data to GPU
	cudaMemcpy(gpu_data,data,array_size,cudaMemcpyHostToDevice);
	cudaMemcpy(gpu_output_data,data,array_size,cudaMemcpyHostToDevice);
	cudaMemcpy(gpu_tmp_data,data,array_size,cudaMemcpyHostToDevice);

	//cudaMemcpy(gpu_data+sizeof(int),data,array_size,cudaMemcpyHostToDevice);
        //cudaMemcpy(gpu_output_data+sizeof(int),data,array_size,cudaMemcpyHostToDevice);
        //cudaMemcpy(gpu_tmp_data+sizeof(int),data,array_size,cudaMemcpyHostToDevice);


    cudaEventRecord(begin, stream);

    /*

    LAUNCH KERNEL HERE

    */
    int THREADS_PER_BLOCK = 1024;//128 ideal
    int BLOCKS = 1;//16 ideal
    dim3 block(THREADS_PER_BLOCK);
    dim3 grid(BLOCKS);
    parallel_implementation<<<grid,block,0,stream>>>(gpu_data,values,gpu_tmp_data,gpu_output_data);



    cudaEventRecord(end, stream);

    /* 

    PERFORM NECESSARY DATA TRANSFER HERE

    */
    cudaMemcpy(h_output+1, gpu_output_data, array_size, cudaMemcpyDeviceToHost);
    h_output[0] = 0;


    cudaStreamSynchronize(stream);

    float ms;
    cudaEventElapsedTime(&ms, begin, end);
    printf("Elapsed time: %f ms\n", ms);

    /* 

    DEALLOCATE RESOURCES HERE

    */
	cudaFree(gpu_data);
	cudaFree(gpu_output_data);
	cudaFree(gpu_tmp_data);



    int * reference_output = serial_implementation(data, values);
    for (int i = 0; i < values; i++) {
        if (reference_output[i] != h_output[i]) {
            printf("ERROR: %d != %d at index %d. Off by %d\n", reference_output[i], h_output[i], i,reference_output[i]- h_output[i]);
            
	   /* printf("V | C | GPU\n");
	    for(int j = 0; j< values;j++){
		printf("%d | %d | %d\n",data[j],reference_output[j],h_output[j]);
	    }*/
	    //abort();
        }
    }

    cudaEventDestroy(begin);
    cudaEventDestroy(end);
    cudaStreamDestroy(stream);

    free(data);
    free(reference_output);
    free(h_output);

    return 0;
}

	.file	"tmpxft_0037fbae_00000000-6_scan.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB7648:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE7648:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z5log_2f
	.type	_Z5log_2f, @function
_Z5log_2f:
.LFB7643:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE7643:
	.size	_Z5log_2f, .-_Z5log_2f
	.globl	_Z21serial_implementationPii
	.type	_Z21serial_implementationPii, @function
_Z21serial_implementationPii:
.LFB7644:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rdi, %rbp
	movslq	%esi, %rdi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movq	%rdi, %rbx
	salq	$2, %rdi
	pushq	%rcx
	.cfi_def_cfa_offset 32
	call	malloc@PLT
	xorl	%esi, %esi
	xorl	%edx, %edx
	movl	%esi, (%rax)
.L5:
	incq	%rdx
	cmpl	%edx, %ebx
	jle	.L9
	movl	-4(%rbp,%rdx,4), %ecx
	addl	-4(%rax,%rdx,4), %ecx
	movl	%ecx, (%rax,%rdx,4)
	jmp	.L5
.L9:
	popq	%rdx
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7644:
	.size	_Z21serial_implementationPii, .-_Z21serial_implementationPii
	.globl	_Z48__device_stub__Z23parallel_implementationPiiS_S_PiiS_S_
	.type	_Z48__device_stub__Z23parallel_implementationPiiS_S_PiiS_S_, @function
_Z48__device_stub__Z23parallel_implementationPiiS_S_PiiS_S_:
.LFB7670:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z23parallel_implementationPiiS_S_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L10:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7670:
	.size	_Z48__device_stub__Z23parallel_implementationPiiS_S_PiiS_S_, .-_Z48__device_stub__Z23parallel_implementationPiiS_S_PiiS_S_
	.globl	_Z23parallel_implementationPiiS_S_
	.type	_Z23parallel_implementationPiiS_S_, @function
_Z23parallel_implementationPiiS_S_:
.LFB7671:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z23parallel_implementationPiiS_S_PiiS_S_
	.cfi_endproc
.LFE7671:
	.size	_Z23parallel_implementationPiiS_S_, .-_Z23parallel_implementationPiiS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z23parallel_implementationPiiS_S_"
.LC1:
	.string	"_ZN37_INTERNAL_feca0e03_7_scan_cu_99bbe6644cuda3std3__419piecewise_constructE"
.LC2:
	.string	"_ZN37_INTERNAL_feca0e03_7_scan_cu_99bbe6644cuda3std6ranges3__45__cpo4swapE"
.LC3:
	.string	"_ZN37_INTERNAL_feca0e03_7_scan_cu_99bbe6644cuda3std6ranges3__45__cpo9iter_moveE"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB7673:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z23parallel_implementationPiiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$1, %r9d
	movq	%rdx, %rcx
	leaq	_ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r8
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE7673:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,comdat
	.align 2
	.weak	_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
	.type	_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv, @function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv:
.LFB8531:
	.cfi_startproc
	endbr64
	movq	%rdi, %rax
	xorl	%edx, %edx
	movl	$2567483615, %edi
.L19:
	movq	(%rax,%rdx,8), %rsi
	incq	%rdx
	movq	(%rax,%rdx,8), %rcx
	andq	$-2147483648, %rsi
	andl	$2147483647, %ecx
	orq	%rsi, %rcx
	movq	%rcx, %rsi
	shrq	%rsi
	xorq	3168(%rax,%rdx,8), %rsi
	andl	$1, %ecx
	je	.L18
	movq	%rdi, %rcx
.L18:
	xorq	%rsi, %rcx
	movq	%rcx, -8(%rax,%rdx,8)
	cmpq	$227, %rdx
	jne	.L19
	movl	$2567483615, %edi
.L21:
	movq	(%rax,%rdx,8), %rsi
	incq	%rdx
	movq	(%rax,%rdx,8), %rcx
	andq	$-2147483648, %rsi
	andl	$2147483647, %ecx
	orq	%rsi, %rcx
	movq	%rcx, %rsi
	shrq	%rsi
	xorq	-1824(%rax,%rdx,8), %rsi
	andl	$1, %ecx
	je	.L20
	movq	%rdi, %rcx
.L20:
	xorq	%rsi, %rcx
	movq	%rcx, -8(%rax,%rdx,8)
	cmpq	$623, %rdx
	jne	.L21
	movq	4984(%rax), %rdx
	movq	(%rax), %rcx
	andq	$-2147483648, %rdx
	andl	$2147483647, %ecx
	orq	%rcx, %rdx
	movq	%rdx, %rcx
	shrq	%rcx
	xorq	3168(%rax), %rcx
	andl	$1, %edx
	je	.L22
	movl	$2567483615, %edx
.L22:
	xorq	%rcx, %rdx
	movq	%rdx, 4984(%rax)
	xorl	%edx, %edx
	movq	%rdx, 4992(%rax)
	ret
	.cfi_endproc
.LFE8531:
	.size	_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv, .-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
	.section	.text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,comdat
	.align 2
	.weak	_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
	.type	_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, @function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv:
.LFB8442:
	.cfi_startproc
	endbr64
	cmpq	$623, 4992(%rdi)
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	%rdi, %rbx
	jbe	.L35
	call	_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
.L35:
	movq	4992(%rbx), %rax
	leaq	1(%rax), %rdx
	movq	(%rbx,%rax,8), %rax
	movq	%rdx, 4992(%rbx)
	popq	%rbx
	.cfi_def_cfa_offset 8
	movq	%rax, %rdx
	shrq	$11, %rdx
	movl	%edx, %edx
	xorq	%rax, %rdx
	movq	%rdx, %rax
	salq	$7, %rax
	andl	$2636928640, %eax
	xorq	%rdx, %rax
	movq	%rax, %rdx
	salq	$15, %rdx
	andl	$4022730752, %edx
	xorq	%rax, %rdx
	movq	%rdx, %rax
	shrq	$18, %rax
	xorq	%rdx, %rax
	ret
	.cfi_endproc
.LFE8442:
	.size	_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, .-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
	.text
	.align 2
	.type	_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE.isra.0, @function
_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE.isra.0:
.LFB8582:
	.cfi_startproc
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movslq	%esi, %rax
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rax, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movslq	%edx, %rbx
	subq	%rax, %rbx
	movl	$4294967294, %eax
	movq	%rbx, %r13
	cmpq	%rbx, %rax
	jb	.L38
	call	_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
	leaq	1(%rbx), %rbx
	imulq	%rbx, %rax
	movq	%rax, %rcx
	movl	%eax, %esi
	cmpl	%ebx, %eax
	jnb	.L39
	movl	%ebx, %eax
	xorl	%edx, %edx
	negl	%eax
	divl	%ebx
	movl	%edx, %r14d
.L40:
	cmpl	%r14d, %esi
	jnb	.L39
	movq	%rbp, %rdi
	call	_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
	imulq	%rbx, %rax
	movq	%rax, %rcx
	movl	%eax, %esi
	jmp	.L40
.L39:
	shrq	$32, %rcx
	jmp	.L42
.L38:
	movl	$4294967295, %eax
	cmpq	%rax, %rbx
	je	.L43
.L47:
	orl	$-1, %edx
	xorl	%esi, %esi
	movq	%rbp, %rdi
	call	_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE.isra.0
	movq	%rbp, %rdi
	movl	%eax, %ebx
	call	_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
	movq	%rbx, %rcx
	salq	$32, %rcx
	addq	%rax, %rcx
	setc	%al
	movzbl	%al, %eax
	cmpq	%rcx, %r13
	jb	.L47
	testq	%rax, %rax
	jne	.L47
	jmp	.L42
.L43:
	call	_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
	movq	%rax, %rcx
.L42:
	popq	%rbx
	.cfi_def_cfa_offset 40
	leal	(%r12,%rcx), %eax
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE8582:
	.size	_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE.isra.0, .-_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE.isra.0
	.section	.rodata.str1.1
.LC4:
	.string	"Elapsed time: %f ms\n"
.LC5:
	.string	"ERROR: %d != %d at index %d. Off by %d\n"
	.section	.text.startup
	.globl	main
	.type	main, @function
main:
.LFB7645:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$4096, %rsp
	.cfi_def_cfa_offset 4152
	orq	$0, (%rsp)
	subq	$1000, %rsp
	.cfi_def_cfa_offset 5152
	movq	8(%rsi), %rdi
	movq	%fs:40, %rax
	movq	%rax, 5080(%rsp)
	xorl	%eax, %eax
	leaq	80(%rsp), %r14
	call	atoi@PLT
	movslq	%eax, %rbx
	movq	%rbx, %r12
	salq	$2, %rbx
	movq	%rbx, %rdi
	call	malloc@PLT
	movl	$1, %edx
	movq	$13, 80(%rsp)
	movq	%rax, %rbp
.L50:
	movq	-8(%r14,%rdx,8), %rax
	movq	%rax, %rcx
	shrq	$30, %rcx
	xorq	%rcx, %rax
	imulq	$1812433253, %rax, %rax
	addl	%edx, %eax
	movq	%rax, (%r14,%rdx,8)
	incq	%rdx
	cmpq	$624, %rdx
	jne	.L50
	movq	$624, 5072(%rsp)
	xorl	%r13d, %r13d
.L51:
	cmpl	%r13d, %r12d
	jle	.L60
	movl	$50, %edx
	xorl	%esi, %esi
	movq	%r14, %rdi
	call	_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE.isra.0
	movl	%eax, 0(%rbp,%r13,4)
	incq	%r13
	jmp	.L51
.L60:
	leaq	8(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	16(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	24(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	4(%rbx), %rdi
	leal	0(,%r12,4), %ebx
	call	malloc@PLT
	movslq	%ebx, %rbx
	leaq	32(%rsp), %rdi
	movq	%rbx, %rsi
	movq	%rax, %r13
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	48(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	32(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%rbp, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%rbp, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	48(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%rbp, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rsi
	movq	16(%rsp), %rdi
	call	cudaEventRecord@PLT
	movl	$4194305, %edx
	movq	8(%rsp), %r9
	movabsq	$4294967297, %rdi
	salq	$10, %rdx
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rdi, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L53
	movq	40(%rsp), %rcx
	movq	48(%rsp), %rdx
	movl	%r12d, %esi
	movq	32(%rsp), %rdi
	call	_Z48__device_stub__Z23parallel_implementationPiiS_S_PiiS_S_
.L53:
	movq	8(%rsp), %rsi
	movq	24(%rsp), %rdi
	leaq	.LC5(%rip), %r15
	call	cudaEventRecord@PLT
	movq	40(%rsp), %rsi
	movq	%rbx, %rdx
	leaq	4(%r13), %rdi
	movl	$2, %ecx
	xorl	%ebx, %ebx
	call	cudaMemcpy@PLT
	xorl	%eax, %eax
	movq	8(%rsp), %rdi
	movl	%eax, 0(%r13)
	call	cudaStreamSynchronize@PLT
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	leaq	4(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	4(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movl	%r12d, %esi
	movq	%rbp, %rdi
	call	_Z21serial_implementationPii
	movq	%rax, %r14
.L54:
	cmpl	%ebx, %r12d
	jle	.L61
	movl	(%r14,%rbx,4), %edx
	movl	0(%r13,%rbx,4), %ecx
	cmpl	%ecx, %edx
	je	.L55
	movl	%edx, %r9d
	movl	%ebx, %r8d
	movq	%r15, %rsi
	movl	$2, %edi
	subl	%ecx, %r9d
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L55:
	incq	%rbx
	jmp	.L54
.L61:
	movq	16(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	24(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	8(%rsp), %rdi
	call	cudaStreamDestroy@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%r14, %rdi
	call	free@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	5080(%rsp), %rax
	subq	%fs:40, %rax
	je	.L57
	call	__stack_chk_fail@PLT
.L57:
	addq	$5096, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7645:
	.size	main, .-main
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.weak	_ZN4cuda3std3__419piecewise_constructE
	.section	.rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
	.type	_ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
	.size	_ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo9iter_moveE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo4swapE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
	.zero	1
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <cassert>
#include <cstdio>
#include <cstdlib>
#include <cmath>
#include <random>
#include <hip/hip_cooperative_groups.h>
/*

WRITE CUDA KERNEL FOR COUNT HERE

*/
__device__
int log_2(float x){
	int count = 0;
	while(x>1){
		x/=2;
		count++;

	}
	return count;
}

__global__
void parallel_implementation(int * data, int vals,int * tmp_data, int * output_data){
    int blocks = gridDim.x;
    int start_index = threadIdx.x + (vals*blockIdx.x)/blocks;
    int end_index = (vals*(blockIdx.x+1))/blocks;
    int layers = log_2(vals);
    //printf("Layers = %d",layers);
    //sync stuff
    //grid_group g = this_grid();

    //data works as previous layer holder
    //output_data works as current layer holder

    //Hillis-Steele Algorithm
    for(int layer = 0; layer < layers; layer++){
	//for each layer
	//if(blockIdx.x==0 && threadIdx.x==vals) printf("layer %d",layer);
	for(int i = start_index;i<end_index;i+=blockDim.x){//move in strides the size of the block
	    //for each element in the array
	    int neighbor_i = i-pow(2,layer); 
	    if(neighbor_i>=0){
		output_data[i]+=data[neighbor_i];//update output
		//tmp_data[i]+=data[i-pow(2,layer)];//update holder container
		//test removal tmp_data[i]=output_data[i];
	    }
	}
	__syncthreads();/*
	if(blockIdx.x==0 && threadIdx.x==0){//copy new array over to data
	    //swap new layers data int "data" for next round
	    //int * tmp = data;
	    //data = tmp_data;
	    //tmp_data = tmp;
	    for i 	
	}*/
	//if(blockIdx.x==0 && threadIdx.x==0) for (int i = 0; i<vals;i++) printf("%d\n",output_data[i]);	
	//prep for next layer
	for(int i = start_index;i<end_index;i+=blockDim.x){
	    data[i] = output_data[i];
	}
	__syncthreads();//sync threads across all blocks before next layer
    }
    //bug removal fix later
    __syncthreads();
    if(blockIdx.x==0 && threadIdx.x==0)for(int i = 2047; i<vals;i+=4096) output_data[i]-=data[0];

}
int * serial_implementation(int * data, int vals) {
    int * output = (int *)malloc(sizeof(int) * vals);
    
    output[0] = 0;
    for (int i = 1; i < vals; i++) {
        output[i] = output[i-1] + data[i-1];
    }
    
    return output;
}

int main(int argc, char ** argv) {
    
    assert(argc == 2);
    int values = atoi(argv[1]); // Values is guaranteed to be no more than 10000000
    int * data = (int *)malloc(sizeof(int) * values);

    // Generate "random" vector
    std::mt19937 gen(13); // Keep constant to maintain determinism between runs
    std::uniform_int_distribution<> dist(0, 50);
    for (int i = 0; i < values; i++) {
        data[i] = dist(gen);
    }

    hipStream_t stream;
    hipEvent_t begin, end;
    hipStreamCreate(&stream);
    hipEventCreate(&begin);
    hipEventCreate(&end);

    int * h_output = (int *)malloc(sizeof(int) * (1+values)); // THIS VARIABLE SHOULD HOLD THE TOTAL COUNT BY THE END

    /*

    PERFORM NECESSARY VARIABLE DECLARATIONS HERE

    PERFORM NECESSARY DATA TRANSFER HERE

    */
	int * gpu_data;
	int * gpu_output_data;
	int * gpu_tmp_data;

	//Determine allocation size
	int array_size = sizeof(int)*values;

	//Allocate memory on GPU
	hipMalloc(&gpu_data, array_size);
	hipMalloc(&gpu_output_data, array_size);
	hipMalloc(&gpu_tmp_data, array_size);
	
	//cudaMalloc(&gpu_data, array_size+sizeof(int));
        //cudaMalloc(&gpu_output_data, array_size+sizeof(int));
        //cudaMalloc(&gpu_tmp_data, array_size+sizeof(int));


	//Copy data to GPU
	hipMemcpy(gpu_data,data,array_size,hipMemcpyHostToDevice);
	hipMemcpy(gpu_output_data,data,array_size,hipMemcpyHostToDevice);
	hipMemcpy(gpu_tmp_data,data,array_size,hipMemcpyHostToDevice);

	//cudaMemcpy(gpu_data+sizeof(int),data,array_size,cudaMemcpyHostToDevice);
        //cudaMemcpy(gpu_output_data+sizeof(int),data,array_size,cudaMemcpyHostToDevice);
        //cudaMemcpy(gpu_tmp_data+sizeof(int),data,array_size,cudaMemcpyHostToDevice);


    hipEventRecord(begin, stream);

    /*

    LAUNCH KERNEL HERE

    */
    int THREADS_PER_BLOCK = 1024;//128 ideal
    int BLOCKS = 1;//16 ideal
    dim3 block(THREADS_PER_BLOCK);
    dim3 grid(BLOCKS);
    parallel_implementation<<<grid,block,0,stream>>>(gpu_data,values,gpu_tmp_data,gpu_output_data);



    hipEventRecord(end, stream);

    /* 

    PERFORM NECESSARY DATA TRANSFER HERE

    */
    hipMemcpy(h_output+1, gpu_output_data, array_size, hipMemcpyDeviceToHost);
    h_output[0] = 0;


    hipStreamSynchronize(stream);

    float ms;
    hipEventElapsedTime(&ms, begin, end);
    printf("Elapsed time: %f ms\n", ms);

    /* 

    DEALLOCATE RESOURCES HERE

    */
	hipFree(gpu_data);
	hipFree(gpu_output_data);
	hipFree(gpu_tmp_data);



    int * reference_output = serial_implementation(data, values);
    for (int i = 0; i < values; i++) {
        if (reference_output[i] != h_output[i]) {
            printf("ERROR: %d != %d at index %d. Off by %d\n", reference_output[i], h_output[i], i,reference_output[i]- h_output[i]);
            
	   /* printf("V | C | GPU\n");
	    for(int j = 0; j< values;j++){
		printf("%d | %d | %d\n",data[j],reference_output[j],h_output[j]);
	    }*/
	    //abort();
        }
    }

    hipEventDestroy(begin);
    hipEventDestroy(end);
    hipStreamDestroy(stream);

    free(data);
    free(reference_output);
    free(h_output);

    return 0;
}

	.text
	.file	"scan.hip"
	.globl	_Z38__device_stub__parallel_implementationPiiS_S_ # -- Begin function _Z38__device_stub__parallel_implementationPiiS_S_
	.type	_Z38__device_stub__parallel_implementationPiiS_S_,@function
_Z38__device_stub__parallel_implementationPiiS_S_: # @_Z38__device_stub__parallel_implementationPiiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z23parallel_implementationPiiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z38__device_stub__parallel_implementationPiiS_S_, .Lfunc_end0-_Z38__device_stub__parallel_implementationPiiS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z21serial_implementationPii    # -- Begin function _Z21serial_implementationPii
	.type	_Z21serial_implementationPii,@function
_Z21serial_implementationPii:           # @_Z21serial_implementationPii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	movl	%esi, %ebp
	movq	%rdi, %rbx
	movslq	%esi, %r14
	leaq	(,%r14,4), %rdi
	callq	malloc
	movl	$0, (%rax)
	cmpl	$2, %r14d
	jl	.LBB1_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%ebp, %ecx
	decq	%rcx
	xorl	%edx, %edx
	xorl	%esi, %esi
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	addl	(%rbx,%rdx,4), %esi
	movl	%esi, 4(%rax,%rdx,4)
	incq	%rdx
	cmpq	%rdx, %rcx
	jne	.LBB1_2
.LBB1_3:                                # %._crit_edge
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z21serial_implementationPii, .Lfunc_end1-_Z21serial_implementationPii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$5080, %rsp                     # imm = 0x13D8
	.cfi_def_cfa_offset 5136
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %ebp
	movslq	%eax, %r15
	leaq	(,%r15,4), %rdi
	callq	malloc
	movq	%rax, %rbx
	movq	$13, 80(%rsp)
	movl	$1, %eax
	movl	$13, %ecx
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	movq	%rcx, %rdx
	shrq	$30, %rdx
	xorl	%ecx, %edx
	imull	$1812433253, %edx, %ecx         # imm = 0x6C078965
	addl	%eax, %ecx
	movq	%rcx, 80(%rsp,%rax,8)
	incq	%rax
	cmpq	$624, %rax                      # imm = 0x270
	jne	.LBB2_1
# %bb.2:                                # %_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEC2Em.exit
	movq	$624, 5072(%rsp)                # imm = 0x270
	movabsq	$214748364800, %rax             # imm = 0x3200000000
	movq	%rax, 72(%rsp)
	movl	%ebp, 12(%rsp)                  # 4-byte Spill
	testl	%ebp, %ebp
	jle	.LBB2_5
# %bb.3:                                # %.lr.ph.preheader
	movl	12(%rsp), %r13d                 # 4-byte Reload
	xorl	%ebp, %ebp
	leaq	80(%rsp), %r14
	leaq	72(%rsp), %r12
.LBB2_4:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movq	%r12, %rdi
	movq	%r14, %rsi
	movq	%r12, %rdx
	callq	_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
	movl	%eax, (%rbx,%rbp,4)
	incq	%rbp
	cmpq	%rbp, %r13
	jne	.LBB2_4
.LBB2_5:                                # %._crit_edge
	leaq	16(%rsp), %rdi
	callq	hipStreamCreate
	leaq	40(%rsp), %rdi
	callq	hipEventCreate
	leaq	32(%rsp), %rdi
	callq	hipEventCreate
	leaq	4(,%r15,4), %rdi
	callq	malloc
	movq	%rax, %r14
	shlq	$34, %r15
	sarq	$32, %r15
	leaq	56(%rsp), %r13
	movq	%r13, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	leaq	24(%rsp), %r12
	movq	%r12, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	leaq	48(%rsp), %rbp
	movq	%rbp, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%r13), %rdi
	movq	%rbx, %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movq	%rbx, %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movq	%rbx, %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	40(%rsp), %rax
	movq	(%rax), %rdi
	leaq	16(%rsp), %r12
	movq	(%r12), %rsi
	callq	hipEventRecord
	movq	(%r12), %r9
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	1023(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movl	12(%rsp), %ebp                  # 4-byte Reload
	jne	.LBB2_7
# %bb.6:
	movq	56(%rsp), %rdi
	movq	48(%rsp), %rdx
	movq	24(%rsp), %rcx
	movl	%ebp, %esi
	callq	_Z38__device_stub__parallel_implementationPiiS_S_
.LBB2_7:
	movq	32(%rsp), %rdi
	movq	16(%rsp), %rsi
	callq	hipEventRecord
	movq	%r14, %rdi
	addq	$4, %rdi
	movq	24(%rsp), %rsi
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$0, (%r14)
	movq	16(%rsp), %rdi
	callq	hipStreamSynchronize
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdx
	leaq	68(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%r15), %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	movl	%ebp, %esi
	callq	_Z21serial_implementationPii
	movq	%rax, %r15
	testl	%ebp, %ebp
	jle	.LBB2_12
# %bb.8:                                # %.lr.ph60.preheader
	movl	%ebp, %r13d
	xorl	%r12d, %r12d
.LBB2_9:                                # %.lr.ph60
                                        # =>This Inner Loop Header: Depth=1
	movl	(%r15,%r12,4), %esi
	movl	(%r14,%r12,4), %edx
	movl	%esi, %r8d
	subl	%edx, %r8d
	je	.LBB2_11
# %bb.10:                               #   in Loop: Header=BB2_9 Depth=1
	movl	$.L.str.1, %edi
	movl	%r12d, %ecx
	xorl	%eax, %eax
	callq	printf
.LBB2_11:                               #   in Loop: Header=BB2_9 Depth=1
	incq	%r12
	cmpq	%r12, %r13
	jne	.LBB2_9
.LBB2_12:                               # %._crit_edge61
	movq	40(%rsp), %rdi
	callq	hipEventDestroy
	movq	32(%rsp), %rdi
	callq	hipEventDestroy
	movq	16(%rsp), %rdi
	callq	hipStreamDestroy
	movq	%rbx, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$5080, %rsp                     # imm = 0x13D8
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.section	.text._ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,"axG",@progbits,_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,comdat
	.weak	_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE # -- Begin function _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
	.p2align	1, 0x90
	.type	_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,@function
_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE: # @_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %r14
	movslq	4(%rdx), %r15
	movq	%rdx, 8(%rsp)                   # 8-byte Spill
	movslq	(%rdx), %rax
	subq	%rax, %r15
	movl	$4294967294, %eax               # imm = 0xFFFFFFFE
	cmpq	%rax, %r15
	ja	.LBB3_2
# %bb.1:
	incl	%r15d
	movq	%r14, %rdi
	movl	%r15d, %esi
	callq	_ZNSt24uniform_int_distributionIiE5_S_ndImSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEjEET1_RT0_S4_
	movl	%eax, %eax
	jmp	.LBB3_7
.LBB3_2:
	movl	$4294967295, %eax               # imm = 0xFFFFFFFF
	cmpq	%rax, %r15
	jne	.LBB3_3
# %bb.6:
	movq	%r14, %rdi
	callq	_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
	jmp	.LBB3_7
.LBB3_3:                                # %.preheader
	movq	%rdi, %r12
	movabsq	$-4294967296, %rbx              # imm = 0xFFFFFFFF00000000
	leaq	16(%rsp), %r13
.LBB3_4:                                # =>This Inner Loop Header: Depth=1
	movq	%rbx, 16(%rsp)
	movq	%r12, %rdi
	movq	%r14, %rsi
	movq	%r13, %rdx
	callq	_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
	movl	%eax, %ebp
	shlq	$32, %rbp
	movq	%r14, %rdi
	callq	_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
	addq	%rbp, %rax
	setb	%cl
	cmpq	%r15, %rax
	ja	.LBB3_4
# %bb.5:                                #   in Loop: Header=BB3_4 Depth=1
	testb	%cl, %cl
	jne	.LBB3_4
.LBB3_7:                                # %.loopexit
	movq	8(%rsp), %rcx                   # 8-byte Reload
	addl	(%rcx), %eax
                                        # kill: def $eax killed $eax killed $rax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, .Lfunc_end3-_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
	.cfi_endproc
                                        # -- End function
	.section	.text._ZNSt24uniform_int_distributionIiE5_S_ndImSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEjEET1_RT0_S4_,"axG",@progbits,_ZNSt24uniform_int_distributionIiE5_S_ndImSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEjEET1_RT0_S4_,comdat
	.weak	_ZNSt24uniform_int_distributionIiE5_S_ndImSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEjEET1_RT0_S4_ # -- Begin function _ZNSt24uniform_int_distributionIiE5_S_ndImSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEjEET1_RT0_S4_
	.p2align	1, 0x90
	.type	_ZNSt24uniform_int_distributionIiE5_S_ndImSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEjEET1_RT0_S4_,@function
_ZNSt24uniform_int_distributionIiE5_S_ndImSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEjEET1_RT0_S4_: # @_ZNSt24uniform_int_distributionIiE5_S_ndImSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEjEET1_RT0_S4_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	movl	%esi, %ebp
	movq	%rdi, %rbx
	callq	_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
	movq	%rax, %rcx
	movl	%ebp, %r14d
	imulq	%r14, %rcx
	cmpl	%ebp, %ecx
	jae	.LBB4_4
# %bb.1:
	movl	%ebp, %eax
	negl	%eax
	xorl	%edx, %edx
	divl	%ebp
	cmpl	%ecx, %edx
	jbe	.LBB4_4
# %bb.2:                                # %.lr.ph.preheader
	movl	%edx, %ebp
.LBB4_3:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movq	%rbx, %rdi
	callq	_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
	movq	%rax, %rcx
	imulq	%r14, %rcx
	cmpl	%ecx, %ebp
	ja	.LBB4_3
.LBB4_4:                                # %.loopexit
	shrq	$32, %rcx
	movl	%ecx, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_ZNSt24uniform_int_distributionIiE5_S_ndImSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEjEET1_RT0_S4_, .Lfunc_end4-_ZNSt24uniform_int_distributionIiE5_S_ndImSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEjEET1_RT0_S4_
	.cfi_endproc
                                        # -- End function
	.section	.text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,comdat
	.weak	_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv # -- Begin function _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
	.p2align	1, 0x90
	.type	_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,@function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv: # @_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	%rdi, %rbx
	movq	4992(%rdi), %rax
	cmpq	$624, %rax                      # imm = 0x270
	jb	.LBB5_2
# %bb.1:
	movq	%rbx, %rdi
	callq	_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
	movq	4992(%rbx), %rax
.LBB5_2:
	leaq	1(%rax), %rcx
	movq	%rcx, 4992(%rbx)
	movq	(%rbx,%rax,8), %rax
	movq	%rax, %rcx
	shrq	$11, %rcx
	movl	%ecx, %ecx
	xorq	%rax, %rcx
	movl	%ecx, %eax
	shll	$7, %eax
	andl	$-1658038656, %eax              # imm = 0x9D2C5680
	xorq	%rcx, %rax
	movl	%eax, %ecx
	shll	$15, %ecx
	andl	$-272236544, %ecx               # imm = 0xEFC60000
	xorq	%rax, %rcx
	movq	%rcx, %rax
	shrq	$18, %rax
	xorq	%rcx, %rax
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, .Lfunc_end5-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
	.cfi_endproc
                                        # -- End function
	.section	.text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,comdat
	.weak	_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv # -- Begin function _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
	.p2align	1, 0x90
	.type	_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,@function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv: # @_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
	.cfi_startproc
# %bb.0:
	movl	$2567483615, %eax               # imm = 0x9908B0DF
	movq	(%rdi), %rdx
	xorl	%ecx, %ecx
.LBB6_1:                                # =>This Inner Loop Header: Depth=1
	andq	$-2147483648, %rdx              # imm = 0x80000000
	movq	8(%rdi,%rcx,8), %rsi
	movl	%esi, %r8d
	andl	$2147483646, %r8d               # imm = 0x7FFFFFFE
	orq	%rdx, %r8
	shrq	%r8
	xorq	3176(%rdi,%rcx,8), %r8
	movq	%rsi, %rdx
                                        # kill: def $esi killed $esi killed $rsi def $rsi
	andl	$1, %esi
	negl	%esi
	andl	%eax, %esi
	xorq	%r8, %rsi
	movq	%rsi, (%rdi,%rcx,8)
	leaq	1(%rcx), %rsi
	movq	%rsi, %rcx
	cmpq	$227, %rsi
	jne	.LBB6_1
# %bb.2:                                # %.preheader.preheader
	movq	1816(%rdi), %rdx
	movl	$228, %ecx
.LBB6_3:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	andq	$-2147483648, %rdx              # imm = 0x80000000
	movq	(%rdi,%rcx,8), %rsi
	movl	%esi, %r8d
	andl	$2147483646, %r8d               # imm = 0x7FFFFFFE
	orq	%rdx, %r8
	shrq	%r8
	xorq	-1824(%rdi,%rcx,8), %r8
	movq	%rsi, %rdx
                                        # kill: def $esi killed $esi killed $rsi def $rsi
	andl	$1, %esi
	negl	%esi
	andl	%eax, %esi
	xorq	%r8, %rsi
	movq	%rsi, -8(%rdi,%rcx,8)
	incq	%rcx
	cmpq	$624, %rcx                      # imm = 0x270
	jne	.LBB6_3
# %bb.4:
	movq	$-2147483648, %rcx              # imm = 0x80000000
	andq	4984(%rdi), %rcx
	movq	(%rdi), %rdx
	movl	%edx, %esi
	andl	$2147483646, %esi               # imm = 0x7FFFFFFE
	orq	%rcx, %rsi
	shrq	%rsi
	xorq	3168(%rdi), %rsi
	andl	$1, %edx
	negl	%edx
	andl	%eax, %edx
	xorq	%rsi, %rdx
	movq	%rdx, 4984(%rdi)
	movq	$0, 4992(%rdi)
	retq
.Lfunc_end6:
	.size	_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv, .Lfunc_end6-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB7_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB7_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23parallel_implementationPiiS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end7:
	.size	__hip_module_ctor, .Lfunc_end7-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB8_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB8_2:
	retq
.Lfunc_end8:
	.size	__hip_module_dtor, .Lfunc_end8-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z23parallel_implementationPiiS_S_,@object # @_Z23parallel_implementationPiiS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z23parallel_implementationPiiS_S_
	.p2align	3, 0x0
_Z23parallel_implementationPiiS_S_:
	.quad	_Z38__device_stub__parallel_implementationPiiS_S_
	.size	_Z23parallel_implementationPiiS_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Elapsed time: %f ms\n"
	.size	.L.str, 21

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"ERROR: %d != %d at index %d. Off by %d\n"
	.size	.L.str.1, 40

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z23parallel_implementationPiiS_S_"
	.size	.L__unnamed_1, 35

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z38__device_stub__parallel_implementationPiiS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z23parallel_implementationPiiS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z23parallel_implementationPiiS_S_ ; -- Begin function _Z23parallel_implementationPiiS_S_
	.globl	_Z23parallel_implementationPiiS_S_
	.p2align	8
	.type	_Z23parallel_implementationPiiS_S_,@function
_Z23parallel_implementationPiiS_S_:     ; @_Z23parallel_implementationPiiS_S_
; %bb.0:
	s_load_b32 s14, s[0:1], 0x8
	s_add_u32 s6, s0, 32
	s_addc_u32 s7, s1, 0
	s_mov_b32 s33, 0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s14, 2
	s_cbranch_scc1 .LBB0_3
; %bb.1:                                ; %.lr.ph.i.preheader
	v_cvt_f32_i32_e32 v1, s14
.LBB0_2:                                ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, 0.5, v1
	s_add_i32 s33, s33, 1
	v_cmp_lt_f32_e32 vcc_lo, 1.0, v1
	s_cbranch_vccnz .LBB0_2
.LBB0_3:                                ; %Flow66
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x20
	s_load_b64 s[4:5], s[0:1], 0x0
	s_load_b64 s[8:9], s[0:1], 0x18
	s_cmp_lt_i32 s33, 1
	s_cbranch_scc1 .LBB0_14
; %bb.4:                                ; %.preheader40.lr.ph
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v1, s2
	s_sub_i32 s1, 0, s2
	s_mul_i32 s0, s15, s14
	s_mov_b32 s10, 0x55555555
	s_mov_b32 s12, 0x968915a9
	v_rcp_iflag_f32_e32 v1, v1
	s_mov_b32 s16, 0x4222de17
	s_mov_b32 s18, 0x3abe935a
	s_mov_b32 s20, 0x47e6c9c2
	s_mov_b32 s22, 0xcfa74449
	s_mov_b32 s24, 0x71bf3c30
	s_mov_b32 s26, 0x1c7792ce
	s_mov_b32 s28, 0x924920da
	s_mov_b32 s38, 0xd5df274d
	s_mov_b32 s40, 0x652b82fe
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v1
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s44, 0x6a5dcb37
	s_delay_alu instid0(VALU_DEP_3)
	v_cvt_u32_f32_e32 v3, v3
	s_mov_b32 s46, 0x623fde64
	s_mov_b32 s48, 0x7c89e6b0
	s_mov_b32 s50, 0x14761f6e
	s_mov_b32 s52, 0x1852b7b0
	v_readfirstlane_b32 s3, v3
	s_mov_b32 s54, 0x11122322
	s_mov_b32 s56, 0x555502a1
	s_mov_b32 s58, 0x55555511
	s_mov_b32 s60, 11
	s_mul_i32 s1, s1, s3
	s_mov_b32 s68, 0
	s_mul_hi_u32 s1, s3, s1
	s_mov_b32 s11, 0x3fe55555
	s_add_i32 s3, s3, s1
	s_mov_b32 s13, 0x3fba6564
	s_mul_hi_u32 s1, s0, s3
	s_mov_b32 s17, 0x3fbdee67
	s_mul_i32 s30, s1, s2
	s_add_i32 s35, s1, 1
	s_sub_i32 s34, s0, s30
	s_mov_b32 s30, 0x9999999c
	s_sub_i32 s36, s34, s2
	s_cmp_ge_u32 s34, s2
	s_mov_b32 s19, 0x3fbe25e4
	s_cselect_b32 s1, s35, s1
	s_cselect_b32 s34, s36, s34
	s_add_i32 s36, s1, 1
	s_cmp_ge_u32 s34, s2
	s_mov_b32 s34, 0xfefa39ef
	s_cselect_b32 s1, s36, s1
	s_add_i32 s0, s0, s14
	v_add_nc_u32_e32 v9, s1, v0
	s_mul_hi_u32 s3, s0, s3
	s_mov_b32 s36, 0x3b39803f
	s_mul_i32 s42, s3, s2
	s_mov_b32 s21, 0x3fc110ef
	s_sub_i32 s0, s0, s42
	s_add_i32 s42, s3, 1
	s_sub_i32 s43, s0, s2
	s_cmp_ge_u32 s0, s2
	s_mov_b32 s23, 0x3fc3b13b
	s_cselect_b32 s1, s42, s3
	s_cselect_b32 s0, s43, s0
	s_add_i32 s3, s1, 1
	s_cmp_ge_u32 s0, s2
	s_mov_b32 s42, 0xfca7ab0c
	s_cselect_b32 s69, s3, s1
	s_mov_b32 s25, 0x3fc745d1
	v_cmp_gt_i32_e32 vcc_lo, s69, v9
	s_mov_b32 s27, 0x3fcc71c7
	s_mov_b32 s29, 0x3fd24924
	s_mov_b32 s31, 0x3fd99999
	s_mov_b32 s35, 0x3fe62e42
	s_mov_b32 s37, 0x3c7abc9e
	s_mov_b32 s39, 0x3c8543b0
	s_mov_b32 s41, 0x3ff71547
	s_mov_b32 s43, 0x3e928af3
	s_mov_b32 s45, 0x3e5ade15
	s_mov_b32 s47, 0x3ec71dee
	s_mov_b32 s49, 0x3efa0199
	s_mov_b32 s51, 0x3f2a01a0
	s_mov_b32 s53, 0x3f56c16c
	s_mov_b32 s55, 0x3f811111
	s_mov_b32 s57, 0x3fa55555
	s_mov_b32 s59, 0x3fc55555
	s_mov_b32 s61, 0x3fe00000
	s_mov_b32 s3, 0xbfe55555
	s_mov_b32 s63, 0xbfe62e42
	s_mov_b32 s65, 0xbc7abc9e
.LBB0_5:                                ; %.preheader40
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
                                        ;     Child Loop BB0_12 Depth 2
	s_and_saveexec_b32 s70, vcc_lo
	s_cbranch_execz .LBB0_10
; %bb.6:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_cmp_eq_u32 s68, 0
	s_mov_b32 s66, 0
	s_cselect_b32 s67, 0x3ff00000, 2.0
	s_mov_b32 s2, s10
	v_frexp_mant_f64_e32 v[5:6], s[66:67]
	s_mov_b32 s62, s34
	s_mov_b32 s64, s36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e64 s0, s[10:11], v[5:6]
	v_cndmask_b32_e64 v3, 0, 1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[5:6], v[5:6], v3
	v_frexp_exp_i32_f64_e32 v3, s[66:67]
	v_add_f64 v[7:8], v[5:6], 1.0
	v_add_f64 v[14:15], v[5:6], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v3, s0, 0, v3, s0
	v_rcp_f64_e32 v[10:11], v[7:8]
	v_add_f64 v[16:17], v[7:8], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[5:6], -v[16:17]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[12:13], -v[7:8], v[10:11], 1.0
	v_fma_f64 v[10:11], v[12:13], v[10:11], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], -v[7:8], v[10:11], 1.0
	v_fma_f64 v[10:11], v[12:13], v[10:11], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[12:13], v[14:15], v[10:11]
	v_mul_f64 v[18:19], v[7:8], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[12:13], v[7:8], -v[18:19]
	v_fma_f64 v[5:6], v[12:13], v[5:6], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[18:19], v[5:6]
	v_add_f64 v[16:17], v[14:15], -v[7:8]
	v_add_f64 v[18:19], v[7:8], -v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[14:15], v[14:15], -v[16:17]
	v_add_f64 v[5:6], v[18:19], -v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[14:15], -v[7:8]
	v_add_f64 v[5:6], v[5:6], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[16:17], v[5:6]
	v_mul_f64 v[5:6], v[10:11], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[12:13], v[5:6]
	v_add_f64 v[10:11], v[7:8], -v[12:13]
	v_mul_f64 v[12:13], v[7:8], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[5:6], -v[10:11]
	v_fma_f64 v[10:11], v[7:8], v[7:8], -v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[14:15], v[5:6], v[5:6]
	v_fma_f64 v[10:11], v[7:8], v[14:15], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[14:15], v[12:13], v[10:11]
	v_fma_f64 v[16:17], v[14:15], s[16:17], s[12:13]
	v_add_f64 v[12:13], v[14:15], -v[12:13]
	v_mul_f64 v[22:23], v[7:8], v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[16:17], v[14:15], v[16:17], s[18:19]
	v_add_f64 v[10:11], v[10:11], -v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[14:15], v[16:17], s[20:21]
	v_fma_f64 v[16:17], v[14:15], v[16:17], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[14:15], v[16:17], s[24:25]
	v_fma_f64 v[16:17], v[14:15], v[16:17], s[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[14:15], v[16:17], s[28:29]
	v_fma_f64 v[16:17], v[14:15], v[16:17], s[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[18:19], v[14:15], v[16:17]
	v_fma_f64 v[12:13], v[14:15], v[16:17], -v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], v[16:17], v[12:13]
	v_add_f64 v[16:17], v[18:19], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[16:17], s[10:11]
	v_add_f64 v[18:19], v[16:17], -v[18:19]
	v_add_f64 v[24:25], v[20:21], s[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[12:13], -v[18:19]
	v_fma_f64 v[18:19], v[14:15], v[7:8], -v[22:23]
	v_add_f64 v[16:17], v[16:17], -v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[12:13], s[38:39]
	v_fma_f64 v[14:15], v[14:15], v[5:6], v[18:19]
	v_ldexp_f64 v[5:6], v[5:6], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[12:13], v[16:17]
	v_fma_f64 v[10:11], v[10:11], v[7:8], v[14:15]
	v_ldexp_f64 v[7:8], v[7:8], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[20:21], v[12:13]
	v_add_f64 v[16:17], v[22:23], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[20:21], -v[14:15]
	v_mul_f64 v[20:21], v[16:17], v[14:15]
	v_add_f64 v[22:23], v[16:17], -v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[12:13], v[18:19]
	v_fma_f64 v[18:19], v[16:17], v[14:15], -v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[10:11], -v[22:23]
	v_fma_f64 v[12:13], v[16:17], v[12:13], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[10:11], v[10:11], v[14:15], v[12:13]
	v_cvt_f64_i32_e32 v[14:15], v3
	v_add_f64 v[12:13], v[20:21], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[16:17], v[7:8], v[12:13]
	v_add_f64 v[18:19], v[12:13], -v[20:21]
	v_mul_f64 v[20:21], v[14:15], s[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[16:17], -v[7:8]
	v_add_f64 v[10:11], v[10:11], -v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[18:19], v[14:15], s[34:35], -v[20:21]
	v_add_f64 v[7:8], v[12:13], -v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[5:6], v[5:6], v[10:11]
	v_fma_f64 v[10:11], v[14:15], s[36:37], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[5:6], v[7:8]
	v_add_f64 v[7:8], v[20:21], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[16:17], v[5:6]
	v_add_f64 v[20:21], v[7:8], -v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[7:8], v[12:13]
	v_add_f64 v[16:17], v[12:13], -v[16:17]
	v_add_f64 v[10:11], v[10:11], -v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[14:15], -v[7:8]
	v_add_f64 v[5:6], v[5:6], -v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[22:23], v[14:15], -v[18:19]
	v_add_f64 v[12:13], v[12:13], -v[18:19]
	v_add_f64 v[16:17], v[10:11], v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], -v[22:23]
	v_add_f64 v[7:8], v[12:13], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[16:17], -v[10:11]
	v_add_f64 v[7:8], v[16:17], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[16:17], -v[12:13]
	v_add_f64 v[5:6], v[5:6], -v[12:13]
	v_add_f64 v[18:19], v[14:15], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[10:11], -v[16:17]
	v_add_f64 v[12:13], v[18:19], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[5:6], v[10:11]
	v_add_f64 v[7:8], v[7:8], -v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[5:6], v[7:8]
	v_add_f64 v[7:8], v[18:19], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[7:8], -v[18:19]
	v_mul_f64 v[12:13], v[7:8], v[1:2]
	v_add_f64 v[5:6], v[5:6], -v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[7:8], v[1:2], v[7:8], -v[12:13]
	v_cmp_class_f64_e64 s0, v[12:13], 0x204
	v_fma_f64 v[5:6], v[1:2], v[5:6], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[12:13], v[5:6]
	v_cndmask_b32_e64 v11, v8, v13, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v10, v7, v12, s0
	v_add_f64 v[7:8], v[7:8], -v[12:13]
	v_mul_f64 v[14:15], v[10:11], s[40:41]
	v_cmp_nlt_f64_e64 s1, 0x40900000, v[10:11]
	v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[10:11]|
	v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[10:11]
	v_add_f64 v[5:6], v[5:6], -v[7:8]
	v_rndne_f64_e32 v[14:15], v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, 0, v6, s0
	v_cndmask_b32_e64 v5, 0, v5, s0
	s_and_b32 s0, s2, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[16:17], v[14:15], s[62:63], v[10:11]
	v_cvt_i32_f64_e32 v3, v[14:15]
	v_fma_f64 v[16:17], v[14:15], s[64:65], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[16:17], s[44:45], s[42:43]
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[46:47]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[48:49]
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[50:51]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[52:53]
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[54:55]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[56:57]
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[58:59]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[60:61]
	v_fma_f64 v[18:19], v[16:17], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[16:17], v[18:19], 1.0
	v_ldexp_f64 v[12:13], v[14:15], v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, 0x7ff00000, v13, s1
	v_cndmask_b32_e64 v7, 0, v12, s0
	s_load_b32 s1, s[6:7], 0xc
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v8, 0, v3, s2
	v_fma_f64 v[5:6], v[7:8], v[5:6], v[7:8]
	v_cmp_class_f64_e64 s0, v[7:8], 0x204
	s_waitcnt lgkmcnt(0)
	s_and_b32 s1, s1, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, v6, v8, s0
	v_cndmask_b32_e64 v5, v5, v7, s0
	v_mov_b32_e32 v7, v9
.LBB0_7:                                ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f64_i32_e32 v[10:11], v7
	s_mov_b32 s2, exec_lo
	v_add_f64 v[10:11], v[10:11], -|v[5:6]|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f64_e32 v3, v[10:11]
	v_cmpx_lt_i32_e32 -1, v3
	s_cbranch_execz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_7 Depth=2
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[10:11], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[12:13], 2, v[7:8]
	v_add_co_u32 v10, s0, s4, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v11, s0, s5, v11, s0
	v_add_co_u32 v12, s0, s8, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v13, s0, s9, v13, s0
	global_load_b32 v3, v[10:11], off
	global_load_b32 v8, v[12:13], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, v8, v3
	global_store_b32 v[12:13], v3, off
.LBB0_9:                                ;   in Loop: Header=BB0_7 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v7, s1, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_i32_e64 s0, s69, v7
	s_or_b32 s66, s0, s66
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s66
	s_cbranch_execnz .LBB0_7
.LBB0_10:                               ; %Flow62
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s70
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_13
; %bb.11:                               ; %.lr.ph44
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_load_b32 s0, s[6:7], 0xc
	v_mov_b32_e32 v5, v9
	s_mov_b32 s64, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s62, s0, 0xffff
.LBB0_12:                               ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[6:7], 2, v[5:6]
	v_add_nc_u32_e32 v5, s62, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s0, s8, v6
	v_add_co_ci_u32_e64 v11, s0, s9, v7, s0
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_le_i32_e64 s0, s69, v5
	v_add_co_u32 v6, s1, s4, v6
	global_load_b32 v3, v[10:11], off
	v_add_co_ci_u32_e64 v7, s1, s5, v7, s1
	s_or_b32 s64, s0, s64
	s_waitcnt vmcnt(0)
	global_store_b32 v[6:7], v3, off
	s_and_not1_b32 exec_lo, exec_lo, s64
	s_cbranch_execnz .LBB0_12
.LBB0_13:                               ; %Flow60
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_add_f64 v[1:2], v[1:2], 1.0
	s_add_i32 s68, s68, 1
	s_waitcnt_vscnt null, 0x0
	s_cmp_eq_u32 s68, s33
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_5
.LBB0_14:                               ; %._crit_edge47
	v_or_b32_e32 v0, s15, v0
	s_cmpk_gt_i32 s14, 0x7ff
	s_waitcnt lgkmcnt(0)
	s_movk_i32 s2, 0x7ff
	s_cselect_b32 s0, -1, 0
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_barrier
	buffer_gl0_inv
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_17
; %bb.15:                               ; %.lr.ph49.preheader
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s8, 0x1ffc
	s_addc_u32 s1, s9, 0
.LBB0_16:                               ; %.lr.ph49
                                        ; =>This Inner Loop Header: Depth=1
	s_clause 0x1
	global_load_b32 v1, v0, s[4:5]
	global_load_b32 v2, v0, s[0:1]
	s_addk_i32 s2, 0x1000
	s_waitcnt vmcnt(0)
	v_sub_nc_u32_e32 v1, v2, v1
	global_store_b32 v0, v1, s[0:1]
	s_add_u32 s0, s0, 0x4000
	s_addc_u32 s1, s1, 0
	s_cmp_lt_i32 s2, s14
	s_cbranch_scc1 .LBB0_16
.LBB0_17:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23parallel_implementationPiiS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 26
		.amdhsa_next_free_sgpr 71
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z23parallel_implementationPiiS_S_, .Lfunc_end0-_Z23parallel_implementationPiiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2672
; NumSgprs: 73
; NumVgprs: 26
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 9
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 73
; NumVGPRsForWavesPerEU: 26
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z23parallel_implementationPiiS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     73
    .sgpr_spill_count: 0
    .symbol:         _Z23parallel_implementationPiiS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     26
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
