#include "includes.h"
__global__ void gpu_stencil37_hack2_cp_rows(double * dst, double * shared_rows, double *shared_cols,double *shared_slices,int d_xpitch,int d_ypitch,int d_zpitch,int s_xpitch,int s_ypitch, int s_zpitch, int n_rows, int n_cols,int n_slices,int tile_x,int tile_y, int tile_z){

#ifdef CUDA_DARTS_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(blockIdx.z==0)&&(threadIdx.x==0)){
printf("copy rows: begin\n");
printf("copy rows: n_cols=%d,n_rows=%d,n_slices=%d\n",n_cols,n_rows,n_slices);
printf("copy rows: gridDim.x=%d,gridDim.y=%d,gridDim.z=%d\n",gridDim.x,gridDim.y,gridDim.z);
printf("copy rows: blockDim.x=%d,blockDim.y=%d,blockDim.z=%d\n",blockDim.x,blockDim.y,blockDim.z);
printf("copy rows: tile_x=%d,tile_y=%d,tile_z=%d\n",tile_x,tile_y,tile_z);
}
#endif
int base_global_slice = tile_z * blockIdx.z;
int base_global_row   = tile_y  * blockIdx.y;
int base_global_col   = blockDim.x*blockIdx.x;

//int dst_area = n_rows*n_cols;
//int s_area = gridDim.y*n_cols*2;
int dst_area = d_ypitch*d_xpitch;
int s_area = gridDim.y*s_xpitch*2;

//int base_global_idx = base_global_slice*dst_area + base_global_row * n_cols + base_global_col;
int base_global_idx = base_global_slice*dst_area + base_global_row * d_xpitch + base_global_col;

int nextRow = base_global_row+1;
bool legalNextRow = nextRow<n_rows;

int tx = threadIdx.x;
bool legalCurCol = (base_global_col + tx)<n_cols;

for(int tz=0;tz<tile_z;++tz){
bool legalCurSlice = (base_global_slice + tz)<n_slices;
int idx_dst =base_global_idx + tz*dst_area+ tx  ;
//int idx = (base_global_slice+tz)*s_area + blockIdx.y*n_cols*2+blockIdx.x*blockDim.x+ tx  ;
int idx = (base_global_slice+tz)*s_area + blockIdx.y*s_xpitch*2+blockIdx.x*blockDim.x+ tx  ;
if(legalCurCol && legalCurSlice){
shared_rows[idx] = dst[idx_dst];
}
if(legalCurCol && legalCurSlice && legalNextRow){
//shared_rows[idx+n_cols] = dst[idx_dst+n_cols];
shared_rows[idx+s_xpitch] = dst[idx_dst+d_xpitch];
}


}
__syncthreads();

#ifdef CUDA_CUDA_DEBUG
if(blockIdx.y==0 && blockIdx.x==0 &&blockIdx.z==0 ){
if((threadIdx.x==0 || threadIdx.x==1 || threadIdx.x==2 ) && threadIdx.y==0){

int d_addr0 = base_global_idx+0*dst_area+threadIdx.x;
int d_addr1 = base_global_idx+1*dst_area+threadIdx.x;
int s_addr00  = base_global_slice+blockIdx.x*blockDim.x + threadIdx.x;
int s_addr01  = base_global_slice+blockIdx.x*blockDim.x + threadIdx.x+s_xpitch;
int s_addr02  = base_global_slice+blockIdx.x*blockDim.x + threadIdx.x+s_xpitch*2;
int s_addr10 = s_area*(base_global_slice+1)+blockIdx.x*blockDim.x+ threadIdx.x;
int s_addr11 = s_area*(base_global_slice+1)+blockIdx.x*blockDim.x+ threadIdx.x+s_xpitch;
int s_addr12 = s_area*(base_global_slice+1)+blockIdx.x*blockDim.x+ threadIdx.x+s_xpitch*2;
int s_addr20 = s_area*(base_global_slice+2)+blockIdx.x*blockDim.x+ threadIdx.x;
int s_addr21 = s_area*(base_global_slice+2)+blockIdx.x*blockDim.x+ threadIdx.x+s_xpitch;
int s_addr22 = s_area*(base_global_slice+2)+blockIdx.x*blockDim.x+ threadIdx.x+s_xpitch*2;
printf("copy rows: blockIdx.x=%d, blockIdx.y=%d,blockIdx.z=%d,dst        : z:%d, addr:%d, val = %f\n",blockIdx.x, blockIdx.y,blockIdx.z,0,d_addr0,dst[d_addr0]);
printf("copy rows: blockIdx.x=%d, blockIdx.y=%d,blockIdx.z=%d,dst        : z:%d, addr:%d, val = %f\n",blockIdx.x, blockIdx.y,blockIdx.z,1,d_addr1,dst[d_addr1]);
printf("copy rows: blockIdx.x=%d, blockIdx.y=%d,blockIdx.z=%d,shared_rows: z:%d, addr:%d, val = %f\n",blockIdx.x, blockIdx.y,blockIdx.z,0,s_addr00,shared_rows[s_addr00]);
printf("copy rows: blockIdx.x=%d, blockIdx.y=%d,blockIdx.z=%d,shared_rows: z:%d, addr:%d, val = %f\n",blockIdx.x, blockIdx.y,blockIdx.z,1,s_addr01,shared_rows[s_addr01]);
printf("copy rows: blockIdx.x=%d, blockIdx.y=%d,blockIdx.z=%d,shared_rows: z:%d, addr:%d, val = %f\n",blockIdx.x, blockIdx.y,blockIdx.z,2,s_addr00,shared_rows[s_addr02]);
printf("copy rows: blockIdx.x=%d, blockIdx.y=%d,blockIdx.z=%d,shared_rows: z:%d, addr:%d, val = %f\n",blockIdx.x, blockIdx.y,blockIdx.z,1,s_addr10,shared_rows[s_addr10]);
printf("copy rows: blockIdx.x=%d, blockIdx.y=%d,blockIdx.z=%d,shared_rows: z:%d, addr:%d, val = %f\n",blockIdx.x, blockIdx.y,blockIdx.z,1,s_addr11,shared_rows[s_addr11]);
printf("copy rows: blockIdx.x=%d, blockIdx.y=%d,blockIdx.z=%d,shared_rows: z:%d, addr:%d, val = %f\n",blockIdx.x, blockIdx.y,blockIdx.z,1,s_addr12,shared_rows[s_addr12]);
printf("copy rows: blockIdx.x=%d, blockIdx.y=%d,blockIdx.z=%d,shared_rows: z:%d, addr:%d, val = %f\n",blockIdx.x, blockIdx.y,blockIdx.z,2,s_addr20,shared_rows[s_addr20]);
printf("copy rows: blockIdx.x=%d, blockIdx.y=%d,blockIdx.z=%d,shared_rows: z:%d, addr:%d, val = %f\n",blockIdx.x, blockIdx.y,blockIdx.z,2,s_addr21,shared_rows[s_addr21]);
printf("copy rows: blockIdx.x=%d, blockIdx.y=%d,blockIdx.z=%d,shared_rows: z:%d, addr:%d, val = %f\n",blockIdx.x, blockIdx.y,blockIdx.z,2,s_addr22,shared_rows[s_addr22]);
}
if(threadIdx.x==0 && threadIdx.y==0){
int addr =  2*s_area+n_cols+256;
int addr1 = 2*dst_area+n_cols+256;
printf("copy rows: shared_rows: addr:%d, val:%f\n", addr, shared_rows[addr]);
printf("copy rows: dst        : addr:%d, val:%f\n", addr1, dst[addr1]);
}
}
#endif

#ifdef CUDA_DARTS_DEBUG

if((blockIdx.x==0)&&(blockIdx.y==0)&&(blockIdx.z==0)&&(threadIdx.x==0)){
printf("copy rows end!\n");
}
#endif
}
	.file	"tmpxft_00218c88_00000000-6_gpu_stencil37_hack2_cp_rows.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z65__device_stub__Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiiiPdS_S_S_iiiiiiiiiiii
	.type	_Z65__device_stub__Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiiiPdS_S_S_iiiiiiiiiiii, @function
_Z65__device_stub__Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiiiPdS_S_S_iiiiiiiiiiii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	296(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	320(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	328(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	336(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	344(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 288
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L2:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z65__device_stub__Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiiiPdS_S_S_iiiiiiiiiiii, .-_Z65__device_stub__Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiiiPdS_S_S_iiiiiiiiiiii
	.globl	_Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii
	.type	_Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii, @function
_Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z65__device_stub__Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiiiPdS_S_S_iiiiiiiiiiii
	.cfi_endproc
.LFE2033:
	.size	_Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii, .-_Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_stencil37_hack2_cp_rows(double * dst, double * shared_rows, double *shared_cols,double *shared_slices,int d_xpitch,int d_ypitch,int d_zpitch,int s_xpitch,int s_ypitch, int s_zpitch, int n_rows, int n_cols,int n_slices,int tile_x,int tile_y, int tile_z){

#ifdef CUDA_DARTS_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(blockIdx.z==0)&&(threadIdx.x==0)){
printf("copy rows: begin\n");
printf("copy rows: n_cols=%d,n_rows=%d,n_slices=%d\n",n_cols,n_rows,n_slices);
printf("copy rows: gridDim.x=%d,gridDim.y=%d,gridDim.z=%d\n",gridDim.x,gridDim.y,gridDim.z);
printf("copy rows: blockDim.x=%d,blockDim.y=%d,blockDim.z=%d\n",blockDim.x,blockDim.y,blockDim.z);
printf("copy rows: tile_x=%d,tile_y=%d,tile_z=%d\n",tile_x,tile_y,tile_z);
}
#endif
int base_global_slice = tile_z * blockIdx.z;
int base_global_row   = tile_y  * blockIdx.y;
int base_global_col   = blockDim.x*blockIdx.x;

//int dst_area = n_rows*n_cols;
//int s_area = gridDim.y*n_cols*2;
int dst_area = d_ypitch*d_xpitch;
int s_area = gridDim.y*s_xpitch*2;

//int base_global_idx = base_global_slice*dst_area + base_global_row * n_cols + base_global_col;
int base_global_idx = base_global_slice*dst_area + base_global_row * d_xpitch + base_global_col;

int nextRow = base_global_row+1;
bool legalNextRow = nextRow<n_rows;

int tx = threadIdx.x;
bool legalCurCol = (base_global_col + tx)<n_cols;

for(int tz=0;tz<tile_z;++tz){
bool legalCurSlice = (base_global_slice + tz)<n_slices;
int idx_dst =base_global_idx + tz*dst_area+ tx  ;
//int idx = (base_global_slice+tz)*s_area + blockIdx.y*n_cols*2+blockIdx.x*blockDim.x+ tx  ;
int idx = (base_global_slice+tz)*s_area + blockIdx.y*s_xpitch*2+blockIdx.x*blockDim.x+ tx  ;
if(legalCurCol && legalCurSlice){
shared_rows[idx] = dst[idx_dst];
}
if(legalCurCol && legalCurSlice && legalNextRow){
//shared_rows[idx+n_cols] = dst[idx_dst+n_cols];
shared_rows[idx+s_xpitch] = dst[idx_dst+d_xpitch];
}


}
__syncthreads();

#ifdef CUDA_CUDA_DEBUG
if(blockIdx.y==0 && blockIdx.x==0 &&blockIdx.z==0 ){
if((threadIdx.x==0 || threadIdx.x==1 || threadIdx.x==2 ) && threadIdx.y==0){

int d_addr0 = base_global_idx+0*dst_area+threadIdx.x;
int d_addr1 = base_global_idx+1*dst_area+threadIdx.x;
int s_addr00  = base_global_slice+blockIdx.x*blockDim.x + threadIdx.x;
int s_addr01  = base_global_slice+blockIdx.x*blockDim.x + threadIdx.x+s_xpitch;
int s_addr02  = base_global_slice+blockIdx.x*blockDim.x + threadIdx.x+s_xpitch*2;
int s_addr10 = s_area*(base_global_slice+1)+blockIdx.x*blockDim.x+ threadIdx.x;
int s_addr11 = s_area*(base_global_slice+1)+blockIdx.x*blockDim.x+ threadIdx.x+s_xpitch;
int s_addr12 = s_area*(base_global_slice+1)+blockIdx.x*blockDim.x+ threadIdx.x+s_xpitch*2;
int s_addr20 = s_area*(base_global_slice+2)+blockIdx.x*blockDim.x+ threadIdx.x;
int s_addr21 = s_area*(base_global_slice+2)+blockIdx.x*blockDim.x+ threadIdx.x+s_xpitch;
int s_addr22 = s_area*(base_global_slice+2)+blockIdx.x*blockDim.x+ threadIdx.x+s_xpitch*2;
printf("copy rows: blockIdx.x=%d, blockIdx.y=%d,blockIdx.z=%d,dst        : z:%d, addr:%d, val = %f\n",blockIdx.x, blockIdx.y,blockIdx.z,0,d_addr0,dst[d_addr0]);
printf("copy rows: blockIdx.x=%d, blockIdx.y=%d,blockIdx.z=%d,dst        : z:%d, addr:%d, val = %f\n",blockIdx.x, blockIdx.y,blockIdx.z,1,d_addr1,dst[d_addr1]);
printf("copy rows: blockIdx.x=%d, blockIdx.y=%d,blockIdx.z=%d,shared_rows: z:%d, addr:%d, val = %f\n",blockIdx.x, blockIdx.y,blockIdx.z,0,s_addr00,shared_rows[s_addr00]);
printf("copy rows: blockIdx.x=%d, blockIdx.y=%d,blockIdx.z=%d,shared_rows: z:%d, addr:%d, val = %f\n",blockIdx.x, blockIdx.y,blockIdx.z,1,s_addr01,shared_rows[s_addr01]);
printf("copy rows: blockIdx.x=%d, blockIdx.y=%d,blockIdx.z=%d,shared_rows: z:%d, addr:%d, val = %f\n",blockIdx.x, blockIdx.y,blockIdx.z,2,s_addr00,shared_rows[s_addr02]);
printf("copy rows: blockIdx.x=%d, blockIdx.y=%d,blockIdx.z=%d,shared_rows: z:%d, addr:%d, val = %f\n",blockIdx.x, blockIdx.y,blockIdx.z,1,s_addr10,shared_rows[s_addr10]);
printf("copy rows: blockIdx.x=%d, blockIdx.y=%d,blockIdx.z=%d,shared_rows: z:%d, addr:%d, val = %f\n",blockIdx.x, blockIdx.y,blockIdx.z,1,s_addr11,shared_rows[s_addr11]);
printf("copy rows: blockIdx.x=%d, blockIdx.y=%d,blockIdx.z=%d,shared_rows: z:%d, addr:%d, val = %f\n",blockIdx.x, blockIdx.y,blockIdx.z,1,s_addr12,shared_rows[s_addr12]);
printf("copy rows: blockIdx.x=%d, blockIdx.y=%d,blockIdx.z=%d,shared_rows: z:%d, addr:%d, val = %f\n",blockIdx.x, blockIdx.y,blockIdx.z,2,s_addr20,shared_rows[s_addr20]);
printf("copy rows: blockIdx.x=%d, blockIdx.y=%d,blockIdx.z=%d,shared_rows: z:%d, addr:%d, val = %f\n",blockIdx.x, blockIdx.y,blockIdx.z,2,s_addr21,shared_rows[s_addr21]);
printf("copy rows: blockIdx.x=%d, blockIdx.y=%d,blockIdx.z=%d,shared_rows: z:%d, addr:%d, val = %f\n",blockIdx.x, blockIdx.y,blockIdx.z,2,s_addr22,shared_rows[s_addr22]);
}
if(threadIdx.x==0 && threadIdx.y==0){
int addr =  2*s_area+n_cols+256;
int addr1 = 2*dst_area+n_cols+256;
printf("copy rows: shared_rows: addr:%d, val:%f\n", addr, shared_rows[addr]);
printf("copy rows: dst        : addr:%d, val:%f\n", addr1, dst[addr1]);
}
}
#endif

#ifdef CUDA_DARTS_DEBUG

if((blockIdx.x==0)&&(blockIdx.y==0)&&(blockIdx.z==0)&&(threadIdx.x==0)){
printf("copy rows end!\n");
}
#endif
}
	.text
	.file	"gpu_stencil37_hack2_cp_rows.hip"
	.globl	_Z42__device_stub__gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii # -- Begin function _Z42__device_stub__gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii
	.type	_Z42__device_stub__gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii,@function
_Z42__device_stub__gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii: # @_Z42__device_stub__gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$224, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$240, %rsp
	.cfi_adjust_cfa_offset -240
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z42__device_stub__gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii, .Lfunc_end0-_Z42__device_stub__gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii,@object # @_Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii
	.p2align	3, 0x0
_Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii:
	.quad	_Z42__device_stub__gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii
	.size	_Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii"
	.size	.L__unnamed_1, 52

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z42__device_stub__gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii ; -- Begin function _Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii
	.globl	_Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii
	.p2align	8
	.type	_Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii,@function
_Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii: ; @_Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii
; %bb.0:
	s_load_b64 s[8:9], s[0:1], 0x48
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s9, 1
	s_cbranch_scc1 .LBB0_6
; %bb.1:                                ; %.lr.ph
	s_clause 0x5
	s_load_b32 s10, s[0:1], 0x2c
	s_load_b32 s12, s[0:1], 0x5c
	s_load_b64 s[16:17], s[0:1], 0x20
	s_load_b32 s19, s[0:1], 0x54
	s_load_b128 s[4:7], s[0:1], 0x38
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mul_i32 s20, s14, s8
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s7, s15, s9
	s_add_i32 s15, s20, 1
	s_ashr_i32 s11, s10, 31
	s_and_b32 s12, s12, 0xffff
	s_mul_i32 s21, s7, s17
	s_mul_i32 s8, s17, s16
	s_cmp_lt_i32 s15, s4
	s_mul_i32 s4, s13, s12
	s_mul_i32 s17, s7, s19
	v_add_nc_u32_e32 v1, s4, v0
	s_cselect_b32 s12, -1, 0
	s_add_i32 s14, s14, s17
	s_add_i32 s21, s21, s20
	s_mul_i32 s14, s10, s14
	s_mul_i32 s15, s16, s21
	v_cmp_le_i32_e32 vcc_lo, s5, v1
	s_lshl_b32 s5, s14, 1
	v_add3_u32 v1, s4, s15, v0
	v_add3_u32 v3, s4, s5, v0
	s_mov_b32 s18, s16
	s_mul_i32 s22, s19, s10
	s_ashr_i32 s19, s16, 31
	s_lshl_b32 s13, s22, 1
	s_lshl_b64 s[4:5], s[10:11], 3
	s_xor_b32 s14, vcc_lo, -1
	s_lshl_b64 s[10:11], s[18:19], 3
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_cmp_lt_i32 s7, s6
	s_cselect_b32 s15, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s16, s14, s15
	s_and_saveexec_b32 s15, s16
	s_cbranch_execz .LBB0_5
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 3, v[1:2]
	v_lshlrev_b64 v[7:8], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	global_load_b64 v[9:10], v[5:6], off
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_waitcnt vmcnt(0)
	global_store_b64 v[7:8], v[9:10], off
	s_cbranch_vccnz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_co_u32 v4, vcc_lo, v5, s10
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v6, vcc_lo
	v_add_co_u32 v6, vcc_lo, v7, s4
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v8, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	global_store_b64 v[6:7], v[4:5], off
.LBB0_5:                                ; %.critedge
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	v_add_nc_u32_e32 v1, s8, v1
	v_add_nc_u32_e32 v3, s13, v3
	s_add_i32 s9, s9, -1
	s_add_i32 s7, s7, 1
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc0 .LBB0_2
.LBB0_6:                                ; %._crit_edge
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 23
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii, .Lfunc_end0-_Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 400
; NumSgprs: 25
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 25
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         76
        .size:           4
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         84
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         92
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         94
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         96
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         98
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         100
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         102
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         144
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 336
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     25
    .sgpr_spill_count: 0
    .symbol:         _Z27gpu_stencil37_hack2_cp_rowsPdS_S_S_iiiiiiiiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
