#define NDISP 48

typedef unsigned char uchar;
using namespace std;

__global__ void path_aggregate(int width, int height, int D, int P1, int P2,
                              int dir, int* Espace, cudaTextureObject_t Cost,
                              short* texturePerp, short* textureParallel)
{
    __shared__ short L_p0[NDISP+2];
    __shared__ short L_c0[NDISP+2];
    __shared__ short delta0;

    short Tp = 0, T = 0, Tp2 = 0;
    float Kt = 0;
    int P1a, P2a; int Td;
    int dy, dx;

    int tid = threadIdx.x;
    int d = tid+1;

    //just one thread to prevent bank conflicts
    if(tid == 0)
        L_p0[0] = L_p0[NDISP+1] = L_c0[0] = L_c0[NDISP+1] = SHRT_MAX;

    if(tid < D)
        L_p0[d] = SHRT_MAX;

    if(tid == 0)
        delta0 = SHRT_MAX;

    int x = 0;
    int y = 0;

    //set initial coordinates of a block
    switch(dir)
    {
        case 0:
            x = 0; y = blockIdx.x; dy = 0; dx = 1;
            break;
        case 1:
            if(blockIdx.x < height)
            {    y = height-1-(blockIdx.x); x = 0; dy=1; dx=1;}
            else
            {    y = 0; x = (blockIdx.x)-height;}
            break;
        case 2:
            y = 0; x = blockIdx.x; dy = 1; dx = 0;
            break;
        case 3:
            if(blockIdx.x < width)
            {    x = blockIdx.x; y = 0; dy = 1; dx = -1;}
            else
            {    y = blockIdx.x-width; x = width-1; dy = 1; dx = -1;}
            break;
        case 4:
            x = width-1; y = blockIdx.x; dy = 0; dx= -1;
            break;
        case 5:
            if(blockIdx.x < height)
            {    x = width-1; y = blockIdx.x; dy=-1; dx = -1;}
            else
            {    y = height-1; x = blockIdx.x-height; dy=-1; dx = -1;}
            break;
        case 6:
            y = height-1; x = blockIdx.x; dy = -1; dx = 0;
            break;
        case 7:
            if(blockIdx.x < height)
            {    x = 0; y = blockIdx.x; dy = -1; dx = 1;}
            else
            {    x = blockIdx.x-height; y = height-1; dy = -1; dx = 1;}
            break;
    }
    __syncthreads();
    //main loop of a thread
    while(x >= 0 && y >= 0 && x < width && y < height)
    {
        //read texture and adjust penalties
        Kt = 1;//textureParallel[y*width+x]/500;
        T = texturePerp[y*width+x];
        Td = abs(T-Tp2);
        short C;
        short bestsad; short bestdisp;
        P1a = P1;
        P2a = P2;

        Tp2 = Tp;
        Tp = T;

        if(tid < D)
        {
            C = tex2D<short>(Cost, (d-1)*width+x, y);
            if(C < SHRT_MAX-5)
            {
                L_c0[d] = C + min((int)L_p0[d], min((int)L_p0[d-1]+P1a, min((int)L_p0[d+1]+P1a, (int)delta0))) - delta0;
                Espace[y*width*D + x*D + d-1] += (int)L_c0[d]*Kt;
                L_p0[d] = L_c0[d];
            }
            else
            {
                L_c0[d] = SHRT_MAX;
                Espace[y*width*D + x*D + d-1] += SHRT_MAX;
                L_p0[d] = L_c0[d];
            }

            __syncthreads();

            for(int i = blockDim.x, n = blockDim.x/2; n>0; n /= 2)
            {
                if((d-1) < n)
                {
                    L_c0[d] = min((int)L_c0[d], (int)L_c0[d+n]);
                }

                if(n*2 != i)
                {
                    L_c0[n+1] = L_c0[2*n+1];
                    n = n+1;
                }
                i = n;

                __syncthreads();
            }

            delta0 = L_c0[1] + P2a;
        }

        __syncthreads();
        x += dx; y += dy;
    }
}

/* BM_cost
 *
 * Calculates block matching cost for D disparity levels
 * between image1 and image2
 */
__global__ void BM_cost(cudaTextureObject_t image1, cudaTextureObject_t image2,
                        short* cost, int width, int height, int D)
{
    extern __shared__ short I[];

    int x = threadIdx.x;
    int y = blockIdx.x;

    I[x] = tex2D<uchar>(image2, x, y);

    __syncthreads();

    short i = tex2D<uchar>(image1, x, y);
    int r = y*width*D + x;

    for(int d=0; d<D; d++)
    {
        if(x >= d)
        {
            cost[r + d*width] = abs(i - I[x-d]);
        }
        else
            cost[r + d*width] = SHRT_MAX;
    }
}

__global__ void energy_minimalize(int *Energy, short* disparity, short* disparity2,
                                  int D, int width, int height)
{
    __shared__ int L[NDISP];    //storage for disparity values
    __shared__ int cL[NDISP];

    int d = threadIdx.x;
    int x = blockIdx.x;
    int y = blockIdx.y;
    float d_refined;

    //read energy for each disparity (one operation)
    L[d] = Energy[y*width*D + x*D + d];
    cL[d] = L[d];

    __syncthreads();
    //use reduction algorithm to minimalize energy

    for(int i = blockDim.x, n = blockDim.x/2; n>0; n /= 2)
    {
        if(d < n)
        {
            L[d] = min(L[d], L[d+n]);
        }

        if(n*2 != i)
        {
            L[n] = L[2*n];
            n = n+1;
        }
        i = n;

        __syncthreads();
    }

    if(cL[d] == L[0])
    {
        if(0 < d && d < D-1)
        {
            int denom2 = max((Energy[(y * width * D) + (x * D) + d - 1]
                              + Energy[(y * width * D) + (x * D) + d + 1]
                              - 2 * Energy[(y * width * D) + (x * D) + d]), 1);
            d_refined = 10 * ((float) d) + (float)((Energy[(y * width * D)
                        + (x * D) + d - 1] - Energy[(y * width * D)
                        + (x * D) + d + 1]) + denom2) / (denom2 * 2);
        }
        else
        {
            d_refined = 10*(float)d;
        }

        disparity[y*width+x] = d_refined;
        if(x-1-d >= 0)
            disparity2[y*width+x-1-d] = d_refined;

    }
    __syncthreads();
}

__global__ void validate(short* disparity, short* disparity2, int width, int height, int disp12maxdiff)
{
    int x = threadIdx.x;
    int y = blockIdx.x;

    int d0 = disparity[y*width + x];
    if(d0 != -1)
    {
        int x2 = x - d0;

        if(0 <= x2 && abs(disparity2[y*width + x2]-d0) > 10*disp12maxdiff)
        {
            disparity[y*width+x] = -1;
        }
    }
}

	.file	"tmpxft_0022ed14_00000000-6_sgm.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z46__device_stub__Z14path_aggregateiiiiiiPiyPsS0_iiiiiiPiyPsS0_
	.type	_Z46__device_stub__Z14path_aggregateiiiiiiPiyPsS0_iiiiiiPiyPsS0_, @function
_Z46__device_stub__Z14path_aggregateiiiiiiPiyPsS0_iiiiiiPiyPsS0_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	224(%rsp), %rax
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	240(%rsp), %rax
	movl	%edx, 36(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rax, 8(%rsp)
	movq	248(%rsp), %rax
	movl	%ecx, 32(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 28(%rsp)
	movl	%r9d, 24(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	%rsp, %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z14path_aggregateiiiiiiPiyPsS0_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 240
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L2:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z46__device_stub__Z14path_aggregateiiiiiiPiyPsS0_iiiiiiPiyPsS0_, .-_Z46__device_stub__Z14path_aggregateiiiiiiPiyPsS0_iiiiiiPiyPsS0_
	.globl	_Z14path_aggregateiiiiiiPiyPsS0_
	.type	_Z14path_aggregateiiiiiiPiyPsS0_, @function
_Z14path_aggregateiiiiiiPiyPsS0_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z14path_aggregateiiiiiiPiyPsS0_iiiiiiPiyPsS0_
	.cfi_endproc
.LFE2033:
	.size	_Z14path_aggregateiiiiiiPiyPsS0_, .-_Z14path_aggregateiiiiiiPiyPsS0_
	.globl	_Z31__device_stub__Z7BM_costyyPsiiiyyPsiii
	.type	_Z31__device_stub__Z7BM_costyyPsiiiyyPsiii, @function
_Z31__device_stub__Z7BM_costyyPsiiiyyPsiii:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z7BM_costyyPsiii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L8:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z31__device_stub__Z7BM_costyyPsiiiyyPsiii, .-_Z31__device_stub__Z7BM_costyyPsiiiyyPsiii
	.globl	_Z7BM_costyyPsiii
	.type	_Z7BM_costyyPsiii, @function
_Z7BM_costyyPsiii:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z7BM_costyyPsiiiyyPsiii
	.cfi_endproc
.LFE2035:
	.size	_Z7BM_costyyPsiii, .-_Z7BM_costyyPsiii
	.globl	_Z45__device_stub__Z17energy_minimalizePiPsS0_iiiPiPsS0_iii
	.type	_Z45__device_stub__Z17energy_minimalizePiPsS0_iiiPiPsS0_iii, @function
_Z45__device_stub__Z17energy_minimalizePiPsS0_iiiPiPsS0_iii:
.LFB2036:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z17energy_minimalizePiPsS0_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L13:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	_Z45__device_stub__Z17energy_minimalizePiPsS0_iiiPiPsS0_iii, .-_Z45__device_stub__Z17energy_minimalizePiPsS0_iiiPiPsS0_iii
	.globl	_Z17energy_minimalizePiPsS0_iii
	.type	_Z17energy_minimalizePiPsS0_iii, @function
_Z17energy_minimalizePiPsS0_iii:
.LFB2037:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z17energy_minimalizePiPsS0_iiiPiPsS0_iii
	.cfi_endproc
.LFE2037:
	.size	_Z17energy_minimalizePiPsS0_iii, .-_Z17energy_minimalizePiPsS0_iii
	.globl	_Z32__device_stub__Z8validatePsS_iiiPsS_iii
	.type	_Z32__device_stub__Z8validatePsS_iiiPsS_iii, @function
_Z32__device_stub__Z8validatePsS_iiiPsS_iii:
.LFB2038:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z8validatePsS_iii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L18:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2038:
	.size	_Z32__device_stub__Z8validatePsS_iiiPsS_iii, .-_Z32__device_stub__Z8validatePsS_iiiPsS_iii
	.globl	_Z8validatePsS_iii
	.type	_Z8validatePsS_iii, @function
_Z8validatePsS_iii:
.LFB2039:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z8validatePsS_iiiPsS_iii
	.cfi_endproc
.LFE2039:
	.size	_Z8validatePsS_iii, .-_Z8validatePsS_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z8validatePsS_iii"
.LC1:
	.string	"_Z17energy_minimalizePiPsS0_iii"
.LC2:
	.string	"_Z7BM_costyyPsiii"
.LC3:
	.string	"_Z14path_aggregateiiiiiiPiyPsS0_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2041:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z8validatePsS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z17energy_minimalizePiPsS0_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7BM_costyyPsiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z14path_aggregateiiiiiiPiyPsS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2041:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#define NDISP 48

typedef unsigned char uchar;
using namespace std;

__global__ void path_aggregate(int width, int height, int D, int P1, int P2,
                              int dir, int* Espace, hipTextureObject_t Cost,
                              short* texturePerp, short* textureParallel)
{
    __shared__ short L_p0[NDISP+2];
    __shared__ short L_c0[NDISP+2];
    __shared__ short delta0;

    short Tp = 0, T = 0, Tp2 = 0;
    float Kt = 0;
    int P1a, P2a; int Td;
    int dy, dx;

    int tid = threadIdx.x;
    int d = tid+1;

    //just one thread to prevent bank conflicts
    if(tid == 0)
        L_p0[0] = L_p0[NDISP+1] = L_c0[0] = L_c0[NDISP+1] = SHRT_MAX;

    if(tid < D)
        L_p0[d] = SHRT_MAX;

    if(tid == 0)
        delta0 = SHRT_MAX;

    int x = 0;
    int y = 0;

    //set initial coordinates of a block
    switch(dir)
    {
        case 0:
            x = 0; y = blockIdx.x; dy = 0; dx = 1;
            break;
        case 1:
            if(blockIdx.x < height)
            {    y = height-1-(blockIdx.x); x = 0; dy=1; dx=1;}
            else
            {    y = 0; x = (blockIdx.x)-height;}
            break;
        case 2:
            y = 0; x = blockIdx.x; dy = 1; dx = 0;
            break;
        case 3:
            if(blockIdx.x < width)
            {    x = blockIdx.x; y = 0; dy = 1; dx = -1;}
            else
            {    y = blockIdx.x-width; x = width-1; dy = 1; dx = -1;}
            break;
        case 4:
            x = width-1; y = blockIdx.x; dy = 0; dx= -1;
            break;
        case 5:
            if(blockIdx.x < height)
            {    x = width-1; y = blockIdx.x; dy=-1; dx = -1;}
            else
            {    y = height-1; x = blockIdx.x-height; dy=-1; dx = -1;}
            break;
        case 6:
            y = height-1; x = blockIdx.x; dy = -1; dx = 0;
            break;
        case 7:
            if(blockIdx.x < height)
            {    x = 0; y = blockIdx.x; dy = -1; dx = 1;}
            else
            {    x = blockIdx.x-height; y = height-1; dy = -1; dx = 1;}
            break;
    }
    __syncthreads();
    //main loop of a thread
    while(x >= 0 && y >= 0 && x < width && y < height)
    {
        //read texture and adjust penalties
        Kt = 1;//textureParallel[y*width+x]/500;
        T = texturePerp[y*width+x];
        Td = abs(T-Tp2);
        short C;
        short bestsad; short bestdisp;
        P1a = P1;
        P2a = P2;

        Tp2 = Tp;
        Tp = T;

        if(tid < D)
        {
            C = tex2D<short>(Cost, (d-1)*width+x, y);
            if(C < SHRT_MAX-5)
            {
                L_c0[d] = C + min((int)L_p0[d], min((int)L_p0[d-1]+P1a, min((int)L_p0[d+1]+P1a, (int)delta0))) - delta0;
                Espace[y*width*D + x*D + d-1] += (int)L_c0[d]*Kt;
                L_p0[d] = L_c0[d];
            }
            else
            {
                L_c0[d] = SHRT_MAX;
                Espace[y*width*D + x*D + d-1] += SHRT_MAX;
                L_p0[d] = L_c0[d];
            }

            __syncthreads();

            for(int i = blockDim.x, n = blockDim.x/2; n>0; n /= 2)
            {
                if((d-1) < n)
                {
                    L_c0[d] = min((int)L_c0[d], (int)L_c0[d+n]);
                }

                if(n*2 != i)
                {
                    L_c0[n+1] = L_c0[2*n+1];
                    n = n+1;
                }
                i = n;

                __syncthreads();
            }

            delta0 = L_c0[1] + P2a;
        }

        __syncthreads();
        x += dx; y += dy;
    }
}

/* BM_cost
 *
 * Calculates block matching cost for D disparity levels
 * between image1 and image2
 */
__global__ void BM_cost(hipTextureObject_t image1, hipTextureObject_t image2,
                        short* cost, int width, int height, int D)
{
    extern __shared__ short I[];

    int x = threadIdx.x;
    int y = blockIdx.x;

    I[x] = tex2D<uchar>(image2, x, y);

    __syncthreads();

    short i = tex2D<uchar>(image1, x, y);
    int r = y*width*D + x;

    for(int d=0; d<D; d++)
    {
        if(x >= d)
        {
            cost[r + d*width] = abs(i - I[x-d]);
        }
        else
            cost[r + d*width] = SHRT_MAX;
    }
}

__global__ void energy_minimalize(int *Energy, short* disparity, short* disparity2,
                                  int D, int width, int height)
{
    __shared__ int L[NDISP];    //storage for disparity values
    __shared__ int cL[NDISP];

    int d = threadIdx.x;
    int x = blockIdx.x;
    int y = blockIdx.y;
    float d_refined;

    //read energy for each disparity (one operation)
    L[d] = Energy[y*width*D + x*D + d];
    cL[d] = L[d];

    __syncthreads();
    //use reduction algorithm to minimalize energy

    for(int i = blockDim.x, n = blockDim.x/2; n>0; n /= 2)
    {
        if(d < n)
        {
            L[d] = min(L[d], L[d+n]);
        }

        if(n*2 != i)
        {
            L[n] = L[2*n];
            n = n+1;
        }
        i = n;

        __syncthreads();
    }

    if(cL[d] == L[0])
    {
        if(0 < d && d < D-1)
        {
            int denom2 = max((Energy[(y * width * D) + (x * D) + d - 1]
                              + Energy[(y * width * D) + (x * D) + d + 1]
                              - 2 * Energy[(y * width * D) + (x * D) + d]), 1);
            d_refined = 10 * ((float) d) + (float)((Energy[(y * width * D)
                        + (x * D) + d - 1] - Energy[(y * width * D)
                        + (x * D) + d + 1]) + denom2) / (denom2 * 2);
        }
        else
        {
            d_refined = 10*(float)d;
        }

        disparity[y*width+x] = d_refined;
        if(x-1-d >= 0)
            disparity2[y*width+x-1-d] = d_refined;

    }
    __syncthreads();
}

__global__ void validate(short* disparity, short* disparity2, int width, int height, int disp12maxdiff)
{
    int x = threadIdx.x;
    int y = blockIdx.x;

    int d0 = disparity[y*width + x];
    if(d0 != -1)
    {
        int x2 = x - d0;

        if(0 <= x2 && abs(disparity2[y*width + x2]-d0) > 10*disp12maxdiff)
        {
            disparity[y*width+x] = -1;
        }
    }
}

	.text
	.file	"sgm.hip"
	.globl	_Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_ # -- Begin function _Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_
	.type	_Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_,@function
_Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_: # @_Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_, .Lfunc_end0-_Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__BM_costP13__hip_textureS0_Psiii # -- Begin function _Z22__device_stub__BM_costP13__hip_textureS0_Psiii
	.type	_Z22__device_stub__BM_costP13__hip_textureS0_Psiii,@function
_Z22__device_stub__BM_costP13__hip_textureS0_Psiii: # @_Z22__device_stub__BM_costP13__hip_textureS0_Psiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7BM_costP13__hip_textureS0_Psiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z22__device_stub__BM_costP13__hip_textureS0_Psiii, .Lfunc_end1-_Z22__device_stub__BM_costP13__hip_textureS0_Psiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__energy_minimalizePiPsS0_iii # -- Begin function _Z32__device_stub__energy_minimalizePiPsS0_iii
	.type	_Z32__device_stub__energy_minimalizePiPsS0_iii,@function
_Z32__device_stub__energy_minimalizePiPsS0_iii: # @_Z32__device_stub__energy_minimalizePiPsS0_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17energy_minimalizePiPsS0_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z32__device_stub__energy_minimalizePiPsS0_iii, .Lfunc_end2-_Z32__device_stub__energy_minimalizePiPsS0_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__validatePsS_iii # -- Begin function _Z23__device_stub__validatePsS_iii
	.type	_Z23__device_stub__validatePsS_iii,@function
_Z23__device_stub__validatePsS_iii:     # @_Z23__device_stub__validatePsS_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8validatePsS_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z23__device_stub__validatePsS_iii, .Lfunc_end3-_Z23__device_stub__validatePsS_iii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7BM_costP13__hip_textureS0_Psiii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17energy_minimalizePiPsS0_iii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8validatePsS_iii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_,@object # @_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_
	.section	.rodata,"a",@progbits
	.globl	_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_
	.p2align	3, 0x0
_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_:
	.quad	_Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_
	.size	_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_, 8

	.type	_Z7BM_costP13__hip_textureS0_Psiii,@object # @_Z7BM_costP13__hip_textureS0_Psiii
	.globl	_Z7BM_costP13__hip_textureS0_Psiii
	.p2align	3, 0x0
_Z7BM_costP13__hip_textureS0_Psiii:
	.quad	_Z22__device_stub__BM_costP13__hip_textureS0_Psiii
	.size	_Z7BM_costP13__hip_textureS0_Psiii, 8

	.type	_Z17energy_minimalizePiPsS0_iii,@object # @_Z17energy_minimalizePiPsS0_iii
	.globl	_Z17energy_minimalizePiPsS0_iii
	.p2align	3, 0x0
_Z17energy_minimalizePiPsS0_iii:
	.quad	_Z32__device_stub__energy_minimalizePiPsS0_iii
	.size	_Z17energy_minimalizePiPsS0_iii, 8

	.type	_Z8validatePsS_iii,@object      # @_Z8validatePsS_iii
	.globl	_Z8validatePsS_iii
	.p2align	3, 0x0
_Z8validatePsS_iii:
	.quad	_Z23__device_stub__validatePsS_iii
	.size	_Z8validatePsS_iii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_"
	.size	.L__unnamed_1, 48

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z7BM_costP13__hip_textureS0_Psiii"
	.size	.L__unnamed_2, 35

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z17energy_minimalizePiPsS0_iii"
	.size	.L__unnamed_3, 32

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z8validatePsS_iii"
	.size	.L__unnamed_4, 19

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_
	.addrsig_sym _Z22__device_stub__BM_costP13__hip_textureS0_Psiii
	.addrsig_sym _Z32__device_stub__energy_minimalizePiPsS0_iii
	.addrsig_sym _Z23__device_stub__validatePsS_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_
	.addrsig_sym _Z7BM_costP13__hip_textureS0_Psiii
	.addrsig_sym _Z17energy_minimalizePiPsS0_iii
	.addrsig_sym _Z8validatePsS_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_ ; -- Begin function _Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_
	.globl	_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_
	.p2align	8
	.type	_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_,@function
_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_: ; @_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_
; %bb.0:
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0x7fff
	ds_store_b16 v1, v2 offset:98
	ds_store_b16 v1, v2
	ds_store_b16 v1, v2 offset:210
	ds_store_b16 v1, v2 offset:112
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s2
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[12:13], s[0:1], 0x10
	v_lshlrev_b32_e32 v1, 1, v0
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e64 s2, s6, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_4
; %bb.3:
	v_mov_b32_e32 v2, 0x7fff
	ds_store_b16 v1, v2 offset:114
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_6
; %bb.5:
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0x7fff
	ds_store_b16 v2, v3 offset:100
.LBB0_6:
	s_or_b32 exec_lo, exec_lo, s3
	s_cmp_lt_i32 s13, 4
	s_cbranch_scc1 .LBB0_11
; %bb.7:                                ; %NodeBlock170
	s_cmp_lt_i32 s13, 6
	s_cbranch_scc1 .LBB0_12
; %bb.8:                                ; %NodeBlock168
	s_cmp_lt_i32 s13, 7
	s_cbranch_scc1 .LBB0_13
; %bb.9:                                ; %LeafBlock166
	s_mov_b32 s8, 0
	s_cmp_eq_u32 s13, 7
	s_mov_b32 s3, 0
	s_mov_b32 s16, 0
                                        ; implicit-def: $sgpr17
                                        ; implicit-def: $sgpr18
	s_cbranch_scc0 .LBB0_14
; %bb.10:
	v_sub_nc_u32_e64 v2, s15, s5 clamp
	s_add_i32 s3, s5, -1
	s_cmp_lt_u32 s15, s5
	s_mov_b32 s17, -1
	s_cselect_b32 s3, s15, s3
	v_readfirstlane_b32 s16, v2
	s_mov_b32 s18, 1
	s_branch .LBB0_14
.LBB0_11:
	s_mov_b32 s8, -1
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $sgpr16
                                        ; implicit-def: $sgpr17
                                        ; implicit-def: $sgpr18
	s_branch .LBB0_29
.LBB0_12:
	s_mov_b32 s8, -1
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $sgpr16
                                        ; implicit-def: $sgpr17
                                        ; implicit-def: $sgpr18
	s_branch .LBB0_17
.LBB0_13:
	s_mov_b32 s8, -1
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $sgpr16
                                        ; implicit-def: $sgpr17
                                        ; implicit-def: $sgpr18
.LBB0_14:                               ; %Flow180
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s8
	s_cbranch_vccnz .LBB0_16
; %bb.15:
	s_mov_b32 s17, -1
	s_add_i32 s3, s5, -1
	s_mov_b32 s18, 0
	s_mov_b32 s16, s15
.LBB0_16:                               ; %Flow181
	s_mov_b32 s8, 0
.LBB0_17:                               ; %Flow186
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s8
	s_cbranch_vccnz .LBB0_28
; %bb.18:                               ; %NodeBlock164
	s_cmp_gt_i32 s13, 4
	s_cbranch_scc0 .LBB0_21
; %bb.19:
	s_cmp_ge_u32 s15, s5
	s_cbranch_scc0 .LBB0_22
; %bb.20:
	s_mov_b32 s17, -1
	s_add_i32 s3, s5, -1
	s_sub_i32 s16, s15, s5
	s_mov_b32 s8, 0
	s_branch .LBB0_23
.LBB0_21:
	s_mov_b32 s8, -1
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $sgpr16
                                        ; implicit-def: $sgpr17
	s_branch .LBB0_26
.LBB0_22:
	s_mov_b32 s8, -1
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $sgpr16
                                        ; implicit-def: $sgpr17
.LBB0_23:                               ; %Flow182
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s8
	s_cbranch_vccnz .LBB0_25
; %bb.24:
	s_mov_b32 s17, -1
	s_add_i32 s16, s4, -1
	s_mov_b32 s3, s15
.LBB0_25:                               ; %Flow183
	s_mov_b32 s8, 0
.LBB0_26:                               ; %Flow184
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s8
	s_mov_b32 s18, s17
	s_cbranch_vccnz .LBB0_28
; %bb.27:
	s_mov_b32 s18, -1
	s_add_i32 s16, s4, -1
	s_mov_b32 s17, 0
	s_mov_b32 s3, s15
.LBB0_28:                               ; %Flow187
	s_mov_b32 s8, 0
.LBB0_29:                               ; %Flow197
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s8
	s_cbranch_vccnz .LBB0_50
; %bb.30:                               ; %NodeBlock162
	s_cmp_lt_i32 s13, 2
	s_cbranch_scc1 .LBB0_33
; %bb.31:                               ; %NodeBlock160
	s_cmp_gt_i32 s13, 2
	s_cbranch_scc0 .LBB0_34
; %bb.32:
	v_sub_nc_u32_e64 v2, s15, s4 clamp
	s_add_i32 s8, s4, -1
	s_cmp_lt_u32 s15, s4
	s_mov_b32 s18, -1
	s_cselect_b32 s16, s15, s8
	v_readfirstlane_b32 s3, v2
	s_mov_b32 s8, 0
	s_mov_b32 s17, 1
	s_branch .LBB0_35
.LBB0_33:
	s_mov_b32 s8, -1
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $sgpr16
                                        ; implicit-def: $sgpr17
                                        ; implicit-def: $sgpr18
	s_branch .LBB0_38
.LBB0_34:
	s_mov_b32 s8, -1
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $sgpr16
                                        ; implicit-def: $sgpr17
                                        ; implicit-def: $sgpr18
.LBB0_35:                               ; %Flow188
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s8
	s_cbranch_vccnz .LBB0_37
; %bb.36:
	s_mov_b32 s3, 0
	s_mov_b32 s16, s15
	s_mov_b32 s17, 1
	s_mov_b32 s18, 0
.LBB0_37:                               ; %Flow189
	s_mov_b32 s8, 0
.LBB0_38:                               ; %Flow195
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s8
	s_cbranch_vccnz .LBB0_50
; %bb.39:                               ; %NodeBlock
	s_cmp_gt_i32 s13, 0
	s_cbranch_scc0 .LBB0_42
; %bb.40:
	s_cmp_ge_u32 s15, s5
	s_cbranch_scc0 .LBB0_43
; %bb.41:
	s_sub_i32 s16, s15, s5
	s_mov_b32 s8, 0
	s_mov_b32 s3, 0
	s_branch .LBB0_44
.LBB0_42:
	s_mov_b32 s8, -1
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $sgpr16
                                        ; implicit-def: $sgpr17
                                        ; implicit-def: $sgpr18
	s_branch .LBB0_47
.LBB0_43:
	s_mov_b32 s8, -1
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $sgpr16
.LBB0_44:                               ; %Flow190
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s8
	s_mov_b32 s17, 1
	s_cbranch_vccnz .LBB0_46
; %bb.45:
	s_not_b32 s3, s15
	s_mov_b32 s16, 0
	s_add_i32 s3, s3, s5
.LBB0_46:                               ; %Flow191
	s_mov_b32 s8, 0
	s_mov_b32 s18, s17
.LBB0_47:                               ; %Flow193
	s_and_not1_b32 vcc_lo, exec_lo, s8
	s_cbranch_vccnz .LBB0_50
; %bb.48:                               ; %LeafBlock
	s_mov_b32 s16, 0
	s_cmp_lg_u32 s13, 0
	s_mov_b32 s3, 0
                                        ; implicit-def: $sgpr17
                                        ; implicit-def: $sgpr18
	s_cbranch_scc1 .LBB0_50
; %bb.49:
	s_mov_b32 s18, 1
	s_mov_b32 s17, 0
	s_mov_b32 s3, s15
.LBB0_50:
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s8, s16, s3
	s_waitcnt lgkmcnt(0)
	s_cmp_gt_i32 s8, -1
	s_barrier
	s_cselect_b32 s8, -1, 0
	s_cmp_lt_i32 s16, s4
	buffer_gl0_inv
	s_cselect_b32 s9, -1, 0
	s_cmp_lt_i32 s3, s5
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s9, s9, s10
	s_and_b32 s8, s9, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s8
	s_cbranch_vccnz .LBB0_65
; %bb.51:                               ; %.lr.ph130
	s_load_b128 s[8:11], s[0:1], 0x18
	v_mul_lo_u32 v2, v0, s4
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, 2, v1
	v_add_nc_u32_e32 v1, 0x70, v1
	v_mov_b32_e32 v5, 0x7fff
	s_add_u32 s14, s0, 56
	s_addc_u32 s15, s1, 0
	s_and_b32 s1, s12, 0xffff
.LBB0_52:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_58 Depth 2
	s_and_saveexec_b32 s12, s2
	s_cbranch_execz .LBB0_64
; %bb.53:                               ;   in Loop: Header=BB0_52 Depth=1
	s_waitcnt lgkmcnt(0)
	s_clause 0x2
	s_load_b128 s[28:31], s[10:11], 0x30
	s_load_b256 s[20:27], s[10:11], 0x0
	s_load_b32 s19, s[10:11], 0x28
	s_mul_i32 s13, s3, s4
	v_cvt_f32_i32_e32 v6, s3
	s_add_i32 s13, s13, s16
	s_waitcnt lgkmcnt(0)
	s_bitcmp0_b32 s30, 20
	v_cvt_f32_u32_e32 v8, s19
	s_cselect_b32 vcc_lo, -1, 0
	s_bitcmp0_b32 s28, 15
                                        ; implicit-def: $sgpr19
	s_cselect_b32 s0, -1, 0
	s_bfe_u32 s33, s22, 0xe000e
	v_cndmask_b32_e64 v8, 1.0, v8, s0
	s_add_i32 s33, s33, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v7, s33
	v_rcp_f32_e32 v11, v8
	v_add_nc_u32_e32 v9, s16, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v7, 1.0, v7, s0
	s_mov_b32 s0, exec_lo
	v_cvt_f32_i32_e32 v9, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v10, v7
	v_dual_mul_f32 v7, v7, v6 :: v_dual_mul_f32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_floor_f32_e32 v7, v7
	v_floor_f32_e32 v8, v8
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v8, v11, v8 :: v_dual_mul_f32 v7, v10, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_cndmask_b32 v7, v6, v7 :: v_dual_cndmask_b32 v6, v9, v8
	image_sample_lz v6, v[6:7], s[20:27], s[28:31] dmask:0x1 dim:SQ_RSRC_IMG_2D
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i16_e32 0x7ff9, v6
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_55
; %bb.54:                               ;   in Loop: Header=BB0_52 Depth=1
	v_mad_u64_u32 v[6:7], null, s13, s6, v[0:1]
	s_movk_i32 s19, 0x7fff
	ds_store_b16 v3, v5
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_u32 v6, vcc_lo, s8, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
	global_load_b32 v8, v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v8, 0x7fff, v8
	global_store_b32 v[6:7], v8, off
                                        ; implicit-def: $vgpr6
.LBB0_55:                               ; %Flow175
                                        ;   in Loop: Header=BB0_52 Depth=1
	s_or_saveexec_b32 s0, s0
	v_mov_b32_e32 v7, s19
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_57
; %bb.56:                               ;   in Loop: Header=BB0_52 Depth=1
	v_mad_u64_u32 v[7:8], null, s13, s6, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s8, v7
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v8, vcc_lo
	global_load_b32 v8, v[9:10], off
	ds_load_i16 v7, v1 offset:4
	ds_load_u16 v11, v4 offset:100
	ds_load_i16 v12, v1
	ds_load_i16 v13, v1 offset:2
	s_waitcnt lgkmcnt(2)
	v_bfe_i32 v14, v11, 0, 16
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v12, s7, v12
	v_sub_nc_u16 v6, v6, v11
	s_waitcnt vmcnt(0)
	v_cvt_f32_i32_e32 v8, v8
	v_add_nc_u32_e32 v7, s7, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_min_i32_e32 v7, v7, v14
	s_waitcnt lgkmcnt(0)
	v_min3_i32 v7, v13, v12, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u16 v7, v6, v7
	v_bfe_i32 v6, v7, 0, 16
	ds_store_b16 v3, v7
	v_cvt_f32_i32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v8, v6
	v_cvt_i32_f32_e32 v6, v6
	global_store_b32 v[9:10], v6, off
.LBB0_57:                               ;   in Loop: Header=BB0_52 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	ds_store_b16 v1, v7 offset:2
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_load_b32 s0, s[14:15], 0xc
	s_waitcnt lgkmcnt(0)
	s_and_b32 s13, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_u32 s13, 2
	s_cbranch_scc1 .LBB0_63
.LBB0_58:                               ; %.lr.ph
                                        ;   Parent Loop BB0_52 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_lshr_b32 s0, s13, 1
	s_mov_b32 s19, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB0_60
; %bb.59:                               ;   in Loop: Header=BB0_58 Depth=2
	v_lshl_add_u32 v6, s0, 1, v3
	ds_load_u16 v7, v3
	ds_load_u16 v6, v6
	s_waitcnt lgkmcnt(0)
	v_min_i16 v6, v7, v6
	ds_store_b16 v3, v6
.LBB0_60:                               ;   in Loop: Header=BB0_58 Depth=2
	s_or_b32 exec_lo, exec_lo, s19
	s_bitcmp0_b32 s13, 0
	s_cbranch_scc1 .LBB0_62
; %bb.61:                               ;   in Loop: Header=BB0_58 Depth=2
	s_lshl_b32 s13, s13, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s13
	s_lshl_b32 s13, s0, 1
	s_add_i32 s0, s0, 1
	v_mov_b32_e32 v7, s13
	ds_load_u16 v6, v6
	s_waitcnt lgkmcnt(0)
	ds_store_b16 v7, v6 offset:2
.LBB0_62:                               ;   in Loop: Header=BB0_58 Depth=2
	s_cmp_lt_u32 s0, 2
	s_mov_b32 s13, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_58
.LBB0_63:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_52 Depth=1
	ds_load_u16 v6, v4 offset:2
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, s1, v6
	ds_store_b16 v4, v6 offset:100
.LBB0_64:                               ; %Flow176
                                        ;   in Loop: Header=BB0_52 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_add_i32 s16, s16, s18
	s_add_i32 s3, s3, s17
	s_waitcnt lgkmcnt(0)
	s_or_b32 s0, s16, s3
	s_barrier
	s_cmp_gt_i32 s0, -1
	buffer_gl0_inv
	s_cselect_b32 s0, -1, 0
	s_cmp_lt_i32 s16, s4
	s_cselect_b32 s12, -1, 0
	s_cmp_lt_i32 s3, s5
	s_cselect_b32 s13, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s12, s12, s13
	s_and_b32 s0, s12, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_52
.LBB0_65:                               ; %.critedge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_
		.amdhsa_group_segment_fixed_size 212
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 34
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_, .Lfunc_end0-_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1604
; NumSgprs: 36
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 212 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 36
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7BM_costP13__hip_textureS0_Psiii ; -- Begin function _Z7BM_costP13__hip_textureS0_Psiii
	.globl	_Z7BM_costP13__hip_textureS0_Psiii
	.p2align	8
	.type	_Z7BM_costP13__hip_textureS0_Psiii,@function
_Z7BM_costP13__hip_textureS0_Psiii:     ; @_Z7BM_costP13__hip_textureS0_Psiii
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x20
	v_cvt_f32_i32_e32 v1, s15
	s_waitcnt lgkmcnt(0)
	s_clause 0x2
	s_load_b128 s[8:11], s[6:7], 0x30
	s_load_b256 s[16:23], s[6:7], 0x0
	s_load_b32 s6, s[6:7], 0x28
	s_waitcnt lgkmcnt(0)
	s_bitcmp0_b32 s10, 20
	s_cselect_b32 vcc_lo, -1, 0
	s_bitcmp0_b32 s8, 15
	v_cvt_f32_u32_e32 v3, s6
	s_cselect_b32 s2, -1, 0
	s_bfe_u32 s7, s18, 0xe000e
	s_mov_b32 s6, 0
	s_add_i32 s7, s7, 1
	v_cndmask_b32_e64 v3, 1.0, v3, s2
	v_cvt_f32_u32_e32 v2, s7
	s_cmp_lt_i32 s3, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v6, v3
	v_cndmask_b32_e64 v4, 1.0, v2, s2
	v_cvt_f32_i32_e32 v2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v5, v4
	v_dual_mul_f32 v4, v4, v1 :: v_dual_mul_f32 v3, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_floor_f32_e32 v4, v4
	v_floor_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v4, v5, v4 :: v_dual_mul_f32 v3, v6, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_cndmask_b32 v4, v1, v4 :: v_dual_cndmask_b32 v3, v2, v3
	image_sample_lz v4, v[3:4], s[16:23], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
	v_lshl_add_u32 v3, v0, 1, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, 0xff, v4
	ds_store_b16 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_5
; %bb.1:                                ; %.lr.ph
	s_clause 0x2
	s_load_b128 s[8:11], s[4:5], 0x30
	s_load_b32 s2, s[4:5], 0x28
	s_load_b256 s[16:23], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_bitcmp0_b32 s10, 20
	v_cvt_f32_u32_e32 v4, s2
	s_cselect_b32 vcc_lo, -1, 0
	s_bitcmp0_b32 s8, 15
	s_cselect_b32 s2, -1, 0
	s_bfe_u32 s4, s18, 0xe000e
	v_cndmask_b32_e64 v4, 1.0, v4, s2
	s_add_i32 s4, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v5, s4
	v_rcp_f32_e32 v6, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v5, 1.0, v5, s2
	v_mul_f32_e32 v4, v4, v2
	v_rcp_f32_e32 v7, v5
	v_mul_f32_e32 v5, v5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_floor_f32_e32 v4, v4
	v_floor_f32_e32 v5, v5
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v4, v6, v4 :: v_dual_mul_f32 v5, v7, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_cndmask_b32 v4, v2, v4 :: v_dual_cndmask_b32 v5, v1, v5
	image_sample_lz v4, v[4:5], s[16:23], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x18
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s15, s15, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, 0xff, v4
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v5, 0x7fff
	s_mov_b32 s4, exec_lo
	v_cmpx_le_u32_e64 s6, v0
	s_cbranch_execz .LBB1_4
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	ds_load_i16 v2, v3
	s_waitcnt lgkmcnt(0)
	v_sub_nc_u32_e32 v2, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, 0, v2
	v_max_i32_e32 v5, v2, v5
.LBB1_4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	v_ashrrev_i32_e32 v2, 31, v1
	v_add_nc_u32_e32 v3, -2, v3
	s_add_i32 s6, s6, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_eq_u32 s3, s6
	v_lshlrev_b64 v[6:7], 1, v[1:2]
	v_add_nc_u32_e32 v1, s2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s0, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
	global_store_b16 v[6:7], v5, off
	s_cbranch_scc0 .LBB1_2
.LBB1_5:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7BM_costP13__hip_textureS0_Psiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 36
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z7BM_costP13__hip_textureS0_Psiii, .Lfunc_end1-_Z7BM_costP13__hip_textureS0_Psiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 572
; NumSgprs: 26
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z17energy_minimalizePiPsS0_iii ; -- Begin function _Z17energy_minimalizePiPsS0_iii
	.globl	_Z17energy_minimalizePiPsS0_iii
	.p2align	8
	.type	_Z17energy_minimalizePiPsS0_iii,@function
_Z17energy_minimalizePiPsS0_iii:        ; @_Z17energy_minimalizePiPsS0_iii
; %bb.0:
	s_clause 0x2
	s_load_b64 s[8:9], s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x34
	v_lshlrev_b32_e32 v3, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v4, 0xc0, v3
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s15, s9
	s_add_i32 s2, s2, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s2, s8, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	s_and_b32 s4, s3, 0xffff
	s_cmp_lt_u32 s4, 2
	global_load_b32 v5, v[1:2], off
	s_waitcnt vmcnt(0)
	ds_store_2addr_b32 v3, v5, v5 offset1:48
	s_waitcnt lgkmcnt(0)
	s_barrier
.LBB2_1:                                ; =>This Inner Loop Header: Depth=1
	buffer_gl0_inv
	s_cbranch_scc1 .LBB2_7
; %bb.2:                                ; %.lr.ph
                                        ;   in Loop: Header=BB2_1 Depth=1
	s_lshr_b32 s3, s4, 1
	s_mov_b32 s5, exec_lo
	v_cmpx_gt_u32_e64 s3, v0
	s_cbranch_execz .LBB2_4
; %bb.3:                                ;   in Loop: Header=BB2_1 Depth=1
	v_lshl_add_u32 v5, s3, 2, v3
	ds_load_b32 v6, v3
	ds_load_b32 v5, v5
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v5, v6, v5
	ds_store_b32 v3, v5
.LBB2_4:                                ;   in Loop: Header=BB2_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_and_b32 s5, s4, -2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s5, s4
	s_cbranch_scc1 .LBB2_6
; %bb.5:                                ;   in Loop: Header=BB2_1 Depth=1
	s_lshl_b32 s4, s5, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s4
	s_lshl_b32 s4, s3, 2
	s_add_i32 s3, s3, 1
	v_mov_b32_e32 v6, s4
	ds_load_b32 v5, v5
	s_waitcnt lgkmcnt(0)
	ds_store_b32 v6, v5
.LBB2_6:                                ;   in Loop: Header=BB2_1 Depth=1
	s_waitcnt lgkmcnt(0)
	s_barrier
	s_cmp_lt_u32 s3, 2
	s_mov_b32 s4, s3
	s_branch .LBB2_1
.LBB2_7:                                ; %._crit_edge
	v_mov_b32_e32 v3, 0
	s_mov_b32 s9, exec_lo
	ds_load_b32 v4, v4
	ds_load_b32 v3, v3
	s_waitcnt lgkmcnt(0)
	v_cmpx_eq_u32_e64 v4, v3
	s_cbranch_execz .LBB2_14
; %bb.8:
	s_load_b64 s[4:5], s[0:1], 0x10
	s_add_i32 s0, s8, -1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	v_cmp_le_i32_e64 s0, s0, v0
	v_cvt_f32_i32_e32 v3, v0
                                        ; implicit-def: $vgpr4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s1
; %bb.9:
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v4, 0x41200000, v3
                                        ; implicit-def: $vgpr1_vgpr2
                                        ; implicit-def: $vgpr3
; %bb.10:                               ; %Flow110
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB2_12
; %bb.11:
	global_load_b96 v[4:6], v[1:2], off offset:-4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v1, v6, v4
	v_lshlrev_b32_e32 v2, 1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v1, v1, v2
	v_sub_nc_u32_e32 v2, v4, v6
	v_max_i32_e32 v1, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v2, v1
	v_lshlrev_b32_e32 v1, 1, v1
	v_cvt_f32_i32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v1, v1
	v_div_scale_f32 v4, null, v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v4, v5, 1.0
	v_fmac_f32_e32 v5, v6, v5
	v_div_scale_f32 v6, vcc_lo, v2, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, v6, v5
	v_fma_f32 v8, -v4, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v8, v5
	v_fma_f32 v4, -v4, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v4, v4, v5, v7
	v_div_fixup_f32 v1, v4, v1, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v4, v3, 0x41200000, v1
.LBB2_12:
	s_or_b32 exec_lo, exec_lo, s0
	v_subrev_nc_u32_e32 v2, s14, v0
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(VALU_DEP_2)
	v_cvt_i32_f32_e32 v1, v4
	s_lshl_b64 s[0:1], s[2:3], 1
	v_mov_b32_e32 v3, 0
	v_cmp_gt_i32_e32 vcc_lo, 0, v2
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b16 v3, v1, s[0:1]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_14
; %bb.13:
	v_xad_u32 v2, v0, -1, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 1, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_store_b16 v[2:3], v1, off
.LBB2_14:                               ; %Flow111
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17energy_minimalizePiPsS0_iii
		.amdhsa_group_segment_fixed_size 384
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z17energy_minimalizePiPsS0_iii, .Lfunc_end2-_Z17energy_minimalizePiPsS0_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 704
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 384 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8validatePsS_iii      ; -- Begin function _Z8validatePsS_iii
	.globl	_Z8validatePsS_iii
	.p2align	8
	.type	_Z8validatePsS_iii,@function
_Z8validatePsS_iii:                     ; @_Z8validatePsS_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s15, s15, s2
	s_mov_b32 s2, exec_lo
	v_add_nc_u32_e32 v1, s15, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 1, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_load_u16 v3, v[1:2], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u16_e32 -1, v3
	s_cbranch_execz .LBB3_4
; %bb.1:
	v_bfe_i32 v3, v3, 0, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v3
	v_cmp_lt_i32_e32 vcc_lo, -1, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_4
; %bb.2:
	v_add_nc_u32_e32 v4, s15, v0
	s_load_b32 s0, s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 1, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, 10
	global_load_i16 v0, v[4:5], off
	s_waitcnt vmcnt(0)
	v_sub_nc_u32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, 0, v0
	v_max_i32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, s0, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_4
; %bb.3:
	v_mov_b32_e32 v0, -1
	global_store_b16 v[1:2], v0, off
.LBB3_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8validatePsS_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 28
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z8validatePsS_iii, .Lfunc_end3-_Z8validatePsS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 236
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 212
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_
    .private_segment_fixed_size: 0
    .sgpr_count:     36
    .sgpr_spill_count: 0
    .symbol:         _Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 36
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7BM_costP13__hip_textureS0_Psiii
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z7BM_costP13__hip_textureS0_Psiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 384
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17energy_minimalizePiPsS0_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z17energy_minimalizePiPsS0_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 28
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8validatePsS_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8validatePsS_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
