struct VMState {
  int a;
  float *b;
};

static const int kOpsPerThread = 1;

__device__ void a0(const VMState& vm) { vm.b[vm.a] = 0.; }
__device__ void a1(const VMState& vm) { vm.b[vm.a] = 1.; }
__device__ void a2(const VMState& vm) { vm.b[vm.a] = 2.; }
__device__ void a3(const VMState& vm) { vm.b[vm.a] = 3.; }
__device__ void a4(const VMState& vm) { vm.b[vm.a] = 4.; }
__device__ void a5(const VMState& vm) { vm.b[vm.a] = 5.; }
__device__ void a6(const VMState& vm) { vm.b[vm.a] = 6.; }

typedef void (*Fn)(const VMState&);

__device__ static Fn table[7] = { &a0, &a1, &a2, &a3, &a4, &a5, &a6 };
__global__ void c(float *out) {
  const int block_size = blockDim.y * blockDim.x;
  const int offset = (blockIdx.y * gridDim.x + blockIdx.x) * block_size * kOpsPerThread;

  int registers[8];
  // for (int i = 0; i < kOpsPerThread; ++i) {
  // }

  registers[threadIdx.x] = 0;

  VMState vm;
  vm.b = out;
  for (int i = 0; i < kOpsPerThread; ++i) {
    vm.a = offset + (i * block_size) + threadIdx.x + registers[threadIdx.x];
    // vm.a = offset + threadIdx.x * kOpsPerThread + i;
    table[threadIdx.x % 7](vm);
  }

}

	.file	"tmpxft_00249942_00000000-6_test_fptr.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2017:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2017:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z2a0RK7VMState.constprop.0, @function
_Z2a0RK7VMState.constprop.0:
.LFB2170:
	.cfi_startproc
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2170:
	.size	_Z2a0RK7VMState.constprop.0, .-_Z2a0RK7VMState.constprop.0
	.globl	_Z2a0RK7VMState
	.type	_Z2a0RK7VMState, @function
_Z2a0RK7VMState:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z2a0RK7VMState, .-_Z2a0RK7VMState
	.globl	_Z2a1RK7VMState
	.type	_Z2a1RK7VMState, @function
_Z2a1RK7VMState:
.LFB2159:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z2a0RK7VMState.constprop.0
	.cfi_endproc
.LFE2159:
	.size	_Z2a1RK7VMState, .-_Z2a1RK7VMState
	.globl	_Z2a2RK7VMState
	.type	_Z2a2RK7VMState, @function
_Z2a2RK7VMState:
.LFB2161:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z2a0RK7VMState.constprop.0
	.cfi_endproc
.LFE2161:
	.size	_Z2a2RK7VMState, .-_Z2a2RK7VMState
	.globl	_Z2a3RK7VMState
	.type	_Z2a3RK7VMState, @function
_Z2a3RK7VMState:
.LFB2163:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z2a0RK7VMState.constprop.0
	.cfi_endproc
.LFE2163:
	.size	_Z2a3RK7VMState, .-_Z2a3RK7VMState
	.globl	_Z2a4RK7VMState
	.type	_Z2a4RK7VMState, @function
_Z2a4RK7VMState:
.LFB2165:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z2a0RK7VMState.constprop.0
	.cfi_endproc
.LFE2165:
	.size	_Z2a4RK7VMState, .-_Z2a4RK7VMState
	.globl	_Z2a5RK7VMState
	.type	_Z2a5RK7VMState, @function
_Z2a5RK7VMState:
.LFB2167:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z2a0RK7VMState.constprop.0
	.cfi_endproc
.LFE2167:
	.size	_Z2a5RK7VMState, .-_Z2a5RK7VMState
	.globl	_Z2a6RK7VMState
	.type	_Z2a6RK7VMState, @function
_Z2a6RK7VMState:
.LFB2169:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z2a0RK7VMState.constprop.0
	.cfi_endproc
.LFE2169:
	.size	_Z2a6RK7VMState, .-_Z2a6RK7VMState
	.globl	_Z20__device_stub__Z1cPfPf
	.type	_Z20__device_stub__Z1cPfPf, @function
_Z20__device_stub__Z1cPfPf:
.LFB2039:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z1cPf(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L18:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2039:
	.size	_Z20__device_stub__Z1cPfPf, .-_Z20__device_stub__Z1cPfPf
	.globl	_Z1cPf
	.type	_Z1cPf, @function
_Z1cPf:
.LFB2040:
	.cfi_startproc
	endbr64
	jmp	_Z20__device_stub__Z1cPfPf
	.cfi_endproc
.LFE2040:
	.size	_Z1cPf, .-_Z1cPf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z1cPf"
.LC1:
	.string	"table"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2042:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z1cPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movl	$56, %r9d
	leaq	_ZL5table(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2042:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL5table
	.comm	_ZL5table,56,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
struct VMState {
  int a;
  float *b;
};

static const int kOpsPerThread = 1;

__device__ void a0(const VMState& vm) { vm.b[vm.a] = 0.; }
__device__ void a1(const VMState& vm) { vm.b[vm.a] = 1.; }
__device__ void a2(const VMState& vm) { vm.b[vm.a] = 2.; }
__device__ void a3(const VMState& vm) { vm.b[vm.a] = 3.; }
__device__ void a4(const VMState& vm) { vm.b[vm.a] = 4.; }
__device__ void a5(const VMState& vm) { vm.b[vm.a] = 5.; }
__device__ void a6(const VMState& vm) { vm.b[vm.a] = 6.; }

typedef void (*Fn)(const VMState&);

__device__ static Fn table[7] = { &a0, &a1, &a2, &a3, &a4, &a5, &a6 };
__global__ void c(float *out) {
  const int block_size = blockDim.y * blockDim.x;
  const int offset = (blockIdx.y * gridDim.x + blockIdx.x) * block_size * kOpsPerThread;

  int registers[8];
  // for (int i = 0; i < kOpsPerThread; ++i) {
  // }

  registers[threadIdx.x] = 0;

  VMState vm;
  vm.b = out;
  for (int i = 0; i < kOpsPerThread; ++i) {
    vm.a = offset + (i * block_size) + threadIdx.x + registers[threadIdx.x];
    // vm.a = offset + threadIdx.x * kOpsPerThread + i;
    table[threadIdx.x % 7](vm);
  }

}

	.text
	.file	"test_fptr.hip"
	.globl	_Z16__device_stub__cPf          # -- Begin function _Z16__device_stub__cPf
	.type	_Z16__device_stub__cPf,@function
_Z16__device_stub__cPf:                 # @_Z16__device_stub__cPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z1cPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z16__device_stub__cPf, .Lfunc_end0-_Z16__device_stub__cPf
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z1cPf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z1cPf,@object                  # @_Z1cPf
	.section	.rodata,"a",@progbits
	.globl	_Z1cPf
	.p2align	3, 0x0
_Z1cPf:
	.quad	_Z16__device_stub__cPf
	.size	_Z1cPf, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z1cPf"
	.size	.L__unnamed_1, 7

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z16__device_stub__cPf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z1cPf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.p2align	2                               ; -- Begin function _Z2a0RK7VMState
	.type	_Z2a0RK7VMState,@function
_Z2a0RK7VMState:                        ; @_Z2a0RK7VMState
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	s_clause 0x1
	flat_load_b32 v2, v[0:1]
	flat_load_b64 v[0:1], v[0:1] offset:8
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
	v_mov_b32_e32 v2, 0
	flat_store_b32 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end0:
	.size	_Z2a0RK7VMState, .Lfunc_end0-_Z2a0RK7VMState
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 84
; NumSgprs: 34
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
	.text
	.p2align	2                               ; -- Begin function _Z2a1RK7VMState
	.type	_Z2a1RK7VMState,@function
_Z2a1RK7VMState:                        ; @_Z2a1RK7VMState
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	s_clause 0x1
	flat_load_b32 v2, v[0:1]
	flat_load_b64 v[0:1], v[0:1] offset:8
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
	v_mov_b32_e32 v2, 1.0
	flat_store_b32 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end1:
	.size	_Z2a1RK7VMState, .Lfunc_end1-_Z2a1RK7VMState
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 84
; NumSgprs: 34
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
	.text
	.p2align	2                               ; -- Begin function _Z2a2RK7VMState
	.type	_Z2a2RK7VMState,@function
_Z2a2RK7VMState:                        ; @_Z2a2RK7VMState
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	s_clause 0x1
	flat_load_b32 v2, v[0:1]
	flat_load_b64 v[0:1], v[0:1] offset:8
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
	v_mov_b32_e32 v2, 2.0
	flat_store_b32 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end2:
	.size	_Z2a2RK7VMState, .Lfunc_end2-_Z2a2RK7VMState
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 84
; NumSgprs: 34
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
	.text
	.p2align	2                               ; -- Begin function _Z2a3RK7VMState
	.type	_Z2a3RK7VMState,@function
_Z2a3RK7VMState:                        ; @_Z2a3RK7VMState
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	s_clause 0x1
	flat_load_b32 v2, v[0:1]
	flat_load_b64 v[0:1], v[0:1] offset:8
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
	v_mov_b32_e32 v2, 0x40400000
	flat_store_b32 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end3:
	.size	_Z2a3RK7VMState, .Lfunc_end3-_Z2a3RK7VMState
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 88
; NumSgprs: 34
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
	.text
	.p2align	2                               ; -- Begin function _Z2a4RK7VMState
	.type	_Z2a4RK7VMState,@function
_Z2a4RK7VMState:                        ; @_Z2a4RK7VMState
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	s_clause 0x1
	flat_load_b32 v2, v[0:1]
	flat_load_b64 v[0:1], v[0:1] offset:8
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
	v_mov_b32_e32 v2, 4.0
	flat_store_b32 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end4:
	.size	_Z2a4RK7VMState, .Lfunc_end4-_Z2a4RK7VMState
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 84
; NumSgprs: 34
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
	.text
	.p2align	2                               ; -- Begin function _Z2a5RK7VMState
	.type	_Z2a5RK7VMState,@function
_Z2a5RK7VMState:                        ; @_Z2a5RK7VMState
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	s_clause 0x1
	flat_load_b32 v2, v[0:1]
	flat_load_b64 v[0:1], v[0:1] offset:8
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
	v_mov_b32_e32 v2, 0x40a00000
	flat_store_b32 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end5:
	.size	_Z2a5RK7VMState, .Lfunc_end5-_Z2a5RK7VMState
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 88
; NumSgprs: 34
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
	.text
	.p2align	2                               ; -- Begin function _Z2a6RK7VMState
	.type	_Z2a6RK7VMState,@function
_Z2a6RK7VMState:                        ; @_Z2a6RK7VMState
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	s_clause 0x1
	flat_load_b32 v2, v[0:1]
	flat_load_b64 v[0:1], v[0:1] offset:8
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
	v_mov_b32_e32 v2, 0x40c00000
	flat_store_b32 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end6:
	.size	_Z2a6RK7VMState, .Lfunc_end6-_Z2a6RK7VMState
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 88
; NumSgprs: 34
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
	.text
	.protected	_Z1cPf                  ; -- Begin function _Z1cPf
	.globl	_Z1cPf
	.p2align	8
	.type	_Z1cPf,@function
_Z1cPf:                                 ; @_Z1cPf
; %bb.0:                                ; %.critedge
	v_mov_b32_e32 v31, v0
	s_mov_b64 s[36:37], s[0:1]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _ZL5table@rel32@lo+4
	s_addc_u32 s1, s1, _ZL5table@rel32@hi+12
	s_mov_b64 s[34:35], s[4:5]
	s_mov_b32 s33, s15
	v_and_b32_e32 v0, 0x3ff, v31
	s_mov_b32 s40, s14
	s_mov_b32 s41, s13
	s_mov_b64 s[42:43], src_private_base
	s_mov_b32 s32, 32
	v_mul_u32_u24_e32 v1, 0x2493, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v1, 16, v1
	v_mul_lo_u16 v1, v1, 7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u16 v1, v0, v1
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v1, 3, v1
	global_load_b64 v[1:2], v1, s[0:1]
	s_clause 0x2
	s_load_b32 s4, s[2:3], 0x14
	s_load_b32 s5, s[2:3], 0x8
	s_load_b64 s[0:1], s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s6, s4, 16
	s_and_b32 s4, s4, 0xffff
	s_mul_i32 s5, s5, s14
	s_mul_i32 s4, s4, s6
	s_add_i32 s5, s5, s13
	s_add_u32 s38, s2, 8
	s_addc_u32 s39, s3, 0
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, s4, s5, v[0:1]
	v_dual_mov_b32 v0, 8 :: v_dual_mov_b32 v5, s1
	v_mov_b32_e32 v4, s0
	s_mov_b32 s0, exec_lo
	s_clause 0x1
	scratch_store_b64 off, v[4:5], off offset:16
	scratch_store_b32 off, v3, off offset:8
.LBB7_1:                                ; =>This Inner Loop Header: Depth=1
	v_readfirstlane_b32 s0, v1
	v_readfirstlane_b32 s1, v2
	s_mov_b32 s42, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u64_e64 s[0:1], v[1:2]
	v_mov_b32_e32 v1, s43
	s_mov_b64 s[4:5], s[36:37]
	s_mov_b64 s[8:9], s[38:39]
	s_mov_b64 s[10:11], s[34:35]
	s_mov_b32 s12, s41
	s_mov_b32 s13, s40
	s_mov_b32 s14, s33
	s_swappc_b64 s[30:31], s[0:1]
                                        ; implicit-def: $vgpr1_vgpr2
                                        ; implicit-def: $vgpr31
                                        ; implicit-def: $vgpr0
	s_xor_b32 exec_lo, exec_lo, s42
	s_cbranch_execnz .LBB7_1
; %bb.2:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z1cPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 32
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 1
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 1
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 1
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 32
		.amdhsa_next_free_sgpr 44
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z1cPf, .Lfunc_end7-_Z1cPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 300
; NumSgprs: 46
; NumVgprs: 32
; ScratchSize: 32
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 46
; NumVGPRsForWavesPerEU: 32
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	_ZL5table,@object               ; @_ZL5table
	.section	.data.rel.ro,"aw",@progbits
	.p2align	4, 0x0
_ZL5table:
	.quad	_Z2a0RK7VMState
	.quad	_Z2a1RK7VMState
	.quad	_Z2a2RK7VMState
	.quad	_Z2a3RK7VMState
	.quad	_Z2a4RK7VMState
	.quad	_Z2a5RK7VMState
	.quad	_Z2a6RK7VMState
	.size	_ZL5table, 56

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z2a0RK7VMState
	.addrsig_sym _Z2a1RK7VMState
	.addrsig_sym _Z2a2RK7VMState
	.addrsig_sym _Z2a3RK7VMState
	.addrsig_sym _Z2a4RK7VMState
	.addrsig_sym _Z2a5RK7VMState
	.addrsig_sym _Z2a6RK7VMState
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         88
        .size:           8
        .value_kind:     hidden_hostcall_buffer
      - .offset:         96
        .size:           8
        .value_kind:     hidden_multigrid_sync_arg
      - .offset:         104
        .size:           8
        .value_kind:     hidden_heap_v1
      - .offset:         112
        .size:           8
        .value_kind:     hidden_default_queue
      - .offset:         208
        .size:           8
        .value_kind:     hidden_queue_ptr
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z1cPf
    .private_segment_fixed_size: 32
    .sgpr_count:     46
    .sgpr_spill_count: 0
    .symbol:         _Z1cPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: true
    .vgpr_count:     32
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
