#include "includes.h"
__global__ void max_pooling_kernel(float *feature_map, float *probs, float *target, int feature_map_size, int feature_map_num, int pooling_rate, float *rnd_array, int rnd_num){
__shared__ float shFm[16*MAX_POOLING_RATE][16*MAX_POOLING_RATE];

int imgIdx = blockIdx.y / (feature_map_size / 16 / pooling_rate);
int fmIdx = blockIdx.x / (feature_map_size / 16 / pooling_rate);
int tx = (blockIdx.x % (feature_map_size / pooling_rate / 16)) * 16 + threadIdx.x;
int ty = (blockIdx.y % (feature_map_size / pooling_rate / 16)) * 16 + threadIdx.y;
int subsample_size = feature_map_size / pooling_rate;

int rnd_index = ((blockIdx.y * blockDim.y + threadIdx.y) * (blockIdx.x * blockDim.x)  + threadIdx.x ) % rnd_num;
float rnd = rnd_array[rnd_index];

float *fm = feature_map + imgIdx * feature_map_num * feature_map_size * feature_map_size +
fmIdx * feature_map_size * feature_map_size;

probs = probs + imgIdx * feature_map_num * feature_map_size * feature_map_size +
fmIdx * feature_map_size * feature_map_size;

target = target + imgIdx * feature_map_num * subsample_size * subsample_size +
fmIdx * subsample_size * subsample_size;

for(int i = 0; i < pooling_rate; i++){
for(int j = 0; j < pooling_rate; j++){
shFm[threadIdx.y*pooling_rate+i][threadIdx.x*pooling_rate+j] =
fm[(ty*pooling_rate+i) * feature_map_size + (tx*pooling_rate+j)];
}
}

__syncthreads();

float sum = 0;
for(int i = 0; i < pooling_rate; i++){
for(int j = 0; j < pooling_rate; j++){
if(shFm[threadIdx.y*pooling_rate+i][threadIdx.x*pooling_rate+j] > 50){
shFm[threadIdx.y*pooling_rate+i][threadIdx.x*pooling_rate+j] = 50.0f;
}
shFm[threadIdx.y*pooling_rate+i][threadIdx.x*pooling_rate+j] =
__expf(shFm[threadIdx.y*pooling_rate+i][threadIdx.x*pooling_rate+j]);
sum += shFm[threadIdx.y*pooling_rate+i][threadIdx.x*pooling_rate+j];
}
}
for(int i = 0; i < pooling_rate; i++){
for(int j = 0; j < pooling_rate; j++){
shFm[threadIdx.y*pooling_rate+i][threadIdx.x*pooling_rate+j] =
__fdividef(shFm[threadIdx.y*pooling_rate+i][threadIdx.x*pooling_rate+j], (1.0f + sum));
probs[(ty*pooling_rate+i) * feature_map_size + (tx*pooling_rate+j)] =
shFm[threadIdx.y*pooling_rate+i][threadIdx.x*pooling_rate+j];
fm[(ty*pooling_rate+i) * feature_map_size + (tx*pooling_rate+j)] = 0;
}
}

sum = 0;
bool isStop = false;
for(int i = 0; i < pooling_rate && !isStop; i++){
for(int j = 0; j < pooling_rate && !isStop; j++){
sum += shFm[threadIdx.y*pooling_rate+i][threadIdx.x*pooling_rate+j];
if(rnd < sum){
fm[(ty*pooling_rate+i) * feature_map_size + (tx*pooling_rate+j)] = 1;
isStop = true;
}
}
}
if(isStop){
target[threadIdx.y*subsample_size+threadIdx.x] = 1;
}else{
target[threadIdx.y*subsample_size+threadIdx.x] = 0;
}
}
	.file	"tmpxft_002554af_00000000-6_max_pooling_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z48__device_stub__Z18max_pooling_kernelPfS_S_iiiS_iPfS_S_iiiS_i
	.type	_Z48__device_stub__Z18max_pooling_kernelPfS_S_iiiS_iPfS_S_iiiS_i, @function
_Z48__device_stub__Z18max_pooling_kernelPfS_S_iiiS_iPfS_S_iiiS_i:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movq	%rsp, %rax
	movq	%rax, 168(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z18max_pooling_kernelPfS_S_iiiS_i(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z48__device_stub__Z18max_pooling_kernelPfS_S_iiiS_iPfS_S_iiiS_i, .-_Z48__device_stub__Z18max_pooling_kernelPfS_S_iiiS_iPfS_S_iiiS_i
	.globl	_Z18max_pooling_kernelPfS_S_iiiS_i
	.type	_Z18max_pooling_kernelPfS_S_iiiS_i, @function
_Z18max_pooling_kernelPfS_S_iiiS_i:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z18max_pooling_kernelPfS_S_iiiS_iPfS_S_iiiS_i
	.cfi_endproc
.LFE2033:
	.size	_Z18max_pooling_kernelPfS_S_iiiS_i, .-_Z18max_pooling_kernelPfS_S_iiiS_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z18max_pooling_kernelPfS_S_iiiS_i"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z18max_pooling_kernelPfS_S_iiiS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void max_pooling_kernel(float *feature_map, float *probs, float *target, int feature_map_size, int feature_map_num, int pooling_rate, float *rnd_array, int rnd_num){
__shared__ float shFm[16*MAX_POOLING_RATE][16*MAX_POOLING_RATE];

int imgIdx = blockIdx.y / (feature_map_size / 16 / pooling_rate);
int fmIdx = blockIdx.x / (feature_map_size / 16 / pooling_rate);
int tx = (blockIdx.x % (feature_map_size / pooling_rate / 16)) * 16 + threadIdx.x;
int ty = (blockIdx.y % (feature_map_size / pooling_rate / 16)) * 16 + threadIdx.y;
int subsample_size = feature_map_size / pooling_rate;

int rnd_index = ((blockIdx.y * blockDim.y + threadIdx.y) * (blockIdx.x * blockDim.x)  + threadIdx.x ) % rnd_num;
float rnd = rnd_array[rnd_index];

float *fm = feature_map + imgIdx * feature_map_num * feature_map_size * feature_map_size +
fmIdx * feature_map_size * feature_map_size;

probs = probs + imgIdx * feature_map_num * feature_map_size * feature_map_size +
fmIdx * feature_map_size * feature_map_size;

target = target + imgIdx * feature_map_num * subsample_size * subsample_size +
fmIdx * subsample_size * subsample_size;

for(int i = 0; i < pooling_rate; i++){
for(int j = 0; j < pooling_rate; j++){
shFm[threadIdx.y*pooling_rate+i][threadIdx.x*pooling_rate+j] =
fm[(ty*pooling_rate+i) * feature_map_size + (tx*pooling_rate+j)];
}
}

__syncthreads();

float sum = 0;
for(int i = 0; i < pooling_rate; i++){
for(int j = 0; j < pooling_rate; j++){
if(shFm[threadIdx.y*pooling_rate+i][threadIdx.x*pooling_rate+j] > 50){
shFm[threadIdx.y*pooling_rate+i][threadIdx.x*pooling_rate+j] = 50.0f;
}
shFm[threadIdx.y*pooling_rate+i][threadIdx.x*pooling_rate+j] =
__expf(shFm[threadIdx.y*pooling_rate+i][threadIdx.x*pooling_rate+j]);
sum += shFm[threadIdx.y*pooling_rate+i][threadIdx.x*pooling_rate+j];
}
}
for(int i = 0; i < pooling_rate; i++){
for(int j = 0; j < pooling_rate; j++){
shFm[threadIdx.y*pooling_rate+i][threadIdx.x*pooling_rate+j] =
__fdividef(shFm[threadIdx.y*pooling_rate+i][threadIdx.x*pooling_rate+j], (1.0f + sum));
probs[(ty*pooling_rate+i) * feature_map_size + (tx*pooling_rate+j)] =
shFm[threadIdx.y*pooling_rate+i][threadIdx.x*pooling_rate+j];
fm[(ty*pooling_rate+i) * feature_map_size + (tx*pooling_rate+j)] = 0;
}
}

sum = 0;
bool isStop = false;
for(int i = 0; i < pooling_rate && !isStop; i++){
for(int j = 0; j < pooling_rate && !isStop; j++){
sum += shFm[threadIdx.y*pooling_rate+i][threadIdx.x*pooling_rate+j];
if(rnd < sum){
fm[(ty*pooling_rate+i) * feature_map_size + (tx*pooling_rate+j)] = 1;
isStop = true;
}
}
}
if(isStop){
target[threadIdx.y*subsample_size+threadIdx.x] = 1;
}else{
target[threadIdx.y*subsample_size+threadIdx.x] = 0;
}
}
	.text
	.file	"max_pooling_kernel.hip"
	.globl	_Z33__device_stub__max_pooling_kernelPfS_S_iiiS_i # -- Begin function _Z33__device_stub__max_pooling_kernelPfS_S_iiiS_i
	.type	_Z33__device_stub__max_pooling_kernelPfS_S_iiiS_i,@function
_Z33__device_stub__max_pooling_kernelPfS_S_iiiS_i: # @_Z33__device_stub__max_pooling_kernelPfS_S_iiiS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18max_pooling_kernelPfS_S_iiiS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__max_pooling_kernelPfS_S_iiiS_i, .Lfunc_end0-_Z33__device_stub__max_pooling_kernelPfS_S_iiiS_i
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18max_pooling_kernelPfS_S_iiiS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18max_pooling_kernelPfS_S_iiiS_i,@object # @_Z18max_pooling_kernelPfS_S_iiiS_i
	.section	.rodata,"a",@progbits
	.globl	_Z18max_pooling_kernelPfS_S_iiiS_i
	.p2align	3, 0x0
_Z18max_pooling_kernelPfS_S_iiiS_i:
	.quad	_Z33__device_stub__max_pooling_kernelPfS_S_iiiS_i
	.size	_Z18max_pooling_kernelPfS_S_iiiS_i, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z18max_pooling_kernelPfS_S_iiiS_i"
	.size	.L__unnamed_1, 35

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__max_pooling_kernelPfS_S_iiiS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18max_pooling_kernelPfS_S_iiiS_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18max_pooling_kernelPfS_S_iiiS_i ; -- Begin function _Z18max_pooling_kernelPfS_S_iiiS_i
	.globl	_Z18max_pooling_kernelPfS_S_iiiS_i
	.p2align	8
	.type	_Z18max_pooling_kernelPfS_S_iiiS_i,@function
_Z18max_pooling_kernelPfS_S_iiiS_i:     ; @_Z18max_pooling_kernelPfS_S_iiiS_i
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x18
	s_load_b64 s[2:3], s[0:1], 0x28
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s8, s6, 31
	s_ashr_i32 s10, s4, 31
	s_add_i32 s7, s6, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s9, s7, s8
	s_lshr_b32 s7, s10, 28
	v_cvt_f32_u32_e32 v1, s9
	s_add_i32 s7, s4, s7
	s_sub_i32 s13, 0, s9
	s_ashr_i32 s12, s7, 4
	s_ashr_i32 s7, s7, 31
	v_rcp_iflag_f32_e32 v1, v1
	s_add_i32 s12, s12, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_xor_b32 s12, s12, s7
	s_xor_b32 s7, s7, s8
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s11, v1
	s_mul_i32 s13, s13, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s13, s11, s13
	s_add_i32 s11, s11, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s13, s12, s11
	s_mul_i32 s16, s13, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s12, s12, s16
	s_add_i32 s16, s13, 1
	s_sub_i32 s17, s12, s9
	s_cmp_ge_u32 s12, s9
	s_cselect_b32 s13, s16, s13
	s_cselect_b32 s12, s17, s12
	s_add_i32 s16, s13, 1
	s_cmp_ge_u32 s12, s9
	s_cselect_b32 s12, s16, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s12, s12, s7
	s_sub_i32 s7, s12, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, s7
	s_sub_i32 s13, 0, s7
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s12, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s13, s13, s12
	s_mul_hi_u32 s13, s12, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s12, s12, s13
	s_mul_hi_u32 s13, s15, s12
	s_mul_hi_u32 s12, s14, s12
	s_mul_i32 s16, s13, s7
	s_add_i32 s17, s13, 1
	s_sub_i32 s16, s15, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s18, s16, s7
	s_cmp_ge_u32 s16, s7
	s_cselect_b32 s13, s17, s13
	s_cselect_b32 s16, s18, s16
	s_add_i32 s17, s13, 1
	s_cmp_ge_u32 s16, s7
	s_mul_i32 s16, s12, s7
	s_cselect_b32 s13, s17, s13
	s_sub_i32 s16, s14, s16
	s_add_i32 s17, s12, 1
	s_sub_i32 s18, s16, s7
	s_cmp_ge_u32 s16, s7
	s_mul_i32 s5, s13, s5
	s_cselect_b32 s12, s17, s12
	s_cselect_b32 s16, s18, s16
	s_add_i32 s17, s12, 1
	s_cmp_ge_u32 s16, s7
	s_mul_i32 s13, s4, s4
	s_cselect_b32 s7, s17, s12
	s_add_i32 s12, s4, s10
	s_xor_b32 s8, s10, s8
	s_xor_b32 s12, s12, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s11, s12, s11
	s_mul_i32 s16, s11, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s10, s12, s16
	s_add_i32 s12, s11, 1
	s_sub_i32 s16, s10, s9
	s_cmp_ge_u32 s10, s9
	s_cselect_b32 s11, s12, s11
	s_cselect_b32 s10, s16, s10
	s_add_i32 s12, s11, 1
	s_cmp_ge_u32 s10, s9
	s_cselect_b32 s9, s12, s11
	s_load_b32 s11, s[0:1], 0x44
	s_xor_b32 s9, s9, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_sub_i32 s12, s9, s8
	s_load_b32 s9, s[0:1], 0x30
	s_ashr_i32 s8, s12, 31
	s_lshr_b32 s8, s8, 28
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s8, s12, s8
	s_ashr_i32 s8, s8, 4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, s8
	s_sub_i32 s16, 0, s8
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s10, v1
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v1, s9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s16, s16, s10
	v_rcp_iflag_f32_e32 v1, v1
	s_mul_hi_u32 s16, s10, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s10, s10, s16
	s_mul_hi_u32 s16, s14, s10
	s_mul_hi_u32 s10, s15, s10
	s_mul_i32 s16, s16, s8
	s_mul_i32 s10, s10, s8
	s_sub_i32 s16, s14, s16
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_sub_i32 s17, s16, s8
	s_cmp_ge_u32 s16, s8
	s_cselect_b32 s16, s17, s16
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_u32_f32_e32 v5, v1
	s_sub_i32 s17, s16, s8
	s_cmp_ge_u32 s16, s8
	v_bfe_u32 v1, v0, 10, 10
	s_cselect_b32 s16, s17, s16
	s_sub_i32 s10, s15, s10
	s_lshl_b32 s16, s16, 4
	s_sub_i32 s17, s10, s8
	s_cmp_ge_u32 s10, s8
	v_and_b32_e32 v0, 0x3ff, v0
	s_cselect_b32 s10, s17, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_sub_i32 s17, s10, s8
	s_cmp_ge_u32 s10, s8
	s_cselect_b32 s17, s17, s10
	s_sub_i32 s8, 0, s9
	v_mul_lo_u32 v4, s8, v5
	s_lshr_b32 s8, s11, 16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s15, s8, v[1:2]
	s_and_b32 s8, s11, 0xffff
	s_mul_i32 s14, s14, s8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v5, v4
	v_mad_u64_u32 v[3:4], null, s14, v2, v[0:1]
	v_lshlrev_b32_e32 v4, 2, v0
	s_mul_i32 s14, s13, s5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v5, v6
	s_ashr_i32 s15, s14, 31
	v_mul_hi_u32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v2, s9
	v_sub_nc_u32_e32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v3, s9, v2
	v_cmp_le_u32_e32 vcc_lo, s9, v2
	v_cndmask_b32_e32 v2, v2, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v3, s9, v2
	v_cmp_le_u32_e32 vcc_lo, s9, v2
	s_load_b128 s[8:11], s[0:1], 0x0
	v_cndmask_b32_e32 v2, v2, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	s_load_b64 s[2:3], s[0:1], 0x10
	s_lshl_b64 s[0:1], s[14:15], 2
	global_load_b32 v2, v[2:3], off
	v_lshl_add_u32 v3, s17, 4, v1
	s_waitcnt lgkmcnt(0)
	s_add_u32 s14, s8, s0
	s_mul_i32 s8, s13, s7
	s_addc_u32 s15, s9, s1
	s_ashr_i32 s9, s8, 31
	v_mul_lo_u32 v3, s4, v3
	s_lshl_b64 s[8:9], s[8:9], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_add_u32 s13, s14, s8
	s_addc_u32 s14, s15, s9
	s_cmp_gt_i32 s6, 0
	s_cselect_b32 s15, -1, 0
	v_add3_u32 v3, v0, v3, s16
	s_cmp_lt_i32 s6, 1
	s_mov_b32 s16, 0
	s_cbranch_scc1 .LBB0_5
; %bb.1:                                ; %.preheader171.lr.ph
	v_mad_u32_u24 v5, 0xc0, v1, v4
	v_mul_lo_u32 v6, s6, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v5, s6, v5
.LBB0_2:                                ; %.preheader171
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v7, v5
	s_mov_b32 s17, 0
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v8, s17, v6
	s_add_i32 s17, s17, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s6, s17
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_u32 v8, vcc_lo, s13, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s14, v9, vcc_lo
	global_load_b32 v8, v[8:9], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v7, v8
	v_add_nc_u32_e32 v7, 4, v7
	s_cbranch_scc0 .LBB0_3
; %bb.4:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v5, 0xc0, v5
	v_add_nc_u32_e32 v6, s4, v6
	s_add_i32 s16, s16, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s16, s6
	s_cbranch_scc0 .LBB0_2
.LBB0_5:                                ; %._crit_edge174
	v_cndmask_b32_e64 v6, 0, 1, s15
	s_and_not1_b32 vcc_lo, exec_lo, s15
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB0_11
; %bb.6:                                ; %.preheader170.lr.ph
	v_mad_u32_u24 v5, 0xc0, v1, v4
	v_mov_b32_e32 v7, 0
	s_mov_b32 s15, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v5, s6, v5
.LBB0_7:                                ; %.preheader170
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_8 Depth 2
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v8, v5
	s_mov_b32 s16, s6
.LBB0_8:                                ;   Parent Loop BB0_7 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ds_load_b32 v9, v8
	s_add_i32 s16, s16, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s16, 0
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f32_e32 vcc_lo, 0x42480000, v9
	v_cndmask_b32_e32 v9, 0x42480000, v9, vcc_lo
	v_mul_f32_e32 v9, 0x3fb8aa3b, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_exp_f32_e32 v9, v9
	ds_store_b32 v8, v9
	v_dual_add_f32 v7, v7, v9 :: v_dual_add_nc_u32 v8, 4, v8
	s_cbranch_scc0 .LBB0_8
; %bb.9:                                ; %._crit_edge178
                                        ;   in Loop: Header=BB0_7 Depth=1
	v_add_nc_u32_e32 v5, 0xc0, v5
	s_add_i32 s15, s15, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s15, s6
	s_cbranch_scc0 .LBB0_7
; %bb.10:                               ; %.preheader169.loopexit
	v_add_f32_e32 v5, 1.0, v7
	s_branch .LBB0_12
.LBB0_11:
	v_mov_b32_e32 v5, 1.0
.LBB0_12:                               ; %.preheader169
	v_cmp_ne_u32_e32 vcc_lo, 1, v6
	s_cbranch_vccnz .LBB0_17
; %bb.13:                               ; %.preheader168.lr.ph
	v_mad_u32_u24 v6, 0xc0, v1, v4
	v_mul_lo_u32 v7, s6, v3
	s_add_u32 s0, s10, s0
	v_mov_b32_e32 v8, 0
	s_addc_u32 s1, s11, s1
	v_mul_lo_u32 v6, s6, v6
	s_add_u32 s0, s0, s8
	s_addc_u32 s1, s1, s9
	s_mov_b32 s8, 0
.LBB0_14:                               ; %.preheader168
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_15 Depth 2
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v9, v6
	s_mov_b32 s9, 0
.LBB0_15:                               ;   Parent Loop BB0_14 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ds_load_b32 v14, v9
	s_waitcnt lgkmcnt(0)
	v_div_scale_f32 v12, null, v5, v5, v14
	v_div_scale_f32 v15, vcc_lo, v14, v5, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v13, v12
	s_waitcnt_depctr 0xfff
	v_fma_f32 v10, -v12, v13, 1.0
	v_dual_fmac_f32 v13, v10, v13 :: v_dual_add_nc_u32 v10, s9, v7
	s_add_i32 s9, s9, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s6, s9
	v_mul_f32_e32 v16, v15, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v11, -v12, v16, v15
	v_fmac_f32_e32 v16, v11, v13
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v12, -v12, v16, v15
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v15, v12, v13, v16
	v_add_co_u32 v12, vcc_lo, s0, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v13, vcc_lo, s1, v11, vcc_lo
	v_div_fixup_f32 v14, v15, v5, v14
	v_add_co_u32 v10, vcc_lo, s13, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s14, v11, vcc_lo
	ds_store_b32 v9, v14
	v_add_nc_u32_e32 v9, 4, v9
	global_store_b32 v[12:13], v14, off
	global_store_b32 v[10:11], v8, off
	s_cbranch_scc0 .LBB0_15
; %bb.16:                               ; %._crit_edge184
                                        ;   in Loop: Header=BB0_14 Depth=1
	v_add_nc_u32_e32 v6, 0xc0, v6
	v_add_nc_u32_e32 v7, s4, v7
	s_add_i32 s8, s8, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s8, s6
	s_cbranch_scc0 .LBB0_14
.LBB0_17:                               ; %.preheader167
	s_cmp_lt_i32 s6, 1
	s_cbranch_scc1 .LBB0_25
; %bb.18:                               ; %.preheader.lr.ph
	v_mad_u32_u24 v4, 0xc0, v1, v4
	v_mul_lo_u32 v3, s6, v3
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, 1.0
	s_mov_b32 s9, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_lo_u32 v4, s6, v4
	s_mov_b32 s10, 0
                                        ; implicit-def: $sgpr8
.LBB0_19:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_20 Depth 2
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v7, v4
	s_mov_b32 s15, 0
	s_mov_b32 s16, 1
                                        ; implicit-def: $sgpr11
                                        ; implicit-def: $sgpr17
.LBB0_20:                               ;   Parent Loop BB0_19 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ds_load_b32 v8, v7
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_nlt_f32_e32 vcc_lo, v2, v5
	v_cmp_lt_f32_e64 s0, v2, v5
	s_and_saveexec_b32 s18, s0
	s_cbranch_execz .LBB0_22
; %bb.21:                               ;   in Loop: Header=BB0_20 Depth=2
	v_add3_u32 v8, v3, s16, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s1, s13, v8
	v_add_co_ci_u32_e64 v9, s1, s14, v9, s1
	global_store_b32 v[8:9], v6, off
.LBB0_22:                               ;   in Loop: Header=BB0_20 Depth=2
	s_or_b32 exec_lo, exec_lo, s18
	s_cmp_ge_i32 s16, s6
	v_add_nc_u32_e32 v7, 4, v7
	s_cselect_b32 s1, -1, 0
	s_add_i32 s16, s16, 1
	s_or_b32 s1, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, exec_lo, s1
	s_or_b32 s15, s1, s15
	s_and_not1_b32 s1, s17, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_and_not1_b32 s11, s11, exec_lo
	s_and_b32 s18, vcc_lo, exec_lo
	s_or_b32 s17, s1, s0
	s_or_b32 s11, s11, s18
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB0_20
; %bb.23:                               ; %._crit_edge191
                                        ;   in Loop: Header=BB0_19 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_add_i32 s10, s10, 1
	v_add_nc_u32_e32 v4, 0xc0, v4
	s_cmp_ge_i32 s10, s6
	v_add_nc_u32_e32 v3, s4, v3
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s0, s17
	s_and_b32 s0, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s9, s0, s9
	s_and_not1_b32 s0, s8, exec_lo
	s_and_b32 s1, s11, exec_lo
	s_or_b32 s8, s0, s1
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB0_19
; %bb.24:                               ; %._crit_edge197
	s_or_b32 exec_lo, exec_lo, s9
	s_mov_b32 s0, 1.0
	s_branch .LBB0_26
.LBB0_25:
	s_mov_b32 s8, -1
                                        ; implicit-def: $sgpr0
.LBB0_26:                               ; %Flow
	v_mov_b32_e32 v2, s0
	s_and_saveexec_b32 s0, s8
; %bb.27:                               ; %.critedge
	v_mov_b32_e32 v2, 0
; %bb.28:
	s_or_b32 exec_lo, exec_lo, s0
	s_mul_i32 s4, s12, s12
	v_mad_u64_u32 v[3:4], null, s12, v1, v[0:1]
	s_mul_i32 s0, s4, s5
	v_mov_b32_e32 v4, 0
	s_ashr_i32 s1, s0, 31
	s_mul_i32 s4, s4, s7
	s_lshl_b64 s[0:1], s[0:1], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_add_u32 s2, s2, s0
	s_addc_u32 s3, s3, s1
	s_ashr_i32 s5, s4, 31
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18max_pooling_kernelPfS_S_iiiS_i
		.amdhsa_group_segment_fixed_size 9216
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18max_pooling_kernelPfS_S_iiiS_i, .Lfunc_end0-_Z18max_pooling_kernelPfS_S_iiiS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1996
; NumSgprs: 21
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 9216 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 9216
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18max_pooling_kernelPfS_S_iiiS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     21
    .sgpr_spill_count: 0
    .symbol:         _Z18max_pooling_kernelPfS_S_iiiS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     17
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
