/*  Project:                ECE 408 Final Project
 *  File Name:              cuda_test.cu
 *  Calls:                  None
 *  Called by:              None
 *  Associated Header:      None
 *  Date created:           Sat Nov 7 2015
 *  Engineers:              Conor Gardner
 *  Compiler:               nvcc
 *  Target OS:              Ubuntu Linux 14.04
 *  Target architecture:    CPU:    x86 (64 bit)
 *                          GPU:    GeForce GTX 970 (compute capability 5.2)
 *  Description:            Simple vector add program designed to verify that your cuda
 *                          toolchain and drivers are properly installed */

#include <cstdio>

// cuda kernel executed on the GPU
__global__ void vector_add(
    unsigned vector_size,
    const float* input_a_d,
    const float* input_b_d,
    float* output_d
){
    
    unsigned ix = (blockIdx.x * blockDim.x) + threadIdx.x;
    
    if (ix < vector_size)
        output_d[ix] = input_a_d[ix] + input_b_d[ix];
    
}

// CPU code which sends the GPU work and verifies the output
int main()
{
    
    // feel free to customize these parameters
    const unsigned vector_size = 1024;
    const unsigned threads_per_block = 256;
    const float tolerance = 0.01;           // maximum floating-point error when verifying (1%)
    
    // initialize memory on the host (just initilize with arbitrary data)
    float* input_a_h = new float[vector_size];
    float* input_b_h = new float[vector_size];
    float* output_h = new float[vector_size];
    for (unsigned ix = 0; ix < vector_size; ix++)
    {
        input_a_h[ix] = ix * (ix / 3.3f);
        input_b_h[ix] = 7.8f * ix + 8.1f;
    }
    
    // allocate memory on the device and perform host
    float* input_a_d;
    float* input_b_d;
    float* output_d;
    cudaMalloc(&input_a_d, vector_size * sizeof(float));
    cudaMalloc(&input_b_d, vector_size * sizeof(float));
    cudaMalloc(&output_d, vector_size * sizeof(float));
    
    // blocking memory copy host --> device
    cudaMemcpy(input_a_d, input_a_h, vector_size * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(input_b_d, input_b_h, vector_size * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(output_d, output_h, vector_size * sizeof(float), cudaMemcpyHostToDevice);
    
    // invoke the GPU - it will perform the vector addition after the previous memcpy
    unsigned blocks_per_grid = (vector_size - 1) / threads_per_block + 1;
    vector_add<<<blocks_per_grid, threads_per_block>>>(vector_size, input_a_d, input_b_d, output_d);
    
    // blocking memory copy device --> host
    cudaMemcpy(input_a_h, input_a_d, vector_size * sizeof(float), cudaMemcpyDeviceToHost);
    cudaMemcpy(input_b_h, input_b_d, vector_size * sizeof(float), cudaMemcpyDeviceToHost);
    cudaMemcpy(output_h, output_d, vector_size * sizeof(float), cudaMemcpyDeviceToHost);
    
    // de-allocate device memory ASAP
    cudaFree(input_a_d);
    cudaFree(input_b_d);
    cudaFree(output_d);
    
    // verify the data received from the device
    float max_percent_err = 0.0f;
    for (unsigned ix = 0; ix < vector_size; ix++)
    {
        
        float host_result = input_a_h[ix] + input_b_h[ix];
        float device_result = output_h[ix];
        
        float percent_err = (host_result - device_result) / host_result;
        if (percent_err < 0.0f)
            percent_err = -percent_err;
        
        if (percent_err > max_percent_err)
            max_percent_err = percent_err;
        
        // print error message and abort on the first incorrect result
        if (percent_err > tolerance)
        {
            printf
            (
                "FAILED to verify element %u: %f + %f = %f.  GPU returned %f\n",
                ix,
                input_a_h[ix],
                input_b_h[ix],
                host_result,
                device_result
            );
            return -1;
        }
        
    }
    printf("SUCCESS with max error = %3.2f%%\n", max_percent_err * 100.0);
    
    // de-allocate host memory
    delete[] input_a_h;
    delete[] input_b_h;
    delete[] output_h;
    
    return 0;
    
}


	.file	"tmpxft_0035f8d1_00000000-6_cuda_test.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z37__device_stub__Z10vector_addjPKfS0_PfjPKfS0_Pf
	.type	_Z37__device_stub__Z10vector_addjPKfS0_PfjPKfS0_Pf, @function
_Z37__device_stub__Z10vector_addjPKfS0_PfjPKfS0_Pf:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10vector_addjPKfS0_Pf(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z37__device_stub__Z10vector_addjPKfS0_PfjPKfS0_Pf, .-_Z37__device_stub__Z10vector_addjPKfS0_PfjPKfS0_Pf
	.globl	_Z10vector_addjPKfS0_Pf
	.type	_Z10vector_addjPKfS0_Pf, @function
_Z10vector_addjPKfS0_Pf:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z10vector_addjPKfS0_PfjPKfS0_Pf
	.cfi_endproc
.LFE2053:
	.size	_Z10vector_addjPKfS0_Pf, .-_Z10vector_addjPKfS0_Pf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC6:
	.string	"FAILED to verify element %u: %f + %f = %f.  GPU returned %f\n"
.LC8:
	.string	"SUCCESS with max error = %3.2f%%\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$4096, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$64, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	movl	$4096, %edi
	movq	%rax, %rbp
	call	_Znam@PLT
	movl	$4096, %edi
	movq	%rax, %rbx
	call	_Znam@PLT
	movss	.LC1(%rip), %xmm4
	movss	.LC2(%rip), %xmm3
	movss	.LC3(%rip), %xmm2
	movq	%rax, %r12
	xorl	%eax, %eax
.L9:
	cvtsi2ssl	%eax, %xmm0
	movaps	%xmm0, %xmm1
	divss	%xmm4, %xmm1
	mulss	%xmm0, %xmm1
	mulss	%xmm3, %xmm0
	movss	%xmm1, 0(%rbp,%rax,4)
	addss	%xmm2, %xmm0
	movss	%xmm0, (%rbx,%rax,4)
	incq	%rax
	cmpq	$1024, %rax
	jne	.L9
	leaq	8(%rsp), %rdi
	movl	$4096, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$4096, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$4096, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$4096, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$4096, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$4096, %edx
	call	cudaMemcpy@PLT
	movl	$16777217, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1073741825, %edi
	salq	$8, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$2, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movq	24(%rsp), %rcx
	movq	16(%rsp), %rdx
	movl	$1024, %edi
	movq	8(%rsp), %rsi
	call	_Z37__device_stub__Z10vector_addjPKfS0_PfjPKfS0_Pf
.L10:
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movl	$4096, %edx
	movq	%rbp, %rdi
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$4096, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rsi
	movl	$4096, %edx
	movq	%r12, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	xorps	%xmm4, %xmm4
	xorl	%edx, %edx
	movss	.LC4(%rip), %xmm7
	movaps	%xmm4, %xmm6
.L17:
	movss	0(%rbp,%rdx,4), %xmm0
	movss	(%rbx,%rdx,4), %xmm1
	movss	(%r12,%rdx,4), %xmm3
	movaps	%xmm0, %xmm2
	addss	%xmm1, %xmm2
	movaps	%xmm2, %xmm5
	subss	%xmm3, %xmm5
	divss	%xmm2, %xmm5
	comiss	%xmm5, %xmm6
	jbe	.L11
	xorps	%xmm7, %xmm5
.L11:
	movaps	%xmm5, %xmm8
	comiss	.LC5(%rip), %xmm5
	maxss	%xmm4, %xmm8
	movaps	%xmm8, %xmm4
	jbe	.L24
	movl	$2, %edi
	movb	$4, %al
	cvtss2sd	%xmm0, %xmm0
	cvtss2sd	%xmm3, %xmm3
	leaq	.LC6(%rip), %rsi
	cvtss2sd	%xmm2, %xmm2
	cvtss2sd	%xmm1, %xmm1
	call	__printf_chk@PLT
	orl	$-1, %eax
	jmp	.L8
.L24:
	incq	%rdx
	cmpq	$1024, %rdx
	jne	.L17
	cvtss2sd	%xmm8, %xmm0
	leaq	.LC8(%rip), %rsi
	mulsd	.LC7(%rip), %xmm0
	movl	$2, %edi
	movb	$1, %al
	call	__printf_chk@PLT
	movq	%rbp, %rdi
	call	_ZdaPv@PLT
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
	movq	%r12, %rdi
	call	_ZdaPv@PLT
	xorl	%eax, %eax
.L8:
	movq	56(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$64, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC9:
	.string	"_Z10vector_addjPKfS0_Pf"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10vector_addjPKfS0_Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1079194419
	.align 4
.LC2:
	.long	1090099610
	.align 4
.LC3:
	.long	1090623898
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC4:
	.long	-2147483648
	.long	0
	.long	0
	.long	0
	.section	.rodata.cst4
	.align 4
.LC5:
	.long	1008981770
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC7:
	.long	0
	.long	1079574528
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*  Project:                ECE 408 Final Project
 *  File Name:              cuda_test.cu
 *  Calls:                  None
 *  Called by:              None
 *  Associated Header:      None
 *  Date created:           Sat Nov 7 2015
 *  Engineers:              Conor Gardner
 *  Compiler:               nvcc
 *  Target OS:              Ubuntu Linux 14.04
 *  Target architecture:    CPU:    x86 (64 bit)
 *                          GPU:    GeForce GTX 970 (compute capability 5.2)
 *  Description:            Simple vector add program designed to verify that your cuda
 *                          toolchain and drivers are properly installed */


#include <hip/hip_runtime.h>
#include <cstdio>

// cuda kernel executed on the GPU
__global__ void vector_add(
    unsigned vector_size,
    const float* input_a_d,
    const float* input_b_d,
    float* output_d
){
    
    unsigned ix = (blockIdx.x * blockDim.x) + threadIdx.x;
    
    if (ix < vector_size)
        output_d[ix] = input_a_d[ix] + input_b_d[ix];
    
}

// CPU code which sends the GPU work and verifies the output
int main()
{
    
    // feel free to customize these parameters
    const unsigned vector_size = 1024;
    const unsigned threads_per_block = 256;
    const float tolerance = 0.01;           // maximum floating-point error when verifying (1%)
    
    // initialize memory on the host (just initilize with arbitrary data)
    float* input_a_h = new float[vector_size];
    float* input_b_h = new float[vector_size];
    float* output_h = new float[vector_size];
    for (unsigned ix = 0; ix < vector_size; ix++)
    {
        input_a_h[ix] = ix * (ix / 3.3f);
        input_b_h[ix] = 7.8f * ix + 8.1f;
    }
    
    // allocate memory on the device and perform host
    float* input_a_d;
    float* input_b_d;
    float* output_d;
    hipMalloc(&input_a_d, vector_size * sizeof(float));
    hipMalloc(&input_b_d, vector_size * sizeof(float));
    hipMalloc(&output_d, vector_size * sizeof(float));
    
    // blocking memory copy host --> device
    hipMemcpy(input_a_d, input_a_h, vector_size * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(input_b_d, input_b_h, vector_size * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(output_d, output_h, vector_size * sizeof(float), hipMemcpyHostToDevice);
    
    // invoke the GPU - it will perform the vector addition after the previous memcpy
    unsigned blocks_per_grid = (vector_size - 1) / threads_per_block + 1;
    vector_add<<<blocks_per_grid, threads_per_block>>>(vector_size, input_a_d, input_b_d, output_d);
    
    // blocking memory copy device --> host
    hipMemcpy(input_a_h, input_a_d, vector_size * sizeof(float), hipMemcpyDeviceToHost);
    hipMemcpy(input_b_h, input_b_d, vector_size * sizeof(float), hipMemcpyDeviceToHost);
    hipMemcpy(output_h, output_d, vector_size * sizeof(float), hipMemcpyDeviceToHost);
    
    // de-allocate device memory ASAP
    hipFree(input_a_d);
    hipFree(input_b_d);
    hipFree(output_d);
    
    // verify the data received from the device
    float max_percent_err = 0.0f;
    for (unsigned ix = 0; ix < vector_size; ix++)
    {
        
        float host_result = input_a_h[ix] + input_b_h[ix];
        float device_result = output_h[ix];
        
        float percent_err = (host_result - device_result) / host_result;
        if (percent_err < 0.0f)
            percent_err = -percent_err;
        
        if (percent_err > max_percent_err)
            max_percent_err = percent_err;
        
        // print error message and abort on the first incorrect result
        if (percent_err > tolerance)
        {
            printf
            (
                "FAILED to verify element %u: %f + %f = %f.  GPU returned %f\n",
                ix,
                input_a_h[ix],
                input_b_h[ix],
                host_result,
                device_result
            );
            return -1;
        }
        
    }
    printf("SUCCESS with max error = %3.2f%%\n", max_percent_err * 100.0);
    
    // de-allocate host memory
    delete[] input_a_h;
    delete[] input_b_h;
    delete[] output_h;
    
    return 0;
    
}


	.text
	.file	"cuda_test.hip"
	.globl	_Z25__device_stub__vector_addjPKfS0_Pf # -- Begin function _Z25__device_stub__vector_addjPKfS0_Pf
	.type	_Z25__device_stub__vector_addjPKfS0_Pf,@function
_Z25__device_stub__vector_addjPKfS0_Pf: # @_Z25__device_stub__vector_addjPKfS0_Pf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10vector_addjPKfS0_Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__vector_addjPKfS0_Pf, .Lfunc_end0-_Z25__device_stub__vector_addjPKfS0_Pf
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x40533333                      # float 3.29999995
.LCPI1_1:
	.long	0x40f9999a                      # float 7.80000019
.LCPI1_2:
	.long	0x4101999a                      # float 8.10000038
.LCPI1_4:
	.long	0x3c23d70a                      # float 0.00999999977
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0
.LCPI1_3:
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI1_5:
	.quad	0x4059000000000000              # double 100
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$4096, %edi                     # imm = 0x1000
	callq	_Znam
	movq	%rax, %rbx
	movl	$4096, %edi                     # imm = 0x1000
	callq	_Znam
	movq	%rax, %r14
	movl	$4096, %edi                     # imm = 0x1000
	callq	_Znam
	movq	%rax, %r15
	xorl	%eax, %eax
	movss	.LCPI1_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movss	.LCPI1_1(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	movss	.LCPI1_2(%rip), %xmm2           # xmm2 = mem[0],zero,zero,zero
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movl	%eax, %ecx
	xorps	%xmm3, %xmm3
	cvtsi2ss	%rcx, %xmm3
	movaps	%xmm3, %xmm4
	divss	%xmm0, %xmm4
	mulss	%xmm3, %xmm4
	movss	%xmm4, (%rbx,%rax,4)
	mulss	%xmm1, %xmm3
	addss	%xmm2, %xmm3
	movss	%xmm3, (%r14,%rax,4)
	incq	%rax
	cmpq	$1024, %rax                     # imm = 0x400
	jne	.LBB1_1
# %bb.2:
	leaq	16(%rsp), %r12
	movl	$4096, %esi                     # imm = 0x1000
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %r13
	movl	$4096, %esi                     # imm = 0x1000
	movq	%r13, %rdi
	callq	hipMalloc
	movq	%rsp, %rbp
	movl	$4096, %esi                     # imm = 0x1000
	movq	%rbp, %rdi
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$4096, %edx                     # imm = 0x1000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$4096, %edx                     # imm = 0x1000
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movl	$4096, %edx                     # imm = 0x1000
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967300, %rdi               # imm = 0x100000004
	leaq	252(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.3:
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movq	(%rsp), %rcx
	movl	$1024, %edi                     # imm = 0x400
	callq	_Z25__device_stub__vector_addjPKfS0_Pf
.LBB1_4:
	movq	16(%rsp), %rsi
	movl	$4096, %edx                     # imm = 0x1000
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	movl	$4096, %edx                     # imm = 0x1000
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rsi
	movl	$4096, %edx                     # imm = 0x1000
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	xorps	%xmm2, %xmm2
	xorl	%esi, %esi
	movaps	.LCPI1_3(%rip), %xmm0           # xmm0 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
	movss	.LCPI1_4(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
.LBB1_5:                                # =>This Inner Loop Header: Depth=1
	movss	(%rbx,%rsi,4), %xmm4            # xmm4 = mem[0],zero,zero,zero
	movss	(%r14,%rsi,4), %xmm5            # xmm5 = mem[0],zero,zero,zero
	movaps	%xmm4, %xmm6
	addss	%xmm5, %xmm6
	movss	(%r15,%rsi,4), %xmm7            # xmm7 = mem[0],zero,zero,zero
	movaps	%xmm6, %xmm8
	subss	%xmm7, %xmm8
	divss	%xmm6, %xmm8
	movaps	%xmm8, %xmm3
	xorps	%xmm0, %xmm3
	maxss	%xmm8, %xmm3
	ucomiss	%xmm1, %xmm3
	ja	.LBB1_9
# %bb.6:                                #   in Loop: Header=BB1_5 Depth=1
	maxss	%xmm2, %xmm3
	incq	%rsi
	movaps	%xmm3, %xmm2
	cmpq	$1024, %rsi                     # imm = 0x400
	jne	.LBB1_5
# %bb.7:
	xorps	%xmm0, %xmm0
	cvtss2sd	%xmm3, %xmm0
	mulsd	.LCPI1_5(%rip), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	movq	%rbx, %rdi
	callq	_ZdaPv
	movq	%r14, %rdi
	callq	_ZdaPv
	movq	%r15, %rdi
	callq	_ZdaPv
	xorl	%eax, %eax
	jmp	.LBB1_8
.LBB1_9:
	xorps	%xmm0, %xmm0
	cvtss2sd	%xmm4, %xmm0
	xorps	%xmm1, %xmm1
	cvtss2sd	%xmm5, %xmm1
	xorps	%xmm2, %xmm2
	cvtss2sd	%xmm6, %xmm2
	xorps	%xmm3, %xmm3
	cvtss2sd	%xmm7, %xmm3
	movl	$.L.str, %edi
                                        # kill: def $esi killed $esi killed $rsi
	movb	$4, %al
	callq	printf
	movl	$-1, %eax
.LBB1_8:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10vector_addjPKfS0_Pf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10vector_addjPKfS0_Pf,@object # @_Z10vector_addjPKfS0_Pf
	.section	.rodata,"a",@progbits
	.globl	_Z10vector_addjPKfS0_Pf
	.p2align	3, 0x0
_Z10vector_addjPKfS0_Pf:
	.quad	_Z25__device_stub__vector_addjPKfS0_Pf
	.size	_Z10vector_addjPKfS0_Pf, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"FAILED to verify element %u: %f + %f = %f.  GPU returned %f\n"
	.size	.L.str, 61

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"SUCCESS with max error = %3.2f%%\n"
	.size	.L.str.1, 34

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10vector_addjPKfS0_Pf"
	.size	.L__unnamed_1, 24

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__vector_addjPKfS0_Pf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10vector_addjPKfS0_Pf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10vector_addjPKfS0_Pf ; -- Begin function _Z10vector_addjPKfS0_Pf
	.globl	_Z10vector_addjPKfS0_Pf
	.p2align	8
	.type	_Z10vector_addjPKfS0_Pf,@function
_Z10vector_addjPKfS0_Pf:                ; @_Z10vector_addjPKfS0_Pf
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b32 s3, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s3, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x8
	v_mov_b32_e32 v2, 0
	s_load_b64 s[0:1], s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10vector_addjPKfS0_Pf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10vector_addjPKfS0_Pf, .Lfunc_end0-_Z10vector_addjPKfS0_Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 180
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10vector_addjPKfS0_Pf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10vector_addjPKfS0_Pf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
