#include<cuda.h>
#include<stdio.h>
#include<stdlib.h>
#include<iostream>

float *hs_device, *gs_device;
double *hd_device, *gd_device;
const unsigned int SINGLE_PRECISION = 1;
const unsigned int DOUBLE_PRECISION = 0;

//generate matrix
template<typename T>
T *GenMatrix(const unsigned int width, const unsigned int height)
{
	T *matrix;
	const unsigned int M_SIZE = width*height;
	unsigned int i = 0, j = 0;
	matrix  = (T*) malloc(M_SIZE * sizeof(double));
	for(i = 0 ;i < height; i++){
		for(j = 0 ;j < width; j++){
			matrix[i * width + j] = (rand()*1.0)/ RAND_MAX;
		}
	}
	return matrix;
}

//display matrix
template<typename T>
int PrintMatrix(T *P, const unsigned int width, const unsigned int height)
{
	unsigned int i = 0, j = 0;
	printf("\n");
	for(i = 0 ;i < height; i++){
		for(j = 0 ;j < width; j++){
			printf("%.3f\t", P[i * width + j]);
		}
		printf("\n");
	}
	return 1;
}
//Init data
template<typename T>
void Init_Cuda(T *M, T *N, const unsigned int width, const unsigned int height, const int sp)
{
	const unsigned int size = width*height*sizeof(T);
	//allocate matrix
	if(sp==SINGLE_PRECISION){
		cudaMalloc((void**)&hs_device, size);
		cudaMemcpy(hs_device, M, size, cudaMemcpyHostToDevice);
		cudaMalloc((void**)&gs_device, size);
		cudaMemcpy(gs_device, N, size,cudaMemcpyHostToDevice);
	}
	else
	{
		cudaMalloc((void**)&hd_device, size);
		cudaMemcpy(hd_device, M, size, cudaMemcpyHostToDevice);
		cudaMalloc((void**)&gd_device, size);
		cudaMemcpy(gd_device, N, size,cudaMemcpyHostToDevice);
	}
}
//Free memory
void Free_Cuda(const int sp)
{
	if(sp==SINGLE_PRECISION){
		cudaFree(hs_device);
		cudaFree(gs_device);
	}
	else
	{
		cudaFree(hd_device);
		cudaFree(gd_device);
	}
}
template<typename T>
__global__ void sor_kernel (T *h, T *g, const unsigned int width, const unsigned int height) {

	int i, r, c;
	i = blockIdx.x*blockDim.x + threadIdx.x;

	while(i<width*height)
	{
		r = i / width;
		c = i % width;

		if (r > 0 && r < height - 1 && c > 0 && c < width - 1) {	//printf("(%d, %d) %.2f %.2f %.2f %.2f\n", i, j, h[(i-1) * N + j] ,  h[(i+1) * N + j] ,  h[i * N + (j-1)] , h[i * N + (j+1)] );
			//printf("\n[%d, %d]", r, c);
			g[r * width + c] = 0.25
					* (h[(r - 1) * width + c] + h[(r + 1) * width + c]
							+ h[r * width + (c - 1)] + h[r * width + (c + 1)]);

		}
		i+=blockDim.x*gridDim.x;
	}

}
template<typename T>
void sor_cpu (T *h, T *g, const unsigned int width, const unsigned int height) {
// note this does Gauss-Seidel relaxation, not Jacobi that is done on gpu
	int i, j;
	for(i=1; i < height-1; i++)
		for(j=1; j < width-1; j++){
			//printf("\n[%d, %d]", i, j);
			//printf("(%d, %d) %.2f %.2f %.2f %.2f\n", i, j, h[(i-1) * N + j] ,  h[(i+1) * N + j] ,  h[i * N + (j-1)] , h[i * N + (j+1)] );
			g[i * width + j] = 0.25 * (h[(i-1) * width + j] + h[(i+1) * width + j]
							+ h[i * width + (j-1)] + h[i * width + (j+1)]);
		}

}
template<typename T>
int Check(const T *KP, const T *CP, const unsigned int width, const unsigned int height)
{
	int i, j;
	float e = 0.001;
	int correct = 1;
	for(i = 1; i < height-1 ; i++)
		for(j = 1; j < width-1; j++)
		{	if(abs(KP[i * width + j] - CP[i * width + j]) > e)
			{	printf("%.5f %.5f\n", KP[i * width + j], CP[i * width + j]);
				return 0;
			}

		}
	return correct;
}
int main(int argc, char *argv[])  {
	// loop counters
	//const int N = 16384;
	unsigned int width = 512;//16384;

	float *hs_host, *gs_host, *ks_host;		// ptr to array holding numbers on host and device to include fixed borders
	double *hd_host, *gd_host, *kd_host;

	int single_double = SINGLE_PRECISION; //1 single, 0 double

	cudaEvent_t start, stop;
	float elapsed_time_ms;

	int T = 128;
	dim3 block(T, 1, 1);
	dim3 grid(((width*width)+ T - 1) / T, 1, 1);
	if (argc != 5) /* argc should be 4 for correct execution */
	{
		/* We print argv[0] assuming it is the program name */
		printf("Wrong parameters. Please use the following format for running.\n");
		printf(" Usage: %s %s %s %s %s", argv[0], "[matrix_size]", "[single|double]", "[divide_val]", "[num_threads]\n");
		exit(EXIT_FAILURE);
	} else {
		//printf("Arguments: %d %d", atoi(argv[1]),	atoi(argv[2]));
		if(atoi(argv[2])!=0)
			single_double = SINGLE_PRECISION;
		else
			single_double = DOUBLE_PRECISION;
		width = atoi(argv[1]);
		block.x = atoi(argv[4]);
		grid.x = ((width*width)/atoi(argv[3]) + block.x - 1) / block.x;

	}
if(single_double==SINGLE_PRECISION)
{
	hs_host = GenMatrix<float>(width, width);
	gs_host = GenMatrix<float>(width, width);
	ks_host = GenMatrix<float>(width, width);

	//PrintMatrix<float>(hs_host, N);
	Init_Cuda<float>(hs_host, gs_host, width, width, SINGLE_PRECISION);
}
else
{
	hd_host = GenMatrix<double>(width, width);
	gd_host = GenMatrix<double>(width, width);
	kd_host = GenMatrix<double>(width, width);
	Init_Cuda<double>(hd_host, gd_host, width, width, DOUBLE_PRECISION);
}

	cudaEventCreate( &start );     // instrument code to measure start time
	cudaEventCreate( &stop );
	cudaEventRecord( start, 0 );
	cudaEventSynchronize( start );

if(single_double==SINGLE_PRECISION)
{
	sor_kernel<float><<<grid,block>>>(hs_device, gs_device, width, width);
	cudaMemcpy(gs_host, gs_device, width*width*sizeof(float) ,cudaMemcpyDeviceToHost);	// copy results back to host, array g
}
else
{
	sor_kernel<double><<<grid,block>>>(hd_device, gd_device, width, width);
	cudaMemcpy(gd_host, gd_device, width*width*sizeof(float) ,cudaMemcpyDeviceToHost);	// copy results back to host, array g
}

	//PrintMatrix(g, width, height);

	cudaEventRecord( stop, 0 );     // instrument code to measue end time
	cudaEventSynchronize( stop );
	cudaEventElapsedTime( &elapsed_time_ms, start, stop );

	printf("[ %s ][ %4dx%4d ][ %10d blocks ][ %5d threads ]\t>\t[ %7.3f (ms) ]\n", ((single_double==SINGLE_PRECISION)?"Single Precision":"Double Precision"), width, width, grid.x, block.x, elapsed_time_ms);

if(single_double==SINGLE_PRECISION)
{
	//sor_cpu<float>(hs_host, ks_host, width, height);
//	/PrintMatrix(ks_host, width, height);
	//if(Check(gs_host, ks_host, width, height)==1)
	//	printf("We do it.\n");
	//else
	//	printf("Something is wrong.\n");
	free(hs_host);
	free(gs_host);
	free(ks_host);
	Free_Cuda(SINGLE_PRECISION);
}
else
{
	//sor_cpu<double>(hd_host, kd_host, width, height);
//	/PrintMatrix(kd_host, width, height);
	//if(Check(gd_host, kd_host, width, height)==1)
	//	printf("We do it.\n");
	//else
	//	printf("Something is wrong.\n");
	free(hd_host);
	free(gd_host);
	free(kd_host);
	Free_Cuda(DOUBLE_PRECISION);
}

	return 0;
}

	.file	"tmpxft_0027721b_00000000-6_sor_s_d.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3646:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3646:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z9Free_Cudai.part.0, @function
_Z9Free_Cudai.part.0:
.LFB4298:
	.cfi_startproc
	pushq	%rax
	.cfi_def_cfa_offset 16
	movq	hs_device(%rip), %rdi
	call	cudaFree@PLT
	movq	gs_device(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	cudaFree@PLT
	.cfi_endproc
.LFE4298:
	.size	_Z9Free_Cudai.part.0, .-_Z9Free_Cudai.part.0
	.type	_ZL40__device_stub__Z10sor_kernelIfEvPT_S1_jjPfS_jj, @function
_ZL40__device_stub__Z10sor_kernelIfEvPT_S1_jjPfS_jj:
.LFB3668:
	.cfi_startproc
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10sor_kernelIfEvPT_S1_jj(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L4:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3668:
	.size	_ZL40__device_stub__Z10sor_kernelIfEvPT_S1_jjPfS_jj, .-_ZL40__device_stub__Z10sor_kernelIfEvPT_S1_jjPfS_jj
	.type	_ZL40__device_stub__Z10sor_kernelIdEvPT_S1_jjPdS_jj, @function
_ZL40__device_stub__Z10sor_kernelIdEvPT_S1_jjPdS_jj:
.LFB3670:
	.cfi_startproc
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10sor_kernelIdEvPT_S1_jj(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L9:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3670:
	.size	_ZL40__device_stub__Z10sor_kernelIdEvPT_S1_jjPdS_jj, .-_ZL40__device_stub__Z10sor_kernelIdEvPT_S1_jjPdS_jj
	.section	.text._Z10sor_kernelIfEvPT_S1_jj,"axG",@progbits,_Z10sor_kernelIfEvPT_S1_jj,comdat
	.weak	_Z10sor_kernelIfEvPT_S1_jj
	.type	_Z10sor_kernelIfEvPT_S1_jj, @function
_Z10sor_kernelIfEvPT_S1_jj:
.LFB3977:
	.cfi_startproc
	endbr64
	jmp	_ZL40__device_stub__Z10sor_kernelIfEvPT_S1_jjPfS_jj
	.cfi_endproc
.LFE3977:
	.size	_Z10sor_kernelIfEvPT_S1_jj, .-_Z10sor_kernelIfEvPT_S1_jj
	.section	.text._Z10sor_kernelIdEvPT_S1_jj,"axG",@progbits,_Z10sor_kernelIdEvPT_S1_jj,comdat
	.weak	_Z10sor_kernelIdEvPT_S1_jj
	.type	_Z10sor_kernelIdEvPT_S1_jj, @function
_Z10sor_kernelIdEvPT_S1_jj:
.LFB3978:
	.cfi_startproc
	endbr64
	jmp	_ZL40__device_stub__Z10sor_kernelIdEvPT_S1_jjPdS_jj
	.cfi_endproc
.LFE3978:
	.size	_Z10sor_kernelIdEvPT_S1_jj, .-_Z10sor_kernelIdEvPT_S1_jj
	.text
	.globl	_Z9Free_Cudai
	.type	_Z9Free_Cudai, @function
_Z9Free_Cudai:
.LFB3638:
	.cfi_startproc
	endbr64
	decl	%edi
	jne	.L16
	jmp	_Z9Free_Cudai.part.0
.L16:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movq	hd_device(%rip), %rdi
	call	cudaFree@PLT
	movq	gd_device(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	cudaFree@PLT
	.cfi_endproc
.LFE3638:
	.size	_Z9Free_Cudai, .-_Z9Free_Cudai
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z10sor_kernelIdEvPT_S1_jj"
.LC1:
	.string	"_Z10sor_kernelIfEvPT_S1_jj"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3673:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z10sor_kernelIdEvPT_S1_jj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10sor_kernelIfEvPT_S1_jj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3673:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.text._Z9GenMatrixIfEPT_jj,"axG",@progbits,_Z9GenMatrixIfEPT_jj,comdat
	.weak	_Z9GenMatrixIfEPT_jj
	.type	_Z9GenMatrixIfEPT_jj, @function
_Z9GenMatrixIfEPT_jj:
.LFB3973:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%r15d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%edi, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%esi, %ebx
	imull	%ebx, %edi
	pushq	%rcx
	.cfi_def_cfa_offset 64
	salq	$3, %rdi
	call	malloc@PLT
	movq	%rax, %r13
.L22:
	cmpq	%rbx, %r14
	je	.L27
	movl	%r15d, %ebp
.L24:
	leal	(%r12,%r15), %eax
	cmpl	%eax, %ebp
	je	.L28
	call	rand@PLT
	movl	%eax, %edx
	movl	%ebp, %eax
	incl	%ebp
	cvtsi2sdl	%edx, %xmm0
	divsd	.LC2(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, 0(%r13,%rax,4)
	jmp	.L24
.L28:
	incq	%r14
	movl	%ebp, %r15d
	jmp	.L22
.L27:
	popq	%rdx
	.cfi_def_cfa_offset 56
	movq	%r13, %rax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3973:
	.size	_Z9GenMatrixIfEPT_jj, .-_Z9GenMatrixIfEPT_jj
	.section	.text._Z9GenMatrixIdEPT_jj,"axG",@progbits,_Z9GenMatrixIdEPT_jj,comdat
	.weak	_Z9GenMatrixIdEPT_jj
	.type	_Z9GenMatrixIdEPT_jj, @function
_Z9GenMatrixIdEPT_jj:
.LFB3975:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%r15d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%edi, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%esi, %ebx
	imull	%ebx, %edi
	pushq	%rcx
	.cfi_def_cfa_offset 64
	salq	$3, %rdi
	call	malloc@PLT
	movq	%rax, %r12
.L30:
	cmpq	%rbx, %r14
	je	.L35
	movl	%r15d, %ebp
.L32:
	leal	0(%r13,%r15), %eax
	cmpl	%eax, %ebp
	je	.L36
	call	rand@PLT
	movl	%eax, %edx
	movl	%ebp, %eax
	incl	%ebp
	cvtsi2sdl	%edx, %xmm0
	divsd	.LC2(%rip), %xmm0
	movsd	%xmm0, (%r12,%rax,8)
	jmp	.L32
.L36:
	incq	%r14
	movl	%ebp, %r15d
	jmp	.L30
.L35:
	popq	%rdx
	.cfi_def_cfa_offset 56
	movq	%r12, %rax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3975:
	.size	_Z9GenMatrixIdEPT_jj, .-_Z9GenMatrixIdEPT_jj
	.section	.rodata.str1.1
.LC3:
	.string	"Single Precision"
.LC4:
	.string	"Double Precision"
.LC5:
	.string	"Wrong parameters. Please use the following format for running.\n"
.LC6:
	.string	"[divide_val]"
.LC7:
	.string	"[single|double]"
.LC8:
	.string	"[matrix_size]"
.LC9:
	.string	" Usage: %s %s %s %s %s"
.LC10:
	.string	"[num_threads]\n"
.LC11:
	.string	"[ %s ][ %4dx%4d ][ %10d blocks ][ %5d threads ]\t>\t[ %7.3f (ms) ]\n"
	.section	.text.startup
	.globl	main
	.type	main, @function
main:
.LFB3643:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	movl	$1, 84(%rsp)
	movl	$1, 88(%rsp)
	movl	$1, 96(%rsp)
	movl	$1, 100(%rsp)
	cmpl	$5, %edi
	je	.L38
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	leaq	.LC10(%rip), %rax
	movl	$2, %edi
	leaq	.LC6(%rip), %r9
	pushq	%rsi
	.cfi_remember_state
	.cfi_def_cfa_offset 184
	leaq	.LC7(%rip), %r8
	leaq	.LC8(%rip), %rcx
	pushq	%rax
	.cfi_def_cfa_offset 192
	movq	(%r14), %rdx
	leaq	.LC9(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L38:
	.cfi_restore_state
	movq	16(%rsi), %rdi
	call	atoi@PLT
	movq	8(%r14), %rdi
	movl	%eax, %r13d
	call	atoi@PLT
	movq	32(%r14), %rdi
	movl	%eax, %ebx
	call	atoi@PLT
	movl	%ebx, %ebp
	movq	24(%r14), %rdi
	imull	%ebx, %ebp
	movl	%eax, %r12d
	call	atoi@PLT
	xorl	%edx, %edx
	movl	%ebx, %esi
	movl	%ebx, %edi
	movl	%eax, %ecx
	movl	%ebp, %eax
	divl	%ecx
	xorl	%edx, %edx
	leal	-1(%r12,%rax), %eax
	divl	%r12d
	movl	%eax, %r14d
	testl	%r13d, %r13d
	je	.L39
	call	_Z9GenMatrixIfEPT_jj
	movl	%ebx, %esi
	movl	%ebx, %edi
	leal	0(,%rbp,4), %r15d
	movq	%rax, 16(%rsp)
	call	_Z9GenMatrixIfEPT_jj
	movl	%ebx, %esi
	movl	%ebx, %edi
	movq	%rax, (%rsp)
	call	_Z9GenMatrixIfEPT_jj
	movq	%r15, %rsi
	leaq	hs_device(%rip), %rdi
	movq	%rax, 32(%rsp)
	call	cudaMalloc@PLT
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	movq	%r15, %rdx
	movq	hs_device(%rip), %rdi
	call	cudaMemcpy@PLT
	movq	%r15, %rsi
	leaq	gs_device(%rip), %rdi
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	movl	$1, %ecx
	movq	%r15, %rdx
	movq	gs_device(%rip), %rdi
	jmp	.L51
.L39:
	call	_Z9GenMatrixIdEPT_jj
	movl	%ebx, %esi
	movl	%ebx, %edi
	leal	0(,%rbp,8), %r15d
	movq	%rax, 24(%rsp)
	call	_Z9GenMatrixIdEPT_jj
	movl	%ebx, %esi
	movl	%ebx, %edi
	movq	%rax, 8(%rsp)
	call	_Z9GenMatrixIdEPT_jj
	movq	%r15, %rsi
	leaq	hd_device(%rip), %rdi
	movq	%rax, 40(%rsp)
	call	cudaMalloc@PLT
	movq	24(%rsp), %rsi
	movl	$1, %ecx
	movq	%r15, %rdx
	movq	hd_device(%rip), %rdi
	call	cudaMemcpy@PLT
	movq	%r15, %rsi
	leaq	gd_device(%rip), %rdi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	movl	$1, %ecx
	movq	%r15, %rdx
	movq	gd_device(%rip), %rdi
.L51:
	call	cudaMemcpy@PLT
	leaq	64(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	72(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	64(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	64(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	testl	%r13d, %r13d
	movl	88(%rsp), %ecx
	movl	100(%rsp), %esi
	movl	%r14d, 92(%rsp)
	movl	$0, %r9d
	movq	92(%rsp), %rdi
	movl	$0, %r8d
	movl	%r12d, 80(%rsp)
	movq	80(%rsp), %rdx
	je	.L41
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L42
	movq	gs_device(%rip), %rsi
	movq	hs_device(%rip), %rdi
	movl	%ebx, %ecx
	movl	%ebx, %edx
	call	_ZL40__device_stub__Z10sor_kernelIfEvPT_S1_jjPfS_jj
.L42:
	movl	%ebp, %edx
	movq	gs_device(%rip), %rsi
	movq	(%rsp), %rdi
	movl	$2, %ecx
	salq	$2, %rdx
	jmp	.L52
.L41:
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L44
	movq	gd_device(%rip), %rsi
	movq	hd_device(%rip), %rdi
	movl	%ebx, %ecx
	movl	%ebx, %edx
	call	_ZL40__device_stub__Z10sor_kernelIdEvPT_S1_jjPdS_jj
.L44:
	movl	%ebp, %edx
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movq	gd_device(%rip), %rsi
	salq	$2, %rdx
.L52:
	call	cudaMemcpy@PLT
	movq	72(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	72(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	leaq	60(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	testl	%r13d, %r13d
	movl	%ebx, %ecx
	movl	%r14d, %r9d
	leaq	.LC3(%rip), %rax
	leaq	.LC4(%rip), %rdx
	cvtss2sd	60(%rsp), %xmm0
	movl	%ebx, %r8d
	cmovne	%rax, %rdx
	pushq	%rax
	.cfi_def_cfa_offset 184
	movl	$2, %edi
	movb	$1, %al
	pushq	%r12
	.cfi_def_cfa_offset 192
	leaq	.LC11(%rip), %rsi
	call	__printf_chk@PLT
	popq	%rdx
	.cfi_def_cfa_offset 184
	popq	%rcx
	.cfi_def_cfa_offset 176
	testl	%r13d, %r13d
	je	.L46
	movq	16(%rsp), %rdi
	call	free@PLT
	movq	(%rsp), %rdi
	call	free@PLT
	movq	32(%rsp), %rdi
	call	free@PLT
	call	_Z9Free_Cudai.part.0
	jmp	.L47
.L46:
	movq	24(%rsp), %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	free@PLT
	movq	40(%rsp), %rdi
	call	free@PLT
	xorl	%edi, %edi
	call	_Z9Free_Cudai
.L47:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L48
	call	__stack_chk_fail@PLT
.L48:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3643:
	.size	main, .-main
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	gd_device
	.bss
	.align 8
	.type	gd_device, @object
	.size	gd_device, 8
gd_device:
	.zero	8
	.globl	hd_device
	.align 8
	.type	hd_device, @object
	.size	hd_device, 8
hd_device:
	.zero	8
	.globl	gs_device
	.align 8
	.type	gs_device, @object
	.size	gs_device, 8
gs_device:
	.zero	8
	.globl	hs_device
	.align 8
	.type	hs_device, @object
	.size	hs_device, 8
hs_device:
	.zero	8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC2:
	.long	-4194304
	.long	1105199103
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include<hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<iostream>

float *hs_device, *gs_device;
double *hd_device, *gd_device;
const unsigned int SINGLE_PRECISION = 1;
const unsigned int DOUBLE_PRECISION = 0;

//generate matrix
template<typename T>
T *GenMatrix(const unsigned int width, const unsigned int height)
{
	T *matrix;
	const unsigned int M_SIZE = width*height;
	unsigned int i = 0, j = 0;
	matrix  = (T*) malloc(M_SIZE * sizeof(double));
	for(i = 0 ;i < height; i++){
		for(j = 0 ;j < width; j++){
			matrix[i * width + j] = (rand()*1.0)/ RAND_MAX;
		}
	}
	return matrix;
}

//display matrix
template<typename T>
int PrintMatrix(T *P, const unsigned int width, const unsigned int height)
{
	unsigned int i = 0, j = 0;
	printf("\n");
	for(i = 0 ;i < height; i++){
		for(j = 0 ;j < width; j++){
			printf("%.3f\t", P[i * width + j]);
		}
		printf("\n");
	}
	return 1;
}
//Init data
template<typename T>
void Init_Cuda(T *M, T *N, const unsigned int width, const unsigned int height, const int sp)
{
	const unsigned int size = width*height*sizeof(T);
	//allocate matrix
	if(sp==SINGLE_PRECISION){
		hipMalloc((void**)&hs_device, size);
		hipMemcpy(hs_device, M, size, hipMemcpyHostToDevice);
		hipMalloc((void**)&gs_device, size);
		hipMemcpy(gs_device, N, size,hipMemcpyHostToDevice);
	}
	else
	{
		hipMalloc((void**)&hd_device, size);
		hipMemcpy(hd_device, M, size, hipMemcpyHostToDevice);
		hipMalloc((void**)&gd_device, size);
		hipMemcpy(gd_device, N, size,hipMemcpyHostToDevice);
	}
}
//Free memory
void Free_Cuda(const int sp)
{
	if(sp==SINGLE_PRECISION){
		hipFree(hs_device);
		hipFree(gs_device);
	}
	else
	{
		hipFree(hd_device);
		hipFree(gd_device);
	}
}
template<typename T>
__global__ void sor_kernel (T *h, T *g, const unsigned int width, const unsigned int height) {

	int i, r, c;
	i = blockIdx.x*blockDim.x + threadIdx.x;

	while(i<width*height)
	{
		r = i / width;
		c = i % width;

		if (r > 0 && r < height - 1 && c > 0 && c < width - 1) {	//printf("(%d, %d) %.2f %.2f %.2f %.2f\n", i, j, h[(i-1) * N + j] ,  h[(i+1) * N + j] ,  h[i * N + (j-1)] , h[i * N + (j+1)] );
			//printf("\n[%d, %d]", r, c);
			g[r * width + c] = 0.25
					* (h[(r - 1) * width + c] + h[(r + 1) * width + c]
							+ h[r * width + (c - 1)] + h[r * width + (c + 1)]);

		}
		i+=blockDim.x*gridDim.x;
	}

}
template<typename T>
void sor_cpu (T *h, T *g, const unsigned int width, const unsigned int height) {
// note this does Gauss-Seidel relaxation, not Jacobi that is done on gpu
	int i, j;
	for(i=1; i < height-1; i++)
		for(j=1; j < width-1; j++){
			//printf("\n[%d, %d]", i, j);
			//printf("(%d, %d) %.2f %.2f %.2f %.2f\n", i, j, h[(i-1) * N + j] ,  h[(i+1) * N + j] ,  h[i * N + (j-1)] , h[i * N + (j+1)] );
			g[i * width + j] = 0.25 * (h[(i-1) * width + j] + h[(i+1) * width + j]
							+ h[i * width + (j-1)] + h[i * width + (j+1)]);
		}

}
template<typename T>
int Check(const T *KP, const T *CP, const unsigned int width, const unsigned int height)
{
	int i, j;
	float e = 0.001;
	int correct = 1;
	for(i = 1; i < height-1 ; i++)
		for(j = 1; j < width-1; j++)
		{	if(abs(KP[i * width + j] - CP[i * width + j]) > e)
			{	printf("%.5f %.5f\n", KP[i * width + j], CP[i * width + j]);
				return 0;
			}

		}
	return correct;
}
int main(int argc, char *argv[])  {
	// loop counters
	//const int N = 16384;
	unsigned int width = 512;//16384;

	float *hs_host, *gs_host, *ks_host;		// ptr to array holding numbers on host and device to include fixed borders
	double *hd_host, *gd_host, *kd_host;

	int single_double = SINGLE_PRECISION; //1 single, 0 double

	hipEvent_t start, stop;
	float elapsed_time_ms;

	int T = 128;
	dim3 block(T, 1, 1);
	dim3 grid(((width*width)+ T - 1) / T, 1, 1);
	if (argc != 5) /* argc should be 4 for correct execution */
	{
		/* We print argv[0] assuming it is the program name */
		printf("Wrong parameters. Please use the following format for running.\n");
		printf(" Usage: %s %s %s %s %s", argv[0], "[matrix_size]", "[single|double]", "[divide_val]", "[num_threads]\n");
		exit(EXIT_FAILURE);
	} else {
		//printf("Arguments: %d %d", atoi(argv[1]),	atoi(argv[2]));
		if(atoi(argv[2])!=0)
			single_double = SINGLE_PRECISION;
		else
			single_double = DOUBLE_PRECISION;
		width = atoi(argv[1]);
		block.x = atoi(argv[4]);
		grid.x = ((width*width)/atoi(argv[3]) + block.x - 1) / block.x;

	}
if(single_double==SINGLE_PRECISION)
{
	hs_host = GenMatrix<float>(width, width);
	gs_host = GenMatrix<float>(width, width);
	ks_host = GenMatrix<float>(width, width);

	//PrintMatrix<float>(hs_host, N);
	Init_Cuda<float>(hs_host, gs_host, width, width, SINGLE_PRECISION);
}
else
{
	hd_host = GenMatrix<double>(width, width);
	gd_host = GenMatrix<double>(width, width);
	kd_host = GenMatrix<double>(width, width);
	Init_Cuda<double>(hd_host, gd_host, width, width, DOUBLE_PRECISION);
}

	hipEventCreate( &start );     // instrument code to measure start time
	hipEventCreate( &stop );
	hipEventRecord( start, 0 );
	hipEventSynchronize( start );

if(single_double==SINGLE_PRECISION)
{
	sor_kernel<float><<<grid,block>>>(hs_device, gs_device, width, width);
	hipMemcpy(gs_host, gs_device, width*width*sizeof(float) ,hipMemcpyDeviceToHost);	// copy results back to host, array g
}
else
{
	sor_kernel<double><<<grid,block>>>(hd_device, gd_device, width, width);
	hipMemcpy(gd_host, gd_device, width*width*sizeof(float) ,hipMemcpyDeviceToHost);	// copy results back to host, array g
}

	//PrintMatrix(g, width, height);

	hipEventRecord( stop, 0 );     // instrument code to measue end time
	hipEventSynchronize( stop );
	hipEventElapsedTime( &elapsed_time_ms, start, stop );

	printf("[ %s ][ %4dx%4d ][ %10d blocks ][ %5d threads ]\t>\t[ %7.3f (ms) ]\n", ((single_double==SINGLE_PRECISION)?"Single Precision":"Double Precision"), width, width, grid.x, block.x, elapsed_time_ms);

if(single_double==SINGLE_PRECISION)
{
	//sor_cpu<float>(hs_host, ks_host, width, height);
//	/PrintMatrix(ks_host, width, height);
	//if(Check(gs_host, ks_host, width, height)==1)
	//	printf("We do it.\n");
	//else
	//	printf("Something is wrong.\n");
	free(hs_host);
	free(gs_host);
	free(ks_host);
	Free_Cuda(SINGLE_PRECISION);
}
else
{
	//sor_cpu<double>(hd_host, kd_host, width, height);
//	/PrintMatrix(kd_host, width, height);
	//if(Check(gd_host, kd_host, width, height)==1)
	//	printf("We do it.\n");
	//else
	//	printf("Something is wrong.\n");
	free(hd_host);
	free(gd_host);
	free(kd_host);
	Free_Cuda(DOUBLE_PRECISION);
}

	return 0;
}

	.text
	.file	"sor_s_d.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z9Free_Cudai                   # -- Begin function _Z9Free_Cudai
	.type	_Z9Free_Cudai,@function
_Z9Free_Cudai:                          # @_Z9Free_Cudai
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	cmpl	$1, %edi
	movl	$hs_device, %eax
	movl	$hd_device, %ecx
	cmoveq	%rax, %rcx
	movq	(%rcx), %rdi
	movl	$gs_device, %eax
	movl	$gd_device, %ebx
	cmoveq	%rax, %rbx
	callq	hipFree
	movq	(%rbx), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	hipFree                         # TAILCALL
.Lfunc_end0:
	.size	_Z9Free_Cudai, .Lfunc_end0-_Z9Free_Cudai
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %r15
	cmpl	$5, %edi
	jne	.LBB1_10
# %bb.1:
	movq	16(%r15), %rdi
	callq	atoi
	movl	%eax, %r13d
	movq	8(%r15), %rdi
	callq	atoi
	movl	%eax, %ebx
	movq	32(%r15), %rdi
	callq	atoi
	movl	%eax, %r14d
	movl	%eax, %r12d
	btsq	$32, %r12
	movl	%ebx, %ebp
	imull	%ebx, %ebp
	movq	24(%r15), %rdi
	callq	atoi
	movl	%eax, %ecx
	movl	%ebp, %eax
	xorl	%edx, %edx
	divl	%ecx
                                        # kill: def $eax killed $eax def $rax
	addl	%r14d, %eax
	decl	%eax
	xorl	%edx, %edx
	movq	%r14, 40(%rsp)                  # 8-byte Spill
	divl	%r14d
	movl	%eax, %r15d
	movq	%r15, 48(%rsp)                  # 8-byte Spill
	btsq	$32, %r15
	movl	%r13d, 12(%rsp)                 # 4-byte Spill
	movl	%ebx, %edi
	movl	%ebx, %esi
	testl	%r13d, %r13d
	je	.LBB1_3
# %bb.2:
	callq	_Z9GenMatrixIfEPT_jj
	movq	%rax, %r13
	movl	%ebx, %edi
	movl	%ebx, %esi
	callq	_Z9GenMatrixIfEPT_jj
	movq	%rax, %r14
	movl	%ebx, %edi
	movl	%ebx, %esi
	callq	_Z9GenMatrixIfEPT_jj
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movq	%r13, 32(%rsp)                  # 8-byte Spill
	movq	%r13, %rdi
	movq	%r14, 24(%rsp)                  # 8-byte Spill
	movq	%r14, %rsi
	movl	%ebx, %edx
	movl	%ebx, %ecx
	movl	$1, %r8d
	callq	_Z9Init_CudaIfEvPT_S1_jji
	jmp	.LBB1_4
.LBB1_3:
	callq	_Z9GenMatrixIdEPT_jj
	movq	%rax, %r13
	movl	%ebx, %edi
	movl	%ebx, %esi
	callq	_Z9GenMatrixIdEPT_jj
	movq	%rax, %r14
	movl	%ebx, %edi
	movl	%ebx, %esi
	callq	_Z9GenMatrixIdEPT_jj
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movq	%r13, 32(%rsp)                  # 8-byte Spill
	movq	%r13, %rdi
	movq	%r14, 24(%rsp)                  # 8-byte Spill
	movq	%r14, %rsi
	movl	%ebx, %edx
	movl	%ebx, %ecx
	xorl	%r8d, %r8d
	callq	_Z9Init_CudaIdEvPT_S1_jji
.LBB1_4:
	leaq	56(%rsp), %r13
	movq	%r13, %rdi
	callq	hipEventCreate
	movq	%rsp, %rdi
	callq	hipEventCreate
	movq	(%r13), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%r13), %rdi
	callq	hipEventSynchronize
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	cmpl	$0, 12(%rsp)                    # 4-byte Folded Reload
	je	.LBB1_7
# %bb.5:
	movl	$.L.str.7, %r15d
	movl	$gs_device, %r13d
	movl	$hs_device, %r14d
	testl	%eax, %eax
	jne	.LBB1_9
# %bb.6:
	movq	hs_device(%rip), %rdi
	movq	gs_device(%rip), %rsi
	movl	%ebx, %edx
	movl	%ebx, %ecx
	callq	_Z25__device_stub__sor_kernelIfEvPT_S1_jj
	jmp	.LBB1_9
.LBB1_7:
	movl	$.L.str.8, %r15d
	movl	$gd_device, %r13d
	movl	$hd_device, %r14d
	testl	%eax, %eax
	jne	.LBB1_9
# %bb.8:
	movq	hd_device(%rip), %rdi
	movq	gd_device(%rip), %rsi
	movl	%ebx, %edx
	movl	%ebx, %ecx
	callq	_Z25__device_stub__sor_kernelIdEvPT_S1_jj
.LBB1_9:
	movq	(%r13), %rsi
	movl	%ebp, %edx
	shlq	$2, %rdx
	movq	24(%rsp), %rbp                  # 8-byte Reload
	movq	%rbp, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	movq	56(%rsp), %rsi
	movq	(%rsp), %rdx
	leaq	68(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%r12), %xmm0
	movl	$.L.str.6, %edi
	movq	%r15, %rsi
	movl	%ebx, %edx
	movl	%ebx, %ecx
	movq	48(%rsp), %r8                   # 8-byte Reload
                                        # kill: def $r8d killed $r8d killed $r8
	movq	40(%rsp), %r9                   # 8-byte Reload
                                        # kill: def $r9d killed $r9d killed $r9
	movb	$1, %al
	callq	printf
	movq	32(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	%rbp, %rdi
	callq	free
	movq	16(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	(%r14), %rdi
	callq	hipFree
	movq	(%r13), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_10:
	.cfi_def_cfa_offset 128
	movl	$.Lstr, %edi
	callq	puts@PLT
	movq	(%r15), %rsi
	movl	$.L.str.1, %edi
	movl	$.L.str.2, %edx
	movl	$.L.str.3, %ecx
	movl	$.L.str.4, %r8d
	movl	$.L.str.5, %r9d
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z9GenMatrixIfEPT_jj
.LCPI2_0:
	.quad	0x41dfffffffc00000              # double 2147483647
	.section	.text._Z9GenMatrixIfEPT_jj,"axG",@progbits,_Z9GenMatrixIfEPT_jj,comdat
	.weak	_Z9GenMatrixIfEPT_jj
	.type	_Z9GenMatrixIfEPT_jj,@function
_Z9GenMatrixIfEPT_jj:                   # @_Z9GenMatrixIfEPT_jj
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%esi, %ebx
	movl	%edi, %ebp
	movl	%esi, %edi
	imull	%ebp, %edi
	shlq	$3, %rdi
	callq	malloc
	movq	%rax, %r14
	movl	%ebx, 12(%rsp)                  # 4-byte Spill
	testl	%ebx, %ebx
	je	.LBB2_6
# %bb.1:                                # %.preheader.lr.ph
	movl	%ebp, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	xorl	%ebx, %ebx
	xorl	%r13d, %r13d
.LBB2_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_4 Depth 2
	testl	%ebp, %ebp
	je	.LBB2_5
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB2_2 Depth=1
	movq	16(%rsp), %r15                  # 8-byte Reload
	movl	%ebx, %r12d
.LBB2_4:                                #   Parent Loop BB2_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	movsd	.LCPI2_0(%rip), %xmm1           # xmm1 = mem[0],zero
	xorps	%xmm0, %xmm0
	cvtsi2sd	%eax, %xmm0
	divsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movl	%r12d, %eax
	movss	%xmm0, (%r14,%rax,4)
	incl	%r12d
	decq	%r15
	jne	.LBB2_4
.LBB2_5:                                # %._crit_edge
                                        #   in Loop: Header=BB2_2 Depth=1
	incl	%r13d
	addl	%ebp, %ebx
	cmpl	12(%rsp), %r13d                 # 4-byte Folded Reload
	jne	.LBB2_2
.LBB2_6:                                # %._crit_edge17
	movq	%r14, %rax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z9GenMatrixIfEPT_jj, .Lfunc_end2-_Z9GenMatrixIfEPT_jj
	.cfi_endproc
                                        # -- End function
	.section	.text._Z9Init_CudaIfEvPT_S1_jji,"axG",@progbits,_Z9Init_CudaIfEvPT_S1_jji,comdat
	.weak	_Z9Init_CudaIfEvPT_S1_jji       # -- Begin function _Z9Init_CudaIfEvPT_S1_jji
	.type	_Z9Init_CudaIfEvPT_S1_jji,@function
_Z9Init_CudaIfEvPT_S1_jji:              # @_Z9Init_CudaIfEvPT_S1_jji
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%edx, %ebx
	movq	%rsi, %r14
	movq	%rdi, %r15
	imull	%ecx, %ebx
	shll	$2, %ebx
	cmpl	$1, %r8d
	movl	$hs_device, %eax
	movl	$hd_device, %r12d
	cmoveq	%rax, %r12
	movl	$gs_device, %eax
	movl	$gd_device, %r13d
	cmoveq	%rax, %r13
	movq	%r12, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	(%r12), %rdi
	movq	%r15, %rsi
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r13, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	(%r13), %rdi
	movq	%r14, %rsi
	movq	%rbx, %rdx
	movl	$1, %ecx
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	hipMemcpy                       # TAILCALL
.Lfunc_end3:
	.size	_Z9Init_CudaIfEvPT_S1_jji, .Lfunc_end3-_Z9Init_CudaIfEvPT_S1_jji
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z9GenMatrixIdEPT_jj
.LCPI4_0:
	.quad	0x41dfffffffc00000              # double 2147483647
	.section	.text._Z9GenMatrixIdEPT_jj,"axG",@progbits,_Z9GenMatrixIdEPT_jj,comdat
	.weak	_Z9GenMatrixIdEPT_jj
	.type	_Z9GenMatrixIdEPT_jj,@function
_Z9GenMatrixIdEPT_jj:                   # @_Z9GenMatrixIdEPT_jj
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%esi, %ebx
	movl	%edi, %ebp
	movl	%esi, %edi
	imull	%ebp, %edi
	shlq	$3, %rdi
	callq	malloc
	movq	%rax, %r14
	movl	%ebx, 12(%rsp)                  # 4-byte Spill
	testl	%ebx, %ebx
	je	.LBB4_6
# %bb.1:                                # %.preheader.lr.ph
	movl	%ebp, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	xorl	%ebx, %ebx
	xorl	%r13d, %r13d
.LBB4_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_4 Depth 2
	testl	%ebp, %ebp
	je	.LBB4_5
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB4_2 Depth=1
	movq	16(%rsp), %r15                  # 8-byte Reload
	movl	%ebx, %r12d
.LBB4_4:                                #   Parent Loop BB4_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	movsd	.LCPI4_0(%rip), %xmm1           # xmm1 = mem[0],zero
	xorps	%xmm0, %xmm0
	cvtsi2sd	%eax, %xmm0
	divsd	%xmm1, %xmm0
	movl	%r12d, %eax
	movsd	%xmm0, (%r14,%rax,8)
	incl	%r12d
	decq	%r15
	jne	.LBB4_4
.LBB4_5:                                # %._crit_edge
                                        #   in Loop: Header=BB4_2 Depth=1
	incl	%r13d
	addl	%ebp, %ebx
	cmpl	12(%rsp), %r13d                 # 4-byte Folded Reload
	jne	.LBB4_2
.LBB4_6:                                # %._crit_edge17
	movq	%r14, %rax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z9GenMatrixIdEPT_jj, .Lfunc_end4-_Z9GenMatrixIdEPT_jj
	.cfi_endproc
                                        # -- End function
	.section	.text._Z9Init_CudaIdEvPT_S1_jji,"axG",@progbits,_Z9Init_CudaIdEvPT_S1_jji,comdat
	.weak	_Z9Init_CudaIdEvPT_S1_jji       # -- Begin function _Z9Init_CudaIdEvPT_S1_jji
	.type	_Z9Init_CudaIdEvPT_S1_jji,@function
_Z9Init_CudaIdEvPT_S1_jji:              # @_Z9Init_CudaIdEvPT_S1_jji
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%edx, %ebx
	movq	%rsi, %r14
	movq	%rdi, %r15
	imull	%ecx, %ebx
	shll	$3, %ebx
	cmpl	$1, %r8d
	movl	$hs_device, %eax
	movl	$hd_device, %r12d
	cmoveq	%rax, %r12
	movl	$gs_device, %eax
	movl	$gd_device, %r13d
	cmoveq	%rax, %r13
	movq	%r12, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	(%r12), %rdi
	movq	%r15, %rsi
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r13, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	(%r13), %rdi
	movq	%r14, %rsi
	movq	%rbx, %rdx
	movl	$1, %ecx
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	hipMemcpy                       # TAILCALL
.Lfunc_end5:
	.size	_Z9Init_CudaIdEvPT_S1_jji, .Lfunc_end5-_Z9Init_CudaIdEvPT_S1_jji
	.cfi_endproc
                                        # -- End function
	.section	.text._Z25__device_stub__sor_kernelIfEvPT_S1_jj,"axG",@progbits,_Z25__device_stub__sor_kernelIfEvPT_S1_jj,comdat
	.weak	_Z25__device_stub__sor_kernelIfEvPT_S1_jj # -- Begin function _Z25__device_stub__sor_kernelIfEvPT_S1_jj
	.type	_Z25__device_stub__sor_kernelIfEvPT_S1_jj,@function
_Z25__device_stub__sor_kernelIfEvPT_S1_jj: # @_Z25__device_stub__sor_kernelIfEvPT_S1_jj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10sor_kernelIfEvPT_S1_jj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z25__device_stub__sor_kernelIfEvPT_S1_jj, .Lfunc_end6-_Z25__device_stub__sor_kernelIfEvPT_S1_jj
	.cfi_endproc
                                        # -- End function
	.section	.text._Z25__device_stub__sor_kernelIdEvPT_S1_jj,"axG",@progbits,_Z25__device_stub__sor_kernelIdEvPT_S1_jj,comdat
	.weak	_Z25__device_stub__sor_kernelIdEvPT_S1_jj # -- Begin function _Z25__device_stub__sor_kernelIdEvPT_S1_jj
	.type	_Z25__device_stub__sor_kernelIdEvPT_S1_jj,@function
_Z25__device_stub__sor_kernelIdEvPT_S1_jj: # @_Z25__device_stub__sor_kernelIdEvPT_S1_jj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10sor_kernelIdEvPT_S1_jj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z25__device_stub__sor_kernelIdEvPT_S1_jj, .Lfunc_end7-_Z25__device_stub__sor_kernelIdEvPT_S1_jj
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB8_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB8_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10sor_kernelIfEvPT_S1_jj, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10sor_kernelIdEvPT_S1_jj, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end8:
	.size	__hip_module_ctor, .Lfunc_end8-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB9_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB9_2:
	retq
.Lfunc_end9:
	.size	__hip_module_dtor, .Lfunc_end9-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	hs_device,@object               # @hs_device
	.bss
	.globl	hs_device
	.p2align	3, 0x0
hs_device:
	.quad	0
	.size	hs_device, 8

	.type	gs_device,@object               # @gs_device
	.globl	gs_device
	.p2align	3, 0x0
gs_device:
	.quad	0
	.size	gs_device, 8

	.type	hd_device,@object               # @hd_device
	.globl	hd_device
	.p2align	3, 0x0
hd_device:
	.quad	0
	.size	hd_device, 8

	.type	gd_device,@object               # @gd_device
	.globl	gd_device
	.p2align	3, 0x0
gd_device:
	.quad	0
	.size	gd_device, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	" Usage: %s %s %s %s %s"
	.size	.L.str.1, 23

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"[matrix_size]"
	.size	.L.str.2, 14

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"[single|double]"
	.size	.L.str.3, 16

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"[divide_val]"
	.size	.L.str.4, 13

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"[num_threads]\n"
	.size	.L.str.5, 15

	.type	_Z10sor_kernelIfEvPT_S1_jj,@object # @_Z10sor_kernelIfEvPT_S1_jj
	.section	.rodata._Z10sor_kernelIfEvPT_S1_jj,"aG",@progbits,_Z10sor_kernelIfEvPT_S1_jj,comdat
	.weak	_Z10sor_kernelIfEvPT_S1_jj
	.p2align	3, 0x0
_Z10sor_kernelIfEvPT_S1_jj:
	.quad	_Z25__device_stub__sor_kernelIfEvPT_S1_jj
	.size	_Z10sor_kernelIfEvPT_S1_jj, 8

	.type	_Z10sor_kernelIdEvPT_S1_jj,@object # @_Z10sor_kernelIdEvPT_S1_jj
	.section	.rodata._Z10sor_kernelIdEvPT_S1_jj,"aG",@progbits,_Z10sor_kernelIdEvPT_S1_jj,comdat
	.weak	_Z10sor_kernelIdEvPT_S1_jj
	.p2align	3, 0x0
_Z10sor_kernelIdEvPT_S1_jj:
	.quad	_Z25__device_stub__sor_kernelIdEvPT_S1_jj
	.size	_Z10sor_kernelIdEvPT_S1_jj, 8

	.type	.L.str.6,@object                # @.str.6
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.6:
	.asciz	"[ %s ][ %4dx%4d ][ %10d blocks ][ %5d threads ]\t>\t[ %7.3f (ms) ]\n"
	.size	.L.str.6, 66

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Single Precision"
	.size	.L.str.7, 17

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"Double Precision"
	.size	.L.str.8, 17

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10sor_kernelIfEvPT_S1_jj"
	.size	.L__unnamed_1, 27

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z10sor_kernelIdEvPT_S1_jj"
	.size	.L__unnamed_2, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Wrong parameters. Please use the following format for running."
	.size	.Lstr, 63

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__sor_kernelIfEvPT_S1_jj
	.addrsig_sym _Z25__device_stub__sor_kernelIdEvPT_S1_jj
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym hs_device
	.addrsig_sym gs_device
	.addrsig_sym hd_device
	.addrsig_sym gd_device
	.addrsig_sym _Z10sor_kernelIfEvPT_S1_jj
	.addrsig_sym _Z10sor_kernelIdEvPT_S1_jj
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._Z10sor_kernelIfEvPT_S1_jj,"axG",@progbits,_Z10sor_kernelIfEvPT_S1_jj,comdat
	.protected	_Z10sor_kernelIfEvPT_S1_jj ; -- Begin function _Z10sor_kernelIfEvPT_S1_jj
	.globl	_Z10sor_kernelIfEvPT_S1_jj
	.p2align	8
	.type	_Z10sor_kernelIfEvPT_S1_jj,@function
_Z10sor_kernelIfEvPT_S1_jj:             ; @_Z10sor_kernelIfEvPT_S1_jj
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[8:9], s[0:1], 0x10
	s_add_u32 s2, s0, 24
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s12, s4, 0xffff
	s_mul_i32 s10, s9, s8
	v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s10, v1
	s_cbranch_execz .LBB0_5
; %bb.1:                                ; %.lr.ph
	v_cvt_f32_u32_e32 v0, s8
	s_sub_i32 s11, 0, s8
	s_load_b32 s2, s[2:3], 0x0
	s_load_b128 s[4:7], s[0:1], 0x0
	s_add_i32 s3, s9, -1
	v_rcp_iflag_f32_e32 v0, v0
	s_add_i32 s9, s8, -1
	s_mov_b32 s13, 0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s12, s2, s12
	v_mul_lo_u32 v2, s11, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v0, v2
	v_add_nc_u32_e32 v0, v0, v2
	v_mov_b32_e32 v2, 0
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v6, v0, v1
	v_not_b32_e32 v7, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[3:4], null, s11, v6, v[1:2]
	v_mad_u64_u32 v[4:5], null, s8, v7, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s8, v3
	v_dual_cndmask_b32 v3, v3, v4 :: v_dual_add_nc_u32 v8, 1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v6, v8, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, 1, v5
	v_cndmask_b32_e32 v5, v5, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[3:4], null, s11, v5, v[1:2]
	v_cmp_gt_u32_e32 vcc_lo, s3, v5
	v_cmp_lt_i32_e64 s2, 0, v5
	v_cmp_gt_u32_e64 s0, s9, v3
	v_cmp_lt_i32_e64 s1, 0, v3
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s2, s0
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v4, v2 :: v_dual_add_nc_u32 v3, s11, v1
	v_dual_mov_b32 v6, v2 :: v_dual_add_nc_u32 v5, s8, v1
	v_dual_mov_b32 v8, v2 :: v_dual_add_nc_u32 v7, -1, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_dual_mov_b32 v10, v2 :: v_dual_add_nc_u32 v9, 1, v1
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	s_clause 0x1
	global_load_b32 v11, v[3:4], off
	global_load_b32 v12, v[5:6], off
	v_lshlrev_b64 v[3:4], 2, v[9:10]
	v_add_co_u32 v5, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_clause 0x1
	global_load_b32 v5, v[5:6], off
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v4, v11, v12
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v4, v5
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v4, v3
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v5, 0x3e800000, v5
	v_add_co_u32 v3, vcc_lo, s6, v3
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	global_store_b32 v[3:4], v5, off
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v1, s12, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s10, v1
	s_or_b32 s13, vcc_lo, s13
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_2
.LBB0_5:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10sor_kernelIfEvPT_S1_jj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z10sor_kernelIfEvPT_S1_jj,"axG",@progbits,_Z10sor_kernelIfEvPT_S1_jj,comdat
.Lfunc_end0:
	.size	_Z10sor_kernelIfEvPT_S1_jj, .Lfunc_end0-_Z10sor_kernelIfEvPT_S1_jj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 596
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z10sor_kernelIdEvPT_S1_jj,"axG",@progbits,_Z10sor_kernelIdEvPT_S1_jj,comdat
	.protected	_Z10sor_kernelIdEvPT_S1_jj ; -- Begin function _Z10sor_kernelIdEvPT_S1_jj
	.globl	_Z10sor_kernelIdEvPT_S1_jj
	.p2align	8
	.type	_Z10sor_kernelIdEvPT_S1_jj,@function
_Z10sor_kernelIdEvPT_S1_jj:             ; @_Z10sor_kernelIdEvPT_S1_jj
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[8:9], s[0:1], 0x10
	s_add_u32 s2, s0, 24
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s12, s4, 0xffff
	s_mul_i32 s10, s9, s8
	v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s10, v1
	s_cbranch_execz .LBB1_5
; %bb.1:                                ; %.lr.ph
	v_cvt_f32_u32_e32 v0, s8
	s_sub_i32 s11, 0, s8
	s_load_b32 s2, s[2:3], 0x0
	s_load_b128 s[4:7], s[0:1], 0x0
	s_add_i32 s3, s9, -1
	v_rcp_iflag_f32_e32 v0, v0
	s_add_i32 s9, s8, -1
	s_mov_b32 s13, 0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s12, s2, s12
	v_mul_lo_u32 v2, s11, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v0, v2
	v_add_nc_u32_e32 v0, v0, v2
	v_mov_b32_e32 v2, 0
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v6, v0, v1
	v_not_b32_e32 v7, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[3:4], null, s11, v6, v[1:2]
	v_mad_u64_u32 v[4:5], null, s8, v7, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s8, v3
	v_dual_cndmask_b32 v3, v3, v4 :: v_dual_add_nc_u32 v8, 1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v6, v8, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, 1, v5
	v_cndmask_b32_e32 v5, v5, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[3:4], null, s11, v5, v[1:2]
	v_cmp_gt_u32_e32 vcc_lo, s3, v5
	v_cmp_lt_i32_e64 s2, 0, v5
	v_cmp_gt_u32_e64 s0, s9, v3
	v_cmp_lt_i32_e64 s1, 0, v3
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s2, s0
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB1_4
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	v_dual_mov_b32 v4, v2 :: v_dual_add_nc_u32 v3, s11, v1
	v_dual_mov_b32 v6, v2 :: v_dual_add_nc_u32 v5, s8, v1
	v_dual_mov_b32 v8, v2 :: v_dual_add_nc_u32 v7, -1, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	v_dual_mov_b32 v10, v2 :: v_dual_add_nc_u32 v9, 1, v1
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[7:8], 3, v[7:8]
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	s_clause 0x1
	global_load_b64 v[3:4], v[3:4], off
	global_load_b64 v[5:6], v[5:6], off
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	global_load_b64 v[7:8], v[7:8], off
	v_add_co_u32 v9, vcc_lo, s4, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
	global_load_b64 v[9:10], v[9:10], off
	s_waitcnt vmcnt(2)
	v_add_f64 v[3:4], v[3:4], v[5:6]
	v_lshlrev_b64 v[5:6], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s6, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[3:4], v[3:4], v[7:8]
	s_waitcnt vmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[9:10]
	s_delay_alu instid0(VALU_DEP_1)
	v_ldexp_f64 v[3:4], v[3:4], -2
	global_store_b64 v[5:6], v[3:4], off
.LBB1_4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v1, s12, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s10, v1
	s_or_b32 s13, vcc_lo, s13
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB1_2
.LBB1_5:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10sor_kernelIdEvPT_S1_jj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z10sor_kernelIdEvPT_S1_jj,"axG",@progbits,_Z10sor_kernelIdEvPT_S1_jj,comdat
.Lfunc_end1:
	.size	_Z10sor_kernelIdEvPT_S1_jj, .Lfunc_end1-_Z10sor_kernelIdEvPT_S1_jj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 600
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10sor_kernelIfEvPT_S1_jj
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10sor_kernelIfEvPT_S1_jj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10sor_kernelIdEvPT_S1_jj
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10sor_kernelIdEvPT_S1_jj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
