/* 2dadvec_kernels.cu
 *
 * This file contains the kernels for the 2D advection DG method.
 * We use K = number of elements
 * and    H = number of sides
 */

#define PI 3.14159

/***********************
 *
 * DEVICE VARIABLES
 *
 ***********************/
/* These are always prefixed with d_ for "device" */
double *d_c;           // holds coefficients for each element
double *d_quad_rhs;    // the right hand side containing the quadrature contributions
double *d_left_riemann_rhs;  // the right hand side containing the left riemann contributions
double *d_right_riemann_rhs; // the right hand side containing the right riemann contributions

// runge kutta variables
double *d_kstar;
double *d_k1;
double *d_k2;
double *d_k3;
double *d_k4;

// precomputed basis functions 
// TODO: maybe making these 2^n makes sure the offsets are cached more efficiently? who knows...
// precomputed basis functions ordered like so
//
// [phi_1(r1, s1), phi_1(r2, s2), ... , phi_1(r_nq, s_nq)   ]
// [phi_2(r1, s1), phi_2(r2, s2), ... , phi_2(r_nq, s_nq)   ]
// [   .               .           .            .           ]
// [   .               .           .            .           ]
// [   .               .           .            .           ]
// [phi_np(r1, s1), phi_np(r2, s2), ... , phi_np(r_nq, s_nq)]
//
__device__ __constant__ double basis[2048];
// note: these are multiplied by the weights
__device__ __constant__ double basis_grad_x[2048]; 
__device__ __constant__ double basis_grad_y[2048]; 

// precomputed basis functions evaluated along the sides. ordered
// similarly to basis and basis_grad_{x,y} but with one "matrix" for each side
// starting with side 0. to get to each side, offset with:
//      side_number * n_p * num_quad1d.
__device__ __constant__ double basis_side[1024];
__device__ __constant__ double basis_vertex[256];

// weights for 2d and 1d quadrature rules
__device__ __constant__ double w[32];
__device__ __constant__ double w_oned[16];

__device__ __constant__ double r1[32];
__device__ __constant__ double r2[32];
__device__ __constant__ double r_oned[32];

void set_basis(void *value, int size) {
    cudaMemcpyToSymbol("basis", value, size * sizeof(double));
}
void set_basis_grad_x(void *value, int size) {
    cudaMemcpyToSymbol("basis_grad_x", value, size * sizeof(double));
}
void set_basis_grad_y(void *value, int size) {
    cudaMemcpyToSymbol("basis_grad_y", value, size * sizeof(double));
}
void set_basis_side(void *value, int size) {
    cudaMemcpyToSymbol("basis_side", value, size * sizeof(double));
}
void set_basis_vertex(void *value, int size) {
    cudaMemcpyToSymbol("basis_vertex", value, size * sizeof(double));
}
void set_w(void *value, int size) {
    cudaMemcpyToSymbol("w", value, size * sizeof(double));
}
void set_w_oned(void *value, int size) {
    cudaMemcpyToSymbol("w_oned", value, size * sizeof(double));
}
void set_r1(void *value, int size) {
    cudaMemcpyToSymbol("r1", value, size * sizeof(double));
}
void set_r2(void *value, int size) {
    cudaMemcpyToSymbol("r2", value, size * sizeof(double));
}
void set_r_oned(void *value, int size) {
    cudaMemcpyToSymbol("r_oned", value, size * sizeof(double));
}

// tells which side (1, 2, or 3) to evaluate this boundary integral over
int *d_left_side_number;
int *d_right_side_number;

double *d_J;        // jacobian determinant 
double *d_min_J;      // for the min sized jacobian
double *d_s_length; // length of sides

// the num_elem values of the x and y coordinates for the two vertices defining a side
// TODO: can i delete these after the lengths are precomputed?
//       maybe these should be in texture memory?
double *d_s_V1x;
double *d_s_V1y;
double *d_s_V2x;
double *d_s_V2y;

// the num_elem values of the x and y partials
double *d_xr;
double *d_yr;
double *d_xs;
double *d_ys;

// the K indices of the sides for each element ranged 0->H-1
int *d_elem_s1;
int *d_elem_s2;
int *d_elem_s3;

// vertex x and y coordinates on the mesh which define an element
// TODO: can i delete these after the jacobians are precomputed?
//       maybe these should be in texture memory?
double *d_V1x;
double *d_V1y;
double *d_V2x;
double *d_V2y;
double *d_V3x;
double *d_V3y;

// stores computed values at three vertices
double *d_Uv1;
double *d_Uv2;
double *d_Uv3;

// normal vectors for the sides
double *d_Nx;
double *d_Ny;

// index lists for sides
int *d_left_elem;  // index of left  element for side idx
int *d_right_elem; // index of right element for side idx

/***********************
 *
 * DEVICE FUNCTIONS
 *
 ***********************/

/* flux function
 *
 * evaluates the flux f(u) at the point u.
 */
__device__ double flux_x(double u) {
    return u;
}
__device__ double flux_y(double u) {
    return u;
}

/* riemann solver
 *
 * evaluates the riemann problem over the boundary using Gaussian quadrature
 * with Legendre polynomials as basis functions.
 */
__device__ double riemann(double u_left, double u_right) {
    return 0.5 * (u_left + u_right);
}

/***********************
 *
 * INITIAL CONDITIONS
 *
 ***********************/

/* initial condition function
 *
 * returns the value of the intial condition at point x
 */
__device__ double u0(double x, double y, int alpha) {
    return x + y;//pow(x - y, alpha);
}

/* boundary exact
 *
 * returns the exact boundary conditions
 */
__device__ double boundary_exact(double x, double y, double t, int alpha) {
    return x - 2*t + y;//u0(x, y, alpha);
}

/* u exact
 *
 * returns the exact value of u for error measurement.
 */
__device__ double uexact(double x, double y, double t, int alpha) {
    return u0(x, y, alpha);
}

/* initial conditions
 *
 * computes the coefficients for the initial conditions
 * THREADS: num_elem
 */
__global__ void init_conditions(double *c, double *J,
                                double *V1x, double *V1y,
                                double *V2x, double *V2y,
                                double *V3x, double *V3y,
                                int n_quad, int n_p, int num_elem, int alpha) {
    int idx = blockDim.x * blockIdx.x + threadIdx.x;
    int i, j;
    double x, y, u;

    if (idx < num_elem) {
        for (i = 0; i < n_p; i++) {
            u = 0.;
            // perform quadrature
            for (j = 0; j < n_quad; j++) {
                // map from the canonical element to the actual point on the mesh
                // x = x2 * r + x3 * s + x1 * (1 - r - s)
                x = r1[j] * V2x[idx] + r2[j] * V3x[idx] + (1 - r1[j] - r2[j]) * V1x[idx];
                y = r1[j] * V2y[idx] + r2[j] * V3y[idx] + (1 - r1[j] - r2[j]) * V1y[idx];

                // evaluate u there
                u += w[j] * u0(x, y, alpha) * basis[i * n_quad + j];
            }
            c[i * num_elem + idx] = u;
        } 
    }
}

/* find min jacobian
 *
 * returns the min jacobian inside of min_J. 
 * each block computes the min jacobian inside of that block and stores it in the
 * blockIdx.x spot of the shared min_J variable.
 * NOTE: this is fixed for 256 threads.
 */
__global__ void min_jacobian(double *J, double *min_J, int num_elem) {
    int idx = blockDim.x * blockIdx.x + threadIdx.x;
    int tid = threadIdx.x;
    int i   = blockDim.x * (blockIdx.x * 256 * 2) + threadIdx.x;

    __shared__ double s_min[256];

    if (idx < num_elem) {
        // set all of min to J[idx] initially
        s_min[tid] = J[idx];
        __syncthreads();

        // test a few
        while (i < num_elem) {
            s_min[tid] = (s_min[tid] < J[i]) ? s_min[tid] : J[i];
            s_min[tid] = (s_min[tid] < J[i + 256]) ? s_min[tid] : J[i];
            i += gridDim.x * 256 * 2;
            __syncthreads();
        }

        // first half of the warps
        __syncthreads();
        if (tid < 128) {
            s_min[tid] = (s_min[tid] < s_min[tid + 128]) ? s_min[tid] : s_min[tid + 128];
        }

        // first and second warps
        __syncthreads();
        if (tid < 64) {
            s_min[tid] = (s_min[tid] < s_min[tid + 64]) ? s_min[tid] : s_min[tid + 64];
        }

        // unroll last warp
        __syncthreads();
        if (tid < 32) {
            if (blockDim.x >= 64) {
                s_min[tid] = (s_min[tid] < s_min[tid + 32]) ? s_min[tid] : s_min[tid + 32];
            }
            if (blockDim.x >= 32) {
                s_min[tid] = (s_min[tid] < s_min[tid + 16]) ? s_min[tid] : s_min[tid + 16];
            }
            if (blockDim.x >= 16) {
                s_min[tid] = (s_min[tid] < s_min[tid + 8]) ? s_min[tid] : s_min[tid + 8];
            }
            if (blockDim.x >= 8) {
                s_min[tid] = (s_min[tid] < s_min[tid + 4]) ? s_min[tid] : s_min[tid + 4];
            }
            if (blockDim.x >= 4) {
                s_min[tid] = (s_min[tid] < s_min[tid + 2]) ? s_min[tid] : s_min[tid + 2];
            }
            if (blockDim.x >= 2) {
                s_min[tid] = (s_min[tid] < s_min[tid + 1]) ? s_min[tid] : s_min[tid + 1];
            }
        }

        __syncthreads();
        if (tid == 0) {
            min_J[blockIdx.x] = s_min[0];
        }
    }
}

/***********************
 *
 * PRECOMPUTING
 *
 ***********************/

/* side length computer
 *
 * precomputes the length of each side.
 * THREADS: num_sides
 */ 
__global__ void preval_side_length(double *s_length, 
                              double *s_V1x, double *s_V1y, 
                              double *s_V2x, double *s_V2y,
                              int num_sides) {
    int idx = blockDim.x * blockIdx.x + threadIdx.x;

    if (idx < num_sides) {
        // compute and store the length of the side
        s_length[idx] = sqrtf(pow(s_V1x[idx] - s_V2x[idx],2) + pow(s_V1y[idx] - s_V2y[idx],2));
    }
}

/* jacobian computing
 *
 * precomputes the jacobian determinant for each element.
 * THREADS: num_elem
 */
__global__ void preval_jacobian(double *J, 
                           double *V1x, double *V1y, 
                           double *V2x, double *V2y, 
                           double *V3x, double *V3y,
                           int num_elem) {
    int idx = blockDim.x * blockIdx.x + threadIdx.x;

    if (idx < num_elem) {
        double x1, y1, x2, y2, x3, y3;

        // read vertex points
        x1 = V1x[idx];
        y1 = V1y[idx];
        x2 = V2x[idx];
        y2 = V2y[idx];
        x3 = V3x[idx];
        y3 = V3y[idx];

        // calculate jacobian determinant
        // x = x2 * r + x3 * s + x1 * (1 - r - s)
        J[idx] = (x2 - x1) * (y3 - y1) - (x3 - x1) * (y2 - y1);
    }
}

/* evaluate normal vectors
 *
 * computes the normal vectors for each element along each side.
 * THREADS: num_sides
 *
 */
__global__ void preval_normals(double *Nx, double *Ny, 
                          double *s_V1x, double *s_V1y, 
                          double *s_V2x, double *s_V2y,
                          double *V1x, double *V1y, 
                          double *V2x, double *V2y, 
                          double *V3x, double *V3y,
                          int *left_side_number, int num_sides) {

    int idx = blockDim.x * blockIdx.x + threadIdx.x;

    if (idx < num_sides) {
        double x, y, length;
        double sv1x, sv1y, sv2x, sv2y;
    
        sv1x = s_V1x[idx];
        sv1y = s_V1y[idx];
        sv2x = s_V2x[idx];
        sv2y = s_V2y[idx];
    
        // lengths of the vector components
        x = sv2x - sv1x;
        y = sv2y - sv1y;
    
        // normalize
        length = sqrtf(pow(x, 2) + pow(y, 2));

        // store the result
        Nx[idx] = -y / length;
        Ny[idx] =  x / length;
    }
}

__global__ void preval_normals_direction(double *Nx, double *Ny, 
                          double *V1x, double *V1y, 
                          double *V2x, double *V2y, 
                          double *V3x, double *V3y,
                          int *left_elem, int *left_side_number, int num_sides) {

    int idx = blockDim.x * blockIdx.x + threadIdx.x;

    if (idx < num_sides) {
        double new_x, new_y, dot;
        double initial_x, initial_y, target_x, target_y;
        double x, y;
        int left_idx, side;

        // get left side's vertices
        left_idx = left_elem[idx];
        side     = left_side_number[idx];

        // get the normal vector
        x = Nx[idx];
        y = Ny[idx];
    
        // make it point the correct direction by learning the third vertex point
        switch (side) {
            case 0: 
                target_x = V3x[left_idx];
                target_y = V3y[left_idx];
                initial_x = (V1x[left_idx] + V2x[left_idx]) / 2.;
                initial_y = (V1y[left_idx] + V2y[left_idx]) / 2.;
                break;
            case 1:
                target_x = V1x[left_idx];
                target_y = V1y[left_idx];
                initial_x = (V2x[left_idx] + V3x[left_idx]) / 2.;
                initial_y = (V2y[left_idx] + V3y[left_idx]) / 2.;
                break;
            case 2:
                target_x = V2x[left_idx];
                target_y = V2y[left_idx];
                initial_x = (V1x[left_idx] + V3x[left_idx]) / 2.;
                initial_y = (V1y[left_idx] + V3y[left_idx]) / 2.;
                break;
        }

        // create the vector pointing towards the third vertex point
        new_x = target_x - initial_x;
        new_y = target_y - initial_y;

        // find the dot product between the normal and new vectors
        dot = x * new_x + y * new_y;
        
        if (dot > 0) {
            Nx[idx] *= -1;
            Ny[idx] *= -1;
        }
    }
}

__global__ void preval_partials(double *V1x, double *V1y,
                                double *V2x, double *V2y,
                                double *V3x, double *V3y,
                                double *xr,  double *yr,
                                double *xs,  double *ys, int num_elem) {
    int idx = blockDim.x * blockIdx.x + threadIdx.x;
    if (idx < num_elem) {
        // evaulate the jacobians of the mappings for the chain rule
        // x = x2 * r + x3 * s + x1 * (1 - r - s)
        xr[idx] = V2x[idx] - V1x[idx];
        yr[idx] = V2y[idx] - V1y[idx];
        xs[idx] = V3x[idx] - V1x[idx];
        ys[idx] = V3y[idx] - V1y[idx];
    }
}

/***********************
 *
 * MAIN FUNCTIONS
 *
 ***********************/

/* riemann evaluation
 *
 * device function to solve the riemann problem.
 */
__device__ double eval_riemann(double *c_left, double *c_right,
                              double v1x, double v1y,
                              double v2x, double v2y,
                              double v3x, double v3y,
                              int j, // j, as usual, is the index of the integration point
                              int left_side, int right_side,
                              int left_idx, int right_idx,
                              int n_p, int n_quad1d,
                              int num_sides, double t, int alpha) {

    double u_left, u_right;
    int i;

    u_left  = 0.;
    u_right = 0.;

    for (i = 0; i < n_p; i++) {
        u_left  += c_left[i] * basis_side[left_side * n_p * n_quad1d + i * n_quad1d + j];
    }

    // make all threads in the first warps be boundary sides
    if (right_idx == -1) {
        double r1_eval, r2_eval;
        double x, y;

        // we need the mapping back to the grid space
        switch (left_side) {
            case 0: 
                r1_eval = 0.5 + 0.5 * r_oned[j];
                r2_eval = 0.;
                break;
            case 1: 
                r1_eval = (1. - r_oned[j]) / 2.;
                r2_eval = (1. + r_oned[j]) / 2.;
                break;
            case 2: 
                r1_eval = 0.;
                r2_eval = 0.5 + 0.5 * r_oned[n_quad1d - 1 - j];
                break;
        }

        // x = x2 * r + x3 * s + x1 * (1 - r - s)
        x = v2x * r1_eval + v3x * r2_eval + v1x * (1 - r1_eval - r2_eval);
        y = v2y * r1_eval + v3y * r2_eval + v1y * (1 - r1_eval - r2_eval);
            
        // deal with the boundary element here
        u_right = boundary_exact(x, y, t, alpha);

    } else {
        // evaluate the right side at the integration point
        for (i = 0; i < n_p; i++) {
            u_right  += c_right[i] * basis_side[right_side * n_p * n_quad1d + i * n_quad1d + n_quad1d - 1 - j];
        }
    }

    return riemann(u_left, u_right);
}

/* surface integral evaluation
 *
 * evaluate all the riemann problems for each element.
 * THREADS: num_sides
 */
__device__ void eval_surface(double *c_left, double *c_right, 
                             double *left_riemann_rhs, double *right_riemann_rhs, 
                             double len,
                             double v1x, double v1y,
                             double v2x, double v2y,
                             double v3x, double v3y,
                             int left_idx,  int right_idx,
                             int left_side, int right_side, 
                             double nx, double ny, 
                             int n_quad1d, int n_p, int num_sides, 
                             int num_elem, double t, int idx, int alpha) {
    int i, j;
    double s, left_sum, right_sum;

    // multiply across by the i'th basis function
    for (i = 0; i < n_p; i++) {
        left_sum  = 0.;
        right_sum = 0.;
        // we're at the j'th integration point
        for (j = 0; j < n_quad1d; j++) {
            // solve the Riemann problem at this integration point
            s = eval_riemann(c_left, c_right,
                             v1x, v1y, v2x, v2y, v3x, v3y,
                             j, left_side, right_side, left_idx, right_idx,
                             n_p, n_quad1d, num_sides, t, alpha);

            // calculate the quadrature over [-1,1] for these sides
            left_sum  += (nx * flux_x(s) + ny * flux_y(s)) * w_oned[j] * 
                         basis_side[left_side * n_p * n_quad1d + i * n_quad1d + j];
            right_sum += (nx * flux_x(s) + ny * flux_y(s)) * w_oned[j] * 
                         basis_side[right_side * n_p * n_quad1d + i * n_quad1d + n_quad1d - 1 - j];
        }

        // store this side's contribution in the riemann rhs vectors
        left_riemann_rhs[i * num_sides + idx]  = -len / 2 * left_sum;
        right_riemann_rhs[i * num_sides + idx] =  len / 2 * right_sum;
    }
}
/* flux boundary evaluation 
 *
 * evaulates the flux at the boundaries by handling them somehow.
 * THREADS: num_boundary
 */

/* volume integrals
 *
 * evaluates and adds the volume integral to the rhs vector
 * THREADS: num_elem
 */
__device__ void eval_volume(double *r_c, double *quad_rhs, 
                            double x_r, double y_r,
                            double x_s, double y_s,
                            int n_quad, int n_p, int num_elem, int idx) {
    int i, j, k;
    double sum, u;

    // evaluate the volume integral for each coefficient
    for (i = 0; i < n_p; i++) {
        sum = 0.;
        for (j = 0; j < n_quad; j++) {
            // Evaluate u at the integration point.
            u = 0.;
            for (k = 0; k < n_p; k++) {
                u += r_c[k] * basis[n_quad * k + j];
            }

            // Add to the sum
            // [fx fy] * [y_s, -y_r; -x_s, x_r] * [phi_x phi_y]
            sum += (  flux_x(u) * ( basis_grad_x[n_quad * i + j] * y_s
                                   -basis_grad_y[n_quad * i + j] * y_r)
                    + flux_y(u) * (-basis_grad_x[n_quad * i + j] * x_s 
                                  + basis_grad_y[n_quad * i + j] * x_r));
        }

        // store the result
        quad_rhs[i * num_elem + idx] = sum;
    }
}

/* evaluate error
 * 
 * evaluates u at the three vertex points for output
 * THREADS: num_elem
 */
__device__ void eval_error(double *c, 
                       double v1x, double v1y,
                       double v2x, double v2y,
                       double v3x, double v3y,
                       double *Uv1, double *Uv2, double *Uv3,
                       int num_elem, int n_p, double t, int idx, int alpha) {

    int i;
    double uv1, uv2, uv3;

    // calculate values at three vertex points
    uv1 = 0.;
    uv2 = 0.;
    uv3 = 0.;
    for (i = 0; i < n_p; i++) {
        uv1 += c[i] * basis_vertex[i * 3 + 0];
        uv2 += c[i] * basis_vertex[i * 3 + 1];
        uv3 += c[i] * basis_vertex[i * 3 + 2];
    }

    // store result
    Uv1[idx] = uv1 - uexact(v1x, v1y, t, alpha);
    Uv2[idx] = uv2 - uexact(v2x, v2y, t, alpha);
    Uv3[idx] = uv3 - uexact(v3x, v3y, t, alpha);
}

/* evaluate u
 * 
 * evaluates u at the three vertex points for output
 * THREADS: num_elem
 */
__device__ void eval_u(double *c, 
                       double *Uv1, double *Uv2, double *Uv3,
                       int num_elem, int n_p, int idx) {
    int i;
    double uv1, uv2, uv3;

    // calculate values at the integration points
    uv1 = 0.;
    uv2 = 0.;
    uv3 = 0.;
    for (i = 0; i < n_p; i++) {
        uv1 += c[i] * basis_vertex[i * 3 + 0];
        uv2 += c[i] * basis_vertex[i * 3 + 1];
        uv3 += c[i] * basis_vertex[i * 3 + 2];
    }

    // store result
    Uv1[idx] = uv1;
    Uv2[idx] = uv2;
    Uv3[idx] = uv3;
}

	.file	"tmpxft_0035dae0_00000000-6_2dadvec_kernels.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"basis"
	.text
	.globl	_Z9set_basisPvi
	.type	_Z9set_basisPvi, @function
_Z9set_basisPvi:
.LFB2008:
	.cfi_startproc
	endbr64
	movslq	%esi, %rdx
	movl	$1, %r8d
	movq	%rdi, %rsi
	xorl	%ecx, %ecx
	salq	$3, %rdx
	leaq	.LC0(%rip), %rdi
	jmp	cudaMemcpyToSymbol@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z9set_basisPvi, .-_Z9set_basisPvi
	.section	.rodata.str1.1
.LC1:
	.string	"basis_grad_x"
	.text
	.globl	_Z16set_basis_grad_xPvi
	.type	_Z16set_basis_grad_xPvi, @function
_Z16set_basis_grad_xPvi:
.LFB2009:
	.cfi_startproc
	endbr64
	movslq	%esi, %rdx
	movl	$1, %r8d
	movq	%rdi, %rsi
	xorl	%ecx, %ecx
	salq	$3, %rdx
	leaq	.LC1(%rip), %rdi
	jmp	cudaMemcpyToSymbol@PLT
	.cfi_endproc
.LFE2009:
	.size	_Z16set_basis_grad_xPvi, .-_Z16set_basis_grad_xPvi
	.section	.rodata.str1.1
.LC2:
	.string	"basis_grad_y"
	.text
	.globl	_Z16set_basis_grad_yPvi
	.type	_Z16set_basis_grad_yPvi, @function
_Z16set_basis_grad_yPvi:
.LFB2010:
	.cfi_startproc
	endbr64
	movslq	%esi, %rdx
	movl	$1, %r8d
	movq	%rdi, %rsi
	xorl	%ecx, %ecx
	salq	$3, %rdx
	leaq	.LC2(%rip), %rdi
	jmp	cudaMemcpyToSymbol@PLT
	.cfi_endproc
.LFE2010:
	.size	_Z16set_basis_grad_yPvi, .-_Z16set_basis_grad_yPvi
	.section	.rodata.str1.1
.LC3:
	.string	"basis_side"
	.text
	.globl	_Z14set_basis_sidePvi
	.type	_Z14set_basis_sidePvi, @function
_Z14set_basis_sidePvi:
.LFB2011:
	.cfi_startproc
	endbr64
	movslq	%esi, %rdx
	movl	$1, %r8d
	movq	%rdi, %rsi
	xorl	%ecx, %ecx
	salq	$3, %rdx
	leaq	.LC3(%rip), %rdi
	jmp	cudaMemcpyToSymbol@PLT
	.cfi_endproc
.LFE2011:
	.size	_Z14set_basis_sidePvi, .-_Z14set_basis_sidePvi
	.section	.rodata.str1.1
.LC4:
	.string	"basis_vertex"
	.text
	.globl	_Z16set_basis_vertexPvi
	.type	_Z16set_basis_vertexPvi, @function
_Z16set_basis_vertexPvi:
.LFB2012:
	.cfi_startproc
	endbr64
	movslq	%esi, %rdx
	movl	$1, %r8d
	movq	%rdi, %rsi
	xorl	%ecx, %ecx
	salq	$3, %rdx
	leaq	.LC4(%rip), %rdi
	jmp	cudaMemcpyToSymbol@PLT
	.cfi_endproc
.LFE2012:
	.size	_Z16set_basis_vertexPvi, .-_Z16set_basis_vertexPvi
	.section	.rodata.str1.1
.LC5:
	.string	"w"
	.text
	.globl	_Z5set_wPvi
	.type	_Z5set_wPvi, @function
_Z5set_wPvi:
.LFB2013:
	.cfi_startproc
	endbr64
	movslq	%esi, %rdx
	movl	$1, %r8d
	movq	%rdi, %rsi
	xorl	%ecx, %ecx
	salq	$3, %rdx
	leaq	.LC5(%rip), %rdi
	jmp	cudaMemcpyToSymbol@PLT
	.cfi_endproc
.LFE2013:
	.size	_Z5set_wPvi, .-_Z5set_wPvi
	.section	.rodata.str1.1
.LC6:
	.string	"w_oned"
	.text
	.globl	_Z10set_w_onedPvi
	.type	_Z10set_w_onedPvi, @function
_Z10set_w_onedPvi:
.LFB2014:
	.cfi_startproc
	endbr64
	movslq	%esi, %rdx
	movl	$1, %r8d
	movq	%rdi, %rsi
	xorl	%ecx, %ecx
	salq	$3, %rdx
	leaq	.LC6(%rip), %rdi
	jmp	cudaMemcpyToSymbol@PLT
	.cfi_endproc
.LFE2014:
	.size	_Z10set_w_onedPvi, .-_Z10set_w_onedPvi
	.section	.rodata.str1.1
.LC7:
	.string	"r1"
	.text
	.globl	_Z6set_r1Pvi
	.type	_Z6set_r1Pvi, @function
_Z6set_r1Pvi:
.LFB2015:
	.cfi_startproc
	endbr64
	movslq	%esi, %rdx
	movl	$1, %r8d
	movq	%rdi, %rsi
	xorl	%ecx, %ecx
	salq	$3, %rdx
	leaq	.LC7(%rip), %rdi
	jmp	cudaMemcpyToSymbol@PLT
	.cfi_endproc
.LFE2015:
	.size	_Z6set_r1Pvi, .-_Z6set_r1Pvi
	.section	.rodata.str1.1
.LC8:
	.string	"r2"
	.text
	.globl	_Z6set_r2Pvi
	.type	_Z6set_r2Pvi, @function
_Z6set_r2Pvi:
.LFB2016:
	.cfi_startproc
	endbr64
	movslq	%esi, %rdx
	movl	$1, %r8d
	movq	%rdi, %rsi
	xorl	%ecx, %ecx
	salq	$3, %rdx
	leaq	.LC8(%rip), %rdi
	jmp	cudaMemcpyToSymbol@PLT
	.cfi_endproc
.LFE2016:
	.size	_Z6set_r2Pvi, .-_Z6set_r2Pvi
	.section	.rodata.str1.1
.LC9:
	.string	"r_oned"
	.text
	.globl	_Z10set_r_onedPvi
	.type	_Z10set_r_onedPvi, @function
_Z10set_r_onedPvi:
.LFB2017:
	.cfi_startproc
	endbr64
	movslq	%esi, %rdx
	movl	$1, %r8d
	movq	%rdi, %rsi
	xorl	%ecx, %ecx
	salq	$3, %rdx
	leaq	.LC9(%rip), %rdi
	jmp	cudaMemcpyToSymbol@PLT
	.cfi_endproc
.LFE2017:
	.size	_Z10set_r_onedPvi, .-_Z10set_r_onedPvi
	.globl	_Z6flux_xd
	.type	_Z6flux_xd, @function
_Z6flux_xd:
.LFB2018:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2018:
	.size	_Z6flux_xd, .-_Z6flux_xd
	.globl	_Z6flux_yd
	.type	_Z6flux_yd, @function
_Z6flux_yd:
.LFB2191:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z6flux_xd
	.cfi_endproc
.LFE2191:
	.size	_Z6flux_yd, .-_Z6flux_yd
	.globl	_Z7riemanndd
	.type	_Z7riemanndd, @function
_Z7riemanndd:
.LFB2020:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2020:
	.size	_Z7riemanndd, .-_Z7riemanndd
	.globl	_Z2u0ddi
	.type	_Z2u0ddi, @function
_Z2u0ddi:
.LFB2021:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2021:
	.size	_Z2u0ddi, .-_Z2u0ddi
	.globl	_Z14boundary_exactdddi
	.type	_Z14boundary_exactdddi, @function
_Z14boundary_exactdddi:
.LFB2022:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2022:
	.size	_Z14boundary_exactdddi, .-_Z14boundary_exactdddi
	.globl	_Z6uexactdddi
	.type	_Z6uexactdddi, @function
_Z6uexactdddi:
.LFB2193:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2193:
	.size	_Z6uexactdddi, .-_Z6uexactdddi
	.globl	_Z12eval_riemannPdS_ddddddiiiiiiiidi
	.type	_Z12eval_riemannPdS_ddddddiiiiiiiidi, @function
_Z12eval_riemannPdS_ddddddiiiiiiiidi:
.LFB2024:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2024:
	.size	_Z12eval_riemannPdS_ddddddiiiiiiiidi, .-_Z12eval_riemannPdS_ddddddiiiiiiiidi
	.globl	_Z12eval_surfacePdS_S_S_dddddddiiiiddiiiidii
	.type	_Z12eval_surfacePdS_S_S_dddddddiiiiddiiiidii, @function
_Z12eval_surfacePdS_S_S_dddddddiiiiddiiiidii:
.LFB2025:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2025:
	.size	_Z12eval_surfacePdS_S_S_dddddddiiiiddiiiidii, .-_Z12eval_surfacePdS_S_S_dddddddiiiiddiiiidii
	.globl	_Z11eval_volumePdS_ddddiiii
	.type	_Z11eval_volumePdS_ddddiiii, @function
_Z11eval_volumePdS_ddddiiii:
.LFB2026:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2026:
	.size	_Z11eval_volumePdS_ddddiiii, .-_Z11eval_volumePdS_ddddiiii
	.globl	_Z10eval_errorPdddddddS_S_S_iidii
	.type	_Z10eval_errorPdddddddS_S_S_iidii, @function
_Z10eval_errorPdddddddS_S_S_iidii:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z10eval_errorPdddddddS_S_S_iidii, .-_Z10eval_errorPdddddddS_S_S_iidii
	.globl	_Z6eval_uPdS_S_S_iii
	.type	_Z6eval_uPdS_S_S_iii, @function
_Z6eval_uPdS_S_S_iii:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z6eval_uPdS_S_S_iii, .-_Z6eval_uPdS_S_S_iii
	.globl	_Z53__device_stub__Z15init_conditionsPdS_S_S_S_S_S_S_iiiiPdS_S_S_S_S_S_S_iiii
	.type	_Z53__device_stub__Z15init_conditionsPdS_S_S_S_S_S_S_iiiiPdS_S_S_S_S_S_S_iiii, @function
_Z53__device_stub__Z15init_conditionsPdS_S_S_S_S_S_S_iiiiPdS_S_S_S_S_S_S_iiii:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	256(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rax, 8(%rsp)
	movq	264(%rsp), %rax
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	%rsp, %rax
	movq	%rax, 192(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	296(%rsp), %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	pushq	80(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z15init_conditionsPdS_S_S_S_S_S_S_iiii(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 272
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L34:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z53__device_stub__Z15init_conditionsPdS_S_S_S_S_S_S_iiiiPdS_S_S_S_S_S_S_iiii, .-_Z53__device_stub__Z15init_conditionsPdS_S_S_S_S_S_S_iiiiPdS_S_S_S_S_S_S_iiii
	.globl	_Z15init_conditionsPdS_S_S_S_S_S_S_iiii
	.type	_Z15init_conditionsPdS_S_S_S_S_S_S_iiii, @function
_Z15init_conditionsPdS_S_S_S_S_S_S_iiii:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z15init_conditionsPdS_S_S_S_S_S_S_iiiiPdS_S_S_S_S_S_S_iiii
	.cfi_endproc
.LFE2054:
	.size	_Z15init_conditionsPdS_S_S_S_S_S_S_iiii, .-_Z15init_conditionsPdS_S_S_S_S_S_S_iiii
	.globl	_Z35__device_stub__Z12min_jacobianPdS_iPdS_i
	.type	_Z35__device_stub__Z12min_jacobianPdS_iPdS_i, @function
_Z35__device_stub__Z12min_jacobianPdS_iPdS_i:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L40
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z12min_jacobianPdS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L40:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L42
	call	__stack_chk_fail@PLT
.L42:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z35__device_stub__Z12min_jacobianPdS_iPdS_i, .-_Z35__device_stub__Z12min_jacobianPdS_iPdS_i
	.globl	_Z12min_jacobianPdS_i
	.type	_Z12min_jacobianPdS_i, @function
_Z12min_jacobianPdS_i:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z12min_jacobianPdS_iPdS_i
	.cfi_endproc
.LFE2056:
	.size	_Z12min_jacobianPdS_i, .-_Z12min_jacobianPdS_i
	.globl	_Z47__device_stub__Z18preval_side_lengthPdS_S_S_S_iPdS_S_S_S_i
	.type	_Z47__device_stub__Z18preval_side_lengthPdS_S_S_S_iPdS_S_S_S_i, @function
_Z47__device_stub__Z18preval_side_lengthPdS_S_S_S_iPdS_S_S_S_i:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L45
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z18preval_side_lengthPdS_S_S_S_i(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L45:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L47
	call	__stack_chk_fail@PLT
.L47:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z47__device_stub__Z18preval_side_lengthPdS_S_S_S_iPdS_S_S_S_i, .-_Z47__device_stub__Z18preval_side_lengthPdS_S_S_S_iPdS_S_S_S_i
	.globl	_Z18preval_side_lengthPdS_S_S_S_i
	.type	_Z18preval_side_lengthPdS_S_S_S_i, @function
_Z18preval_side_lengthPdS_S_S_S_i:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z18preval_side_lengthPdS_S_S_S_iPdS_S_S_S_i
	.cfi_endproc
.LFE2058:
	.size	_Z18preval_side_lengthPdS_S_S_S_i, .-_Z18preval_side_lengthPdS_S_S_S_i
	.globl	_Z48__device_stub__Z15preval_jacobianPdS_S_S_S_S_S_iPdS_S_S_S_S_S_i
	.type	_Z48__device_stub__Z15preval_jacobianPdS_S_S_S_S_S_iPdS_S_S_S_S_S_i, @function
_Z48__device_stub__Z15preval_jacobianPdS_S_S_S_S_S_iPdS_S_S_S_S_S_i:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	224(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L50
	pushq	80(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z15preval_jacobianPdS_S_S_S_S_S_i(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 240
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L50:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L52
	call	__stack_chk_fail@PLT
.L52:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z48__device_stub__Z15preval_jacobianPdS_S_S_S_S_S_iPdS_S_S_S_S_S_i, .-_Z48__device_stub__Z15preval_jacobianPdS_S_S_S_S_S_iPdS_S_S_S_S_S_i
	.globl	_Z15preval_jacobianPdS_S_S_S_S_S_i
	.type	_Z15preval_jacobianPdS_S_S_S_S_S_i, @function
_Z15preval_jacobianPdS_S_S_S_S_S_i:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z15preval_jacobianPdS_S_S_S_S_S_iPdS_S_S_S_S_S_i
	.cfi_endproc
.LFE2060:
	.size	_Z15preval_jacobianPdS_S_S_S_S_S_i, .-_Z15preval_jacobianPdS_S_S_S_S_S_i
	.globl	_Z59__device_stub__Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_PiiPdS_S_S_S_S_S_S_S_S_S_S_Pii
	.type	_Z59__device_stub__Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_PiiPdS_S_S_S_S_S_S_S_S_S_S_Pii, @function
_Z59__device_stub__Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_PiiPdS_S_S_S_S_S_S_S_S_S_S_Pii:
.LFB2061:
	.cfi_startproc
	endbr64
	subq	$312, %rsp
	.cfi_def_cfa_offset 320
	movq	320(%rsp), %rax
	movq	%rdi, 104(%rsp)
	leaq	136(%rsp), %rdi
	movq	%rsi, 96(%rsp)
	leaq	148(%rsp), %rsi
	movq	%rax, 56(%rsp)
	movq	328(%rsp), %rax
	movq	%rdx, 88(%rsp)
	leaq	120(%rsp), %rdx
	movq	%rax, 48(%rsp)
	movq	336(%rsp), %rax
	movq	%rcx, 80(%rsp)
	leaq	128(%rsp), %rcx
	movq	%rax, 40(%rsp)
	movq	344(%rsp), %rax
	movq	%r8, 72(%rsp)
	movq	%rax, 32(%rsp)
	movq	352(%rsp), %rax
	movq	%r9, 64(%rsp)
	movq	%rax, 24(%rsp)
	movq	360(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	368(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 296(%rsp)
	xorl	%eax, %eax
	leaq	104(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	376(%rsp), %rax
	movq	%rax, 288(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 136(%rsp)
	movl	$1, 144(%rsp)
	movq	%rax, 148(%rsp)
	movl	$1, 156(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L55
	pushq	128(%rsp)
	.cfi_def_cfa_offset 328
	leaq	_Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii(%rip), %rdi
	pushq	128(%rsp)
	.cfi_def_cfa_offset 336
	movq	164(%rsp), %rcx
	movl	172(%rsp), %r8d
	movq	152(%rsp), %rsi
	movl	160(%rsp), %edx
	leaq	200(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 328
	popq	%rdx
	.cfi_def_cfa_offset 320
.L55:
	movq	296(%rsp), %rax
	subq	%fs:40, %rax
	je	.L57
	call	__stack_chk_fail@PLT
.L57:
	addq	$312, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2061:
	.size	_Z59__device_stub__Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_PiiPdS_S_S_S_S_S_S_S_S_S_S_Pii, .-_Z59__device_stub__Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_PiiPdS_S_S_S_S_S_S_S_S_S_S_Pii
	.globl	_Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii
	.type	_Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii, @function
_Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii:
.LFB2062:
	.cfi_startproc
	endbr64
	jmp	_Z59__device_stub__Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_PiiPdS_S_S_S_S_S_S_S_S_S_S_Pii
	.cfi_endproc
.LFE2062:
	.size	_Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii, .-_Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii
	.globl	_Z64__device_stub__Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_iPdS_S_S_S_S_S_S_PiS0_i
	.type	_Z64__device_stub__Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_iPdS_S_S_S_S_S_S_PiS0_i, @function
_Z64__device_stub__Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_iPdS_S_S_S_S_S_S_PiS0_i:
.LFB2063:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	256(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	96(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	264(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rax, 16(%rsp)
	movq	272(%rsp), %rax
	movq	%rcx, 48(%rsp)
	leaq	88(%rsp), %rcx
	movq	%rax, 8(%rsp)
	movq	280(%rsp), %rax
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 104(%rsp)
	movq	%rax, 144(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 208(%rsp)
	movq	%rsp, %rax
	movq	%rax, 216(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L60
	pushq	88(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 272
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L60:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L62
	call	__stack_chk_fail@PLT
.L62:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2063:
	.size	_Z64__device_stub__Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_iPdS_S_S_S_S_S_S_PiS0_i, .-_Z64__device_stub__Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_iPdS_S_S_S_S_S_S_PiS0_i
	.globl	_Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i
	.type	_Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i, @function
_Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i:
.LFB2064:
	.cfi_startproc
	endbr64
	jmp	_Z64__device_stub__Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_iPdS_S_S_S_S_S_S_PiS0_i
	.cfi_endproc
.LFE2064:
	.size	_Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i, .-_Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i
	.globl	_Z54__device_stub__Z15preval_partialsPdS_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_i
	.type	_Z54__device_stub__Z15preval_partialsPdS_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_i, @function
_Z54__device_stub__Z15preval_partialsPdS_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_i:
.LFB2065:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	256(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	96(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	264(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rax, 16(%rsp)
	movq	272(%rsp), %rax
	movq	%rcx, 48(%rsp)
	leaq	88(%rsp), %rcx
	movq	%rax, 8(%rsp)
	movq	280(%rsp), %rax
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 104(%rsp)
	movq	%rax, 144(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 208(%rsp)
	movq	%rsp, %rax
	movq	%rax, 216(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L65
	pushq	88(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 272
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L65:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L67
	call	__stack_chk_fail@PLT
.L67:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2065:
	.size	_Z54__device_stub__Z15preval_partialsPdS_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_i, .-_Z54__device_stub__Z15preval_partialsPdS_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_i
	.globl	_Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i
	.type	_Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i, @function
_Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i:
.LFB2066:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__Z15preval_partialsPdS_S_S_S_S_S_S_S_S_iPdS_S_S_S_S_S_S_S_S_i
	.cfi_endproc
.LFE2066:
	.size	_Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i, .-_Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i
	.section	.rodata.str1.1
.LC10:
	.string	"_Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i"
.LC11:
	.string	"_Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i"
.LC12:
	.string	"_Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii"
.LC13:
	.string	"_Z15preval_jacobianPdS_S_S_S_S_S_i"
.LC14:
	.string	"_Z18preval_side_lengthPdS_S_S_S_i"
.LC15:
	.string	"_Z12min_jacobianPdS_i"
.LC16:
	.string	"_Z15init_conditionsPdS_S_S_S_S_S_S_iiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2068:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z15preval_jacobianPdS_S_S_S_S_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC14(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z18preval_side_lengthPdS_S_S_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC15(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z12min_jacobianPdS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC16(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z15init_conditionsPdS_S_S_S_S_S_S_iiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC0(%rip), %rdx
	movl	$16384, %r9d
	leaq	_ZL5basis(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$16384, %r9d
	leaq	_ZL12basis_grad_x(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$16384, %r9d
	leaq	_ZL12basis_grad_y(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8192, %r9d
	leaq	_ZL10basis_side(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2048, %r9d
	leaq	_ZL12basis_vertex(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$256, %r9d
	leaq	_ZL1w(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$128, %r9d
	leaq	_ZL6w_oned(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$256, %r9d
	leaq	_ZL2r1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$256, %r9d
	leaq	_ZL2r2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$256, %r9d
	movq	%rdx, %rcx
	leaq	_ZL6r_oned(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2068:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	d_right_elem
	.bss
	.align 8
	.type	d_right_elem, @object
	.size	d_right_elem, 8
d_right_elem:
	.zero	8
	.globl	d_left_elem
	.align 8
	.type	d_left_elem, @object
	.size	d_left_elem, 8
d_left_elem:
	.zero	8
	.globl	d_Ny
	.align 8
	.type	d_Ny, @object
	.size	d_Ny, 8
d_Ny:
	.zero	8
	.globl	d_Nx
	.align 8
	.type	d_Nx, @object
	.size	d_Nx, 8
d_Nx:
	.zero	8
	.globl	d_Uv3
	.align 8
	.type	d_Uv3, @object
	.size	d_Uv3, 8
d_Uv3:
	.zero	8
	.globl	d_Uv2
	.align 8
	.type	d_Uv2, @object
	.size	d_Uv2, 8
d_Uv2:
	.zero	8
	.globl	d_Uv1
	.align 8
	.type	d_Uv1, @object
	.size	d_Uv1, 8
d_Uv1:
	.zero	8
	.globl	d_V3y
	.align 8
	.type	d_V3y, @object
	.size	d_V3y, 8
d_V3y:
	.zero	8
	.globl	d_V3x
	.align 8
	.type	d_V3x, @object
	.size	d_V3x, 8
d_V3x:
	.zero	8
	.globl	d_V2y
	.align 8
	.type	d_V2y, @object
	.size	d_V2y, 8
d_V2y:
	.zero	8
	.globl	d_V2x
	.align 8
	.type	d_V2x, @object
	.size	d_V2x, 8
d_V2x:
	.zero	8
	.globl	d_V1y
	.align 8
	.type	d_V1y, @object
	.size	d_V1y, 8
d_V1y:
	.zero	8
	.globl	d_V1x
	.align 8
	.type	d_V1x, @object
	.size	d_V1x, 8
d_V1x:
	.zero	8
	.globl	d_elem_s3
	.align 8
	.type	d_elem_s3, @object
	.size	d_elem_s3, 8
d_elem_s3:
	.zero	8
	.globl	d_elem_s2
	.align 8
	.type	d_elem_s2, @object
	.size	d_elem_s2, 8
d_elem_s2:
	.zero	8
	.globl	d_elem_s1
	.align 8
	.type	d_elem_s1, @object
	.size	d_elem_s1, 8
d_elem_s1:
	.zero	8
	.globl	d_ys
	.align 8
	.type	d_ys, @object
	.size	d_ys, 8
d_ys:
	.zero	8
	.globl	d_xs
	.align 8
	.type	d_xs, @object
	.size	d_xs, 8
d_xs:
	.zero	8
	.globl	d_yr
	.align 8
	.type	d_yr, @object
	.size	d_yr, 8
d_yr:
	.zero	8
	.globl	d_xr
	.align 8
	.type	d_xr, @object
	.size	d_xr, 8
d_xr:
	.zero	8
	.globl	d_s_V2y
	.align 8
	.type	d_s_V2y, @object
	.size	d_s_V2y, 8
d_s_V2y:
	.zero	8
	.globl	d_s_V2x
	.align 8
	.type	d_s_V2x, @object
	.size	d_s_V2x, 8
d_s_V2x:
	.zero	8
	.globl	d_s_V1y
	.align 8
	.type	d_s_V1y, @object
	.size	d_s_V1y, 8
d_s_V1y:
	.zero	8
	.globl	d_s_V1x
	.align 8
	.type	d_s_V1x, @object
	.size	d_s_V1x, 8
d_s_V1x:
	.zero	8
	.globl	d_s_length
	.align 8
	.type	d_s_length, @object
	.size	d_s_length, 8
d_s_length:
	.zero	8
	.globl	d_min_J
	.align 8
	.type	d_min_J, @object
	.size	d_min_J, 8
d_min_J:
	.zero	8
	.globl	d_J
	.align 8
	.type	d_J, @object
	.size	d_J, 8
d_J:
	.zero	8
	.globl	d_right_side_number
	.align 8
	.type	d_right_side_number, @object
	.size	d_right_side_number, 8
d_right_side_number:
	.zero	8
	.globl	d_left_side_number
	.align 8
	.type	d_left_side_number, @object
	.size	d_left_side_number, 8
d_left_side_number:
	.zero	8
	.local	_ZL6r_oned
	.comm	_ZL6r_oned,256,32
	.local	_ZL2r2
	.comm	_ZL2r2,256,32
	.local	_ZL2r1
	.comm	_ZL2r1,256,32
	.local	_ZL6w_oned
	.comm	_ZL6w_oned,128,32
	.local	_ZL1w
	.comm	_ZL1w,256,32
	.local	_ZL12basis_vertex
	.comm	_ZL12basis_vertex,2048,32
	.local	_ZL10basis_side
	.comm	_ZL10basis_side,8192,32
	.local	_ZL12basis_grad_y
	.comm	_ZL12basis_grad_y,16384,32
	.local	_ZL12basis_grad_x
	.comm	_ZL12basis_grad_x,16384,32
	.local	_ZL5basis
	.comm	_ZL5basis,16384,32
	.globl	d_k4
	.align 8
	.type	d_k4, @object
	.size	d_k4, 8
d_k4:
	.zero	8
	.globl	d_k3
	.align 8
	.type	d_k3, @object
	.size	d_k3, 8
d_k3:
	.zero	8
	.globl	d_k2
	.align 8
	.type	d_k2, @object
	.size	d_k2, 8
d_k2:
	.zero	8
	.globl	d_k1
	.align 8
	.type	d_k1, @object
	.size	d_k1, 8
d_k1:
	.zero	8
	.globl	d_kstar
	.align 8
	.type	d_kstar, @object
	.size	d_kstar, 8
d_kstar:
	.zero	8
	.globl	d_right_riemann_rhs
	.align 8
	.type	d_right_riemann_rhs, @object
	.size	d_right_riemann_rhs, 8
d_right_riemann_rhs:
	.zero	8
	.globl	d_left_riemann_rhs
	.align 8
	.type	d_left_riemann_rhs, @object
	.size	d_left_riemann_rhs, 8
d_left_riemann_rhs:
	.zero	8
	.globl	d_quad_rhs
	.align 8
	.type	d_quad_rhs, @object
	.size	d_quad_rhs, 8
d_quad_rhs:
	.zero	8
	.globl	d_c
	.align 8
	.type	d_c, @object
	.size	d_c, 8
d_c:
	.zero	8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
/* 2dadvec_kernels.cu
 *
 * This file contains the kernels for the 2D advection DG method.
 * We use K = number of elements
 * and    H = number of sides
 */

#define PI 3.14159

/***********************
 *
 * DEVICE VARIABLES
 *
 ***********************/
/* These are always prefixed with d_ for "device" */
double *d_c;           // holds coefficients for each element
double *d_quad_rhs;    // the right hand side containing the quadrature contributions
double *d_left_riemann_rhs;  // the right hand side containing the left riemann contributions
double *d_right_riemann_rhs; // the right hand side containing the right riemann contributions

// runge kutta variables
double *d_kstar;
double *d_k1;
double *d_k2;
double *d_k3;
double *d_k4;

// precomputed basis functions 
// TODO: maybe making these 2^n makes sure the offsets are cached more efficiently? who knows...
// precomputed basis functions ordered like so
//
// [phi_1(r1, s1), phi_1(r2, s2), ... , phi_1(r_nq, s_nq)   ]
// [phi_2(r1, s1), phi_2(r2, s2), ... , phi_2(r_nq, s_nq)   ]
// [   .               .           .            .           ]
// [   .               .           .            .           ]
// [   .               .           .            .           ]
// [phi_np(r1, s1), phi_np(r2, s2), ... , phi_np(r_nq, s_nq)]
//
__device__ __constant__ double basis[2048];
// note: these are multiplied by the weights
__device__ __constant__ double basis_grad_x[2048]; 
__device__ __constant__ double basis_grad_y[2048]; 

// precomputed basis functions evaluated along the sides. ordered
// similarly to basis and basis_grad_{x,y} but with one "matrix" for each side
// starting with side 0. to get to each side, offset with:
//      side_number * n_p * num_quad1d.
__device__ __constant__ double basis_side[1024];
__device__ __constant__ double basis_vertex[256];

// weights for 2d and 1d quadrature rules
__device__ __constant__ double w[32];
__device__ __constant__ double w_oned[16];

__device__ __constant__ double r1[32];
__device__ __constant__ double r2[32];
__device__ __constant__ double r_oned[32];

void set_basis(void *value, int size) {
    hipMemcpyToSymbol(HIP_SYMBOL("basis"), value, size * sizeof(double));
}
void set_basis_grad_x(void *value, int size) {
    hipMemcpyToSymbol(HIP_SYMBOL("basis_grad_x"), value, size * sizeof(double));
}
void set_basis_grad_y(void *value, int size) {
    hipMemcpyToSymbol(HIP_SYMBOL("basis_grad_y"), value, size * sizeof(double));
}
void set_basis_side(void *value, int size) {
    hipMemcpyToSymbol(HIP_SYMBOL("basis_side"), value, size * sizeof(double));
}
void set_basis_vertex(void *value, int size) {
    hipMemcpyToSymbol(HIP_SYMBOL("basis_vertex"), value, size * sizeof(double));
}
void set_w(void *value, int size) {
    hipMemcpyToSymbol(HIP_SYMBOL("w"), value, size * sizeof(double));
}
void set_w_oned(void *value, int size) {
    hipMemcpyToSymbol(HIP_SYMBOL("w_oned"), value, size * sizeof(double));
}
void set_r1(void *value, int size) {
    hipMemcpyToSymbol(HIP_SYMBOL("r1"), value, size * sizeof(double));
}
void set_r2(void *value, int size) {
    hipMemcpyToSymbol(HIP_SYMBOL("r2"), value, size * sizeof(double));
}
void set_r_oned(void *value, int size) {
    hipMemcpyToSymbol(HIP_SYMBOL("r_oned"), value, size * sizeof(double));
}

// tells which side (1, 2, or 3) to evaluate this boundary integral over
int *d_left_side_number;
int *d_right_side_number;

double *d_J;        // jacobian determinant 
double *d_min_J;      // for the min sized jacobian
double *d_s_length; // length of sides

// the num_elem values of the x and y coordinates for the two vertices defining a side
// TODO: can i delete these after the lengths are precomputed?
//       maybe these should be in texture memory?
double *d_s_V1x;
double *d_s_V1y;
double *d_s_V2x;
double *d_s_V2y;

// the num_elem values of the x and y partials
double *d_xr;
double *d_yr;
double *d_xs;
double *d_ys;

// the K indices of the sides for each element ranged 0->H-1
int *d_elem_s1;
int *d_elem_s2;
int *d_elem_s3;

// vertex x and y coordinates on the mesh which define an element
// TODO: can i delete these after the jacobians are precomputed?
//       maybe these should be in texture memory?
double *d_V1x;
double *d_V1y;
double *d_V2x;
double *d_V2y;
double *d_V3x;
double *d_V3y;

// stores computed values at three vertices
double *d_Uv1;
double *d_Uv2;
double *d_Uv3;

// normal vectors for the sides
double *d_Nx;
double *d_Ny;

// index lists for sides
int *d_left_elem;  // index of left  element for side idx
int *d_right_elem; // index of right element for side idx

/***********************
 *
 * DEVICE FUNCTIONS
 *
 ***********************/

/* flux function
 *
 * evaluates the flux f(u) at the point u.
 */
__device__ double flux_x(double u) {
    return u;
}
__device__ double flux_y(double u) {
    return u;
}

/* riemann solver
 *
 * evaluates the riemann problem over the boundary using Gaussian quadrature
 * with Legendre polynomials as basis functions.
 */
__device__ double riemann(double u_left, double u_right) {
    return 0.5 * (u_left + u_right);
}

/***********************
 *
 * INITIAL CONDITIONS
 *
 ***********************/

/* initial condition function
 *
 * returns the value of the intial condition at point x
 */
__device__ double u0(double x, double y, int alpha) {
    return x + y;//pow(x - y, alpha);
}

/* boundary exact
 *
 * returns the exact boundary conditions
 */
__device__ double boundary_exact(double x, double y, double t, int alpha) {
    return x - 2*t + y;//u0(x, y, alpha);
}

/* u exact
 *
 * returns the exact value of u for error measurement.
 */
__device__ double uexact(double x, double y, double t, int alpha) {
    return u0(x, y, alpha);
}

/* initial conditions
 *
 * computes the coefficients for the initial conditions
 * THREADS: num_elem
 */
__global__ void init_conditions(double *c, double *J,
                                double *V1x, double *V1y,
                                double *V2x, double *V2y,
                                double *V3x, double *V3y,
                                int n_quad, int n_p, int num_elem, int alpha) {
    int idx = blockDim.x * blockIdx.x + threadIdx.x;
    int i, j;
    double x, y, u;

    if (idx < num_elem) {
        for (i = 0; i < n_p; i++) {
            u = 0.;
            // perform quadrature
            for (j = 0; j < n_quad; j++) {
                // map from the canonical element to the actual point on the mesh
                // x = x2 * r + x3 * s + x1 * (1 - r - s)
                x = r1[j] * V2x[idx] + r2[j] * V3x[idx] + (1 - r1[j] - r2[j]) * V1x[idx];
                y = r1[j] * V2y[idx] + r2[j] * V3y[idx] + (1 - r1[j] - r2[j]) * V1y[idx];

                // evaluate u there
                u += w[j] * u0(x, y, alpha) * basis[i * n_quad + j];
            }
            c[i * num_elem + idx] = u;
        } 
    }
}

/* find min jacobian
 *
 * returns the min jacobian inside of min_J. 
 * each block computes the min jacobian inside of that block and stores it in the
 * blockIdx.x spot of the shared min_J variable.
 * NOTE: this is fixed for 256 threads.
 */
__global__ void min_jacobian(double *J, double *min_J, int num_elem) {
    int idx = blockDim.x * blockIdx.x + threadIdx.x;
    int tid = threadIdx.x;
    int i   = blockDim.x * (blockIdx.x * 256 * 2) + threadIdx.x;

    __shared__ double s_min[256];

    if (idx < num_elem) {
        // set all of min to J[idx] initially
        s_min[tid] = J[idx];
        __syncthreads();

        // test a few
        while (i < num_elem) {
            s_min[tid] = (s_min[tid] < J[i]) ? s_min[tid] : J[i];
            s_min[tid] = (s_min[tid] < J[i + 256]) ? s_min[tid] : J[i];
            i += gridDim.x * 256 * 2;
            __syncthreads();
        }

        // first half of the warps
        __syncthreads();
        if (tid < 128) {
            s_min[tid] = (s_min[tid] < s_min[tid + 128]) ? s_min[tid] : s_min[tid + 128];
        }

        // first and second warps
        __syncthreads();
        if (tid < 64) {
            s_min[tid] = (s_min[tid] < s_min[tid + 64]) ? s_min[tid] : s_min[tid + 64];
        }

        // unroll last warp
        __syncthreads();
        if (tid < 32) {
            if (blockDim.x >= 64) {
                s_min[tid] = (s_min[tid] < s_min[tid + 32]) ? s_min[tid] : s_min[tid + 32];
            }
            if (blockDim.x >= 32) {
                s_min[tid] = (s_min[tid] < s_min[tid + 16]) ? s_min[tid] : s_min[tid + 16];
            }
            if (blockDim.x >= 16) {
                s_min[tid] = (s_min[tid] < s_min[tid + 8]) ? s_min[tid] : s_min[tid + 8];
            }
            if (blockDim.x >= 8) {
                s_min[tid] = (s_min[tid] < s_min[tid + 4]) ? s_min[tid] : s_min[tid + 4];
            }
            if (blockDim.x >= 4) {
                s_min[tid] = (s_min[tid] < s_min[tid + 2]) ? s_min[tid] : s_min[tid + 2];
            }
            if (blockDim.x >= 2) {
                s_min[tid] = (s_min[tid] < s_min[tid + 1]) ? s_min[tid] : s_min[tid + 1];
            }
        }

        __syncthreads();
        if (tid == 0) {
            min_J[blockIdx.x] = s_min[0];
        }
    }
}

/***********************
 *
 * PRECOMPUTING
 *
 ***********************/

/* side length computer
 *
 * precomputes the length of each side.
 * THREADS: num_sides
 */ 
__global__ void preval_side_length(double *s_length, 
                              double *s_V1x, double *s_V1y, 
                              double *s_V2x, double *s_V2y,
                              int num_sides) {
    int idx = blockDim.x * blockIdx.x + threadIdx.x;

    if (idx < num_sides) {
        // compute and store the length of the side
        s_length[idx] = sqrtf(pow(s_V1x[idx] - s_V2x[idx],2) + pow(s_V1y[idx] - s_V2y[idx],2));
    }
}

/* jacobian computing
 *
 * precomputes the jacobian determinant for each element.
 * THREADS: num_elem
 */
__global__ void preval_jacobian(double *J, 
                           double *V1x, double *V1y, 
                           double *V2x, double *V2y, 
                           double *V3x, double *V3y,
                           int num_elem) {
    int idx = blockDim.x * blockIdx.x + threadIdx.x;

    if (idx < num_elem) {
        double x1, y1, x2, y2, x3, y3;

        // read vertex points
        x1 = V1x[idx];
        y1 = V1y[idx];
        x2 = V2x[idx];
        y2 = V2y[idx];
        x3 = V3x[idx];
        y3 = V3y[idx];

        // calculate jacobian determinant
        // x = x2 * r + x3 * s + x1 * (1 - r - s)
        J[idx] = (x2 - x1) * (y3 - y1) - (x3 - x1) * (y2 - y1);
    }
}

/* evaluate normal vectors
 *
 * computes the normal vectors for each element along each side.
 * THREADS: num_sides
 *
 */
__global__ void preval_normals(double *Nx, double *Ny, 
                          double *s_V1x, double *s_V1y, 
                          double *s_V2x, double *s_V2y,
                          double *V1x, double *V1y, 
                          double *V2x, double *V2y, 
                          double *V3x, double *V3y,
                          int *left_side_number, int num_sides) {

    int idx = blockDim.x * blockIdx.x + threadIdx.x;

    if (idx < num_sides) {
        double x, y, length;
        double sv1x, sv1y, sv2x, sv2y;
    
        sv1x = s_V1x[idx];
        sv1y = s_V1y[idx];
        sv2x = s_V2x[idx];
        sv2y = s_V2y[idx];
    
        // lengths of the vector components
        x = sv2x - sv1x;
        y = sv2y - sv1y;
    
        // normalize
        length = sqrtf(pow(x, 2) + pow(y, 2));

        // store the result
        Nx[idx] = -y / length;
        Ny[idx] =  x / length;
    }
}

__global__ void preval_normals_direction(double *Nx, double *Ny, 
                          double *V1x, double *V1y, 
                          double *V2x, double *V2y, 
                          double *V3x, double *V3y,
                          int *left_elem, int *left_side_number, int num_sides) {

    int idx = blockDim.x * blockIdx.x + threadIdx.x;

    if (idx < num_sides) {
        double new_x, new_y, dot;
        double initial_x, initial_y, target_x, target_y;
        double x, y;
        int left_idx, side;

        // get left side's vertices
        left_idx = left_elem[idx];
        side     = left_side_number[idx];

        // get the normal vector
        x = Nx[idx];
        y = Ny[idx];
    
        // make it point the correct direction by learning the third vertex point
        switch (side) {
            case 0: 
                target_x = V3x[left_idx];
                target_y = V3y[left_idx];
                initial_x = (V1x[left_idx] + V2x[left_idx]) / 2.;
                initial_y = (V1y[left_idx] + V2y[left_idx]) / 2.;
                break;
            case 1:
                target_x = V1x[left_idx];
                target_y = V1y[left_idx];
                initial_x = (V2x[left_idx] + V3x[left_idx]) / 2.;
                initial_y = (V2y[left_idx] + V3y[left_idx]) / 2.;
                break;
            case 2:
                target_x = V2x[left_idx];
                target_y = V2y[left_idx];
                initial_x = (V1x[left_idx] + V3x[left_idx]) / 2.;
                initial_y = (V1y[left_idx] + V3y[left_idx]) / 2.;
                break;
        }

        // create the vector pointing towards the third vertex point
        new_x = target_x - initial_x;
        new_y = target_y - initial_y;

        // find the dot product between the normal and new vectors
        dot = x * new_x + y * new_y;
        
        if (dot > 0) {
            Nx[idx] *= -1;
            Ny[idx] *= -1;
        }
    }
}

__global__ void preval_partials(double *V1x, double *V1y,
                                double *V2x, double *V2y,
                                double *V3x, double *V3y,
                                double *xr,  double *yr,
                                double *xs,  double *ys, int num_elem) {
    int idx = blockDim.x * blockIdx.x + threadIdx.x;
    if (idx < num_elem) {
        // evaulate the jacobians of the mappings for the chain rule
        // x = x2 * r + x3 * s + x1 * (1 - r - s)
        xr[idx] = V2x[idx] - V1x[idx];
        yr[idx] = V2y[idx] - V1y[idx];
        xs[idx] = V3x[idx] - V1x[idx];
        ys[idx] = V3y[idx] - V1y[idx];
    }
}

/***********************
 *
 * MAIN FUNCTIONS
 *
 ***********************/

/* riemann evaluation
 *
 * device function to solve the riemann problem.
 */
__device__ double eval_riemann(double *c_left, double *c_right,
                              double v1x, double v1y,
                              double v2x, double v2y,
                              double v3x, double v3y,
                              int j, // j, as usual, is the index of the integration point
                              int left_side, int right_side,
                              int left_idx, int right_idx,
                              int n_p, int n_quad1d,
                              int num_sides, double t, int alpha) {

    double u_left, u_right;
    int i;

    u_left  = 0.;
    u_right = 0.;

    for (i = 0; i < n_p; i++) {
        u_left  += c_left[i] * basis_side[left_side * n_p * n_quad1d + i * n_quad1d + j];
    }

    // make all threads in the first warps be boundary sides
    if (right_idx == -1) {
        double r1_eval, r2_eval;
        double x, y;

        // we need the mapping back to the grid space
        switch (left_side) {
            case 0: 
                r1_eval = 0.5 + 0.5 * r_oned[j];
                r2_eval = 0.;
                break;
            case 1: 
                r1_eval = (1. - r_oned[j]) / 2.;
                r2_eval = (1. + r_oned[j]) / 2.;
                break;
            case 2: 
                r1_eval = 0.;
                r2_eval = 0.5 + 0.5 * r_oned[n_quad1d - 1 - j];
                break;
        }

        // x = x2 * r + x3 * s + x1 * (1 - r - s)
        x = v2x * r1_eval + v3x * r2_eval + v1x * (1 - r1_eval - r2_eval);
        y = v2y * r1_eval + v3y * r2_eval + v1y * (1 - r1_eval - r2_eval);
            
        // deal with the boundary element here
        u_right = boundary_exact(x, y, t, alpha);

    } else {
        // evaluate the right side at the integration point
        for (i = 0; i < n_p; i++) {
            u_right  += c_right[i] * basis_side[right_side * n_p * n_quad1d + i * n_quad1d + n_quad1d - 1 - j];
        }
    }

    return riemann(u_left, u_right);
}

/* surface integral evaluation
 *
 * evaluate all the riemann problems for each element.
 * THREADS: num_sides
 */
__device__ void eval_surface(double *c_left, double *c_right, 
                             double *left_riemann_rhs, double *right_riemann_rhs, 
                             double len,
                             double v1x, double v1y,
                             double v2x, double v2y,
                             double v3x, double v3y,
                             int left_idx,  int right_idx,
                             int left_side, int right_side, 
                             double nx, double ny, 
                             int n_quad1d, int n_p, int num_sides, 
                             int num_elem, double t, int idx, int alpha) {
    int i, j;
    double s, left_sum, right_sum;

    // multiply across by the i'th basis function
    for (i = 0; i < n_p; i++) {
        left_sum  = 0.;
        right_sum = 0.;
        // we're at the j'th integration point
        for (j = 0; j < n_quad1d; j++) {
            // solve the Riemann problem at this integration point
            s = eval_riemann(c_left, c_right,
                             v1x, v1y, v2x, v2y, v3x, v3y,
                             j, left_side, right_side, left_idx, right_idx,
                             n_p, n_quad1d, num_sides, t, alpha);

            // calculate the quadrature over [-1,1] for these sides
            left_sum  += (nx * flux_x(s) + ny * flux_y(s)) * w_oned[j] * 
                         basis_side[left_side * n_p * n_quad1d + i * n_quad1d + j];
            right_sum += (nx * flux_x(s) + ny * flux_y(s)) * w_oned[j] * 
                         basis_side[right_side * n_p * n_quad1d + i * n_quad1d + n_quad1d - 1 - j];
        }

        // store this side's contribution in the riemann rhs vectors
        left_riemann_rhs[i * num_sides + idx]  = -len / 2 * left_sum;
        right_riemann_rhs[i * num_sides + idx] =  len / 2 * right_sum;
    }
}
/* flux boundary evaluation 
 *
 * evaulates the flux at the boundaries by handling them somehow.
 * THREADS: num_boundary
 */

/* volume integrals
 *
 * evaluates and adds the volume integral to the rhs vector
 * THREADS: num_elem
 */
__device__ void eval_volume(double *r_c, double *quad_rhs, 
                            double x_r, double y_r,
                            double x_s, double y_s,
                            int n_quad, int n_p, int num_elem, int idx) {
    int i, j, k;
    double sum, u;

    // evaluate the volume integral for each coefficient
    for (i = 0; i < n_p; i++) {
        sum = 0.;
        for (j = 0; j < n_quad; j++) {
            // Evaluate u at the integration point.
            u = 0.;
            for (k = 0; k < n_p; k++) {
                u += r_c[k] * basis[n_quad * k + j];
            }

            // Add to the sum
            // [fx fy] * [y_s, -y_r; -x_s, x_r] * [phi_x phi_y]
            sum += (  flux_x(u) * ( basis_grad_x[n_quad * i + j] * y_s
                                   -basis_grad_y[n_quad * i + j] * y_r)
                    + flux_y(u) * (-basis_grad_x[n_quad * i + j] * x_s 
                                  + basis_grad_y[n_quad * i + j] * x_r));
        }

        // store the result
        quad_rhs[i * num_elem + idx] = sum;
    }
}

/* evaluate error
 * 
 * evaluates u at the three vertex points for output
 * THREADS: num_elem
 */
__device__ void eval_error(double *c, 
                       double v1x, double v1y,
                       double v2x, double v2y,
                       double v3x, double v3y,
                       double *Uv1, double *Uv2, double *Uv3,
                       int num_elem, int n_p, double t, int idx, int alpha) {

    int i;
    double uv1, uv2, uv3;

    // calculate values at three vertex points
    uv1 = 0.;
    uv2 = 0.;
    uv3 = 0.;
    for (i = 0; i < n_p; i++) {
        uv1 += c[i] * basis_vertex[i * 3 + 0];
        uv2 += c[i] * basis_vertex[i * 3 + 1];
        uv3 += c[i] * basis_vertex[i * 3 + 2];
    }

    // store result
    Uv1[idx] = uv1 - uexact(v1x, v1y, t, alpha);
    Uv2[idx] = uv2 - uexact(v2x, v2y, t, alpha);
    Uv3[idx] = uv3 - uexact(v3x, v3y, t, alpha);
}

/* evaluate u
 * 
 * evaluates u at the three vertex points for output
 * THREADS: num_elem
 */
__device__ void eval_u(double *c, 
                       double *Uv1, double *Uv2, double *Uv3,
                       int num_elem, int n_p, int idx) {
    int i;
    double uv1, uv2, uv3;

    // calculate values at the integration points
    uv1 = 0.;
    uv2 = 0.;
    uv3 = 0.;
    for (i = 0; i < n_p; i++) {
        uv1 += c[i] * basis_vertex[i * 3 + 0];
        uv2 += c[i] * basis_vertex[i * 3 + 1];
        uv3 += c[i] * basis_vertex[i * 3 + 2];
    }

    // store result
    Uv1[idx] = uv1;
    Uv2[idx] = uv2;
    Uv3[idx] = uv3;
}

	.text
	.file	"2dadvec_kernels.hip"
	.globl	_Z9set_basisPvi                 # -- Begin function _Z9set_basisPvi
	.type	_Z9set_basisPvi,@function
_Z9set_basisPvi:                        # @_Z9set_basisPvi
	.cfi_startproc
# %bb.0:
	movq	%rdi, %rax
	movslq	%esi, %rdx
	shlq	$3, %rdx
	movl	$.L.str, %edi
	movq	%rax, %rsi
	xorl	%ecx, %ecx
	movl	$1, %r8d
	jmp	hipMemcpyToSymbol               # TAILCALL
.Lfunc_end0:
	.size	_Z9set_basisPvi, .Lfunc_end0-_Z9set_basisPvi
	.cfi_endproc
                                        # -- End function
	.globl	_Z16set_basis_grad_xPvi         # -- Begin function _Z16set_basis_grad_xPvi
	.type	_Z16set_basis_grad_xPvi,@function
_Z16set_basis_grad_xPvi:                # @_Z16set_basis_grad_xPvi
	.cfi_startproc
# %bb.0:
	movq	%rdi, %rax
	movslq	%esi, %rdx
	shlq	$3, %rdx
	movl	$.L.str.1, %edi
	movq	%rax, %rsi
	xorl	%ecx, %ecx
	movl	$1, %r8d
	jmp	hipMemcpyToSymbol               # TAILCALL
.Lfunc_end1:
	.size	_Z16set_basis_grad_xPvi, .Lfunc_end1-_Z16set_basis_grad_xPvi
	.cfi_endproc
                                        # -- End function
	.globl	_Z16set_basis_grad_yPvi         # -- Begin function _Z16set_basis_grad_yPvi
	.type	_Z16set_basis_grad_yPvi,@function
_Z16set_basis_grad_yPvi:                # @_Z16set_basis_grad_yPvi
	.cfi_startproc
# %bb.0:
	movq	%rdi, %rax
	movslq	%esi, %rdx
	shlq	$3, %rdx
	movl	$.L.str.2, %edi
	movq	%rax, %rsi
	xorl	%ecx, %ecx
	movl	$1, %r8d
	jmp	hipMemcpyToSymbol               # TAILCALL
.Lfunc_end2:
	.size	_Z16set_basis_grad_yPvi, .Lfunc_end2-_Z16set_basis_grad_yPvi
	.cfi_endproc
                                        # -- End function
	.globl	_Z14set_basis_sidePvi           # -- Begin function _Z14set_basis_sidePvi
	.type	_Z14set_basis_sidePvi,@function
_Z14set_basis_sidePvi:                  # @_Z14set_basis_sidePvi
	.cfi_startproc
# %bb.0:
	movq	%rdi, %rax
	movslq	%esi, %rdx
	shlq	$3, %rdx
	movl	$.L.str.3, %edi
	movq	%rax, %rsi
	xorl	%ecx, %ecx
	movl	$1, %r8d
	jmp	hipMemcpyToSymbol               # TAILCALL
.Lfunc_end3:
	.size	_Z14set_basis_sidePvi, .Lfunc_end3-_Z14set_basis_sidePvi
	.cfi_endproc
                                        # -- End function
	.globl	_Z16set_basis_vertexPvi         # -- Begin function _Z16set_basis_vertexPvi
	.type	_Z16set_basis_vertexPvi,@function
_Z16set_basis_vertexPvi:                # @_Z16set_basis_vertexPvi
	.cfi_startproc
# %bb.0:
	movq	%rdi, %rax
	movslq	%esi, %rdx
	shlq	$3, %rdx
	movl	$.L.str.4, %edi
	movq	%rax, %rsi
	xorl	%ecx, %ecx
	movl	$1, %r8d
	jmp	hipMemcpyToSymbol               # TAILCALL
.Lfunc_end4:
	.size	_Z16set_basis_vertexPvi, .Lfunc_end4-_Z16set_basis_vertexPvi
	.cfi_endproc
                                        # -- End function
	.globl	_Z5set_wPvi                     # -- Begin function _Z5set_wPvi
	.type	_Z5set_wPvi,@function
_Z5set_wPvi:                            # @_Z5set_wPvi
	.cfi_startproc
# %bb.0:
	movq	%rdi, %rax
	movslq	%esi, %rdx
	shlq	$3, %rdx
	movl	$.L.str.5, %edi
	movq	%rax, %rsi
	xorl	%ecx, %ecx
	movl	$1, %r8d
	jmp	hipMemcpyToSymbol               # TAILCALL
.Lfunc_end5:
	.size	_Z5set_wPvi, .Lfunc_end5-_Z5set_wPvi
	.cfi_endproc
                                        # -- End function
	.globl	_Z10set_w_onedPvi               # -- Begin function _Z10set_w_onedPvi
	.type	_Z10set_w_onedPvi,@function
_Z10set_w_onedPvi:                      # @_Z10set_w_onedPvi
	.cfi_startproc
# %bb.0:
	movq	%rdi, %rax
	movslq	%esi, %rdx
	shlq	$3, %rdx
	movl	$.L.str.6, %edi
	movq	%rax, %rsi
	xorl	%ecx, %ecx
	movl	$1, %r8d
	jmp	hipMemcpyToSymbol               # TAILCALL
.Lfunc_end6:
	.size	_Z10set_w_onedPvi, .Lfunc_end6-_Z10set_w_onedPvi
	.cfi_endproc
                                        # -- End function
	.globl	_Z6set_r1Pvi                    # -- Begin function _Z6set_r1Pvi
	.type	_Z6set_r1Pvi,@function
_Z6set_r1Pvi:                           # @_Z6set_r1Pvi
	.cfi_startproc
# %bb.0:
	movq	%rdi, %rax
	movslq	%esi, %rdx
	shlq	$3, %rdx
	movl	$.L.str.7, %edi
	movq	%rax, %rsi
	xorl	%ecx, %ecx
	movl	$1, %r8d
	jmp	hipMemcpyToSymbol               # TAILCALL
.Lfunc_end7:
	.size	_Z6set_r1Pvi, .Lfunc_end7-_Z6set_r1Pvi
	.cfi_endproc
                                        # -- End function
	.globl	_Z6set_r2Pvi                    # -- Begin function _Z6set_r2Pvi
	.type	_Z6set_r2Pvi,@function
_Z6set_r2Pvi:                           # @_Z6set_r2Pvi
	.cfi_startproc
# %bb.0:
	movq	%rdi, %rax
	movslq	%esi, %rdx
	shlq	$3, %rdx
	movl	$.L.str.8, %edi
	movq	%rax, %rsi
	xorl	%ecx, %ecx
	movl	$1, %r8d
	jmp	hipMemcpyToSymbol               # TAILCALL
.Lfunc_end8:
	.size	_Z6set_r2Pvi, .Lfunc_end8-_Z6set_r2Pvi
	.cfi_endproc
                                        # -- End function
	.globl	_Z10set_r_onedPvi               # -- Begin function _Z10set_r_onedPvi
	.type	_Z10set_r_onedPvi,@function
_Z10set_r_onedPvi:                      # @_Z10set_r_onedPvi
	.cfi_startproc
# %bb.0:
	movq	%rdi, %rax
	movslq	%esi, %rdx
	shlq	$3, %rdx
	movl	$.L.str.9, %edi
	movq	%rax, %rsi
	xorl	%ecx, %ecx
	movl	$1, %r8d
	jmp	hipMemcpyToSymbol               # TAILCALL
.Lfunc_end9:
	.size	_Z10set_r_onedPvi, .Lfunc_end9-_Z10set_r_onedPvi
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__init_conditionsPdS_S_S_S_S_S_S_iiii # -- Begin function _Z30__device_stub__init_conditionsPdS_S_S_S_S_S_S_iiii
	.type	_Z30__device_stub__init_conditionsPdS_S_S_S_S_S_S_iiii,@function
_Z30__device_stub__init_conditionsPdS_S_S_S_S_S_S_iiii: # @_Z30__device_stub__init_conditionsPdS_S_S_S_S_S_S_iiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15init_conditionsPdS_S_S_S_S_S_S_iiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_Z30__device_stub__init_conditionsPdS_S_S_S_S_S_S_iiii, .Lfunc_end10-_Z30__device_stub__init_conditionsPdS_S_S_S_S_S_S_iiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__min_jacobianPdS_i # -- Begin function _Z27__device_stub__min_jacobianPdS_i
	.type	_Z27__device_stub__min_jacobianPdS_i,@function
_Z27__device_stub__min_jacobianPdS_i:   # @_Z27__device_stub__min_jacobianPdS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12min_jacobianPdS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	_Z27__device_stub__min_jacobianPdS_i, .Lfunc_end11-_Z27__device_stub__min_jacobianPdS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__preval_side_lengthPdS_S_S_S_i # -- Begin function _Z33__device_stub__preval_side_lengthPdS_S_S_S_i
	.type	_Z33__device_stub__preval_side_lengthPdS_S_S_S_i,@function
_Z33__device_stub__preval_side_lengthPdS_S_S_S_i: # @_Z33__device_stub__preval_side_lengthPdS_S_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18preval_side_lengthPdS_S_S_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end12:
	.size	_Z33__device_stub__preval_side_lengthPdS_S_S_S_i, .Lfunc_end12-_Z33__device_stub__preval_side_lengthPdS_S_S_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__preval_jacobianPdS_S_S_S_S_S_i # -- Begin function _Z30__device_stub__preval_jacobianPdS_S_S_S_S_S_i
	.type	_Z30__device_stub__preval_jacobianPdS_S_S_S_S_S_i,@function
_Z30__device_stub__preval_jacobianPdS_S_S_S_S_S_i: # @_Z30__device_stub__preval_jacobianPdS_S_S_S_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15preval_jacobianPdS_S_S_S_S_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end13:
	.size	_Z30__device_stub__preval_jacobianPdS_S_S_S_S_S_i, .Lfunc_end13-_Z30__device_stub__preval_jacobianPdS_S_S_S_S_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii # -- Begin function _Z29__device_stub__preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii
	.type	_Z29__device_stub__preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii,@function
_Z29__device_stub__preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii: # @_Z29__device_stub__preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end14:
	.size	_Z29__device_stub__preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii, .Lfunc_end14-_Z29__device_stub__preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii
	.cfi_endproc
                                        # -- End function
	.globl	_Z39__device_stub__preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i # -- Begin function _Z39__device_stub__preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i
	.type	_Z39__device_stub__preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i,@function
_Z39__device_stub__preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i: # @_Z39__device_stub__preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end15:
	.size	_Z39__device_stub__preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i, .Lfunc_end15-_Z39__device_stub__preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__preval_partialsPdS_S_S_S_S_S_S_S_S_i # -- Begin function _Z30__device_stub__preval_partialsPdS_S_S_S_S_S_S_S_S_i
	.type	_Z30__device_stub__preval_partialsPdS_S_S_S_S_S_S_S_S_i,@function
_Z30__device_stub__preval_partialsPdS_S_S_S_S_S_S_S_S_i: # @_Z30__device_stub__preval_partialsPdS_S_S_S_S_S_S_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end16:
	.size	_Z30__device_stub__preval_partialsPdS_S_S_S_S_S_S_S_S_i, .Lfunc_end16-_Z30__device_stub__preval_partialsPdS_S_S_S_S_S_S_S_S_i
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB17_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB17_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15init_conditionsPdS_S_S_S_S_S_S_iiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12min_jacobianPdS_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18preval_side_lengthPdS_S_S_S_i, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15preval_jacobianPdS_S_S_S_S_S_i, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$basis, %esi
	movl	$.L.str, %edx
	movl	$.L.str, %ecx
	movl	$16384, %r9d                    # imm = 0x4000
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$basis_grad_x, %esi
	movl	$.L.str.1, %edx
	movl	$.L.str.1, %ecx
	movl	$16384, %r9d                    # imm = 0x4000
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$basis_grad_y, %esi
	movl	$.L.str.2, %edx
	movl	$.L.str.2, %ecx
	movl	$16384, %r9d                    # imm = 0x4000
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$basis_side, %esi
	movl	$.L.str.3, %edx
	movl	$.L.str.3, %ecx
	movl	$8192, %r9d                     # imm = 0x2000
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$basis_vertex, %esi
	movl	$.L.str.4, %edx
	movl	$.L.str.4, %ecx
	movl	$2048, %r9d                     # imm = 0x800
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$w, %esi
	movl	$.L.str.5, %edx
	movl	$.L.str.5, %ecx
	movl	$256, %r9d                      # imm = 0x100
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$w_oned, %esi
	movl	$.L.str.6, %edx
	movl	$.L.str.6, %ecx
	movl	$128, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$r1, %esi
	movl	$.L.str.7, %edx
	movl	$.L.str.7, %ecx
	movl	$256, %r9d                      # imm = 0x100
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$r2, %esi
	movl	$.L.str.8, %edx
	movl	$.L.str.8, %ecx
	movl	$256, %r9d                      # imm = 0x100
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$r_oned, %esi
	movl	$.L.str.9, %edx
	movl	$.L.str.9, %ecx
	movl	$256, %r9d                      # imm = 0x100
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end17:
	.size	__hip_module_ctor, .Lfunc_end17-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB18_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB18_2:
	retq
.Lfunc_end18:
	.size	__hip_module_dtor, .Lfunc_end18-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	d_c,@object                     # @d_c
	.bss
	.globl	d_c
	.p2align	3, 0x0
d_c:
	.quad	0
	.size	d_c, 8

	.type	d_quad_rhs,@object              # @d_quad_rhs
	.globl	d_quad_rhs
	.p2align	3, 0x0
d_quad_rhs:
	.quad	0
	.size	d_quad_rhs, 8

	.type	d_left_riemann_rhs,@object      # @d_left_riemann_rhs
	.globl	d_left_riemann_rhs
	.p2align	3, 0x0
d_left_riemann_rhs:
	.quad	0
	.size	d_left_riemann_rhs, 8

	.type	d_right_riemann_rhs,@object     # @d_right_riemann_rhs
	.globl	d_right_riemann_rhs
	.p2align	3, 0x0
d_right_riemann_rhs:
	.quad	0
	.size	d_right_riemann_rhs, 8

	.type	d_kstar,@object                 # @d_kstar
	.globl	d_kstar
	.p2align	3, 0x0
d_kstar:
	.quad	0
	.size	d_kstar, 8

	.type	d_k1,@object                    # @d_k1
	.globl	d_k1
	.p2align	3, 0x0
d_k1:
	.quad	0
	.size	d_k1, 8

	.type	d_k2,@object                    # @d_k2
	.globl	d_k2
	.p2align	3, 0x0
d_k2:
	.quad	0
	.size	d_k2, 8

	.type	d_k3,@object                    # @d_k3
	.globl	d_k3
	.p2align	3, 0x0
d_k3:
	.quad	0
	.size	d_k3, 8

	.type	d_k4,@object                    # @d_k4
	.globl	d_k4
	.p2align	3, 0x0
d_k4:
	.quad	0
	.size	d_k4, 8

	.type	basis,@object                   # @basis
	.local	basis
	.comm	basis,16384,16
	.type	basis_grad_x,@object            # @basis_grad_x
	.local	basis_grad_x
	.comm	basis_grad_x,16384,16
	.type	basis_grad_y,@object            # @basis_grad_y
	.local	basis_grad_y
	.comm	basis_grad_y,16384,16
	.type	basis_side,@object              # @basis_side
	.local	basis_side
	.comm	basis_side,8192,16
	.type	basis_vertex,@object            # @basis_vertex
	.local	basis_vertex
	.comm	basis_vertex,2048,16
	.type	w,@object                       # @w
	.local	w
	.comm	w,256,16
	.type	w_oned,@object                  # @w_oned
	.local	w_oned
	.comm	w_oned,128,16
	.type	r1,@object                      # @r1
	.local	r1
	.comm	r1,256,16
	.type	r2,@object                      # @r2
	.local	r2
	.comm	r2,256,16
	.type	r_oned,@object                  # @r_oned
	.local	r_oned
	.comm	r_oned,256,16
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"basis"
	.size	.L.str, 6

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"basis_grad_x"
	.size	.L.str.1, 13

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"basis_grad_y"
	.size	.L.str.2, 13

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"basis_side"
	.size	.L.str.3, 11

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"basis_vertex"
	.size	.L.str.4, 13

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"w"
	.size	.L.str.5, 2

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"w_oned"
	.size	.L.str.6, 7

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"r1"
	.size	.L.str.7, 3

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"r2"
	.size	.L.str.8, 3

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"r_oned"
	.size	.L.str.9, 7

	.type	d_left_side_number,@object      # @d_left_side_number
	.bss
	.globl	d_left_side_number
	.p2align	3, 0x0
d_left_side_number:
	.quad	0
	.size	d_left_side_number, 8

	.type	d_right_side_number,@object     # @d_right_side_number
	.globl	d_right_side_number
	.p2align	3, 0x0
d_right_side_number:
	.quad	0
	.size	d_right_side_number, 8

	.type	d_J,@object                     # @d_J
	.globl	d_J
	.p2align	3, 0x0
d_J:
	.quad	0
	.size	d_J, 8

	.type	d_min_J,@object                 # @d_min_J
	.globl	d_min_J
	.p2align	3, 0x0
d_min_J:
	.quad	0
	.size	d_min_J, 8

	.type	d_s_length,@object              # @d_s_length
	.globl	d_s_length
	.p2align	3, 0x0
d_s_length:
	.quad	0
	.size	d_s_length, 8

	.type	d_s_V1x,@object                 # @d_s_V1x
	.globl	d_s_V1x
	.p2align	3, 0x0
d_s_V1x:
	.quad	0
	.size	d_s_V1x, 8

	.type	d_s_V1y,@object                 # @d_s_V1y
	.globl	d_s_V1y
	.p2align	3, 0x0
d_s_V1y:
	.quad	0
	.size	d_s_V1y, 8

	.type	d_s_V2x,@object                 # @d_s_V2x
	.globl	d_s_V2x
	.p2align	3, 0x0
d_s_V2x:
	.quad	0
	.size	d_s_V2x, 8

	.type	d_s_V2y,@object                 # @d_s_V2y
	.globl	d_s_V2y
	.p2align	3, 0x0
d_s_V2y:
	.quad	0
	.size	d_s_V2y, 8

	.type	d_xr,@object                    # @d_xr
	.globl	d_xr
	.p2align	3, 0x0
d_xr:
	.quad	0
	.size	d_xr, 8

	.type	d_yr,@object                    # @d_yr
	.globl	d_yr
	.p2align	3, 0x0
d_yr:
	.quad	0
	.size	d_yr, 8

	.type	d_xs,@object                    # @d_xs
	.globl	d_xs
	.p2align	3, 0x0
d_xs:
	.quad	0
	.size	d_xs, 8

	.type	d_ys,@object                    # @d_ys
	.globl	d_ys
	.p2align	3, 0x0
d_ys:
	.quad	0
	.size	d_ys, 8

	.type	d_elem_s1,@object               # @d_elem_s1
	.globl	d_elem_s1
	.p2align	3, 0x0
d_elem_s1:
	.quad	0
	.size	d_elem_s1, 8

	.type	d_elem_s2,@object               # @d_elem_s2
	.globl	d_elem_s2
	.p2align	3, 0x0
d_elem_s2:
	.quad	0
	.size	d_elem_s2, 8

	.type	d_elem_s3,@object               # @d_elem_s3
	.globl	d_elem_s3
	.p2align	3, 0x0
d_elem_s3:
	.quad	0
	.size	d_elem_s3, 8

	.type	d_V1x,@object                   # @d_V1x
	.globl	d_V1x
	.p2align	3, 0x0
d_V1x:
	.quad	0
	.size	d_V1x, 8

	.type	d_V1y,@object                   # @d_V1y
	.globl	d_V1y
	.p2align	3, 0x0
d_V1y:
	.quad	0
	.size	d_V1y, 8

	.type	d_V2x,@object                   # @d_V2x
	.globl	d_V2x
	.p2align	3, 0x0
d_V2x:
	.quad	0
	.size	d_V2x, 8

	.type	d_V2y,@object                   # @d_V2y
	.globl	d_V2y
	.p2align	3, 0x0
d_V2y:
	.quad	0
	.size	d_V2y, 8

	.type	d_V3x,@object                   # @d_V3x
	.globl	d_V3x
	.p2align	3, 0x0
d_V3x:
	.quad	0
	.size	d_V3x, 8

	.type	d_V3y,@object                   # @d_V3y
	.globl	d_V3y
	.p2align	3, 0x0
d_V3y:
	.quad	0
	.size	d_V3y, 8

	.type	d_Uv1,@object                   # @d_Uv1
	.globl	d_Uv1
	.p2align	3, 0x0
d_Uv1:
	.quad	0
	.size	d_Uv1, 8

	.type	d_Uv2,@object                   # @d_Uv2
	.globl	d_Uv2
	.p2align	3, 0x0
d_Uv2:
	.quad	0
	.size	d_Uv2, 8

	.type	d_Uv3,@object                   # @d_Uv3
	.globl	d_Uv3
	.p2align	3, 0x0
d_Uv3:
	.quad	0
	.size	d_Uv3, 8

	.type	d_Nx,@object                    # @d_Nx
	.globl	d_Nx
	.p2align	3, 0x0
d_Nx:
	.quad	0
	.size	d_Nx, 8

	.type	d_Ny,@object                    # @d_Ny
	.globl	d_Ny
	.p2align	3, 0x0
d_Ny:
	.quad	0
	.size	d_Ny, 8

	.type	d_left_elem,@object             # @d_left_elem
	.globl	d_left_elem
	.p2align	3, 0x0
d_left_elem:
	.quad	0
	.size	d_left_elem, 8

	.type	d_right_elem,@object            # @d_right_elem
	.globl	d_right_elem
	.p2align	3, 0x0
d_right_elem:
	.quad	0
	.size	d_right_elem, 8

	.type	_Z15init_conditionsPdS_S_S_S_S_S_S_iiii,@object # @_Z15init_conditionsPdS_S_S_S_S_S_S_iiii
	.section	.rodata,"a",@progbits
	.globl	_Z15init_conditionsPdS_S_S_S_S_S_S_iiii
	.p2align	3, 0x0
_Z15init_conditionsPdS_S_S_S_S_S_S_iiii:
	.quad	_Z30__device_stub__init_conditionsPdS_S_S_S_S_S_S_iiii
	.size	_Z15init_conditionsPdS_S_S_S_S_S_S_iiii, 8

	.type	_Z12min_jacobianPdS_i,@object   # @_Z12min_jacobianPdS_i
	.globl	_Z12min_jacobianPdS_i
	.p2align	3, 0x0
_Z12min_jacobianPdS_i:
	.quad	_Z27__device_stub__min_jacobianPdS_i
	.size	_Z12min_jacobianPdS_i, 8

	.type	_Z18preval_side_lengthPdS_S_S_S_i,@object # @_Z18preval_side_lengthPdS_S_S_S_i
	.globl	_Z18preval_side_lengthPdS_S_S_S_i
	.p2align	3, 0x0
_Z18preval_side_lengthPdS_S_S_S_i:
	.quad	_Z33__device_stub__preval_side_lengthPdS_S_S_S_i
	.size	_Z18preval_side_lengthPdS_S_S_S_i, 8

	.type	_Z15preval_jacobianPdS_S_S_S_S_S_i,@object # @_Z15preval_jacobianPdS_S_S_S_S_S_i
	.globl	_Z15preval_jacobianPdS_S_S_S_S_S_i
	.p2align	3, 0x0
_Z15preval_jacobianPdS_S_S_S_S_S_i:
	.quad	_Z30__device_stub__preval_jacobianPdS_S_S_S_S_S_i
	.size	_Z15preval_jacobianPdS_S_S_S_S_S_i, 8

	.type	_Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii,@object # @_Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii
	.globl	_Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii
	.p2align	3, 0x0
_Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii:
	.quad	_Z29__device_stub__preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii
	.size	_Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii, 8

	.type	_Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i,@object # @_Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i
	.globl	_Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i
	.p2align	3, 0x0
_Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i:
	.quad	_Z39__device_stub__preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i
	.size	_Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i, 8

	.type	_Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i,@object # @_Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i
	.globl	_Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i
	.p2align	3, 0x0
_Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i:
	.quad	_Z30__device_stub__preval_partialsPdS_S_S_S_S_S_S_S_S_i
	.size	_Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z15init_conditionsPdS_S_S_S_S_S_S_iiii"
	.size	.L__unnamed_1, 40

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z12min_jacobianPdS_i"
	.size	.L__unnamed_2, 22

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z18preval_side_lengthPdS_S_S_S_i"
	.size	.L__unnamed_3, 34

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z15preval_jacobianPdS_S_S_S_S_S_i"
	.size	.L__unnamed_4, 35

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii"
	.size	.L__unnamed_5, 46

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i"
	.size	.L__unnamed_6, 51

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i"
	.size	.L__unnamed_7, 41

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__init_conditionsPdS_S_S_S_S_S_S_iiii
	.addrsig_sym _Z27__device_stub__min_jacobianPdS_i
	.addrsig_sym _Z33__device_stub__preval_side_lengthPdS_S_S_S_i
	.addrsig_sym _Z30__device_stub__preval_jacobianPdS_S_S_S_S_S_i
	.addrsig_sym _Z29__device_stub__preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii
	.addrsig_sym _Z39__device_stub__preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i
	.addrsig_sym _Z30__device_stub__preval_partialsPdS_S_S_S_S_S_S_S_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym basis
	.addrsig_sym basis_grad_x
	.addrsig_sym basis_grad_y
	.addrsig_sym basis_side
	.addrsig_sym basis_vertex
	.addrsig_sym w
	.addrsig_sym w_oned
	.addrsig_sym r1
	.addrsig_sym r2
	.addrsig_sym r_oned
	.addrsig_sym _Z15init_conditionsPdS_S_S_S_S_S_S_iiii
	.addrsig_sym _Z12min_jacobianPdS_i
	.addrsig_sym _Z18preval_side_lengthPdS_S_S_S_i
	.addrsig_sym _Z15preval_jacobianPdS_S_S_S_S_S_i
	.addrsig_sym _Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii
	.addrsig_sym _Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i
	.addrsig_sym _Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15init_conditionsPdS_S_S_S_S_S_S_iiii ; -- Begin function _Z15init_conditionsPdS_S_S_S_S_S_S_iiii
	.globl	_Z15init_conditionsPdS_S_S_S_S_S_S_iiii
	.p2align	8
	.type	_Z15init_conditionsPdS_S_S_S_S_S_S_iiii,@function
_Z15init_conditionsPdS_S_S_S_S_S_S_iiii: ; @_Z15init_conditionsPdS_S_S_S_S_S_S_iiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x5c
	s_load_b128 s[4:7], s[0:1], 0x40
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_cmp_gt_i32 s5, 0
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s6, v1
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s7, s2
	s_cbranch_execz .LBB0_7
; %bb.1:                                ; %.preheader.lr.ph
	s_clause 0x1
	s_load_b256 s[8:15], s[0:1], 0x10
	s_load_b128 s[16:19], s[0:1], 0x30
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b64 s[0:1], s[0:1], 0x0
	s_cmp_gt_i32 s4, 0
	s_mov_b32 s2, s3
	s_cselect_b32 s7, -1, 0
	v_lshlrev_b64 v[12:13], 3, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s12, v12
	v_add_co_ci_u32_e32 v3, vcc_lo, s13, v13, vcc_lo
	v_add_co_u32 v4, vcc_lo, s16, v12
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v13, vcc_lo
	v_add_co_u32 v6, vcc_lo, s8, v12
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v13, vcc_lo
	v_add_co_u32 v8, vcc_lo, s14, v12
	v_add_co_ci_u32_e32 v9, vcc_lo, s15, v13, vcc_lo
	v_add_co_u32 v10, vcc_lo, s18, v12
	v_add_co_ci_u32_e32 v11, vcc_lo, s19, v13, vcc_lo
	v_add_co_u32 v12, vcc_lo, s10, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s11, v13, vcc_lo
	s_mov_b32 s16, s3
.LBB0_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
	s_and_not1_b32 vcc_lo, exec_lo, s7
	s_cbranch_vccnz .LBB0_5
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[16:17], v[2:3], off
	global_load_b64 v[18:19], v[4:5], off
	global_load_b64 v[20:21], v[6:7], off
	global_load_b64 v[22:23], v[8:9], off
	global_load_b64 v[24:25], v[10:11], off
	global_load_b64 v[26:27], v[12:13], off
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, basis@rel32@lo+4
	s_addc_u32 s9, s9, basis@rel32@hi+12
	s_lshl_b64 s[10:11], s[2:3], 3
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_add_u32 s8, s10, s8
	s_addc_u32 s9, s11, s9
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, r1@rel32@lo+4
	s_addc_u32 s11, s11, r1@rel32@hi+12
	s_mov_b32 s17, s4
	s_getpc_b64 s[12:13]
	s_add_u32 s12, s12, r2@rel32@lo+4
	s_addc_u32 s13, s13, r2@rel32@hi+12
	s_getpc_b64 s[14:15]
	s_add_u32 s14, s14, w@rel32@lo+4
	s_addc_u32 s15, s15, w@rel32@hi+12
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_load_b64 s[18:19], s[12:13], 0x0
	s_load_b64 s[20:21], s[10:11], 0x0
	s_add_i32 s17, s17, -1
	s_waitcnt vmcnt(4) lgkmcnt(0)
	v_mul_f64 v[28:29], s[18:19], v[18:19]
	v_add_f64 v[30:31], -s[20:21], 1.0
	s_waitcnt vmcnt(1)
	v_mul_f64 v[32:33], s[18:19], v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[28:29], s[20:21], v[16:17], v[28:29]
	v_add_f64 v[30:31], v[30:31], -s[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[32:33], s[20:21], v[22:23], v[32:33]
	s_load_b64 s[18:19], s[14:15], 0x0
	v_fma_f64 v[28:29], v[30:31], v[20:21], v[28:29]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[30:31], v[30:31], v[26:27], v[32:33]
	v_add_f64 v[28:29], v[28:29], v[30:31]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[28:29], s[18:19], v[28:29]
	s_load_b64 s[18:19], s[8:9], 0x0
	s_add_u32 s8, s8, 8
	s_addc_u32 s9, s9, 0
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s17, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[14:15], s[18:19], v[28:29], v[14:15]
	s_cbranch_scc1 .LBB0_4
	s_branch .LBB0_6
.LBB0_5:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
.LBB0_6:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mad_u64_u32 v[16:17], null, s16, s6, v[1:2]
	s_add_i32 s16, s16, 1
	s_add_i32 s2, s2, s4
	s_cmp_lg_u32 s16, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v17, 31, v16
	v_lshlrev_b64 v[16:17], 3, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v16, vcc_lo, s0, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s1, v17, vcc_lo
	global_store_b64 v[16:17], v[14:15], off
	s_cbranch_scc1 .LBB0_2
.LBB0_7:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15init_conditionsPdS_S_S_S_S_S_S_iiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 34
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15init_conditionsPdS_S_S_S_S_S_S_iiii, .Lfunc_end0-_Z15init_conditionsPdS_S_S_S_S_S_S_iiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 660
; NumSgprs: 24
; NumVgprs: 34
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 34
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z12min_jacobianPdS_i   ; -- Begin function _Z12min_jacobianPdS_i
	.globl	_Z12min_jacobianPdS_i
	.p2align	8
	.type	_Z12min_jacobianPdS_i,@function
_Z12min_jacobianPdS_i:                  ; @_Z12min_jacobianPdS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s10, s[0:1], 0x10
	s_add_u32 s8, s0, 24
	s_mov_b32 s2, s15
	s_addc_u32 s9, s1, 0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
	v_cmpx_gt_i32_e64 s10, v1
	s_cbranch_execz .LBB1_23
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_mul_i32 s0, s2, s3
	v_lshlrev_b32_e32 v3, 3, v0
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_load_b64 v[4:5], v[1:2], off
	v_lshl_add_u32 v1, s0, 9, v0
	s_waitcnt vmcnt(0)
	ds_store_b64 v3, v[4:5]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_i32_e64 s10, v1
	s_cbranch_execz .LBB1_4
; %bb.2:                                ; %.lr.ph
	s_load_b32 s0, s[8:9], 0x0
	s_mov_b32 s9, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s8, s0, 9
.LBB1_3:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[1:2]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	s_clause 0x1
	global_load_b64 v[6:7], v[4:5], off
	global_load_b64 v[4:5], v[4:5], off offset:2048
	ds_load_b64 v[8:9], v3
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[8:9], v[6:7]
	v_dual_cndmask_b32 v9, v7, v9 :: v_dual_cndmask_b32 v8, v6, v8
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_f64_e32 vcc_lo, v[8:9], v[4:5]
	v_dual_cndmask_b32 v4, v6, v8 :: v_dual_add_nc_u32 v1, s8, v1
	v_cmp_le_i32_e64 s0, s10, v1
	v_cndmask_b32_e32 v5, v7, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	s_or_b32 s9, s0, s9
	ds_store_b64 v3, v[4:5]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB1_3
.LBB1_4:                                ; %Flow109
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB1_6
; %bb.5:
	ds_load_b64 v[1:2], v3
	ds_load_b64 v[4:5], v3 offset:1024
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[1:2], v[4:5]
	v_dual_cndmask_b32 v2, v5, v2 :: v_dual_cndmask_b32 v1, v4, v1
	ds_store_b64 v3, v[1:2]
.LBB1_6:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB1_8
; %bb.7:
	ds_load_b64 v[1:2], v3
	ds_load_b64 v[4:5], v3 offset:512
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[1:2], v[4:5]
	v_dual_cndmask_b32 v2, v5, v2 :: v_dual_cndmask_b32 v1, v4, v1
	ds_store_b64 v3, v[1:2]
.LBB1_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB1_21
; %bb.9:
	s_cmp_lt_u32 s3, 64
	s_cbranch_scc1 .LBB1_11
; %bb.10:
	ds_load_b64 v[1:2], v3
	ds_load_b64 v[4:5], v3 offset:256
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[1:2], v[4:5]
	v_dual_cndmask_b32 v2, v5, v2 :: v_dual_cndmask_b32 v1, v4, v1
	ds_store_b64 v3, v[1:2]
.LBB1_11:
	s_cmp_lt_u32 s3, 32
	s_cbranch_scc1 .LBB1_13
; %bb.12:
	ds_load_2addr_b64 v[4:7], v3 offset1:16
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[6:7]
	v_dual_cndmask_b32 v2, v7, v5 :: v_dual_cndmask_b32 v1, v6, v4
	ds_store_b64 v3, v[1:2]
.LBB1_13:
	s_cmp_lt_u32 s3, 16
	s_cbranch_scc1 .LBB1_15
; %bb.14:
	ds_load_2addr_b64 v[4:7], v3 offset1:8
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[6:7]
	v_dual_cndmask_b32 v2, v7, v5 :: v_dual_cndmask_b32 v1, v6, v4
	ds_store_b64 v3, v[1:2]
.LBB1_15:
	s_cmp_lt_u32 s3, 8
	s_cbranch_scc1 .LBB1_17
; %bb.16:
	ds_load_2addr_b64 v[4:7], v3 offset1:4
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[6:7]
	v_dual_cndmask_b32 v2, v7, v5 :: v_dual_cndmask_b32 v1, v6, v4
	ds_store_b64 v3, v[1:2]
.LBB1_17:
	s_cmp_lt_u32 s3, 4
	s_cbranch_scc1 .LBB1_19
; %bb.18:
	ds_load_2addr_b64 v[4:7], v3 offset1:2
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[6:7]
	v_dual_cndmask_b32 v2, v7, v5 :: v_dual_cndmask_b32 v1, v6, v4
	ds_store_b64 v3, v[1:2]
.LBB1_19:
	s_cmp_lt_u32 s3, 2
	s_cbranch_scc1 .LBB1_21
; %bb.20:
	ds_load_2addr_b64 v[4:7], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[6:7]
	v_dual_cndmask_b32 v2, v7, v5 :: v_dual_cndmask_b32 v1, v6, v4
	ds_store_b64 v3, v[1:2]
.LBB1_21:                               ; %Flow107
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_23
; %bb.22:
	v_mov_b32_e32 v2, 0
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB1_23:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12min_jacobianPdS_i
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z12min_jacobianPdS_i, .Lfunc_end1-_Z12min_jacobianPdS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 876
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z18preval_side_lengthPdS_S_S_S_i ; -- Begin function _Z18preval_side_lengthPdS_S_S_S_i
	.globl	_Z18preval_side_lengthPdS_S_S_S_i
	.p2align	8
	.type	_Z18preval_side_lengthPdS_S_S_S_i,@function
_Z18preval_side_lengthPdS_S_S_S_i:      ; @_Z18preval_side_lengthPdS_S_S_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b32 s3, s[0:1], 0x28
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB2_2
; %bb.1:
	s_load_b256 s[8:15], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b64 s[0:1], s[0:1], 0x20
	s_mov_b32 s2, 0x55555555
	s_mov_b32 s3, 0x3fe55555
	s_mov_b32 s4, 0x968915a9
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	s_mov_b32 s6, 0x4222de17
	s_mov_b32 s5, 0x3fba6564
	s_mov_b32 s7, 0x3fbdee67
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_u32 v2, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s14, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s15, v1, vcc_lo
	v_add_co_u32 v6, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s13, v1, vcc_lo
	v_add_co_u32 v8, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v1, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	global_load_b64 v[4:5], v[4:5], off
	global_load_b64 v[6:7], v[6:7], off
	global_load_b64 v[8:9], v[8:9], off
	s_waitcnt vmcnt(2)
	v_add_f64 v[4:5], v[2:3], -v[4:5]
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[6:7], -v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_frexp_mant_f64_e64 v[6:7], |v[4:5]|
	v_frexp_mant_f64_e64 v[8:9], |v[2:3]|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[6:7]
	v_cmp_gt_f64_e64 s0, s[2:3], v[8:9]
	v_cndmask_b32_e64 v10, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v11, 0, 1, s0
	v_ldexp_f64 v[6:7], v[6:7], v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[8:9], v[8:9], v11
	v_add_f64 v[10:11], v[6:7], 1.0
	v_add_f64 v[22:23], v[6:7], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[8:9], 1.0
	v_rcp_f64_e32 v[14:15], v[10:11]
	v_add_f64 v[26:27], v[10:11], -1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[16:17], v[12:13]
	v_add_f64 v[30:31], v[12:13], -1.0
	v_add_f64 v[6:7], v[6:7], -v[26:27]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[18:19], v[14:15], v[14:15]
	v_fma_f64 v[16:17], v[20:21], v[16:17], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[14:15], v[18:19], v[14:15], v[14:15]
	v_add_f64 v[18:19], v[8:9], -1.0
	v_fma_f64 v[16:17], v[20:21], v[16:17], v[16:17]
	v_add_f64 v[8:9], v[8:9], -v[30:31]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[20:21], v[22:23], v[14:15]
	v_mul_f64 v[24:25], v[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[28:29], v[10:11], v[20:21]
	v_mul_f64 v[32:33], v[12:13], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[10:11], v[20:21], v[10:11], -v[28:29]
	v_fma_f64 v[12:13], v[24:25], v[12:13], -v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[6:7], v[20:21], v[6:7], v[10:11]
	v_fma_f64 v[8:9], v[24:25], v[8:9], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[28:29], v[6:7]
	v_add_f64 v[12:13], v[32:33], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[22:23], -v[10:11]
	v_add_f64 v[28:29], v[10:11], -v[28:29]
	v_add_f64 v[30:31], v[18:19], -v[12:13]
	v_add_f64 v[32:33], v[12:13], -v[32:33]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[22:23], v[22:23], -v[26:27]
	v_add_f64 v[6:7], v[28:29], -v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[18:19], v[18:19], -v[30:31]
	v_add_f64 v[8:9], v[32:33], -v[8:9]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[22:23], -v[10:11]
	v_add_f64 v[12:13], v[18:19], -v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], v[10:11]
	v_add_f64 v[8:9], v[8:9], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[26:27], v[6:7]
	v_add_f64 v[8:9], v[30:31], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[6:7], v[14:15], v[6:7]
	v_mul_f64 v[8:9], v[16:17], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[20:21], v[6:7]
	v_add_f64 v[12:13], v[24:25], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[10:11], -v[20:21]
	v_mul_f64 v[18:19], v[10:11], v[10:11]
	v_add_f64 v[16:17], v[12:13], -v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[6:7], v[6:7], -v[14:15]
	v_mul_f64 v[14:15], v[12:13], v[12:13]
	v_add_f64 v[8:9], v[8:9], -v[16:17]
	v_fma_f64 v[16:17], v[10:11], v[10:11], -v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[20:21], v[6:7], v[6:7]
	v_fma_f64 v[22:23], v[12:13], v[12:13], -v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[8:9], v[8:9]
	v_fma_f64 v[16:17], v[10:11], v[20:21], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[12:13], v[24:25], v[22:23]
	v_add_f64 v[22:23], v[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[14:15], v[20:21]
	v_fma_f64 v[26:27], v[22:23], s[6:7], s[4:5]
	v_add_f64 v[18:19], v[22:23], -v[18:19]
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[28:29], v[24:25], s[6:7], s[4:5]
	s_mov_b32 s4, 0x3abe935a
	s_mov_b32 s5, 0x3fbe25e4
	v_add_f64 v[14:15], v[24:25], -v[14:15]
	v_mul_f64 v[36:37], v[10:11], v[22:23]
	v_mul_f64 v[40:41], v[12:13], v[24:25]
	s_mov_b32 s6, 0x652b82fe
	s_mov_b32 s7, 0x3ff71547
	v_fma_f64 v[26:27], v[22:23], v[26:27], s[4:5]
	v_add_f64 v[16:17], v[16:17], -v[18:19]
	v_fma_f64 v[28:29], v[24:25], v[28:29], s[4:5]
	s_mov_b32 s4, 0x47e6c9c2
	s_mov_b32 s5, 0x3fc110ef
	v_add_f64 v[14:15], v[20:21], -v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[26:27], v[22:23], v[26:27], s[4:5]
	v_fma_f64 v[28:29], v[24:25], v[28:29], s[4:5]
	s_mov_b32 s4, 0xcfa74449
	s_mov_b32 s5, 0x3fc3b13b
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[26:27], v[22:23], v[26:27], s[4:5]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[28:29], v[24:25], v[28:29], s[4:5]
	s_mov_b32 s4, 0x71bf3c30
	s_mov_b32 s5, 0x3fc745d1
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[26:27], v[22:23], v[26:27], s[4:5]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[28:29], v[24:25], v[28:29], s[4:5]
	s_mov_b32 s4, 0x1c7792ce
	s_mov_b32 s5, 0x3fcc71c7
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[26:27], v[22:23], v[26:27], s[4:5]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[28:29], v[24:25], v[28:29], s[4:5]
	s_mov_b32 s4, 0x924920da
	s_mov_b32 s5, 0x3fd24924
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[26:27], v[22:23], v[26:27], s[4:5]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[28:29], v[24:25], v[28:29], s[4:5]
	s_mov_b32 s4, 0x9999999c
	s_mov_b32 s5, 0x3fd99999
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[26:27], v[22:23], v[26:27], s[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[28:29], v[24:25], v[28:29], s[4:5]
	s_mov_b32 s4, 0x3b39803f
	s_mov_b32 s5, 0x3c7abc9e
	v_mul_f64 v[30:31], v[22:23], v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[32:33], v[24:25], v[28:29]
	v_fma_f64 v[18:19], v[22:23], v[26:27], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[24:25], v[28:29], -v[32:33]
	v_fma_f64 v[18:19], v[16:17], v[26:27], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[14:15], v[28:29], v[20:21]
	v_add_f64 v[26:27], v[30:31], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[28:29], v[32:33], v[20:21]
	v_add_f64 v[34:35], v[26:27], s[2:3]
	v_add_f64 v[30:31], v[26:27], -v[30:31]
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f64 v[38:39], v[28:29], s[2:3]
	v_add_f64 v[32:33], v[28:29], -v[32:33]
	s_mov_b32 s3, 0xbfe55555
	s_delay_alu instid0(VALU_DEP_4) | instid1(SALU_CYCLE_1)
	v_add_f64 v[42:43], v[34:35], s[2:3]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[18:19], v[18:19], -v[30:31]
	v_fma_f64 v[30:31], v[22:23], v[10:11], -v[36:37]
	v_add_f64 v[44:45], v[38:39], s[2:3]
	v_add_f64 v[20:21], v[20:21], -v[32:33]
	v_fma_f64 v[32:33], v[24:25], v[12:13], -v[40:41]
	s_mov_b32 s2, 0xd5df274d
	s_mov_b32 s3, 0x3c8543b0
	v_add_f64 v[26:27], v[26:27], -v[42:43]
	v_add_f64 v[18:19], v[18:19], s[2:3]
	v_fma_f64 v[22:23], v[22:23], v[6:7], v[30:31]
	v_add_f64 v[28:29], v[28:29], -v[44:45]
	v_add_f64 v[20:21], v[20:21], s[2:3]
	v_fma_f64 v[24:25], v[24:25], v[8:9], v[32:33]
	s_mov_b32 s2, 0xfefa39ef
	s_mov_b32 s3, 0x3fe62e42
	v_ldexp_f64 v[6:7], v[6:7], 1
	v_ldexp_f64 v[8:9], v[8:9], 1
	v_add_f64 v[18:19], v[18:19], v[26:27]
	v_fma_f64 v[16:17], v[16:17], v[10:11], v[22:23]
	v_ldexp_f64 v[10:11], v[10:11], 1
	v_add_f64 v[20:21], v[20:21], v[28:29]
	v_fma_f64 v[14:15], v[14:15], v[12:13], v[24:25]
	v_ldexp_f64 v[12:13], v[12:13], 1
	v_add_f64 v[22:23], v[34:35], v[18:19]
	v_add_f64 v[24:25], v[36:37], v[16:17]
	v_add_f64 v[26:27], v[38:39], v[20:21]
	v_add_f64 v[28:29], v[40:41], v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[30:31], v[34:35], -v[22:23]
	v_mul_f64 v[32:33], v[24:25], v[22:23]
	v_add_f64 v[36:37], v[24:25], -v[36:37]
	v_add_f64 v[34:35], v[38:39], -v[26:27]
	v_mul_f64 v[38:39], v[28:29], v[26:27]
	v_add_f64 v[40:41], v[28:29], -v[40:41]
	v_add_f64 v[18:19], v[18:19], v[30:31]
	v_fma_f64 v[30:31], v[24:25], v[22:23], -v[32:33]
	v_add_f64 v[16:17], v[16:17], -v[36:37]
	v_add_f64 v[20:21], v[20:21], v[34:35]
	v_fma_f64 v[34:35], v[28:29], v[26:27], -v[38:39]
	v_add_f64 v[14:15], v[14:15], -v[40:41]
	v_fma_f64 v[18:19], v[24:25], v[18:19], v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[28:29], v[20:21], v[34:35]
	v_fma_f64 v[16:17], v[16:17], v[22:23], v[18:19]
	v_frexp_exp_i32_f64_e32 v22, v[4:5]
	v_frexp_exp_i32_f64_e32 v23, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[14:15], v[14:15], v[26:27], v[20:21]
	v_add_f64 v[18:19], v[32:33], v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v22, vcc_lo, 0, v22, vcc_lo
	v_add_f64 v[20:21], v[38:39], v[14:15]
	v_subrev_co_ci_u32_e64 v28, vcc_lo, 0, v23, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[22:23], v22
	v_cvt_f64_i32_e32 v[28:29], v28
	v_add_f64 v[24:25], v[10:11], v[18:19]
	v_add_f64 v[26:27], v[18:19], -v[32:33]
	v_add_f64 v[30:31], v[12:13], v[20:21]
	v_add_f64 v[32:33], v[20:21], -v[38:39]
	v_mul_f64 v[34:35], v[22:23], s[2:3]
	v_add_f64 v[10:11], v[24:25], -v[10:11]
	v_add_f64 v[16:17], v[16:17], -v[26:27]
	v_mul_f64 v[26:27], v[28:29], s[2:3]
	v_add_f64 v[12:13], v[30:31], -v[12:13]
	v_add_f64 v[14:15], v[14:15], -v[32:33]
	v_fma_f64 v[32:33], v[22:23], s[2:3], -v[34:35]
	v_add_f64 v[10:11], v[18:19], -v[10:11]
	v_add_f64 v[6:7], v[6:7], v[16:17]
	v_fma_f64 v[16:17], v[28:29], s[2:3], -v[26:27]
	v_add_f64 v[12:13], v[20:21], -v[12:13]
	v_add_f64 v[8:9], v[8:9], v[14:15]
	s_mov_b32 s3, 0xbfe62e42
	v_fma_f64 v[14:15], v[22:23], s[4:5], v[32:33]
	v_add_f64 v[6:7], v[6:7], v[10:11]
	v_fma_f64 v[10:11], v[28:29], s[4:5], v[16:17]
	s_mov_b32 s5, 0xbc7abc9e
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[8:9], v[8:9], v[12:13]
	v_add_f64 v[12:13], v[34:35], v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[16:17], v[24:25], v[6:7]
	v_add_f64 v[18:19], v[26:27], v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[20:21], v[30:31], v[8:9]
	v_add_f64 v[34:35], v[12:13], -v[34:35]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[22:23], v[12:13], v[16:17]
	v_add_f64 v[24:25], v[16:17], -v[24:25]
	v_add_f64 v[26:27], v[18:19], -v[26:27]
	v_add_f64 v[28:29], v[18:19], v[20:21]
	v_add_f64 v[30:31], v[20:21], -v[30:31]
	v_add_f64 v[14:15], v[14:15], -v[34:35]
	v_add_f64 v[32:33], v[22:23], -v[12:13]
	v_add_f64 v[6:7], v[6:7], -v[24:25]
	v_add_f64 v[10:11], v[10:11], -v[26:27]
	v_add_f64 v[36:37], v[28:29], -v[18:19]
	v_add_f64 v[8:9], v[8:9], -v[30:31]
	v_add_f64 v[38:39], v[22:23], -v[32:33]
	v_add_f64 v[16:17], v[16:17], -v[32:33]
	v_add_f64 v[24:25], v[14:15], v[6:7]
	v_add_f64 v[40:41], v[28:29], -v[36:37]
	v_add_f64 v[20:21], v[20:21], -v[36:37]
	v_add_f64 v[12:13], v[12:13], -v[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[18:19], -v[40:41]
	v_add_f64 v[12:13], v[16:17], v[12:13]
	v_add_f64 v[16:17], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[18:19], v[20:21], v[18:19]
	v_add_f64 v[20:21], v[24:25], -v[14:15]
	v_add_f64 v[12:13], v[24:25], v[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[26:27], v[16:17], -v[10:11]
	v_add_f64 v[18:19], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[24:25], v[24:25], -v[20:21]
	v_add_f64 v[6:7], v[6:7], -v[20:21]
	v_add_f64 v[30:31], v[22:23], v[12:13]
	v_add_f64 v[16:17], v[16:17], -v[26:27]
	v_add_f64 v[8:9], v[8:9], -v[26:27]
	v_add_f64 v[32:33], v[28:29], v[18:19]
	v_add_f64 v[14:15], v[14:15], -v[24:25]
	v_add_f64 v[20:21], v[30:31], -v[22:23]
	v_add_f64 v[10:11], v[10:11], -v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[16:17], v[32:33], -v[28:29]
	v_add_f64 v[6:7], v[6:7], v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[12:13], v[12:13], -v[20:21]
	v_add_f64 v[8:9], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[18:19], -v[16:17]
	v_add_f64 v[6:7], v[6:7], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[8:9], v[10:11]
	v_add_f64 v[10:11], v[30:31], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[32:33], v[8:9]
	v_add_f64 v[14:15], v[10:11], -v[30:31]
	v_add_f64 v[16:17], v[10:11], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[18:19], v[12:13], -v[32:33]
	v_add_f64 v[20:21], v[12:13], v[12:13]
	v_add_f64 v[6:7], v[6:7], -v[14:15]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[10:11], v[10:11], 2.0, -v[16:17]
	v_cmp_class_f64_e64 vcc_lo, v[16:17], 0x204
	v_add_f64 v[8:9], v[8:9], -v[18:19]
	v_fma_f64 v[12:13], v[12:13], 2.0, -v[20:21]
	v_cmp_class_f64_e64 s0, v[20:21], 0x204
	v_fma_f64 v[6:7], v[6:7], 2.0, v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[8:9], v[8:9], 2.0, v[12:13]
	v_add_f64 v[10:11], v[16:17], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[20:21], v[8:9]
	v_dual_cndmask_b32 v15, v11, v17 :: v_dual_cndmask_b32 v14, v10, v16
	v_add_f64 v[10:11], v[10:11], -v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v19, v13, v21, s0
	v_cndmask_b32_e64 v18, v12, v20, s0
	s_mov_b32 s0, 0xfca7ab0c
	v_mul_f64 v[22:23], v[14:15], s[6:7]
	s_mov_b32 s1, 0x3e928af3
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[14:15]|
	v_mul_f64 v[24:25], v[18:19], s[6:7]
	v_add_f64 v[12:13], v[12:13], -v[20:21]
	v_add_f64 v[6:7], v[6:7], -v[10:11]
	v_rndne_f64_e32 v[22:23], v[22:23]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_rndne_f64_e32 v[24:25], v[24:25]
	v_add_f64 v[8:9], v[8:9], -v[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v7, 0, v7 :: v_dual_cndmask_b32 v6, 0, v6
	v_fma_f64 v[26:27], v[22:23], s[2:3], v[14:15]
	v_cvt_i32_f64_e32 v34, v[22:23]
	v_fma_f64 v[28:29], v[24:25], s[2:3], v[18:19]
	s_mov_b32 s2, 0x6a5dcb37
	s_mov_b32 s3, 0x3e5ade15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[26:27], v[22:23], s[4:5], v[26:27]
	v_fma_f64 v[28:29], v[24:25], s[4:5], v[28:29]
	v_cmp_ngt_f64_e64 s4, 0xc090cc00, v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[30:31], v[26:27], s[2:3], s[0:1]
	v_fma_f64 v[32:33], v[28:29], s[2:3], s[0:1]
	s_mov_b32 s0, 0x623fde64
	s_mov_b32 s1, 0x3ec71dee
	v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[14:15]
	v_cmp_nlt_f64_e64 s3, 0x40900000, v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[30:31], v[26:27], v[30:31], s[0:1]
	v_fma_f64 v[32:33], v[28:29], v[32:33], s[0:1]
	s_mov_b32 s0, 0x7c89e6b0
	s_mov_b32 s1, 0x3efa0199
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[30:31], v[26:27], v[30:31], s[0:1]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[32:33], v[28:29], v[32:33], s[0:1]
	s_mov_b32 s0, 0x14761f6e
	s_mov_b32 s1, 0x3f2a01a0
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[30:31], v[26:27], v[30:31], s[0:1]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[32:33], v[28:29], v[32:33], s[0:1]
	s_mov_b32 s0, 0x1852b7b0
	s_mov_b32 s1, 0x3f56c16c
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[30:31], v[26:27], v[30:31], s[0:1]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[32:33], v[28:29], v[32:33], s[0:1]
	s_mov_b32 s0, 0x11122322
	s_mov_b32 s1, 0x3f811111
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[30:31], v[26:27], v[30:31], s[0:1]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[32:33], v[28:29], v[32:33], s[0:1]
	s_mov_b32 s0, 0x555502a1
	s_mov_b32 s1, 0x3fa55555
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[30:31], v[26:27], v[30:31], s[0:1]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[32:33], v[28:29], v[32:33], s[0:1]
	s_mov_b32 s0, 0x55555511
	s_mov_b32 s1, 0x3fc55555
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[30:31], v[26:27], v[30:31], s[0:1]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[32:33], v[28:29], v[32:33], s[0:1]
	s_mov_b32 s0, 11
	s_mov_b32 s1, 0x3fe00000
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[30:31], v[26:27], v[30:31], s[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[32:33], v[28:29], v[32:33], s[0:1]
	v_cmp_nlt_f64_e64 s1, 0x40900000, v[14:15]
	v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[18:19]|
	v_fma_f64 v[30:31], v[26:27], v[30:31], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[32:33], v[28:29], v[32:33], 1.0
	s_and_b32 vcc_lo, s2, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v9, 0, v9, s0
	v_cndmask_b32_e64 v8, 0, v8, s0
	v_fma_f64 v[22:23], v[26:27], v[30:31], 1.0
	v_cvt_i32_f64_e32 v26, v[24:25]
	v_fma_f64 v[24:25], v[28:29], v[32:33], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[16:17], v[22:23], v34
	v_ldexp_f64 v[20:21], v[24:25], v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, 0x7ff00000, v17, s1
	v_cmp_neq_f64_e64 s1, 0x7ff00000, |v[4:5]|
	v_cndmask_b32_e64 v12, 0x7ff00000, v21, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v11, 0, v10, s2
	v_cndmask_b32_e32 v10, 0, v16, vcc_lo
	s_and_b32 vcc_lo, s4, s3
	v_cndmask_b32_e64 v13, 0, v12, s4
	v_cndmask_b32_e32 v12, 0, v20, vcc_lo
	v_cmp_neq_f64_e64 s3, 0x7ff00000, |v[2:3]|
	v_fma_f64 v[6:7], v[10:11], v[6:7], v[10:11]
	v_cmp_class_f64_e64 vcc_lo, v[10:11], 0x204
	v_cmp_neq_f64_e64 s2, 0, v[4:5]
	v_cmp_neq_f64_e64 s4, 0, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v7, v7, v11 :: v_dual_cndmask_b32 v2, v6, v10
	s_and_b32 vcc_lo, s2, s1
	s_delay_alu instid0(VALU_DEP_1)
	v_and_b32_e32 v7, 0x7fffffff, v7
	v_fma_f64 v[8:9], v[12:13], v[8:9], v[12:13]
	v_cmp_class_f64_e64 s0, v[12:13], 0x204
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	s_and_b32 vcc_lo, s4, s3
	v_cndmask_b32_e64 v7, 0x7ff00000, v7, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v3, 0, v7, s2
	v_cndmask_b32_e64 v9, v9, v13, s0
	v_cndmask_b32_e64 v6, v8, v12, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v9, 0x7fffffff, v9
	v_cndmask_b32_e64 v4, 0x7ff00000, v9, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v5, 0, v4, s4
	v_cndmask_b32_e32 v4, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[4:5]
	v_cvt_f32_f64_e32 v2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v3, 0x4f800000, v2
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
	v_cndmask_b32_e32 v2, v2, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v4, -1, v3
	v_add_nc_u32_e32 v5, 1, v3
	v_fma_f32 v6, -v4, v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, -v5, v3, v2
	v_cmp_ge_f32_e64 s0, 0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v3, v3, v4, s0
	v_cmp_lt_f32_e64 s0, 0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v3, v5, s0
	v_mul_f32_e32 v4, 0x37800000, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v2, 0x260
	v_cndmask_b32_e32 v2, v3, v2, vcc_lo
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cvt_f64_f32_e32 v[2:3], v2
	global_store_b64 v[0:1], v[2:3], off
.LBB2_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18preval_side_lengthPdS_S_S_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 46
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z18preval_side_lengthPdS_S_S_S_i, .Lfunc_end2-_Z18preval_side_lengthPdS_S_S_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3668
; NumSgprs: 18
; NumVgprs: 46
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 46
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z15preval_jacobianPdS_S_S_S_S_S_i ; -- Begin function _Z15preval_jacobianPdS_S_S_S_S_S_i
	.globl	_Z15preval_jacobianPdS_S_S_S_S_S_i
	.p2align	8
	.type	_Z15preval_jacobianPdS_S_S_S_S_S_i,@function
_Z15preval_jacobianPdS_S_S_S_S_S_i:     ; @_Z15preval_jacobianPdS_S_S_S_S_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b32 s3, s[0:1], 0x38
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB3_2
; %bb.1:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[12:19], s[0:1], 0x20
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v1, vcc_lo
	v_add_co_u32 v6, vcc_lo, s14, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s15, v1, vcc_lo
	v_add_co_u32 v8, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v1, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	global_load_b64 v[4:5], v[4:5], off
	global_load_b64 v[6:7], v[6:7], off
	global_load_b64 v[8:9], v[8:9], off
	v_add_co_u32 v10, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v1, vcc_lo
	v_add_co_u32 v12, vcc_lo, s16, v0
	v_add_co_ci_u32_e32 v13, vcc_lo, s17, v1, vcc_lo
	global_load_b64 v[10:11], v[10:11], off
	global_load_b64 v[12:13], v[12:13], off
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_waitcnt vmcnt(3)
	v_add_f64 v[6:7], v[6:7], -v[2:3]
	s_waitcnt vmcnt(2)
	v_add_f64 v[8:9], v[8:9], -v[4:5]
	s_waitcnt vmcnt(1)
	v_add_f64 v[2:3], v[10:11], -v[2:3]
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[12:13], -v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[2:3], v[2:3], v[4:5], -v[6:7]
	global_store_b64 v[0:1], v[2:3], off
.LBB3_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15preval_jacobianPdS_S_S_S_S_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z15preval_jacobianPdS_S_S_S_S_S_i, .Lfunc_end3-_Z15preval_jacobianPdS_S_S_S_S_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 324
; NumSgprs: 22
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii ; -- Begin function _Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii
	.globl	_Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii
	.p2align	8
	.type	_Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii,@function
_Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii: ; @_Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x7c
	s_load_b32 s3, s[0:1], 0x68
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB4_2
; %bb.1:
	s_clause 0x1
	s_load_b256 s[8:15], s[0:1], 0x0
	s_load_b128 s[0:3], s[0:1], 0x20
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s4, 0x968915a9
	s_mov_b32 s6, 0x4222de17
	s_mov_b32 s5, 0x3fba6564
	s_mov_b32 s7, 0x3fbdee67
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s13, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s14, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s15, v1, vcc_lo
	v_add_co_u32 v6, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v8, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v1, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	global_load_b64 v[6:7], v[6:7], off
	global_load_b64 v[4:5], v[4:5], off
	global_load_b64 v[8:9], v[8:9], off
	s_mov_b32 s2, 0x55555555
	s_mov_b32 s3, 0x3fe55555
	s_waitcnt vmcnt(2)
	v_add_f64 v[2:3], v[6:7], -v[2:3]
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[8:9], -v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
	v_frexp_mant_f64_e64 v[8:9], |v[4:5]|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[6:7]
	v_cmp_gt_f64_e64 s0, s[2:3], v[8:9]
	v_cndmask_b32_e64 v10, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v11, 0, 1, s0
	v_ldexp_f64 v[6:7], v[6:7], v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[8:9], v[8:9], v11
	v_add_f64 v[10:11], v[6:7], 1.0
	v_add_f64 v[22:23], v[6:7], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[8:9], 1.0
	v_rcp_f64_e32 v[14:15], v[10:11]
	v_add_f64 v[26:27], v[10:11], -1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[16:17], v[12:13]
	v_add_f64 v[30:31], v[12:13], -1.0
	v_add_f64 v[6:7], v[6:7], -v[26:27]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[18:19], v[14:15], v[14:15]
	v_fma_f64 v[16:17], v[20:21], v[16:17], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[14:15], v[18:19], v[14:15], v[14:15]
	v_add_f64 v[18:19], v[8:9], -1.0
	v_fma_f64 v[16:17], v[20:21], v[16:17], v[16:17]
	v_add_f64 v[8:9], v[8:9], -v[30:31]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[20:21], v[22:23], v[14:15]
	v_mul_f64 v[24:25], v[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[28:29], v[10:11], v[20:21]
	v_mul_f64 v[32:33], v[12:13], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[10:11], v[20:21], v[10:11], -v[28:29]
	v_fma_f64 v[12:13], v[24:25], v[12:13], -v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[6:7], v[20:21], v[6:7], v[10:11]
	v_fma_f64 v[8:9], v[24:25], v[8:9], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[28:29], v[6:7]
	v_add_f64 v[12:13], v[32:33], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[22:23], -v[10:11]
	v_add_f64 v[28:29], v[10:11], -v[28:29]
	v_add_f64 v[30:31], v[18:19], -v[12:13]
	v_add_f64 v[32:33], v[12:13], -v[32:33]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[22:23], v[22:23], -v[26:27]
	v_add_f64 v[6:7], v[28:29], -v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[18:19], v[18:19], -v[30:31]
	v_add_f64 v[8:9], v[32:33], -v[8:9]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[22:23], -v[10:11]
	v_add_f64 v[12:13], v[18:19], -v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], v[10:11]
	v_add_f64 v[8:9], v[8:9], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[26:27], v[6:7]
	v_add_f64 v[8:9], v[30:31], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[6:7], v[14:15], v[6:7]
	v_mul_f64 v[8:9], v[16:17], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[20:21], v[6:7]
	v_add_f64 v[12:13], v[24:25], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[10:11], -v[20:21]
	v_mul_f64 v[18:19], v[10:11], v[10:11]
	v_add_f64 v[16:17], v[12:13], -v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[6:7], v[6:7], -v[14:15]
	v_mul_f64 v[14:15], v[12:13], v[12:13]
	v_add_f64 v[8:9], v[8:9], -v[16:17]
	v_fma_f64 v[16:17], v[10:11], v[10:11], -v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[20:21], v[6:7], v[6:7]
	v_fma_f64 v[22:23], v[12:13], v[12:13], -v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[8:9], v[8:9]
	v_fma_f64 v[16:17], v[10:11], v[20:21], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[12:13], v[24:25], v[22:23]
	v_add_f64 v[22:23], v[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[14:15], v[20:21]
	v_fma_f64 v[26:27], v[22:23], s[6:7], s[4:5]
	v_add_f64 v[18:19], v[22:23], -v[18:19]
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[28:29], v[24:25], s[6:7], s[4:5]
	s_mov_b32 s4, 0x3abe935a
	s_mov_b32 s5, 0x3fbe25e4
	v_add_f64 v[14:15], v[24:25], -v[14:15]
	v_mul_f64 v[36:37], v[10:11], v[22:23]
	v_mul_f64 v[40:41], v[12:13], v[24:25]
	s_mov_b32 s6, 0x652b82fe
	s_mov_b32 s7, 0x3ff71547
	v_fma_f64 v[26:27], v[22:23], v[26:27], s[4:5]
	v_add_f64 v[16:17], v[16:17], -v[18:19]
	v_fma_f64 v[28:29], v[24:25], v[28:29], s[4:5]
	s_mov_b32 s4, 0x47e6c9c2
	s_mov_b32 s5, 0x3fc110ef
	v_add_f64 v[14:15], v[20:21], -v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[26:27], v[22:23], v[26:27], s[4:5]
	v_fma_f64 v[28:29], v[24:25], v[28:29], s[4:5]
	s_mov_b32 s4, 0xcfa74449
	s_mov_b32 s5, 0x3fc3b13b
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[26:27], v[22:23], v[26:27], s[4:5]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[28:29], v[24:25], v[28:29], s[4:5]
	s_mov_b32 s4, 0x71bf3c30
	s_mov_b32 s5, 0x3fc745d1
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[26:27], v[22:23], v[26:27], s[4:5]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[28:29], v[24:25], v[28:29], s[4:5]
	s_mov_b32 s4, 0x1c7792ce
	s_mov_b32 s5, 0x3fcc71c7
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[26:27], v[22:23], v[26:27], s[4:5]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[28:29], v[24:25], v[28:29], s[4:5]
	s_mov_b32 s4, 0x924920da
	s_mov_b32 s5, 0x3fd24924
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[26:27], v[22:23], v[26:27], s[4:5]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[28:29], v[24:25], v[28:29], s[4:5]
	s_mov_b32 s4, 0x9999999c
	s_mov_b32 s5, 0x3fd99999
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[26:27], v[22:23], v[26:27], s[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[28:29], v[24:25], v[28:29], s[4:5]
	s_mov_b32 s4, 0x3b39803f
	s_mov_b32 s5, 0x3c7abc9e
	v_mul_f64 v[30:31], v[22:23], v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[32:33], v[24:25], v[28:29]
	v_fma_f64 v[18:19], v[22:23], v[26:27], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[24:25], v[28:29], -v[32:33]
	v_fma_f64 v[18:19], v[16:17], v[26:27], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[14:15], v[28:29], v[20:21]
	v_add_f64 v[26:27], v[30:31], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[28:29], v[32:33], v[20:21]
	v_add_f64 v[34:35], v[26:27], s[2:3]
	v_add_f64 v[30:31], v[26:27], -v[30:31]
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f64 v[38:39], v[28:29], s[2:3]
	v_add_f64 v[32:33], v[28:29], -v[32:33]
	s_mov_b32 s3, 0xbfe55555
	s_delay_alu instid0(VALU_DEP_4) | instid1(SALU_CYCLE_1)
	v_add_f64 v[42:43], v[34:35], s[2:3]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[18:19], v[18:19], -v[30:31]
	v_fma_f64 v[30:31], v[22:23], v[10:11], -v[36:37]
	v_add_f64 v[44:45], v[38:39], s[2:3]
	v_add_f64 v[20:21], v[20:21], -v[32:33]
	v_fma_f64 v[32:33], v[24:25], v[12:13], -v[40:41]
	s_mov_b32 s2, 0xd5df274d
	s_mov_b32 s3, 0x3c8543b0
	v_add_f64 v[26:27], v[26:27], -v[42:43]
	v_add_f64 v[18:19], v[18:19], s[2:3]
	v_fma_f64 v[22:23], v[22:23], v[6:7], v[30:31]
	v_add_f64 v[28:29], v[28:29], -v[44:45]
	v_add_f64 v[20:21], v[20:21], s[2:3]
	v_fma_f64 v[24:25], v[24:25], v[8:9], v[32:33]
	s_mov_b32 s2, 0xfefa39ef
	s_mov_b32 s3, 0x3fe62e42
	v_ldexp_f64 v[6:7], v[6:7], 1
	v_ldexp_f64 v[8:9], v[8:9], 1
	v_add_f64 v[18:19], v[18:19], v[26:27]
	v_fma_f64 v[16:17], v[16:17], v[10:11], v[22:23]
	v_ldexp_f64 v[10:11], v[10:11], 1
	v_add_f64 v[20:21], v[20:21], v[28:29]
	v_fma_f64 v[14:15], v[14:15], v[12:13], v[24:25]
	v_ldexp_f64 v[12:13], v[12:13], 1
	v_add_f64 v[22:23], v[34:35], v[18:19]
	v_add_f64 v[24:25], v[36:37], v[16:17]
	v_add_f64 v[26:27], v[38:39], v[20:21]
	v_add_f64 v[28:29], v[40:41], v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[30:31], v[34:35], -v[22:23]
	v_mul_f64 v[32:33], v[24:25], v[22:23]
	v_add_f64 v[36:37], v[24:25], -v[36:37]
	v_add_f64 v[34:35], v[38:39], -v[26:27]
	v_mul_f64 v[38:39], v[28:29], v[26:27]
	v_add_f64 v[40:41], v[28:29], -v[40:41]
	v_add_f64 v[18:19], v[18:19], v[30:31]
	v_fma_f64 v[30:31], v[24:25], v[22:23], -v[32:33]
	v_add_f64 v[16:17], v[16:17], -v[36:37]
	v_add_f64 v[20:21], v[20:21], v[34:35]
	v_fma_f64 v[34:35], v[28:29], v[26:27], -v[38:39]
	v_add_f64 v[14:15], v[14:15], -v[40:41]
	v_fma_f64 v[18:19], v[24:25], v[18:19], v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[28:29], v[20:21], v[34:35]
	v_fma_f64 v[16:17], v[16:17], v[22:23], v[18:19]
	v_frexp_exp_i32_f64_e32 v22, v[2:3]
	v_frexp_exp_i32_f64_e32 v23, v[4:5]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[14:15], v[14:15], v[26:27], v[20:21]
	v_add_f64 v[18:19], v[32:33], v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v22, vcc_lo, 0, v22, vcc_lo
	v_add_f64 v[20:21], v[38:39], v[14:15]
	v_subrev_co_ci_u32_e64 v28, vcc_lo, 0, v23, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[22:23], v22
	v_cvt_f64_i32_e32 v[28:29], v28
	v_add_f64 v[24:25], v[10:11], v[18:19]
	v_add_f64 v[26:27], v[18:19], -v[32:33]
	v_add_f64 v[30:31], v[12:13], v[20:21]
	v_add_f64 v[32:33], v[20:21], -v[38:39]
	v_mul_f64 v[34:35], v[22:23], s[2:3]
	v_add_f64 v[10:11], v[24:25], -v[10:11]
	v_add_f64 v[16:17], v[16:17], -v[26:27]
	v_mul_f64 v[26:27], v[28:29], s[2:3]
	v_add_f64 v[12:13], v[30:31], -v[12:13]
	v_add_f64 v[14:15], v[14:15], -v[32:33]
	v_fma_f64 v[32:33], v[22:23], s[2:3], -v[34:35]
	v_add_f64 v[10:11], v[18:19], -v[10:11]
	v_add_f64 v[6:7], v[6:7], v[16:17]
	v_fma_f64 v[16:17], v[28:29], s[2:3], -v[26:27]
	v_add_f64 v[12:13], v[20:21], -v[12:13]
	v_add_f64 v[8:9], v[8:9], v[14:15]
	s_mov_b32 s3, 0xbfe62e42
	v_fma_f64 v[14:15], v[22:23], s[4:5], v[32:33]
	v_add_f64 v[6:7], v[6:7], v[10:11]
	v_fma_f64 v[10:11], v[28:29], s[4:5], v[16:17]
	s_mov_b32 s5, 0xbc7abc9e
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[8:9], v[8:9], v[12:13]
	v_add_f64 v[12:13], v[34:35], v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[16:17], v[24:25], v[6:7]
	v_add_f64 v[18:19], v[26:27], v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[20:21], v[30:31], v[8:9]
	v_add_f64 v[34:35], v[12:13], -v[34:35]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[22:23], v[12:13], v[16:17]
	v_add_f64 v[24:25], v[16:17], -v[24:25]
	v_add_f64 v[26:27], v[18:19], -v[26:27]
	v_add_f64 v[28:29], v[18:19], v[20:21]
	v_add_f64 v[30:31], v[20:21], -v[30:31]
	v_add_f64 v[14:15], v[14:15], -v[34:35]
	v_add_f64 v[32:33], v[22:23], -v[12:13]
	v_add_f64 v[6:7], v[6:7], -v[24:25]
	v_add_f64 v[10:11], v[10:11], -v[26:27]
	v_add_f64 v[36:37], v[28:29], -v[18:19]
	v_add_f64 v[8:9], v[8:9], -v[30:31]
	v_add_f64 v[38:39], v[22:23], -v[32:33]
	v_add_f64 v[16:17], v[16:17], -v[32:33]
	v_add_f64 v[24:25], v[14:15], v[6:7]
	v_add_f64 v[40:41], v[28:29], -v[36:37]
	v_add_f64 v[20:21], v[20:21], -v[36:37]
	v_add_f64 v[12:13], v[12:13], -v[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[18:19], -v[40:41]
	v_add_f64 v[12:13], v[16:17], v[12:13]
	v_add_f64 v[16:17], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[18:19], v[20:21], v[18:19]
	v_add_f64 v[20:21], v[24:25], -v[14:15]
	v_add_f64 v[12:13], v[24:25], v[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[26:27], v[16:17], -v[10:11]
	v_add_f64 v[18:19], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[24:25], v[24:25], -v[20:21]
	v_add_f64 v[6:7], v[6:7], -v[20:21]
	v_add_f64 v[30:31], v[22:23], v[12:13]
	v_add_f64 v[16:17], v[16:17], -v[26:27]
	v_add_f64 v[8:9], v[8:9], -v[26:27]
	v_add_f64 v[32:33], v[28:29], v[18:19]
	v_add_f64 v[14:15], v[14:15], -v[24:25]
	v_add_f64 v[20:21], v[30:31], -v[22:23]
	v_add_f64 v[10:11], v[10:11], -v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[16:17], v[32:33], -v[28:29]
	v_add_f64 v[6:7], v[6:7], v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[12:13], v[12:13], -v[20:21]
	v_add_f64 v[8:9], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[18:19], -v[16:17]
	v_add_f64 v[6:7], v[6:7], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[8:9], v[10:11]
	v_add_f64 v[10:11], v[30:31], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[32:33], v[8:9]
	v_add_f64 v[14:15], v[10:11], -v[30:31]
	v_add_f64 v[16:17], v[10:11], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[18:19], v[12:13], -v[32:33]
	v_add_f64 v[20:21], v[12:13], v[12:13]
	v_add_f64 v[6:7], v[6:7], -v[14:15]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[10:11], v[10:11], 2.0, -v[16:17]
	v_cmp_class_f64_e64 vcc_lo, v[16:17], 0x204
	v_add_f64 v[8:9], v[8:9], -v[18:19]
	v_fma_f64 v[12:13], v[12:13], 2.0, -v[20:21]
	v_cmp_class_f64_e64 s0, v[20:21], 0x204
	v_fma_f64 v[6:7], v[6:7], 2.0, v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[8:9], v[8:9], 2.0, v[12:13]
	v_add_f64 v[10:11], v[16:17], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[20:21], v[8:9]
	v_dual_cndmask_b32 v15, v11, v17 :: v_dual_cndmask_b32 v14, v10, v16
	v_add_f64 v[10:11], v[10:11], -v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v19, v13, v21, s0
	v_cndmask_b32_e64 v18, v12, v20, s0
	s_mov_b32 s0, 0xfca7ab0c
	v_mul_f64 v[22:23], v[14:15], s[6:7]
	s_mov_b32 s1, 0x3e928af3
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[14:15]|
	v_mul_f64 v[24:25], v[18:19], s[6:7]
	v_add_f64 v[12:13], v[12:13], -v[20:21]
	v_add_f64 v[6:7], v[6:7], -v[10:11]
	v_rndne_f64_e32 v[22:23], v[22:23]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_rndne_f64_e32 v[24:25], v[24:25]
	v_add_f64 v[8:9], v[8:9], -v[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v7, 0, v7 :: v_dual_cndmask_b32 v6, 0, v6
	v_fma_f64 v[26:27], v[22:23], s[2:3], v[14:15]
	v_cvt_i32_f64_e32 v34, v[22:23]
	v_fma_f64 v[28:29], v[24:25], s[2:3], v[18:19]
	s_mov_b32 s2, 0x6a5dcb37
	s_mov_b32 s3, 0x3e5ade15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[26:27], v[22:23], s[4:5], v[26:27]
	v_fma_f64 v[28:29], v[24:25], s[4:5], v[28:29]
	v_cmp_ngt_f64_e64 s4, 0xc090cc00, v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[30:31], v[26:27], s[2:3], s[0:1]
	v_fma_f64 v[32:33], v[28:29], s[2:3], s[0:1]
	s_mov_b32 s0, 0x623fde64
	s_mov_b32 s1, 0x3ec71dee
	v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[14:15]
	v_cmp_nlt_f64_e64 s3, 0x40900000, v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[30:31], v[26:27], v[30:31], s[0:1]
	v_fma_f64 v[32:33], v[28:29], v[32:33], s[0:1]
	s_mov_b32 s0, 0x7c89e6b0
	s_mov_b32 s1, 0x3efa0199
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[30:31], v[26:27], v[30:31], s[0:1]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[32:33], v[28:29], v[32:33], s[0:1]
	s_mov_b32 s0, 0x14761f6e
	s_mov_b32 s1, 0x3f2a01a0
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[30:31], v[26:27], v[30:31], s[0:1]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[32:33], v[28:29], v[32:33], s[0:1]
	s_mov_b32 s0, 0x1852b7b0
	s_mov_b32 s1, 0x3f56c16c
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[30:31], v[26:27], v[30:31], s[0:1]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[32:33], v[28:29], v[32:33], s[0:1]
	s_mov_b32 s0, 0x11122322
	s_mov_b32 s1, 0x3f811111
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[30:31], v[26:27], v[30:31], s[0:1]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[32:33], v[28:29], v[32:33], s[0:1]
	s_mov_b32 s0, 0x555502a1
	s_mov_b32 s1, 0x3fa55555
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[30:31], v[26:27], v[30:31], s[0:1]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[32:33], v[28:29], v[32:33], s[0:1]
	s_mov_b32 s0, 0x55555511
	s_mov_b32 s1, 0x3fc55555
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[30:31], v[26:27], v[30:31], s[0:1]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[32:33], v[28:29], v[32:33], s[0:1]
	s_mov_b32 s0, 11
	s_mov_b32 s1, 0x3fe00000
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[30:31], v[26:27], v[30:31], s[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[32:33], v[28:29], v[32:33], s[0:1]
	v_cmp_nlt_f64_e64 s1, 0x40900000, v[14:15]
	v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[18:19]|
	v_fma_f64 v[30:31], v[26:27], v[30:31], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[32:33], v[28:29], v[32:33], 1.0
	s_and_b32 vcc_lo, s2, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v9, 0, v9, s0
	v_cndmask_b32_e64 v8, 0, v8, s0
	v_fma_f64 v[22:23], v[26:27], v[30:31], 1.0
	v_cvt_i32_f64_e32 v26, v[24:25]
	v_fma_f64 v[24:25], v[28:29], v[32:33], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[16:17], v[22:23], v34
	v_ldexp_f64 v[20:21], v[24:25], v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, 0x7ff00000, v17, s1
	v_cmp_neq_f64_e64 s1, 0x7ff00000, |v[2:3]|
	v_cndmask_b32_e64 v12, 0x7ff00000, v21, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v11, 0, v10, s2
	v_cndmask_b32_e32 v10, 0, v16, vcc_lo
	s_and_b32 vcc_lo, s4, s3
	v_cndmask_b32_e64 v13, 0, v12, s4
	v_cndmask_b32_e32 v12, 0, v20, vcc_lo
	v_cmp_neq_f64_e64 s3, 0x7ff00000, |v[4:5]|
	v_fma_f64 v[6:7], v[10:11], v[6:7], v[10:11]
	v_cmp_class_f64_e64 vcc_lo, v[10:11], 0x204
	v_cmp_neq_f64_e64 s2, 0, v[2:3]
	v_cmp_neq_f64_e64 s4, 0, v[4:5]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v7, v7, v11 :: v_dual_cndmask_b32 v6, v6, v10
	s_and_b32 vcc_lo, s2, s1
	s_delay_alu instid0(VALU_DEP_1)
	v_and_b32_e32 v7, 0x7fffffff, v7
	v_fma_f64 v[8:9], v[12:13], v[8:9], v[12:13]
	v_cmp_class_f64_e64 s0, v[12:13], 0x204
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	s_and_b32 vcc_lo, s4, s3
	v_cndmask_b32_e64 v7, 0x7ff00000, v7, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v7, 0, v7, s2
	v_cndmask_b32_e64 v9, v9, v13, s0
	v_cndmask_b32_e64 v8, v8, v12, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v8, 0, v8 :: v_dual_and_b32 v9, 0x7fffffff, v9
	v_cndmask_b32_e64 v9, 0x7ff00000, v9, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v9, 0, v9, s4
	v_add_f64 v[6:7], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v6, v[6:7]
	v_mul_f32_e32 v7, 0x4f800000, v6
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, v6, v7, vcc_lo
	v_sqrt_f32_e32 v7, v6
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v8, -1, v7
	v_add_nc_u32_e32 v9, 1, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v10, -v8, v7, v6
	v_fma_f32 v11, -v9, v7, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s0, 0, v10
	v_cndmask_b32_e64 v7, v7, v8, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, 0, v11
	v_cndmask_b32_e64 v7, v7, v9, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v8, 0x37800000, v7
	v_cndmask_b32_e32 v7, v7, v8, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v6, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, v7, v6, vcc_lo
	v_cvt_f64_f32_e32 v[6:7], v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], -v[4:5]
	v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], v[2:3]
	v_div_scale_f64 v[20:21], vcc_lo, -v[4:5], v[6:7], -v[4:5]
	v_rcp_f64_e32 v[12:13], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[14:15], v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
	v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
	v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
	v_div_scale_f64 v[16:17], s0, v[2:3], v[6:7], v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
	v_mul_f64 v[18:19], v[20:21], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[22:23], v[16:17], v[14:15]
	v_fma_f64 v[8:9], -v[8:9], v[18:19], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[10:11], -v[10:11], v[22:23], v[16:17]
	v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19]
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[22:23]
	v_div_fixup_f64 v[4:5], v[8:9], v[6:7], -v[4:5]
	s_delay_alu instid0(VALU_DEP_2)
	v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3]
	v_add_co_u32 v6, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	global_store_b64 v[6:7], v[4:5], off
	global_store_b64 v[0:1], v[2:3], off
.LBB4_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 368
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 46
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii, .Lfunc_end4-_Z14preval_normalsPdS_S_S_S_S_S_S_S_S_S_S_Pii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3900
; NumSgprs: 18
; NumVgprs: 46
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 46
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i ; -- Begin function _Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i
	.globl	_Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i
	.p2align	8
	.type	_Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i,@function
_Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i: ; @_Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x64
	s_load_b32 s3, s[0:1], 0x50
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB5_17
; %bb.1:                                ; %NodeBlock108
	s_clause 0x1
	s_load_b128 s[16:19], s[0:1], 0x40
	s_load_b512 s[0:15], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $vgpr16_vgpr17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_lshlrev_b64 v[5:6], 3, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v7, vcc_lo, s16, v3
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v4, vcc_lo
	v_add_co_u32 v2, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, s19, v4, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v6, vcc_lo
	global_load_b32 v19, v[2:3], off
	v_add_co_u32 v2, vcc_lo, s2, v5
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v6, vcc_lo
	global_load_b32 v18, v[7:8], off
	global_load_b64 v[4:5], v[0:1], off
	global_load_b64 v[6:7], v[2:3], off
	s_mov_b32 s1, 0
	s_mov_b32 s0, exec_lo
                                        ; implicit-def: $vgpr8_vgpr9
	s_waitcnt vmcnt(3)
	v_cmpx_lt_i32_e32 0, v19
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB5_9
; %bb.2:                                ; %NodeBlock
	s_mov_b32 s2, exec_lo
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $vgpr16_vgpr17
	v_cmpx_lt_i32_e32 1, v19
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB5_6
; %bb.3:                                ; %LeafBlock106
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $vgpr16_vgpr17
	v_cmpx_eq_u32_e32 2, v19
	s_cbranch_execz .LBB5_5
; %bb.4:
	s_waitcnt vmcnt(2)
	v_ashrrev_i32_e32 v19, 31, v18
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[16:17], 3, v[18:19]
	v_add_co_u32 v8, vcc_lo, s4, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v17, vcc_lo
	v_add_co_u32 v10, vcc_lo, s12, v16
	v_add_co_ci_u32_e32 v11, vcc_lo, s13, v17, vcc_lo
	global_load_b64 v[8:9], v[8:9], off
	global_load_b64 v[10:11], v[10:11], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], v[8:9], v[10:11]
	v_add_co_u32 v10, vcc_lo, s8, v16
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v17, vcc_lo
	v_add_co_u32 v12, vcc_lo, s10, v16
	v_add_co_ci_u32_e32 v13, vcc_lo, s11, v17, vcc_lo
	v_add_co_u32 v14, vcc_lo, s6, v16
	v_add_co_ci_u32_e32 v15, vcc_lo, s7, v17, vcc_lo
	v_add_co_u32 v16, vcc_lo, s14, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s15, v17, vcc_lo
.LBB5_5:                                ; %Flow112
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s1, s1, exec_lo
                                        ; implicit-def: $vgpr18
.LBB5_6:                                ; %Flow111
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB5_8
; %bb.7:
	s_waitcnt vmcnt(2)
	v_ashrrev_i32_e32 v19, 31, v18
	s_or_b32 s1, s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[16:17], 3, v[18:19]
	v_add_co_u32 v8, vcc_lo, s8, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v17, vcc_lo
	v_add_co_u32 v10, vcc_lo, s12, v16
	v_add_co_ci_u32_e32 v11, vcc_lo, s13, v17, vcc_lo
	global_load_b64 v[8:9], v[8:9], off
	global_load_b64 v[10:11], v[10:11], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], v[8:9], v[10:11]
	v_add_co_u32 v10, vcc_lo, s4, v16
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v17, vcc_lo
	v_add_co_u32 v12, vcc_lo, s6, v16
	v_add_co_ci_u32_e32 v13, vcc_lo, s7, v17, vcc_lo
	v_add_co_u32 v14, vcc_lo, s10, v16
	v_add_co_ci_u32_e32 v15, vcc_lo, s11, v17, vcc_lo
	v_add_co_u32 v16, vcc_lo, s14, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s15, v17, vcc_lo
.LBB5_8:                                ; %Flow113
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s1, s1, exec_lo
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr18
.LBB5_9:                                ; %Flow110
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB5_13
; %bb.10:                               ; %LeafBlock
	s_mov_b32 s3, s1
	s_mov_b32 s2, exec_lo
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $vgpr16_vgpr17
	v_cmpx_eq_u32_e32 0, v19
	s_cbranch_execz .LBB5_12
; %bb.11:
	s_waitcnt vmcnt(2)
	v_ashrrev_i32_e32 v19, 31, v18
	s_or_b32 s3, s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[16:17], 3, v[18:19]
	v_add_co_u32 v8, vcc_lo, s4, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v17, vcc_lo
	v_add_co_u32 v10, vcc_lo, s8, v16
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v17, vcc_lo
	global_load_b64 v[8:9], v[8:9], off
	global_load_b64 v[10:11], v[10:11], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], v[8:9], v[10:11]
	v_add_co_u32 v10, vcc_lo, s12, v16
	v_add_co_ci_u32_e32 v11, vcc_lo, s13, v17, vcc_lo
	v_add_co_u32 v12, vcc_lo, s14, v16
	v_add_co_ci_u32_e32 v13, vcc_lo, s15, v17, vcc_lo
	v_add_co_u32 v14, vcc_lo, s6, v16
	v_add_co_ci_u32_e32 v15, vcc_lo, s7, v17, vcc_lo
	v_add_co_u32 v16, vcc_lo, s10, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s11, v17, vcc_lo
.LBB5_12:                               ; %Flow115
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s1, s1, exec_lo
	s_and_b32 s2, s3, exec_lo
	s_or_b32 s1, s1, s2
.LBB5_13:                               ; %Flow114
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr18_vgpr19
                                        ; implicit-def: $vgpr20_vgpr21
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB5_15
; %bb.14:                               ; %.sink.split
	global_load_b64 v[14:15], v[14:15], off
	global_load_b64 v[16:17], v[16:17], off
	global_load_b64 v[10:11], v[10:11], off
	global_load_b64 v[12:13], v[12:13], off
	s_waitcnt vmcnt(2)
	v_add_f64 v[14:15], v[14:15], v[16:17]
	s_waitcnt vmcnt(1)
	v_fma_f64 v[18:19], v[8:9], -0.5, v[10:11]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[20:21], v[14:15], -0.5, v[12:13]
.LBB5_15:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[4:5], v[18:19]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[6:7], v[6:7], v[20:21], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_f64_e32 vcc_lo, 0, v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB5_17
; %bb.16:
	v_xor_b32_e32 v5, 0x80000000, v5
	global_store_b64 v[0:1], v[4:5], off
	global_load_b64 v[0:1], v[2:3], off
	s_waitcnt vmcnt(0)
	v_xor_b32_e32 v1, 0x80000000, v1
	global_store_b64 v[2:3], v[0:1], off
.LBB5_17:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i, .Lfunc_end5-_Z24preval_normals_directionPdS_S_S_S_S_S_S_PiS0_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 892
; NumSgprs: 22
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i ; -- Begin function _Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i
	.globl	_Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i
	.p2align	8
	.type	_Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i,@function
_Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i: ; @_Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x64
	s_load_b32 s3, s[0:1], 0x50
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB6_2
; %bb.1:
	s_load_b512 s[4:19], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b128 s[0:3], s[0:1], 0x40
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s8, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	global_load_b64 v[6:7], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[2:3], -v[6:7]
	v_add_co_u32 v6, vcc_lo, s16, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s17, v1, vcc_lo
	v_add_co_u32 v8, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v1, vcc_lo
	v_add_co_u32 v10, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo
	global_store_b64 v[6:7], v[2:3], off
	global_load_b64 v[2:3], v[8:9], off
	global_load_b64 v[6:7], v[10:11], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[2:3], -v[6:7]
	v_add_co_u32 v6, vcc_lo, s18, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s19, v1, vcc_lo
	v_add_co_u32 v8, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v1, vcc_lo
	global_store_b64 v[6:7], v[2:3], off
	global_load_b64 v[2:3], v[8:9], off
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[2:3], -v[4:5]
	v_add_co_u32 v4, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v6, vcc_lo, s14, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s15, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b64 v[4:5], v[2:3], off
	global_load_b64 v[2:3], v[6:7], off
	global_load_b64 v[4:5], v[10:11], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[2:3], -v[4:5]
	global_store_b64 v[0:1], v[2:3], off
.LBB6_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i, .Lfunc_end6-_Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 376
; NumSgprs: 22
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
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	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	basis                   ; @basis
	.type	basis,@object
	.section	.bss,"aw",@nobits
	.globl	basis
	.p2align	4, 0x0
basis:
	.zero	16384
	.size	basis, 16384

	.protected	basis_grad_x            ; @basis_grad_x
	.type	basis_grad_x,@object
	.globl	basis_grad_x
	.p2align	4, 0x0
basis_grad_x:
	.zero	16384
	.size	basis_grad_x, 16384

	.protected	basis_grad_y            ; @basis_grad_y
	.type	basis_grad_y,@object
	.globl	basis_grad_y
	.p2align	4, 0x0
basis_grad_y:
	.zero	16384
	.size	basis_grad_y, 16384

	.protected	basis_side              ; @basis_side
	.type	basis_side,@object
	.globl	basis_side
	.p2align	4, 0x0
basis_side:
	.zero	8192
	.size	basis_side, 8192

	.protected	basis_vertex            ; @basis_vertex
	.type	basis_vertex,@object
	.globl	basis_vertex
	.p2align	4, 0x0
basis_vertex:
	.zero	2048
	.size	basis_vertex, 2048

	.protected	w                       ; @w
	.type	w,@object
	.globl	w
	.p2align	4, 0x0
w:
	.zero	256
	.size	w, 256

	.protected	w_oned                  ; @w_oned
	.type	w_oned,@object
	.globl	w_oned
	.p2align	4, 0x0
w_oned:
	.zero	128
	.size	w_oned, 128

	.protected	r1                      ; @r1
	.type	r1,@object
	.globl	r1
	.p2align	4, 0x0
r1:
	.zero	256
	.size	r1, 256

	.protected	r2                      ; @r2
	.type	r2,@object
	.globl	r2
	.p2align	4, 0x0
r2:
	.zero	256
	.size	r2, 256

	.protected	r_oned                  ; @r_oned
	.type	r_oned,@object
	.globl	r_oned
	.p2align	4, 0x0
r_oned:
	.zero	256
	.size	r_oned, 256

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym basis
	.addrsig_sym basis_grad_x
	.addrsig_sym basis_grad_y
	.addrsig_sym basis_side
	.addrsig_sym basis_vertex
	.addrsig_sym w
	.addrsig_sym w_oned
	.addrsig_sym r1
	.addrsig_sym r2
	.addrsig_sym r_oned
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
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        .value_kind:     hidden_remainder_z
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         152
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 344
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z15preval_partialsPdS_S_S_S_S_S_S_S_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
