/*
 * Copyright (C) 2018 Philip Langdale <philipl@overt.org>
 *
 * This file is part of FFmpeg.
 *
 * FFmpeg is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * FFmpeg is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with FFmpeg; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
 */

template<typename T>
__inline__ __device__ T spatial_predictor(T a, T b, T c, T d, T e, T f, T g,
                                          T h, T i, T j, T k, T l, T m, T n)
{
    int spatial_pred = (d + k)/2;
    int spatial_score = abs(c - j) + abs(d - k) + abs(e - l);

    int score = abs(b - k) + abs(c - l) + abs(d - m);
    if (score < spatial_score) {
        spatial_pred = (c + l)/2;
        spatial_score = score;
        score = abs(a - l) + abs(b - m) + abs(c - n);
        if (score < spatial_score) {
          spatial_pred = (b + m)/2;
          spatial_score = score;
        }
    }
    score = abs(d - i) + abs(e - j) + abs(f - k);
    if (score < spatial_score) {
        spatial_pred = (e + j)/2;
        spatial_score = score;
        score = abs(e - h) + abs(f - i) + abs(g - j);
        if (score < spatial_score) {
          spatial_pred = (f + i)/2;
          spatial_score = score;
        }
    }
    return spatial_pred;
}

__inline__ __device__ int max3(int a, int b, int c)
{
    int x = max(a, b);
    return max(x, c);
}

__inline__ __device__ int min3(int a, int b, int c)
{
    int x = min(a, b);
    return min(x, c);
}

template<typename T>
__inline__ __device__ T temporal_predictor(T A, T B, T C, T D, T E, T F,
                                           T G, T H, T I, T J, T K, T L,
                                           T spatial_pred, bool skip_check)
{
    int p0 = (C + H) / 2;
    int p1 = F;
    int p2 = (D + I) / 2;
    int p3 = G;
    int p4 = (E + J) / 2;

    int tdiff0 = abs(D - I);
    int tdiff1 = (abs(A - F) + abs(B - G)) / 2;
    int tdiff2 = (abs(K - F) + abs(G - L)) / 2;

    int diff = max3(tdiff0, tdiff1, tdiff2);

    if (!skip_check) {
      int maxi = max3(p2 - p3, p2 - p1, min(p0 - p1, p4 - p3));
      int mini = min3(p2 - p3, p2 - p1, max(p0 - p1, p4 - p3));
      diff = max3(diff, mini, -maxi);
    }

    if (spatial_pred > p2 + diff) {
      spatial_pred = p2 + diff;
    }
    if (spatial_pred < p2 - diff) {
      spatial_pred = p2 - diff;
    }

    return spatial_pred;
}

template<typename T>
__inline__ __device__ void yadif_single(T *dst,
                                        cudaTextureObject_t prev,
                                        cudaTextureObject_t cur,
                                        cudaTextureObject_t next,
                                        int dst_width, int dst_height, int dst_pitch,
                                        int src_width, int src_height,
                                        int parity, int tff, bool skip_spatial_check)
{
    // Identify location
    int xo = blockIdx.x * blockDim.x + threadIdx.x;
    int yo = blockIdx.y * blockDim.y + threadIdx.y;

    if (xo >= dst_width || yo >= dst_height) {
        return;
    }

    // Don't modify the primary field
    if (yo % 2 == parity) {
      dst[yo*dst_pitch+xo] = tex2D<T>(cur, xo, yo);
      return;
    }

    // Calculate spatial prediction
    T a = tex2D<T>(cur, xo - 3, yo - 1);
    T b = tex2D<T>(cur, xo - 2, yo - 1);
    T c = tex2D<T>(cur, xo - 1, yo - 1);
    T d = tex2D<T>(cur, xo - 0, yo - 1);
    T e = tex2D<T>(cur, xo + 1, yo - 1);
    T f = tex2D<T>(cur, xo + 2, yo - 1);
    T g = tex2D<T>(cur, xo + 3, yo - 1);

    T h = tex2D<T>(cur, xo - 3, yo + 1);
    T i = tex2D<T>(cur, xo - 2, yo + 1);
    T j = tex2D<T>(cur, xo - 1, yo + 1);
    T k = tex2D<T>(cur, xo - 0, yo + 1);
    T l = tex2D<T>(cur, xo + 1, yo + 1);
    T m = tex2D<T>(cur, xo + 2, yo + 1);
    T n = tex2D<T>(cur, xo + 3, yo + 1);

    T spatial_pred =
        spatial_predictor(a, b, c, d, e, f, g, h, i, j, k, l, m, n);

    // Calculate temporal prediction
    int is_second_field = !(parity ^ tff);

    cudaTextureObject_t prev2 = prev;
    cudaTextureObject_t prev1 = is_second_field ? cur : prev;
    cudaTextureObject_t next1 = is_second_field ? next : cur;
    cudaTextureObject_t next2 = next;

    T A = tex2D<T>(prev2, xo,  yo - 1);
    T B = tex2D<T>(prev2, xo,  yo + 1);
    T C = tex2D<T>(prev1, xo,  yo - 2);
    T D = tex2D<T>(prev1, xo,  yo + 0);
    T E = tex2D<T>(prev1, xo,  yo + 2);
    T F = tex2D<T>(cur,   xo,  yo - 1);
    T G = tex2D<T>(cur,   xo,  yo + 1);
    T H = tex2D<T>(next1, xo,  yo - 2);
    T I = tex2D<T>(next1, xo,  yo + 0);
    T J = tex2D<T>(next1, xo,  yo + 2);
    T K = tex2D<T>(next2, xo,  yo - 1);
    T L = tex2D<T>(next2, xo,  yo + 1);

    spatial_pred = temporal_predictor(A, B, C, D, E, F, G, H, I, J, K, L,
                                      spatial_pred, skip_spatial_check);

    dst[yo*dst_pitch+xo] = spatial_pred;
}

template <typename T>
__inline__ __device__ void yadif_double(T *dst,
                                        cudaTextureObject_t prev,
                                        cudaTextureObject_t cur,
                                        cudaTextureObject_t next,
                                        int dst_width, int dst_height, int dst_pitch,
                                        int src_width, int src_height,
                                        int parity, int tff, bool skip_spatial_check)
{
    int xo = blockIdx.x * blockDim.x + threadIdx.x;
    int yo = blockIdx.y * blockDim.y + threadIdx.y;

    if (xo >= dst_width || yo >= dst_height) {
        return;
    }

    if (yo % 2 == parity) {
      // Don't modify the primary field
      dst[yo*dst_pitch+xo] = tex2D<T>(cur, xo, yo);
      return;
    }

    T a = tex2D<T>(cur, xo - 3, yo - 1);
    T b = tex2D<T>(cur, xo - 2, yo - 1);
    T c = tex2D<T>(cur, xo - 1, yo - 1);
    T d = tex2D<T>(cur, xo - 0, yo - 1);
    T e = tex2D<T>(cur, xo + 1, yo - 1);
    T f = tex2D<T>(cur, xo + 2, yo - 1);
    T g = tex2D<T>(cur, xo + 3, yo - 1);

    T h = tex2D<T>(cur, xo - 3, yo + 1);
    T i = tex2D<T>(cur, xo - 2, yo + 1);
    T j = tex2D<T>(cur, xo - 1, yo + 1);
    T k = tex2D<T>(cur, xo - 0, yo + 1);
    T l = tex2D<T>(cur, xo + 1, yo + 1);
    T m = tex2D<T>(cur, xo + 2, yo + 1);
    T n = tex2D<T>(cur, xo + 3, yo + 1);

    T spatial_pred;
    spatial_pred.x =
        spatial_predictor(a.x, b.x, c.x, d.x, e.x, f.x, g.x, h.x, i.x, j.x, k.x, l.x, m.x, n.x);
    spatial_pred.y =
        spatial_predictor(a.y, b.y, c.y, d.y, e.y, f.y, g.y, h.y, i.y, j.y, k.y, l.y, m.y, n.y);

    // Calculate temporal prediction
    int is_second_field = !(parity ^ tff);

    cudaTextureObject_t prev2 = prev;
    cudaTextureObject_t prev1 = is_second_field ? cur : prev;
    cudaTextureObject_t next1 = is_second_field ? next : cur;
    cudaTextureObject_t next2 = next;

    T A = tex2D<T>(prev2, xo,  yo - 1);
    T B = tex2D<T>(prev2, xo,  yo + 1);
    T C = tex2D<T>(prev1, xo,  yo - 2);
    T D = tex2D<T>(prev1, xo,  yo + 0);
    T E = tex2D<T>(prev1, xo,  yo + 2);
    T F = tex2D<T>(cur,   xo,  yo - 1);
    T G = tex2D<T>(cur,   xo,  yo + 1);
    T H = tex2D<T>(next1, xo,  yo - 2);
    T I = tex2D<T>(next1, xo,  yo + 0);
    T J = tex2D<T>(next1, xo,  yo + 2);
    T K = tex2D<T>(next2, xo,  yo - 1);
    T L = tex2D<T>(next2, xo,  yo + 1);

    spatial_pred.x =
        temporal_predictor(A.x, B.x, C.x, D.x, E.x, F.x, G.x, H.x, I.x, J.x, K.x, L.x,
                           spatial_pred.x, skip_spatial_check);
    spatial_pred.y =
        temporal_predictor(A.y, B.y, C.y, D.y, E.y, F.y, G.y, H.y, I.y, J.y, K.y, L.y,
                           spatial_pred.y, skip_spatial_check);

    dst[yo*dst_pitch+xo] = spatial_pred;
}

extern "C" {

__global__ void yadif_uchar(unsigned char *dst,
                            cudaTextureObject_t prev,
                            cudaTextureObject_t cur,
                            cudaTextureObject_t next,
                            int dst_width, int dst_height, int dst_pitch,
                            int src_width, int src_height,
                            int parity, int tff, bool skip_spatial_check)
{
    yadif_single(dst, prev, cur, next,
                 dst_width, dst_height, dst_pitch,
                 src_width, src_height,
                 parity, tff, skip_spatial_check);
}

__global__ void yadif_ushort(unsigned short *dst,
                            cudaTextureObject_t prev,
                            cudaTextureObject_t cur,
                            cudaTextureObject_t next,
                            int dst_width, int dst_height, int dst_pitch,
                            int src_width, int src_height,
                            int parity, int tff, bool skip_spatial_check)
{
    yadif_single(dst, prev, cur, next,
                 dst_width, dst_height, dst_pitch,
                 src_width, src_height,
                 parity, tff, skip_spatial_check);
}

__global__ void yadif_uchar2(uchar2 *dst,
                            cudaTextureObject_t prev,
                            cudaTextureObject_t cur,
                            cudaTextureObject_t next,
                            int dst_width, int dst_height, int dst_pitch,
                            int src_width, int src_height,
                            int parity, int tff, bool skip_spatial_check)
{
    yadif_double(dst, prev, cur, next,
                 dst_width, dst_height, dst_pitch,
                 src_width, src_height,
                 parity, tff, skip_spatial_check);
}

__global__ void yadif_ushort2(ushort2 *dst,
                            cudaTextureObject_t prev,
                            cudaTextureObject_t cur,
                            cudaTextureObject_t next,
                            int dst_width, int dst_height, int dst_pitch,
                            int src_width, int src_height,
                            int parity, int tff, bool skip_spatial_check)
{
    yadif_double(dst, prev, cur, next,
                 dst_width, dst_height, dst_pitch,
                 src_width, src_height,
                 parity, tff, skip_spatial_check);
}

} /* extern "C" */

	.file	"tmpxft_00323be5_00000000-6_vf_yadif_cuda.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2016:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2016:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z42__device_stub__Z11yadif_ucharPhyyyiiiiiiibPhyyyiiiiiiib
	.type	_Z42__device_stub__Z11yadif_ucharPhyyyiiiiiiibPhyyyiiiiiiib, @function
_Z42__device_stub__Z11yadif_ucharPhyyyiiiiiiibPhyyyiiiiiiib:
.LFB2038:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movl	280(%rsp), %eax
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movb	%al, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 248
	leaq	yadif_uchar(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 256
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L2:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2038:
	.size	_Z42__device_stub__Z11yadif_ucharPhyyyiiiiiiibPhyyyiiiiiiib, .-_Z42__device_stub__Z11yadif_ucharPhyyyiiiiiiibPhyyyiiiiiiib
	.globl	yadif_uchar
	.type	yadif_uchar, @function
yadif_uchar:
.LFB2039:
	.cfi_startproc
	endbr64
	movzbl	48(%rsp), %eax
	movl	%eax, 48(%rsp)
	jmp	_Z42__device_stub__Z11yadif_ucharPhyyyiiiiiiibPhyyyiiiiiiib
	.cfi_endproc
.LFE2039:
	.size	yadif_uchar, .-yadif_uchar
	.globl	_Z43__device_stub__Z12yadif_ushortPtyyyiiiiiiibPtyyyiiiiiiib
	.type	_Z43__device_stub__Z12yadif_ushortPtyyyiiiiiiibPtyyyiiiiiiib, @function
_Z43__device_stub__Z12yadif_ushortPtyyyiiiiiiibPtyyyiiiiiiib:
.LFB2040:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movl	280(%rsp), %eax
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movb	%al, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	64(%rsp)
	.cfi_def_cfa_offset 248
	leaq	yadif_ushort(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 256
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L8:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	_Z43__device_stub__Z12yadif_ushortPtyyyiiiiiiibPtyyyiiiiiiib, .-_Z43__device_stub__Z12yadif_ushortPtyyyiiiiiiibPtyyyiiiiiiib
	.globl	yadif_ushort
	.type	yadif_ushort, @function
yadif_ushort:
.LFB2041:
	.cfi_startproc
	endbr64
	movzbl	48(%rsp), %eax
	movl	%eax, 48(%rsp)
	jmp	_Z43__device_stub__Z12yadif_ushortPtyyyiiiiiiibPtyyyiiiiiiib
	.cfi_endproc
.LFE2041:
	.size	yadif_ushort, .-yadif_ushort
	.globl	_Z49__device_stub__Z12yadif_uchar2P6uchar2yyyiiiiiiibP6uchar2yyyiiiiiiib
	.type	_Z49__device_stub__Z12yadif_uchar2P6uchar2yyyiiiiiiibP6uchar2yyyiiiiiiib, @function
_Z49__device_stub__Z12yadif_uchar2P6uchar2yyyiiiiiiibP6uchar2yyyiiiiiiib:
.LFB2042:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movl	280(%rsp), %eax
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movb	%al, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	64(%rsp)
	.cfi_def_cfa_offset 248
	leaq	yadif_uchar2(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 256
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L13:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2042:
	.size	_Z49__device_stub__Z12yadif_uchar2P6uchar2yyyiiiiiiibP6uchar2yyyiiiiiiib, .-_Z49__device_stub__Z12yadif_uchar2P6uchar2yyyiiiiiiibP6uchar2yyyiiiiiiib
	.globl	yadif_uchar2
	.type	yadif_uchar2, @function
yadif_uchar2:
.LFB2043:
	.cfi_startproc
	endbr64
	movzbl	48(%rsp), %eax
	movl	%eax, 48(%rsp)
	jmp	_Z49__device_stub__Z12yadif_uchar2P6uchar2yyyiiiiiiibP6uchar2yyyiiiiiiib
	.cfi_endproc
.LFE2043:
	.size	yadif_uchar2, .-yadif_uchar2
	.globl	_Z51__device_stub__Z13yadif_ushort2P7ushort2yyyiiiiiiibP7ushort2yyyiiiiiiib
	.type	_Z51__device_stub__Z13yadif_ushort2P7ushort2yyyiiiiiiibP7ushort2yyyiiiiiiib, @function
_Z51__device_stub__Z13yadif_ushort2P7ushort2yyyiiiiiiibP7ushort2yyyiiiiiiib:
.LFB2044:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movl	280(%rsp), %eax
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movb	%al, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	64(%rsp)
	.cfi_def_cfa_offset 248
	leaq	yadif_ushort2(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 256
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L18:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2044:
	.size	_Z51__device_stub__Z13yadif_ushort2P7ushort2yyyiiiiiiibP7ushort2yyyiiiiiiib, .-_Z51__device_stub__Z13yadif_ushort2P7ushort2yyyiiiiiiibP7ushort2yyyiiiiiiib
	.globl	yadif_ushort2
	.type	yadif_ushort2, @function
yadif_ushort2:
.LFB2045:
	.cfi_startproc
	endbr64
	movzbl	48(%rsp), %eax
	movl	%eax, 48(%rsp)
	jmp	_Z51__device_stub__Z13yadif_ushort2P7ushort2yyyiiiiiiibP7ushort2yyyiiiiiiib
	.cfi_endproc
.LFE2045:
	.size	yadif_ushort2, .-yadif_ushort2
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"yadif_ushort2"
.LC1:
	.string	"yadif_uchar2"
.LC2:
	.string	"yadif_ushort"
.LC3:
	.string	"yadif_uchar"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2047:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	yadif_ushort2(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	yadif_uchar2(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	yadif_ushort(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	yadif_uchar(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2047:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
/*
 * Copyright (C) 2018 Philip Langdale <philipl@overt.org>
 *
 * This file is part of FFmpeg.
 *
 * FFmpeg is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * FFmpeg is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with FFmpeg; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
 */

template<typename T>
__inline__ __device__ T spatial_predictor(T a, T b, T c, T d, T e, T f, T g,
                                          T h, T i, T j, T k, T l, T m, T n)
{
    int spatial_pred = (d + k)/2;
    int spatial_score = abs(c - j) + abs(d - k) + abs(e - l);

    int score = abs(b - k) + abs(c - l) + abs(d - m);
    if (score < spatial_score) {
        spatial_pred = (c + l)/2;
        spatial_score = score;
        score = abs(a - l) + abs(b - m) + abs(c - n);
        if (score < spatial_score) {
          spatial_pred = (b + m)/2;
          spatial_score = score;
        }
    }
    score = abs(d - i) + abs(e - j) + abs(f - k);
    if (score < spatial_score) {
        spatial_pred = (e + j)/2;
        spatial_score = score;
        score = abs(e - h) + abs(f - i) + abs(g - j);
        if (score < spatial_score) {
          spatial_pred = (f + i)/2;
          spatial_score = score;
        }
    }
    return spatial_pred;
}

__inline__ __device__ int max3(int a, int b, int c)
{
    int x = max(a, b);
    return max(x, c);
}

__inline__ __device__ int min3(int a, int b, int c)
{
    int x = min(a, b);
    return min(x, c);
}

template<typename T>
__inline__ __device__ T temporal_predictor(T A, T B, T C, T D, T E, T F,
                                           T G, T H, T I, T J, T K, T L,
                                           T spatial_pred, bool skip_check)
{
    int p0 = (C + H) / 2;
    int p1 = F;
    int p2 = (D + I) / 2;
    int p3 = G;
    int p4 = (E + J) / 2;

    int tdiff0 = abs(D - I);
    int tdiff1 = (abs(A - F) + abs(B - G)) / 2;
    int tdiff2 = (abs(K - F) + abs(G - L)) / 2;

    int diff = max3(tdiff0, tdiff1, tdiff2);

    if (!skip_check) {
      int maxi = max3(p2 - p3, p2 - p1, min(p0 - p1, p4 - p3));
      int mini = min3(p2 - p3, p2 - p1, max(p0 - p1, p4 - p3));
      diff = max3(diff, mini, -maxi);
    }

    if (spatial_pred > p2 + diff) {
      spatial_pred = p2 + diff;
    }
    if (spatial_pred < p2 - diff) {
      spatial_pred = p2 - diff;
    }

    return spatial_pred;
}

template<typename T>
__inline__ __device__ void yadif_single(T *dst,
                                        hipTextureObject_t prev,
                                        hipTextureObject_t cur,
                                        hipTextureObject_t next,
                                        int dst_width, int dst_height, int dst_pitch,
                                        int src_width, int src_height,
                                        int parity, int tff, bool skip_spatial_check)
{
    // Identify location
    int xo = blockIdx.x * blockDim.x + threadIdx.x;
    int yo = blockIdx.y * blockDim.y + threadIdx.y;

    if (xo >= dst_width || yo >= dst_height) {
        return;
    }

    // Don't modify the primary field
    if (yo % 2 == parity) {
      dst[yo*dst_pitch+xo] = tex2D<T>(cur, xo, yo);
      return;
    }

    // Calculate spatial prediction
    T a = tex2D<T>(cur, xo - 3, yo - 1);
    T b = tex2D<T>(cur, xo - 2, yo - 1);
    T c = tex2D<T>(cur, xo - 1, yo - 1);
    T d = tex2D<T>(cur, xo - 0, yo - 1);
    T e = tex2D<T>(cur, xo + 1, yo - 1);
    T f = tex2D<T>(cur, xo + 2, yo - 1);
    T g = tex2D<T>(cur, xo + 3, yo - 1);

    T h = tex2D<T>(cur, xo - 3, yo + 1);
    T i = tex2D<T>(cur, xo - 2, yo + 1);
    T j = tex2D<T>(cur, xo - 1, yo + 1);
    T k = tex2D<T>(cur, xo - 0, yo + 1);
    T l = tex2D<T>(cur, xo + 1, yo + 1);
    T m = tex2D<T>(cur, xo + 2, yo + 1);
    T n = tex2D<T>(cur, xo + 3, yo + 1);

    T spatial_pred =
        spatial_predictor(a, b, c, d, e, f, g, h, i, j, k, l, m, n);

    // Calculate temporal prediction
    int is_second_field = !(parity ^ tff);

    hipTextureObject_t prev2 = prev;
    hipTextureObject_t prev1 = is_second_field ? cur : prev;
    hipTextureObject_t next1 = is_second_field ? next : cur;
    hipTextureObject_t next2 = next;

    T A = tex2D<T>(prev2, xo,  yo - 1);
    T B = tex2D<T>(prev2, xo,  yo + 1);
    T C = tex2D<T>(prev1, xo,  yo - 2);
    T D = tex2D<T>(prev1, xo,  yo + 0);
    T E = tex2D<T>(prev1, xo,  yo + 2);
    T F = tex2D<T>(cur,   xo,  yo - 1);
    T G = tex2D<T>(cur,   xo,  yo + 1);
    T H = tex2D<T>(next1, xo,  yo - 2);
    T I = tex2D<T>(next1, xo,  yo + 0);
    T J = tex2D<T>(next1, xo,  yo + 2);
    T K = tex2D<T>(next2, xo,  yo - 1);
    T L = tex2D<T>(next2, xo,  yo + 1);

    spatial_pred = temporal_predictor(A, B, C, D, E, F, G, H, I, J, K, L,
                                      spatial_pred, skip_spatial_check);

    dst[yo*dst_pitch+xo] = spatial_pred;
}

template <typename T>
__inline__ __device__ void yadif_double(T *dst,
                                        hipTextureObject_t prev,
                                        hipTextureObject_t cur,
                                        hipTextureObject_t next,
                                        int dst_width, int dst_height, int dst_pitch,
                                        int src_width, int src_height,
                                        int parity, int tff, bool skip_spatial_check)
{
    int xo = blockIdx.x * blockDim.x + threadIdx.x;
    int yo = blockIdx.y * blockDim.y + threadIdx.y;

    if (xo >= dst_width || yo >= dst_height) {
        return;
    }

    if (yo % 2 == parity) {
      // Don't modify the primary field
      dst[yo*dst_pitch+xo] = tex2D<T>(cur, xo, yo);
      return;
    }

    T a = tex2D<T>(cur, xo - 3, yo - 1);
    T b = tex2D<T>(cur, xo - 2, yo - 1);
    T c = tex2D<T>(cur, xo - 1, yo - 1);
    T d = tex2D<T>(cur, xo - 0, yo - 1);
    T e = tex2D<T>(cur, xo + 1, yo - 1);
    T f = tex2D<T>(cur, xo + 2, yo - 1);
    T g = tex2D<T>(cur, xo + 3, yo - 1);

    T h = tex2D<T>(cur, xo - 3, yo + 1);
    T i = tex2D<T>(cur, xo - 2, yo + 1);
    T j = tex2D<T>(cur, xo - 1, yo + 1);
    T k = tex2D<T>(cur, xo - 0, yo + 1);
    T l = tex2D<T>(cur, xo + 1, yo + 1);
    T m = tex2D<T>(cur, xo + 2, yo + 1);
    T n = tex2D<T>(cur, xo + 3, yo + 1);

    T spatial_pred;
    spatial_pred.x =
        spatial_predictor(a.x, b.x, c.x, d.x, e.x, f.x, g.x, h.x, i.x, j.x, k.x, l.x, m.x, n.x);
    spatial_pred.y =
        spatial_predictor(a.y, b.y, c.y, d.y, e.y, f.y, g.y, h.y, i.y, j.y, k.y, l.y, m.y, n.y);

    // Calculate temporal prediction
    int is_second_field = !(parity ^ tff);

    hipTextureObject_t prev2 = prev;
    hipTextureObject_t prev1 = is_second_field ? cur : prev;
    hipTextureObject_t next1 = is_second_field ? next : cur;
    hipTextureObject_t next2 = next;

    T A = tex2D<T>(prev2, xo,  yo - 1);
    T B = tex2D<T>(prev2, xo,  yo + 1);
    T C = tex2D<T>(prev1, xo,  yo - 2);
    T D = tex2D<T>(prev1, xo,  yo + 0);
    T E = tex2D<T>(prev1, xo,  yo + 2);
    T F = tex2D<T>(cur,   xo,  yo - 1);
    T G = tex2D<T>(cur,   xo,  yo + 1);
    T H = tex2D<T>(next1, xo,  yo - 2);
    T I = tex2D<T>(next1, xo,  yo + 0);
    T J = tex2D<T>(next1, xo,  yo + 2);
    T K = tex2D<T>(next2, xo,  yo - 1);
    T L = tex2D<T>(next2, xo,  yo + 1);

    spatial_pred.x =
        temporal_predictor(A.x, B.x, C.x, D.x, E.x, F.x, G.x, H.x, I.x, J.x, K.x, L.x,
                           spatial_pred.x, skip_spatial_check);
    spatial_pred.y =
        temporal_predictor(A.y, B.y, C.y, D.y, E.y, F.y, G.y, H.y, I.y, J.y, K.y, L.y,
                           spatial_pred.y, skip_spatial_check);

    dst[yo*dst_pitch+xo] = spatial_pred;
}

extern "C" {

__global__ void yadif_uchar(unsigned char *dst,
                            hipTextureObject_t prev,
                            hipTextureObject_t cur,
                            hipTextureObject_t next,
                            int dst_width, int dst_height, int dst_pitch,
                            int src_width, int src_height,
                            int parity, int tff, bool skip_spatial_check)
{
    yadif_single(dst, prev, cur, next,
                 dst_width, dst_height, dst_pitch,
                 src_width, src_height,
                 parity, tff, skip_spatial_check);
}

__global__ void yadif_ushort(unsigned short *dst,
                            hipTextureObject_t prev,
                            hipTextureObject_t cur,
                            hipTextureObject_t next,
                            int dst_width, int dst_height, int dst_pitch,
                            int src_width, int src_height,
                            int parity, int tff, bool skip_spatial_check)
{
    yadif_single(dst, prev, cur, next,
                 dst_width, dst_height, dst_pitch,
                 src_width, src_height,
                 parity, tff, skip_spatial_check);
}

__global__ void yadif_uchar2(uchar2 *dst,
                            hipTextureObject_t prev,
                            hipTextureObject_t cur,
                            hipTextureObject_t next,
                            int dst_width, int dst_height, int dst_pitch,
                            int src_width, int src_height,
                            int parity, int tff, bool skip_spatial_check)
{
    yadif_double(dst, prev, cur, next,
                 dst_width, dst_height, dst_pitch,
                 src_width, src_height,
                 parity, tff, skip_spatial_check);
}

__global__ void yadif_ushort2(ushort2 *dst,
                            hipTextureObject_t prev,
                            hipTextureObject_t cur,
                            hipTextureObject_t next,
                            int dst_width, int dst_height, int dst_pitch,
                            int src_width, int src_height,
                            int parity, int tff, bool skip_spatial_check)
{
    yadif_double(dst, prev, cur, next,
                 dst_width, dst_height, dst_pitch,
                 src_width, src_height,
                 parity, tff, skip_spatial_check);
}

} /* extern "C" */

	.text
	.file	"vf_yadif_cuda.hip"
	.globl	__device_stub__yadif_uchar      # -- Begin function __device_stub__yadif_uchar
	.type	__device_stub__yadif_uchar,@function
__device_stub__yadif_uchar:             # @__device_stub__yadif_uchar
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movb	280(%rsp), %al
	leaq	56(%rsp), %r10
	movq	%rdi, (%r10)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	7(%rsp), %r9
	movb	%al, (%r9)
	leaq	96(%rsp), %rbx
	movq	%r10, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	movq	%r9, 88(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$yadif_uchar, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__yadif_uchar, .Lfunc_end0-__device_stub__yadif_uchar
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__yadif_ushort     # -- Begin function __device_stub__yadif_ushort
	.type	__device_stub__yadif_ushort,@function
__device_stub__yadif_ushort:            # @__device_stub__yadif_ushort
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movb	280(%rsp), %al
	leaq	56(%rsp), %r10
	movq	%rdi, (%r10)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	7(%rsp), %r9
	movb	%al, (%r9)
	leaq	96(%rsp), %rbx
	movq	%r10, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	movq	%r9, 88(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$yadif_ushort, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	__device_stub__yadif_ushort, .Lfunc_end1-__device_stub__yadif_ushort
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__yadif_uchar2     # -- Begin function __device_stub__yadif_uchar2
	.type	__device_stub__yadif_uchar2,@function
__device_stub__yadif_uchar2:            # @__device_stub__yadif_uchar2
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movb	280(%rsp), %al
	leaq	56(%rsp), %r10
	movq	%rdi, (%r10)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	7(%rsp), %r9
	movb	%al, (%r9)
	leaq	96(%rsp), %rbx
	movq	%r10, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	movq	%r9, 88(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$yadif_uchar2, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	__device_stub__yadif_uchar2, .Lfunc_end2-__device_stub__yadif_uchar2
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__yadif_ushort2    # -- Begin function __device_stub__yadif_ushort2
	.type	__device_stub__yadif_ushort2,@function
__device_stub__yadif_ushort2:           # @__device_stub__yadif_ushort2
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movb	280(%rsp), %al
	leaq	56(%rsp), %r10
	movq	%rdi, (%r10)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	7(%rsp), %r9
	movb	%al, (%r9)
	leaq	96(%rsp), %rbx
	movq	%r10, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	movq	%r9, 88(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$yadif_ushort2, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	__device_stub__yadif_ushort2, .Lfunc_end3-__device_stub__yadif_ushort2
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$yadif_uchar, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$yadif_ushort, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$yadif_uchar2, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$yadif_ushort2, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	yadif_uchar,@object             # @yadif_uchar
	.section	.rodata,"a",@progbits
	.globl	yadif_uchar
	.p2align	3, 0x0
yadif_uchar:
	.quad	__device_stub__yadif_uchar
	.size	yadif_uchar, 8

	.type	yadif_ushort,@object            # @yadif_ushort
	.globl	yadif_ushort
	.p2align	3, 0x0
yadif_ushort:
	.quad	__device_stub__yadif_ushort
	.size	yadif_ushort, 8

	.type	yadif_uchar2,@object            # @yadif_uchar2
	.globl	yadif_uchar2
	.p2align	3, 0x0
yadif_uchar2:
	.quad	__device_stub__yadif_uchar2
	.size	yadif_uchar2, 8

	.type	yadif_ushort2,@object           # @yadif_ushort2
	.globl	yadif_ushort2
	.p2align	3, 0x0
yadif_ushort2:
	.quad	__device_stub__yadif_ushort2
	.size	yadif_ushort2, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"yadif_uchar"
	.size	.L__unnamed_1, 12

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"yadif_ushort"
	.size	.L__unnamed_2, 13

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"yadif_uchar2"
	.size	.L__unnamed_3, 13

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"yadif_ushort2"
	.size	.L__unnamed_4, 14

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__yadif_uchar
	.addrsig_sym __device_stub__yadif_ushort
	.addrsig_sym __device_stub__yadif_uchar2
	.addrsig_sym __device_stub__yadif_ushort2
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym yadif_uchar
	.addrsig_sym yadif_ushort
	.addrsig_sym yadif_uchar2
	.addrsig_sym yadif_ushort2
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	yadif_uchar             ; -- Begin function yadif_uchar
	.globl	yadif_uchar
	.p2align	8
	.type	yadif_uchar,@function
yadif_uchar:                            ; @yadif_uchar
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b128 s[4:7], s[0:1], 0x20
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	v_cmp_gt_i32_e64 s2, s5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_12
; %bb.1:
	s_load_b128 s[36:39], s[0:1], 0x34
	v_lshrrev_b32_e32 v2, 31, v1
	s_load_b256 s[8:15], s[0:1], 0x0
	v_cvt_f32_i32_e32 v8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v1, v2
	v_and_b32_e32 v2, -2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v1, v2
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, s36, v2
                                        ; implicit-def: $vgpr2
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s5, exec_lo, s0
	s_cbranch_execz .LBB0_9
; %bb.2:
	s_clause 0x2
	s_load_b128 s[24:27], s[12:13], 0x30
	s_load_b256 s[16:23], s[12:13], 0x0
	s_load_b32 s1, s[12:13], 0x28
	s_waitcnt lgkmcnt(0)
	s_bitcmp0_b32 s26, 20
	s_cselect_b32 vcc_lo, -1, 0
	s_bitcmp0_b32 s24, 15
	s_cselect_b32 s0, -1, 0
	s_bfe_u32 s2, s18, 0xe000e
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, 1
	v_cvt_f32_u32_e32 v9, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v9, 1.0, v9, s0
	v_add_nc_u32_e32 v2, -1, v1
	v_cvt_f32_i32_e32 v10, v2
	v_add_nc_u32_e32 v2, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v15, v2
	v_add_nc_u32_e32 v3, -2, v0
	v_rcp_f32_e32 v2, v9
	v_cvt_f32_i32_e32 v11, v3
	v_cvt_f32_u32_e32 v3, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v16, 1.0, v3, s0
	v_add_nc_u32_e32 v7, 1, v1
	v_dual_mul_f32 v3, v9, v10 :: v_dual_add_nc_u32 v4, -1, v0
	s_mov_b32 s0, exec_lo
	v_rcp_f32_e32 v26, v16
	v_mul_f32_e32 v14, v16, v8
	v_cvt_f32_i32_e32 v12, v7
	v_mul_f32_e32 v7, v16, v11
	v_cvt_f32_i32_e32 v4, v4
	v_floor_f32_e32 v3, v3
	v_floor_f32_e32 v14, v14
	v_add_nc_u32_e32 v5, 1, v0
	v_add_nc_u32_e32 v6, 3, v0
	v_mul_f32_e32 v9, v9, v12
	v_floor_f32_e32 v7, v7
	v_mul_f32_e32 v14, v26, v14
	v_cvt_f32_i32_e32 v5, v5
	v_mul_f32_e32 v3, v2, v3
	v_cvt_f32_i32_e32 v6, v6
	v_floor_f32_e32 v9, v9
	v_dual_mul_f32 v7, v26, v7 :: v_dual_cndmask_b32 v20, v8, v14
	v_mul_f32_e32 v17, v16, v5
	v_mul_f32_e32 v13, v16, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v18, v16, v15 :: v_dual_mul_f32 v9, v2, v9
	v_cndmask_b32_e32 v2, v11, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_floor_f32_e32 v17, v17
	v_floor_f32_e32 v13, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_floor_f32_e32 v23, v18
	v_cndmask_b32_e32 v3, v10, v3, vcc_lo
	v_mul_f32_e32 v17, v26, v17
	v_mul_f32_e32 v19, v16, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v21, v3
	v_dual_mov_b32 v25, v3 :: v_dual_cndmask_b32 v22, v5, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_floor_f32_e32 v24, v19
	v_cndmask_b32_e32 v5, v12, v9, vcc_lo
	v_mul_f32_e32 v13, v26, v13
	v_dual_mul_f32 v7, v26, v24 :: v_dual_mov_b32 v14, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v18, v4, v13, vcc_lo
	v_mul_f32_e32 v4, v26, v23
	v_mov_b32_e32 v13, v2
	v_dual_mov_b32 v19, v3 :: v_dual_cndmask_b32 v6, v6, v7
	v_mov_b32_e32 v23, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e32 v24, v15, v4, vcc_lo
	v_mov_b32_e32 v7, v3
	s_clause 0x2
	image_sample_lz v15, v[13:14], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v11, v[18:19], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v9, v[20:21], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	v_mov_b32_e32 v19, v5
	v_mov_b32_e32 v21, v5
	s_clause 0x2
	image_sample_lz v14, v[22:23], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v17, v[24:25], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v13, v[6:7], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	v_mov_b32_e32 v23, v5
	v_mov_b32_e32 v25, v5
	s_clause 0x4
	image_sample_lz v7, v[18:19], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v19, v[20:21], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v20, v[22:23], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v21, v[2:3], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v22, v[24:25], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	v_add_nc_u32_e32 v2, -3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v2, v2
	v_mul_f32_e32 v4, v16, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_floor_f32_e32 v4, v4
	v_mul_f32_e32 v4, v26, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v2, v4, vcc_lo
	image_sample_lz v16, v[4:5], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	s_waitcnt vmcnt(10)
	v_and_b32_e32 v18, 0xff, v11
	s_waitcnt vmcnt(9)
	v_and_b32_e32 v9, 0xff, v9
	s_waitcnt vmcnt(8)
	v_and_b32_e32 v2, 0xff, v14
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v14, 0xff, v7
	s_waitcnt vmcnt(4)
	v_and_b32_e32 v11, 0xff, v19
	s_waitcnt vmcnt(3)
	v_and_b32_e32 v19, 0xff, v20
	s_waitcnt vmcnt(2)
	v_and_b32_e32 v20, 0xff, v21
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v21, 0xff, v22
	v_sub_nc_u32_e32 v7, v18, v14
	v_sub_nc_u32_e32 v22, v9, v11
	v_sub_nc_u32_e32 v23, v2, v19
	v_sub_nc_u32_e32 v24, v20, v11
	v_sub_nc_u32_e32 v25, v18, v19
	v_sub_nc_u32_e32 v26, v9, v21
	v_sub_nc_u32_e32 v27, 0, v7
	v_sub_nc_u32_e32 v28, 0, v22
	v_sub_nc_u32_e32 v29, 0, v23
	v_sub_nc_u32_e32 v30, 0, v24
	v_sub_nc_u32_e32 v31, 0, v25
	v_sub_nc_u32_e32 v32, 0, v26
	v_max_i32_e32 v7, v7, v27
	v_max_i32_e32 v22, v22, v28
	v_max_i32_e32 v23, v23, v29
	v_max_i32_e32 v24, v24, v30
	v_max_i32_e32 v25, v25, v31
	v_max_i32_e32 v26, v26, v32
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add3_u32 v23, v22, v7, v23
	v_add_nc_u32_e32 v7, v11, v9
	v_add3_u32 v22, v25, v24, v26
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_u32_e64 v22, v23
	s_cbranch_execz .LBB0_4
; %bb.3:
	v_mov_b32_e32 v7, v5
	v_mov_b32_e32 v5, v3
	s_clause 0x1
	image_sample_lz v3, v[4:5], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v4, v[6:7], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	v_sub_nc_u32_e32 v5, v20, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, 0, v5
	v_max_i32_e32 v5, v5, v6
	v_add_nc_u32_e32 v6, v19, v18
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, 0xff, v3
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, 0xff, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v3, v19
	v_sub_nc_u32_e32 v4, v18, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v7, 0, v3
	v_sub_nc_u32_e32 v23, 0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_max_i32_e32 v3, v3, v7
	v_max_i32_e32 v4, v4, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v3, v4, v5, v3
	v_add_nc_u32_e32 v4, v21, v20
	v_cmp_lt_u32_e32 vcc_lo, v3, v22
	v_min_u32_e32 v23, v3, v22
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e32 v7, v6, v4, vcc_lo
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s0
	v_and_b32_e32 v3, 0xff, v15
	v_and_b32_e32 v4, 0xff, v17
	v_sub_nc_u32_e32 v5, v2, v14
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v6, v9, v3
	v_sub_nc_u32_e32 v15, v4, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v17, 0, v5
	v_sub_nc_u32_e32 v18, 0, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v19, 0, v15
	v_max_i32_e32 v5, v5, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_max_i32_e32 v6, v6, v18
	v_max_i32_e32 v15, v15, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v5, v5, v6, v15
	v_cmpx_lt_u32_e64 v5, v23
	s_cbranch_execz .LBB0_6
; %bb.5:
	v_and_b32_e32 v7, 0xff, v13
	v_sub_nc_u32_e32 v13, v4, v3
	v_add_nc_u32_e32 v3, v3, v4
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v6, 0xff, v16
	v_sub_nc_u32_e32 v7, v7, v14
	v_sub_nc_u32_e32 v15, 0, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v6, v2, v6
	v_add_nc_u32_e32 v2, v14, v2
	v_sub_nc_u32_e32 v17, 0, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_max_i32_e32 v13, v13, v15
	v_sub_nc_u32_e32 v16, 0, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_max_i32_e32 v7, v7, v17
	v_max_i32_e32 v6, v6, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v6, v13, v6, v7
	v_cmp_lt_u32_e32 vcc_lo, v6, v5
	v_cndmask_b32_e32 v7, v2, v3, vcc_lo
.LBB0_6:                                ; %_Z17spatial_predictorIhET_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_.exit.i
	s_or_b32 exec_lo, exec_lo, s0
	s_clause 0x1
	s_load_b128 s[60:63], s[10:11], 0x30
	s_load_b256 s[24:31], s[10:11], 0x0
	s_bitcmp1_b32 s38, 0
	v_cvt_f32_i32_e32 v19, v1
	s_cselect_b32 s7, -1, 0
	s_cmp_eq_u32 s36, s37
	s_cselect_b32 s1, s13, s11
	s_cselect_b32 s0, s12, s10
	s_load_b32 s4, s[10:11], 0x28
	s_clause 0x1
	s_load_b128 s[52:55], s[0:1], 0x30
	s_load_b32 s10, s[0:1], 0x28
	s_load_b256 s[44:51], s[14:15], 0x0
	s_cselect_b32 s3, s15, s13
	s_cselect_b32 s2, s14, s12
	s_load_b256 s[16:23], s[0:1], 0x0
	s_load_b32 s11, s[14:15], 0x28
	s_clause 0x2
	s_load_b32 s33, s[2:3], 0x28
	s_load_b128 s[56:59], s[2:3], 0x30
	s_load_b256 s[36:43], s[2:3], 0x0
	s_load_b128 s[64:67], s[14:15], 0x30
	s_waitcnt lgkmcnt(0)
	s_bitcmp0_b32 s62, 20
	s_cselect_b32 vcc_lo, -1, 0
	s_bitcmp0_b32 s60, 15
	s_cselect_b32 s1, -1, 0
	s_bfe_u32 s0, s26, 0xe000e
	v_cvt_f32_u32_e32 v3, s4
	s_add_i32 s0, s0, 1
	s_bitcmp0_b32 s54, 20
	v_cvt_f32_u32_e32 v2, s0
	s_cselect_b32 s0, -1, 0
	v_cndmask_b32_e64 v3, 1.0, v3, s1
	s_bitcmp0_b32 s52, 15
	v_cvt_f32_u32_e32 v4, s10
	v_cndmask_b32_e64 v2, 1.0, v2, s1
	s_cselect_b32 s2, -1, 0
	v_rcp_f32_e32 v6, v3
	s_bfe_u32 s1, s18, 0xe000e
	v_cvt_f32_u32_e32 v15, s11
	v_rcp_f32_e32 v13, v2
	v_mul_f32_e32 v3, v3, v8
	s_add_i32 s1, s1, 1
	s_bitcmp0_b32 s58, 20
	v_cvt_f32_u32_e32 v14, s1
	s_cselect_b32 s1, -1, 0
	v_floor_f32_e32 v3, v3
	s_bitcmp0_b32 s56, 15
	v_cvt_f32_u32_e32 v17, s33
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f32_e32 v3, v6, v3
	v_mul_f32_e32 v5, v2, v10
	v_cndmask_b32_e64 v6, 1.0, v14, s2
	v_cndmask_b32_e64 v14, 1.0, v4, s2
	s_cselect_b32 s2, -1, 0
	v_cndmask_b32_e32 v4, v8, v3, vcc_lo
	v_floor_f32_e32 v5, v5
	v_mul_f32_e32 v2, v2, v12
	s_bfe_u32 s3, s38, 0xe000e
	v_mul_f32_e32 v3, v14, v8
	s_add_i32 s10, s3, 1
	v_mul_f32_e32 v5, v13, v5
	v_floor_f32_e32 v2, v2
	s_bitcmp0_b32 s66, 20
	v_floor_f32_e32 v3, v3
	s_cselect_b32 s3, -1, 0
	s_bitcmp0_b32 s64, 15
	v_mul_f32_e32 v2, v13, v2
	v_rcp_f32_e32 v13, v14
	v_cndmask_b32_e32 v5, v10, v5, vcc_lo
	s_cselect_b32 s4, -1, 0
	s_bfe_u32 s14, s46, 0xe000e
	v_mul_f32_e32 v14, v6, v19
	s_add_i32 s14, s14, 1
	image_sample_lz v18, v[4:5], s[24:31], s[60:63] dmask:0x1 dim:SQ_RSRC_IMG_2D
	v_cndmask_b32_e32 v5, v12, v2, vcc_lo
	v_cndmask_b32_e64 v15, 1.0, v15, s4
	v_floor_f32_e32 v14, v14
	v_mul_f32_e32 v2, v13, v3
	v_cvt_f32_u32_e32 v3, s14
	v_rcp_f32_e32 v13, v6
	s_waitcnt vmcnt(1)
	v_cvt_f32_u32_e32 v16, s10
	v_rcp_f32_e32 v22, v15
	v_mul_f32_e32 v15, v15, v8
	v_cndmask_b32_e64 v3, 1.0, v3, s4
	v_cndmask_b32_e64 v2, v8, v2, s0
	s_and_b32 vcc_lo, exec_lo, s7
	s_delay_alu instid0(VALU_DEP_2)
	v_rcp_f32_e32 v20, v3
	v_mul_f32_e32 v21, v3, v10
	v_mul_f32_e32 v23, v13, v14
	v_cndmask_b32_e64 v14, 1.0, v16, s2
	v_cndmask_b32_e64 v16, 1.0, v17, s2
	v_mul_f32_e32 v3, v3, v12
	v_floor_f32_e32 v17, v21
	v_floor_f32_e32 v21, v15
	v_rcp_f32_e32 v15, v14
	v_rcp_f32_e32 v24, v16
	v_floor_f32_e32 v3, v3
	v_mul_f32_e32 v17, v20, v17
	v_dual_mul_f32 v21, v22, v21 :: v_dual_mul_f32 v22, v16, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v17, v10, v17, s3
	v_cndmask_b32_e64 v16, v8, v21, s3
	v_mul_f32_e32 v10, v20, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_floor_f32_e32 v20, v22
	image_sample_lz v22, v[16:17], s[44:51], s[64:67] dmask:0x1 dim:SQ_RSRC_IMG_2D
	v_cndmask_b32_e64 v17, v12, v10, s3
	v_mul_f32_e32 v10, v24, v20
	v_cndmask_b32_e64 v3, v19, v23, s0
	image_sample_lz v20, v[4:5], s[24:31], s[60:63] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v3, v[2:3], s[16:23], s[52:55] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v16, v[16:17], s[44:51], s[64:67] dmask:0x1 dim:SQ_RSRC_IMG_2D
	v_cndmask_b32_e64 v4, v8, v10, s1
	s_waitcnt vmcnt(4)
	v_and_b32_e32 v8, 0xff, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v8, v8, v9
	v_sub_nc_u32_e32 v17, 0, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_max_i32_e32 v8, v8, v17
	s_waitcnt vmcnt(2)
	v_and_b32_e32 v10, 0xff, v20
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, 0xff, v3
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v16, 0xff, v16
	v_sub_nc_u32_e32 v10, v10, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v16, v11, v16
	v_sub_nc_u32_e32 v18, 0, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v20, 0, v16
	v_max_i32_e32 v10, v10, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_max_i32_e32 v16, v16, v20
	v_mul_f32_e32 v25, v14, v19
	v_add_nc_u32_e32 v8, v10, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_floor_f32_e32 v21, v25
	v_mul_f32_e32 v12, v15, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v5, v19, v12, s1
	v_and_b32_e32 v12, 0xff, v22
	image_sample_lz v5, v[4:5], s[36:43], s[56:59] dmask:0x1 dim:SQ_RSRC_IMG_2D
	v_sub_nc_u32_e32 v12, v12, v9
	v_sub_nc_u32_e32 v19, 0, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v12, v12, v19
	v_add_nc_u32_e32 v10, v16, v12
	v_lshrrev_b32_e32 v12, 1, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v10, 1, v10
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v5, 0xff, v5
	v_sub_nc_u32_e32 v17, v3, v5
	v_add_nc_u32_e32 v3, v5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v18, 0, v17
	v_lshrrev_b32_e32 v8, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v5, v17, v18
	v_max3_i32 v10, v5, v12, v10
	s_cbranch_vccnz .LBB0_8
; %bb.7:
	v_add_nc_u32_e32 v3, 2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v3, v3
	v_dual_mul_f32 v12, v14, v3 :: v_dual_add_nc_u32 v5, -2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v17, v5
	v_floor_f32_e32 v5, v12
	v_mul_f32_e32 v16, v6, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v6, v6, v17
	v_mul_f32_e32 v14, v14, v17
	v_mul_f32_e32 v5, v15, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_floor_f32_e32 v12, v16
	v_floor_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_floor_f32_e32 v14, v14
	v_cndmask_b32_e64 v5, v3, v5, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v12, v13, v12
	v_mul_f32_e32 v6, v13, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v3, v3, v12, s0
	v_mul_f32_e32 v12, v15, v14
	image_sample_lz v13, v[4:5], s[36:43], s[56:59] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v14, v[2:3], s[16:23], s[52:55] dmask:0x1 dim:SQ_RSRC_IMG_2D
	v_cndmask_b32_e64 v3, v17, v6, s0
	v_cndmask_b32_e64 v5, v17, v12, s1
	image_sample_lz v2, v[2:3], s[16:23], s[52:55] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v3, v[4:5], s[36:43], s[56:59] dmask:0x1 dim:SQ_RSRC_IMG_2D
	s_waitcnt vmcnt(3)
	v_and_b32_e32 v5, 0xff, v13
	s_waitcnt vmcnt(2)
	v_and_b32_e32 v4, 0xff, v14
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, 0xff, v2
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, 0xff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v2, v2, v3
	v_add_nc_u32_e32 v3, v4, v5
	v_sub_nc_u32_e32 v4, v8, v11
	v_sub_nc_u32_e32 v5, v8, v9
	v_lshrrev_b32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v3, 1, v3
	v_sub_nc_u32_e32 v2, v2, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v11
	v_min_i32_e32 v6, v2, v3
	v_max_i32_e32 v2, v2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_max3_i32 v3, v4, v5, v6
	v_min3_i32 v2, v4, v5, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, 0, v3
	v_max3_i32 v10, v10, v2, v3
.LBB0_8:                                ; %_Z18temporal_predictorIhET_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_b.exit.i
	v_lshrrev_b32_e32 v2, 1, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v10, v8
	v_min_u32_e32 v2, v3, v2
	v_sub_nc_u32_e32 v3, v8, v10
                                        ; implicit-def: $vgpr8
	s_delay_alu instid0(VALU_DEP_1)
	v_max_i32_e32 v2, v3, v2
.LBB0_9:                                ; %Flow
	s_and_not1_saveexec_b32 s1, s5
	s_cbranch_execz .LBB0_11
; %bb.10:
	s_clause 0x2
	s_load_b128 s[24:27], s[12:13], 0x30
	s_load_b256 s[16:23], s[12:13], 0x0
	s_load_b32 s2, s[12:13], 0x28
	v_cvt_f32_i32_e32 v2, v1
	s_waitcnt lgkmcnt(0)
	s_bitcmp0_b32 s26, 20
	s_cselect_b32 vcc_lo, -1, 0
	s_bitcmp0_b32 s24, 15
	v_cvt_f32_u32_e32 v4, s2
	s_cselect_b32 s0, -1, 0
	s_bfe_u32 s3, s18, 0xe000e
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s3, s3, 1
	v_cndmask_b32_e64 v4, 1.0, v4, s0
	v_cvt_f32_u32_e32 v3, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v6, v4
	v_cndmask_b32_e64 v3, 1.0, v3, s0
	v_mul_f32_e32 v4, v4, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v5, v3
	v_mul_f32_e32 v3, v3, v2
	v_floor_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_floor_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v4, v6, v4 :: v_dual_mul_f32 v3, v5, v3
	v_dual_cndmask_b32 v3, v2, v3 :: v_dual_cndmask_b32 v2, v8, v4
	image_sample_lz v2, v[2:3], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
.LBB0_11:                               ; %.sink.split.i
	s_or_b32 exec_lo, exec_lo, s1
	v_mad_u64_u32 v[3:4], null, v1, s6, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v3
	v_add_co_u32 v0, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b8 v[0:1], v2, off
.LBB0_12:                               ; %_Z12yadif_singleIhEvPT_P13__hip_textureS3_S3_iiiiiiib.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel yadif_uchar
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 33
		.amdhsa_next_free_sgpr 68
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	yadif_uchar, .Lfunc_end0-yadif_uchar
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2624
; NumSgprs: 70
; NumVgprs: 33
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 8
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 70
; NumVGPRsForWavesPerEU: 33
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	yadif_ushort            ; -- Begin function yadif_ushort
	.globl	yadif_ushort
	.p2align	8
	.type	yadif_ushort,@function
yadif_ushort:                           ; @yadif_ushort
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b128 s[4:7], s[0:1], 0x20
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	v_cmp_gt_i32_e64 s2, s5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_12
; %bb.1:
	s_load_b128 s[36:39], s[0:1], 0x34
	v_lshrrev_b32_e32 v2, 31, v1
	s_load_b256 s[8:15], s[0:1], 0x0
	v_cvt_f32_i32_e32 v8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v1, v2
	v_and_b32_e32 v2, -2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v1, v2
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, s36, v2
                                        ; implicit-def: $vgpr2
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s5, exec_lo, s0
	s_cbranch_execz .LBB1_9
; %bb.2:
	s_clause 0x2
	s_load_b128 s[24:27], s[12:13], 0x30
	s_load_b256 s[16:23], s[12:13], 0x0
	s_load_b32 s1, s[12:13], 0x28
	s_waitcnt lgkmcnt(0)
	s_bitcmp0_b32 s26, 20
	s_cselect_b32 vcc_lo, -1, 0
	s_bitcmp0_b32 s24, 15
	s_cselect_b32 s0, -1, 0
	s_bfe_u32 s2, s18, 0xe000e
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, 1
	v_cvt_f32_u32_e32 v9, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v9, 1.0, v9, s0
	v_add_nc_u32_e32 v2, -1, v1
	v_cvt_f32_i32_e32 v10, v2
	v_add_nc_u32_e32 v2, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v15, v2
	v_add_nc_u32_e32 v3, -2, v0
	v_rcp_f32_e32 v2, v9
	v_cvt_f32_i32_e32 v11, v3
	v_cvt_f32_u32_e32 v3, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v16, 1.0, v3, s0
	v_add_nc_u32_e32 v7, 1, v1
	v_dual_mul_f32 v3, v9, v10 :: v_dual_add_nc_u32 v4, -1, v0
	s_mov_b32 s0, exec_lo
	v_rcp_f32_e32 v26, v16
	v_mul_f32_e32 v14, v16, v8
	v_cvt_f32_i32_e32 v12, v7
	v_mul_f32_e32 v7, v16, v11
	v_cvt_f32_i32_e32 v4, v4
	v_floor_f32_e32 v3, v3
	v_floor_f32_e32 v14, v14
	v_add_nc_u32_e32 v5, 1, v0
	v_add_nc_u32_e32 v6, 3, v0
	v_mul_f32_e32 v9, v9, v12
	v_floor_f32_e32 v7, v7
	v_mul_f32_e32 v14, v26, v14
	v_cvt_f32_i32_e32 v5, v5
	v_mul_f32_e32 v3, v2, v3
	v_cvt_f32_i32_e32 v6, v6
	v_floor_f32_e32 v9, v9
	v_dual_mul_f32 v7, v26, v7 :: v_dual_cndmask_b32 v20, v8, v14
	v_mul_f32_e32 v17, v16, v5
	v_mul_f32_e32 v13, v16, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v18, v16, v15 :: v_dual_mul_f32 v9, v2, v9
	v_cndmask_b32_e32 v2, v11, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_floor_f32_e32 v17, v17
	v_floor_f32_e32 v13, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_floor_f32_e32 v23, v18
	v_cndmask_b32_e32 v3, v10, v3, vcc_lo
	v_mul_f32_e32 v17, v26, v17
	v_mul_f32_e32 v19, v16, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v21, v3
	v_dual_mov_b32 v25, v3 :: v_dual_cndmask_b32 v22, v5, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_floor_f32_e32 v24, v19
	v_cndmask_b32_e32 v5, v12, v9, vcc_lo
	v_mul_f32_e32 v13, v26, v13
	v_dual_mul_f32 v7, v26, v24 :: v_dual_mov_b32 v14, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v18, v4, v13, vcc_lo
	v_mul_f32_e32 v4, v26, v23
	v_mov_b32_e32 v13, v2
	v_dual_mov_b32 v19, v3 :: v_dual_cndmask_b32 v6, v6, v7
	v_mov_b32_e32 v23, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e32 v24, v15, v4, vcc_lo
	v_mov_b32_e32 v7, v3
	s_clause 0x2
	image_sample_lz v15, v[13:14], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v11, v[18:19], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v9, v[20:21], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	v_mov_b32_e32 v19, v5
	v_mov_b32_e32 v21, v5
	s_clause 0x2
	image_sample_lz v14, v[22:23], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v17, v[24:25], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v13, v[6:7], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	v_mov_b32_e32 v23, v5
	v_mov_b32_e32 v25, v5
	s_clause 0x4
	image_sample_lz v7, v[18:19], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v19, v[20:21], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v20, v[22:23], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v21, v[2:3], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v22, v[24:25], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	v_add_nc_u32_e32 v2, -3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v2, v2
	v_mul_f32_e32 v4, v16, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_floor_f32_e32 v4, v4
	v_mul_f32_e32 v4, v26, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v2, v4, vcc_lo
	image_sample_lz v16, v[4:5], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	s_waitcnt vmcnt(10)
	v_and_b32_e32 v18, 0xffff, v11
	s_waitcnt vmcnt(9)
	v_and_b32_e32 v9, 0xffff, v9
	s_waitcnt vmcnt(8)
	v_and_b32_e32 v2, 0xffff, v14
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v14, 0xffff, v7
	s_waitcnt vmcnt(4)
	v_and_b32_e32 v11, 0xffff, v19
	s_waitcnt vmcnt(3)
	v_and_b32_e32 v19, 0xffff, v20
	s_waitcnt vmcnt(2)
	v_and_b32_e32 v20, 0xffff, v21
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v21, 0xffff, v22
	v_sub_nc_u32_e32 v7, v18, v14
	v_sub_nc_u32_e32 v22, v9, v11
	v_sub_nc_u32_e32 v23, v2, v19
	v_sub_nc_u32_e32 v24, v20, v11
	v_sub_nc_u32_e32 v25, v18, v19
	v_sub_nc_u32_e32 v26, v9, v21
	v_sub_nc_u32_e32 v27, 0, v7
	v_sub_nc_u32_e32 v28, 0, v22
	v_sub_nc_u32_e32 v29, 0, v23
	v_sub_nc_u32_e32 v30, 0, v24
	v_sub_nc_u32_e32 v31, 0, v25
	v_sub_nc_u32_e32 v32, 0, v26
	v_max_i32_e32 v7, v7, v27
	v_max_i32_e32 v22, v22, v28
	v_max_i32_e32 v23, v23, v29
	v_max_i32_e32 v24, v24, v30
	v_max_i32_e32 v25, v25, v31
	v_max_i32_e32 v26, v26, v32
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add3_u32 v23, v22, v7, v23
	v_add_nc_u32_e32 v7, v11, v9
	v_add3_u32 v22, v25, v24, v26
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_u32_e64 v22, v23
	s_cbranch_execz .LBB1_4
; %bb.3:
	v_mov_b32_e32 v7, v5
	v_mov_b32_e32 v5, v3
	s_clause 0x1
	image_sample_lz v3, v[4:5], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v4, v[6:7], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
	v_sub_nc_u32_e32 v5, v20, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, 0, v5
	v_max_i32_e32 v5, v5, v6
	v_add_nc_u32_e32 v6, v19, v18
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, 0xffff, v3
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v3, v19
	v_sub_nc_u32_e32 v4, v18, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v7, 0, v3
	v_sub_nc_u32_e32 v23, 0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_max_i32_e32 v3, v3, v7
	v_max_i32_e32 v4, v4, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v3, v4, v5, v3
	v_add_nc_u32_e32 v4, v21, v20
	v_cmp_lt_u32_e32 vcc_lo, v3, v22
	v_min_u32_e32 v23, v3, v22
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e32 v7, v6, v4, vcc_lo
.LBB1_4:
	s_or_b32 exec_lo, exec_lo, s0
	v_and_b32_e32 v3, 0xffff, v15
	v_and_b32_e32 v4, 0xffff, v17
	v_sub_nc_u32_e32 v5, v2, v14
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v6, v9, v3
	v_sub_nc_u32_e32 v15, v4, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v17, 0, v5
	v_sub_nc_u32_e32 v18, 0, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v19, 0, v15
	v_max_i32_e32 v5, v5, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_max_i32_e32 v6, v6, v18
	v_max_i32_e32 v15, v15, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v5, v5, v6, v15
	v_cmpx_lt_u32_e64 v5, v23
	s_cbranch_execz .LBB1_6
; %bb.5:
	v_and_b32_e32 v7, 0xffff, v13
	v_sub_nc_u32_e32 v13, v4, v3
	v_add_nc_u32_e32 v3, v3, v4
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v6, 0xffff, v16
	v_sub_nc_u32_e32 v7, v7, v14
	v_sub_nc_u32_e32 v15, 0, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v6, v2, v6
	v_add_nc_u32_e32 v2, v14, v2
	v_sub_nc_u32_e32 v17, 0, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_max_i32_e32 v13, v13, v15
	v_sub_nc_u32_e32 v16, 0, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_max_i32_e32 v7, v7, v17
	v_max_i32_e32 v6, v6, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v6, v13, v6, v7
	v_cmp_lt_u32_e32 vcc_lo, v6, v5
	v_cndmask_b32_e32 v7, v2, v3, vcc_lo
.LBB1_6:                                ; %_Z17spatial_predictorItET_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_.exit.i
	s_or_b32 exec_lo, exec_lo, s0
	s_clause 0x1
	s_load_b128 s[60:63], s[10:11], 0x30
	s_load_b256 s[24:31], s[10:11], 0x0
	s_bitcmp1_b32 s38, 0
	v_cvt_f32_i32_e32 v19, v1
	s_cselect_b32 s7, -1, 0
	s_cmp_eq_u32 s36, s37
	s_cselect_b32 s1, s13, s11
	s_cselect_b32 s0, s12, s10
	s_load_b32 s4, s[10:11], 0x28
	s_clause 0x1
	s_load_b128 s[52:55], s[0:1], 0x30
	s_load_b32 s10, s[0:1], 0x28
	s_load_b256 s[44:51], s[14:15], 0x0
	s_cselect_b32 s3, s15, s13
	s_cselect_b32 s2, s14, s12
	s_load_b256 s[16:23], s[0:1], 0x0
	s_load_b32 s11, s[14:15], 0x28
	s_clause 0x2
	s_load_b32 s33, s[2:3], 0x28
	s_load_b128 s[56:59], s[2:3], 0x30
	s_load_b256 s[36:43], s[2:3], 0x0
	s_load_b128 s[64:67], s[14:15], 0x30
	s_waitcnt lgkmcnt(0)
	s_bitcmp0_b32 s62, 20
	s_cselect_b32 vcc_lo, -1, 0
	s_bitcmp0_b32 s60, 15
	s_cselect_b32 s1, -1, 0
	s_bfe_u32 s0, s26, 0xe000e
	v_cvt_f32_u32_e32 v3, s4
	s_add_i32 s0, s0, 1
	s_bitcmp0_b32 s54, 20
	v_cvt_f32_u32_e32 v2, s0
	s_cselect_b32 s0, -1, 0
	v_cndmask_b32_e64 v3, 1.0, v3, s1
	s_bitcmp0_b32 s52, 15
	v_cvt_f32_u32_e32 v4, s10
	v_cndmask_b32_e64 v2, 1.0, v2, s1
	s_cselect_b32 s2, -1, 0
	v_rcp_f32_e32 v6, v3
	s_bfe_u32 s1, s18, 0xe000e
	v_cvt_f32_u32_e32 v15, s11
	v_rcp_f32_e32 v13, v2
	v_mul_f32_e32 v3, v3, v8
	s_add_i32 s1, s1, 1
	s_bitcmp0_b32 s58, 20
	v_cvt_f32_u32_e32 v14, s1
	s_cselect_b32 s1, -1, 0
	v_floor_f32_e32 v3, v3
	s_bitcmp0_b32 s56, 15
	v_cvt_f32_u32_e32 v17, s33
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f32_e32 v3, v6, v3
	v_mul_f32_e32 v5, v2, v10
	v_cndmask_b32_e64 v6, 1.0, v14, s2
	v_cndmask_b32_e64 v14, 1.0, v4, s2
	s_cselect_b32 s2, -1, 0
	v_cndmask_b32_e32 v4, v8, v3, vcc_lo
	v_floor_f32_e32 v5, v5
	v_mul_f32_e32 v2, v2, v12
	s_bfe_u32 s3, s38, 0xe000e
	v_mul_f32_e32 v3, v14, v8
	s_add_i32 s10, s3, 1
	v_mul_f32_e32 v5, v13, v5
	v_floor_f32_e32 v2, v2
	s_bitcmp0_b32 s66, 20
	v_floor_f32_e32 v3, v3
	s_cselect_b32 s3, -1, 0
	s_bitcmp0_b32 s64, 15
	v_mul_f32_e32 v2, v13, v2
	v_rcp_f32_e32 v13, v14
	v_cndmask_b32_e32 v5, v10, v5, vcc_lo
	s_cselect_b32 s4, -1, 0
	s_bfe_u32 s14, s46, 0xe000e
	v_mul_f32_e32 v14, v6, v19
	s_add_i32 s14, s14, 1
	image_sample_lz v18, v[4:5], s[24:31], s[60:63] dmask:0x1 dim:SQ_RSRC_IMG_2D
	v_cndmask_b32_e32 v5, v12, v2, vcc_lo
	v_cndmask_b32_e64 v15, 1.0, v15, s4
	v_floor_f32_e32 v14, v14
	v_mul_f32_e32 v2, v13, v3
	v_cvt_f32_u32_e32 v3, s14
	v_rcp_f32_e32 v13, v6
	s_waitcnt vmcnt(1)
	v_cvt_f32_u32_e32 v16, s10
	v_rcp_f32_e32 v22, v15
	v_mul_f32_e32 v15, v15, v8
	v_cndmask_b32_e64 v3, 1.0, v3, s4
	v_cndmask_b32_e64 v2, v8, v2, s0
	s_and_b32 vcc_lo, exec_lo, s7
	s_delay_alu instid0(VALU_DEP_2)
	v_rcp_f32_e32 v20, v3
	v_mul_f32_e32 v21, v3, v10
	v_mul_f32_e32 v23, v13, v14
	v_cndmask_b32_e64 v14, 1.0, v16, s2
	v_cndmask_b32_e64 v16, 1.0, v17, s2
	v_mul_f32_e32 v3, v3, v12
	v_floor_f32_e32 v17, v21
	v_floor_f32_e32 v21, v15
	v_rcp_f32_e32 v15, v14
	v_rcp_f32_e32 v24, v16
	v_floor_f32_e32 v3, v3
	v_mul_f32_e32 v17, v20, v17
	v_dual_mul_f32 v21, v22, v21 :: v_dual_mul_f32 v22, v16, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v17, v10, v17, s3
	v_cndmask_b32_e64 v16, v8, v21, s3
	v_mul_f32_e32 v10, v20, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_floor_f32_e32 v20, v22
	image_sample_lz v22, v[16:17], s[44:51], s[64:67] dmask:0x1 dim:SQ_RSRC_IMG_2D
	v_cndmask_b32_e64 v17, v12, v10, s3
	v_mul_f32_e32 v10, v24, v20
	v_cndmask_b32_e64 v3, v19, v23, s0
	image_sample_lz v20, v[4:5], s[24:31], s[60:63] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v3, v[2:3], s[16:23], s[52:55] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v16, v[16:17], s[44:51], s[64:67] dmask:0x1 dim:SQ_RSRC_IMG_2D
	v_cndmask_b32_e64 v4, v8, v10, s1
	s_waitcnt vmcnt(4)
	v_and_b32_e32 v8, 0xffff, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v8, v8, v9
	v_sub_nc_u32_e32 v17, 0, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_max_i32_e32 v8, v8, v17
	s_waitcnt vmcnt(2)
	v_and_b32_e32 v10, 0xffff, v20
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, 0xffff, v3
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v16, 0xffff, v16
	v_sub_nc_u32_e32 v10, v10, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v16, v11, v16
	v_sub_nc_u32_e32 v18, 0, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v20, 0, v16
	v_max_i32_e32 v10, v10, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_max_i32_e32 v16, v16, v20
	v_mul_f32_e32 v25, v14, v19
	v_add_nc_u32_e32 v8, v10, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_floor_f32_e32 v21, v25
	v_mul_f32_e32 v12, v15, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v5, v19, v12, s1
	v_and_b32_e32 v12, 0xffff, v22
	image_sample_lz v5, v[4:5], s[36:43], s[56:59] dmask:0x1 dim:SQ_RSRC_IMG_2D
	v_sub_nc_u32_e32 v12, v12, v9
	v_sub_nc_u32_e32 v19, 0, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v12, v12, v19
	v_add_nc_u32_e32 v10, v16, v12
	v_lshrrev_b32_e32 v12, 1, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v10, 1, v10
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v5, 0xffff, v5
	v_sub_nc_u32_e32 v17, v3, v5
	v_add_nc_u32_e32 v3, v5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v18, 0, v17
	v_lshrrev_b32_e32 v8, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v5, v17, v18
	v_max3_i32 v10, v5, v12, v10
	s_cbranch_vccnz .LBB1_8
; %bb.7:
	v_add_nc_u32_e32 v3, 2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v3, v3
	v_dual_mul_f32 v12, v14, v3 :: v_dual_add_nc_u32 v5, -2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v17, v5
	v_floor_f32_e32 v5, v12
	v_mul_f32_e32 v16, v6, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v6, v6, v17
	v_mul_f32_e32 v14, v14, v17
	v_mul_f32_e32 v5, v15, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_floor_f32_e32 v12, v16
	v_floor_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_floor_f32_e32 v14, v14
	v_cndmask_b32_e64 v5, v3, v5, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v12, v13, v12
	v_mul_f32_e32 v6, v13, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v3, v3, v12, s0
	v_mul_f32_e32 v12, v15, v14
	image_sample_lz v13, v[4:5], s[36:43], s[56:59] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v14, v[2:3], s[16:23], s[52:55] dmask:0x1 dim:SQ_RSRC_IMG_2D
	v_cndmask_b32_e64 v3, v17, v6, s0
	v_cndmask_b32_e64 v5, v17, v12, s1
	image_sample_lz v2, v[2:3], s[16:23], s[52:55] dmask:0x1 dim:SQ_RSRC_IMG_2D
	image_sample_lz v3, v[4:5], s[36:43], s[56:59] dmask:0x1 dim:SQ_RSRC_IMG_2D
	s_waitcnt vmcnt(3)
	v_and_b32_e32 v5, 0xffff, v13
	s_waitcnt vmcnt(2)
	v_and_b32_e32 v4, 0xffff, v14
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, 0xffff, v2
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v2, v2, v3
	v_add_nc_u32_e32 v3, v4, v5
	v_sub_nc_u32_e32 v4, v8, v11
	v_sub_nc_u32_e32 v5, v8, v9
	v_lshrrev_b32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v3, 1, v3
	v_sub_nc_u32_e32 v2, v2, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v11
	v_min_i32_e32 v6, v2, v3
	v_max_i32_e32 v2, v2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_max3_i32 v3, v4, v5, v6
	v_min3_i32 v2, v4, v5, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, 0, v3
	v_max3_i32 v10, v10, v2, v3
.LBB1_8:                                ; %_Z18temporal_predictorItET_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_b.exit.i
	v_lshrrev_b32_e32 v2, 1, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v10, v8
	v_min_u32_e32 v2, v3, v2
	v_sub_nc_u32_e32 v3, v8, v10
                                        ; implicit-def: $vgpr8
	s_delay_alu instid0(VALU_DEP_1)
	v_max_i32_e32 v2, v3, v2
.LBB1_9:                                ; %Flow
	s_and_not1_saveexec_b32 s1, s5
	s_cbranch_execz .LBB1_11
; %bb.10:
	s_clause 0x2
	s_load_b128 s[24:27], s[12:13], 0x30
	s_load_b256 s[16:23], s[12:13], 0x0
	s_load_b32 s2, s[12:13], 0x28
	v_cvt_f32_i32_e32 v2, v1
	s_waitcnt lgkmcnt(0)
	s_bitcmp0_b32 s26, 20
	s_cselect_b32 vcc_lo, -1, 0
	s_bitcmp0_b32 s24, 15
	v_cvt_f32_u32_e32 v4, s2
	s_cselect_b32 s0, -1, 0
	s_bfe_u32 s3, s18, 0xe000e
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s3, s3, 1
	v_cndmask_b32_e64 v4, 1.0, v4, s0
	v_cvt_f32_u32_e32 v3, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v6, v4
	v_cndmask_b32_e64 v3, 1.0, v3, s0
	v_mul_f32_e32 v4, v4, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v5, v3
	v_mul_f32_e32 v3, v3, v2
	v_floor_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_floor_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v4, v6, v4 :: v_dual_mul_f32 v3, v5, v3
	v_dual_cndmask_b32 v3, v2, v3 :: v_dual_cndmask_b32 v2, v8, v4
	image_sample_lz v2, v[2:3], s[16:23], s[24:27] dmask:0x1 dim:SQ_RSRC_IMG_2D
.LBB1_11:                               ; %.sink.split.i
	s_or_b32 exec_lo, exec_lo, s1
	v_mad_u64_u32 v[3:4], null, v1, s6, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[0:1], 1, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b16 v[0:1], v2, off
.LBB1_12:                               ; %_Z12yadif_singleItEvPT_P13__hip_textureS3_S3_iiiiiiib.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel yadif_ushort
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 33
		.amdhsa_next_free_sgpr 68
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	yadif_ushort, .Lfunc_end1-yadif_ushort
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2636
; NumSgprs: 70
; NumVgprs: 33
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 8
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 70
; NumVGPRsForWavesPerEU: 33
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	yadif_uchar2            ; -- Begin function yadif_uchar2
	.globl	yadif_uchar2
	.p2align	8
	.type	yadif_uchar2,@function
yadif_uchar2:                           ; @yadif_uchar2
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b128 s[28:31], s[0:1], 0x20
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[2:3], null, s15, s3, v[4:5]
	v_cmp_gt_i32_e32 vcc_lo, s28, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s29, v2
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_17
; %bb.1:
	s_load_b128 s[36:39], s[0:1], 0x34
	v_lshrrev_b32_e32 v1, 31, v2
	s_load_b256 s[4:11], s[0:1], 0x0
	v_cvt_f32_i32_e32 v31, v0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, v2, v1
	v_and_b32_e32 v1, -2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v2, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_ne_u32_e64 s36, v1
	s_xor_b32 s28, exec_lo, s0
	s_cbranch_execz .LBB2_15
; %bb.2:
	s_clause 0x2
	s_load_b128 s[20:23], s[8:9], 0x30
	s_load_b256 s[12:19], s[8:9], 0x0
	s_load_b32 s1, s[8:9], 0x28
	v_add_nc_u32_e32 v9, 1, v2
	v_add_nc_u32_e32 v7, 2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cvt_f32_i32_e32 v33, v9
	v_add_nc_u32_e32 v6, 1, v0
	v_cvt_f32_i32_e32 v7, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_cvt_f32_i32_e32 v19, v6
	s_waitcnt lgkmcnt(0)
	s_bitcmp0_b32 s22, 20
	v_cvt_f32_u32_e32 v11, s1
	s_cselect_b32 vcc_lo, -1, 0
	s_bitcmp0_b32 s20, 15
	s_cselect_b32 s0, -1, 0
	s_bfe_u32 s2, s14, 0xe000e
	v_cndmask_b32_e64 v6, 1.0, v11, s0
	v_add_nc_u32_e32 v3, -3, v0
	s_add_i32 s2, s2, 1
	v_add_nc_u32_e32 v5, -1, v0
	v_cvt_f32_u32_e32 v10, s2
	v_mul_f32_e32 v16, v6, v7
	v_mul_f32_e32 v14, v6, v31
	v_cvt_f32_i32_e32 v3, v3
	v_add_nc_u32_e32 v1, -1, v2
	v_dual_mul_f32 v15, v6, v19 :: v_dual_add_nc_u32 v8, 3, v0
	v_cvt_f32_i32_e32 v12, v5
	v_cndmask_b32_e64 v5, 1.0, v10, s0
	v_mul_f32_e32 v10, v6, v3
	v_cvt_f32_i32_e32 v1, v1
	v_add_nc_u32_e32 v4, -2, v0
	v_cvt_f32_i32_e32 v8, v8
	v_rcp_f32_e32 v20, v5
	v_rcp_f32_e32 v21, v6
	v_mul_f32_e32 v9, v5, v1
	v_cvt_f32_i32_e32 v4, v4
	v_mul_f32_e32 v5, v5, v33
	v_mul_f32_e32 v23, v6, v8
	v_floor_f32_e32 v15, v15
	v_floor_f32_e32 v24, v16
	v_mul_f32_e32 v11, v6, v4
	v_floor_f32_e32 v25, v5
	v_mul_f32_e32 v13, v6, v12
	v_floor_f32_e32 v6, v9
	v_floor_f32_e32 v9, v10
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v20, v6
	v_cndmask_b32_e32 v6, v1, v6, vcc_lo
	v_floor_f32_e32 v10, v11
	v_floor_f32_e32 v11, v13
	v_floor_f32_e32 v13, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v5, v21, v9 :: v_dual_mov_b32 v14, v6
	v_mul_f32_e32 v9, v21, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v10, v21, v11
	v_dual_mul_f32 v27, v21, v13 :: v_dual_mov_b32 v22, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v26, v6 :: v_dual_cndmask_b32 v11, v4, v9
	v_dual_cndmask_b32 v13, v12, v10 :: v_dual_mov_b32 v12, v6
	v_cndmask_b32_e32 v5, v3, v5, vcc_lo
	v_mul_f32_e32 v3, v21, v15
	s_clause 0x2
	image_sample_lz v[9:10], v[5:6], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	image_sample_lz v[15:16], v[11:12], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	image_sample_lz v[17:18], v[13:14], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_mul_f32_e32 v14, v21, v24
	v_dual_mul_f32 v12, v20, v25 :: v_dual_mov_b32 v35, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v34, v7, v14, vcc_lo
	v_floor_f32_e32 v4, v23
	v_dual_mul_f32 v4, v21, v4 :: v_dual_cndmask_b32 v21, v31, v27
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_cndmask_b32 v36, v8, v4 :: v_dual_cndmask_b32 v25, v19, v3
	s_clause 0x1
	image_sample_lz v[23:24], v[21:22], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	image_sample_lz v[19:20], v[25:26], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_dual_mov_b32 v37, v6 :: v_dual_cndmask_b32 v6, v33, v12
	image_sample_lz v[7:8], v[34:35], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_mov_b32_e32 v14, v6
	v_mov_b32_e32 v22, v6
	s_waitcnt vmcnt(4)
	v_dual_mov_b32 v26, v6 :: v_dual_and_b32 v15, 0xff, v15
	s_waitcnt vmcnt(2)
	v_and_b32_e32 v32, 0xff, v23
	image_sample_lz v[3:4], v[36:37], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_mov_b32_e32 v35, v6
	s_clause 0x3
	image_sample_lz v[29:30], v[13:14], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	image_sample_lz v[27:28], v[21:22], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	image_sample_lz v[25:26], v[25:26], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	image_sample_lz v[21:22], v[34:35], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_and_b32_e32 v34, 0xff, v17
	v_mov_b32_e32 v12, v6
	v_mov_b32_e32 v37, v6
	s_waitcnt vmcnt(6)
	v_and_b32_e32 v17, 0xff, v19
	s_waitcnt vmcnt(3)
	v_and_b32_e32 v19, 0xff, v29
	s_clause 0x2
	image_sample_lz v[5:6], v[5:6], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	image_sample_lz v[11:12], v[11:12], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	image_sample_lz v[13:14], v[36:37], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v27, 0xff, v27
	s_waitcnt vmcnt(4)
	v_and_b32_e32 v25, 0xff, v25
	s_waitcnt vmcnt(3)
	v_and_b32_e32 v21, 0xff, v21
	v_sub_nc_u32_e32 v23, v34, v19
	v_sub_nc_u32_e32 v29, v32, v27
	v_sub_nc_u32_e32 v35, v17, v25
	v_sub_nc_u32_e32 v36, v15, v27
	v_sub_nc_u32_e32 v37, v34, v25
	v_sub_nc_u32_e32 v38, v32, v21
	v_sub_nc_u32_e32 v39, 0, v23
	v_sub_nc_u32_e32 v40, 0, v29
	v_sub_nc_u32_e32 v41, 0, v35
	v_sub_nc_u32_e32 v42, 0, v36
	v_sub_nc_u32_e32 v43, 0, v37
	v_sub_nc_u32_e32 v44, 0, v38
	v_max_i32_e32 v23, v23, v39
	v_max_i32_e32 v29, v29, v40
	v_max_i32_e32 v35, v35, v41
	v_max_i32_e32 v36, v36, v42
	v_max_i32_e32 v37, v37, v43
	v_max_i32_e32 v38, v38, v44
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add3_u32 v29, v29, v23, v35
	v_add_nc_u32_e32 v23, v27, v32
	v_add3_u32 v35, v37, v36, v38
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_u32_e64 v35, v29
	s_cbranch_execz .LBB2_4
; %bb.3:
	v_and_b32_e32 v9, 0xff, v9
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v13, 0xff, v13
	v_sub_nc_u32_e32 v23, v15, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v9, v9, v25
	v_sub_nc_u32_e32 v13, v34, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v29, 0, v23
	v_add_nc_u32_e32 v25, v25, v34
	v_sub_nc_u32_e32 v36, 0, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v37, 0, v13
	v_max_i32_e32 v23, v23, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_max_i32_e32 v9, v9, v36
	v_max_i32_e32 v13, v13, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v9, v23, v9, v13
	v_add_nc_u32_e32 v13, v21, v15
	v_cmp_lt_u32_e32 vcc_lo, v9, v35
	v_min_u32_e32 v29, v9, v35
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e32 v23, v25, v13, vcc_lo
.LBB2_4:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v9, 0xff, v11
	v_and_b32_e32 v7, 0xff, v7
	v_sub_nc_u32_e32 v11, v17, v19
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_sub_nc_u32_e32 v13, v32, v9
	v_sub_nc_u32_e32 v15, v7, v27
	v_sub_nc_u32_e32 v21, 0, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v25, 0, v13
	v_sub_nc_u32_e32 v34, 0, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_max_i32_e32 v11, v11, v21
	v_max_i32_e32 v13, v13, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v15, v15, v34
	v_add3_u32 v11, v11, v13, v15
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_u32_e64 v11, v29
	s_cbranch_execz .LBB2_6
; %bb.5:
	v_and_b32_e32 v5, 0xff, v5
	v_and_b32_e32 v3, 0xff, v3
	v_sub_nc_u32_e32 v13, v7, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v5, v17, v5
	v_sub_nc_u32_e32 v3, v3, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v15, 0, v13
	v_sub_nc_u32_e32 v21, 0, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v23, 0, v3
	v_max_i32_e32 v13, v13, v15
	v_add_nc_u32_e32 v15, v19, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_max_i32_e32 v5, v5, v21
	v_max_i32_e32 v3, v3, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v3, v13, v5, v3
	v_add_nc_u32_e32 v5, v9, v7
	v_cmp_lt_u32_e32 vcc_lo, v3, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v23, v15, v5, vcc_lo
.LBB2_6:                                ; %_Z17spatial_predictorIhET_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_.exit.i
	s_or_b32 exec_lo, exec_lo, s0
	v_and_b32_e32 v7, 0xff, v18
	v_and_b32_e32 v3, 0xff, v30
	v_and_b32_e32 v24, 0xff, v24
	v_and_b32_e32 v25, 0xff, v28
	v_and_b32_e32 v5, 0xff, v20
	v_and_b32_e32 v9, 0xff, v26
	v_sub_nc_u32_e32 v15, v7, v3
	v_and_b32_e32 v11, 0xff, v16
	v_and_b32_e32 v13, 0xff, v22
	v_sub_nc_u32_e32 v16, v24, v25
	v_sub_nc_u32_e32 v18, v5, v9
	v_sub_nc_u32_e32 v17, 0, v15
	v_sub_nc_u32_e32 v19, v11, v25
	v_sub_nc_u32_e32 v20, v7, v9
	v_sub_nc_u32_e32 v21, v24, v13
	v_sub_nc_u32_e32 v22, 0, v18
	v_max_i32_e32 v15, v15, v17
	v_sub_nc_u32_e32 v17, 0, v16
	v_sub_nc_u32_e32 v26, 0, v19
	v_sub_nc_u32_e32 v28, 0, v20
	v_sub_nc_u32_e32 v29, 0, v21
	s_mov_b32 s0, exec_lo
	v_max_i32_e32 v16, v16, v17
	v_max_i32_e32 v17, v18, v22
	v_max_i32_e32 v18, v19, v26
	v_max_i32_e32 v19, v20, v28
	v_max_i32_e32 v20, v21, v29
	v_add_nc_u32_e32 v26, v25, v24
	v_add3_u32 v15, v16, v15, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v16, v19, v18, v20
	v_cmpx_lt_u32_e64 v16, v15
	s_cbranch_execz .LBB2_8
; %bb.7:
	v_and_b32_e32 v10, 0xff, v10
	v_and_b32_e32 v14, 0xff, v14
	v_sub_nc_u32_e32 v15, v11, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v10, v10, v9
	v_sub_nc_u32_e32 v14, v7, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v17, 0, v15
	v_add_nc_u32_e32 v7, v9, v7
	v_sub_nc_u32_e32 v18, 0, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v19, 0, v14
	v_max_i32_e32 v15, v15, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_max_i32_e32 v10, v10, v18
	v_max_i32_e32 v14, v14, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v9, v15, v10, v14
	v_add_nc_u32_e32 v10, v13, v11
	v_cmp_lt_u32_e32 vcc_lo, v9, v16
	v_min_u32_e32 v15, v9, v16
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e32 v26, v7, v10, vcc_lo
.LBB2_8:
	s_or_b32 exec_lo, exec_lo, s0
	v_and_b32_e32 v7, 0xff, v12
	v_and_b32_e32 v8, 0xff, v8
	v_sub_nc_u32_e32 v9, v5, v3
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v10, v24, v7
	v_sub_nc_u32_e32 v11, v8, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v12, 0, v9
	v_sub_nc_u32_e32 v13, 0, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v14, 0, v11
	v_max_i32_e32 v9, v9, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_max_i32_e32 v10, v10, v13
	v_max_i32_e32 v11, v11, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v9, v10, v11
	v_cmpx_lt_u32_e64 v9, v15
	s_cbranch_execz .LBB2_10
; %bb.9:
	v_and_b32_e32 v6, 0xff, v6
	v_and_b32_e32 v4, 0xff, v4
	v_sub_nc_u32_e32 v10, v8, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v6, v5, v6
	v_sub_nc_u32_e32 v4, v4, v3
	s_delay_alu instid0(VALU_DEP_3)
	v_sub_nc_u32_e32 v11, 0, v10
	v_add_nc_u32_e32 v3, v3, v5
	v_add_nc_u32_e32 v5, v7, v8
	v_sub_nc_u32_e32 v12, 0, v6
	v_sub_nc_u32_e32 v13, 0, v4
	v_max_i32_e32 v10, v10, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_max_i32_e32 v6, v6, v12
	v_max_i32_e32 v4, v4, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v4, v10, v6, v4
	v_cmp_lt_u32_e32 vcc_lo, v4, v9
	v_cndmask_b32_e32 v26, v3, v5, vcc_lo
.LBB2_10:                               ; %_Z17spatial_predictorIhET_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_.exit170.i
	s_or_b32 exec_lo, exec_lo, s0
	s_bitcmp1_b32 s38, 0
	s_load_b128 s[56:59], s[6:7], 0x30
	s_cselect_b32 s31, -1, 0
	s_load_b256 s[20:27], s[6:7], 0x0
	s_xor_b32 s29, s31, -1
	s_cmp_eq_u32 s36, s37
	v_cvt_f32_i32_e32 v17, v2
	s_cselect_b32 s3, s9, s7
	s_cselect_b32 s2, s8, s6
	s_load_b128 s[52:55], s[2:3], 0x30
	s_load_b32 s1, s[6:7], 0x28
	s_load_b256 s[12:19], s[2:3], 0x0
	s_cselect_b32 s7, s11, s9
	s_cselect_b32 s6, s10, s8
	s_load_b32 s3, s[2:3], 0x28
	s_clause 0x1
	s_load_b128 s[60:63], s[6:7], 0x30
	s_load_b256 s[36:43], s[6:7], 0x0
	s_clause 0x1
	s_load_b128 s[64:67], s[10:11], 0x30
	s_load_b256 s[44:51], s[10:11], 0x0
	s_load_b32 s6, s[6:7], 0x28
	s_load_b32 s7, s[10:11], 0x28
	s_waitcnt lgkmcnt(0)
	s_bitcmp0_b32 s58, 20
	s_cselect_b32 vcc_lo, -1, 0
	s_bitcmp0_b32 s56, 15
	s_cselect_b32 s0, -1, 0
	s_bfe_u32 s33, s22, 0xe000e
	v_cvt_f32_u32_e32 v4, s1
	s_add_i32 s33, s33, 1
	s_bitcmp0_b32 s54, 20
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v4, 1.0, v4, s0
	v_add_nc_u32_e32 v3, -2, v2
	s_bitcmp0_b32 s52, 15
	s_cselect_b32 s2, -1, 0
	v_rcp_f32_e32 v9, v4
	v_mul_f32_e32 v4, v4, v31
	v_cvt_f32_i32_e32 v7, v3
	v_cvt_f32_u32_e32 v3, s33
	s_bfe_u32 s33, s14, 0xe000e
	v_cvt_f32_u32_e32 v15, s7
	v_floor_f32_e32 v4, v4
	s_add_i32 s33, s33, 1
	v_cndmask_b32_e64 v3, 1.0, v3, s0
	v_cvt_f32_u32_e32 v5, s33
	s_bitcmp0_b32 s62, 20
	v_mul_f32_e32 v4, v9, v4
	v_cvt_f32_u32_e32 v9, s3
	v_rcp_f32_e32 v8, v3
	v_cndmask_b32_e64 v13, 1.0, v5, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v9, 1.0, v9, s2
	v_mul_f32_e32 v6, v3, v1
	v_mul_f32_e32 v3, v3, v33
	v_rcp_f32_e32 v14, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_floor_f32_e32 v5, v6
	v_mul_f32_e32 v6, v13, v7
	v_floor_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_floor_f32_e32 v10, v6
	v_mul_f32_e32 v5, v8, v5
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v8, v8, v3
	s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v10, v14, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v6, v1, v5 :: v_dual_cndmask_b32 v5, v31, v4
	v_cndmask_b32_e64 v12, v7, v10, s1
	image_sample_lz v[3:4], v[5:6], s[20:27], s[56:59] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_cndmask_b32_e32 v6, v33, v8, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_bitcmp0_b32 s60, 15
	v_rcp_f32_e32 v8, v9
	s_cselect_b32 s0, -1, 0
	s_bfe_u32 s2, s38, 0xe000e
	v_mul_f32_e32 v9, v9, v31
	s_add_i32 s10, s2, 1
	s_bitcmp0_b32 s66, 20
	v_cvt_f32_u32_e32 v11, s10
	s_cselect_b32 s2, -1, 0
	s_bitcmp0_b32 s64, 15
	v_floor_f32_e32 v9, v9
	s_cselect_b32 s3, -1, 0
	s_bfe_u32 s11, s46, 0xe000e
	v_cndmask_b32_e64 v30, 1.0, v11, s0
	s_add_i32 s11, s11, 1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v8, v8, v9
	v_cvt_f32_u32_e32 v9, s11
	v_rcp_f32_e32 v34, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v11, v31, v8, s1
	v_cndmask_b32_e64 v8, 1.0, v9, s3
	v_cndmask_b32_e64 v9, 1.0, v15, s3
	v_cvt_f32_u32_e32 v15, s6
	s_delay_alu instid0(VALU_DEP_3)
	v_rcp_f32_e32 v16, v8
	v_mul_f32_e32 v19, v8, v1
	v_mul_f32_e32 v8, v8, v33
	v_rcp_f32_e32 v20, v9
	v_mul_f32_e32 v9, v9, v31
	v_cndmask_b32_e64 v15, 1.0, v15, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_floor_f32_e32 v8, v8
	v_mul_f32_e32 v10, v13, v17
	v_floor_f32_e32 v9, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_floor_f32_e32 v10, v10
	s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v9, v20, v9
	v_mul_f32_e32 v20, v30, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v18, v14, v10
	v_mul_f32_e32 v10, v30, v7
	v_cndmask_b32_e64 v9, v31, v9, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_floor_f32_e32 v20, v20
	v_floor_f32_e32 v21, v10
	v_floor_f32_e32 v10, v19
	v_mul_f32_e32 v19, v15, v31
	v_rcp_f32_e32 v15, v15
	image_sample_lz v[5:6], v[5:6], s[20:27], s[56:59] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_mul_f32_e32 v10, v16, v10
	v_floor_f32_e32 v19, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, v1, v10, s2
	v_dual_mul_f32 v1, v16, v8 :: v_dual_mul_f32 v8, v34, v21
	v_mul_f32_e32 v19, v15, v19
	image_sample_lz v[15:16], v[9:10], s[44:51], s[64:67] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_cndmask_b32_e64 v10, v33, v1, s2
	v_cndmask_b32_e32 v29, v7, v8, vcc_lo
	v_dual_cndmask_b32 v28, v31, v19 :: v_dual_mul_f32 v1, v34, v20
	image_sample_lz v[7:8], v[11:12], s[12:19], s[52:55] dmask:0x3 dim:SQ_RSRC_IMG_2D
	image_sample_lz v[19:20], v[9:10], s[44:51], s[64:67] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_cndmask_b32_e64 v12, v17, v18, s1
	image_sample_lz v[9:10], v[28:29], s[36:43], s[60:63] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_cndmask_b32_e32 v29, v17, v1, vcc_lo
	v_add_nc_u32_e32 v1, 2, v2
	image_sample_lz v[21:22], v[11:12], s[12:19], s[52:55] dmask:0x3 dim:SQ_RSRC_IMG_2D
	image_sample_lz v[17:18], v[28:29], s[36:43], s[60:63] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_cvt_f32_i32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v12, v13, v1
	v_mul_f32_e32 v13, v30, v1
	v_floor_f32_e32 v12, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_floor_f32_e32 v13, v13
	v_mul_f32_e32 v13, v34, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v12, v14, v12 :: v_dual_cndmask_b32 v29, v1, v13
	v_cndmask_b32_e64 v12, v1, v12, s1
	image_sample_lz v[13:14], v[11:12], s[12:19], s[52:55] dmask:0x3 dim:SQ_RSRC_IMG_2D
	image_sample_lz v[11:12], v[28:29], s[36:43], s[60:63] dmask:0x3 dim:SQ_RSRC_IMG_2D
	s_and_b32 vcc_lo, exec_lo, s31
	s_waitcnt vmcnt(9)
	v_and_b32_e32 v1, 0xff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v1, v32
	s_waitcnt vmcnt(8)
	v_and_b32_e32 v3, 0xff, v5
	v_sub_nc_u32_e32 v3, v3, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v28, 0, v3
	s_waitcnt vmcnt(7)
	v_and_b32_e32 v5, 0xff, v15
	v_max_i32_e32 v3, v3, v28
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v15, 0xff, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v5, v5, v32
	v_sub_nc_u32_e32 v19, 0, v1
	v_sub_nc_u32_e32 v15, v27, v15
	s_delay_alu instid0(VALU_DEP_3)
	v_sub_nc_u32_e32 v29, 0, v5
	s_waitcnt vmcnt(3)
	v_and_b32_e32 v21, 0xff, v21
	s_waitcnt vmcnt(2)
	v_and_b32_e32 v17, 0xff, v17
	v_max_i32_e32 v1, v1, v19
	v_sub_nc_u32_e32 v30, 0, v15
	v_max_i32_e32 v5, v5, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v19, v21, v17
	v_add_nc_u32_e32 v1, v3, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_max_i32_e32 v15, v15, v30
	v_sub_nc_u32_e32 v3, 0, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v5, v15, v5
	v_add_nc_u32_e32 v15, v17, v21
	v_lshrrev_b32_e32 v17, 1, v1
	v_max_i32_e32 v3, v19, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshrrev_b32_e32 v5, 1, v5
	v_lshrrev_b32_e32 v1, 1, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_max3_i32 v3, v3, v17, v5
	s_cbranch_vccnz .LBB2_12
; %bb.11:
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, 0xff, v13
	v_and_b32_e32 v7, 0xff, v7
	v_and_b32_e32 v9, 0xff, v9
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v11, 0xff, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, v9, v7
	v_add_nc_u32_e32 v5, v11, v5
	v_sub_nc_u32_e32 v9, v1, v27
	v_sub_nc_u32_e32 v11, v1, v32
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshrrev_b32_e32 v7, 1, v7
	v_lshrrev_b32_e32 v5, 1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v7, v7, v32
	v_sub_nc_u32_e32 v5, v5, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_min_i32_e32 v13, v7, v5
	v_max_i32_e32 v5, v7, v5
	v_max3_i32 v7, v9, v11, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v5, v9, v11, v5
	v_sub_nc_u32_e32 v7, 0, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_max3_i32 v3, v3, v5, v7
.LBB2_12:                               ; %_Z18temporal_predictorIhET_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_b.exit.i
	v_and_b32_e32 v4, 0xff, v4
	v_and_b32_e32 v5, 0xff, v6
	v_and_b32_e32 v6, 0xff, v16
	v_and_b32_e32 v7, 0xff, v20
	v_and_b32_e32 v9, 0xff, v22
	v_sub_nc_u32_e32 v4, v4, v24
	v_sub_nc_u32_e32 v5, v5, v25
	v_sub_nc_u32_e32 v6, v6, v24
	v_sub_nc_u32_e32 v7, v25, v7
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v11, 0xff, v18
	v_sub_nc_u32_e32 v13, 0, v4
	v_sub_nc_u32_e32 v15, 0, v5
	v_sub_nc_u32_e32 v16, 0, v6
	v_sub_nc_u32_e32 v17, 0, v7
	v_sub_nc_u32_e32 v18, v9, v11
	v_max_i32_e32 v4, v4, v13
	v_max_i32_e32 v5, v5, v15
	v_max_i32_e32 v6, v6, v16
	v_max_i32_e32 v7, v7, v17
	v_sub_nc_u32_e32 v13, 0, v18
	s_and_not1_b32 vcc_lo, exec_lo, s29
	v_add_nc_u32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v5, v7, v6
	v_add_nc_u32_e32 v6, v11, v9
	v_max_i32_e32 v7, v18, v13
	v_lshrrev_b32_e32 v9, 1, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshrrev_b32_e32 v5, 1, v5
	v_lshrrev_b32_e32 v4, 1, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_max3_i32 v5, v7, v9, v5
	s_cbranch_vccnz .LBB2_14
; %bb.13:
	v_and_b32_e32 v6, 0xff, v14
	v_and_b32_e32 v7, 0xff, v8
	v_and_b32_e32 v8, 0xff, v10
	v_and_b32_e32 v9, 0xff, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, v8, v7
	v_add_nc_u32_e32 v6, v9, v6
	v_sub_nc_u32_e32 v8, v4, v25
	v_sub_nc_u32_e32 v9, v4, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshrrev_b32_e32 v7, 1, v7
	v_lshrrev_b32_e32 v6, 1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v7, v7, v24
	v_sub_nc_u32_e32 v6, v6, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_min_i32_e32 v10, v7, v6
	v_max_i32_e32 v6, v7, v6
	v_max3_i32 v7, v8, v9, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v6, v8, v9, v6
	v_sub_nc_u32_e32 v7, 0, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_max3_i32 v5, v5, v6, v7
.LBB2_14:                               ; %_Z18temporal_predictorIhET_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_b.exit176.i
	v_mad_u64_u32 v[6:7], null, v2, s30, v[0:1]
	v_lshrrev_b32_e32 v8, 1, v23
	v_add_nc_u32_e32 v9, v3, v1
	v_lshrrev_b32_e32 v10, 1, v26
	v_add_nc_u32_e32 v11, v5, v4
	v_sub_nc_u32_e32 v4, v4, v5
	v_sub_nc_u32_e32 v1, v1, v3
	v_min_u32_e32 v0, v9, v8
	v_ashrrev_i32_e32 v7, 31, v6
	v_min_u32_e32 v2, v11, v10
                                        ; implicit-def: $vgpr31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_max_i32_e32 v3, v1, v0
	v_lshlrev_b64 v[0:1], 1, v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_max_i32_e32 v2, v4, v2
	v_and_b32_e32 v3, 0xff, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b16 v2, 8, v2
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_or_b32_e32 v2, v3, v2
	global_store_b16 v[0:1], v2, off
                                        ; implicit-def: $vgpr2_vgpr3
                                        ; implicit-def: $vgpr0_vgpr1
.LBB2_15:                               ; %Flow
	s_and_not1_saveexec_b32 s0, s28
	s_cbranch_execz .LBB2_17
; %bb.16:
	s_clause 0x2
	s_load_b128 s[20:23], s[8:9], 0x30
	s_load_b256 s[12:19], s[8:9], 0x0
	s_load_b32 s1, s[8:9], 0x28
	v_cvt_f32_i32_e32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_bitcmp0_b32 s22, 20
	s_cselect_b32 vcc_lo, -1, 0
	s_bitcmp0_b32 s20, 15
	v_cvt_f32_u32_e32 v4, s1
	s_cselect_b32 s0, -1, 0
	s_bfe_u32 s2, s14, 0xe000e
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s2, s2, 1
	v_cndmask_b32_e64 v4, 1.0, v4, s0
	v_cvt_f32_u32_e32 v3, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v6, v4
	v_cndmask_b32_e64 v3, 1.0, v3, s0
	v_mul_f32_e32 v4, v4, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v5, v3
	v_mul_f32_e32 v3, v3, v1
	v_floor_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_floor_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, v5, v3
	v_dual_mul_f32 v5, v6, v4 :: v_dual_cndmask_b32 v4, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v31, v5, vcc_lo
	v_mad_u64_u32 v[5:6], null, v2, s30, v[0:1]
	image_sample_lz v[3:4], v[3:4], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[0:1], 1, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_lshlrev_b16 v2, 8, v4
	v_and_b32_e32 v3, 0xff, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_or_b32_e32 v2, v3, v2
	global_store_b16 v[0:1], v2, off
.LBB2_17:                               ; %_Z12yadif_doubleI15HIP_vector_typeIhLj2EEEvPT_P13__hip_textureS5_S5_iiiiiiib.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel yadif_uchar2
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 45
		.amdhsa_next_free_sgpr 68
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	yadif_uchar2, .Lfunc_end2-yadif_uchar2
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3484
; NumSgprs: 70
; NumVgprs: 45
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 8
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 70
; NumVGPRsForWavesPerEU: 45
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	yadif_ushort2           ; -- Begin function yadif_ushort2
	.globl	yadif_ushort2
	.p2align	8
	.type	yadif_ushort2,@function
yadif_ushort2:                          ; @yadif_ushort2
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b128 s[28:31], s[0:1], 0x20
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[2:3], null, s15, s3, v[4:5]
	v_cmp_gt_i32_e32 vcc_lo, s28, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s29, v2
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_17
; %bb.1:
	s_load_b128 s[36:39], s[0:1], 0x34
	v_lshrrev_b32_e32 v1, 31, v2
	s_load_b256 s[4:11], s[0:1], 0x0
	v_cvt_f32_i32_e32 v31, v0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, v2, v1
	v_and_b32_e32 v1, -2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v2, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_ne_u32_e64 s36, v1
	s_xor_b32 s28, exec_lo, s0
	s_cbranch_execz .LBB3_15
; %bb.2:
	s_clause 0x2
	s_load_b128 s[20:23], s[8:9], 0x30
	s_load_b256 s[12:19], s[8:9], 0x0
	s_load_b32 s1, s[8:9], 0x28
	v_add_nc_u32_e32 v9, 1, v2
	v_add_nc_u32_e32 v7, 2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cvt_f32_i32_e32 v33, v9
	v_add_nc_u32_e32 v6, 1, v0
	v_cvt_f32_i32_e32 v7, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_cvt_f32_i32_e32 v19, v6
	s_waitcnt lgkmcnt(0)
	s_bitcmp0_b32 s22, 20
	v_cvt_f32_u32_e32 v11, s1
	s_cselect_b32 vcc_lo, -1, 0
	s_bitcmp0_b32 s20, 15
	s_cselect_b32 s0, -1, 0
	s_bfe_u32 s2, s14, 0xe000e
	v_cndmask_b32_e64 v6, 1.0, v11, s0
	v_add_nc_u32_e32 v3, -3, v0
	s_add_i32 s2, s2, 1
	v_add_nc_u32_e32 v5, -1, v0
	v_cvt_f32_u32_e32 v10, s2
	v_mul_f32_e32 v16, v6, v7
	v_mul_f32_e32 v14, v6, v31
	v_cvt_f32_i32_e32 v3, v3
	v_add_nc_u32_e32 v1, -1, v2
	v_dual_mul_f32 v15, v6, v19 :: v_dual_add_nc_u32 v8, 3, v0
	v_cvt_f32_i32_e32 v12, v5
	v_cndmask_b32_e64 v5, 1.0, v10, s0
	v_mul_f32_e32 v10, v6, v3
	v_cvt_f32_i32_e32 v1, v1
	v_add_nc_u32_e32 v4, -2, v0
	v_cvt_f32_i32_e32 v8, v8
	v_rcp_f32_e32 v20, v5
	v_rcp_f32_e32 v21, v6
	v_mul_f32_e32 v9, v5, v1
	v_cvt_f32_i32_e32 v4, v4
	v_mul_f32_e32 v5, v5, v33
	v_mul_f32_e32 v23, v6, v8
	v_floor_f32_e32 v15, v15
	v_floor_f32_e32 v24, v16
	v_mul_f32_e32 v11, v6, v4
	v_floor_f32_e32 v25, v5
	v_mul_f32_e32 v13, v6, v12
	v_floor_f32_e32 v6, v9
	v_floor_f32_e32 v9, v10
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v20, v6
	v_cndmask_b32_e32 v6, v1, v6, vcc_lo
	v_floor_f32_e32 v10, v11
	v_floor_f32_e32 v11, v13
	v_floor_f32_e32 v13, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v5, v21, v9 :: v_dual_mov_b32 v14, v6
	v_mul_f32_e32 v9, v21, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v10, v21, v11
	v_dual_mul_f32 v27, v21, v13 :: v_dual_mov_b32 v22, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v26, v6 :: v_dual_cndmask_b32 v11, v4, v9
	v_dual_cndmask_b32 v13, v12, v10 :: v_dual_mov_b32 v12, v6
	v_cndmask_b32_e32 v5, v3, v5, vcc_lo
	v_mul_f32_e32 v3, v21, v15
	s_clause 0x2
	image_sample_lz v[9:10], v[5:6], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	image_sample_lz v[15:16], v[11:12], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	image_sample_lz v[17:18], v[13:14], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_mul_f32_e32 v14, v21, v24
	v_dual_mul_f32 v12, v20, v25 :: v_dual_mov_b32 v35, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v34, v7, v14, vcc_lo
	v_floor_f32_e32 v4, v23
	v_dual_mul_f32 v4, v21, v4 :: v_dual_cndmask_b32 v21, v31, v27
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_cndmask_b32 v36, v8, v4 :: v_dual_cndmask_b32 v25, v19, v3
	s_clause 0x1
	image_sample_lz v[23:24], v[21:22], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	image_sample_lz v[19:20], v[25:26], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_dual_mov_b32 v37, v6 :: v_dual_cndmask_b32 v6, v33, v12
	image_sample_lz v[7:8], v[34:35], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_mov_b32_e32 v14, v6
	v_mov_b32_e32 v22, v6
	s_waitcnt vmcnt(4)
	v_dual_mov_b32 v26, v6 :: v_dual_and_b32 v15, 0xffff, v15
	s_waitcnt vmcnt(2)
	v_and_b32_e32 v32, 0xffff, v23
	image_sample_lz v[3:4], v[36:37], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_mov_b32_e32 v35, v6
	s_clause 0x3
	image_sample_lz v[29:30], v[13:14], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	image_sample_lz v[27:28], v[21:22], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	image_sample_lz v[25:26], v[25:26], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	image_sample_lz v[21:22], v[34:35], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_and_b32_e32 v34, 0xffff, v17
	v_mov_b32_e32 v12, v6
	v_mov_b32_e32 v37, v6
	s_waitcnt vmcnt(6)
	v_and_b32_e32 v17, 0xffff, v19
	s_waitcnt vmcnt(3)
	v_and_b32_e32 v19, 0xffff, v29
	s_clause 0x2
	image_sample_lz v[5:6], v[5:6], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	image_sample_lz v[11:12], v[11:12], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	image_sample_lz v[13:14], v[36:37], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v27, 0xffff, v27
	s_waitcnt vmcnt(4)
	v_and_b32_e32 v25, 0xffff, v25
	s_waitcnt vmcnt(3)
	v_and_b32_e32 v21, 0xffff, v21
	v_sub_nc_u32_e32 v23, v34, v19
	v_sub_nc_u32_e32 v29, v32, v27
	v_sub_nc_u32_e32 v35, v17, v25
	v_sub_nc_u32_e32 v36, v15, v27
	v_sub_nc_u32_e32 v37, v34, v25
	v_sub_nc_u32_e32 v38, v32, v21
	v_sub_nc_u32_e32 v39, 0, v23
	v_sub_nc_u32_e32 v40, 0, v29
	v_sub_nc_u32_e32 v41, 0, v35
	v_sub_nc_u32_e32 v42, 0, v36
	v_sub_nc_u32_e32 v43, 0, v37
	v_sub_nc_u32_e32 v44, 0, v38
	v_max_i32_e32 v23, v23, v39
	v_max_i32_e32 v29, v29, v40
	v_max_i32_e32 v35, v35, v41
	v_max_i32_e32 v36, v36, v42
	v_max_i32_e32 v37, v37, v43
	v_max_i32_e32 v38, v38, v44
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add3_u32 v29, v29, v23, v35
	v_add_nc_u32_e32 v23, v27, v32
	v_add3_u32 v35, v37, v36, v38
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_u32_e64 v35, v29
	s_cbranch_execz .LBB3_4
; %bb.3:
	v_and_b32_e32 v9, 0xffff, v9
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v13, 0xffff, v13
	v_sub_nc_u32_e32 v23, v15, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v9, v9, v25
	v_sub_nc_u32_e32 v13, v34, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v29, 0, v23
	v_add_nc_u32_e32 v25, v25, v34
	v_sub_nc_u32_e32 v36, 0, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v37, 0, v13
	v_max_i32_e32 v23, v23, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_max_i32_e32 v9, v9, v36
	v_max_i32_e32 v13, v13, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v9, v23, v9, v13
	v_add_nc_u32_e32 v13, v21, v15
	v_cmp_lt_u32_e32 vcc_lo, v9, v35
	v_min_u32_e32 v29, v9, v35
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e32 v23, v25, v13, vcc_lo
.LBB3_4:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v9, 0xffff, v11
	v_and_b32_e32 v7, 0xffff, v7
	v_sub_nc_u32_e32 v11, v17, v19
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_sub_nc_u32_e32 v13, v32, v9
	v_sub_nc_u32_e32 v15, v7, v27
	v_sub_nc_u32_e32 v21, 0, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v25, 0, v13
	v_sub_nc_u32_e32 v34, 0, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_max_i32_e32 v11, v11, v21
	v_max_i32_e32 v13, v13, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v15, v15, v34
	v_add3_u32 v11, v11, v13, v15
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_u32_e64 v11, v29
	s_cbranch_execz .LBB3_6
; %bb.5:
	v_and_b32_e32 v5, 0xffff, v5
	v_and_b32_e32 v3, 0xffff, v3
	v_sub_nc_u32_e32 v13, v7, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v5, v17, v5
	v_sub_nc_u32_e32 v3, v3, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v15, 0, v13
	v_sub_nc_u32_e32 v21, 0, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v23, 0, v3
	v_max_i32_e32 v13, v13, v15
	v_add_nc_u32_e32 v15, v19, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_max_i32_e32 v5, v5, v21
	v_max_i32_e32 v3, v3, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v3, v13, v5, v3
	v_add_nc_u32_e32 v5, v9, v7
	v_cmp_lt_u32_e32 vcc_lo, v3, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v23, v15, v5, vcc_lo
.LBB3_6:                                ; %_Z17spatial_predictorItET_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_.exit.i
	s_or_b32 exec_lo, exec_lo, s0
	v_and_b32_e32 v7, 0xffff, v18
	v_and_b32_e32 v3, 0xffff, v30
	v_and_b32_e32 v24, 0xffff, v24
	v_and_b32_e32 v25, 0xffff, v28
	v_and_b32_e32 v5, 0xffff, v20
	v_and_b32_e32 v9, 0xffff, v26
	v_sub_nc_u32_e32 v15, v7, v3
	v_and_b32_e32 v11, 0xffff, v16
	v_and_b32_e32 v13, 0xffff, v22
	v_sub_nc_u32_e32 v16, v24, v25
	v_sub_nc_u32_e32 v18, v5, v9
	v_sub_nc_u32_e32 v17, 0, v15
	v_sub_nc_u32_e32 v19, v11, v25
	v_sub_nc_u32_e32 v20, v7, v9
	v_sub_nc_u32_e32 v21, v24, v13
	v_sub_nc_u32_e32 v22, 0, v18
	v_max_i32_e32 v15, v15, v17
	v_sub_nc_u32_e32 v17, 0, v16
	v_sub_nc_u32_e32 v26, 0, v19
	v_sub_nc_u32_e32 v28, 0, v20
	v_sub_nc_u32_e32 v29, 0, v21
	s_mov_b32 s0, exec_lo
	v_max_i32_e32 v16, v16, v17
	v_max_i32_e32 v17, v18, v22
	v_max_i32_e32 v18, v19, v26
	v_max_i32_e32 v19, v20, v28
	v_max_i32_e32 v20, v21, v29
	v_add_nc_u32_e32 v26, v25, v24
	v_add3_u32 v15, v16, v15, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v16, v19, v18, v20
	v_cmpx_lt_u32_e64 v16, v15
	s_cbranch_execz .LBB3_8
; %bb.7:
	v_and_b32_e32 v10, 0xffff, v10
	v_and_b32_e32 v14, 0xffff, v14
	v_sub_nc_u32_e32 v15, v11, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v10, v10, v9
	v_sub_nc_u32_e32 v14, v7, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v17, 0, v15
	v_add_nc_u32_e32 v7, v9, v7
	v_sub_nc_u32_e32 v18, 0, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v19, 0, v14
	v_max_i32_e32 v15, v15, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_max_i32_e32 v10, v10, v18
	v_max_i32_e32 v14, v14, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v9, v15, v10, v14
	v_add_nc_u32_e32 v10, v13, v11
	v_cmp_lt_u32_e32 vcc_lo, v9, v16
	v_min_u32_e32 v15, v9, v16
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e32 v26, v7, v10, vcc_lo
.LBB3_8:
	s_or_b32 exec_lo, exec_lo, s0
	v_and_b32_e32 v7, 0xffff, v12
	v_and_b32_e32 v8, 0xffff, v8
	v_sub_nc_u32_e32 v9, v5, v3
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v10, v24, v7
	v_sub_nc_u32_e32 v11, v8, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v12, 0, v9
	v_sub_nc_u32_e32 v13, 0, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v14, 0, v11
	v_max_i32_e32 v9, v9, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_max_i32_e32 v10, v10, v13
	v_max_i32_e32 v11, v11, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v9, v10, v11
	v_cmpx_lt_u32_e64 v9, v15
	s_cbranch_execz .LBB3_10
; %bb.9:
	v_and_b32_e32 v6, 0xffff, v6
	v_and_b32_e32 v4, 0xffff, v4
	v_sub_nc_u32_e32 v10, v8, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v6, v5, v6
	v_sub_nc_u32_e32 v4, v4, v3
	s_delay_alu instid0(VALU_DEP_3)
	v_sub_nc_u32_e32 v11, 0, v10
	v_add_nc_u32_e32 v3, v3, v5
	v_add_nc_u32_e32 v5, v7, v8
	v_sub_nc_u32_e32 v12, 0, v6
	v_sub_nc_u32_e32 v13, 0, v4
	v_max_i32_e32 v10, v10, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_max_i32_e32 v6, v6, v12
	v_max_i32_e32 v4, v4, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v4, v10, v6, v4
	v_cmp_lt_u32_e32 vcc_lo, v4, v9
	v_cndmask_b32_e32 v26, v3, v5, vcc_lo
.LBB3_10:                               ; %_Z17spatial_predictorItET_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_.exit170.i
	s_or_b32 exec_lo, exec_lo, s0
	s_bitcmp1_b32 s38, 0
	s_load_b128 s[56:59], s[6:7], 0x30
	s_cselect_b32 s31, -1, 0
	s_load_b256 s[20:27], s[6:7], 0x0
	s_xor_b32 s29, s31, -1
	s_cmp_eq_u32 s36, s37
	v_cvt_f32_i32_e32 v17, v2
	s_cselect_b32 s3, s9, s7
	s_cselect_b32 s2, s8, s6
	s_load_b128 s[52:55], s[2:3], 0x30
	s_load_b32 s1, s[6:7], 0x28
	s_load_b256 s[12:19], s[2:3], 0x0
	s_cselect_b32 s7, s11, s9
	s_cselect_b32 s6, s10, s8
	s_load_b32 s3, s[2:3], 0x28
	s_clause 0x1
	s_load_b128 s[60:63], s[6:7], 0x30
	s_load_b256 s[36:43], s[6:7], 0x0
	s_clause 0x1
	s_load_b128 s[64:67], s[10:11], 0x30
	s_load_b256 s[44:51], s[10:11], 0x0
	s_load_b32 s6, s[6:7], 0x28
	s_load_b32 s7, s[10:11], 0x28
	s_waitcnt lgkmcnt(0)
	s_bitcmp0_b32 s58, 20
	s_cselect_b32 vcc_lo, -1, 0
	s_bitcmp0_b32 s56, 15
	s_cselect_b32 s0, -1, 0
	s_bfe_u32 s33, s22, 0xe000e
	v_cvt_f32_u32_e32 v4, s1
	s_add_i32 s33, s33, 1
	s_bitcmp0_b32 s54, 20
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v4, 1.0, v4, s0
	v_add_nc_u32_e32 v3, -2, v2
	s_bitcmp0_b32 s52, 15
	s_cselect_b32 s2, -1, 0
	v_rcp_f32_e32 v9, v4
	v_mul_f32_e32 v4, v4, v31
	v_cvt_f32_i32_e32 v7, v3
	v_cvt_f32_u32_e32 v3, s33
	s_bfe_u32 s33, s14, 0xe000e
	v_cvt_f32_u32_e32 v15, s7
	v_floor_f32_e32 v4, v4
	s_add_i32 s33, s33, 1
	v_cndmask_b32_e64 v3, 1.0, v3, s0
	v_cvt_f32_u32_e32 v5, s33
	s_bitcmp0_b32 s62, 20
	v_mul_f32_e32 v4, v9, v4
	v_cvt_f32_u32_e32 v9, s3
	v_rcp_f32_e32 v8, v3
	v_cndmask_b32_e64 v13, 1.0, v5, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v9, 1.0, v9, s2
	v_mul_f32_e32 v6, v3, v1
	v_mul_f32_e32 v3, v3, v33
	v_rcp_f32_e32 v14, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_floor_f32_e32 v5, v6
	v_mul_f32_e32 v6, v13, v7
	v_floor_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_floor_f32_e32 v10, v6
	v_mul_f32_e32 v5, v8, v5
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v8, v8, v3
	s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v10, v14, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v6, v1, v5 :: v_dual_cndmask_b32 v5, v31, v4
	v_cndmask_b32_e64 v12, v7, v10, s1
	image_sample_lz v[3:4], v[5:6], s[20:27], s[56:59] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_cndmask_b32_e32 v6, v33, v8, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_bitcmp0_b32 s60, 15
	v_rcp_f32_e32 v8, v9
	s_cselect_b32 s0, -1, 0
	s_bfe_u32 s2, s38, 0xe000e
	v_mul_f32_e32 v9, v9, v31
	s_add_i32 s10, s2, 1
	s_bitcmp0_b32 s66, 20
	v_cvt_f32_u32_e32 v11, s10
	s_cselect_b32 s2, -1, 0
	s_bitcmp0_b32 s64, 15
	v_floor_f32_e32 v9, v9
	s_cselect_b32 s3, -1, 0
	s_bfe_u32 s11, s46, 0xe000e
	v_cndmask_b32_e64 v30, 1.0, v11, s0
	s_add_i32 s11, s11, 1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v8, v8, v9
	v_cvt_f32_u32_e32 v9, s11
	v_rcp_f32_e32 v34, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v11, v31, v8, s1
	v_cndmask_b32_e64 v8, 1.0, v9, s3
	v_cndmask_b32_e64 v9, 1.0, v15, s3
	v_cvt_f32_u32_e32 v15, s6
	s_delay_alu instid0(VALU_DEP_3)
	v_rcp_f32_e32 v16, v8
	v_mul_f32_e32 v19, v8, v1
	v_mul_f32_e32 v8, v8, v33
	v_rcp_f32_e32 v20, v9
	v_mul_f32_e32 v9, v9, v31
	v_cndmask_b32_e64 v15, 1.0, v15, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_floor_f32_e32 v8, v8
	v_mul_f32_e32 v10, v13, v17
	v_floor_f32_e32 v9, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_floor_f32_e32 v10, v10
	s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v9, v20, v9
	v_mul_f32_e32 v20, v30, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v18, v14, v10
	v_mul_f32_e32 v10, v30, v7
	v_cndmask_b32_e64 v9, v31, v9, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_floor_f32_e32 v20, v20
	v_floor_f32_e32 v21, v10
	v_floor_f32_e32 v10, v19
	v_mul_f32_e32 v19, v15, v31
	v_rcp_f32_e32 v15, v15
	image_sample_lz v[5:6], v[5:6], s[20:27], s[56:59] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_mul_f32_e32 v10, v16, v10
	v_floor_f32_e32 v19, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, v1, v10, s2
	v_dual_mul_f32 v1, v16, v8 :: v_dual_mul_f32 v8, v34, v21
	v_mul_f32_e32 v19, v15, v19
	image_sample_lz v[15:16], v[9:10], s[44:51], s[64:67] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_cndmask_b32_e64 v10, v33, v1, s2
	v_cndmask_b32_e32 v29, v7, v8, vcc_lo
	v_dual_cndmask_b32 v28, v31, v19 :: v_dual_mul_f32 v1, v34, v20
	image_sample_lz v[7:8], v[11:12], s[12:19], s[52:55] dmask:0x3 dim:SQ_RSRC_IMG_2D
	image_sample_lz v[19:20], v[9:10], s[44:51], s[64:67] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_cndmask_b32_e64 v12, v17, v18, s1
	image_sample_lz v[9:10], v[28:29], s[36:43], s[60:63] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_cndmask_b32_e32 v29, v17, v1, vcc_lo
	v_add_nc_u32_e32 v1, 2, v2
	image_sample_lz v[21:22], v[11:12], s[12:19], s[52:55] dmask:0x3 dim:SQ_RSRC_IMG_2D
	image_sample_lz v[17:18], v[28:29], s[36:43], s[60:63] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_cvt_f32_i32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v12, v13, v1
	v_mul_f32_e32 v13, v30, v1
	v_floor_f32_e32 v12, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_floor_f32_e32 v13, v13
	v_mul_f32_e32 v13, v34, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v12, v14, v12 :: v_dual_cndmask_b32 v29, v1, v13
	v_cndmask_b32_e64 v12, v1, v12, s1
	image_sample_lz v[13:14], v[11:12], s[12:19], s[52:55] dmask:0x3 dim:SQ_RSRC_IMG_2D
	image_sample_lz v[11:12], v[28:29], s[36:43], s[60:63] dmask:0x3 dim:SQ_RSRC_IMG_2D
	s_and_b32 vcc_lo, exec_lo, s31
	s_waitcnt vmcnt(9)
	v_and_b32_e32 v1, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v1, v32
	s_waitcnt vmcnt(8)
	v_and_b32_e32 v3, 0xffff, v5
	v_sub_nc_u32_e32 v3, v3, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v28, 0, v3
	s_waitcnt vmcnt(7)
	v_and_b32_e32 v5, 0xffff, v15
	v_max_i32_e32 v3, v3, v28
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v15, 0xffff, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v5, v5, v32
	v_sub_nc_u32_e32 v19, 0, v1
	v_sub_nc_u32_e32 v15, v27, v15
	s_delay_alu instid0(VALU_DEP_3)
	v_sub_nc_u32_e32 v29, 0, v5
	s_waitcnt vmcnt(3)
	v_and_b32_e32 v21, 0xffff, v21
	s_waitcnt vmcnt(2)
	v_and_b32_e32 v17, 0xffff, v17
	v_max_i32_e32 v1, v1, v19
	v_sub_nc_u32_e32 v30, 0, v15
	v_max_i32_e32 v5, v5, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v19, v21, v17
	v_add_nc_u32_e32 v1, v3, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_max_i32_e32 v15, v15, v30
	v_sub_nc_u32_e32 v3, 0, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v5, v15, v5
	v_add_nc_u32_e32 v15, v17, v21
	v_lshrrev_b32_e32 v17, 1, v1
	v_max_i32_e32 v3, v19, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshrrev_b32_e32 v5, 1, v5
	v_lshrrev_b32_e32 v1, 1, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_max3_i32 v3, v3, v17, v5
	s_cbranch_vccnz .LBB3_12
; %bb.11:
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, 0xffff, v13
	v_and_b32_e32 v7, 0xffff, v7
	v_and_b32_e32 v9, 0xffff, v9
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v11, 0xffff, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, v9, v7
	v_add_nc_u32_e32 v5, v11, v5
	v_sub_nc_u32_e32 v9, v1, v27
	v_sub_nc_u32_e32 v11, v1, v32
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshrrev_b32_e32 v7, 1, v7
	v_lshrrev_b32_e32 v5, 1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v7, v7, v32
	v_sub_nc_u32_e32 v5, v5, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_min_i32_e32 v13, v7, v5
	v_max_i32_e32 v5, v7, v5
	v_max3_i32 v7, v9, v11, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v5, v9, v11, v5
	v_sub_nc_u32_e32 v7, 0, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_max3_i32 v3, v3, v5, v7
.LBB3_12:                               ; %_Z18temporal_predictorItET_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_b.exit.i
	v_and_b32_e32 v4, 0xffff, v4
	v_and_b32_e32 v5, 0xffff, v6
	v_and_b32_e32 v6, 0xffff, v16
	v_and_b32_e32 v7, 0xffff, v20
	v_and_b32_e32 v9, 0xffff, v22
	v_sub_nc_u32_e32 v4, v4, v24
	v_sub_nc_u32_e32 v5, v5, v25
	v_sub_nc_u32_e32 v6, v6, v24
	v_sub_nc_u32_e32 v7, v25, v7
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v11, 0xffff, v18
	v_sub_nc_u32_e32 v13, 0, v4
	v_sub_nc_u32_e32 v15, 0, v5
	v_sub_nc_u32_e32 v16, 0, v6
	v_sub_nc_u32_e32 v17, 0, v7
	v_sub_nc_u32_e32 v18, v9, v11
	v_max_i32_e32 v4, v4, v13
	v_max_i32_e32 v5, v5, v15
	v_max_i32_e32 v6, v6, v16
	v_max_i32_e32 v7, v7, v17
	v_sub_nc_u32_e32 v13, 0, v18
	s_and_not1_b32 vcc_lo, exec_lo, s29
	v_add_nc_u32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v5, v7, v6
	v_add_nc_u32_e32 v6, v11, v9
	v_max_i32_e32 v7, v18, v13
	v_lshrrev_b32_e32 v9, 1, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshrrev_b32_e32 v5, 1, v5
	v_lshrrev_b32_e32 v4, 1, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_max3_i32 v5, v7, v9, v5
	s_cbranch_vccnz .LBB3_14
; %bb.13:
	v_and_b32_e32 v6, 0xffff, v14
	v_and_b32_e32 v7, 0xffff, v8
	v_and_b32_e32 v8, 0xffff, v10
	v_and_b32_e32 v9, 0xffff, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, v8, v7
	v_add_nc_u32_e32 v6, v9, v6
	v_sub_nc_u32_e32 v8, v4, v25
	v_sub_nc_u32_e32 v9, v4, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshrrev_b32_e32 v7, 1, v7
	v_lshrrev_b32_e32 v6, 1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v7, v7, v24
	v_sub_nc_u32_e32 v6, v6, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_min_i32_e32 v10, v7, v6
	v_max_i32_e32 v6, v7, v6
	v_max3_i32 v7, v8, v9, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v6, v8, v9, v6
	v_sub_nc_u32_e32 v7, 0, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_max3_i32 v5, v5, v6, v7
.LBB3_14:                               ; %_Z18temporal_predictorItET_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_b.exit176.i
	v_mad_u64_u32 v[6:7], null, v2, s30, v[0:1]
	v_lshrrev_b32_e32 v0, 1, v23
	v_add_nc_u32_e32 v2, v3, v1
	v_lshrrev_b32_e32 v8, 1, v26
	v_add_nc_u32_e32 v9, v5, v4
	v_sub_nc_u32_e32 v3, v1, v3
	v_sub_nc_u32_e32 v4, v4, v5
	v_ashrrev_i32_e32 v7, 31, v6
	v_min_u32_e32 v2, v2, v0
	v_min_u32_e32 v5, v9, v8
                                        ; implicit-def: $vgpr31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 2, v[6:7]
	v_max_i32_e32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_max_i32_e32 v3, v4, v5
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	v_perm_b32 v2, v3, v2, 0x5040100
	global_store_b32 v[0:1], v2, off
                                        ; implicit-def: $vgpr2_vgpr3
                                        ; implicit-def: $vgpr0_vgpr1
.LBB3_15:                               ; %Flow
	s_and_not1_saveexec_b32 s0, s28
	s_cbranch_execz .LBB3_17
; %bb.16:
	s_clause 0x2
	s_load_b128 s[20:23], s[8:9], 0x30
	s_load_b256 s[12:19], s[8:9], 0x0
	s_load_b32 s1, s[8:9], 0x28
	v_cvt_f32_i32_e32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_bitcmp0_b32 s22, 20
	s_cselect_b32 vcc_lo, -1, 0
	s_bitcmp0_b32 s20, 15
	v_cvt_f32_u32_e32 v4, s1
	s_cselect_b32 s0, -1, 0
	s_bfe_u32 s2, s14, 0xe000e
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s2, s2, 1
	v_cndmask_b32_e64 v4, 1.0, v4, s0
	v_cvt_f32_u32_e32 v3, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v6, v4
	v_cndmask_b32_e64 v3, 1.0, v3, s0
	v_mul_f32_e32 v4, v4, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v5, v3
	v_mul_f32_e32 v3, v3, v1
	v_floor_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_floor_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, v5, v3
	v_dual_mul_f32 v5, v6, v4 :: v_dual_cndmask_b32 v4, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v31, v5, vcc_lo
	v_mad_u64_u32 v[5:6], null, v2, s30, v[0:1]
	image_sample_lz v[3:4], v[3:4], s[12:19], s[20:23] dmask:0x3 dim:SQ_RSRC_IMG_2D
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[0:1], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_perm_b32 v2, v4, v3, 0x5040100
	global_store_b32 v[0:1], v2, off
.LBB3_17:                               ; %_Z12yadif_doubleI15HIP_vector_typeItLj2EEEvPT_P13__hip_textureS5_S5_iiiiiiib.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel yadif_ushort2
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 45
		.amdhsa_next_free_sgpr 68
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	yadif_ushort2, .Lfunc_end3-yadif_ushort2
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3460
; NumSgprs: 70
; NumVgprs: 45
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 8
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 70
; NumVGPRsForWavesPerEU: 45
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           1
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           yadif_uchar
    .private_segment_fixed_size: 0
    .sgpr_count:     70
    .sgpr_spill_count: 0
    .symbol:         yadif_uchar.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     33
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           1
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           yadif_ushort
    .private_segment_fixed_size: 0
    .sgpr_count:     70
    .sgpr_spill_count: 0
    .symbol:         yadif_ushort.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     33
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
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    .name:           yadif_uchar2
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
