#include "includes.h"
__global__ void convolutionLayers3DKernel( float *d_Dst, float *d_Src, int imageW, int imageH, int imageD, int kernel_index, int kernel_radius )
{
__shared__ float s_Data[LAYERS_BLOCKDIM_X][LAYERS_BLOCKDIM_Y][(LAYERS_RESULT_STEPS + 2 * LAYERS_HALO_STEPS) * LAYERS_BLOCKDIM_Z + 1];

//Offset to the upper halo edge
const int baseX = blockIdx.x * LAYERS_BLOCKDIM_X + threadIdx.x;
const int baseY = blockIdx.y * LAYERS_BLOCKDIM_Y + threadIdx.y;
const int baseZ = (blockIdx.z * LAYERS_RESULT_STEPS - LAYERS_HALO_STEPS) * LAYERS_BLOCKDIM_Z + threadIdx.z;
d_Src += (baseZ * imageH + baseY) * imageW + baseX;
d_Dst += (baseZ * imageH + baseY) * imageW + baseX;

const int pitch = imageW*imageH;
const float* kernel = &c_Kernel[kernel_index*MAX_KERNEL_LENGTH];

//Main data
#pragma unroll

for (int i = LAYERS_HALO_STEPS; i < LAYERS_HALO_STEPS + LAYERS_RESULT_STEPS; i++) {
s_Data[threadIdx.x][threadIdx.y][threadIdx.z + i * LAYERS_BLOCKDIM_Z] = d_Src[i * LAYERS_BLOCKDIM_Z * pitch];
}

//Upper halo
#pragma unroll

for (int i = 0; i < LAYERS_HALO_STEPS; i++) {
s_Data[threadIdx.x][threadIdx.y][threadIdx.z + i * LAYERS_BLOCKDIM_Z] = (baseZ + i * LAYERS_BLOCKDIM_Z >= 0) ? d_Src[i * LAYERS_BLOCKDIM_Z * pitch] : 0;
}

//Lower halo
#pragma unroll

for (int i = LAYERS_HALO_STEPS + LAYERS_RESULT_STEPS; i < LAYERS_HALO_STEPS + LAYERS_RESULT_STEPS + LAYERS_HALO_STEPS; i++) {
s_Data[threadIdx.x][threadIdx.y][threadIdx.z + i * LAYERS_BLOCKDIM_Z]= (baseZ + i * LAYERS_BLOCKDIM_Z < imageD) ? d_Src[i * LAYERS_BLOCKDIM_Z * pitch] : 0;
}

//Compute and store results
__syncthreads();
#pragma unroll

for (int i = LAYERS_HALO_STEPS; i < LAYERS_HALO_STEPS + LAYERS_RESULT_STEPS; i++) {
float sum = 0;
//#pragma unroll

for (int j = -kernel_radius; j <= kernel_radius; j++) {
sum += kernel[kernel_radius - j] * s_Data[threadIdx.x][threadIdx.y][threadIdx.z + i * LAYERS_BLOCKDIM_Z + j];
}

d_Dst[i * LAYERS_BLOCKDIM_Z * pitch] = sum;
}
}
	.file	"tmpxft_002c5bfe_00000000-6_convolutionLayers3DKernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z52__device_stub__Z25convolutionLayers3DKernelPfS_iiiiiPfS_iiiii
	.type	_Z52__device_stub__Z25convolutionLayers3DKernelPfS_iiiiiPfS_iiiii, @function
_Z52__device_stub__Z25convolutionLayers3DKernelPfS_iiiiiPfS_iiiii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movq	%rsp, %rax
	movq	%rax, 136(%rsp)
	leaq	176(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z25convolutionLayers3DKernelPfS_iiiii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 192
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z52__device_stub__Z25convolutionLayers3DKernelPfS_iiiiiPfS_iiiii, .-_Z52__device_stub__Z25convolutionLayers3DKernelPfS_iiiiiPfS_iiiii
	.globl	_Z25convolutionLayers3DKernelPfS_iiiii
	.type	_Z25convolutionLayers3DKernelPfS_iiiii, @function
_Z25convolutionLayers3DKernelPfS_iiiii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__Z25convolutionLayers3DKernelPfS_iiiiiPfS_iiiii
	.cfi_endproc
.LFE2033:
	.size	_Z25convolutionLayers3DKernelPfS_iiiii, .-_Z25convolutionLayers3DKernelPfS_iiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z25convolutionLayers3DKernelPfS_iiiii"
.LC1:
	.string	"c_Kernel"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z25convolutionLayers3DKernelPfS_iiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movl	$1280, %r9d
	leaq	_ZL8c_Kernel(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL8c_Kernel
	.comm	_ZL8c_Kernel,1280,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convolutionLayers3DKernel( float *d_Dst, float *d_Src, int imageW, int imageH, int imageD, int kernel_index, int kernel_radius )
{
__shared__ float s_Data[LAYERS_BLOCKDIM_X][LAYERS_BLOCKDIM_Y][(LAYERS_RESULT_STEPS + 2 * LAYERS_HALO_STEPS) * LAYERS_BLOCKDIM_Z + 1];

//Offset to the upper halo edge
const int baseX = blockIdx.x * LAYERS_BLOCKDIM_X + threadIdx.x;
const int baseY = blockIdx.y * LAYERS_BLOCKDIM_Y + threadIdx.y;
const int baseZ = (blockIdx.z * LAYERS_RESULT_STEPS - LAYERS_HALO_STEPS) * LAYERS_BLOCKDIM_Z + threadIdx.z;
d_Src += (baseZ * imageH + baseY) * imageW + baseX;
d_Dst += (baseZ * imageH + baseY) * imageW + baseX;

const int pitch = imageW*imageH;
const float* kernel = &c_Kernel[kernel_index*MAX_KERNEL_LENGTH];

//Main data
#pragma unroll

for (int i = LAYERS_HALO_STEPS; i < LAYERS_HALO_STEPS + LAYERS_RESULT_STEPS; i++) {
s_Data[threadIdx.x][threadIdx.y][threadIdx.z + i * LAYERS_BLOCKDIM_Z] = d_Src[i * LAYERS_BLOCKDIM_Z * pitch];
}

//Upper halo
#pragma unroll

for (int i = 0; i < LAYERS_HALO_STEPS; i++) {
s_Data[threadIdx.x][threadIdx.y][threadIdx.z + i * LAYERS_BLOCKDIM_Z] = (baseZ + i * LAYERS_BLOCKDIM_Z >= 0) ? d_Src[i * LAYERS_BLOCKDIM_Z * pitch] : 0;
}

//Lower halo
#pragma unroll

for (int i = LAYERS_HALO_STEPS + LAYERS_RESULT_STEPS; i < LAYERS_HALO_STEPS + LAYERS_RESULT_STEPS + LAYERS_HALO_STEPS; i++) {
s_Data[threadIdx.x][threadIdx.y][threadIdx.z + i * LAYERS_BLOCKDIM_Z]= (baseZ + i * LAYERS_BLOCKDIM_Z < imageD) ? d_Src[i * LAYERS_BLOCKDIM_Z * pitch] : 0;
}

//Compute and store results
__syncthreads();
#pragma unroll

for (int i = LAYERS_HALO_STEPS; i < LAYERS_HALO_STEPS + LAYERS_RESULT_STEPS; i++) {
float sum = 0;
//#pragma unroll

for (int j = -kernel_radius; j <= kernel_radius; j++) {
sum += kernel[kernel_radius - j] * s_Data[threadIdx.x][threadIdx.y][threadIdx.z + i * LAYERS_BLOCKDIM_Z + j];
}

d_Dst[i * LAYERS_BLOCKDIM_Z * pitch] = sum;
}
}
	.text
	.file	"convolutionLayers3DKernel.hip"
	.globl	_Z40__device_stub__convolutionLayers3DKernelPfS_iiiii # -- Begin function _Z40__device_stub__convolutionLayers3DKernelPfS_iiiii
	.type	_Z40__device_stub__convolutionLayers3DKernelPfS_iiiii,@function
_Z40__device_stub__convolutionLayers3DKernelPfS_iiiii: # @_Z40__device_stub__convolutionLayers3DKernelPfS_iiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z25convolutionLayers3DKernelPfS_iiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z40__device_stub__convolutionLayers3DKernelPfS_iiiii, .Lfunc_end0-_Z40__device_stub__convolutionLayers3DKernelPfS_iiiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z25convolutionLayers3DKernelPfS_iiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$c_Kernel, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$1280, %r9d                     # imm = 0x500
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	c_Kernel,@object                # @c_Kernel
	.local	c_Kernel
	.comm	c_Kernel,1280,16
	.type	_Z25convolutionLayers3DKernelPfS_iiiii,@object # @_Z25convolutionLayers3DKernelPfS_iiiii
	.section	.rodata,"a",@progbits
	.globl	_Z25convolutionLayers3DKernelPfS_iiiii
	.p2align	3, 0x0
_Z25convolutionLayers3DKernelPfS_iiiii:
	.quad	_Z40__device_stub__convolutionLayers3DKernelPfS_iiiii
	.size	_Z25convolutionLayers3DKernelPfS_iiiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z25convolutionLayers3DKernelPfS_iiiii"
	.size	.L__unnamed_1, 39

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"c_Kernel"
	.size	.L__unnamed_2, 9

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z40__device_stub__convolutionLayers3DKernelPfS_iiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym c_Kernel
	.addrsig_sym _Z25convolutionLayers3DKernelPfS_iiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z25convolutionLayers3DKernelPfS_iiiii ; -- Begin function _Z25convolutionLayers3DKernelPfS_iiiii
	.globl	_Z25convolutionLayers3DKernelPfS_iiiii
	.p2align	8
	.type	_Z25convolutionLayers3DKernelPfS_iiiii,@function
_Z25convolutionLayers3DKernelPfS_iiiii: ; @_Z25convolutionLayers3DKernelPfS_iiiii
; %bb.0:                                ; %.preheader61
	s_load_b256 s[4:11], s[0:1], 0x0
	v_bfe_u32 v6, v0, 20, 10
	s_lshl_b32 s2, s15, 5
	v_bfe_u32 v14, v0, 10, 10
	v_and_b32_e32 v15, 0x3ff, v0
	s_load_b32 s12, s[0:1], 0x20
	v_add3_u32 v7, v6, s2, -16
	s_lshl_b32 s2, s14, 3
	v_lshlrev_b32_e32 v6, 2, v6
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v1, v7, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add3_u32 v1, s2, v14, v1
	s_lshl_b32 s2, s13, 3
	v_mul_lo_u32 v1, v1, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add3_u32 v0, s2, v15, v1
	s_mul_i32 s2, s9, s8
	s_lshl_b32 s8, s2, 4
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	s_ashr_i32 s9, s8, 31
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	s_lshl_b64 s[6:7], s[8:9], 2
	s_lshl_b64 s[8:9], s[2:3], 5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v4, s6
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v8, s8
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, v10, s8
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v12, s8
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v13, vcc_lo
	s_clause 0x3
	global_load_b32 v16, v[8:9], off
	global_load_b32 v10, v[10:11], off
	global_load_b32 v11, v[12:13], off
	global_load_b32 v12, v[2:3], off
	v_mul_u32_u24_e32 v8, 0x104, v14
	v_mul_u32_u24_e32 v9, 0x820, v15
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v6, v9, v8, v6
	v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v8, 0
	s_waitcnt vmcnt(2)
	ds_store_2addr_b32 v6, v16, v10 offset0:16 offset1:24
	s_waitcnt vmcnt(0)
	ds_store_2addr_b32 v6, v11, v12 offset0:32 offset1:40
	v_cmpx_lt_i32_e32 -1, v7
	s_cbranch_execz .LBB0_2
; %bb.1:
	global_load_b32 v9, v[4:5], off
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v9
	v_cmpx_lt_i32_e32 -9, v7
	s_cbranch_execz .LBB0_4
; %bb.3:
	s_lshl_b64 s[14:15], s[2:3], 7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_sub_co_u32 v4, vcc_lo, v2, s14
	v_subrev_co_ci_u32_e32 v5, vcc_lo, s15, v3, vcc_lo
	global_load_b32 v8, v[4:5], off
.LBB0_4:                                ; %.preheader.preheader
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v5, 48, v7
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v8 offset:32
	v_cmp_gt_i32_e32 vcc_lo, s10, v5
	v_mov_b32_e32 v5, 0
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_6
; %bb.5:
	v_add_co_u32 v8, vcc_lo, v2, s8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v3, vcc_lo
	global_load_b32 v5, v[8:9], off
.LBB0_6:                                ; %.preheader.1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v7, 56, v7
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v5 offset:192
	v_cmpx_gt_i32_e64 s10, v7
	s_cbranch_execz .LBB0_8
; %bb.7:
	s_lshl_b64 s[8:9], s[2:3], 6
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v2, vcc_lo, v2, s8
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_load_b32 v4, v[2:3], off
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_mul_i32 s0, s11, 0x50
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, c_Kernel@rel32@lo+4
	s_addc_u32 s9, s9, c_Kernel@rel32@hi+12
	s_ashr_i32 s1, s0, 31
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_lshl_b64 s[0:1], s[0:1], 2
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_add_u32 s3, s0, s8
	s_addc_u32 s8, s1, s9
	s_cmp_gt_i32 s12, -1
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v4 offset:224
	s_cselect_b32 s9, -1, 0
	s_cmp_lt_i32 s12, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_14
; %bb.9:                                ; %.lr.ph.preheader
	s_lshl_b32 s0, s12, 2
	v_mov_b32_e32 v3, 0
	v_subrev_nc_u32_e32 v2, s0, v6
	s_lshl_b32 s0, s12, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 s4, s0
	v_add_nc_u32_e32 v4, 64, v2
.LBB0_10:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_ashr_i32 s5, s4, 31
	ds_load_b32 v5, v4
	s_lshl_b64 s[10:11], s[4:5], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s10, s3, s10
	s_addc_u32 s11, s8, s11
	s_add_i32 s4, s4, -1
	s_load_b32 s1, s[10:11], 0x0
	v_add_nc_u32_e32 v4, 4, v4
	s_cmp_eq_u32 s4, -1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v3, s1, v5
	s_cbranch_scc0 .LBB0_10
; %bb.11:                               ; %._crit_edge
	v_add_co_u32 v7, vcc_lo, v0, s6
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v1, vcc_lo
	v_add_nc_u32_e32 v4, 0x60, v2
	v_mov_b32_e32 v2, 0
	global_store_b32 v[7:8], v3, off
.LBB0_12:                               ; %.lr.ph.1
                                        ; =>This Inner Loop Header: Depth=1
	s_ashr_i32 s1, s0, 31
	ds_load_b32 v3, v4
	s_lshl_b64 s[4:5], s[0:1], 2
	v_add_nc_u32_e32 v4, 4, v4
	s_add_u32 s4, s3, s4
	s_addc_u32 s5, s8, s5
	s_add_i32 s0, s0, -1
	s_load_b32 s1, s[4:5], 0x0
	s_cmp_eq_u32 s0, -1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v2, s1, v3
	s_cbranch_scc0 .LBB0_12
; %bb.13:                               ; %Flow132
	s_mov_b32 s0, 0
	s_branch .LBB0_15
.LBB0_14:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr2
.LBB0_15:                               ; %Flow133
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_17
; %bb.16:                               ; %._crit_edge.1.critedge
	v_add_co_u32 v3, vcc_lo, v0, s6
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v1, vcc_lo
	v_mov_b32_e32 v2, 0
	global_store_b32 v[3:4], v2, off
.LBB0_17:                               ; %._crit_edge.1
	s_mul_i32 s0, s2, 24
	v_cndmask_b32_e64 v4, 0, 1, s9
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[0:1], 2
	v_add_co_u32 v7, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v1, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s9
	global_store_b32 v[7:8], v2, off
	s_cbranch_vccnz .LBB0_24
; %bb.18:                               ; %.lr.ph.2.preheader
	s_lshl_b32 s0, s12, 2
	v_mov_b32_e32 v5, 0
	v_subrev_nc_u32_e32 v3, s0, v6
	s_lshl_b32 s0, s12, 1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v2, 0x80, v3
.LBB0_19:                               ; %.lr.ph.2
                                        ; =>This Inner Loop Header: Depth=1
	s_ashr_i32 s1, s0, 31
	ds_load_b32 v6, v2
	s_lshl_b64 s[4:5], s[0:1], 2
	v_add_nc_u32_e32 v2, 4, v2
	s_add_u32 s4, s3, s4
	s_addc_u32 s5, s8, s5
	s_add_i32 s0, s0, -1
	s_load_b32 s1, s[4:5], 0x0
	s_cmp_lg_u32 s0, -1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v5, s1, v6
	s_cbranch_scc1 .LBB0_19
; %bb.20:                               ; %._crit_edge.2
	s_lshl_b32 s0, s2, 5
	v_cmp_ne_u32_e32 vcc_lo, 1, v4
	s_ashr_i32 s1, s0, 31
	v_mov_b32_e32 v2, 0
	s_lshl_b64 s[0:1], s[0:1], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, s0, v0, s0
	v_add_co_ci_u32_e64 v7, s0, s1, v1, s0
	global_store_b32 v[6:7], v5, off
	s_cbranch_vccnz .LBB0_23
; %bb.21:                               ; %.lr.ph.3.preheader
	v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v3, 0xa0, v3
	s_lshl_b32 s0, s12, 1
.LBB0_22:                               ; %.lr.ph.3
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s1, s0, 31
	ds_load_b32 v4, v3
	s_lshl_b64 s[4:5], s[0:1], 2
	s_add_u32 s4, s3, s4
	s_addc_u32 s5, s8, s5
	s_add_i32 s0, s0, -1
	s_load_b32 s1, s[4:5], 0x0
	v_add_nc_u32_e32 v3, 4, v3
	s_cmp_eq_u32 s0, -1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v2, s1, v4
	s_cbranch_scc0 .LBB0_22
.LBB0_23:                               ; %Flow130
	s_mov_b32 s0, 0
	s_branch .LBB0_25
.LBB0_24:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr2
.LBB0_25:                               ; %Flow131
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_27
; %bb.26:                               ; %._crit_edge.3.critedge
	s_lshl_b32 s0, s2, 5
	v_mov_b32_e32 v2, 0
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[0:1], 2
	v_add_co_u32 v3, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[3:4], v2, off
.LBB0_27:                               ; %._crit_edge.3
	s_mul_i32 s0, s2, 40
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s1, s0, 31
	s_lshl_b64 s[0:1], s[0:1], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v0, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z25convolutionLayers3DKernelPfS_iiiii
		.amdhsa_group_segment_fixed_size 16640
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 36
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z25convolutionLayers3DKernelPfS_iiiii, .Lfunc_end0-_Z25convolutionLayers3DKernelPfS_iiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1236
; NumSgprs: 18
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 16640 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	c_Kernel                ; @c_Kernel
	.type	c_Kernel,@object
	.section	.bss,"aw",@nobits
	.globl	c_Kernel
	.p2align	4, 0x0
c_Kernel:
	.zero	1280
	.size	c_Kernel, 1280

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym c_Kernel
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 16640
    .kernarg_segment_align: 8
    .kernarg_segment_size: 36
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z25convolutionLayers3DKernelPfS_iiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z25convolutionLayers3DKernelPfS_iiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     17
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
