﻿#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <time.h>
#include <cuda_runtime.h>

#define BLOCK_SIZE 32

#define WA (10 * BLOCK_SIZE) // Matrix A width
#define HA (10 * BLOCK_SIZE) // Matrix A height
#define WB (20 * BLOCK_SIZE) // Matrix B width
#define HB WA  // Matrix B height
#define WC WB  // Matrix C width 
#define HC HA  // Matrix C height

void MatInit(float* data, int size)
{
    for (int i = 0; i < size; ++i)
        data[i] = rand() / (float)RAND_MAX;
}

__device__  float * GetSubMatrix(float *matrix, int m, int index, int width)
{
	return  matrix+width*BLOCK_SIZE*index+BLOCK_SIZE*m;
}

void CpuMul(float* C, const float* A, const float* B, int hA, int wA, int wB)
{
    for (int i = 0; i < hA; ++i)
        for (int j = 0; j < wB; ++j)
		{
            double sum = 0;
            for (int k = 0; k < wA; ++k) 
			{
                double a = A[i * wA + k];
                double b = B[k * wB + j];
                sum += a * b;
            }
            C[i * wB + j] = (float)sum;
        }
}

__global__ void GpuMul1( float* C, float* A, float* B, int wA, int wB)
{
    int bx = blockIdx.x;
    int tx = threadIdx.x;    

	int idx = bx * blockDim.x + tx;
	int row = idx / wB;
	int column = idx % wB;

	float sum = 0;

	for(int i = 0; i < wA; ++i)
	{
		sum += A[row * wA + i] * B[i * wB + column];
	}
	C[row * wB + column] = sum;
//	printf("%d %d %d %d %f\n",row * wB + column,idx,row,column,sum);
}

__global__ void GpuMul2( float* C, float* A, float* B, int wA, int wB)
{
    __shared__ float As[BLOCK_SIZE][BLOCK_SIZE];

    __shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];

    int bx = blockIdx.x;
    int by = blockIdx.y;

    int tx = threadIdx.x;
    int ty = threadIdx.y;     

    float sum = 0;

    for (int m= 0; m<wA/BLOCK_SIZE; m++) 
	{
		float *subA=GetSubMatrix(A, m, by, wA);

		float *subB=GetSubMatrix(B, bx, m, wB);

        As[ty][tx] = *(subA+ wA * ty + tx);
        Bs[ty][tx] = *(subB+ wB * ty + tx);

        __syncthreads();
        for (int k = 0; k < BLOCK_SIZE; ++k)
            sum += As[ty][k] * Bs[k][tx];
        __syncthreads();
    }

	float *subC=GetSubMatrix(C, bx, by, wB);
    *(subC + wB * ty + tx)= sum;
}

int main()
{
    // allocate host memory for matrices A and B
    int size_A = WA * HA;
    int mem_size_A = sizeof(float) * size_A;
    float* h_A = (float*) malloc(mem_size_A);

    int size_B = WB * HB;
    int mem_size_B = sizeof(float) * size_B;
    float* h_B = (float*) malloc(mem_size_B);
	clock_t start, finish;
	double time[3];

    MatInit(h_A, size_A);
    MatInit(h_B, size_B);

    float* d_A;
    cudaMalloc((void**) &d_A, mem_size_A);
    float* d_B;
    cudaMalloc((void**) &d_B, mem_size_B);

    // copy host memory to device
    cudaMemcpy(d_A, h_A, mem_size_A, cudaMemcpyHostToDevice) ;
    cudaMemcpy(d_B, h_B, mem_size_B, cudaMemcpyHostToDevice) ;

    // allocate device memory for result
    int size_C = WC * HC;
    int mem_size_C = sizeof(float) * size_C;
    float* d1_C;
    cudaMalloc((void**) &d1_C, mem_size_C);
	float* d2_C;
    cudaMalloc((void**) &d2_C, mem_size_C);

    // allocate host memory for the result
	float* h0_C = (float*) malloc(mem_size_C);
    float* h1_C = (float*) malloc(mem_size_C);
	float* h2_C = (float*) malloc(mem_size_C);
    
	start=clock();
	int threads1 = BLOCK_SIZE * BLOCK_SIZE;
	int grid1 = WC*HC/threads1;
    GpuMul1<<< grid1, threads1 >>>(d1_C, d_A, d_B, WA, WB);
	cudaThreadSynchronize();
	finish=clock();  
	time[1]=(double)(finish-start)/CLOCKS_PER_SEC;
    cudaMemcpy(h1_C, d1_C, mem_size_C, cudaMemcpyDeviceToHost);

	start=clock();
	dim3 threads2(BLOCK_SIZE, BLOCK_SIZE);
	dim3 grid2(WC / threads2.x, HC / threads2.y);
    GpuMul2<<< grid2, threads2 >>>(d2_C, d_A, d_B, WA, WB);
	cudaThreadSynchronize();
	finish=clock();  
	time[2]=(double)(finish-start)/CLOCKS_PER_SEC;
    cudaMemcpy(h2_C, d2_C, mem_size_C, cudaMemcpyDeviceToHost);

	start=clock();
    CpuMul(h0_C, h_A, h_B, HA, WA, WB);
	finish=clock();
	time[0]=(double)(finish-start)/CLOCKS_PER_SEC;

//	for(int i=0;i<WC*HC;i++)
//		printf("%f %f %f\n",h0_C[i],h1_C[i],h2_C[i]);

	printf("%f  %f  %f",time[0],time[1],time[2]);

    // clean up memory
    free(h_A);
    free(h_B);
    free(h0_C);
	free(h1_C);
	free(h2_C);
    cudaFree(d_A);
    cudaFree(d_B);
    cudaFree(d1_C);
	cudaFree(d2_C);
    cudaThreadExit();
}

 
	.file	"tmpxft_002bd3f0_00000000-6_lab4.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2033:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z7MatInitPfi
	.type	_Z7MatInitPfi, @function
_Z7MatInitPfi:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	xorl	%ebx, %ebx
.L3:
	cmpl	%ebx, %ebp
	jle	.L7
	call	rand@PLT
	cvtsi2ssl	%eax, %xmm0
	mulss	.LC0(%rip), %xmm0
	movss	%xmm0, (%r12,%rbx,4)
	incq	%rbx
	jmp	.L3
.L7:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z7MatInitPfi, .-_Z7MatInitPfi
	.globl	_Z12GetSubMatrixPfiii
	.type	_Z12GetSubMatrixPfiii, @function
_Z12GetSubMatrixPfiii:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z12GetSubMatrixPfiii, .-_Z12GetSubMatrixPfiii
	.globl	_Z6CpuMulPfPKfS1_iii
	.type	_Z6CpuMulPfPKfS1_iii, @function
_Z6CpuMulPfPKfS1_iii:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%r10d, %r10d
	xorl	%r11d, %r11d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	xorl	%ecx, %ecx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdx, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movslq	%r9d, %rbx
	salq	$2, %rbx
.L11:
	cmpl	%r12d, %r11d
	jge	.L10
	movslq	%r10d, %rax
	leaq	(%rdi,%rax,4), %r14
	movslq	%ecx, %rax
	leaq	(%rsi,%rax,4), %r13
	xorl	%eax, %eax
.L16:
	cmpl	%eax, %r9d
	jle	.L13
	leaq	0(%rbp,%rax,4), %r15
	xorl	%edx, %edx
	xorps	%xmm0, %xmm0
.L14:
	cmpl	%edx, %r8d
	jle	.L18
	cvtss2sd	0(%r13,%rdx,4), %xmm1
	cvtss2sd	(%r15), %xmm2
	mulsd	%xmm2, %xmm1
	incq	%rdx
	addq	%rbx, %r15
	addsd	%xmm1, %xmm0
	jmp	.L14
.L18:
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%r14,%rax,4)
	incq	%rax
	jmp	.L16
.L13:
	incl	%r11d
	addl	%r9d, %r10d
	addl	%r8d, %ecx
	jmp	.L11
.L10:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z6CpuMulPfPKfS1_iii, .-_Z6CpuMulPfPKfS1_iii
	.globl	_Z32__device_stub__Z7GpuMul1PfS_S_iiPfS_S_ii
	.type	_Z32__device_stub__Z7GpuMul1PfS_S_iiPfS_S_ii, @function
_Z32__device_stub__Z7GpuMul1PfS_S_iiPfS_S_ii:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z7GpuMul1PfS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L19:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z32__device_stub__Z7GpuMul1PfS_S_iiPfS_S_ii, .-_Z32__device_stub__Z7GpuMul1PfS_S_iiPfS_S_ii
	.globl	_Z7GpuMul1PfS_S_ii
	.type	_Z7GpuMul1PfS_S_ii, @function
_Z7GpuMul1PfS_S_ii:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z7GpuMul1PfS_S_iiPfS_S_ii
	.cfi_endproc
.LFE2056:
	.size	_Z7GpuMul1PfS_S_ii, .-_Z7GpuMul1PfS_S_ii
	.globl	_Z32__device_stub__Z7GpuMul2PfS_S_iiPfS_S_ii
	.type	_Z32__device_stub__Z7GpuMul2PfS_S_iiPfS_S_ii, @function
_Z32__device_stub__Z7GpuMul2PfS_S_iiPfS_S_ii:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z7GpuMul2PfS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L24:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z32__device_stub__Z7GpuMul2PfS_S_iiPfS_S_ii, .-_Z32__device_stub__Z7GpuMul2PfS_S_iiPfS_S_ii
	.globl	_Z7GpuMul2PfS_S_ii
	.type	_Z7GpuMul2PfS_S_ii, @function
_Z7GpuMul2PfS_S_ii:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z7GpuMul2PfS_S_iiPfS_S_ii
	.cfi_endproc
.LFE2058:
	.size	_Z7GpuMul2PfS_S_ii, .-_Z7GpuMul2PfS_S_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC3:
	.string	"%f  %f  %f"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$409600, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$819200, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$102400, %esi
	movq	%rbp, %rdi
	movq	%rax, %rbx
	call	_Z7MatInitPfi
	movl	$204800, %esi
	movq	%rbx, %rdi
	call	_Z7MatInitPfi
	leaq	16(%rsp), %rdi
	movl	$409600, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$819200, %esi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$409600, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$819200, %edx
	call	cudaMemcpy@PLT
	leaq	32(%rsp), %rdi
	movl	$819200, %esi
	call	cudaMalloc@PLT
	movl	$819200, %esi
	leaq	40(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$819200, %edi
	call	malloc@PLT
	movl	$819200, %edi
	movq	%rax, %r14
	call	malloc@PLT
	movl	$819200, %edi
	movq	%rax, %r13
	call	malloc@PLT
	movq	%rax, %r12
	call	clock@PLT
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$536870937, %edi
	salq	$10, %rdx
	movq	%rax, %r15
	movl	$1, %ecx
	salq	$3, %rdi
	movl	$1, %esi
	movq	%rdx, 60(%rsp)
	movl	$1, 68(%rsp)
	movq	%rdi, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$320, %ecx
	movl	$640, %r8d
	movq	32(%rsp), %rdi
	call	_Z32__device_stub__Z7GpuMul1PfS_S_iiPfS_S_ii
.L30:
	call	cudaThreadSynchronize@PLT
	call	clock@PLT
	movq	32(%rsp), %rsi
	movl	$2, %ecx
	movq	%r13, %rdi
	subq	%r15, %rax
	movl	$819200, %edx
	cvtsi2sdq	%rax, %xmm0
	divsd	.LC2(%rip), %xmm0
	movsd	%xmm0, (%rsp)
	call	cudaMemcpy@PLT
	call	clock@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movl	$1, 68(%rsp)
	movq	%rax, %r15
	movabsq	$42949672980, %rdi
	movabsq	$137438953504, %rdx
	movq	%rdi, 60(%rsp)
	movq	%rdx, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L31
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$320, %ecx
	movl	$640, %r8d
	movq	40(%rsp), %rdi
	call	_Z32__device_stub__Z7GpuMul2PfS_S_iiPfS_S_ii
.L31:
	call	cudaThreadSynchronize@PLT
	call	clock@PLT
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movq	%r12, %rdi
	subq	%r15, %rax
	movl	$819200, %edx
	cvtsi2sdq	%rax, %xmm2
	divsd	.LC2(%rip), %xmm2
	movsd	%xmm2, 8(%rsp)
	call	cudaMemcpy@PLT
	call	clock@PLT
	movl	$320, %ecx
	movq	%rbx, %rdx
	movq	%rbp, %rsi
	movl	$640, %r9d
	movl	$320, %r8d
	movq	%r14, %rdi
	movq	%rax, %r15
	call	_Z6CpuMulPfPKfS1_iii
	call	clock@PLT
	movsd	8(%rsp), %xmm2
	movsd	(%rsp), %xmm1
	leaq	.LC3(%rip), %rsi
	subq	%r15, %rax
	movl	$2, %edi
	cvtsi2sdq	%rax, %xmm0
	movb	$3, %al
	divsd	.LC2(%rip), %xmm0
	call	__printf_chk@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	%r14, %rdi
	call	free@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	call	cudaThreadExit@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L32
	call	__stack_chk_fail@PLT
.L32:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z7GpuMul2PfS_S_ii"
.LC5:
	.string	"_Z7GpuMul1PfS_S_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z7GpuMul2PfS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7GpuMul1PfS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2060:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	805306368
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC2:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

﻿#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <time.h>
#include <hip/hip_runtime.h>

#define BLOCK_SIZE 32

#define WA (10 * BLOCK_SIZE) // Matrix A width
#define HA (10 * BLOCK_SIZE) // Matrix A height
#define WB (20 * BLOCK_SIZE) // Matrix B width
#define HB WA  // Matrix B height
#define WC WB  // Matrix C width 
#define HC HA  // Matrix C height

void MatInit(float* data, int size)
{
    for (int i = 0; i < size; ++i)
        data[i] = rand() / (float)RAND_MAX;
}

__device__  float * GetSubMatrix(float *matrix, int m, int index, int width)
{
	return  matrix+width*BLOCK_SIZE*index+BLOCK_SIZE*m;
}

void CpuMul(float* C, const float* A, const float* B, int hA, int wA, int wB)
{
    for (int i = 0; i < hA; ++i)
        for (int j = 0; j < wB; ++j)
		{
            double sum = 0;
            for (int k = 0; k < wA; ++k) 
			{
                double a = A[i * wA + k];
                double b = B[k * wB + j];
                sum += a * b;
            }
            C[i * wB + j] = (float)sum;
        }
}

__global__ void GpuMul1( float* C, float* A, float* B, int wA, int wB)
{
    int bx = blockIdx.x;
    int tx = threadIdx.x;    

	int idx = bx * blockDim.x + tx;
	int row = idx / wB;
	int column = idx % wB;

	float sum = 0;

	for(int i = 0; i < wA; ++i)
	{
		sum += A[row * wA + i] * B[i * wB + column];
	}
	C[row * wB + column] = sum;
//	printf("%d %d %d %d %f\n",row * wB + column,idx,row,column,sum);
}

__global__ void GpuMul2( float* C, float* A, float* B, int wA, int wB)
{
    __shared__ float As[BLOCK_SIZE][BLOCK_SIZE];

    __shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];

    int bx = blockIdx.x;
    int by = blockIdx.y;

    int tx = threadIdx.x;
    int ty = threadIdx.y;     

    float sum = 0;

    for (int m= 0; m<wA/BLOCK_SIZE; m++) 
	{
		float *subA=GetSubMatrix(A, m, by, wA);

		float *subB=GetSubMatrix(B, bx, m, wB);

        As[ty][tx] = *(subA+ wA * ty + tx);
        Bs[ty][tx] = *(subB+ wB * ty + tx);

        __syncthreads();
        for (int k = 0; k < BLOCK_SIZE; ++k)
            sum += As[ty][k] * Bs[k][tx];
        __syncthreads();
    }

	float *subC=GetSubMatrix(C, bx, by, wB);
    *(subC + wB * ty + tx)= sum;
}

int main()
{
    // allocate host memory for matrices A and B
    int size_A = WA * HA;
    int mem_size_A = sizeof(float) * size_A;
    float* h_A = (float*) malloc(mem_size_A);

    int size_B = WB * HB;
    int mem_size_B = sizeof(float) * size_B;
    float* h_B = (float*) malloc(mem_size_B);
	clock_t start, finish;
	double time[3];

    MatInit(h_A, size_A);
    MatInit(h_B, size_B);

    float* d_A;
    hipMalloc((void**) &d_A, mem_size_A);
    float* d_B;
    hipMalloc((void**) &d_B, mem_size_B);

    // copy host memory to device
    hipMemcpy(d_A, h_A, mem_size_A, hipMemcpyHostToDevice) ;
    hipMemcpy(d_B, h_B, mem_size_B, hipMemcpyHostToDevice) ;

    // allocate device memory for result
    int size_C = WC * HC;
    int mem_size_C = sizeof(float) * size_C;
    float* d1_C;
    hipMalloc((void**) &d1_C, mem_size_C);
	float* d2_C;
    hipMalloc((void**) &d2_C, mem_size_C);

    // allocate host memory for the result
	float* h0_C = (float*) malloc(mem_size_C);
    float* h1_C = (float*) malloc(mem_size_C);
	float* h2_C = (float*) malloc(mem_size_C);
    
	start=clock();
	int threads1 = BLOCK_SIZE * BLOCK_SIZE;
	int grid1 = WC*HC/threads1;
    GpuMul1<<< grid1, threads1 >>>(d1_C, d_A, d_B, WA, WB);
	hipDeviceSynchronize();
	finish=clock();  
	time[1]=(double)(finish-start)/CLOCKS_PER_SEC;
    hipMemcpy(h1_C, d1_C, mem_size_C, hipMemcpyDeviceToHost);

	start=clock();
	dim3 threads2(BLOCK_SIZE, BLOCK_SIZE);
	dim3 grid2(WC / threads2.x, HC / threads2.y);
    GpuMul2<<< grid2, threads2 >>>(d2_C, d_A, d_B, WA, WB);
	hipDeviceSynchronize();
	finish=clock();  
	time[2]=(double)(finish-start)/CLOCKS_PER_SEC;
    hipMemcpy(h2_C, d2_C, mem_size_C, hipMemcpyDeviceToHost);

	start=clock();
    CpuMul(h0_C, h_A, h_B, HA, WA, WB);
	finish=clock();
	time[0]=(double)(finish-start)/CLOCKS_PER_SEC;

//	for(int i=0;i<WC*HC;i++)
//		printf("%f %f %f\n",h0_C[i],h1_C[i],h2_C[i]);

	printf("%f  %f  %f",time[0],time[1],time[2]);

    // clean up memory
    free(h_A);
    free(h_B);
    free(h0_C);
	free(h1_C);
	free(h2_C);
    hipFree(d_A);
    hipFree(d_B);
    hipFree(d1_C);
	hipFree(d2_C);
    hipDeviceReset();
}

 
	.text
	.file	"lab4.hip"
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z7MatInitPfi
.LCPI0_0:
	.long	0x30000000                      # float 4.65661287E-10
	.text
	.globl	_Z7MatInitPfi
	.type	_Z7MatInitPfi,@function
_Z7MatInitPfi:                          # @_Z7MatInitPfi
	.cfi_startproc
# %bb.0:
	testl	%esi, %esi
	jle	.LBB0_4
# %bb.1:                                # %.lr.ph.preheader
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %rbx
	movl	%esi, %r14d
	xorl	%r15d, %r15d
.LBB0_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	.LCPI0_0(%rip), %xmm0
	movss	%xmm0, (%rbx,%r15,4)
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB0_2
# %bb.3:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r14
	.cfi_restore %r15
.LBB0_4:                                # %._crit_edge
	retq
.Lfunc_end0:
	.size	_Z7MatInitPfi, .Lfunc_end0-_Z7MatInitPfi
	.cfi_endproc
                                        # -- End function
	.globl	_Z6CpuMulPfPKfS1_iii            # -- Begin function _Z6CpuMulPfPKfS1_iii
	.type	_Z6CpuMulPfPKfS1_iii,@function
_Z6CpuMulPfPKfS1_iii:                   # @_Z6CpuMulPfPKfS1_iii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdx, -8(%rsp)                  # 8-byte Spill
	movq	%rsi, -16(%rsp)                 # 8-byte Spill
	movq	%rdi, -24(%rsp)                 # 8-byte Spill
	testl	%ecx, %ecx
	jle	.LBB1_9
# %bb.1:                                # %.preheader29.lr.ph
	movslq	%r9d, %rdi
	movl	%ecx, %ecx
	movl	%edi, %r10d
	movl	%r8d, %r11d
	leaq	(,%rdi,4), %rbx
	xorl	%r14d, %r14d
	xorl	%r15d, %r15d
.LBB1_2:                                # %.preheader29
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_4 Depth 2
                                        #       Child Loop BB1_6 Depth 3
	testl	%r9d, %r9d
	jle	.LBB1_8
# %bb.3:                                # %.preheader.lr.ph
                                        #   in Loop: Header=BB1_2 Depth=1
	movl	%r14d, %eax
	movq	-16(%rsp), %rdx                 # 8-byte Reload
	leaq	(%rdx,%rax,4), %r12
	movq	%r15, %rax
	imulq	%rdi, %rax
	movq	-24(%rsp), %rdx                 # 8-byte Reload
	leaq	(%rdx,%rax,4), %r13
	movq	-8(%rsp), %rdx                  # 8-byte Reload
	xorl	%eax, %eax
.LBB1_4:                                # %.preheader
                                        #   Parent Loop BB1_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB1_6 Depth 3
	xorpd	%xmm0, %xmm0
	testl	%r8d, %r8d
	jle	.LBB1_7
# %bb.5:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB1_4 Depth=2
	movq	%rdx, %rbp
	xorl	%esi, %esi
.LBB1_6:                                # %.lr.ph
                                        #   Parent Loop BB1_2 Depth=1
                                        #     Parent Loop BB1_4 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	xorps	%xmm1, %xmm1
	cvtss2sd	(%r12,%rsi,4), %xmm1
	xorps	%xmm2, %xmm2
	cvtss2sd	(%rbp), %xmm2
	mulsd	%xmm1, %xmm2
	addsd	%xmm2, %xmm0
	incq	%rsi
	addq	%rbx, %rbp
	cmpq	%rsi, %r11
	jne	.LBB1_6
.LBB1_7:                                # %._crit_edge
                                        #   in Loop: Header=BB1_4 Depth=2
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%r13,%rax,4)
	incq	%rax
	addq	$4, %rdx
	cmpq	%r10, %rax
	jne	.LBB1_4
.LBB1_8:                                # %._crit_edge33
                                        #   in Loop: Header=BB1_2 Depth=1
	incq	%r15
	addl	%r8d, %r14d
	cmpq	%rcx, %r15
	jne	.LBB1_2
.LBB1_9:                                # %._crit_edge35
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z6CpuMulPfPKfS1_iii, .Lfunc_end1-_Z6CpuMulPfPKfS1_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__GpuMul1PfS_S_ii # -- Begin function _Z22__device_stub__GpuMul1PfS_S_ii
	.type	_Z22__device_stub__GpuMul1PfS_S_ii,@function
_Z22__device_stub__GpuMul1PfS_S_ii:     # @_Z22__device_stub__GpuMul1PfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7GpuMul1PfS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z22__device_stub__GpuMul1PfS_S_ii, .Lfunc_end2-_Z22__device_stub__GpuMul1PfS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__GpuMul2PfS_S_ii # -- Begin function _Z22__device_stub__GpuMul2PfS_S_ii
	.type	_Z22__device_stub__GpuMul2PfS_S_ii,@function
_Z22__device_stub__GpuMul2PfS_S_ii:     # @_Z22__device_stub__GpuMul2PfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7GpuMul2PfS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z22__device_stub__GpuMul2PfS_S_ii, .Lfunc_end3-_Z22__device_stub__GpuMul2PfS_S_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI4_0:
	.long	0x30000000                      # float 4.65661287E-10
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI4_1:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$409600, %edi                   # imm = 0x64000
	callq	malloc
	movq	%rax, %rbx
	movl	$819200, %edi                   # imm = 0xC8000
	callq	malloc
	movq	%rax, %r14
	xorl	%r15d, %r15d
.LBB4_1:                                # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	movss	.LCPI4_0(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	%xmm1, %xmm0
	movss	%xmm0, (%rbx,%r15,4)
	incq	%r15
	cmpq	$102400, %r15                   # imm = 0x19000
	jne	.LBB4_1
# %bb.2:                                # %.lr.ph.i53.preheader
	xorl	%r15d, %r15d
.LBB4_3:                                # %.lr.ph.i53
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	.LCPI4_0(%rip), %xmm0
	movss	%xmm0, (%r14,%r15,4)
	incq	%r15
	cmpq	$204800, %r15                   # imm = 0x32000
	jne	.LBB4_3
# %bb.4:                                # %_Z7MatInitPfi.exit57
	leaq	40(%rsp), %r15
	movl	$409600, %esi                   # imm = 0x64000
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	32(%rsp), %r12
	movl	$819200, %esi                   # imm = 0xC8000
	movq	%r12, %rdi
	callq	hipMalloc
	movq	(%r15), %rdi
	movl	$409600, %edx                   # imm = 0x64000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movl	$819200, %edx                   # imm = 0xC8000
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	24(%rsp), %rdi
	movl	$819200, %esi                   # imm = 0xC8000
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$819200, %esi                   # imm = 0xC8000
	callq	hipMalloc
	movl	$819200, %edi                   # imm = 0xC8000
	callq	malloc
	movq	%rax, %r15
	movl	$819200, %edi                   # imm = 0xC8000
	callq	malloc
	movq	%rax, %r13
	callq	clock
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movabsq	$4294967496, %rdi               # imm = 0x1000000C8
	leaq	824(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_6
# %bb.5:
	movq	24(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdx
	movl	$320, %ecx                      # imm = 0x140
	movl	$640, %r8d                      # imm = 0x280
	callq	_Z22__device_stub__GpuMul1PfS_S_ii
.LBB4_6:
	callq	hipDeviceSynchronize
	callq	clock
	movq	%rax, %rbp
	movq	24(%rsp), %rsi
	movl	$819200, %edx                   # imm = 0xC8000
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	callq	clock
	movq	%rax, (%rsp)                    # 8-byte Spill
	movabsq	$42949672980, %rdi              # imm = 0xA00000014
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	%r15, 48(%rsp)                  # 8-byte Spill
	jne	.LBB4_8
# %bb.7:
	movq	16(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdx
	movl	$320, %ecx                      # imm = 0x140
	movl	$640, %r8d                      # imm = 0x280
	callq	_Z22__device_stub__GpuMul2PfS_S_ii
.LBB4_8:                                # %_Z6CpuMulPfPKfS1_iii.exit
	callq	hipDeviceSynchronize
	callq	clock
	movq	%rax, %r15
	movq	16(%rsp), %rsi
	movl	$819200, %edx                   # imm = 0xC8000
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	callq	clock
	movq	%rax, %r12
	subq	(%rsp), %r15                    # 8-byte Folded Reload
	cvtsi2sd	%r15, %xmm0
	movsd	.LCPI4_1(%rip), %xmm1           # xmm1 = mem[0],zero
	divsd	%xmm1, %xmm0
	movsd	%xmm0, (%rsp)                   # 8-byte Spill
	subq	8(%rsp), %rbp                   # 8-byte Folded Reload
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rbp, %xmm0
	divsd	%xmm1, %xmm0
	movsd	%xmm0, 8(%rsp)                  # 8-byte Spill
	callq	clock
	subq	%r12, %rax
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI4_1(%rip), %xmm0
	movl	$.L.str, %edi
	movsd	8(%rsp), %xmm1                  # 8-byte Reload
                                        # xmm1 = mem[0],zero
	movsd	(%rsp), %xmm2                   # 8-byte Reload
                                        # xmm2 = mem[0],zero
	movb	$3, %al
	callq	printf
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	48(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	%r13, %rdi
	callq	free
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	callq	hipDeviceReset
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7GpuMul1PfS_S_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7GpuMul2PfS_S_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7GpuMul1PfS_S_ii,@object      # @_Z7GpuMul1PfS_S_ii
	.section	.rodata,"a",@progbits
	.globl	_Z7GpuMul1PfS_S_ii
	.p2align	3, 0x0
_Z7GpuMul1PfS_S_ii:
	.quad	_Z22__device_stub__GpuMul1PfS_S_ii
	.size	_Z7GpuMul1PfS_S_ii, 8

	.type	_Z7GpuMul2PfS_S_ii,@object      # @_Z7GpuMul2PfS_S_ii
	.globl	_Z7GpuMul2PfS_S_ii
	.p2align	3, 0x0
_Z7GpuMul2PfS_S_ii:
	.quad	_Z22__device_stub__GpuMul2PfS_S_ii
	.size	_Z7GpuMul2PfS_S_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%f  %f  %f"
	.size	.L.str, 11

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7GpuMul1PfS_S_ii"
	.size	.L__unnamed_1, 19

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z7GpuMul2PfS_S_ii"
	.size	.L__unnamed_2, 19

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__GpuMul1PfS_S_ii
	.addrsig_sym _Z22__device_stub__GpuMul2PfS_S_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7GpuMul1PfS_S_ii
	.addrsig_sym _Z7GpuMul2PfS_S_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7GpuMul1PfS_S_ii      ; -- Begin function _Z7GpuMul1PfS_S_ii
	.globl	_Z7GpuMul1PfS_S_ii
	.p2align	8
	.type	_Z7GpuMul1PfS_S_ii,@function
_Z7GpuMul1PfS_S_ii:                     ; @_Z7GpuMul1PfS_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x2c
	s_load_b256 s[0:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s8, 0xffff
	s_cmp_lt_i32 s6, 1
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	s_cbranch_scc1 .LBB0_3
; %bb.1:                                ; %.lr.ph
	s_ashr_i32 s8, s7, 31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v4, v1, v2
	s_add_i32 s9, s7, s8
	s_xor_b32 s9, s9, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v4, v4, v2
	v_cvt_f32_u32_e32 v0, s9
	s_sub_i32 s10, 0, s9
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v3, s10, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v0, v3
	v_add_nc_u32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v4, v0
	v_mul_lo_u32 v3, v0, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v0
	v_subrev_nc_u32_e32 v5, s9, v3
	v_cmp_le_u32_e32 vcc_lo, s9, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
	v_xor_b32_e32 v5, s8, v2
	v_cmp_le_u32_e32 vcc_lo, s9, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, 1, v0
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v5
	v_sub_nc_u32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v0, s6
	v_mul_lo_u32 v0, v0, s7
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[5:6], 2, v[3:4]
	v_sub_nc_u32_e32 v3, v1, v0
	v_mov_b32_e32 v0, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s2, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v4, 31, v3
	s_add_i32 s6, s6, -1
	s_cmp_eq_u32 s6, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[7:8], 2, v[3:4]
	v_add_nc_u32_e32 v3, s7, v3
	v_add_co_u32 v7, vcc_lo, s4, v7
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	global_load_b32 v4, v[5:6], off
	global_load_b32 v7, v[7:8], off
	v_add_co_u32 v5, vcc_lo, v5, 4
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v0, v4, v7
	s_cbranch_scc0 .LBB0_2
	s_branch .LBB0_4
.LBB0_3:
	v_mov_b32_e32 v0, 0
.LBB0_4:                                ; %Flow47
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7GpuMul1PfS_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7GpuMul1PfS_S_ii, .Lfunc_end0-_Z7GpuMul1PfS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 428
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7GpuMul2PfS_S_ii      ; -- Begin function _Z7GpuMul2PfS_S_ii
	.globl	_Z7GpuMul2PfS_S_ii
	.p2align	8
	.type	_Z7GpuMul2PfS_S_ii,@function
_Z7GpuMul2PfS_S_ii:                     ; @_Z7GpuMul2PfS_S_ii
; %bb.0:
	s_load_b256 s[0:7], s[0:1], 0x0
	v_bfe_u32 v6, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v6, s7
	s_cmp_gt_i32 s6, 31
	v_ashrrev_i32_e32 v3, 31, v2
	s_cbranch_scc1 .LBB1_2
; %bb.1:                                ; %.._crit_edge_crit_edge
	v_mov_b32_e32 v1, 0
	s_lshl_b32 s8, s14, 5
	s_mov_b32 s11, 0
	s_ashr_i32 s9, s8, 31
	s_branch .LBB1_3
.LBB1_2:
	s_mov_b32 s11, -1
                                        ; implicit-def: $sgpr8_sgpr9
.LBB1_3:                                ; %Flow83
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_lshl_b32 s10, s15, 5
	s_cbranch_vccnz .LBB1_8
; %bb.4:                                ; %.lr.ph
	v_mul_lo_u32 v4, v6, s6
	v_mov_b32_e32 v5, 0
	s_ashr_i32 s9, s6, 31
	s_mul_i32 s8, s10, s6
	s_lshr_b32 s11, s9, 27
	s_ashr_i32 s9, s8, 31
	s_add_i32 s11, s6, s11
	s_lshl_b64 s[8:9], s[8:9], 2
	v_lshlrev_b64 v[7:8], 2, v[4:5]
	v_lshlrev_b32_e32 v4, 7, v6
	s_ashr_i32 s6, s11, 5
	s_add_u32 s11, s2, s8
	s_addc_u32 s12, s3, s9
	s_lshl_b32 s8, s14, 5
	v_add_co_u32 v7, vcc_lo, s11, v7
	v_lshlrev_b32_e32 v11, 2, v0
	s_ashr_i32 s9, s8, 31
	v_add_co_ci_u32_e32 v8, vcc_lo, s12, v8, vcc_lo
	v_lshlrev_b64 v[9:10], 2, v[2:3]
	s_lshl_b64 s[2:3], s[8:9], 2
	v_add_co_u32 v6, vcc_lo, v7, v11
	s_add_u32 s2, s4, s2
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
	s_addc_u32 s3, s5, s3
	v_add_co_u32 v12, vcc_lo, s2, v9
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v10, vcc_lo
	v_or_b32_e32 v9, 0x1000, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v10, vcc_lo, v12, v11
	v_dual_mov_b32 v1, v5 :: v_dual_add_nc_u32 v8, v4, v11
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v12, v9, v4
	s_mov_b32 s3, 0
	s_mov_b32 s4, 0
.LBB1_5:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_6 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s2, s4, 5
	s_mul_i32 s12, s2, s7
	s_lshl_b64 s[14:15], s[2:3], 2
	s_ashr_i32 s13, s12, 31
	v_add_co_u32 v13, vcc_lo, v6, s14
	s_lshl_b64 s[12:13], s[12:13], 2
	v_add_co_ci_u32_e32 v14, vcc_lo, s15, v7, vcc_lo
	v_add_co_u32 v15, vcc_lo, v10, s12
	v_add_co_ci_u32_e32 v16, vcc_lo, s13, v11, vcc_lo
	global_load_b32 v14, v[13:14], off
	global_load_b32 v15, v[15:16], off
	v_mov_b32_e32 v13, v9
	s_mov_b32 s2, 0
	s_waitcnt vmcnt(1)
	ds_store_b32 v8, v14
	s_waitcnt vmcnt(0)
	ds_store_b32 v12, v15
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB1_6:                                ;   Parent Loop BB1_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v14, s2, v4
	s_add_i32 s2, s2, 4
	ds_load_b32 v15, v13
	ds_load_b32 v14, v14
	v_add_nc_u32_e32 v13, 0x80, v13
	s_cmpk_eq_i32 s2, 0x80
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v5, v14, v15
	s_cbranch_scc0 .LBB1_6
; %bb.7:                                ;   in Loop: Header=BB1_5 Depth=1
	s_add_i32 s4, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s4, s6
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB1_5
	s_branch .LBB1_9
.LBB1_8:
	v_mov_b32_e32 v5, s11
.LBB1_9:                                ; %Flow84
	s_mul_i32 s2, s10, s7
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_ashr_i32 s3, s2, 31
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_lshl_b64 s[2:3], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_u32 s2, s0, s2
	s_addc_u32 s3, s1, s3
	s_lshl_b64 s[0:1], s[8:9], 2
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
	global_store_b32 v[0:1], v5, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7GpuMul2PfS_S_ii
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z7GpuMul2PfS_S_ii, .Lfunc_end1-_Z7GpuMul2PfS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 564
; NumSgprs: 18
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7GpuMul1PfS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7GpuMul1PfS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 8192
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7GpuMul2PfS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7GpuMul2PfS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     17
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
