#include<time.h>
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<cuda.h>

/* Macro for mapping three dimensional index (ix,iy,iz) to 
 * linear index. The vertical index (z) is running fastest so 
 * that vertical columns are always kept together in memory.
 */
#define LINIDX(n, ix,iy,iz) ((n.z)*(n.y)*(ix) + (n.z)*(iy) + (iz))
#define GLINIDX(n, ix,iy,iz) ((n->z)*(n->y)*(ix) + (n->z)*(iy) + (iz))
#define len n.x*n.y*n.z

#define BLOCK_SIZE 5

/* Structure for three dimensional grid size */
struct N {
  int x;   // Number of grid points in x-direction
  int y;   // Number of grid points in y-direction
  int z;   // Number of grid points in z-direction
};

/* Number of gridpoints */
struct N n;

/* Relative residual reduction target */
//const float resreduction = 1.0e-5;


/* parameters of PDE */
const float lambda2 = 1e4;
const float omega2 = 1.0;
const float delta = 0.0;


/* *********************************************************** *

* Block-Jacobi Preconditioner

* y = M^{-1}.b

* *********************************************************** */

void prec_BJ(const struct N n,
	      const float* b,
	      float* y) {
  int ix, iy, iz;
  // Grid spacings in all dirctions
  float hx = 1./n.x;
  float hy = 1./n.y;
  float hz = 1./n.z;
  float hx_inv2 = 1./(hx*hx);
  float hy_inv2 = 1./(hy*hy);
  float hz_inv2 = 1./(hz*hz);
   float *c,*d;
  // Temporary arrays for Thomas algorithm
   cudaMallocHost((void**)&c,n.z*sizeof(float));
   cudaMallocHost((void**)&d,n.z*sizeof(float));
   // float c[100],d[100];
   //float* c=malloc(n.z*sizeof(float));
   //float* d=malloc(n.z*sizeof(float));
   // Loop over number of relaxation steps
  for (ix = 0; ix<n.x; ix++) {
    for (iy = 0; iy<n.y; iy++) {
      // Do a tridiagonal solve in the vertical direction
      // STEP 1: Calculate modified coefficients
      c[0] = (-omega2*lambda2*hz_inv2)
	/ (delta+2.*omega2*(hx_inv2+hy_inv2+lambda2*hz_inv2));
      d[0] = b[LINIDX(n, ix,iy,0)]
	/ (delta+2.*omega2*(hx_inv2+hy_inv2+lambda2*hz_inv2));
      for (iz = 1; iz<n.z; iz++) {
        c[iz] = (-omega2*lambda2*hz_inv2) 
	  / ( (delta+2.*omega2*(hx_inv2+hy_inv2+lambda2*hz_inv2)) 
	      - (-omega2*lambda2*hz_inv2) * c[iz-1]);
        d[iz] = (b[LINIDX(n, ix,iy,iz)] 
                 - (-omega2*lambda2*hz_inv2)*d[iz-1])
	  / ( (delta+2.*omega2*(hx_inv2+hy_inv2+lambda2*hz_inv2))
	      - (-omega2*lambda2*hz_inv2)*c[iz-1]);
      }
      // STEP 2: Back-substitution.
      y[LINIDX(n, ix,iy,n.z-1)] = d[n.z-1];
      for (iz = n.z-2; iz>=0; iz--) {
        y[LINIDX(n, ix,iy,iz)] 
          = d[iz] - c[iz]*y[LINIDX(n, ix,iy,iz+1)];
      }
    }
  }
  cudaFree(c);
  cudaFree(d);
}





__global__ void gpu_bj(const struct N *n,
	      const float* b,
	      float* y) {
  int ix, iy, iz;
  // Grid spacings in all dirctions
  float hx = 1./n->x;
  float hy = 1./n->y;
  float hz = 1./n->z;
  float hx_inv2 = 1./(hx*hx);
  float hy_inv2 = 1./(hy*hy);
  float hz_inv2 = 1./(hz*hz);
  
  //float *c,*d;
  // Temporary arrays for Thomas algorithm
  //cudaMalloc((void**)&c,n->z*sizeof(float));
  //cudaMalloc((void**)&d,n->z*sizeof(float));
  float c[1000],d[1000];
  //float* c=malloc(n.z*sizeof(float));
  //float* d=malloc(n.z*sizeof(float));
  // Loop over number of relaxation steps
  ix=blockIdx.x*BLOCK_SIZE+threadIdx.x;
  iy=blockIdx.y*BLOCK_SIZE+threadIdx.y;
  // for (ix = 0; ix<n->x; ix++) {
  // for (iy = 0; iy<n->y; iy++) {
      // Do a tridiagonal solve in the vertical direction
      // STEP 1: Calculate modified coefficients
      c[0] = (-omega2*lambda2*hz_inv2)/(delta+2.*omega2*(hx_inv2+hy_inv2+lambda2*hz_inv2));
      d[0] = b[GLINIDX(n, ix,iy,0)]/(delta+2.*omega2*(hx_inv2+hy_inv2+lambda2*hz_inv2));
      for (iz = 1; iz<n->z; iz++) {
        c[iz] = (-omega2*lambda2*hz_inv2)/( (delta+2.*omega2*(hx_inv2+hy_inv2+lambda2*hz_inv2))- (-omega2*lambda2*hz_inv2) * c[iz-1]);
        d[iz] = (b[GLINIDX(n, ix,iy,iz)]-(-omega2*lambda2*hz_inv2)*d[iz-1])/((delta+2.*omega2*(hx_inv2+hy_inv2+lambda2*hz_inv2))- (-omega2*lambda2*hz_inv2)*c[iz-1]);
      }
      // STEP 2: Back-substitution.
      y[GLINIDX(n, ix,iy,n->z-1)] = d[n->z-1];
      for (iz = n->z-2; iz>=0; iz--) {
        y[GLINIDX(n, ix,iy,iz)]=d[iz] - c[iz]*y[GLINIDX(n, ix,iy,iz+1)];
      }
      // }
      // }
}




int main(){
  n.x = 20;
  n.y = 100;
  n.z = 20;
  int i;  
  
  printf(" parameters\n");
  printf(" ==========\n");
  printf(" nx        = %10d\n",n.x);
  printf(" ny        = %10d\n",n.y);
  printf(" nz        = %10d\n",n.z);
  printf(" omega2    = %12.6e\n",omega2);
  printf(" lambda2   = %12.6e\n",lambda2);
  printf(" delta     = %12.6e\n",delta);
  
  float x[len],y[len],gpu_y[len];
  for(i=0;i<len;i++){
    x[i]=1.2;
  }
  double start1=clock();
  for(i=0;i<1000;i++)
  prec_BJ(n,x,y);
  double end1=clock();


  N *h_n,*dev_n;
  h_n=(struct N*)malloc(sizeof(N));

  h_n->x=n.x;
  h_n->y=n.y;
  h_n->z=n.z;
  
  float *dev_b, *dev_y;


  cudaMalloc((void**)&dev_n,sizeof(N));
  cudaMalloc((void**)&dev_b,len*sizeof(float));
  cudaMalloc((void**)&dev_y,len*sizeof(float));


  cudaMemcpy(dev_n,h_n,sizeof(N),cudaMemcpyHostToDevice);
  cudaMemcpy(dev_b,x,len*sizeof(float),cudaMemcpyHostToDevice);
  dim3 dimBlock(BLOCK_SIZE,BLOCK_SIZE);
  dim3 dimGrid(n.x/BLOCK_SIZE,n.y/BLOCK_SIZE);
  gpu_bj<<<dimGrid,dimBlock>>>(dev_n,dev_b,dev_y);
  cudaMemcpy(gpu_y,dev_y,len*sizeof(float),cudaMemcpyDeviceToHost);
  


  
  /*for(i=0;i<len;i++){
    if(y[i]-gpu_y[i]>0.00001)
      printf("%f--%f\n",y[i],gpu_y[i]);
    else
      printf(".");
      }*/

  cudaFree(dev_n);
  cudaFree(dev_b);
  cudaFree(dev_y);
  
  printf("cpu time = %f\n",(double)(end1-start1)/CLOCKS_PER_SEC*1000000);

  return(0);
}



	.file	"tmpxft_003414ba_00000000-6_bj.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z7prec_BJ1NPKfPf
	.type	_Z7prec_BJ1NPKfPf, @function
_Z7prec_BJ1NPKfPf:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	cvtsi2sdl	%edi, %xmm1
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%edi, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movslq	%esi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	leaq	0(,%r13,4), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rbp, %rsi
	movq	%r13, %rbx
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movsd	.LC0(%rip), %xmm0
	movq	%rdi, 32(%rsp)
	movl	36(%rsp), %r12d
	leaq	56(%rsp), %rdi
	movaps	%xmm0, %xmm2
	movq	%rdx, 8(%rsp)
	cvtsi2sdl	%r12d, %xmm3
	divsd	%xmm1, %xmm2
	movaps	%xmm0, %xmm1
	movq	%rcx, 16(%rsp)
	movl	%r13d, 40(%rsp)
	movl	%r12d, %r15d
	imull	%r13d, %r15d
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	divsd	%xmm3, %xmm1
	cvtsi2sdl	%r13d, %xmm3
	cvtsd2ss	%xmm2, %xmm2
	mulss	%xmm2, %xmm2
	divsd	%xmm3, %xmm0
	movss	.LC1(%rip), %xmm3
	movaps	%xmm3, %xmm5
	movaps	%xmm3, %xmm6
	cvtsd2ss	%xmm1, %xmm1
	mulss	%xmm1, %xmm1
	divss	%xmm2, %xmm5
	cvtsd2ss	%xmm0, %xmm0
	mulss	%xmm0, %xmm0
	divss	%xmm1, %xmm6
	movss	%xmm5, (%rsp)
	divss	%xmm0, %xmm3
	movss	%xmm6, 4(%rsp)
	movss	%xmm3, 24(%rsp)
	call	cudaMallocHost@PLT
	leaq	64(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMallocHost@PLT
	leal	-2(%r13), %eax
	xorl	%r9d, %r9d
	xorl	%r10d, %r10d
	movq	64(%rsp), %rsi
	movl	%eax, 28(%rsp)
	movss	.LC3(%rip), %xmm6
	xorps	%xmm7, %xmm7
	movq	56(%rsp), %rdi
	movss	.LC2(%rip), %xmm5
	leaq	-4(%rsi,%rbp), %r11
.L3:
	cmpl	%r14d, %r10d
	jge	.L9
	movq	16(%rsp), %rcx
	movq	8(%rsp), %rdx
	movslq	%r9d, %rax
	xorl	%r8d, %r8d
	salq	$2, %rax
	addq	%rax, %rcx
	addq	%rdx, %rax
.L10:
	cmpl	%r12d, %r8d
	jge	.L14
	movss	24(%rsp), %xmm1
	movss	(%rsp), %xmm0
	xorl	%edx, %edx
	addss	4(%rsp), %xmm0
	mulss	%xmm5, %xmm1
	subss	%xmm1, %xmm0
	movaps	%xmm1, %xmm4
	cvtss2sd	%xmm1, %xmm3
	movaps	%xmm3, %xmm1
	xorps	%xmm6, %xmm4
	cvtss2sd	%xmm0, %xmm0
	addsd	%xmm0, %xmm0
	addsd	%xmm7, %xmm0
	divsd	%xmm0, %xmm1
	cvtsd2ss	%xmm1, %xmm1
	movss	%xmm1, (%rdi)
	cvtss2sd	(%rax), %xmm1
	divsd	%xmm0, %xmm1
	cvtsd2ss	%xmm1, %xmm1
	movss	%xmm1, (%rsi)
.L4:
	incq	%rdx
	cmpl	%edx, %ebx
	jle	.L15
	movss	-4(%rdi,%rdx,4), %xmm2
	movaps	%xmm3, %xmm1
	mulss	%xmm4, %xmm2
	cvtss2sd	%xmm2, %xmm2
	addsd	%xmm0, %xmm2
	divsd	%xmm2, %xmm1
	cvtsd2ss	%xmm1, %xmm1
	movss	%xmm1, (%rdi,%rdx,4)
	movss	-4(%rsi,%rdx,4), %xmm1
	mulss	%xmm4, %xmm1
	addss	(%rax,%rdx,4), %xmm1
	cvtss2sd	%xmm1, %xmm1
	divsd	%xmm2, %xmm1
	cvtsd2ss	%xmm1, %xmm1
	movss	%xmm1, (%rsi,%rdx,4)
	jmp	.L4
.L15:
	movss	(%r11), %xmm0
	movslq	28(%rsp), %rdx
	movss	%xmm0, -4(%rcx,%r13,4)
.L6:
	testl	%edx, %edx
	js	.L16
	movss	(%rdi,%rdx,4), %xmm1
	mulss	4(%rcx,%rdx,4), %xmm1
	movss	(%rsi,%rdx,4), %xmm0
	subss	%xmm1, %xmm0
	movss	%xmm0, (%rcx,%rdx,4)
	decq	%rdx
	jmp	.L6
.L16:
	incl	%r8d
	addq	%rbp, %rcx
	addq	%rbp, %rax
	jmp	.L10
.L14:
	incl	%r10d
	addl	%r15d, %r9d
	jmp	.L3
.L9:
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z7prec_BJ1NPKfPf, .-_Z7prec_BJ1NPKfPf
	.globl	_Z32__device_stub__Z6gpu_bjPK1NPKfPfPK1NPKfPf
	.type	_Z32__device_stub__Z6gpu_bjPK1NPKfPfPK1NPKfPf, @function
_Z32__device_stub__Z6gpu_bjPK1NPKfPfPK1NPKfPf:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z6gpu_bjPK1NPKfPf(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L17:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z32__device_stub__Z6gpu_bjPK1NPKfPfPK1NPKfPf, .-_Z32__device_stub__Z6gpu_bjPK1NPKfPfPK1NPKfPf
	.globl	_Z6gpu_bjPK1NPKfPf
	.type	_Z6gpu_bjPK1NPKfPf, @function
_Z6gpu_bjPK1NPKfPf:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z6gpu_bjPK1NPKfPfPK1NPKfPf
	.cfi_endproc
.LFE2054:
	.size	_Z6gpu_bjPK1NPKfPf, .-_Z6gpu_bjPK1NPKfPf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC5:
	.string	" parameters\n"
.LC6:
	.string	" ==========\n"
.LC7:
	.string	" nx        = %10d\n"
.LC8:
	.string	" ny        = %10d\n"
.LC9:
	.string	" nz        = %10d\n"
.LC10:
	.string	" omega2    = %12.6e\n"
.LC12:
	.string	" lambda2   = %12.6e\n"
.LC13:
	.string	" delta     = %12.6e\n"
.LC16:
	.string	"cpu time = %f\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	movq	%rsp, %rbp
	.cfi_def_cfa_register 6
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$80, %rsp
	.cfi_offset 14, -24
	.cfi_offset 13, -32
	.cfi_offset 12, -40
	.cfi_offset 3, -48
	movq	%fs:40, %rax
	movq	%rax, -40(%rbp)
	movabsq	$429496729620, %rax
	movl	$20, 8+n(%rip)
	movq	%rax, n(%rip)
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	n(%rip), %edx
	leaq	.LC7(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	4+n(%rip), %edx
	leaq	.LC8(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	8+n(%rip), %edx
	leaq	.LC9(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	movsd	.LC0(%rip), %xmm0
	leaq	.LC10(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	call	__printf_chk@PLT
	movsd	.LC11(%rip), %xmm0
	leaq	.LC12(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	$2, %edi
	xorps	%xmm0, %xmm0
	movb	$1, %al
	leaq	.LC13(%rip), %rsi
	call	__printf_chk@PLT
	movl	n(%rip), %edx
	movq	%rsp, %rsi
	imull	4+n(%rip), %edx
	imull	8+n(%rip), %edx
	movslq	%edx, %rax
	leaq	15(,%rax,4), %rax
	movq	%rax, %rdi
	movq	%rax, %rcx
	andq	$-4096, %rdi
	andq	$-16, %rcx
	subq	%rdi, %rsi
.L23:
	cmpq	%rsi, %rsp
	je	.L24
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L23
.L24:
	andl	$4095, %ecx
	subq	%rcx, %rsp
	testq	%rcx, %rcx
	je	.L25
	orq	$0, -8(%rsp,%rcx)
.L25:
	movq	%rax, %rdi
	movq	%rax, %rcx
	movq	%rsp, %rsi
	movq	%rsp, %rbx
	andq	$-4096, %rdi
	andq	$-16, %rcx
	subq	%rdi, %rsi
.L26:
	cmpq	%rsi, %rsp
	je	.L27
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L26
.L27:
	andl	$4095, %ecx
	subq	%rcx, %rsp
	testq	%rcx, %rcx
	je	.L28
	orq	$0, -8(%rsp,%rcx)
.L28:
	movq	%rax, %rcx
	movq	%rsp, %rsi
	andq	$-4096, %rax
	movq	%rsp, %r12
	andq	$-16, %rcx
	subq	%rax, %rsi
.L29:
	cmpq	%rsi, %rsp
	je	.L30
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L29
.L30:
	movq	%rcx, %rax
	andl	$4095, %eax
	subq	%rax, %rsp
	testq	%rax, %rax
	je	.L31
	orq	$0, -8(%rsp,%rax)
.L31:
	movss	.LC14(%rip), %xmm0
	movq	%rsp, %r14
	xorl	%eax, %eax
.L32:
	cmpl	%eax, %edx
	jle	.L48
	movss	%xmm0, (%rbx,%rax,4)
	incq	%rax
	jmp	.L32
.L48:
	call	clock@PLT
	movl	$1000, %r13d
	cvtsi2sdq	%rax, %xmm2
	movsd	%xmm2, -104(%rbp)
.L34:
	movq	n(%rip), %rdi
	movl	8+n(%rip), %esi
	movq	%r12, %rcx
	movq	%rbx, %rdx
	call	_Z7prec_BJ1NPKfPf
	decl	%r13d
	jne	.L34
	call	clock@PLT
	movl	$12, %edi
	cvtsi2sdq	%rax, %xmm3
	movq	%xmm3, %r13
	call	malloc@PLT
	leaq	-88(%rbp), %rdi
	movl	$12, %esi
	movq	%rax, %r12
	movq	n(%rip), %rax
	movq	%rax, (%r12)
	movl	8+n(%rip), %eax
	movl	%eax, 8(%r12)
	call	cudaMalloc@PLT
	movl	n(%rip), %esi
	leaq	-80(%rbp), %rdi
	imull	4+n(%rip), %esi
	imull	8+n(%rip), %esi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	n(%rip), %esi
	leaq	-72(%rbp), %rdi
	imull	4+n(%rip), %esi
	imull	8+n(%rip), %esi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movq	-88(%rbp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$12, %edx
	call	cudaMemcpy@PLT
	movl	n(%rip), %edx
	movq	-80(%rbp), %rdi
	movq	%rbx, %rsi
	imull	4+n(%rip), %edx
	movl	$1, %ecx
	imull	8+n(%rip), %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	$5, %esi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	4+n(%rip), %eax
	cltd
	idivl	%esi
	movl	%eax, %ecx
	movl	n(%rip), %eax
	movl	%ecx, -48(%rbp)
	movl	$1, %ecx
	cltd
	idivl	%esi
	movabsq	$21474836485, %rdx
	movl	$1, %esi
	movl	%eax, -52(%rbp)
	movq	-52(%rbp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	movq	-72(%rbp), %rdx
	movq	-80(%rbp), %rsi
	movq	-88(%rbp), %rdi
	call	_Z32__device_stub__Z6gpu_bjPK1NPKfPfPK1NPKfPf
.L35:
	movl	n(%rip), %edx
	movq	-72(%rbp), %rsi
	movl	$2, %ecx
	movq	%r14, %rdi
	imull	4+n(%rip), %edx
	imull	8+n(%rip), %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movq	-88(%rbp), %rdi
	call	cudaFree@PLT
	movq	-80(%rbp), %rdi
	call	cudaFree@PLT
	movq	-72(%rbp), %rdi
	call	cudaFree@PLT
	movq	%r13, %xmm0
	subsd	-104(%rbp), %xmm0
	movb	$1, %al
	movsd	.LC15(%rip), %xmm1
	leaq	.LC16(%rip), %rsi
	movl	$2, %edi
	divsd	%xmm1, %xmm0
	mulsd	%xmm1, %xmm0
	call	__printf_chk@PLT
	movq	-40(%rbp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	leaq	-32(%rbp), %rsp
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC17:
	.string	"_Z6gpu_bjPK1NPKfPf"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC17(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6gpu_bjPK1NPKfPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	n
	.bss
	.align 8
	.type	n, @object
	.size	n, 12
n:
	.zero	12
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	0
	.long	1072693248
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1065353216
	.align 4
.LC2:
	.long	-971227136
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC3:
	.long	-2147483648
	.long	0
	.long	0
	.long	0
	.section	.rodata.cst8
	.align 8
.LC11:
	.long	0
	.long	1086556160
	.section	.rodata.cst4
	.align 4
.LC14:
	.long	1067030938
	.section	.rodata.cst8
	.align 8
.LC15:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include<time.h>
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<hip/hip_runtime.h>

/* Macro for mapping three dimensional index (ix,iy,iz) to 
 * linear index. The vertical index (z) is running fastest so 
 * that vertical columns are always kept together in memory.
 */
#define LINIDX(n, ix,iy,iz) ((n.z)*(n.y)*(ix) + (n.z)*(iy) + (iz))
#define GLINIDX(n, ix,iy,iz) ((n->z)*(n->y)*(ix) + (n->z)*(iy) + (iz))
#define len n.x*n.y*n.z

#define BLOCK_SIZE 5

/* Structure for three dimensional grid size */
struct N {
  int x;   // Number of grid points in x-direction
  int y;   // Number of grid points in y-direction
  int z;   // Number of grid points in z-direction
};

/* Number of gridpoints */
struct N n;

/* Relative residual reduction target */
//const float resreduction = 1.0e-5;


/* parameters of PDE */
const float lambda2 = 1e4;
const float omega2 = 1.0;
const float delta = 0.0;


/* *********************************************************** *

* Block-Jacobi Preconditioner

* y = M^{-1}.b

* *********************************************************** */

void prec_BJ(const struct N n,
	      const float* b,
	      float* y) {
  int ix, iy, iz;
  // Grid spacings in all dirctions
  float hx = 1./n.x;
  float hy = 1./n.y;
  float hz = 1./n.z;
  float hx_inv2 = 1./(hx*hx);
  float hy_inv2 = 1./(hy*hy);
  float hz_inv2 = 1./(hz*hz);
   float *c,*d;
  // Temporary arrays for Thomas algorithm
   hipHostMalloc((void**)&c,n.z*sizeof(float), hipHostMallocDefault);
   hipHostMalloc((void**)&d,n.z*sizeof(float), hipHostMallocDefault);
   // float c[100],d[100];
   //float* c=malloc(n.z*sizeof(float));
   //float* d=malloc(n.z*sizeof(float));
   // Loop over number of relaxation steps
  for (ix = 0; ix<n.x; ix++) {
    for (iy = 0; iy<n.y; iy++) {
      // Do a tridiagonal solve in the vertical direction
      // STEP 1: Calculate modified coefficients
      c[0] = (-omega2*lambda2*hz_inv2)
	/ (delta+2.*omega2*(hx_inv2+hy_inv2+lambda2*hz_inv2));
      d[0] = b[LINIDX(n, ix,iy,0)]
	/ (delta+2.*omega2*(hx_inv2+hy_inv2+lambda2*hz_inv2));
      for (iz = 1; iz<n.z; iz++) {
        c[iz] = (-omega2*lambda2*hz_inv2) 
	  / ( (delta+2.*omega2*(hx_inv2+hy_inv2+lambda2*hz_inv2)) 
	      - (-omega2*lambda2*hz_inv2) * c[iz-1]);
        d[iz] = (b[LINIDX(n, ix,iy,iz)] 
                 - (-omega2*lambda2*hz_inv2)*d[iz-1])
	  / ( (delta+2.*omega2*(hx_inv2+hy_inv2+lambda2*hz_inv2))
	      - (-omega2*lambda2*hz_inv2)*c[iz-1]);
      }
      // STEP 2: Back-substitution.
      y[LINIDX(n, ix,iy,n.z-1)] = d[n.z-1];
      for (iz = n.z-2; iz>=0; iz--) {
        y[LINIDX(n, ix,iy,iz)] 
          = d[iz] - c[iz]*y[LINIDX(n, ix,iy,iz+1)];
      }
    }
  }
  hipFree(c);
  hipFree(d);
}





__global__ void gpu_bj(const struct N *n,
	      const float* b,
	      float* y) {
  int ix, iy, iz;
  // Grid spacings in all dirctions
  float hx = 1./n->x;
  float hy = 1./n->y;
  float hz = 1./n->z;
  float hx_inv2 = 1./(hx*hx);
  float hy_inv2 = 1./(hy*hy);
  float hz_inv2 = 1./(hz*hz);
  
  //float *c,*d;
  // Temporary arrays for Thomas algorithm
  //cudaMalloc((void**)&c,n->z*sizeof(float));
  //cudaMalloc((void**)&d,n->z*sizeof(float));
  float c[1000],d[1000];
  //float* c=malloc(n.z*sizeof(float));
  //float* d=malloc(n.z*sizeof(float));
  // Loop over number of relaxation steps
  ix=blockIdx.x*BLOCK_SIZE+threadIdx.x;
  iy=blockIdx.y*BLOCK_SIZE+threadIdx.y;
  // for (ix = 0; ix<n->x; ix++) {
  // for (iy = 0; iy<n->y; iy++) {
      // Do a tridiagonal solve in the vertical direction
      // STEP 1: Calculate modified coefficients
      c[0] = (-omega2*lambda2*hz_inv2)/(delta+2.*omega2*(hx_inv2+hy_inv2+lambda2*hz_inv2));
      d[0] = b[GLINIDX(n, ix,iy,0)]/(delta+2.*omega2*(hx_inv2+hy_inv2+lambda2*hz_inv2));
      for (iz = 1; iz<n->z; iz++) {
        c[iz] = (-omega2*lambda2*hz_inv2)/( (delta+2.*omega2*(hx_inv2+hy_inv2+lambda2*hz_inv2))- (-omega2*lambda2*hz_inv2) * c[iz-1]);
        d[iz] = (b[GLINIDX(n, ix,iy,iz)]-(-omega2*lambda2*hz_inv2)*d[iz-1])/((delta+2.*omega2*(hx_inv2+hy_inv2+lambda2*hz_inv2))- (-omega2*lambda2*hz_inv2)*c[iz-1]);
      }
      // STEP 2: Back-substitution.
      y[GLINIDX(n, ix,iy,n->z-1)] = d[n->z-1];
      for (iz = n->z-2; iz>=0; iz--) {
        y[GLINIDX(n, ix,iy,iz)]=d[iz] - c[iz]*y[GLINIDX(n, ix,iy,iz+1)];
      }
      // }
      // }
}




int main(){
  n.x = 20;
  n.y = 100;
  n.z = 20;
  int i;  
  
  printf(" parameters\n");
  printf(" ==========\n");
  printf(" nx        = %10d\n",n.x);
  printf(" ny        = %10d\n",n.y);
  printf(" nz        = %10d\n",n.z);
  printf(" omega2    = %12.6e\n",omega2);
  printf(" lambda2   = %12.6e\n",lambda2);
  printf(" delta     = %12.6e\n",delta);
  
  float x[len],y[len],gpu_y[len];
  for(i=0;i<len;i++){
    x[i]=1.2;
  }
  double start1=clock();
  for(i=0;i<1000;i++)
  prec_BJ(n,x,y);
  double end1=clock();


  N *h_n,*dev_n;
  h_n=(struct N*)malloc(sizeof(N));

  h_n->x=n.x;
  h_n->y=n.y;
  h_n->z=n.z;
  
  float *dev_b, *dev_y;


  hipMalloc((void**)&dev_n,sizeof(N));
  hipMalloc((void**)&dev_b,len*sizeof(float));
  hipMalloc((void**)&dev_y,len*sizeof(float));


  hipMemcpy(dev_n,h_n,sizeof(N),hipMemcpyHostToDevice);
  hipMemcpy(dev_b,x,len*sizeof(float),hipMemcpyHostToDevice);
  dim3 dimBlock(BLOCK_SIZE,BLOCK_SIZE);
  dim3 dimGrid(n.x/BLOCK_SIZE,n.y/BLOCK_SIZE);
  gpu_bj<<<dimGrid,dimBlock>>>(dev_n,dev_b,dev_y);
  hipMemcpy(gpu_y,dev_y,len*sizeof(float),hipMemcpyDeviceToHost);
  


  
  /*for(i=0;i<len;i++){
    if(y[i]-gpu_y[i]>0.00001)
      printf("%f--%f\n",y[i],gpu_y[i]);
    else
      printf(".");
      }*/

  hipFree(dev_n);
  hipFree(dev_b);
  hipFree(dev_y);
  
  printf("cpu time = %f\n",(double)(end1-start1)/CLOCKS_PER_SEC*1000000);

  return(0);
}



	.text
	.file	"bj.hip"
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z7prec_BJ1NPKfPf
.LCPI0_0:
	.quad	0x3ff0000000000000              # double 1
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0
.LCPI0_1:
	.long	0x3f800000                      # float 1
.LCPI0_2:
	.long	0xc61c4000                      # float -1.0E+4
.LCPI0_3:
	.long	0x461c4000                      # float 1.0E+4
	.text
	.globl	_Z7prec_BJ1NPKfPf
	.type	_Z7prec_BJ1NPKfPf,@function
_Z7prec_BJ1NPKfPf:                      # @_Z7prec_BJ1NPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rcx, %rbx
	movq	%rdx, %r14
	movl	%esi, %r15d
	movq	%rdi, %r12
	movslq	%esi, %r13
	shlq	$2, %r13
	leaq	64(%rsp), %rbp
	xorl	%eax, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movq	%rbp, %rdi
	movq	%r13, %rsi
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	40(%rsp), %rdi
	movq	%r13, %rsi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movq	(%rbp), %rdi
	movq	%r12, 32(%rsp)                  # 8-byte Spill
	testl	%r12d, %r12d
	jle	.LBB0_13
# %bb.1:                                # %.preheader.lr.ph
	movq	%r14, %r11
	movq	32(%rsp), %rax                  # 8-byte Reload
	movq	%rax, %rdx
	shrq	$32, %rdx
	cvtsi2sd	%r15d, %xmm0
	movsd	.LCPI0_0(%rip), %xmm1           # xmm1 = mem[0],zero
	movapd	%xmm1, %xmm2
	divsd	%xmm0, %xmm2
	xorps	%xmm0, %xmm0
	cvtsd2ss	%xmm2, %xmm0
	mulss	%xmm0, %xmm0
	movss	.LCPI0_1(%rip), %xmm2           # xmm2 = mem[0],zero,zero,zero
	cvtsi2sd	%edx, %xmm3
	movapd	%xmm1, %xmm4
	divsd	%xmm3, %xmm4
	movaps	%xmm2, %xmm3
	cvtsd2ss	%xmm4, %xmm4
	divss	%xmm0, %xmm3
	mulss	%xmm4, %xmm4
	xorps	%xmm0, %xmm0
	cvtsi2sd	%eax, %xmm0
	divsd	%xmm0, %xmm1
	movaps	%xmm2, %xmm0
	cvtsd2ss	%xmm1, %xmm1
	divss	%xmm4, %xmm0
	mulss	%xmm1, %xmm1
	divss	%xmm1, %xmm2
	addss	%xmm0, %xmm2
	movss	.LCPI0_2(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	mulss	%xmm3, %xmm0
	mulss	.LCPI0_3(%rip), %xmm3
	xorps	%xmm1, %xmm1
	cvtss2sd	%xmm0, %xmm1
	addss	%xmm2, %xmm3
	cvtss2sd	%xmm3, %xmm3
	addsd	%xmm3, %xmm3
	xorps	%xmm2, %xmm2
	addsd	%xmm3, %xmm2
	movaps	%xmm1, %xmm3
	divsd	%xmm2, %xmm3
	cvtsd2ss	%xmm3, %xmm3
	movq	40(%rsp), %rcx
	leal	-1(%r15), %eax
	movl	%eax, 12(%rsp)                  # 4-byte Spill
	movslq	%eax, %rsi
	leal	-2(%r15), %eax
	cltq
	movl	%r15d, %r9d
	movl	%r15d, %r8d
	movq	%rdx, %r14
	imull	%edx, %r8d
	movl	%r8d, 28(%rsp)                  # 4-byte Spill
	incq	%rax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movl	$0, 8(%rsp)                     # 4-byte Folded Spill
	movq	%r11, 56(%rsp)                  # 8-byte Spill
.LBB0_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_4 Depth 2
                                        #       Child Loop BB0_7 Depth 3
                                        #       Child Loop BB0_10 Depth 3
	testl	%r14d, %r14d
	jle	.LBB0_12
# %bb.3:                                # %.lr.ph88
                                        #   in Loop: Header=BB0_2 Depth=1
	movl	8(%rsp), %eax                   # 4-byte Reload
	movl	%eax, %r13d
	imull	%r14d, %r13d
	movl	12(%rsp), %edx                  # 4-byte Reload
	movq	16(%rsp), %rax                  # 8-byte Reload
	movl	%eax, %r10d
	xorl	%ebp, %ebp
.LBB0_4:                                #   Parent Loop BB0_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB0_7 Depth 3
                                        #       Child Loop BB0_10 Depth 3
	leal	(%r13,%rbp), %r12d
	imull	%r15d, %r12d
	movss	%xmm3, (%rdi)
	movslq	%r12d, %rax
	xorps	%xmm4, %xmm4
	cvtss2sd	(%r11,%rax,4), %xmm4
	divsd	%xmm2, %xmm4
	cvtsd2ss	%xmm4, %xmm4
	movss	%xmm4, (%rcx)
	cmpl	$1, %r15d
	jle	.LBB0_5
# %bb.6:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB0_4 Depth=2
	movslq	%r10d, %rax
	leaq	(%rbx,%rax,4), %r8
	leaq	(%r11,%rax,4), %r11
	movl	$1, %eax
.LBB0_7:                                # %.lr.ph
                                        #   Parent Loop BB0_2 Depth=1
                                        #     Parent Loop BB0_4 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	-4(%rdi,%rax,4), %xmm4          # xmm4 = mem[0],zero,zero,zero
	mulss	%xmm0, %xmm4
	cvtss2sd	%xmm4, %xmm4
	movapd	%xmm2, %xmm5
	subsd	%xmm4, %xmm5
	movaps	%xmm1, %xmm4
	divsd	%xmm5, %xmm4
	cvtsd2ss	%xmm4, %xmm4
	movss	%xmm4, (%rdi,%rax,4)
	movss	(%r11,%rax,4), %xmm4            # xmm4 = mem[0],zero,zero,zero
	movss	-4(%rcx,%rax,4), %xmm6          # xmm6 = mem[0],zero,zero,zero
	mulss	%xmm0, %xmm6
	subss	%xmm6, %xmm4
	cvtss2sd	%xmm4, %xmm4
	divsd	%xmm5, %xmm4
	cvtsd2ss	%xmm4, %xmm4
	movss	%xmm4, (%rcx,%rax,4)
	incq	%rax
	cmpq	%rax, %r9
	jne	.LBB0_7
# %bb.8:                                # %._crit_edge
                                        #   in Loop: Header=BB0_4 Depth=2
	addl	%esi, %r12d
	movss	(%rcx,%rsi,4), %xmm4            # xmm4 = mem[0],zero,zero,zero
	movslq	%r12d, %rax
	movss	%xmm4, (%rbx,%rax,4)
	cmpl	$2, %r15d
	jl	.LBB0_11
# %bb.9:                                # %.lr.ph85
                                        #   in Loop: Header=BB0_4 Depth=2
	movl	%edx, %eax
	movq	48(%rsp), %r11                  # 8-byte Reload
.LBB0_10:                               #   Parent Loop BB0_2 Depth=1
                                        #     Parent Loop BB0_4 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	-4(%rcx,%r11,4), %xmm4          # xmm4 = mem[0],zero,zero,zero
	movss	-4(%rdi,%r11,4), %xmm5          # xmm5 = mem[0],zero,zero,zero
	cltq
	mulss	(%rbx,%rax,4), %xmm5
	subss	%xmm5, %xmm4
	movss	%xmm4, -4(%r8,%r11,4)
	decl	%eax
	decq	%r11
	jg	.LBB0_10
	jmp	.LBB0_11
.LBB0_5:                                # %._crit_edge.thread
                                        #   in Loop: Header=BB0_4 Depth=2
	movss	(%rcx,%rsi,4), %xmm4            # xmm4 = mem[0],zero,zero,zero
	addl	%esi, %r12d
	movslq	%r12d, %rax
	movss	%xmm4, (%rbx,%rax,4)
.LBB0_11:                               # %._crit_edge86
                                        #   in Loop: Header=BB0_4 Depth=2
	incq	%rbp
	addl	%r15d, %r10d
	addl	%r15d, %edx
	cmpq	%r14, %rbp
	movq	56(%rsp), %r11                  # 8-byte Reload
	jne	.LBB0_4
.LBB0_12:                               # %._crit_edge89
                                        #   in Loop: Header=BB0_2 Depth=1
	movl	8(%rsp), %r8d                   # 4-byte Reload
	incl	%r8d
	movq	16(%rsp), %rax                  # 8-byte Reload
	movl	28(%rsp), %edx                  # 4-byte Reload
	addl	%edx, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	addl	%edx, 12(%rsp)                  # 4-byte Folded Spill
	movl	%r8d, 8(%rsp)                   # 4-byte Spill
	cmpl	32(%rsp), %r8d                  # 4-byte Folded Reload
	jne	.LBB0_2
.LBB0_13:                               # %._crit_edge91
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z7prec_BJ1NPKfPf, .Lfunc_end0-_Z7prec_BJ1NPKfPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__gpu_bjPK1NPKfPf # -- Begin function _Z21__device_stub__gpu_bjPK1NPKfPf
	.type	_Z21__device_stub__gpu_bjPK1NPKfPf,@function
_Z21__device_stub__gpu_bjPK1NPKfPf:     # @_Z21__device_stub__gpu_bjPK1NPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6gpu_bjPK1NPKfPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z21__device_stub__gpu_bjPK1NPKfPf, .Lfunc_end1-_Z21__device_stub__gpu_bjPK1NPKfPf
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI2_0:
	.quad	0x3ff0000000000000              # double 1
.LCPI2_1:
	.quad	0x40c3880000000000              # double 1.0E+4
.LCPI2_2:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movabsq	$429496729620, %rax             # imm = 0x6400000014
	movq	%rax, n(%rip)
	movl	$20, n+8(%rip)
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movl	n(%rip), %esi
	movl	$.L.str.2, %edi
	xorl	%eax, %eax
	callq	printf
	movl	n+4(%rip), %esi
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	movl	n+8(%rip), %esi
	movl	$.L.str.4, %edi
	xorl	%eax, %eax
	callq	printf
	movsd	.LCPI2_0(%rip), %xmm0           # xmm0 = mem[0],zero
	movl	$.L.str.5, %edi
	movb	$1, %al
	callq	printf
	movsd	.LCPI2_1(%rip), %xmm0           # xmm0 = mem[0],zero
	movl	$.L.str.6, %edi
	movb	$1, %al
	callq	printf
	movl	$.L.str.7, %edi
	xorps	%xmm0, %xmm0
	movb	$1, %al
	callq	printf
	movl	n+4(%rip), %eax
	imull	n(%rip), %eax
	imull	n+8(%rip), %eax
	movq	%rsp, %r15
	leaq	15(,%rax,4), %rcx
	andq	$-16, %rcx
	subq	%rcx, %r15
	movq	%r15, %rsp
	movq	%rsp, %r12
	subq	%rcx, %r12
	movq	%r12, %rsp
	movq	%rsp, %rbx
	subq	%rcx, %rbx
	movq	%rbx, %rsp
	testl	%eax, %eax
	jle	.LBB2_3
# %bb.1:                                # %.lr.ph.preheader
	xorl	%ecx, %ecx
.LBB2_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$1067030938, (%r15,%rcx,4)      # imm = 0x3F99999A
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB2_2
.LBB2_3:                                # %._crit_edge
	movl	$1000, %r14d                    # imm = 0x3E8
	callq	clock
	movq	%rax, -48(%rbp)                 # 8-byte Spill
.LBB2_4:                                # =>This Inner Loop Header: Depth=1
	movq	n(%rip), %rdi
	movl	n+8(%rip), %esi
	movq	%r15, %rdx
	movq	%r12, %rcx
	callq	_Z7prec_BJ1NPKfPf
	decl	%r14d
	jne	.LBB2_4
# %bb.5:
	callq	clock
	movq	%rax, -80(%rbp)                 # 8-byte Spill
	movl	$12, %edi
	callq	malloc
	movq	%rax, %r13
	movl	n(%rip), %eax
	movl	%eax, (%r13)
	movl	n+4(%rip), %eax
	movl	%eax, 4(%r13)
	movl	n+8(%rip), %eax
	movl	%eax, 8(%r13)
	leaq	-72(%rbp), %r14
	movl	$12, %esi
	movq	%r14, %rdi
	callq	hipMalloc
	movslq	n(%rip), %rax
	movslq	n+4(%rip), %rcx
	imulq	%rax, %rcx
	movslq	n+8(%rip), %rsi
	imulq	%rcx, %rsi
	shlq	$2, %rsi
	leaq	-64(%rbp), %r12
	movq	%r12, %rdi
	callq	hipMalloc
	movslq	n(%rip), %rax
	movslq	n+4(%rip), %rcx
	imulq	%rax, %rcx
	movslq	n+8(%rip), %rsi
	imulq	%rcx, %rsi
	shlq	$2, %rsi
	leaq	-56(%rbp), %rdi
	callq	hipMalloc
	movq	(%r14), %rdi
	movl	$12, %edx
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movslq	n(%rip), %rax
	movslq	n+4(%rip), %rcx
	imulq	%rax, %rcx
	movslq	n+8(%rip), %rdx
	imulq	%rcx, %rdx
	shlq	$2, %rdx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movslq	n(%rip), %rax
	imulq	$1717986919, %rax, %rax         # imm = 0x66666667
	movq	%rax, %rcx
	shrq	$63, %rcx
	sarq	$33, %rax
	addl	%ecx, %eax
	movslq	n+4(%rip), %rcx
	imulq	$1717986919, %rcx, %rdi         # imm = 0x66666667
	movq	%rdi, %rcx
	shrq	$63, %rcx
	sarq	$33, %rdi
	addl	%ecx, %edi
	shlq	$32, %rdi
	orq	%rax, %rdi
	movabsq	$21474836485, %rdx              # imm = 0x500000005
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_7
# %bb.6:
	movq	-72(%rbp), %rdi
	movq	-64(%rbp), %rsi
	movq	-56(%rbp), %rdx
	callq	_Z21__device_stub__gpu_bjPK1NPKfPf
.LBB2_7:
	cvtsi2sdq	-80(%rbp), %xmm1        # 8-byte Folded Reload
	cvtsi2sdq	-48(%rbp), %xmm0        # 8-byte Folded Reload
	subsd	%xmm0, %xmm1
	movsd	%xmm1, -48(%rbp)                # 8-byte Spill
	movq	-56(%rbp), %rsi
	movslq	n(%rip), %rax
	movslq	n+4(%rip), %rcx
	imulq	%rax, %rcx
	movslq	n+8(%rip), %rdx
	imulq	%rcx, %rdx
	shlq	$2, %rdx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	-72(%rbp), %rdi
	callq	hipFree
	movq	-64(%rbp), %rdi
	callq	hipFree
	movq	-56(%rbp), %rdi
	callq	hipFree
	movsd	.LCPI2_2(%rip), %xmm0           # xmm0 = mem[0],zero
	movsd	-48(%rbp), %xmm1                # 8-byte Reload
                                        # xmm1 = mem[0],zero
	divsd	%xmm0, %xmm1
	mulsd	%xmm0, %xmm1
	movapd	%xmm1, %xmm0
	movl	$.L.str.8, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	leaq	-40(%rbp), %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa %rsp, 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6gpu_bjPK1NPKfPf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	n,@object                       # @n
	.bss
	.globl	n
	.p2align	3, 0x0
n:
	.zero	12
	.size	n, 12

	.type	_Z6gpu_bjPK1NPKfPf,@object      # @_Z6gpu_bjPK1NPKfPf
	.section	.rodata,"a",@progbits
	.globl	_Z6gpu_bjPK1NPKfPf
	.p2align	3, 0x0
_Z6gpu_bjPK1NPKfPf:
	.quad	_Z21__device_stub__gpu_bjPK1NPKfPf
	.size	_Z6gpu_bjPK1NPKfPf, 8

	.type	.L.str.2,@object                # @.str.2
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.2:
	.asciz	" nx        = %10d\n"
	.size	.L.str.2, 19

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	" ny        = %10d\n"
	.size	.L.str.3, 19

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	" nz        = %10d\n"
	.size	.L.str.4, 19

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	" omega2    = %12.6e\n"
	.size	.L.str.5, 21

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	" lambda2   = %12.6e\n"
	.size	.L.str.6, 21

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	" delta     = %12.6e\n"
	.size	.L.str.7, 21

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"cpu time = %f\n"
	.size	.L.str.8, 15

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6gpu_bjPK1NPKfPf"
	.size	.L__unnamed_1, 19

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	" parameters"
	.size	.Lstr, 12

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	" =========="
	.size	.Lstr.1, 12

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__gpu_bjPK1NPKfPf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6gpu_bjPK1NPKfPf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6gpu_bjPK1NPKfPf      ; -- Begin function _Z6gpu_bjPK1NPKfPf
	.globl	_Z6gpu_bjPK1NPKfPf
	.p2align	8
	.type	_Z6gpu_bjPK1NPKfPf,@function
_Z6gpu_bjPK1NPKfPf:                     ; @_Z6gpu_bjPK1NPKfPf
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[8:9], s[0:1], 0x10
	v_and_b32_e32 v1, 0x3ff, v0
	s_mul_i32 s15, s15, 5
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	s_load_b64 s[0:1], s[4:5], 0x0
	s_load_b32 s4, s[4:5], 0x8
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_i32_e32 v[2:3], s0
	v_cvt_f64_i32_e32 v[4:5], s1
	v_cvt_f64_i32_e32 v[10:11], s4
	s_cmp_lt_i32 s4, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f64 v[12:13], null, v[2:3], v[2:3], 1.0
	v_div_scale_f64 v[14:15], null, v[4:5], v[4:5], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_div_scale_f64 v[16:17], null, v[10:11], v[10:11], 1.0
	v_div_scale_f64 v[28:29], vcc_lo, 1.0, v[2:3], 1.0
	v_div_scale_f64 v[30:31], s0, 1.0, v[4:5], 1.0
	v_rcp_f64_e32 v[6:7], v[12:13]
	v_rcp_f64_e32 v[8:9], v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[18:19], v[16:17]
	v_fma_f64 v[20:21], -v[12:13], v[6:7], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[22:23], -v[14:15], v[8:9], 1.0
	v_fma_f64 v[24:25], -v[16:17], v[18:19], 1.0
	v_fma_f64 v[6:7], v[6:7], v[20:21], v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[20:21], v[8:9], v[22:23], v[8:9]
	v_mad_u64_u32 v[8:9], null, s14, 5, v[1:2]
	v_fma_f64 v[18:19], v[18:19], v[24:25], v[18:19]
	v_bfe_u32 v9, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v8, s1, v8
	v_add3_u32 v0, s15, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v0, s4
	v_ashrrev_i32_e32 v1, 31, v0
	v_fma_f64 v[22:23], -v[12:13], v[6:7], 1.0
	v_fma_f64 v[24:25], -v[14:15], v[20:21], 1.0
	v_fma_f64 v[26:27], -v[16:17], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[22:23], v[6:7], v[22:23], v[6:7]
	v_lshlrev_b64 v[6:7], 2, v[0:1]
	v_fma_f64 v[20:21], v[20:21], v[24:25], v[20:21]
	v_div_scale_f64 v[24:25], s1, 1.0, v[10:11], 1.0
	v_fma_f64 v[18:19], v[18:19], v[26:27], v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v26, s2, s6, v6
	v_add_co_ci_u32_e64 v27, s2, s7, v7, s2
	global_load_b32 v36, v[26:27], off
	v_mul_f64 v[26:27], v[28:29], v[22:23]
	v_mul_f64 v[32:33], v[30:31], v[20:21]
	v_mul_f64 v[34:35], v[24:25], v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[12:13], -v[12:13], v[26:27], v[28:29]
	v_fma_f64 v[14:15], -v[14:15], v[32:33], v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[16:17], -v[16:17], v[34:35], v[24:25]
	v_div_fmas_f64 v[12:13], v[12:13], v[22:23], v[26:27]
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[14:15], v[14:15], v[20:21], v[32:33]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[16:17], v[16:17], v[18:19], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f64 v[2:3], v[12:13], v[2:3], 1.0
	v_div_fixup_f64 v[4:5], v[14:15], v[4:5], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f64 v[10:11], v[16:17], v[10:11], 1.0
	v_cvt_f32_f64_e32 v2, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_f64_e32 v3, v[4:5]
	v_cvt_f32_f64_e32 v4, v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v2, v2, v2 :: v_dual_mul_f32 v3, v3, v3
	v_div_scale_f32 v5, null, v2, v2, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v4, v4, v4
	v_div_scale_f32 v10, null, v3, v3, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v12, v5
	v_div_scale_f32 v15, vcc_lo, 1.0, v2, 1.0
	v_rcp_f32_e32 v13, v10
	v_div_scale_f32 v11, null, v4, v4, 1.0
	v_div_scale_f32 v16, s0, 1.0, v3, 1.0
	v_div_scale_f32 v20, s1, 1.0, v4, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v17, -v5, v12, 1.0
	v_rcp_f32_e32 v14, v11
	v_fma_f32 v18, -v10, v13, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v12, v17, v12 :: v_dual_fmac_f32 v13, v18, v13
	v_mul_f32_e32 v17, v15, v12
	s_waitcnt_depctr 0xfff
	v_fma_f32 v19, -v11, v14, 1.0
	v_mul_f32_e32 v18, v16, v13
	v_fma_f32 v21, -v5, v17, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v14, v19, v14
	v_fma_f32 v22, -v10, v18, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v17, v21, v12
	v_dual_mul_f32 v19, v20, v14 :: v_dual_fmac_f32 v18, v22, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v5, -v5, v17, v15
	v_fma_f32 v23, -v11, v19, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v10, -v10, v18, v16
	v_div_fmas_f32 v5, v5, v12, v17
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v10, v10, v13, v18
	s_mov_b32 vcc_lo, s1
	v_div_fixup_f32 v2, v5, v2, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v3, v10, v3, 1.0
	v_dual_fmac_f32 v19, v23, v14 :: v_dual_add_f32 v2, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v11, -v11, v19, v20
	v_div_fmas_f32 v11, v11, v14, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v10, v11, v4, 1.0
	v_fmamk_f32 v2, v10, 0x461c4000, v2
	v_mul_f32_e32 v10, 0xc61c4000, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[4:5], v2
	v_cvt_f64_f32_e32 v[2:3], v10
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[11:12], v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[4:5], 2.0, 0
	v_div_scale_f64 v[13:14], null, v[4:5], v[4:5], v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f64 v[15:16], null, v[4:5], v[4:5], v[11:12]
	v_div_scale_f64 v[25:26], vcc_lo, v[2:3], v[4:5], v[2:3]
	v_rcp_f64_e32 v[17:18], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[19:20], v[15:16]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[21:22], -v[13:14], v[17:18], 1.0
	v_fma_f64 v[23:24], -v[15:16], v[19:20], 1.0
	v_fma_f64 v[17:18], v[17:18], v[21:22], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], v[19:20], v[23:24], v[19:20]
	v_fma_f64 v[21:22], -v[13:14], v[17:18], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[23:24], -v[15:16], v[19:20], 1.0
	v_fma_f64 v[17:18], v[17:18], v[21:22], v[17:18]
	v_div_scale_f64 v[21:22], s0, v[11:12], v[4:5], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[19:20], v[19:20], v[23:24], v[19:20]
	v_mul_f64 v[23:24], v[25:26], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[27:28], v[21:22], v[19:20]
	v_fma_f64 v[13:14], -v[13:14], v[23:24], v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], -v[15:16], v[27:28], v[21:22]
	v_div_fmas_f64 v[13:14], v[13:14], v[17:18], v[23:24]
	s_mov_b32 vcc_lo, s0
	s_mov_b32 s0, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[15:16], v[15:16], v[19:20], v[27:28]
	v_div_fixup_f64 v[13:14], v[13:14], v[4:5], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[15:16], v[15:16], v[4:5], v[11:12]
	v_cvt_f32_f64_e32 v12, v[13:14]
	s_delay_alu instid0(VALU_DEP_2)
	v_cvt_f32_f64_e32 v11, v[15:16]
	s_clause 0x1
	scratch_store_b32 off, v12, off offset:16
	scratch_store_b32 off, v11, off offset:4016
	s_cbranch_scc0 .LBB0_2
; %bb.1:                                ; %._crit_edge81.critedge
	s_lshl_b32 s0, s4, 2
	v_add_co_u32 v13, vcc_lo, v0, s4
	s_addk_i32 s0, 0xfb0
	scratch_load_b32 v15, off, s0 offset:-4
	s_ashr_i32 s0, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v14, vcc_lo, s0, v1, vcc_lo
	s_mov_b32 s0, 0
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, s8, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s9, v14, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[13:14], v15, off offset:-4
.LBB0_2:                                ; %Flow111
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_7
; %bb.3:                                ; %.lr.ph.preheader
	v_add_co_u32 v6, vcc_lo, v6, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	v_or_b32_e64 v13, 16, 4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, 4
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	v_or_b32_e64 v14, 0xfb0, 4
	s_add_i32 s1, s4, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, s1
.LBB0_4:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v17, v[6:7], off
	v_mul_f32_e32 v12, v10, v12
	s_add_i32 s2, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s2, 0
	v_cvt_f64_f32_e32 v[15:16], v12
	s_waitcnt vmcnt(0)
	v_fma_f32 v17, -v10, v11, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[4:5], -v[15:16]
	v_cvt_f64_f32_e32 v[15:16], v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f64 v[17:18], null, v[11:12], v[11:12], v[2:3]
	v_div_scale_f64 v[29:30], vcc_lo, v[2:3], v[11:12], v[2:3]
	v_div_scale_f64 v[19:20], null, v[11:12], v[11:12], v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[21:22], v[17:18]
	v_rcp_f64_e32 v[23:24], v[19:20]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[25:26], -v[17:18], v[21:22], 1.0
	v_fma_f64 v[27:28], -v[19:20], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[21:22], v[25:26], v[21:22]
	v_fma_f64 v[23:24], v[23:24], v[27:28], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[25:26], -v[17:18], v[21:22], 1.0
	v_fma_f64 v[27:28], -v[19:20], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[21:22], v[21:22], v[25:26], v[21:22]
	v_div_scale_f64 v[25:26], s0, v[15:16], v[11:12], v[15:16]
	v_fma_f64 v[23:24], v[23:24], v[27:28], v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[27:28], v[29:30], v[21:22]
	v_mul_f64 v[31:32], v[25:26], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[17:18], -v[17:18], v[27:28], v[29:30]
	v_fma_f64 v[19:20], -v[19:20], v[31:32], v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[17:18], v[17:18], v[21:22], v[27:28]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[19:20], v[19:20], v[23:24], v[31:32]
	v_add_co_u32 v6, vcc_lo, v6, 4
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fixup_f64 v[17:18], v[17:18], v[11:12], v[2:3]
	v_div_fixup_f64 v[15:16], v[19:20], v[11:12], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_f64_e32 v12, v[17:18]
	v_cvt_f32_f64_e32 v11, v[15:16]
	scratch_store_b32 v13, v12, off
	v_add_nc_u32_e32 v13, 4, v13
	scratch_store_b32 v14, v11, off
	v_add_nc_u32_e32 v14, 4, v14
	s_cbranch_scc1 .LBB0_4
; %bb.5:                                ; %._crit_edge
	s_lshl_b32 s0, s4, 2
	v_add3_u32 v4, v9, v8, s15
	s_add_i32 s2, s0, 0xfb0
	v_add_co_u32 v0, vcc_lo, v0, s4
	scratch_load_b32 v10, off, s2 offset:-4
	v_mad_u64_u32 v[2:3], null, s4, v4, s[4:5]
	s_ashr_i32 s2, s4, 31
	s_add_i32 s0, s0, -8
	v_add_co_ci_u32_e32 v1, vcc_lo, s2, v1, vcc_lo
	v_add_nc_u32_e64 v5, s0, 16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v3, -2, v2
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_nc_u32_e32 v2, -1, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v4, 31, v3
	v_add_co_u32 v6, vcc_lo, s8, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v1, vcc_lo
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v4, vcc_lo
	v_add_nc_u32_e64 v4, 0xfb0, s0
	s_waitcnt vmcnt(0)
	global_store_b32 v[6:7], v10, off offset:-4
.LBB0_6:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v3, 31, v2
	scratch_load_b32 v8, v4, off
	scratch_load_b32 v9, v5, off
	v_add_nc_u32_e32 v4, -4, v4
	v_add_nc_u32_e32 v5, -4, v5
	s_add_i32 s1, s1, -1
	v_lshlrev_b64 v[6:7], 2, v[2:3]
	v_add_nc_u32_e32 v2, -1, v2
	s_cmp_eq_u32 s1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
	global_load_b32 v3, v[6:7], off
	s_waitcnt vmcnt(0)
	v_fma_f32 v3, -v9, v3, v8
	global_store_b32 v[0:1], v3, off
	v_add_co_u32 v0, vcc_lo, v0, -4
	v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo
	s_cbranch_scc0 .LBB0_6
.LBB0_7:                                ; %._crit_edge81
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6gpu_bjPK1NPKfPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 8016
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 37
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6gpu_bjPK1NPKfPf, .Lfunc_end0-_Z6gpu_bjPK1NPKfPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1812
; NumSgprs: 18
; NumVgprs: 37
; ScratchSize: 8016
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 37
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6gpu_bjPK1NPKfPf
    .private_segment_fixed_size: 8016
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6gpu_bjPK1NPKfPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     37
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
