#include <stdlib.h>
#include <stdio.h>

#define CUDA_DEVICE (0)
#define NUM_THREADS (1<<13)
#define BLOCK_DIM (64)
#define GRID_DIM (NUM_THREADS/BLOCK_DIM)
#define NUM_BYTES (NUM_THREADS*4*sizeof(float))

// Compile and run with the commands:
//   nvcc float4_test.cu
//   ./a.out
//
// Failure occurs on my Tesla C870 card when KERNEL_INVOCATIONS is a large
// number (e.g. 100), and TEST_KERNEL is 1 or 3. Kernels 1 and 3 are those
// which write float4 values to device memory. Failure does not occur on
// my Quadro NVS 290 card for any of the kernels.
//
#define KERNEL_INVOCATIONS (100)
#define TEST_KERNEL (1)


__global__ void testKernel1(float4* g_out, float4* g_in) {
    const int idx = blockDim.x*blockIdx.x + threadIdx.x;
    g_out[idx] = g_in[idx];
}

__global__ void testKernel2(float* g_out, float4* g_in) {
    const int idx = BLOCK_DIM*blockIdx.x + threadIdx.x;
    float4 f4 = g_in[idx];
    g_out[4*idx+0] = f4.x;
    g_out[4*idx+1] = f4.y;
    g_out[4*idx+2] = f4.z;
    g_out[4*idx+3] = f4.w;
}

__global__ void testKernel3(float4* g_out, float* g_in) {
    const int idx = BLOCK_DIM*blockIdx.x + threadIdx.x;
    float x = g_in[4*idx+0];
    float y = g_in[4*idx+1];
    float z = g_in[4*idx+2];
    float w = g_in[4*idx+3];
    g_out[idx] = make_float4(x, y, z, w);
}

__global__ void testKernel4(float* g_out, float* g_in) {
    const int idx = BLOCK_DIM*blockIdx.x + threadIdx.x;
    g_out[NUM_THREADS*0 + idx] = g_in[NUM_THREADS*0 + idx];
    g_out[NUM_THREADS*1 + idx] = g_in[NUM_THREADS*1 + idx];
    g_out[NUM_THREADS*2 + idx] = g_in[NUM_THREADS*2 + idx];
    g_out[NUM_THREADS*3 + idx] = g_in[NUM_THREADS*3 + idx];
}

int main( int argc, char** argv)  {
    cudaSetDevice(CUDA_DEVICE);
    
    float *input = (float *)malloc(NUM_BYTES);
    float *output = (float *)malloc(NUM_BYTES);
    void* d_input;
    void* d_output;
    cudaMalloc(&d_input, NUM_BYTES);
    cudaMalloc(&d_output, NUM_BYTES);
    
    for (int i = 0; i < NUM_THREADS*4; i++) {
        input[i] = i;
    }
    cudaMemcpy(d_input, input, NUM_BYTES, cudaMemcpyHostToDevice);
    
    dim3 gridDim(GRID_DIM, 1, 1);
    dim3 blockDim(BLOCK_DIM, 1, 1);
    for (int i = 0; i < KERNEL_INVOCATIONS; i++) {
        switch (TEST_KERNEL) {
        case 1:
            testKernel1 <<<gridDim, blockDim>>> ((float4 *)d_output, (float4 *)d_input);
            break;
        case 2:
            testKernel2 <<<gridDim, blockDim>>> ((float *)d_output, (float4 *)d_input);
            break;
        case 3:
            testKernel3 <<<gridDim, blockDim>>> ((float4 *)d_output, (float *)d_input);
            break;
        case 4:
            testKernel4 <<<gridDim, blockDim>>> ((float *)d_output, (float *)d_input);
            break;
        }
        cudaThreadSynchronize();
    }
    
    cudaMemcpy(output, d_output, NUM_BYTES, cudaMemcpyDeviceToHost);
    for (int i = 0; i < NUM_THREADS*4; i++) {
        if (output[i] != i) {
            printf("KERNEL=%d FAILED: elem #%d = %f\n", TEST_KERNEL, i, output[i]);
        }
    }
    
    free(input);
    free(output);
    cudaFree(d_input);
    cudaFree(d_output);
}

	.file	"tmpxft_0036caa2_00000000-6_float4_test.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z40__device_stub__Z11testKernel1P6float4S0_P6float4S0_
	.type	_Z40__device_stub__Z11testKernel1P6float4S0_P6float4S0_, @function
_Z40__device_stub__Z11testKernel1P6float4S0_P6float4S0_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z11testKernel1P6float4S0_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z40__device_stub__Z11testKernel1P6float4S0_P6float4S0_, .-_Z40__device_stub__Z11testKernel1P6float4S0_P6float4S0_
	.globl	_Z11testKernel1P6float4S0_
	.type	_Z11testKernel1P6float4S0_, @function
_Z11testKernel1P6float4S0_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z11testKernel1P6float4S0_P6float4S0_
	.cfi_endproc
.LFE2053:
	.size	_Z11testKernel1P6float4S0_, .-_Z11testKernel1P6float4S0_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"KERNEL=%d FAILED: elem #%d = %f\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	xorl	%edi, %edi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	call	cudaSetDevice@PLT
	movl	$131072, %edi
	call	malloc@PLT
	movl	$131072, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movq	%rsp, %rdi
	movl	$131072, %esi
	movq	%rax, %rbp
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$131072, %esi
	call	cudaMalloc@PLT
	xorl	%eax, %eax
.L9:
	cvtsi2ssl	%eax, %xmm0
	movss	%xmm0, (%r12,%rax,4)
	incq	%rax
	cmpq	$32768, %rax
	jne	.L9
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movl	$131072, %edx
	movq	%r12, %rsi
	movl	$100, %ebx
	call	cudaMemcpy@PLT
	movl	$33554433, %eax
	movl	$1, 24(%rsp)
	salq	$7, %rax
	movl	$1, 36(%rsp)
	movq	%rax, 16(%rsp)
	subq	$64, %rax
	movq	%rax, 28(%rsp)
.L11:
	movl	36(%rsp), %ecx
	movq	28(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	16(%rsp), %rdi
	movl	24(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z40__device_stub__Z11testKernel1P6float4S0_P6float4S0_
.L10:
	call	cudaThreadSynchronize@PLT
	decl	%ebx
	jne	.L11
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	xorl	%ebx, %ebx
	movl	$131072, %edx
	leaq	.LC0(%rip), %r13
	call	cudaMemcpy@PLT
.L14:
	cvtsi2ssl	%ebx, %xmm1
	movss	0(%rbp,%rbx,4), %xmm0
	movl	%ebx, %ecx
	ucomiss	%xmm1, %xmm0
	jp	.L16
	je	.L12
.L16:
	movl	$1, %edx
	movq	%r13, %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
.L12:
	incq	%rbx
	cmpq	$32768, %rbx
	jne	.L14
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.text
	.globl	_Z39__device_stub__Z11testKernel2PfP6float4PfP6float4
	.type	_Z39__device_stub__Z11testKernel2PfP6float4PfP6float4, @function
_Z39__device_stub__Z11testKernel2PfP6float4PfP6float4:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z11testKernel2PfP6float4(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L21:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L23
	call	__stack_chk_fail@PLT
.L23:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z39__device_stub__Z11testKernel2PfP6float4PfP6float4, .-_Z39__device_stub__Z11testKernel2PfP6float4PfP6float4
	.globl	_Z11testKernel2PfP6float4
	.type	_Z11testKernel2PfP6float4, @function
_Z11testKernel2PfP6float4:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z11testKernel2PfP6float4PfP6float4
	.cfi_endproc
.LFE2055:
	.size	_Z11testKernel2PfP6float4, .-_Z11testKernel2PfP6float4
	.globl	_Z39__device_stub__Z11testKernel3P6float4PfP6float4Pf
	.type	_Z39__device_stub__Z11testKernel3P6float4PfP6float4Pf, @function
_Z39__device_stub__Z11testKernel3P6float4PfP6float4Pf:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z11testKernel3P6float4Pf(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L26:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L28
	call	__stack_chk_fail@PLT
.L28:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z39__device_stub__Z11testKernel3P6float4PfP6float4Pf, .-_Z39__device_stub__Z11testKernel3P6float4PfP6float4Pf
	.globl	_Z11testKernel3P6float4Pf
	.type	_Z11testKernel3P6float4Pf, @function
_Z11testKernel3P6float4Pf:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z11testKernel3P6float4PfP6float4Pf
	.cfi_endproc
.LFE2057:
	.size	_Z11testKernel3P6float4Pf, .-_Z11testKernel3P6float4Pf
	.globl	_Z33__device_stub__Z11testKernel4PfS_PfS_
	.type	_Z33__device_stub__Z11testKernel4PfS_PfS_, @function
_Z33__device_stub__Z11testKernel4PfS_PfS_:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L31
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z11testKernel4PfS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L31:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z33__device_stub__Z11testKernel4PfS_PfS_, .-_Z33__device_stub__Z11testKernel4PfS_PfS_
	.globl	_Z11testKernel4PfS_
	.type	_Z11testKernel4PfS_, @function
_Z11testKernel4PfS_:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z11testKernel4PfS_PfS_
	.cfi_endproc
.LFE2059:
	.size	_Z11testKernel4PfS_, .-_Z11testKernel4PfS_
	.section	.rodata.str1.1
.LC1:
	.string	"_Z11testKernel4PfS_"
.LC2:
	.string	"_Z11testKernel3P6float4Pf"
.LC3:
	.string	"_Z11testKernel2PfP6float4"
.LC4:
	.string	"_Z11testKernel1P6float4S0_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z11testKernel4PfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11testKernel3P6float4Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11testKernel2PfP6float4(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11testKernel1P6float4S0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2061:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>

#define CUDA_DEVICE (0)
#define NUM_THREADS (1<<13)
#define BLOCK_DIM (64)
#define GRID_DIM (NUM_THREADS/BLOCK_DIM)
#define NUM_BYTES (NUM_THREADS*4*sizeof(float))

// Compile and run with the commands:
//   nvcc float4_test.cu
//   ./a.out
//
// Failure occurs on my Tesla C870 card when KERNEL_INVOCATIONS is a large
// number (e.g. 100), and TEST_KERNEL is 1 or 3. Kernels 1 and 3 are those
// which write float4 values to device memory. Failure does not occur on
// my Quadro NVS 290 card for any of the kernels.
//
#define KERNEL_INVOCATIONS (100)
#define TEST_KERNEL (1)


__global__ void testKernel1(float4* g_out, float4* g_in) {
    const int idx = blockDim.x*blockIdx.x + threadIdx.x;
    g_out[idx] = g_in[idx];
}

__global__ void testKernel2(float* g_out, float4* g_in) {
    const int idx = BLOCK_DIM*blockIdx.x + threadIdx.x;
    float4 f4 = g_in[idx];
    g_out[4*idx+0] = f4.x;
    g_out[4*idx+1] = f4.y;
    g_out[4*idx+2] = f4.z;
    g_out[4*idx+3] = f4.w;
}

__global__ void testKernel3(float4* g_out, float* g_in) {
    const int idx = BLOCK_DIM*blockIdx.x + threadIdx.x;
    float x = g_in[4*idx+0];
    float y = g_in[4*idx+1];
    float z = g_in[4*idx+2];
    float w = g_in[4*idx+3];
    g_out[idx] = make_float4(x, y, z, w);
}

__global__ void testKernel4(float* g_out, float* g_in) {
    const int idx = BLOCK_DIM*blockIdx.x + threadIdx.x;
    g_out[NUM_THREADS*0 + idx] = g_in[NUM_THREADS*0 + idx];
    g_out[NUM_THREADS*1 + idx] = g_in[NUM_THREADS*1 + idx];
    g_out[NUM_THREADS*2 + idx] = g_in[NUM_THREADS*2 + idx];
    g_out[NUM_THREADS*3 + idx] = g_in[NUM_THREADS*3 + idx];
}

int main( int argc, char** argv)  {
    hipSetDevice(CUDA_DEVICE);
    
    float *input = (float *)malloc(NUM_BYTES);
    float *output = (float *)malloc(NUM_BYTES);
    void* d_input;
    void* d_output;
    hipMalloc(&d_input, NUM_BYTES);
    hipMalloc(&d_output, NUM_BYTES);
    
    for (int i = 0; i < NUM_THREADS*4; i++) {
        input[i] = i;
    }
    hipMemcpy(d_input, input, NUM_BYTES, hipMemcpyHostToDevice);
    
    dim3 gridDim(GRID_DIM, 1, 1);
    dim3 blockDim(BLOCK_DIM, 1, 1);
    for (int i = 0; i < KERNEL_INVOCATIONS; i++) {
        switch (TEST_KERNEL) {
        case 1:
            testKernel1 <<<gridDim, blockDim>>> ((float4 *)d_output, (float4 *)d_input);
            break;
        case 2:
            testKernel2 <<<gridDim, blockDim>>> ((float *)d_output, (float4 *)d_input);
            break;
        case 3:
            testKernel3 <<<gridDim, blockDim>>> ((float4 *)d_output, (float *)d_input);
            break;
        case 4:
            testKernel4 <<<gridDim, blockDim>>> ((float *)d_output, (float *)d_input);
            break;
        }
        hipDeviceSynchronize();
    }
    
    hipMemcpy(output, d_output, NUM_BYTES, hipMemcpyDeviceToHost);
    for (int i = 0; i < NUM_THREADS*4; i++) {
        if (output[i] != i) {
            printf("KERNEL=%d FAILED: elem #%d = %f\n", TEST_KERNEL, i, output[i]);
        }
    }
    
    free(input);
    free(output);
    hipFree(d_input);
    hipFree(d_output);
}

	.text
	.file	"float4_test.hip"
	.globl	_Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_ # -- Begin function _Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_
	.type	_Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_,@function
_Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_: # @_Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11testKernel1P15HIP_vector_typeIfLj4EES1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_, .Lfunc_end0-_Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE # -- Begin function _Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE
	.type	_Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE,@function
_Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE: # @_Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11testKernel2PfP15HIP_vector_typeIfLj4EE, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE, .Lfunc_end1-_Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf # -- Begin function _Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf
	.type	_Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf,@function
_Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf: # @_Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11testKernel3P15HIP_vector_typeIfLj4EEPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf, .Lfunc_end2-_Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__testKernel4PfS_ # -- Begin function _Z26__device_stub__testKernel4PfS_
	.type	_Z26__device_stub__testKernel4PfS_,@function
_Z26__device_stub__testKernel4PfS_:     # @_Z26__device_stub__testKernel4PfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11testKernel4PfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z26__device_stub__testKernel4PfS_, .Lfunc_end3-_Z26__device_stub__testKernel4PfS_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$16, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	xorl	%r15d, %r15d
	xorl	%edi, %edi
	callq	hipSetDevice
	movl	$131072, %edi                   # imm = 0x20000
	callq	malloc
	movq	%rax, %rbx
	movl	$131072, %edi                   # imm = 0x20000
	callq	malloc
	movq	%rax, %r14
	leaq	8(%rsp), %rdi
	movl	$131072, %esi                   # imm = 0x20000
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$131072, %esi                   # imm = 0x20000
	callq	hipMalloc
.LBB4_1:                                # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2ss	%r15d, %xmm0
	movss	%xmm0, (%rbx,%r15,4)
	incq	%r15
	cmpq	$32768, %r15                    # imm = 0x8000
	jne	.LBB4_1
# %bb.2:
	movabsq	$4294967360, %r15               # imm = 0x100000040
	movq	8(%rsp), %rdi
	movl	$131072, %edx                   # imm = 0x20000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$100, %ebp
	leaq	64(%r15), %r12
.LBB4_3:                                # =>This Inner Loop Header: Depth=1
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_5
# %bb.4:                                #   in Loop: Header=BB4_3 Depth=1
	movq	(%rsp), %rdi
	movq	8(%rsp), %rsi
	callq	_Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_
.LBB4_5:                                #   in Loop: Header=BB4_3 Depth=1
	callq	hipDeviceSynchronize
	decl	%ebp
	jne	.LBB4_3
# %bb.6:
	movq	(%rsp), %rsi
	movl	$131072, %edx                   # imm = 0x20000
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%r15d, %r15d
.LBB4_7:                                # =>This Inner Loop Header: Depth=1
	xorps	%xmm1, %xmm1
	cvtsi2ss	%r15d, %xmm1
	movss	(%r14,%r15,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	ucomiss	%xmm1, %xmm0
	jne	.LBB4_8
	jnp	.LBB4_9
.LBB4_8:                                #   in Loop: Header=BB4_7 Depth=1
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str, %edi
	movl	$1, %esi
	movl	%r15d, %edx
	movb	$1, %al
	callq	printf
.LBB4_9:                                #   in Loop: Header=BB4_7 Depth=1
	incq	%r15
	cmpq	$32768, %r15                    # imm = 0x8000
	jne	.LBB4_7
# %bb.10:
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$16, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11testKernel1P15HIP_vector_typeIfLj4EES1_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11testKernel2PfP15HIP_vector_typeIfLj4EE, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11testKernel3P15HIP_vector_typeIfLj4EEPf, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11testKernel4PfS_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z11testKernel1P15HIP_vector_typeIfLj4EES1_,@object # @_Z11testKernel1P15HIP_vector_typeIfLj4EES1_
	.section	.rodata,"a",@progbits
	.globl	_Z11testKernel1P15HIP_vector_typeIfLj4EES1_
	.p2align	3, 0x0
_Z11testKernel1P15HIP_vector_typeIfLj4EES1_:
	.quad	_Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_
	.size	_Z11testKernel1P15HIP_vector_typeIfLj4EES1_, 8

	.type	_Z11testKernel2PfP15HIP_vector_typeIfLj4EE,@object # @_Z11testKernel2PfP15HIP_vector_typeIfLj4EE
	.globl	_Z11testKernel2PfP15HIP_vector_typeIfLj4EE
	.p2align	3, 0x0
_Z11testKernel2PfP15HIP_vector_typeIfLj4EE:
	.quad	_Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE
	.size	_Z11testKernel2PfP15HIP_vector_typeIfLj4EE, 8

	.type	_Z11testKernel3P15HIP_vector_typeIfLj4EEPf,@object # @_Z11testKernel3P15HIP_vector_typeIfLj4EEPf
	.globl	_Z11testKernel3P15HIP_vector_typeIfLj4EEPf
	.p2align	3, 0x0
_Z11testKernel3P15HIP_vector_typeIfLj4EEPf:
	.quad	_Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf
	.size	_Z11testKernel3P15HIP_vector_typeIfLj4EEPf, 8

	.type	_Z11testKernel4PfS_,@object     # @_Z11testKernel4PfS_
	.globl	_Z11testKernel4PfS_
	.p2align	3, 0x0
_Z11testKernel4PfS_:
	.quad	_Z26__device_stub__testKernel4PfS_
	.size	_Z11testKernel4PfS_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"KERNEL=%d FAILED: elem #%d = %f\n"
	.size	.L.str, 33

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z11testKernel1P15HIP_vector_typeIfLj4EES1_"
	.size	.L__unnamed_1, 44

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z11testKernel2PfP15HIP_vector_typeIfLj4EE"
	.size	.L__unnamed_2, 43

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z11testKernel3P15HIP_vector_typeIfLj4EEPf"
	.size	.L__unnamed_3, 43

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z11testKernel4PfS_"
	.size	.L__unnamed_4, 20

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_
	.addrsig_sym _Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE
	.addrsig_sym _Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf
	.addrsig_sym _Z26__device_stub__testKernel4PfS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z11testKernel1P15HIP_vector_typeIfLj4EES1_
	.addrsig_sym _Z11testKernel2PfP15HIP_vector_typeIfLj4EE
	.addrsig_sym _Z11testKernel3P15HIP_vector_typeIfLj4EEPf
	.addrsig_sym _Z11testKernel4PfS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11testKernel1P15HIP_vector_typeIfLj4EES1_ ; -- Begin function _Z11testKernel1P15HIP_vector_typeIfLj4EES1_
	.globl	_Z11testKernel1P15HIP_vector_typeIfLj4EES1_
	.p2align	8
	.type	_Z11testKernel1P15HIP_vector_typeIfLj4EES1_,@function
_Z11testKernel1P15HIP_vector_typeIfLj4EES1_: ; @_Z11testKernel1P15HIP_vector_typeIfLj4EES1_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 4, v[1:2]
	v_add_co_u32 v0, vcc_lo, s2, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	global_load_b128 v[0:3], v[0:1], off
	s_waitcnt vmcnt(0)
	global_store_b128 v[4:5], v[0:3], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11testKernel1P15HIP_vector_typeIfLj4EES1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11testKernel1P15HIP_vector_typeIfLj4EES1_, .Lfunc_end0-_Z11testKernel1P15HIP_vector_typeIfLj4EES1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 120
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11testKernel2PfP15HIP_vector_typeIfLj4EE ; -- Begin function _Z11testKernel2PfP15HIP_vector_typeIfLj4EE
	.globl	_Z11testKernel2PfP15HIP_vector_typeIfLj4EE
	.p2align	8
	.type	_Z11testKernel2PfP15HIP_vector_typeIfLj4EE,@function
_Z11testKernel2PfP15HIP_vector_typeIfLj4EE: ; @_Z11testKernel2PfP15HIP_vector_typeIfLj4EE
; %bb.0:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshl_add_u32 v4, s15, 6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[0:1], 4, v[4:5]
	v_lshlrev_b32_e32 v4, 2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v5, 31, v4
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	global_load_b128 v[0:3], v[0:1], off
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b128 v[4:5], v[0:3], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11testKernel2PfP15HIP_vector_typeIfLj4EE
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z11testKernel2PfP15HIP_vector_typeIfLj4EE, .Lfunc_end1-_Z11testKernel2PfP15HIP_vector_typeIfLj4EE
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 116
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11testKernel3P15HIP_vector_typeIfLj4EEPf ; -- Begin function _Z11testKernel3P15HIP_vector_typeIfLj4EEPf
	.globl	_Z11testKernel3P15HIP_vector_typeIfLj4EEPf
	.p2align	8
	.type	_Z11testKernel3P15HIP_vector_typeIfLj4EEPf,@function
_Z11testKernel3P15HIP_vector_typeIfLj4EEPf: ; @_Z11testKernel3P15HIP_vector_typeIfLj4EEPf
; %bb.0:
	v_lshl_add_u32 v4, s15, 6, v0
	s_load_b128 s[0:3], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v0, 2, v4
	v_ashrrev_i32_e32 v5, 31, v4
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 4, v[4:5]
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	global_load_b128 v[0:3], v[0:1], off
	s_waitcnt vmcnt(0)
	global_store_b128 v[4:5], v[0:3], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11testKernel3P15HIP_vector_typeIfLj4EEPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z11testKernel3P15HIP_vector_typeIfLj4EEPf, .Lfunc_end2-_Z11testKernel3P15HIP_vector_typeIfLj4EEPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 120
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11testKernel4PfS_     ; -- Begin function _Z11testKernel4PfS_
	.globl	_Z11testKernel4PfS_
	.p2align	8
	.type	_Z11testKernel4PfS_,@function
_Z11testKernel4PfS_:                    ; @_Z11testKernel4PfS_
; %bb.0:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshl_add_u32 v0, s15, 6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v6, v[2:3], off
	v_add_co_u32 v4, vcc_lo, 0x8000, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v6, off
	global_load_b32 v8, v[4:5], off
	v_add_co_u32 v4, vcc_lo, 0x8000, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
	v_add_co_u32 v6, vcc_lo, 0x10000, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v3, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[4:5], v8, off
	global_load_b32 v6, v[6:7], off
	v_add_co_u32 v4, vcc_lo, 0x10000, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, 0x18000, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, 0x18000, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[4:5], v6, off
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11testKernel4PfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z11testKernel4PfS_, .Lfunc_end3-_Z11testKernel4PfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 252
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11testKernel1P15HIP_vector_typeIfLj4EES1_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11testKernel1P15HIP_vector_typeIfLj4EES1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11testKernel2PfP15HIP_vector_typeIfLj4EE
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11testKernel2PfP15HIP_vector_typeIfLj4EE.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11testKernel3P15HIP_vector_typeIfLj4EEPf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11testKernel3P15HIP_vector_typeIfLj4EEPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11testKernel4PfS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11testKernel4PfS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
