// Copyright 2016 Massachusetts Institute of Technology. See LICENSE file for details.
// http://docs.nvidia.com/cuda/samples/6_Advanced/reduction/doc/reduction.pdf

template <unsigned int blockSize, typename T, typename R>
__device__ void cuda_reduce(R reduce, size_t n, T *g_idata, T *g_odata, off_t incx, off_t incy, off_t incz, double a = 0) {
    extern __shared__ char vdata[];
    T* sdata = (T*) vdata;

    off_t grid_index = blockIdx.y*incy + blockIdx.z*incz;

    unsigned int tid = threadIdx.x;
    unsigned int i = blockIdx.x*(blockSize) + tid;
    unsigned int gridSize = blockSize*gridDim.x;

    if (i < n) {
        sdata[tid] = g_idata[incx*i + grid_index];
        i += gridSize;
    }

    while (i < n) {
        reduce(sdata[tid], g_idata[incx*i + grid_index]);
        i += gridSize;
    }

    __syncthreads();

    if (blockSize >= 512) { if (tid < 256 && tid + 256 < n) { reduce(sdata[tid], sdata[tid + 256]); } __syncthreads(); }
    if (blockSize >= 256) { if (tid < 128 && tid + 128 < n) { reduce(sdata[tid], sdata[tid + 128]); } __syncthreads(); }
    if (blockSize >= 128) { if (tid <  64 && tid +  64 < n) { reduce(sdata[tid], sdata[tid +  64]); } __syncthreads(); }
    if (tid < 32) {
        if (blockSize >=  64) { if (tid <  32 && tid + 32 < n) { reduce(sdata[tid], sdata[tid +  32]); } }
        if (blockSize >=  32) { if (tid <  16 && tid + 16 < n) { reduce(sdata[tid], sdata[tid +  16]); } }
        if (blockSize >=  16) { if (tid <   8 && tid +  8 < n) { reduce(sdata[tid], sdata[tid +   8]); } }
        if (blockSize >=   8) { if (tid <   4 && tid +  4 < n) { reduce(sdata[tid], sdata[tid +   4]); } }
        if (blockSize >=   4) { if (tid <   2 && tid +  2 < n) { reduce(sdata[tid], sdata[tid +   2]); } }
        if (blockSize >=   2) { if (tid <   1 && tid +  1 < n) { reduce(sdata[tid], sdata[tid +   1]); } }
    }

    if (tid == 0) {
        off_t o = blockIdx.x + gridDim.x*(blockIdx.y + gridDim.y*blockIdx.z);
        if (a == 0)
	    g_odata[o] = sdata[0];
	else
	    g_odata[o] = a*g_odata[o] + sdata[0];
    }
}

struct Sum { template<typename T> __device__ void operator() (T& acc, const T v) { acc += v; } };
struct Min { template<typename T> __device__ void operator() (T& acc, const T v) { if (v < acc) acc = v; } };
struct Max { template<typename T> __device__ void operator() (T& acc, const T v) { if (v > acc) acc = v; } };

extern "C" {
// Sum
  __global__ void cuda_sum_512_double(size_t n, double* g_idata, double* g_odata, double a, off_t incx, off_t incy, off_t incz) { cuda_reduce<512>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_256_double(size_t n, double* g_idata, double* g_odata, double a, off_t incx, off_t incy, off_t incz) { cuda_reduce<256>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_128_double(size_t n, double* g_idata, double* g_odata, double a, off_t incx, off_t incy, off_t incz) { cuda_reduce<128>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_64_double(size_t n, double* g_idata, double* g_odata, double a, off_t incx, off_t incy, off_t incz) { cuda_reduce<64>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_32_double(size_t n, double* g_idata, double* g_odata, double a, off_t incx, off_t incy, off_t incz) { cuda_reduce<32>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_16_double(size_t n, double* g_idata, double* g_odata, double a, off_t incx, off_t incy, off_t incz) { cuda_reduce<16>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_8_double(size_t n, double* g_idata, double* g_odata, double a, off_t incx, off_t incy, off_t incz) { cuda_reduce<8>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_4_double(size_t n, double* g_idata, double* g_odata, double a, off_t incx, off_t incy, off_t incz) { cuda_reduce<4>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_2_double(size_t n, double* g_idata, double* g_odata, double a, off_t incx, off_t incy, off_t incz) { cuda_reduce<2>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }

  __global__ void cuda_sum_512_float(size_t n, float* g_idata, float* g_odata, float a, off_t incx, off_t incy, off_t incz) { cuda_reduce<512>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_256_float(size_t n, float* g_idata, float* g_odata, float a, off_t incx, off_t incy, off_t incz) { cuda_reduce<256>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_128_float(size_t n, float* g_idata, float* g_odata, float a, off_t incx, off_t incy, off_t incz) { cuda_reduce<128>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_64_float(size_t n, float* g_idata, float* g_odata, float a, off_t incx, off_t incy, off_t incz) { cuda_reduce<64>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_32_float(size_t n, float* g_idata, float* g_odata, float a, off_t incx, off_t incy, off_t incz) { cuda_reduce<32>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_16_float(size_t n, float* g_idata, float* g_odata, float a, off_t incx, off_t incy, off_t incz) { cuda_reduce<16>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_8_float(size_t n, float* g_idata, float* g_odata, float a, off_t incx, off_t incy, off_t incz) { cuda_reduce<8>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_4_float(size_t n, float* g_idata, float* g_odata, float a, off_t incx, off_t incy, off_t incz) { cuda_reduce<4>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_2_float(size_t n, float* g_idata, float* g_odata, float a, off_t incx, off_t incy, off_t incz) { cuda_reduce<2>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }

// Max
  __global__ void cuda_maximum_512_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<512>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_256_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<256>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_128_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<128>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_64_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<64>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_32_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<32>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_16_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<16>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_8_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<8>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_4_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<4>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_2_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<2>(Max(), n, g_idata, g_odata, incx, incy, incz); }

  __global__ void cuda_maximum_512_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<512>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_256_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<256>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_128_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<128>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_64_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<64>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_32_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<32>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_16_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<16>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_8_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<8>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_4_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<4>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_2_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<2>(Max(), n, g_idata, g_odata, incx, incy, incz); }

// Min
  __global__ void cuda_minimum_512_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<512>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_256_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<256>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_128_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<128>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_64_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<64>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_32_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<32>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_16_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<16>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_8_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<8>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_4_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<4>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_2_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<2>(Min(), n, g_idata, g_odata, incx, incy, incz); }

  __global__ void cuda_minimum_512_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<512>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_256_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<256>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_128_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<128>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_64_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<64>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_32_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<32>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_16_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<16>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_8_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<8>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_4_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<4>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_2_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<2>(Min(), n, g_idata, g_odata, incx, incy, incz); }
}

	.file	"tmpxft_002b1838_00000000-6_cudaReduce.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2014:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2014:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, @function
_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0:
.LFB2261:
	.cfi_startproc
	jmp	cudaLaunchKernel@PLT
	.cfi_endproc
.LFE2261:
	.size	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, .-_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	.globl	_Z46__device_stub__Z19cuda_sum_512_doublemPdS_dlllmPdS_dlll
	.type	_Z46__device_stub__Z19cuda_sum_512_doublemPdS_dlllmPdS_dlll, @function
_Z46__device_stub__Z19cuda_sum_512_doublemPdS_dlllmPdS_dlll:
.LFB2036:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movsd	%xmm0, 32(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	cuda_sum_512_double(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L3:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	_Z46__device_stub__Z19cuda_sum_512_doublemPdS_dlllmPdS_dlll, .-_Z46__device_stub__Z19cuda_sum_512_doublemPdS_dlllmPdS_dlll
	.globl	cuda_sum_512_double
	.type	cuda_sum_512_double, @function
cuda_sum_512_double:
.LFB2037:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z19cuda_sum_512_doublemPdS_dlllmPdS_dlll
	.cfi_endproc
.LFE2037:
	.size	cuda_sum_512_double, .-cuda_sum_512_double
	.globl	_Z46__device_stub__Z19cuda_sum_256_doublemPdS_dlllmPdS_dlll
	.type	_Z46__device_stub__Z19cuda_sum_256_doublemPdS_dlllmPdS_dlll, @function
_Z46__device_stub__Z19cuda_sum_256_doublemPdS_dlllmPdS_dlll:
.LFB2038:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movsd	%xmm0, 32(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	cuda_sum_256_double(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L9:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2038:
	.size	_Z46__device_stub__Z19cuda_sum_256_doublemPdS_dlllmPdS_dlll, .-_Z46__device_stub__Z19cuda_sum_256_doublemPdS_dlllmPdS_dlll
	.globl	cuda_sum_256_double
	.type	cuda_sum_256_double, @function
cuda_sum_256_double:
.LFB2039:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z19cuda_sum_256_doublemPdS_dlllmPdS_dlll
	.cfi_endproc
.LFE2039:
	.size	cuda_sum_256_double, .-cuda_sum_256_double
	.globl	_Z46__device_stub__Z19cuda_sum_128_doublemPdS_dlllmPdS_dlll
	.type	_Z46__device_stub__Z19cuda_sum_128_doublemPdS_dlllmPdS_dlll, @function
_Z46__device_stub__Z19cuda_sum_128_doublemPdS_dlllmPdS_dlll:
.LFB2040:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movsd	%xmm0, 32(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	cuda_sum_128_double(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L14:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	_Z46__device_stub__Z19cuda_sum_128_doublemPdS_dlllmPdS_dlll, .-_Z46__device_stub__Z19cuda_sum_128_doublemPdS_dlllmPdS_dlll
	.globl	cuda_sum_128_double
	.type	cuda_sum_128_double, @function
cuda_sum_128_double:
.LFB2041:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z19cuda_sum_128_doublemPdS_dlllmPdS_dlll
	.cfi_endproc
.LFE2041:
	.size	cuda_sum_128_double, .-cuda_sum_128_double
	.globl	_Z45__device_stub__Z18cuda_sum_64_doublemPdS_dlllmPdS_dlll
	.type	_Z45__device_stub__Z18cuda_sum_64_doublemPdS_dlllmPdS_dlll, @function
_Z45__device_stub__Z18cuda_sum_64_doublemPdS_dlllmPdS_dlll:
.LFB2042:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movsd	%xmm0, 32(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	cuda_sum_64_double(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L19:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2042:
	.size	_Z45__device_stub__Z18cuda_sum_64_doublemPdS_dlllmPdS_dlll, .-_Z45__device_stub__Z18cuda_sum_64_doublemPdS_dlllmPdS_dlll
	.globl	cuda_sum_64_double
	.type	cuda_sum_64_double, @function
cuda_sum_64_double:
.LFB2043:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z18cuda_sum_64_doublemPdS_dlllmPdS_dlll
	.cfi_endproc
.LFE2043:
	.size	cuda_sum_64_double, .-cuda_sum_64_double
	.globl	_Z45__device_stub__Z18cuda_sum_32_doublemPdS_dlllmPdS_dlll
	.type	_Z45__device_stub__Z18cuda_sum_32_doublemPdS_dlllmPdS_dlll, @function
_Z45__device_stub__Z18cuda_sum_32_doublemPdS_dlllmPdS_dlll:
.LFB2044:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movsd	%xmm0, 32(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	cuda_sum_32_double(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L24:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2044:
	.size	_Z45__device_stub__Z18cuda_sum_32_doublemPdS_dlllmPdS_dlll, .-_Z45__device_stub__Z18cuda_sum_32_doublemPdS_dlllmPdS_dlll
	.globl	cuda_sum_32_double
	.type	cuda_sum_32_double, @function
cuda_sum_32_double:
.LFB2045:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z18cuda_sum_32_doublemPdS_dlllmPdS_dlll
	.cfi_endproc
.LFE2045:
	.size	cuda_sum_32_double, .-cuda_sum_32_double
	.globl	_Z45__device_stub__Z18cuda_sum_16_doublemPdS_dlllmPdS_dlll
	.type	_Z45__device_stub__Z18cuda_sum_16_doublemPdS_dlllmPdS_dlll, @function
_Z45__device_stub__Z18cuda_sum_16_doublemPdS_dlllmPdS_dlll:
.LFB2046:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movsd	%xmm0, 32(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	cuda_sum_16_double(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L29:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2046:
	.size	_Z45__device_stub__Z18cuda_sum_16_doublemPdS_dlllmPdS_dlll, .-_Z45__device_stub__Z18cuda_sum_16_doublemPdS_dlllmPdS_dlll
	.globl	cuda_sum_16_double
	.type	cuda_sum_16_double, @function
cuda_sum_16_double:
.LFB2047:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z18cuda_sum_16_doublemPdS_dlllmPdS_dlll
	.cfi_endproc
.LFE2047:
	.size	cuda_sum_16_double, .-cuda_sum_16_double
	.globl	_Z44__device_stub__Z17cuda_sum_8_doublemPdS_dlllmPdS_dlll
	.type	_Z44__device_stub__Z17cuda_sum_8_doublemPdS_dlllmPdS_dlll, @function
_Z44__device_stub__Z17cuda_sum_8_doublemPdS_dlllmPdS_dlll:
.LFB2048:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movsd	%xmm0, 32(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	cuda_sum_8_double(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L34:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2048:
	.size	_Z44__device_stub__Z17cuda_sum_8_doublemPdS_dlllmPdS_dlll, .-_Z44__device_stub__Z17cuda_sum_8_doublemPdS_dlllmPdS_dlll
	.globl	cuda_sum_8_double
	.type	cuda_sum_8_double, @function
cuda_sum_8_double:
.LFB2049:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z17cuda_sum_8_doublemPdS_dlllmPdS_dlll
	.cfi_endproc
.LFE2049:
	.size	cuda_sum_8_double, .-cuda_sum_8_double
	.globl	_Z44__device_stub__Z17cuda_sum_4_doublemPdS_dlllmPdS_dlll
	.type	_Z44__device_stub__Z17cuda_sum_4_doublemPdS_dlllmPdS_dlll, @function
_Z44__device_stub__Z17cuda_sum_4_doublemPdS_dlllmPdS_dlll:
.LFB2050:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movsd	%xmm0, 32(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L39
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	cuda_sum_4_double(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L39:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L41
	call	__stack_chk_fail@PLT
.L41:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2050:
	.size	_Z44__device_stub__Z17cuda_sum_4_doublemPdS_dlllmPdS_dlll, .-_Z44__device_stub__Z17cuda_sum_4_doublemPdS_dlllmPdS_dlll
	.globl	cuda_sum_4_double
	.type	cuda_sum_4_double, @function
cuda_sum_4_double:
.LFB2051:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z17cuda_sum_4_doublemPdS_dlllmPdS_dlll
	.cfi_endproc
.LFE2051:
	.size	cuda_sum_4_double, .-cuda_sum_4_double
	.globl	_Z44__device_stub__Z17cuda_sum_2_doublemPdS_dlllmPdS_dlll
	.type	_Z44__device_stub__Z17cuda_sum_2_doublemPdS_dlllmPdS_dlll, @function
_Z44__device_stub__Z17cuda_sum_2_doublemPdS_dlllmPdS_dlll:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movsd	%xmm0, 32(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L44
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	cuda_sum_2_double(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L44:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L46
	call	__stack_chk_fail@PLT
.L46:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z44__device_stub__Z17cuda_sum_2_doublemPdS_dlllmPdS_dlll, .-_Z44__device_stub__Z17cuda_sum_2_doublemPdS_dlllmPdS_dlll
	.globl	cuda_sum_2_double
	.type	cuda_sum_2_double, @function
cuda_sum_2_double:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z17cuda_sum_2_doublemPdS_dlllmPdS_dlll
	.cfi_endproc
.LFE2053:
	.size	cuda_sum_2_double, .-cuda_sum_2_double
	.globl	_Z45__device_stub__Z18cuda_sum_512_floatmPfS_flllmPfS_flll
	.type	_Z45__device_stub__Z18cuda_sum_512_floatmPfS_flllmPfS_flll, @function
_Z45__device_stub__Z18cuda_sum_512_floatmPfS_flllmPfS_flll:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movss	%xmm0, 36(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L49
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	cuda_sum_512_float(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L49:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L51
	call	__stack_chk_fail@PLT
.L51:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z45__device_stub__Z18cuda_sum_512_floatmPfS_flllmPfS_flll, .-_Z45__device_stub__Z18cuda_sum_512_floatmPfS_flllmPfS_flll
	.globl	cuda_sum_512_float
	.type	cuda_sum_512_float, @function
cuda_sum_512_float:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z18cuda_sum_512_floatmPfS_flllmPfS_flll
	.cfi_endproc
.LFE2055:
	.size	cuda_sum_512_float, .-cuda_sum_512_float
	.globl	_Z45__device_stub__Z18cuda_sum_256_floatmPfS_flllmPfS_flll
	.type	_Z45__device_stub__Z18cuda_sum_256_floatmPfS_flllmPfS_flll, @function
_Z45__device_stub__Z18cuda_sum_256_floatmPfS_flllmPfS_flll:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movss	%xmm0, 36(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	cuda_sum_256_float(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L54:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L56
	call	__stack_chk_fail@PLT
.L56:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z45__device_stub__Z18cuda_sum_256_floatmPfS_flllmPfS_flll, .-_Z45__device_stub__Z18cuda_sum_256_floatmPfS_flllmPfS_flll
	.globl	cuda_sum_256_float
	.type	cuda_sum_256_float, @function
cuda_sum_256_float:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z18cuda_sum_256_floatmPfS_flllmPfS_flll
	.cfi_endproc
.LFE2057:
	.size	cuda_sum_256_float, .-cuda_sum_256_float
	.globl	_Z45__device_stub__Z18cuda_sum_128_floatmPfS_flllmPfS_flll
	.type	_Z45__device_stub__Z18cuda_sum_128_floatmPfS_flllmPfS_flll, @function
_Z45__device_stub__Z18cuda_sum_128_floatmPfS_flllmPfS_flll:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movss	%xmm0, 36(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L59
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	cuda_sum_128_float(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L59:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L61
	call	__stack_chk_fail@PLT
.L61:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z45__device_stub__Z18cuda_sum_128_floatmPfS_flllmPfS_flll, .-_Z45__device_stub__Z18cuda_sum_128_floatmPfS_flllmPfS_flll
	.globl	cuda_sum_128_float
	.type	cuda_sum_128_float, @function
cuda_sum_128_float:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z18cuda_sum_128_floatmPfS_flllmPfS_flll
	.cfi_endproc
.LFE2059:
	.size	cuda_sum_128_float, .-cuda_sum_128_float
	.globl	_Z44__device_stub__Z17cuda_sum_64_floatmPfS_flllmPfS_flll
	.type	_Z44__device_stub__Z17cuda_sum_64_floatmPfS_flllmPfS_flll, @function
_Z44__device_stub__Z17cuda_sum_64_floatmPfS_flllmPfS_flll:
.LFB2060:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movss	%xmm0, 36(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L64
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	cuda_sum_64_float(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L64:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L66
	call	__stack_chk_fail@PLT
.L66:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2060:
	.size	_Z44__device_stub__Z17cuda_sum_64_floatmPfS_flllmPfS_flll, .-_Z44__device_stub__Z17cuda_sum_64_floatmPfS_flllmPfS_flll
	.globl	cuda_sum_64_float
	.type	cuda_sum_64_float, @function
cuda_sum_64_float:
.LFB2061:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z17cuda_sum_64_floatmPfS_flllmPfS_flll
	.cfi_endproc
.LFE2061:
	.size	cuda_sum_64_float, .-cuda_sum_64_float
	.globl	_Z44__device_stub__Z17cuda_sum_32_floatmPfS_flllmPfS_flll
	.type	_Z44__device_stub__Z17cuda_sum_32_floatmPfS_flllmPfS_flll, @function
_Z44__device_stub__Z17cuda_sum_32_floatmPfS_flllmPfS_flll:
.LFB2062:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movss	%xmm0, 36(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L69
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	cuda_sum_32_float(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L69:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L71
	call	__stack_chk_fail@PLT
.L71:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2062:
	.size	_Z44__device_stub__Z17cuda_sum_32_floatmPfS_flllmPfS_flll, .-_Z44__device_stub__Z17cuda_sum_32_floatmPfS_flllmPfS_flll
	.globl	cuda_sum_32_float
	.type	cuda_sum_32_float, @function
cuda_sum_32_float:
.LFB2063:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z17cuda_sum_32_floatmPfS_flllmPfS_flll
	.cfi_endproc
.LFE2063:
	.size	cuda_sum_32_float, .-cuda_sum_32_float
	.globl	_Z44__device_stub__Z17cuda_sum_16_floatmPfS_flllmPfS_flll
	.type	_Z44__device_stub__Z17cuda_sum_16_floatmPfS_flllmPfS_flll, @function
_Z44__device_stub__Z17cuda_sum_16_floatmPfS_flllmPfS_flll:
.LFB2064:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movss	%xmm0, 36(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L74
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	cuda_sum_16_float(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L74:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L76
	call	__stack_chk_fail@PLT
.L76:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2064:
	.size	_Z44__device_stub__Z17cuda_sum_16_floatmPfS_flllmPfS_flll, .-_Z44__device_stub__Z17cuda_sum_16_floatmPfS_flllmPfS_flll
	.globl	cuda_sum_16_float
	.type	cuda_sum_16_float, @function
cuda_sum_16_float:
.LFB2065:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z17cuda_sum_16_floatmPfS_flllmPfS_flll
	.cfi_endproc
.LFE2065:
	.size	cuda_sum_16_float, .-cuda_sum_16_float
	.globl	_Z43__device_stub__Z16cuda_sum_8_floatmPfS_flllmPfS_flll
	.type	_Z43__device_stub__Z16cuda_sum_8_floatmPfS_flllmPfS_flll, @function
_Z43__device_stub__Z16cuda_sum_8_floatmPfS_flllmPfS_flll:
.LFB2066:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movss	%xmm0, 36(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L79
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	cuda_sum_8_float(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L79:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L81
	call	__stack_chk_fail@PLT
.L81:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2066:
	.size	_Z43__device_stub__Z16cuda_sum_8_floatmPfS_flllmPfS_flll, .-_Z43__device_stub__Z16cuda_sum_8_floatmPfS_flllmPfS_flll
	.globl	cuda_sum_8_float
	.type	cuda_sum_8_float, @function
cuda_sum_8_float:
.LFB2067:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z16cuda_sum_8_floatmPfS_flllmPfS_flll
	.cfi_endproc
.LFE2067:
	.size	cuda_sum_8_float, .-cuda_sum_8_float
	.globl	_Z43__device_stub__Z16cuda_sum_4_floatmPfS_flllmPfS_flll
	.type	_Z43__device_stub__Z16cuda_sum_4_floatmPfS_flllmPfS_flll, @function
_Z43__device_stub__Z16cuda_sum_4_floatmPfS_flllmPfS_flll:
.LFB2068:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movss	%xmm0, 36(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L84
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	cuda_sum_4_float(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L84:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L86
	call	__stack_chk_fail@PLT
.L86:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2068:
	.size	_Z43__device_stub__Z16cuda_sum_4_floatmPfS_flllmPfS_flll, .-_Z43__device_stub__Z16cuda_sum_4_floatmPfS_flllmPfS_flll
	.globl	cuda_sum_4_float
	.type	cuda_sum_4_float, @function
cuda_sum_4_float:
.LFB2069:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z16cuda_sum_4_floatmPfS_flllmPfS_flll
	.cfi_endproc
.LFE2069:
	.size	cuda_sum_4_float, .-cuda_sum_4_float
	.globl	_Z43__device_stub__Z16cuda_sum_2_floatmPfS_flllmPfS_flll
	.type	_Z43__device_stub__Z16cuda_sum_2_floatmPfS_flllmPfS_flll, @function
_Z43__device_stub__Z16cuda_sum_2_floatmPfS_flllmPfS_flll:
.LFB2070:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movss	%xmm0, 36(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L89
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	cuda_sum_2_float(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L89:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L91
	call	__stack_chk_fail@PLT
.L91:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2070:
	.size	_Z43__device_stub__Z16cuda_sum_2_floatmPfS_flllmPfS_flll, .-_Z43__device_stub__Z16cuda_sum_2_floatmPfS_flllmPfS_flll
	.globl	cuda_sum_2_float
	.type	cuda_sum_2_float, @function
cuda_sum_2_float:
.LFB2071:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z16cuda_sum_2_floatmPfS_flllmPfS_flll
	.cfi_endproc
.LFE2071:
	.size	cuda_sum_2_float, .-cuda_sum_2_float
	.globl	_Z49__device_stub__Z23cuda_maximum_512_doublemPdS_lllmPdS_lll
	.type	_Z49__device_stub__Z23cuda_maximum_512_doublemPdS_lllmPdS_lll, @function
_Z49__device_stub__Z23cuda_maximum_512_doublemPdS_lllmPdS_lll:
.LFB2072:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L94
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_maximum_512_double(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L94:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L96
	call	__stack_chk_fail@PLT
.L96:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2072:
	.size	_Z49__device_stub__Z23cuda_maximum_512_doublemPdS_lllmPdS_lll, .-_Z49__device_stub__Z23cuda_maximum_512_doublemPdS_lllmPdS_lll
	.globl	cuda_maximum_512_double
	.type	cuda_maximum_512_double, @function
cuda_maximum_512_double:
.LFB2073:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z23cuda_maximum_512_doublemPdS_lllmPdS_lll
	.cfi_endproc
.LFE2073:
	.size	cuda_maximum_512_double, .-cuda_maximum_512_double
	.globl	_Z49__device_stub__Z23cuda_maximum_256_doublemPdS_lllmPdS_lll
	.type	_Z49__device_stub__Z23cuda_maximum_256_doublemPdS_lllmPdS_lll, @function
_Z49__device_stub__Z23cuda_maximum_256_doublemPdS_lllmPdS_lll:
.LFB2074:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L99
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_maximum_256_double(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L99:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L101
	call	__stack_chk_fail@PLT
.L101:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2074:
	.size	_Z49__device_stub__Z23cuda_maximum_256_doublemPdS_lllmPdS_lll, .-_Z49__device_stub__Z23cuda_maximum_256_doublemPdS_lllmPdS_lll
	.globl	cuda_maximum_256_double
	.type	cuda_maximum_256_double, @function
cuda_maximum_256_double:
.LFB2075:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z23cuda_maximum_256_doublemPdS_lllmPdS_lll
	.cfi_endproc
.LFE2075:
	.size	cuda_maximum_256_double, .-cuda_maximum_256_double
	.globl	_Z49__device_stub__Z23cuda_maximum_128_doublemPdS_lllmPdS_lll
	.type	_Z49__device_stub__Z23cuda_maximum_128_doublemPdS_lllmPdS_lll, @function
_Z49__device_stub__Z23cuda_maximum_128_doublemPdS_lllmPdS_lll:
.LFB2076:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L104
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_maximum_128_double(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L104:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L106
	call	__stack_chk_fail@PLT
.L106:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2076:
	.size	_Z49__device_stub__Z23cuda_maximum_128_doublemPdS_lllmPdS_lll, .-_Z49__device_stub__Z23cuda_maximum_128_doublemPdS_lllmPdS_lll
	.globl	cuda_maximum_128_double
	.type	cuda_maximum_128_double, @function
cuda_maximum_128_double:
.LFB2077:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z23cuda_maximum_128_doublemPdS_lllmPdS_lll
	.cfi_endproc
.LFE2077:
	.size	cuda_maximum_128_double, .-cuda_maximum_128_double
	.globl	_Z48__device_stub__Z22cuda_maximum_64_doublemPdS_lllmPdS_lll
	.type	_Z48__device_stub__Z22cuda_maximum_64_doublemPdS_lllmPdS_lll, @function
_Z48__device_stub__Z22cuda_maximum_64_doublemPdS_lllmPdS_lll:
.LFB2078:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L109
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_maximum_64_double(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L109:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L111
	call	__stack_chk_fail@PLT
.L111:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2078:
	.size	_Z48__device_stub__Z22cuda_maximum_64_doublemPdS_lllmPdS_lll, .-_Z48__device_stub__Z22cuda_maximum_64_doublemPdS_lllmPdS_lll
	.globl	cuda_maximum_64_double
	.type	cuda_maximum_64_double, @function
cuda_maximum_64_double:
.LFB2079:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z22cuda_maximum_64_doublemPdS_lllmPdS_lll
	.cfi_endproc
.LFE2079:
	.size	cuda_maximum_64_double, .-cuda_maximum_64_double
	.globl	_Z48__device_stub__Z22cuda_maximum_32_doublemPdS_lllmPdS_lll
	.type	_Z48__device_stub__Z22cuda_maximum_32_doublemPdS_lllmPdS_lll, @function
_Z48__device_stub__Z22cuda_maximum_32_doublemPdS_lllmPdS_lll:
.LFB2080:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L114
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_maximum_32_double(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L114:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L116
	call	__stack_chk_fail@PLT
.L116:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2080:
	.size	_Z48__device_stub__Z22cuda_maximum_32_doublemPdS_lllmPdS_lll, .-_Z48__device_stub__Z22cuda_maximum_32_doublemPdS_lllmPdS_lll
	.globl	cuda_maximum_32_double
	.type	cuda_maximum_32_double, @function
cuda_maximum_32_double:
.LFB2081:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z22cuda_maximum_32_doublemPdS_lllmPdS_lll
	.cfi_endproc
.LFE2081:
	.size	cuda_maximum_32_double, .-cuda_maximum_32_double
	.globl	_Z48__device_stub__Z22cuda_maximum_16_doublemPdS_lllmPdS_lll
	.type	_Z48__device_stub__Z22cuda_maximum_16_doublemPdS_lllmPdS_lll, @function
_Z48__device_stub__Z22cuda_maximum_16_doublemPdS_lllmPdS_lll:
.LFB2082:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L119
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_maximum_16_double(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L119:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L121
	call	__stack_chk_fail@PLT
.L121:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2082:
	.size	_Z48__device_stub__Z22cuda_maximum_16_doublemPdS_lllmPdS_lll, .-_Z48__device_stub__Z22cuda_maximum_16_doublemPdS_lllmPdS_lll
	.globl	cuda_maximum_16_double
	.type	cuda_maximum_16_double, @function
cuda_maximum_16_double:
.LFB2083:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z22cuda_maximum_16_doublemPdS_lllmPdS_lll
	.cfi_endproc
.LFE2083:
	.size	cuda_maximum_16_double, .-cuda_maximum_16_double
	.globl	_Z47__device_stub__Z21cuda_maximum_8_doublemPdS_lllmPdS_lll
	.type	_Z47__device_stub__Z21cuda_maximum_8_doublemPdS_lllmPdS_lll, @function
_Z47__device_stub__Z21cuda_maximum_8_doublemPdS_lllmPdS_lll:
.LFB2084:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L124
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_maximum_8_double(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L124:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L126
	call	__stack_chk_fail@PLT
.L126:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2084:
	.size	_Z47__device_stub__Z21cuda_maximum_8_doublemPdS_lllmPdS_lll, .-_Z47__device_stub__Z21cuda_maximum_8_doublemPdS_lllmPdS_lll
	.globl	cuda_maximum_8_double
	.type	cuda_maximum_8_double, @function
cuda_maximum_8_double:
.LFB2085:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z21cuda_maximum_8_doublemPdS_lllmPdS_lll
	.cfi_endproc
.LFE2085:
	.size	cuda_maximum_8_double, .-cuda_maximum_8_double
	.globl	_Z47__device_stub__Z21cuda_maximum_4_doublemPdS_lllmPdS_lll
	.type	_Z47__device_stub__Z21cuda_maximum_4_doublemPdS_lllmPdS_lll, @function
_Z47__device_stub__Z21cuda_maximum_4_doublemPdS_lllmPdS_lll:
.LFB2086:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L129
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_maximum_4_double(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L129:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L131
	call	__stack_chk_fail@PLT
.L131:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2086:
	.size	_Z47__device_stub__Z21cuda_maximum_4_doublemPdS_lllmPdS_lll, .-_Z47__device_stub__Z21cuda_maximum_4_doublemPdS_lllmPdS_lll
	.globl	cuda_maximum_4_double
	.type	cuda_maximum_4_double, @function
cuda_maximum_4_double:
.LFB2087:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z21cuda_maximum_4_doublemPdS_lllmPdS_lll
	.cfi_endproc
.LFE2087:
	.size	cuda_maximum_4_double, .-cuda_maximum_4_double
	.globl	_Z47__device_stub__Z21cuda_maximum_2_doublemPdS_lllmPdS_lll
	.type	_Z47__device_stub__Z21cuda_maximum_2_doublemPdS_lllmPdS_lll, @function
_Z47__device_stub__Z21cuda_maximum_2_doublemPdS_lllmPdS_lll:
.LFB2088:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L134
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_maximum_2_double(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L134:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L136
	call	__stack_chk_fail@PLT
.L136:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2088:
	.size	_Z47__device_stub__Z21cuda_maximum_2_doublemPdS_lllmPdS_lll, .-_Z47__device_stub__Z21cuda_maximum_2_doublemPdS_lllmPdS_lll
	.globl	cuda_maximum_2_double
	.type	cuda_maximum_2_double, @function
cuda_maximum_2_double:
.LFB2089:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z21cuda_maximum_2_doublemPdS_lllmPdS_lll
	.cfi_endproc
.LFE2089:
	.size	cuda_maximum_2_double, .-cuda_maximum_2_double
	.globl	_Z48__device_stub__Z22cuda_maximum_512_floatmPfS_lllmPfS_lll
	.type	_Z48__device_stub__Z22cuda_maximum_512_floatmPfS_lllmPfS_lll, @function
_Z48__device_stub__Z22cuda_maximum_512_floatmPfS_lllmPfS_lll:
.LFB2090:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L139
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_maximum_512_float(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L139:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L141
	call	__stack_chk_fail@PLT
.L141:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2090:
	.size	_Z48__device_stub__Z22cuda_maximum_512_floatmPfS_lllmPfS_lll, .-_Z48__device_stub__Z22cuda_maximum_512_floatmPfS_lllmPfS_lll
	.globl	cuda_maximum_512_float
	.type	cuda_maximum_512_float, @function
cuda_maximum_512_float:
.LFB2091:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z22cuda_maximum_512_floatmPfS_lllmPfS_lll
	.cfi_endproc
.LFE2091:
	.size	cuda_maximum_512_float, .-cuda_maximum_512_float
	.globl	_Z48__device_stub__Z22cuda_maximum_256_floatmPfS_lllmPfS_lll
	.type	_Z48__device_stub__Z22cuda_maximum_256_floatmPfS_lllmPfS_lll, @function
_Z48__device_stub__Z22cuda_maximum_256_floatmPfS_lllmPfS_lll:
.LFB2092:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L144
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_maximum_256_float(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L144:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L146
	call	__stack_chk_fail@PLT
.L146:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2092:
	.size	_Z48__device_stub__Z22cuda_maximum_256_floatmPfS_lllmPfS_lll, .-_Z48__device_stub__Z22cuda_maximum_256_floatmPfS_lllmPfS_lll
	.globl	cuda_maximum_256_float
	.type	cuda_maximum_256_float, @function
cuda_maximum_256_float:
.LFB2093:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z22cuda_maximum_256_floatmPfS_lllmPfS_lll
	.cfi_endproc
.LFE2093:
	.size	cuda_maximum_256_float, .-cuda_maximum_256_float
	.globl	_Z48__device_stub__Z22cuda_maximum_128_floatmPfS_lllmPfS_lll
	.type	_Z48__device_stub__Z22cuda_maximum_128_floatmPfS_lllmPfS_lll, @function
_Z48__device_stub__Z22cuda_maximum_128_floatmPfS_lllmPfS_lll:
.LFB2094:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L149
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_maximum_128_float(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L149:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L151
	call	__stack_chk_fail@PLT
.L151:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2094:
	.size	_Z48__device_stub__Z22cuda_maximum_128_floatmPfS_lllmPfS_lll, .-_Z48__device_stub__Z22cuda_maximum_128_floatmPfS_lllmPfS_lll
	.globl	cuda_maximum_128_float
	.type	cuda_maximum_128_float, @function
cuda_maximum_128_float:
.LFB2095:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z22cuda_maximum_128_floatmPfS_lllmPfS_lll
	.cfi_endproc
.LFE2095:
	.size	cuda_maximum_128_float, .-cuda_maximum_128_float
	.globl	_Z47__device_stub__Z21cuda_maximum_64_floatmPfS_lllmPfS_lll
	.type	_Z47__device_stub__Z21cuda_maximum_64_floatmPfS_lllmPfS_lll, @function
_Z47__device_stub__Z21cuda_maximum_64_floatmPfS_lllmPfS_lll:
.LFB2096:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L154
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_maximum_64_float(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L154:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L156
	call	__stack_chk_fail@PLT
.L156:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2096:
	.size	_Z47__device_stub__Z21cuda_maximum_64_floatmPfS_lllmPfS_lll, .-_Z47__device_stub__Z21cuda_maximum_64_floatmPfS_lllmPfS_lll
	.globl	cuda_maximum_64_float
	.type	cuda_maximum_64_float, @function
cuda_maximum_64_float:
.LFB2097:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z21cuda_maximum_64_floatmPfS_lllmPfS_lll
	.cfi_endproc
.LFE2097:
	.size	cuda_maximum_64_float, .-cuda_maximum_64_float
	.globl	_Z47__device_stub__Z21cuda_maximum_32_floatmPfS_lllmPfS_lll
	.type	_Z47__device_stub__Z21cuda_maximum_32_floatmPfS_lllmPfS_lll, @function
_Z47__device_stub__Z21cuda_maximum_32_floatmPfS_lllmPfS_lll:
.LFB2098:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L159
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_maximum_32_float(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L159:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L161
	call	__stack_chk_fail@PLT
.L161:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2098:
	.size	_Z47__device_stub__Z21cuda_maximum_32_floatmPfS_lllmPfS_lll, .-_Z47__device_stub__Z21cuda_maximum_32_floatmPfS_lllmPfS_lll
	.globl	cuda_maximum_32_float
	.type	cuda_maximum_32_float, @function
cuda_maximum_32_float:
.LFB2099:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z21cuda_maximum_32_floatmPfS_lllmPfS_lll
	.cfi_endproc
.LFE2099:
	.size	cuda_maximum_32_float, .-cuda_maximum_32_float
	.globl	_Z47__device_stub__Z21cuda_maximum_16_floatmPfS_lllmPfS_lll
	.type	_Z47__device_stub__Z21cuda_maximum_16_floatmPfS_lllmPfS_lll, @function
_Z47__device_stub__Z21cuda_maximum_16_floatmPfS_lllmPfS_lll:
.LFB2100:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L164
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_maximum_16_float(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L164:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L166
	call	__stack_chk_fail@PLT
.L166:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2100:
	.size	_Z47__device_stub__Z21cuda_maximum_16_floatmPfS_lllmPfS_lll, .-_Z47__device_stub__Z21cuda_maximum_16_floatmPfS_lllmPfS_lll
	.globl	cuda_maximum_16_float
	.type	cuda_maximum_16_float, @function
cuda_maximum_16_float:
.LFB2101:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z21cuda_maximum_16_floatmPfS_lllmPfS_lll
	.cfi_endproc
.LFE2101:
	.size	cuda_maximum_16_float, .-cuda_maximum_16_float
	.globl	_Z46__device_stub__Z20cuda_maximum_8_floatmPfS_lllmPfS_lll
	.type	_Z46__device_stub__Z20cuda_maximum_8_floatmPfS_lllmPfS_lll, @function
_Z46__device_stub__Z20cuda_maximum_8_floatmPfS_lllmPfS_lll:
.LFB2102:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L169
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_maximum_8_float(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L169:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L171
	call	__stack_chk_fail@PLT
.L171:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2102:
	.size	_Z46__device_stub__Z20cuda_maximum_8_floatmPfS_lllmPfS_lll, .-_Z46__device_stub__Z20cuda_maximum_8_floatmPfS_lllmPfS_lll
	.globl	cuda_maximum_8_float
	.type	cuda_maximum_8_float, @function
cuda_maximum_8_float:
.LFB2103:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z20cuda_maximum_8_floatmPfS_lllmPfS_lll
	.cfi_endproc
.LFE2103:
	.size	cuda_maximum_8_float, .-cuda_maximum_8_float
	.globl	_Z46__device_stub__Z20cuda_maximum_4_floatmPfS_lllmPfS_lll
	.type	_Z46__device_stub__Z20cuda_maximum_4_floatmPfS_lllmPfS_lll, @function
_Z46__device_stub__Z20cuda_maximum_4_floatmPfS_lllmPfS_lll:
.LFB2104:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L174
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_maximum_4_float(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L174:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L176
	call	__stack_chk_fail@PLT
.L176:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2104:
	.size	_Z46__device_stub__Z20cuda_maximum_4_floatmPfS_lllmPfS_lll, .-_Z46__device_stub__Z20cuda_maximum_4_floatmPfS_lllmPfS_lll
	.globl	cuda_maximum_4_float
	.type	cuda_maximum_4_float, @function
cuda_maximum_4_float:
.LFB2105:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z20cuda_maximum_4_floatmPfS_lllmPfS_lll
	.cfi_endproc
.LFE2105:
	.size	cuda_maximum_4_float, .-cuda_maximum_4_float
	.globl	_Z46__device_stub__Z20cuda_maximum_2_floatmPfS_lllmPfS_lll
	.type	_Z46__device_stub__Z20cuda_maximum_2_floatmPfS_lllmPfS_lll, @function
_Z46__device_stub__Z20cuda_maximum_2_floatmPfS_lllmPfS_lll:
.LFB2106:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L179
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_maximum_2_float(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L179:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L181
	call	__stack_chk_fail@PLT
.L181:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2106:
	.size	_Z46__device_stub__Z20cuda_maximum_2_floatmPfS_lllmPfS_lll, .-_Z46__device_stub__Z20cuda_maximum_2_floatmPfS_lllmPfS_lll
	.globl	cuda_maximum_2_float
	.type	cuda_maximum_2_float, @function
cuda_maximum_2_float:
.LFB2107:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z20cuda_maximum_2_floatmPfS_lllmPfS_lll
	.cfi_endproc
.LFE2107:
	.size	cuda_maximum_2_float, .-cuda_maximum_2_float
	.globl	_Z49__device_stub__Z23cuda_minimum_512_doublemPdS_lllmPdS_lll
	.type	_Z49__device_stub__Z23cuda_minimum_512_doublemPdS_lllmPdS_lll, @function
_Z49__device_stub__Z23cuda_minimum_512_doublemPdS_lllmPdS_lll:
.LFB2108:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L184
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_minimum_512_double(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L184:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L186
	call	__stack_chk_fail@PLT
.L186:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2108:
	.size	_Z49__device_stub__Z23cuda_minimum_512_doublemPdS_lllmPdS_lll, .-_Z49__device_stub__Z23cuda_minimum_512_doublemPdS_lllmPdS_lll
	.globl	cuda_minimum_512_double
	.type	cuda_minimum_512_double, @function
cuda_minimum_512_double:
.LFB2109:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z23cuda_minimum_512_doublemPdS_lllmPdS_lll
	.cfi_endproc
.LFE2109:
	.size	cuda_minimum_512_double, .-cuda_minimum_512_double
	.globl	_Z49__device_stub__Z23cuda_minimum_256_doublemPdS_lllmPdS_lll
	.type	_Z49__device_stub__Z23cuda_minimum_256_doublemPdS_lllmPdS_lll, @function
_Z49__device_stub__Z23cuda_minimum_256_doublemPdS_lllmPdS_lll:
.LFB2110:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L189
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_minimum_256_double(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L189:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L191
	call	__stack_chk_fail@PLT
.L191:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2110:
	.size	_Z49__device_stub__Z23cuda_minimum_256_doublemPdS_lllmPdS_lll, .-_Z49__device_stub__Z23cuda_minimum_256_doublemPdS_lllmPdS_lll
	.globl	cuda_minimum_256_double
	.type	cuda_minimum_256_double, @function
cuda_minimum_256_double:
.LFB2111:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z23cuda_minimum_256_doublemPdS_lllmPdS_lll
	.cfi_endproc
.LFE2111:
	.size	cuda_minimum_256_double, .-cuda_minimum_256_double
	.globl	_Z49__device_stub__Z23cuda_minimum_128_doublemPdS_lllmPdS_lll
	.type	_Z49__device_stub__Z23cuda_minimum_128_doublemPdS_lllmPdS_lll, @function
_Z49__device_stub__Z23cuda_minimum_128_doublemPdS_lllmPdS_lll:
.LFB2112:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L194
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_minimum_128_double(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L194:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L196
	call	__stack_chk_fail@PLT
.L196:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2112:
	.size	_Z49__device_stub__Z23cuda_minimum_128_doublemPdS_lllmPdS_lll, .-_Z49__device_stub__Z23cuda_minimum_128_doublemPdS_lllmPdS_lll
	.globl	cuda_minimum_128_double
	.type	cuda_minimum_128_double, @function
cuda_minimum_128_double:
.LFB2113:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z23cuda_minimum_128_doublemPdS_lllmPdS_lll
	.cfi_endproc
.LFE2113:
	.size	cuda_minimum_128_double, .-cuda_minimum_128_double
	.globl	_Z48__device_stub__Z22cuda_minimum_64_doublemPdS_lllmPdS_lll
	.type	_Z48__device_stub__Z22cuda_minimum_64_doublemPdS_lllmPdS_lll, @function
_Z48__device_stub__Z22cuda_minimum_64_doublemPdS_lllmPdS_lll:
.LFB2114:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L199
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_minimum_64_double(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L199:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L201
	call	__stack_chk_fail@PLT
.L201:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2114:
	.size	_Z48__device_stub__Z22cuda_minimum_64_doublemPdS_lllmPdS_lll, .-_Z48__device_stub__Z22cuda_minimum_64_doublemPdS_lllmPdS_lll
	.globl	cuda_minimum_64_double
	.type	cuda_minimum_64_double, @function
cuda_minimum_64_double:
.LFB2115:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z22cuda_minimum_64_doublemPdS_lllmPdS_lll
	.cfi_endproc
.LFE2115:
	.size	cuda_minimum_64_double, .-cuda_minimum_64_double
	.globl	_Z48__device_stub__Z22cuda_minimum_32_doublemPdS_lllmPdS_lll
	.type	_Z48__device_stub__Z22cuda_minimum_32_doublemPdS_lllmPdS_lll, @function
_Z48__device_stub__Z22cuda_minimum_32_doublemPdS_lllmPdS_lll:
.LFB2116:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L204
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_minimum_32_double(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L204:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L206
	call	__stack_chk_fail@PLT
.L206:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2116:
	.size	_Z48__device_stub__Z22cuda_minimum_32_doublemPdS_lllmPdS_lll, .-_Z48__device_stub__Z22cuda_minimum_32_doublemPdS_lllmPdS_lll
	.globl	cuda_minimum_32_double
	.type	cuda_minimum_32_double, @function
cuda_minimum_32_double:
.LFB2117:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z22cuda_minimum_32_doublemPdS_lllmPdS_lll
	.cfi_endproc
.LFE2117:
	.size	cuda_minimum_32_double, .-cuda_minimum_32_double
	.globl	_Z48__device_stub__Z22cuda_minimum_16_doublemPdS_lllmPdS_lll
	.type	_Z48__device_stub__Z22cuda_minimum_16_doublemPdS_lllmPdS_lll, @function
_Z48__device_stub__Z22cuda_minimum_16_doublemPdS_lllmPdS_lll:
.LFB2118:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L209
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_minimum_16_double(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L209:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L211
	call	__stack_chk_fail@PLT
.L211:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2118:
	.size	_Z48__device_stub__Z22cuda_minimum_16_doublemPdS_lllmPdS_lll, .-_Z48__device_stub__Z22cuda_minimum_16_doublemPdS_lllmPdS_lll
	.globl	cuda_minimum_16_double
	.type	cuda_minimum_16_double, @function
cuda_minimum_16_double:
.LFB2119:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z22cuda_minimum_16_doublemPdS_lllmPdS_lll
	.cfi_endproc
.LFE2119:
	.size	cuda_minimum_16_double, .-cuda_minimum_16_double
	.globl	_Z47__device_stub__Z21cuda_minimum_8_doublemPdS_lllmPdS_lll
	.type	_Z47__device_stub__Z21cuda_minimum_8_doublemPdS_lllmPdS_lll, @function
_Z47__device_stub__Z21cuda_minimum_8_doublemPdS_lllmPdS_lll:
.LFB2120:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L214
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_minimum_8_double(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L214:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L216
	call	__stack_chk_fail@PLT
.L216:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2120:
	.size	_Z47__device_stub__Z21cuda_minimum_8_doublemPdS_lllmPdS_lll, .-_Z47__device_stub__Z21cuda_minimum_8_doublemPdS_lllmPdS_lll
	.globl	cuda_minimum_8_double
	.type	cuda_minimum_8_double, @function
cuda_minimum_8_double:
.LFB2121:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z21cuda_minimum_8_doublemPdS_lllmPdS_lll
	.cfi_endproc
.LFE2121:
	.size	cuda_minimum_8_double, .-cuda_minimum_8_double
	.globl	_Z47__device_stub__Z21cuda_minimum_4_doublemPdS_lllmPdS_lll
	.type	_Z47__device_stub__Z21cuda_minimum_4_doublemPdS_lllmPdS_lll, @function
_Z47__device_stub__Z21cuda_minimum_4_doublemPdS_lllmPdS_lll:
.LFB2122:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L219
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_minimum_4_double(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L219:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L221
	call	__stack_chk_fail@PLT
.L221:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2122:
	.size	_Z47__device_stub__Z21cuda_minimum_4_doublemPdS_lllmPdS_lll, .-_Z47__device_stub__Z21cuda_minimum_4_doublemPdS_lllmPdS_lll
	.globl	cuda_minimum_4_double
	.type	cuda_minimum_4_double, @function
cuda_minimum_4_double:
.LFB2123:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z21cuda_minimum_4_doublemPdS_lllmPdS_lll
	.cfi_endproc
.LFE2123:
	.size	cuda_minimum_4_double, .-cuda_minimum_4_double
	.globl	_Z47__device_stub__Z21cuda_minimum_2_doublemPdS_lllmPdS_lll
	.type	_Z47__device_stub__Z21cuda_minimum_2_doublemPdS_lllmPdS_lll, @function
_Z47__device_stub__Z21cuda_minimum_2_doublemPdS_lllmPdS_lll:
.LFB2124:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L224
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_minimum_2_double(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L224:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L226
	call	__stack_chk_fail@PLT
.L226:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2124:
	.size	_Z47__device_stub__Z21cuda_minimum_2_doublemPdS_lllmPdS_lll, .-_Z47__device_stub__Z21cuda_minimum_2_doublemPdS_lllmPdS_lll
	.globl	cuda_minimum_2_double
	.type	cuda_minimum_2_double, @function
cuda_minimum_2_double:
.LFB2125:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z21cuda_minimum_2_doublemPdS_lllmPdS_lll
	.cfi_endproc
.LFE2125:
	.size	cuda_minimum_2_double, .-cuda_minimum_2_double
	.globl	_Z48__device_stub__Z22cuda_minimum_512_floatmPfS_lllmPfS_lll
	.type	_Z48__device_stub__Z22cuda_minimum_512_floatmPfS_lllmPfS_lll, @function
_Z48__device_stub__Z22cuda_minimum_512_floatmPfS_lllmPfS_lll:
.LFB2126:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L229
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_minimum_512_float(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L229:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L231
	call	__stack_chk_fail@PLT
.L231:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2126:
	.size	_Z48__device_stub__Z22cuda_minimum_512_floatmPfS_lllmPfS_lll, .-_Z48__device_stub__Z22cuda_minimum_512_floatmPfS_lllmPfS_lll
	.globl	cuda_minimum_512_float
	.type	cuda_minimum_512_float, @function
cuda_minimum_512_float:
.LFB2127:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z22cuda_minimum_512_floatmPfS_lllmPfS_lll
	.cfi_endproc
.LFE2127:
	.size	cuda_minimum_512_float, .-cuda_minimum_512_float
	.globl	_Z48__device_stub__Z22cuda_minimum_256_floatmPfS_lllmPfS_lll
	.type	_Z48__device_stub__Z22cuda_minimum_256_floatmPfS_lllmPfS_lll, @function
_Z48__device_stub__Z22cuda_minimum_256_floatmPfS_lllmPfS_lll:
.LFB2128:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L234
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_minimum_256_float(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L234:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L236
	call	__stack_chk_fail@PLT
.L236:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2128:
	.size	_Z48__device_stub__Z22cuda_minimum_256_floatmPfS_lllmPfS_lll, .-_Z48__device_stub__Z22cuda_minimum_256_floatmPfS_lllmPfS_lll
	.globl	cuda_minimum_256_float
	.type	cuda_minimum_256_float, @function
cuda_minimum_256_float:
.LFB2129:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z22cuda_minimum_256_floatmPfS_lllmPfS_lll
	.cfi_endproc
.LFE2129:
	.size	cuda_minimum_256_float, .-cuda_minimum_256_float
	.globl	_Z48__device_stub__Z22cuda_minimum_128_floatmPfS_lllmPfS_lll
	.type	_Z48__device_stub__Z22cuda_minimum_128_floatmPfS_lllmPfS_lll, @function
_Z48__device_stub__Z22cuda_minimum_128_floatmPfS_lllmPfS_lll:
.LFB2130:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L239
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_minimum_128_float(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L239:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L241
	call	__stack_chk_fail@PLT
.L241:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2130:
	.size	_Z48__device_stub__Z22cuda_minimum_128_floatmPfS_lllmPfS_lll, .-_Z48__device_stub__Z22cuda_minimum_128_floatmPfS_lllmPfS_lll
	.globl	cuda_minimum_128_float
	.type	cuda_minimum_128_float, @function
cuda_minimum_128_float:
.LFB2131:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z22cuda_minimum_128_floatmPfS_lllmPfS_lll
	.cfi_endproc
.LFE2131:
	.size	cuda_minimum_128_float, .-cuda_minimum_128_float
	.globl	_Z47__device_stub__Z21cuda_minimum_64_floatmPfS_lllmPfS_lll
	.type	_Z47__device_stub__Z21cuda_minimum_64_floatmPfS_lllmPfS_lll, @function
_Z47__device_stub__Z21cuda_minimum_64_floatmPfS_lllmPfS_lll:
.LFB2132:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L244
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_minimum_64_float(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L244:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L246
	call	__stack_chk_fail@PLT
.L246:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2132:
	.size	_Z47__device_stub__Z21cuda_minimum_64_floatmPfS_lllmPfS_lll, .-_Z47__device_stub__Z21cuda_minimum_64_floatmPfS_lllmPfS_lll
	.globl	cuda_minimum_64_float
	.type	cuda_minimum_64_float, @function
cuda_minimum_64_float:
.LFB2133:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z21cuda_minimum_64_floatmPfS_lllmPfS_lll
	.cfi_endproc
.LFE2133:
	.size	cuda_minimum_64_float, .-cuda_minimum_64_float
	.globl	_Z47__device_stub__Z21cuda_minimum_32_floatmPfS_lllmPfS_lll
	.type	_Z47__device_stub__Z21cuda_minimum_32_floatmPfS_lllmPfS_lll, @function
_Z47__device_stub__Z21cuda_minimum_32_floatmPfS_lllmPfS_lll:
.LFB2134:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L249
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_minimum_32_float(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L249:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L251
	call	__stack_chk_fail@PLT
.L251:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2134:
	.size	_Z47__device_stub__Z21cuda_minimum_32_floatmPfS_lllmPfS_lll, .-_Z47__device_stub__Z21cuda_minimum_32_floatmPfS_lllmPfS_lll
	.globl	cuda_minimum_32_float
	.type	cuda_minimum_32_float, @function
cuda_minimum_32_float:
.LFB2135:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z21cuda_minimum_32_floatmPfS_lllmPfS_lll
	.cfi_endproc
.LFE2135:
	.size	cuda_minimum_32_float, .-cuda_minimum_32_float
	.globl	_Z47__device_stub__Z21cuda_minimum_16_floatmPfS_lllmPfS_lll
	.type	_Z47__device_stub__Z21cuda_minimum_16_floatmPfS_lllmPfS_lll, @function
_Z47__device_stub__Z21cuda_minimum_16_floatmPfS_lllmPfS_lll:
.LFB2136:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L254
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_minimum_16_float(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L254:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L256
	call	__stack_chk_fail@PLT
.L256:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2136:
	.size	_Z47__device_stub__Z21cuda_minimum_16_floatmPfS_lllmPfS_lll, .-_Z47__device_stub__Z21cuda_minimum_16_floatmPfS_lllmPfS_lll
	.globl	cuda_minimum_16_float
	.type	cuda_minimum_16_float, @function
cuda_minimum_16_float:
.LFB2137:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z21cuda_minimum_16_floatmPfS_lllmPfS_lll
	.cfi_endproc
.LFE2137:
	.size	cuda_minimum_16_float, .-cuda_minimum_16_float
	.globl	_Z46__device_stub__Z20cuda_minimum_8_floatmPfS_lllmPfS_lll
	.type	_Z46__device_stub__Z20cuda_minimum_8_floatmPfS_lllmPfS_lll, @function
_Z46__device_stub__Z20cuda_minimum_8_floatmPfS_lllmPfS_lll:
.LFB2138:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L259
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_minimum_8_float(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L259:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L261
	call	__stack_chk_fail@PLT
.L261:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2138:
	.size	_Z46__device_stub__Z20cuda_minimum_8_floatmPfS_lllmPfS_lll, .-_Z46__device_stub__Z20cuda_minimum_8_floatmPfS_lllmPfS_lll
	.globl	cuda_minimum_8_float
	.type	cuda_minimum_8_float, @function
cuda_minimum_8_float:
.LFB2139:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z20cuda_minimum_8_floatmPfS_lllmPfS_lll
	.cfi_endproc
.LFE2139:
	.size	cuda_minimum_8_float, .-cuda_minimum_8_float
	.globl	_Z46__device_stub__Z20cuda_minimum_4_floatmPfS_lllmPfS_lll
	.type	_Z46__device_stub__Z20cuda_minimum_4_floatmPfS_lllmPfS_lll, @function
_Z46__device_stub__Z20cuda_minimum_4_floatmPfS_lllmPfS_lll:
.LFB2140:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L264
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_minimum_4_float(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L264:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L266
	call	__stack_chk_fail@PLT
.L266:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2140:
	.size	_Z46__device_stub__Z20cuda_minimum_4_floatmPfS_lllmPfS_lll, .-_Z46__device_stub__Z20cuda_minimum_4_floatmPfS_lllmPfS_lll
	.globl	cuda_minimum_4_float
	.type	cuda_minimum_4_float, @function
cuda_minimum_4_float:
.LFB2141:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z20cuda_minimum_4_floatmPfS_lllmPfS_lll
	.cfi_endproc
.LFE2141:
	.size	cuda_minimum_4_float, .-cuda_minimum_4_float
	.globl	_Z46__device_stub__Z20cuda_minimum_2_floatmPfS_lllmPfS_lll
	.type	_Z46__device_stub__Z20cuda_minimum_2_floatmPfS_lllmPfS_lll, @function
_Z46__device_stub__Z20cuda_minimum_2_floatmPfS_lllmPfS_lll:
.LFB2142:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L269
	pushq	56(%rsp)
	.cfi_def_cfa_offset 168
	leaq	cuda_minimum_2_float(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 176
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L269:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L271
	call	__stack_chk_fail@PLT
.L271:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2142:
	.size	_Z46__device_stub__Z20cuda_minimum_2_floatmPfS_lllmPfS_lll, .-_Z46__device_stub__Z20cuda_minimum_2_floatmPfS_lllmPfS_lll
	.globl	cuda_minimum_2_float
	.type	cuda_minimum_2_float, @function
cuda_minimum_2_float:
.LFB2143:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z20cuda_minimum_2_floatmPfS_lllmPfS_lll
	.cfi_endproc
.LFE2143:
	.size	cuda_minimum_2_float, .-cuda_minimum_2_float
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"cuda_minimum_2_float"
.LC1:
	.string	"cuda_minimum_4_float"
.LC2:
	.string	"cuda_minimum_8_float"
.LC3:
	.string	"cuda_minimum_16_float"
.LC4:
	.string	"cuda_minimum_32_float"
.LC5:
	.string	"cuda_minimum_64_float"
.LC6:
	.string	"cuda_minimum_128_float"
.LC7:
	.string	"cuda_minimum_256_float"
.LC8:
	.string	"cuda_minimum_512_float"
.LC9:
	.string	"cuda_minimum_2_double"
.LC10:
	.string	"cuda_minimum_4_double"
.LC11:
	.string	"cuda_minimum_8_double"
.LC12:
	.string	"cuda_minimum_16_double"
.LC13:
	.string	"cuda_minimum_32_double"
.LC14:
	.string	"cuda_minimum_64_double"
.LC15:
	.string	"cuda_minimum_128_double"
.LC16:
	.string	"cuda_minimum_256_double"
.LC17:
	.string	"cuda_minimum_512_double"
.LC18:
	.string	"cuda_maximum_2_float"
.LC19:
	.string	"cuda_maximum_4_float"
.LC20:
	.string	"cuda_maximum_8_float"
.LC21:
	.string	"cuda_maximum_16_float"
.LC22:
	.string	"cuda_maximum_32_float"
.LC23:
	.string	"cuda_maximum_64_float"
.LC24:
	.string	"cuda_maximum_128_float"
.LC25:
	.string	"cuda_maximum_256_float"
.LC26:
	.string	"cuda_maximum_512_float"
.LC27:
	.string	"cuda_maximum_2_double"
.LC28:
	.string	"cuda_maximum_4_double"
.LC29:
	.string	"cuda_maximum_8_double"
.LC30:
	.string	"cuda_maximum_16_double"
.LC31:
	.string	"cuda_maximum_32_double"
.LC32:
	.string	"cuda_maximum_64_double"
.LC33:
	.string	"cuda_maximum_128_double"
.LC34:
	.string	"cuda_maximum_256_double"
.LC35:
	.string	"cuda_maximum_512_double"
.LC36:
	.string	"cuda_sum_2_float"
.LC37:
	.string	"cuda_sum_4_float"
.LC38:
	.string	"cuda_sum_8_float"
.LC39:
	.string	"cuda_sum_16_float"
.LC40:
	.string	"cuda_sum_32_float"
.LC41:
	.string	"cuda_sum_64_float"
.LC42:
	.string	"cuda_sum_128_float"
.LC43:
	.string	"cuda_sum_256_float"
.LC44:
	.string	"cuda_sum_512_float"
.LC45:
	.string	"cuda_sum_2_double"
.LC46:
	.string	"cuda_sum_4_double"
.LC47:
	.string	"cuda_sum_8_double"
.LC48:
	.string	"cuda_sum_16_double"
.LC49:
	.string	"cuda_sum_32_double"
.LC50:
	.string	"cuda_sum_64_double"
.LC51:
	.string	"cuda_sum_128_double"
.LC52:
	.string	"cuda_sum_256_double"
.LC53:
	.string	"cuda_sum_512_double"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2145:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	cuda_minimum_2_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_minimum_4_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_minimum_8_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_minimum_16_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_minimum_32_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_minimum_64_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_minimum_128_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_minimum_256_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC8(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	cuda_minimum_512_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_minimum_2_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_minimum_4_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_minimum_8_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_minimum_16_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_minimum_32_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC14(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_minimum_64_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC15(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_minimum_128_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC16(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	cuda_minimum_256_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC17(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_minimum_512_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC18(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_maximum_2_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC19(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_maximum_4_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC20(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_maximum_8_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC21(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_maximum_16_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC22(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_maximum_32_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC23(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_maximum_64_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC24(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	cuda_maximum_128_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC25(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_maximum_256_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC26(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_maximum_512_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC27(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_maximum_2_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC28(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_maximum_4_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC29(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_maximum_8_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC30(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_maximum_16_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC31(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_maximum_32_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC32(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	cuda_maximum_64_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC33(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_maximum_128_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC34(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_maximum_256_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC35(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_maximum_512_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC36(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_sum_2_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC37(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_sum_4_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC38(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_sum_8_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC39(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_sum_16_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC40(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	cuda_sum_32_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC41(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_sum_64_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC42(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_sum_128_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC43(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_sum_256_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC44(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_sum_512_float(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC45(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_sum_2_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC46(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_sum_4_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC47(%rip), %rdx
	movq	%rbx, %rdi
	leaq	cuda_sum_8_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC48(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	movq	%rdx, %rcx
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	cuda_sum_16_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC49(%rip), %rdx
	orl	$-1, %r8d
	leaq	cuda_sum_32_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC50(%rip), %rdx
	orl	$-1, %r8d
	leaq	cuda_sum_64_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC51(%rip), %rdx
	orl	$-1, %r8d
	leaq	cuda_sum_128_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC52(%rip), %rdx
	orl	$-1, %r8d
	leaq	cuda_sum_256_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC53(%rip), %rdx
	orl	$-1, %r8d
	leaq	cuda_sum_512_double(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2145:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
// Copyright 2016 Massachusetts Institute of Technology. See LICENSE file for details.
// http://docs.nvidia.com/cuda/samples/6_Advanced/reduction/doc/reduction.pdf

template <unsigned int blockSize, typename T, typename R>
__device__ void cuda_reduce(R reduce, size_t n, T *g_idata, T *g_odata, off_t incx, off_t incy, off_t incz, double a = 0) {
    extern __shared__ char vdata[];
    T* sdata = (T*) vdata;

    off_t grid_index = blockIdx.y*incy + blockIdx.z*incz;

    unsigned int tid = threadIdx.x;
    unsigned int i = blockIdx.x*(blockSize) + tid;
    unsigned int gridSize = blockSize*gridDim.x;

    if (i < n) {
        sdata[tid] = g_idata[incx*i + grid_index];
        i += gridSize;
    }

    while (i < n) {
        reduce(sdata[tid], g_idata[incx*i + grid_index]);
        i += gridSize;
    }

    __syncthreads();

    if (blockSize >= 512) { if (tid < 256 && tid + 256 < n) { reduce(sdata[tid], sdata[tid + 256]); } __syncthreads(); }
    if (blockSize >= 256) { if (tid < 128 && tid + 128 < n) { reduce(sdata[tid], sdata[tid + 128]); } __syncthreads(); }
    if (blockSize >= 128) { if (tid <  64 && tid +  64 < n) { reduce(sdata[tid], sdata[tid +  64]); } __syncthreads(); }
    if (tid < 32) {
        if (blockSize >=  64) { if (tid <  32 && tid + 32 < n) { reduce(sdata[tid], sdata[tid +  32]); } }
        if (blockSize >=  32) { if (tid <  16 && tid + 16 < n) { reduce(sdata[tid], sdata[tid +  16]); } }
        if (blockSize >=  16) { if (tid <   8 && tid +  8 < n) { reduce(sdata[tid], sdata[tid +   8]); } }
        if (blockSize >=   8) { if (tid <   4 && tid +  4 < n) { reduce(sdata[tid], sdata[tid +   4]); } }
        if (blockSize >=   4) { if (tid <   2 && tid +  2 < n) { reduce(sdata[tid], sdata[tid +   2]); } }
        if (blockSize >=   2) { if (tid <   1 && tid +  1 < n) { reduce(sdata[tid], sdata[tid +   1]); } }
    }

    if (tid == 0) {
        off_t o = blockIdx.x + gridDim.x*(blockIdx.y + gridDim.y*blockIdx.z);
        if (a == 0)
	    g_odata[o] = sdata[0];
	else
	    g_odata[o] = a*g_odata[o] + sdata[0];
    }
}

struct Sum { template<typename T> __device__ void operator() (T& acc, const T v) { acc += v; } };
struct Min { template<typename T> __device__ void operator() (T& acc, const T v) { if (v < acc) acc = v; } };
struct Max { template<typename T> __device__ void operator() (T& acc, const T v) { if (v > acc) acc = v; } };

extern "C" {
// Sum
  __global__ void cuda_sum_512_double(size_t n, double* g_idata, double* g_odata, double a, off_t incx, off_t incy, off_t incz) { cuda_reduce<512>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_256_double(size_t n, double* g_idata, double* g_odata, double a, off_t incx, off_t incy, off_t incz) { cuda_reduce<256>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_128_double(size_t n, double* g_idata, double* g_odata, double a, off_t incx, off_t incy, off_t incz) { cuda_reduce<128>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_64_double(size_t n, double* g_idata, double* g_odata, double a, off_t incx, off_t incy, off_t incz) { cuda_reduce<64>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_32_double(size_t n, double* g_idata, double* g_odata, double a, off_t incx, off_t incy, off_t incz) { cuda_reduce<32>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_16_double(size_t n, double* g_idata, double* g_odata, double a, off_t incx, off_t incy, off_t incz) { cuda_reduce<16>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_8_double(size_t n, double* g_idata, double* g_odata, double a, off_t incx, off_t incy, off_t incz) { cuda_reduce<8>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_4_double(size_t n, double* g_idata, double* g_odata, double a, off_t incx, off_t incy, off_t incz) { cuda_reduce<4>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_2_double(size_t n, double* g_idata, double* g_odata, double a, off_t incx, off_t incy, off_t incz) { cuda_reduce<2>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }

  __global__ void cuda_sum_512_float(size_t n, float* g_idata, float* g_odata, float a, off_t incx, off_t incy, off_t incz) { cuda_reduce<512>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_256_float(size_t n, float* g_idata, float* g_odata, float a, off_t incx, off_t incy, off_t incz) { cuda_reduce<256>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_128_float(size_t n, float* g_idata, float* g_odata, float a, off_t incx, off_t incy, off_t incz) { cuda_reduce<128>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_64_float(size_t n, float* g_idata, float* g_odata, float a, off_t incx, off_t incy, off_t incz) { cuda_reduce<64>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_32_float(size_t n, float* g_idata, float* g_odata, float a, off_t incx, off_t incy, off_t incz) { cuda_reduce<32>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_16_float(size_t n, float* g_idata, float* g_odata, float a, off_t incx, off_t incy, off_t incz) { cuda_reduce<16>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_8_float(size_t n, float* g_idata, float* g_odata, float a, off_t incx, off_t incy, off_t incz) { cuda_reduce<8>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_4_float(size_t n, float* g_idata, float* g_odata, float a, off_t incx, off_t incy, off_t incz) { cuda_reduce<4>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }
  __global__ void cuda_sum_2_float(size_t n, float* g_idata, float* g_odata, float a, off_t incx, off_t incy, off_t incz) { cuda_reduce<2>(Sum(), n, g_idata, g_odata, incx, incy, incz, a); }

// Max
  __global__ void cuda_maximum_512_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<512>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_256_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<256>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_128_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<128>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_64_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<64>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_32_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<32>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_16_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<16>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_8_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<8>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_4_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<4>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_2_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<2>(Max(), n, g_idata, g_odata, incx, incy, incz); }

  __global__ void cuda_maximum_512_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<512>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_256_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<256>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_128_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<128>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_64_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<64>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_32_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<32>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_16_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<16>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_8_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<8>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_4_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<4>(Max(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_maximum_2_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<2>(Max(), n, g_idata, g_odata, incx, incy, incz); }

// Min
  __global__ void cuda_minimum_512_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<512>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_256_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<256>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_128_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<128>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_64_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<64>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_32_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<32>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_16_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<16>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_8_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<8>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_4_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<4>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_2_double(size_t n, double* g_idata, double* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<2>(Min(), n, g_idata, g_odata, incx, incy, incz); }

  __global__ void cuda_minimum_512_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<512>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_256_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<256>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_128_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<128>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_64_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<64>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_32_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<32>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_16_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<16>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_8_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<8>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_4_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<4>(Min(), n, g_idata, g_odata, incx, incy, incz); }
  __global__ void cuda_minimum_2_float(size_t n, float* g_idata, float* g_odata, off_t incx, off_t incy, off_t incz) { cuda_reduce<2>(Min(), n, g_idata, g_odata, incx, incy, incz); }
}

	.text
	.file	"cudaReduce.hip"
	.globl	__device_stub__cuda_sum_512_double # -- Begin function __device_stub__cuda_sum_512_double
	.type	__device_stub__cuda_sum_512_double,@function
__device_stub__cuda_sum_512_double:     # @__device_stub__cuda_sum_512_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	40(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_sum_512_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__cuda_sum_512_double, .Lfunc_end0-__device_stub__cuda_sum_512_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_sum_256_double # -- Begin function __device_stub__cuda_sum_256_double
	.type	__device_stub__cuda_sum_256_double,@function
__device_stub__cuda_sum_256_double:     # @__device_stub__cuda_sum_256_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	40(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_sum_256_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	__device_stub__cuda_sum_256_double, .Lfunc_end1-__device_stub__cuda_sum_256_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_sum_128_double # -- Begin function __device_stub__cuda_sum_128_double
	.type	__device_stub__cuda_sum_128_double,@function
__device_stub__cuda_sum_128_double:     # @__device_stub__cuda_sum_128_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	40(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_sum_128_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	__device_stub__cuda_sum_128_double, .Lfunc_end2-__device_stub__cuda_sum_128_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_sum_64_double # -- Begin function __device_stub__cuda_sum_64_double
	.type	__device_stub__cuda_sum_64_double,@function
__device_stub__cuda_sum_64_double:      # @__device_stub__cuda_sum_64_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	40(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_sum_64_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	__device_stub__cuda_sum_64_double, .Lfunc_end3-__device_stub__cuda_sum_64_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_sum_32_double # -- Begin function __device_stub__cuda_sum_32_double
	.type	__device_stub__cuda_sum_32_double,@function
__device_stub__cuda_sum_32_double:      # @__device_stub__cuda_sum_32_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	40(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_sum_32_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	__device_stub__cuda_sum_32_double, .Lfunc_end4-__device_stub__cuda_sum_32_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_sum_16_double # -- Begin function __device_stub__cuda_sum_16_double
	.type	__device_stub__cuda_sum_16_double,@function
__device_stub__cuda_sum_16_double:      # @__device_stub__cuda_sum_16_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	40(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_sum_16_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	__device_stub__cuda_sum_16_double, .Lfunc_end5-__device_stub__cuda_sum_16_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_sum_8_double # -- Begin function __device_stub__cuda_sum_8_double
	.type	__device_stub__cuda_sum_8_double,@function
__device_stub__cuda_sum_8_double:       # @__device_stub__cuda_sum_8_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	40(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_sum_8_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	__device_stub__cuda_sum_8_double, .Lfunc_end6-__device_stub__cuda_sum_8_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_sum_4_double # -- Begin function __device_stub__cuda_sum_4_double
	.type	__device_stub__cuda_sum_4_double,@function
__device_stub__cuda_sum_4_double:       # @__device_stub__cuda_sum_4_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	40(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_sum_4_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	__device_stub__cuda_sum_4_double, .Lfunc_end7-__device_stub__cuda_sum_4_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_sum_2_double # -- Begin function __device_stub__cuda_sum_2_double
	.type	__device_stub__cuda_sum_2_double,@function
__device_stub__cuda_sum_2_double:       # @__device_stub__cuda_sum_2_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	40(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_sum_2_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	__device_stub__cuda_sum_2_double, .Lfunc_end8-__device_stub__cuda_sum_2_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_sum_512_float # -- Begin function __device_stub__cuda_sum_512_float
	.type	__device_stub__cuda_sum_512_float,@function
__device_stub__cuda_sum_512_float:      # @__device_stub__cuda_sum_512_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	48(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_sum_512_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	__device_stub__cuda_sum_512_float, .Lfunc_end9-__device_stub__cuda_sum_512_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_sum_256_float # -- Begin function __device_stub__cuda_sum_256_float
	.type	__device_stub__cuda_sum_256_float,@function
__device_stub__cuda_sum_256_float:      # @__device_stub__cuda_sum_256_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	48(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_sum_256_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	__device_stub__cuda_sum_256_float, .Lfunc_end10-__device_stub__cuda_sum_256_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_sum_128_float # -- Begin function __device_stub__cuda_sum_128_float
	.type	__device_stub__cuda_sum_128_float,@function
__device_stub__cuda_sum_128_float:      # @__device_stub__cuda_sum_128_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	48(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_sum_128_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	__device_stub__cuda_sum_128_float, .Lfunc_end11-__device_stub__cuda_sum_128_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_sum_64_float # -- Begin function __device_stub__cuda_sum_64_float
	.type	__device_stub__cuda_sum_64_float,@function
__device_stub__cuda_sum_64_float:       # @__device_stub__cuda_sum_64_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	48(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_sum_64_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end12:
	.size	__device_stub__cuda_sum_64_float, .Lfunc_end12-__device_stub__cuda_sum_64_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_sum_32_float # -- Begin function __device_stub__cuda_sum_32_float
	.type	__device_stub__cuda_sum_32_float,@function
__device_stub__cuda_sum_32_float:       # @__device_stub__cuda_sum_32_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	48(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_sum_32_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end13:
	.size	__device_stub__cuda_sum_32_float, .Lfunc_end13-__device_stub__cuda_sum_32_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_sum_16_float # -- Begin function __device_stub__cuda_sum_16_float
	.type	__device_stub__cuda_sum_16_float,@function
__device_stub__cuda_sum_16_float:       # @__device_stub__cuda_sum_16_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	48(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_sum_16_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end14:
	.size	__device_stub__cuda_sum_16_float, .Lfunc_end14-__device_stub__cuda_sum_16_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_sum_8_float # -- Begin function __device_stub__cuda_sum_8_float
	.type	__device_stub__cuda_sum_8_float,@function
__device_stub__cuda_sum_8_float:        # @__device_stub__cuda_sum_8_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	48(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_sum_8_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end15:
	.size	__device_stub__cuda_sum_8_float, .Lfunc_end15-__device_stub__cuda_sum_8_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_sum_4_float # -- Begin function __device_stub__cuda_sum_4_float
	.type	__device_stub__cuda_sum_4_float,@function
__device_stub__cuda_sum_4_float:        # @__device_stub__cuda_sum_4_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	48(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_sum_4_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end16:
	.size	__device_stub__cuda_sum_4_float, .Lfunc_end16-__device_stub__cuda_sum_4_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_sum_2_float # -- Begin function __device_stub__cuda_sum_2_float
	.type	__device_stub__cuda_sum_2_float,@function
__device_stub__cuda_sum_2_float:        # @__device_stub__cuda_sum_2_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	48(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_sum_2_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end17:
	.size	__device_stub__cuda_sum_2_float, .Lfunc_end17-__device_stub__cuda_sum_2_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_maximum_512_double # -- Begin function __device_stub__cuda_maximum_512_double
	.type	__device_stub__cuda_maximum_512_double,@function
__device_stub__cuda_maximum_512_double: # @__device_stub__cuda_maximum_512_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_maximum_512_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end18:
	.size	__device_stub__cuda_maximum_512_double, .Lfunc_end18-__device_stub__cuda_maximum_512_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_maximum_256_double # -- Begin function __device_stub__cuda_maximum_256_double
	.type	__device_stub__cuda_maximum_256_double,@function
__device_stub__cuda_maximum_256_double: # @__device_stub__cuda_maximum_256_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_maximum_256_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end19:
	.size	__device_stub__cuda_maximum_256_double, .Lfunc_end19-__device_stub__cuda_maximum_256_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_maximum_128_double # -- Begin function __device_stub__cuda_maximum_128_double
	.type	__device_stub__cuda_maximum_128_double,@function
__device_stub__cuda_maximum_128_double: # @__device_stub__cuda_maximum_128_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_maximum_128_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end20:
	.size	__device_stub__cuda_maximum_128_double, .Lfunc_end20-__device_stub__cuda_maximum_128_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_maximum_64_double # -- Begin function __device_stub__cuda_maximum_64_double
	.type	__device_stub__cuda_maximum_64_double,@function
__device_stub__cuda_maximum_64_double:  # @__device_stub__cuda_maximum_64_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_maximum_64_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end21:
	.size	__device_stub__cuda_maximum_64_double, .Lfunc_end21-__device_stub__cuda_maximum_64_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_maximum_32_double # -- Begin function __device_stub__cuda_maximum_32_double
	.type	__device_stub__cuda_maximum_32_double,@function
__device_stub__cuda_maximum_32_double:  # @__device_stub__cuda_maximum_32_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_maximum_32_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end22:
	.size	__device_stub__cuda_maximum_32_double, .Lfunc_end22-__device_stub__cuda_maximum_32_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_maximum_16_double # -- Begin function __device_stub__cuda_maximum_16_double
	.type	__device_stub__cuda_maximum_16_double,@function
__device_stub__cuda_maximum_16_double:  # @__device_stub__cuda_maximum_16_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_maximum_16_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end23:
	.size	__device_stub__cuda_maximum_16_double, .Lfunc_end23-__device_stub__cuda_maximum_16_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_maximum_8_double # -- Begin function __device_stub__cuda_maximum_8_double
	.type	__device_stub__cuda_maximum_8_double,@function
__device_stub__cuda_maximum_8_double:   # @__device_stub__cuda_maximum_8_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_maximum_8_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end24:
	.size	__device_stub__cuda_maximum_8_double, .Lfunc_end24-__device_stub__cuda_maximum_8_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_maximum_4_double # -- Begin function __device_stub__cuda_maximum_4_double
	.type	__device_stub__cuda_maximum_4_double,@function
__device_stub__cuda_maximum_4_double:   # @__device_stub__cuda_maximum_4_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_maximum_4_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end25:
	.size	__device_stub__cuda_maximum_4_double, .Lfunc_end25-__device_stub__cuda_maximum_4_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_maximum_2_double # -- Begin function __device_stub__cuda_maximum_2_double
	.type	__device_stub__cuda_maximum_2_double,@function
__device_stub__cuda_maximum_2_double:   # @__device_stub__cuda_maximum_2_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_maximum_2_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end26:
	.size	__device_stub__cuda_maximum_2_double, .Lfunc_end26-__device_stub__cuda_maximum_2_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_maximum_512_float # -- Begin function __device_stub__cuda_maximum_512_float
	.type	__device_stub__cuda_maximum_512_float,@function
__device_stub__cuda_maximum_512_float:  # @__device_stub__cuda_maximum_512_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_maximum_512_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end27:
	.size	__device_stub__cuda_maximum_512_float, .Lfunc_end27-__device_stub__cuda_maximum_512_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_maximum_256_float # -- Begin function __device_stub__cuda_maximum_256_float
	.type	__device_stub__cuda_maximum_256_float,@function
__device_stub__cuda_maximum_256_float:  # @__device_stub__cuda_maximum_256_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_maximum_256_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end28:
	.size	__device_stub__cuda_maximum_256_float, .Lfunc_end28-__device_stub__cuda_maximum_256_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_maximum_128_float # -- Begin function __device_stub__cuda_maximum_128_float
	.type	__device_stub__cuda_maximum_128_float,@function
__device_stub__cuda_maximum_128_float:  # @__device_stub__cuda_maximum_128_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_maximum_128_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end29:
	.size	__device_stub__cuda_maximum_128_float, .Lfunc_end29-__device_stub__cuda_maximum_128_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_maximum_64_float # -- Begin function __device_stub__cuda_maximum_64_float
	.type	__device_stub__cuda_maximum_64_float,@function
__device_stub__cuda_maximum_64_float:   # @__device_stub__cuda_maximum_64_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_maximum_64_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end30:
	.size	__device_stub__cuda_maximum_64_float, .Lfunc_end30-__device_stub__cuda_maximum_64_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_maximum_32_float # -- Begin function __device_stub__cuda_maximum_32_float
	.type	__device_stub__cuda_maximum_32_float,@function
__device_stub__cuda_maximum_32_float:   # @__device_stub__cuda_maximum_32_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_maximum_32_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end31:
	.size	__device_stub__cuda_maximum_32_float, .Lfunc_end31-__device_stub__cuda_maximum_32_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_maximum_16_float # -- Begin function __device_stub__cuda_maximum_16_float
	.type	__device_stub__cuda_maximum_16_float,@function
__device_stub__cuda_maximum_16_float:   # @__device_stub__cuda_maximum_16_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_maximum_16_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end32:
	.size	__device_stub__cuda_maximum_16_float, .Lfunc_end32-__device_stub__cuda_maximum_16_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_maximum_8_float # -- Begin function __device_stub__cuda_maximum_8_float
	.type	__device_stub__cuda_maximum_8_float,@function
__device_stub__cuda_maximum_8_float:    # @__device_stub__cuda_maximum_8_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_maximum_8_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end33:
	.size	__device_stub__cuda_maximum_8_float, .Lfunc_end33-__device_stub__cuda_maximum_8_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_maximum_4_float # -- Begin function __device_stub__cuda_maximum_4_float
	.type	__device_stub__cuda_maximum_4_float,@function
__device_stub__cuda_maximum_4_float:    # @__device_stub__cuda_maximum_4_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_maximum_4_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end34:
	.size	__device_stub__cuda_maximum_4_float, .Lfunc_end34-__device_stub__cuda_maximum_4_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_maximum_2_float # -- Begin function __device_stub__cuda_maximum_2_float
	.type	__device_stub__cuda_maximum_2_float,@function
__device_stub__cuda_maximum_2_float:    # @__device_stub__cuda_maximum_2_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_maximum_2_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end35:
	.size	__device_stub__cuda_maximum_2_float, .Lfunc_end35-__device_stub__cuda_maximum_2_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_minimum_512_double # -- Begin function __device_stub__cuda_minimum_512_double
	.type	__device_stub__cuda_minimum_512_double,@function
__device_stub__cuda_minimum_512_double: # @__device_stub__cuda_minimum_512_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_minimum_512_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end36:
	.size	__device_stub__cuda_minimum_512_double, .Lfunc_end36-__device_stub__cuda_minimum_512_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_minimum_256_double # -- Begin function __device_stub__cuda_minimum_256_double
	.type	__device_stub__cuda_minimum_256_double,@function
__device_stub__cuda_minimum_256_double: # @__device_stub__cuda_minimum_256_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_minimum_256_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end37:
	.size	__device_stub__cuda_minimum_256_double, .Lfunc_end37-__device_stub__cuda_minimum_256_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_minimum_128_double # -- Begin function __device_stub__cuda_minimum_128_double
	.type	__device_stub__cuda_minimum_128_double,@function
__device_stub__cuda_minimum_128_double: # @__device_stub__cuda_minimum_128_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_minimum_128_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end38:
	.size	__device_stub__cuda_minimum_128_double, .Lfunc_end38-__device_stub__cuda_minimum_128_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_minimum_64_double # -- Begin function __device_stub__cuda_minimum_64_double
	.type	__device_stub__cuda_minimum_64_double,@function
__device_stub__cuda_minimum_64_double:  # @__device_stub__cuda_minimum_64_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_minimum_64_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end39:
	.size	__device_stub__cuda_minimum_64_double, .Lfunc_end39-__device_stub__cuda_minimum_64_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_minimum_32_double # -- Begin function __device_stub__cuda_minimum_32_double
	.type	__device_stub__cuda_minimum_32_double,@function
__device_stub__cuda_minimum_32_double:  # @__device_stub__cuda_minimum_32_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_minimum_32_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end40:
	.size	__device_stub__cuda_minimum_32_double, .Lfunc_end40-__device_stub__cuda_minimum_32_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_minimum_16_double # -- Begin function __device_stub__cuda_minimum_16_double
	.type	__device_stub__cuda_minimum_16_double,@function
__device_stub__cuda_minimum_16_double:  # @__device_stub__cuda_minimum_16_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_minimum_16_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end41:
	.size	__device_stub__cuda_minimum_16_double, .Lfunc_end41-__device_stub__cuda_minimum_16_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_minimum_8_double # -- Begin function __device_stub__cuda_minimum_8_double
	.type	__device_stub__cuda_minimum_8_double,@function
__device_stub__cuda_minimum_8_double:   # @__device_stub__cuda_minimum_8_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_minimum_8_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end42:
	.size	__device_stub__cuda_minimum_8_double, .Lfunc_end42-__device_stub__cuda_minimum_8_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_minimum_4_double # -- Begin function __device_stub__cuda_minimum_4_double
	.type	__device_stub__cuda_minimum_4_double,@function
__device_stub__cuda_minimum_4_double:   # @__device_stub__cuda_minimum_4_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_minimum_4_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end43:
	.size	__device_stub__cuda_minimum_4_double, .Lfunc_end43-__device_stub__cuda_minimum_4_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_minimum_2_double # -- Begin function __device_stub__cuda_minimum_2_double
	.type	__device_stub__cuda_minimum_2_double,@function
__device_stub__cuda_minimum_2_double:   # @__device_stub__cuda_minimum_2_double
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_minimum_2_double, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end44:
	.size	__device_stub__cuda_minimum_2_double, .Lfunc_end44-__device_stub__cuda_minimum_2_double
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_minimum_512_float # -- Begin function __device_stub__cuda_minimum_512_float
	.type	__device_stub__cuda_minimum_512_float,@function
__device_stub__cuda_minimum_512_float:  # @__device_stub__cuda_minimum_512_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_minimum_512_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end45:
	.size	__device_stub__cuda_minimum_512_float, .Lfunc_end45-__device_stub__cuda_minimum_512_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_minimum_256_float # -- Begin function __device_stub__cuda_minimum_256_float
	.type	__device_stub__cuda_minimum_256_float,@function
__device_stub__cuda_minimum_256_float:  # @__device_stub__cuda_minimum_256_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_minimum_256_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end46:
	.size	__device_stub__cuda_minimum_256_float, .Lfunc_end46-__device_stub__cuda_minimum_256_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_minimum_128_float # -- Begin function __device_stub__cuda_minimum_128_float
	.type	__device_stub__cuda_minimum_128_float,@function
__device_stub__cuda_minimum_128_float:  # @__device_stub__cuda_minimum_128_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_minimum_128_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end47:
	.size	__device_stub__cuda_minimum_128_float, .Lfunc_end47-__device_stub__cuda_minimum_128_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_minimum_64_float # -- Begin function __device_stub__cuda_minimum_64_float
	.type	__device_stub__cuda_minimum_64_float,@function
__device_stub__cuda_minimum_64_float:   # @__device_stub__cuda_minimum_64_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_minimum_64_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end48:
	.size	__device_stub__cuda_minimum_64_float, .Lfunc_end48-__device_stub__cuda_minimum_64_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_minimum_32_float # -- Begin function __device_stub__cuda_minimum_32_float
	.type	__device_stub__cuda_minimum_32_float,@function
__device_stub__cuda_minimum_32_float:   # @__device_stub__cuda_minimum_32_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_minimum_32_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end49:
	.size	__device_stub__cuda_minimum_32_float, .Lfunc_end49-__device_stub__cuda_minimum_32_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_minimum_16_float # -- Begin function __device_stub__cuda_minimum_16_float
	.type	__device_stub__cuda_minimum_16_float,@function
__device_stub__cuda_minimum_16_float:   # @__device_stub__cuda_minimum_16_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_minimum_16_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end50:
	.size	__device_stub__cuda_minimum_16_float, .Lfunc_end50-__device_stub__cuda_minimum_16_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_minimum_8_float # -- Begin function __device_stub__cuda_minimum_8_float
	.type	__device_stub__cuda_minimum_8_float,@function
__device_stub__cuda_minimum_8_float:    # @__device_stub__cuda_minimum_8_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_minimum_8_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end51:
	.size	__device_stub__cuda_minimum_8_float, .Lfunc_end51-__device_stub__cuda_minimum_8_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_minimum_4_float # -- Begin function __device_stub__cuda_minimum_4_float
	.type	__device_stub__cuda_minimum_4_float,@function
__device_stub__cuda_minimum_4_float:    # @__device_stub__cuda_minimum_4_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_minimum_4_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end52:
	.size	__device_stub__cuda_minimum_4_float, .Lfunc_end52-__device_stub__cuda_minimum_4_float
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__cuda_minimum_2_float # -- Begin function __device_stub__cuda_minimum_2_float
	.type	__device_stub__cuda_minimum_2_float,@function
__device_stub__cuda_minimum_2_float:    # @__device_stub__cuda_minimum_2_float
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$cuda_minimum_2_float, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end53:
	.size	__device_stub__cuda_minimum_2_float, .Lfunc_end53-__device_stub__cuda_minimum_2_float
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB54_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB54_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_sum_512_double, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_sum_256_double, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_sum_128_double, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_sum_64_double, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_sum_32_double, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_sum_16_double, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_sum_8_double, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_sum_4_double, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_sum_2_double, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_sum_512_float, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_sum_256_float, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_sum_128_float, %esi
	movl	$.L__unnamed_12, %edx
	movl	$.L__unnamed_12, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_sum_64_float, %esi
	movl	$.L__unnamed_13, %edx
	movl	$.L__unnamed_13, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_sum_32_float, %esi
	movl	$.L__unnamed_14, %edx
	movl	$.L__unnamed_14, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_sum_16_float, %esi
	movl	$.L__unnamed_15, %edx
	movl	$.L__unnamed_15, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_sum_8_float, %esi
	movl	$.L__unnamed_16, %edx
	movl	$.L__unnamed_16, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_sum_4_float, %esi
	movl	$.L__unnamed_17, %edx
	movl	$.L__unnamed_17, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_sum_2_float, %esi
	movl	$.L__unnamed_18, %edx
	movl	$.L__unnamed_18, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_maximum_512_double, %esi
	movl	$.L__unnamed_19, %edx
	movl	$.L__unnamed_19, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_maximum_256_double, %esi
	movl	$.L__unnamed_20, %edx
	movl	$.L__unnamed_20, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_maximum_128_double, %esi
	movl	$.L__unnamed_21, %edx
	movl	$.L__unnamed_21, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_maximum_64_double, %esi
	movl	$.L__unnamed_22, %edx
	movl	$.L__unnamed_22, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_maximum_32_double, %esi
	movl	$.L__unnamed_23, %edx
	movl	$.L__unnamed_23, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_maximum_16_double, %esi
	movl	$.L__unnamed_24, %edx
	movl	$.L__unnamed_24, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_maximum_8_double, %esi
	movl	$.L__unnamed_25, %edx
	movl	$.L__unnamed_25, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_maximum_4_double, %esi
	movl	$.L__unnamed_26, %edx
	movl	$.L__unnamed_26, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_maximum_2_double, %esi
	movl	$.L__unnamed_27, %edx
	movl	$.L__unnamed_27, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_maximum_512_float, %esi
	movl	$.L__unnamed_28, %edx
	movl	$.L__unnamed_28, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_maximum_256_float, %esi
	movl	$.L__unnamed_29, %edx
	movl	$.L__unnamed_29, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_maximum_128_float, %esi
	movl	$.L__unnamed_30, %edx
	movl	$.L__unnamed_30, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_maximum_64_float, %esi
	movl	$.L__unnamed_31, %edx
	movl	$.L__unnamed_31, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_maximum_32_float, %esi
	movl	$.L__unnamed_32, %edx
	movl	$.L__unnamed_32, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_maximum_16_float, %esi
	movl	$.L__unnamed_33, %edx
	movl	$.L__unnamed_33, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_maximum_8_float, %esi
	movl	$.L__unnamed_34, %edx
	movl	$.L__unnamed_34, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_maximum_4_float, %esi
	movl	$.L__unnamed_35, %edx
	movl	$.L__unnamed_35, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_maximum_2_float, %esi
	movl	$.L__unnamed_36, %edx
	movl	$.L__unnamed_36, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_minimum_512_double, %esi
	movl	$.L__unnamed_37, %edx
	movl	$.L__unnamed_37, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_minimum_256_double, %esi
	movl	$.L__unnamed_38, %edx
	movl	$.L__unnamed_38, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_minimum_128_double, %esi
	movl	$.L__unnamed_39, %edx
	movl	$.L__unnamed_39, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_minimum_64_double, %esi
	movl	$.L__unnamed_40, %edx
	movl	$.L__unnamed_40, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_minimum_32_double, %esi
	movl	$.L__unnamed_41, %edx
	movl	$.L__unnamed_41, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_minimum_16_double, %esi
	movl	$.L__unnamed_42, %edx
	movl	$.L__unnamed_42, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_minimum_8_double, %esi
	movl	$.L__unnamed_43, %edx
	movl	$.L__unnamed_43, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_minimum_4_double, %esi
	movl	$.L__unnamed_44, %edx
	movl	$.L__unnamed_44, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_minimum_2_double, %esi
	movl	$.L__unnamed_45, %edx
	movl	$.L__unnamed_45, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_minimum_512_float, %esi
	movl	$.L__unnamed_46, %edx
	movl	$.L__unnamed_46, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_minimum_256_float, %esi
	movl	$.L__unnamed_47, %edx
	movl	$.L__unnamed_47, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_minimum_128_float, %esi
	movl	$.L__unnamed_48, %edx
	movl	$.L__unnamed_48, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_minimum_64_float, %esi
	movl	$.L__unnamed_49, %edx
	movl	$.L__unnamed_49, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_minimum_32_float, %esi
	movl	$.L__unnamed_50, %edx
	movl	$.L__unnamed_50, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_minimum_16_float, %esi
	movl	$.L__unnamed_51, %edx
	movl	$.L__unnamed_51, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$cuda_minimum_8_float, %esi
	movl	$.L__unnamed_52, %edx
	movl	$.L__unnamed_52, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movq	$0, 24(%rsp)
	movq	$0, 16(%rsp)
	movq	$0, 8(%rsp)
	movq	$0, (%rsp)
	movl	$cuda_minimum_4_float, %esi
	movl	$.L__unnamed_53, %edx
	movl	$.L__unnamed_53, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movq	$0, 24(%rsp)
	movq	$0, 16(%rsp)
	movq	$0, 8(%rsp)
	movq	$0, (%rsp)
	movl	$cuda_minimum_2_float, %esi
	movl	$.L__unnamed_54, %edx
	movl	$.L__unnamed_54, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end54:
	.size	__hip_module_ctor, .Lfunc_end54-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB55_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB55_2:
	retq
.Lfunc_end55:
	.size	__hip_module_dtor, .Lfunc_end55-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	cuda_sum_512_double,@object     # @cuda_sum_512_double
	.section	.rodata,"a",@progbits
	.globl	cuda_sum_512_double
	.p2align	3, 0x0
cuda_sum_512_double:
	.quad	__device_stub__cuda_sum_512_double
	.size	cuda_sum_512_double, 8

	.type	cuda_sum_256_double,@object     # @cuda_sum_256_double
	.globl	cuda_sum_256_double
	.p2align	3, 0x0
cuda_sum_256_double:
	.quad	__device_stub__cuda_sum_256_double
	.size	cuda_sum_256_double, 8

	.type	cuda_sum_128_double,@object     # @cuda_sum_128_double
	.globl	cuda_sum_128_double
	.p2align	3, 0x0
cuda_sum_128_double:
	.quad	__device_stub__cuda_sum_128_double
	.size	cuda_sum_128_double, 8

	.type	cuda_sum_64_double,@object      # @cuda_sum_64_double
	.globl	cuda_sum_64_double
	.p2align	3, 0x0
cuda_sum_64_double:
	.quad	__device_stub__cuda_sum_64_double
	.size	cuda_sum_64_double, 8

	.type	cuda_sum_32_double,@object      # @cuda_sum_32_double
	.globl	cuda_sum_32_double
	.p2align	3, 0x0
cuda_sum_32_double:
	.quad	__device_stub__cuda_sum_32_double
	.size	cuda_sum_32_double, 8

	.type	cuda_sum_16_double,@object      # @cuda_sum_16_double
	.globl	cuda_sum_16_double
	.p2align	3, 0x0
cuda_sum_16_double:
	.quad	__device_stub__cuda_sum_16_double
	.size	cuda_sum_16_double, 8

	.type	cuda_sum_8_double,@object       # @cuda_sum_8_double
	.globl	cuda_sum_8_double
	.p2align	3, 0x0
cuda_sum_8_double:
	.quad	__device_stub__cuda_sum_8_double
	.size	cuda_sum_8_double, 8

	.type	cuda_sum_4_double,@object       # @cuda_sum_4_double
	.globl	cuda_sum_4_double
	.p2align	3, 0x0
cuda_sum_4_double:
	.quad	__device_stub__cuda_sum_4_double
	.size	cuda_sum_4_double, 8

	.type	cuda_sum_2_double,@object       # @cuda_sum_2_double
	.globl	cuda_sum_2_double
	.p2align	3, 0x0
cuda_sum_2_double:
	.quad	__device_stub__cuda_sum_2_double
	.size	cuda_sum_2_double, 8

	.type	cuda_sum_512_float,@object      # @cuda_sum_512_float
	.globl	cuda_sum_512_float
	.p2align	3, 0x0
cuda_sum_512_float:
	.quad	__device_stub__cuda_sum_512_float
	.size	cuda_sum_512_float, 8

	.type	cuda_sum_256_float,@object      # @cuda_sum_256_float
	.globl	cuda_sum_256_float
	.p2align	3, 0x0
cuda_sum_256_float:
	.quad	__device_stub__cuda_sum_256_float
	.size	cuda_sum_256_float, 8

	.type	cuda_sum_128_float,@object      # @cuda_sum_128_float
	.globl	cuda_sum_128_float
	.p2align	3, 0x0
cuda_sum_128_float:
	.quad	__device_stub__cuda_sum_128_float
	.size	cuda_sum_128_float, 8

	.type	cuda_sum_64_float,@object       # @cuda_sum_64_float
	.globl	cuda_sum_64_float
	.p2align	3, 0x0
cuda_sum_64_float:
	.quad	__device_stub__cuda_sum_64_float
	.size	cuda_sum_64_float, 8

	.type	cuda_sum_32_float,@object       # @cuda_sum_32_float
	.globl	cuda_sum_32_float
	.p2align	3, 0x0
cuda_sum_32_float:
	.quad	__device_stub__cuda_sum_32_float
	.size	cuda_sum_32_float, 8

	.type	cuda_sum_16_float,@object       # @cuda_sum_16_float
	.globl	cuda_sum_16_float
	.p2align	3, 0x0
cuda_sum_16_float:
	.quad	__device_stub__cuda_sum_16_float
	.size	cuda_sum_16_float, 8

	.type	cuda_sum_8_float,@object        # @cuda_sum_8_float
	.globl	cuda_sum_8_float
	.p2align	3, 0x0
cuda_sum_8_float:
	.quad	__device_stub__cuda_sum_8_float
	.size	cuda_sum_8_float, 8

	.type	cuda_sum_4_float,@object        # @cuda_sum_4_float
	.globl	cuda_sum_4_float
	.p2align	3, 0x0
cuda_sum_4_float:
	.quad	__device_stub__cuda_sum_4_float
	.size	cuda_sum_4_float, 8

	.type	cuda_sum_2_float,@object        # @cuda_sum_2_float
	.globl	cuda_sum_2_float
	.p2align	3, 0x0
cuda_sum_2_float:
	.quad	__device_stub__cuda_sum_2_float
	.size	cuda_sum_2_float, 8

	.type	cuda_maximum_512_double,@object # @cuda_maximum_512_double
	.globl	cuda_maximum_512_double
	.p2align	3, 0x0
cuda_maximum_512_double:
	.quad	__device_stub__cuda_maximum_512_double
	.size	cuda_maximum_512_double, 8

	.type	cuda_maximum_256_double,@object # @cuda_maximum_256_double
	.globl	cuda_maximum_256_double
	.p2align	3, 0x0
cuda_maximum_256_double:
	.quad	__device_stub__cuda_maximum_256_double
	.size	cuda_maximum_256_double, 8

	.type	cuda_maximum_128_double,@object # @cuda_maximum_128_double
	.globl	cuda_maximum_128_double
	.p2align	3, 0x0
cuda_maximum_128_double:
	.quad	__device_stub__cuda_maximum_128_double
	.size	cuda_maximum_128_double, 8

	.type	cuda_maximum_64_double,@object  # @cuda_maximum_64_double
	.globl	cuda_maximum_64_double
	.p2align	3, 0x0
cuda_maximum_64_double:
	.quad	__device_stub__cuda_maximum_64_double
	.size	cuda_maximum_64_double, 8

	.type	cuda_maximum_32_double,@object  # @cuda_maximum_32_double
	.globl	cuda_maximum_32_double
	.p2align	3, 0x0
cuda_maximum_32_double:
	.quad	__device_stub__cuda_maximum_32_double
	.size	cuda_maximum_32_double, 8

	.type	cuda_maximum_16_double,@object  # @cuda_maximum_16_double
	.globl	cuda_maximum_16_double
	.p2align	3, 0x0
cuda_maximum_16_double:
	.quad	__device_stub__cuda_maximum_16_double
	.size	cuda_maximum_16_double, 8

	.type	cuda_maximum_8_double,@object   # @cuda_maximum_8_double
	.globl	cuda_maximum_8_double
	.p2align	3, 0x0
cuda_maximum_8_double:
	.quad	__device_stub__cuda_maximum_8_double
	.size	cuda_maximum_8_double, 8

	.type	cuda_maximum_4_double,@object   # @cuda_maximum_4_double
	.globl	cuda_maximum_4_double
	.p2align	3, 0x0
cuda_maximum_4_double:
	.quad	__device_stub__cuda_maximum_4_double
	.size	cuda_maximum_4_double, 8

	.type	cuda_maximum_2_double,@object   # @cuda_maximum_2_double
	.globl	cuda_maximum_2_double
	.p2align	3, 0x0
cuda_maximum_2_double:
	.quad	__device_stub__cuda_maximum_2_double
	.size	cuda_maximum_2_double, 8

	.type	cuda_maximum_512_float,@object  # @cuda_maximum_512_float
	.globl	cuda_maximum_512_float
	.p2align	3, 0x0
cuda_maximum_512_float:
	.quad	__device_stub__cuda_maximum_512_float
	.size	cuda_maximum_512_float, 8

	.type	cuda_maximum_256_float,@object  # @cuda_maximum_256_float
	.globl	cuda_maximum_256_float
	.p2align	3, 0x0
cuda_maximum_256_float:
	.quad	__device_stub__cuda_maximum_256_float
	.size	cuda_maximum_256_float, 8

	.type	cuda_maximum_128_float,@object  # @cuda_maximum_128_float
	.globl	cuda_maximum_128_float
	.p2align	3, 0x0
cuda_maximum_128_float:
	.quad	__device_stub__cuda_maximum_128_float
	.size	cuda_maximum_128_float, 8

	.type	cuda_maximum_64_float,@object   # @cuda_maximum_64_float
	.globl	cuda_maximum_64_float
	.p2align	3, 0x0
cuda_maximum_64_float:
	.quad	__device_stub__cuda_maximum_64_float
	.size	cuda_maximum_64_float, 8

	.type	cuda_maximum_32_float,@object   # @cuda_maximum_32_float
	.globl	cuda_maximum_32_float
	.p2align	3, 0x0
cuda_maximum_32_float:
	.quad	__device_stub__cuda_maximum_32_float
	.size	cuda_maximum_32_float, 8

	.type	cuda_maximum_16_float,@object   # @cuda_maximum_16_float
	.globl	cuda_maximum_16_float
	.p2align	3, 0x0
cuda_maximum_16_float:
	.quad	__device_stub__cuda_maximum_16_float
	.size	cuda_maximum_16_float, 8

	.type	cuda_maximum_8_float,@object    # @cuda_maximum_8_float
	.globl	cuda_maximum_8_float
	.p2align	3, 0x0
cuda_maximum_8_float:
	.quad	__device_stub__cuda_maximum_8_float
	.size	cuda_maximum_8_float, 8

	.type	cuda_maximum_4_float,@object    # @cuda_maximum_4_float
	.globl	cuda_maximum_4_float
	.p2align	3, 0x0
cuda_maximum_4_float:
	.quad	__device_stub__cuda_maximum_4_float
	.size	cuda_maximum_4_float, 8

	.type	cuda_maximum_2_float,@object    # @cuda_maximum_2_float
	.globl	cuda_maximum_2_float
	.p2align	3, 0x0
cuda_maximum_2_float:
	.quad	__device_stub__cuda_maximum_2_float
	.size	cuda_maximum_2_float, 8

	.type	cuda_minimum_512_double,@object # @cuda_minimum_512_double
	.globl	cuda_minimum_512_double
	.p2align	3, 0x0
cuda_minimum_512_double:
	.quad	__device_stub__cuda_minimum_512_double
	.size	cuda_minimum_512_double, 8

	.type	cuda_minimum_256_double,@object # @cuda_minimum_256_double
	.globl	cuda_minimum_256_double
	.p2align	3, 0x0
cuda_minimum_256_double:
	.quad	__device_stub__cuda_minimum_256_double
	.size	cuda_minimum_256_double, 8

	.type	cuda_minimum_128_double,@object # @cuda_minimum_128_double
	.globl	cuda_minimum_128_double
	.p2align	3, 0x0
cuda_minimum_128_double:
	.quad	__device_stub__cuda_minimum_128_double
	.size	cuda_minimum_128_double, 8

	.type	cuda_minimum_64_double,@object  # @cuda_minimum_64_double
	.globl	cuda_minimum_64_double
	.p2align	3, 0x0
cuda_minimum_64_double:
	.quad	__device_stub__cuda_minimum_64_double
	.size	cuda_minimum_64_double, 8

	.type	cuda_minimum_32_double,@object  # @cuda_minimum_32_double
	.globl	cuda_minimum_32_double
	.p2align	3, 0x0
cuda_minimum_32_double:
	.quad	__device_stub__cuda_minimum_32_double
	.size	cuda_minimum_32_double, 8

	.type	cuda_minimum_16_double,@object  # @cuda_minimum_16_double
	.globl	cuda_minimum_16_double
	.p2align	3, 0x0
cuda_minimum_16_double:
	.quad	__device_stub__cuda_minimum_16_double
	.size	cuda_minimum_16_double, 8

	.type	cuda_minimum_8_double,@object   # @cuda_minimum_8_double
	.globl	cuda_minimum_8_double
	.p2align	3, 0x0
cuda_minimum_8_double:
	.quad	__device_stub__cuda_minimum_8_double
	.size	cuda_minimum_8_double, 8

	.type	cuda_minimum_4_double,@object   # @cuda_minimum_4_double
	.globl	cuda_minimum_4_double
	.p2align	3, 0x0
cuda_minimum_4_double:
	.quad	__device_stub__cuda_minimum_4_double
	.size	cuda_minimum_4_double, 8

	.type	cuda_minimum_2_double,@object   # @cuda_minimum_2_double
	.globl	cuda_minimum_2_double
	.p2align	3, 0x0
cuda_minimum_2_double:
	.quad	__device_stub__cuda_minimum_2_double
	.size	cuda_minimum_2_double, 8

	.type	cuda_minimum_512_float,@object  # @cuda_minimum_512_float
	.globl	cuda_minimum_512_float
	.p2align	3, 0x0
cuda_minimum_512_float:
	.quad	__device_stub__cuda_minimum_512_float
	.size	cuda_minimum_512_float, 8

	.type	cuda_minimum_256_float,@object  # @cuda_minimum_256_float
	.globl	cuda_minimum_256_float
	.p2align	3, 0x0
cuda_minimum_256_float:
	.quad	__device_stub__cuda_minimum_256_float
	.size	cuda_minimum_256_float, 8

	.type	cuda_minimum_128_float,@object  # @cuda_minimum_128_float
	.globl	cuda_minimum_128_float
	.p2align	3, 0x0
cuda_minimum_128_float:
	.quad	__device_stub__cuda_minimum_128_float
	.size	cuda_minimum_128_float, 8

	.type	cuda_minimum_64_float,@object   # @cuda_minimum_64_float
	.globl	cuda_minimum_64_float
	.p2align	3, 0x0
cuda_minimum_64_float:
	.quad	__device_stub__cuda_minimum_64_float
	.size	cuda_minimum_64_float, 8

	.type	cuda_minimum_32_float,@object   # @cuda_minimum_32_float
	.globl	cuda_minimum_32_float
	.p2align	3, 0x0
cuda_minimum_32_float:
	.quad	__device_stub__cuda_minimum_32_float
	.size	cuda_minimum_32_float, 8

	.type	cuda_minimum_16_float,@object   # @cuda_minimum_16_float
	.globl	cuda_minimum_16_float
	.p2align	3, 0x0
cuda_minimum_16_float:
	.quad	__device_stub__cuda_minimum_16_float
	.size	cuda_minimum_16_float, 8

	.type	cuda_minimum_8_float,@object    # @cuda_minimum_8_float
	.globl	cuda_minimum_8_float
	.p2align	3, 0x0
cuda_minimum_8_float:
	.quad	__device_stub__cuda_minimum_8_float
	.size	cuda_minimum_8_float, 8

	.type	cuda_minimum_4_float,@object    # @cuda_minimum_4_float
	.globl	cuda_minimum_4_float
	.p2align	3, 0x0
cuda_minimum_4_float:
	.quad	__device_stub__cuda_minimum_4_float
	.size	cuda_minimum_4_float, 8

	.type	cuda_minimum_2_float,@object    # @cuda_minimum_2_float
	.globl	cuda_minimum_2_float
	.p2align	3, 0x0
cuda_minimum_2_float:
	.quad	__device_stub__cuda_minimum_2_float
	.size	cuda_minimum_2_float, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"cuda_sum_512_double"
	.size	.L__unnamed_1, 20

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"cuda_sum_256_double"
	.size	.L__unnamed_2, 20

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"cuda_sum_128_double"
	.size	.L__unnamed_3, 20

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"cuda_sum_64_double"
	.size	.L__unnamed_4, 19

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"cuda_sum_32_double"
	.size	.L__unnamed_5, 19

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"cuda_sum_16_double"
	.size	.L__unnamed_6, 19

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"cuda_sum_8_double"
	.size	.L__unnamed_7, 18

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"cuda_sum_4_double"
	.size	.L__unnamed_8, 18

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"cuda_sum_2_double"
	.size	.L__unnamed_9, 18

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"cuda_sum_512_float"
	.size	.L__unnamed_10, 19

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"cuda_sum_256_float"
	.size	.L__unnamed_11, 19

	.type	.L__unnamed_12,@object          # @11
.L__unnamed_12:
	.asciz	"cuda_sum_128_float"
	.size	.L__unnamed_12, 19

	.type	.L__unnamed_13,@object          # @12
.L__unnamed_13:
	.asciz	"cuda_sum_64_float"
	.size	.L__unnamed_13, 18

	.type	.L__unnamed_14,@object          # @13
.L__unnamed_14:
	.asciz	"cuda_sum_32_float"
	.size	.L__unnamed_14, 18

	.type	.L__unnamed_15,@object          # @14
.L__unnamed_15:
	.asciz	"cuda_sum_16_float"
	.size	.L__unnamed_15, 18

	.type	.L__unnamed_16,@object          # @15
.L__unnamed_16:
	.asciz	"cuda_sum_8_float"
	.size	.L__unnamed_16, 17

	.type	.L__unnamed_17,@object          # @16
.L__unnamed_17:
	.asciz	"cuda_sum_4_float"
	.size	.L__unnamed_17, 17

	.type	.L__unnamed_18,@object          # @17
.L__unnamed_18:
	.asciz	"cuda_sum_2_float"
	.size	.L__unnamed_18, 17

	.type	.L__unnamed_19,@object          # @18
.L__unnamed_19:
	.asciz	"cuda_maximum_512_double"
	.size	.L__unnamed_19, 24

	.type	.L__unnamed_20,@object          # @19
.L__unnamed_20:
	.asciz	"cuda_maximum_256_double"
	.size	.L__unnamed_20, 24

	.type	.L__unnamed_21,@object          # @20
.L__unnamed_21:
	.asciz	"cuda_maximum_128_double"
	.size	.L__unnamed_21, 24

	.type	.L__unnamed_22,@object          # @21
.L__unnamed_22:
	.asciz	"cuda_maximum_64_double"
	.size	.L__unnamed_22, 23

	.type	.L__unnamed_23,@object          # @22
.L__unnamed_23:
	.asciz	"cuda_maximum_32_double"
	.size	.L__unnamed_23, 23

	.type	.L__unnamed_24,@object          # @23
.L__unnamed_24:
	.asciz	"cuda_maximum_16_double"
	.size	.L__unnamed_24, 23

	.type	.L__unnamed_25,@object          # @24
.L__unnamed_25:
	.asciz	"cuda_maximum_8_double"
	.size	.L__unnamed_25, 22

	.type	.L__unnamed_26,@object          # @25
.L__unnamed_26:
	.asciz	"cuda_maximum_4_double"
	.size	.L__unnamed_26, 22

	.type	.L__unnamed_27,@object          # @26
.L__unnamed_27:
	.asciz	"cuda_maximum_2_double"
	.size	.L__unnamed_27, 22

	.type	.L__unnamed_28,@object          # @27
.L__unnamed_28:
	.asciz	"cuda_maximum_512_float"
	.size	.L__unnamed_28, 23

	.type	.L__unnamed_29,@object          # @28
.L__unnamed_29:
	.asciz	"cuda_maximum_256_float"
	.size	.L__unnamed_29, 23

	.type	.L__unnamed_30,@object          # @29
.L__unnamed_30:
	.asciz	"cuda_maximum_128_float"
	.size	.L__unnamed_30, 23

	.type	.L__unnamed_31,@object          # @30
.L__unnamed_31:
	.asciz	"cuda_maximum_64_float"
	.size	.L__unnamed_31, 22

	.type	.L__unnamed_32,@object          # @31
.L__unnamed_32:
	.asciz	"cuda_maximum_32_float"
	.size	.L__unnamed_32, 22

	.type	.L__unnamed_33,@object          # @32
.L__unnamed_33:
	.asciz	"cuda_maximum_16_float"
	.size	.L__unnamed_33, 22

	.type	.L__unnamed_34,@object          # @33
.L__unnamed_34:
	.asciz	"cuda_maximum_8_float"
	.size	.L__unnamed_34, 21

	.type	.L__unnamed_35,@object          # @34
.L__unnamed_35:
	.asciz	"cuda_maximum_4_float"
	.size	.L__unnamed_35, 21

	.type	.L__unnamed_36,@object          # @35
.L__unnamed_36:
	.asciz	"cuda_maximum_2_float"
	.size	.L__unnamed_36, 21

	.type	.L__unnamed_37,@object          # @36
.L__unnamed_37:
	.asciz	"cuda_minimum_512_double"
	.size	.L__unnamed_37, 24

	.type	.L__unnamed_38,@object          # @37
.L__unnamed_38:
	.asciz	"cuda_minimum_256_double"
	.size	.L__unnamed_38, 24

	.type	.L__unnamed_39,@object          # @38
.L__unnamed_39:
	.asciz	"cuda_minimum_128_double"
	.size	.L__unnamed_39, 24

	.type	.L__unnamed_40,@object          # @39
.L__unnamed_40:
	.asciz	"cuda_minimum_64_double"
	.size	.L__unnamed_40, 23

	.type	.L__unnamed_41,@object          # @40
.L__unnamed_41:
	.asciz	"cuda_minimum_32_double"
	.size	.L__unnamed_41, 23

	.type	.L__unnamed_42,@object          # @41
.L__unnamed_42:
	.asciz	"cuda_minimum_16_double"
	.size	.L__unnamed_42, 23

	.type	.L__unnamed_43,@object          # @42
.L__unnamed_43:
	.asciz	"cuda_minimum_8_double"
	.size	.L__unnamed_43, 22

	.type	.L__unnamed_44,@object          # @43
.L__unnamed_44:
	.asciz	"cuda_minimum_4_double"
	.size	.L__unnamed_44, 22

	.type	.L__unnamed_45,@object          # @44
.L__unnamed_45:
	.asciz	"cuda_minimum_2_double"
	.size	.L__unnamed_45, 22

	.type	.L__unnamed_46,@object          # @45
.L__unnamed_46:
	.asciz	"cuda_minimum_512_float"
	.size	.L__unnamed_46, 23

	.type	.L__unnamed_47,@object          # @46
.L__unnamed_47:
	.asciz	"cuda_minimum_256_float"
	.size	.L__unnamed_47, 23

	.type	.L__unnamed_48,@object          # @47
.L__unnamed_48:
	.asciz	"cuda_minimum_128_float"
	.size	.L__unnamed_48, 23

	.type	.L__unnamed_49,@object          # @48
.L__unnamed_49:
	.asciz	"cuda_minimum_64_float"
	.size	.L__unnamed_49, 22

	.type	.L__unnamed_50,@object          # @49
.L__unnamed_50:
	.asciz	"cuda_minimum_32_float"
	.size	.L__unnamed_50, 22

	.type	.L__unnamed_51,@object          # @50
.L__unnamed_51:
	.asciz	"cuda_minimum_16_float"
	.size	.L__unnamed_51, 22

	.type	.L__unnamed_52,@object          # @51
.L__unnamed_52:
	.asciz	"cuda_minimum_8_float"
	.size	.L__unnamed_52, 21

	.type	.L__unnamed_53,@object          # @52
.L__unnamed_53:
	.asciz	"cuda_minimum_4_float"
	.size	.L__unnamed_53, 21

	.type	.L__unnamed_54,@object          # @53
.L__unnamed_54:
	.asciz	"cuda_minimum_2_float"
	.size	.L__unnamed_54, 21

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__cuda_sum_512_double
	.addrsig_sym __device_stub__cuda_sum_256_double
	.addrsig_sym __device_stub__cuda_sum_128_double
	.addrsig_sym __device_stub__cuda_sum_64_double
	.addrsig_sym __device_stub__cuda_sum_32_double
	.addrsig_sym __device_stub__cuda_sum_16_double
	.addrsig_sym __device_stub__cuda_sum_8_double
	.addrsig_sym __device_stub__cuda_sum_4_double
	.addrsig_sym __device_stub__cuda_sum_2_double
	.addrsig_sym __device_stub__cuda_sum_512_float
	.addrsig_sym __device_stub__cuda_sum_256_float
	.addrsig_sym __device_stub__cuda_sum_128_float
	.addrsig_sym __device_stub__cuda_sum_64_float
	.addrsig_sym __device_stub__cuda_sum_32_float
	.addrsig_sym __device_stub__cuda_sum_16_float
	.addrsig_sym __device_stub__cuda_sum_8_float
	.addrsig_sym __device_stub__cuda_sum_4_float
	.addrsig_sym __device_stub__cuda_sum_2_float
	.addrsig_sym __device_stub__cuda_maximum_512_double
	.addrsig_sym __device_stub__cuda_maximum_256_double
	.addrsig_sym __device_stub__cuda_maximum_128_double
	.addrsig_sym __device_stub__cuda_maximum_64_double
	.addrsig_sym __device_stub__cuda_maximum_32_double
	.addrsig_sym __device_stub__cuda_maximum_16_double
	.addrsig_sym __device_stub__cuda_maximum_8_double
	.addrsig_sym __device_stub__cuda_maximum_4_double
	.addrsig_sym __device_stub__cuda_maximum_2_double
	.addrsig_sym __device_stub__cuda_maximum_512_float
	.addrsig_sym __device_stub__cuda_maximum_256_float
	.addrsig_sym __device_stub__cuda_maximum_128_float
	.addrsig_sym __device_stub__cuda_maximum_64_float
	.addrsig_sym __device_stub__cuda_maximum_32_float
	.addrsig_sym __device_stub__cuda_maximum_16_float
	.addrsig_sym __device_stub__cuda_maximum_8_float
	.addrsig_sym __device_stub__cuda_maximum_4_float
	.addrsig_sym __device_stub__cuda_maximum_2_float
	.addrsig_sym __device_stub__cuda_minimum_512_double
	.addrsig_sym __device_stub__cuda_minimum_256_double
	.addrsig_sym __device_stub__cuda_minimum_128_double
	.addrsig_sym __device_stub__cuda_minimum_64_double
	.addrsig_sym __device_stub__cuda_minimum_32_double
	.addrsig_sym __device_stub__cuda_minimum_16_double
	.addrsig_sym __device_stub__cuda_minimum_8_double
	.addrsig_sym __device_stub__cuda_minimum_4_double
	.addrsig_sym __device_stub__cuda_minimum_2_double
	.addrsig_sym __device_stub__cuda_minimum_512_float
	.addrsig_sym __device_stub__cuda_minimum_256_float
	.addrsig_sym __device_stub__cuda_minimum_128_float
	.addrsig_sym __device_stub__cuda_minimum_64_float
	.addrsig_sym __device_stub__cuda_minimum_32_float
	.addrsig_sym __device_stub__cuda_minimum_16_float
	.addrsig_sym __device_stub__cuda_minimum_8_float
	.addrsig_sym __device_stub__cuda_minimum_4_float
	.addrsig_sym __device_stub__cuda_minimum_2_float
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym cuda_sum_512_double
	.addrsig_sym cuda_sum_256_double
	.addrsig_sym cuda_sum_128_double
	.addrsig_sym cuda_sum_64_double
	.addrsig_sym cuda_sum_32_double
	.addrsig_sym cuda_sum_16_double
	.addrsig_sym cuda_sum_8_double
	.addrsig_sym cuda_sum_4_double
	.addrsig_sym cuda_sum_2_double
	.addrsig_sym cuda_sum_512_float
	.addrsig_sym cuda_sum_256_float
	.addrsig_sym cuda_sum_128_float
	.addrsig_sym cuda_sum_64_float
	.addrsig_sym cuda_sum_32_float
	.addrsig_sym cuda_sum_16_float
	.addrsig_sym cuda_sum_8_float
	.addrsig_sym cuda_sum_4_float
	.addrsig_sym cuda_sum_2_float
	.addrsig_sym cuda_maximum_512_double
	.addrsig_sym cuda_maximum_256_double
	.addrsig_sym cuda_maximum_128_double
	.addrsig_sym cuda_maximum_64_double
	.addrsig_sym cuda_maximum_32_double
	.addrsig_sym cuda_maximum_16_double
	.addrsig_sym cuda_maximum_8_double
	.addrsig_sym cuda_maximum_4_double
	.addrsig_sym cuda_maximum_2_double
	.addrsig_sym cuda_maximum_512_float
	.addrsig_sym cuda_maximum_256_float
	.addrsig_sym cuda_maximum_128_float
	.addrsig_sym cuda_maximum_64_float
	.addrsig_sym cuda_maximum_32_float
	.addrsig_sym cuda_maximum_16_float
	.addrsig_sym cuda_maximum_8_float
	.addrsig_sym cuda_maximum_4_float
	.addrsig_sym cuda_maximum_2_float
	.addrsig_sym cuda_minimum_512_double
	.addrsig_sym cuda_minimum_256_double
	.addrsig_sym cuda_minimum_128_double
	.addrsig_sym cuda_minimum_64_double
	.addrsig_sym cuda_minimum_32_double
	.addrsig_sym cuda_minimum_16_double
	.addrsig_sym cuda_minimum_8_double
	.addrsig_sym cuda_minimum_4_double
	.addrsig_sym cuda_minimum_2_double
	.addrsig_sym cuda_minimum_512_float
	.addrsig_sym cuda_minimum_256_float
	.addrsig_sym cuda_minimum_128_float
	.addrsig_sym cuda_minimum_64_float
	.addrsig_sym cuda_minimum_32_float
	.addrsig_sym cuda_minimum_16_float
	.addrsig_sym cuda_minimum_8_float
	.addrsig_sym cuda_minimum_4_float
	.addrsig_sym cuda_minimum_2_float
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	cuda_sum_512_double     ; -- Begin function cuda_sum_512_double
	.globl	cuda_sum_512_double
	.p2align	8
	.type	cuda_sum_512_double,@function
cuda_sum_512_double:                    ; @cuda_sum_512_double
; %bb.0:
	s_clause 0x2
	s_load_b256 s[16:23], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x38
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 9, v0
	v_lshl_add_u32 v7, v0, 3, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s19
	s_mul_hi_u32 s3, s14, s18
	s_mul_i32 s19, s15, s21
	s_mul_hi_u32 s21, s15, s20
	s_mul_i32 s18, s14, s18
	s_mul_i32 s20, s15, s20
	s_add_i32 s3, s3, s2
	s_add_i32 s21, s21, s19
	s_add_u32 s18, s20, s18
	s_addc_u32 s19, s21, s3
	s_add_u32 s2, s0, 56
	s_addc_u32 s3, s1, 0
	s_lshl_b32 s0, s12, 9
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s16, 0
	s_lshl_b64 s[20:21], s[18:19], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s20, s20, s6
	s_addc_u32 s21, s21, s7
	v_mad_u64_u32 v[5:6], null, v1, s17, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s0, v1
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s20, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s21, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v7, v[3:4]
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB0_6
; %bb.3:                                ; %.lr.ph.i
	ds_load_b64 v[3:4], v7
	s_lshl_b64 s[18:19], s[18:19], 3
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, s0, v1
	s_add_u32 s6, s6, s18
	s_addc_u32 s18, s7, s19
	s_mov_b32 s7, 0
.LBB0_4:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v2, s16
	v_mul_lo_u32 v10, v1, s17
	v_mad_u64_u32 v[8:9], null, v1, s16, 0
	v_add3_u32 v9, v9, v10, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	v_add_co_u32 v1, vcc_lo, s6, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s18, v2, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[5:6]
	global_load_b64 v[1:2], v[1:2], off
	s_or_b32 s7, vcc_lo, s7
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[1:2]
	v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v2, v6
	v_add_nc_u32_e32 v5, s0, v5
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_4
; %bb.5:                                ; %._crit_edge.i.loopexit
	s_or_b32 exec_lo, exec_lo, s7
	ds_store_b64 v7, v[3:4]
.LBB0_6:                                ; %Flow31
	s_or_b32 exec_lo, exec_lo, s1
	v_or_b32_e32 v1, 0x100, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s0, 0x100, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s1, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_8
; %bb.7:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[3:4], v1
	ds_load_b64 v[5:6], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[5:6]
	ds_store_b64 v7, v[3:4]
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v1, 0x80, v0
	v_cmp_gt_u32_e64 s0, 0x80, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s1, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_10
; %bb.9:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[3:4], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v7, v[1:2]
.LBB0_10:
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v1, 64, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s0, 64, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s1, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_12
; %bb.11:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[3:4], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v7, v[1:2]
.LBB0_12:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB0_25
; %bb.13:
	v_or_b32_e32 v1, 32, v0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB0_15
; %bb.14:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[3:4], v1
	ds_load_b64 v[5:6], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[5:6]
	ds_store_b64 v7, v[3:4]
.LBB0_15:
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v1, 16, v0
	v_cmp_gt_u32_e64 s0, 16, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB0_17
; %bb.16:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[3:4], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v7, v[1:2]
.LBB0_17:
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s0, 8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB0_19
; %bb.18:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[3:4], v1
	ds_load_b64 v[5:6], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[5:6]
	ds_store_b64 v7, v[3:4]
.LBB0_19:
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v1, 4, v0
	v_cmp_gt_u32_e64 s0, 4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB0_21
; %bb.20:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[3:4], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v7, v[1:2]
.LBB0_21:
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s0, 2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB0_23
; %bb.22:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[3:4], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v7, v[1:2]
.LBB0_23:
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_gt_u64_e64 s0, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_25
; %bb.24:
	v_mov_b32_e32 v5, 0
	ds_load_2addr_b64 v[1:4], v5 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[3:4], v[1:2]
	ds_store_b64 v5, v[1:2]
.LBB0_25:                               ; %Flow30
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s1, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_31
; %bb.26:
	v_cmp_neq_f64_e64 s0, s[10:11], 0
	s_load_b32 s2, s[2:3], 0x4
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, s14
	s_mul_i32 s2, s2, s12
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_add_i32 s0, s2, s13
	s_cbranch_vccz .LBB0_28
; %bb.27:
	s_lshl_b64 s[2:3], s[0:1], 3
	v_mov_b32_e32 v2, 0
	s_add_u32 s4, s8, s2
	s_addc_u32 s5, s9, s3
	s_load_b64 s[2:3], s[4:5], 0x0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[0:1], s[2:3], s[10:11], v[0:1]
	s_mov_b32 s2, 0
	global_store_b64 v2, v[0:1], s[4:5]
	s_branch .LBB0_29
.LBB0_28:
	s_mov_b32 s2, -1
.LBB0_29:                               ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_31
; %bb.30:
	v_mov_b32_e32 v2, 0
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB0_31:                               ; %_Z11cuda_reduceILj512Ed3SumEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_sum_512_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	cuda_sum_512_double, .Lfunc_end0-cuda_sum_512_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1416
; NumSgprs: 26
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_sum_256_double     ; -- Begin function cuda_sum_256_double
	.globl	cuda_sum_256_double
	.p2align	8
	.type	cuda_sum_256_double,@function
cuda_sum_256_double:                    ; @cuda_sum_256_double
; %bb.0:
	s_clause 0x2
	s_load_b256 s[16:23], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x38
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 8, v0
	v_lshl_add_u32 v7, v0, 3, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s19
	s_mul_hi_u32 s3, s14, s18
	s_mul_i32 s19, s15, s21
	s_mul_hi_u32 s21, s15, s20
	s_mul_i32 s18, s14, s18
	s_mul_i32 s20, s15, s20
	s_add_i32 s3, s3, s2
	s_add_i32 s21, s21, s19
	s_add_u32 s18, s20, s18
	s_addc_u32 s19, s21, s3
	s_add_u32 s2, s0, 56
	s_addc_u32 s3, s1, 0
	s_lshl_b32 s0, s12, 8
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB1_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s16, 0
	s_lshl_b64 s[20:21], s[18:19], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s20, s20, s6
	s_addc_u32 s21, s21, s7
	v_mad_u64_u32 v[5:6], null, v1, s17, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s0, v1
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s20, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s21, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v7, v[3:4]
.LBB1_2:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB1_6
; %bb.3:                                ; %.lr.ph.i
	ds_load_b64 v[3:4], v7
	s_lshl_b64 s[18:19], s[18:19], 3
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, s0, v1
	s_add_u32 s6, s6, s18
	s_addc_u32 s18, s7, s19
	s_mov_b32 s7, 0
.LBB1_4:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v2, s16
	v_mul_lo_u32 v10, v1, s17
	v_mad_u64_u32 v[8:9], null, v1, s16, 0
	v_add3_u32 v9, v9, v10, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	v_add_co_u32 v1, vcc_lo, s6, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s18, v2, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[5:6]
	global_load_b64 v[1:2], v[1:2], off
	s_or_b32 s7, vcc_lo, s7
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[1:2]
	v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v2, v6
	v_add_nc_u32_e32 v5, s0, v5
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB1_4
; %bb.5:                                ; %._crit_edge.i.loopexit
	s_or_b32 exec_lo, exec_lo, s7
	ds_store_b64 v7, v[3:4]
.LBB1_6:                                ; %Flow31
	s_or_b32 exec_lo, exec_lo, s1
	v_or_b32_e32 v1, 0x80, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s0, 0x80, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s1, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB1_8
; %bb.7:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[3:4], v1
	ds_load_b64 v[5:6], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[5:6]
	ds_store_b64 v7, v[3:4]
.LBB1_8:
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v1, 64, v0
	v_cmp_gt_u32_e64 s0, 64, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s1, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB1_10
; %bb.9:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[3:4], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v7, v[1:2]
.LBB1_10:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB1_23
; %bb.11:
	v_or_b32_e32 v1, 32, v0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB1_13
; %bb.12:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[3:4], v1
	ds_load_b64 v[5:6], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[5:6]
	ds_store_b64 v7, v[3:4]
.LBB1_13:
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v1, 16, v0
	v_cmp_gt_u32_e64 s0, 16, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB1_15
; %bb.14:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[3:4], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v7, v[1:2]
.LBB1_15:
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s0, 8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB1_17
; %bb.16:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[3:4], v1
	ds_load_b64 v[5:6], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[5:6]
	ds_store_b64 v7, v[3:4]
.LBB1_17:
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v1, 4, v0
	v_cmp_gt_u32_e64 s0, 4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB1_19
; %bb.18:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[3:4], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v7, v[1:2]
.LBB1_19:
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s0, 2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB1_21
; %bb.20:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[3:4], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v7, v[1:2]
.LBB1_21:
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_gt_u64_e64 s0, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_23
; %bb.22:
	v_mov_b32_e32 v5, 0
	ds_load_2addr_b64 v[1:4], v5 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[3:4], v[1:2]
	ds_store_b64 v5, v[1:2]
.LBB1_23:                               ; %Flow30
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s1, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_29
; %bb.24:
	v_cmp_neq_f64_e64 s0, s[10:11], 0
	s_load_b32 s2, s[2:3], 0x4
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, s14
	s_mul_i32 s2, s2, s12
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_add_i32 s0, s2, s13
	s_cbranch_vccz .LBB1_26
; %bb.25:
	s_lshl_b64 s[2:3], s[0:1], 3
	v_mov_b32_e32 v2, 0
	s_add_u32 s4, s8, s2
	s_addc_u32 s5, s9, s3
	s_load_b64 s[2:3], s[4:5], 0x0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[0:1], s[2:3], s[10:11], v[0:1]
	s_mov_b32 s2, 0
	global_store_b64 v2, v[0:1], s[4:5]
	s_branch .LBB1_27
.LBB1_26:
	s_mov_b32 s2, -1
.LBB1_27:                               ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB1_29
; %bb.28:
	v_mov_b32_e32 v2, 0
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB1_29:                               ; %_Z11cuda_reduceILj256Ed3SumEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_sum_256_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	cuda_sum_256_double, .Lfunc_end1-cuda_sum_256_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1308
; NumSgprs: 26
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_sum_128_double     ; -- Begin function cuda_sum_128_double
	.globl	cuda_sum_128_double
	.p2align	8
	.type	cuda_sum_128_double,@function
cuda_sum_128_double:                    ; @cuda_sum_128_double
; %bb.0:
	s_clause 0x2
	s_load_b256 s[16:23], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x38
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 7, v0
	v_lshl_add_u32 v7, v0, 3, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s19
	s_mul_hi_u32 s3, s14, s18
	s_mul_i32 s19, s15, s21
	s_mul_hi_u32 s21, s15, s20
	s_mul_i32 s18, s14, s18
	s_mul_i32 s20, s15, s20
	s_add_i32 s3, s3, s2
	s_add_i32 s21, s21, s19
	s_add_u32 s18, s20, s18
	s_addc_u32 s19, s21, s3
	s_add_u32 s2, s0, 56
	s_addc_u32 s3, s1, 0
	s_lshl_b32 s0, s12, 7
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB2_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s16, 0
	s_lshl_b64 s[20:21], s[18:19], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s20, s20, s6
	s_addc_u32 s21, s21, s7
	v_mad_u64_u32 v[5:6], null, v1, s17, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s0, v1
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s20, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s21, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v7, v[3:4]
.LBB2_2:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB2_6
; %bb.3:                                ; %.lr.ph.i
	ds_load_b64 v[3:4], v7
	s_lshl_b64 s[18:19], s[18:19], 3
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, s0, v1
	s_add_u32 s6, s6, s18
	s_addc_u32 s18, s7, s19
	s_mov_b32 s7, 0
.LBB2_4:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v2, s16
	v_mul_lo_u32 v10, v1, s17
	v_mad_u64_u32 v[8:9], null, v1, s16, 0
	v_add3_u32 v9, v9, v10, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	v_add_co_u32 v1, vcc_lo, s6, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s18, v2, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[5:6]
	global_load_b64 v[1:2], v[1:2], off
	s_or_b32 s7, vcc_lo, s7
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[1:2]
	v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v2, v6
	v_add_nc_u32_e32 v5, s0, v5
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB2_4
; %bb.5:                                ; %._crit_edge.i.loopexit
	s_or_b32 exec_lo, exec_lo, s7
	ds_store_b64 v7, v[3:4]
.LBB2_6:                                ; %Flow31
	s_or_b32 exec_lo, exec_lo, s1
	v_or_b32_e32 v1, 64, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s0, 64, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s1, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB2_8
; %bb.7:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[3:4], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v7, v[1:2]
.LBB2_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB2_21
; %bb.9:
	v_or_b32_e32 v1, 32, v0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB2_11
; %bb.10:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[3:4], v1
	ds_load_b64 v[5:6], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[5:6]
	ds_store_b64 v7, v[3:4]
.LBB2_11:
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v1, 16, v0
	v_cmp_gt_u32_e64 s0, 16, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB2_13
; %bb.12:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[3:4], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v7, v[1:2]
.LBB2_13:
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s0, 8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB2_15
; %bb.14:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[3:4], v1
	ds_load_b64 v[5:6], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[5:6]
	ds_store_b64 v7, v[3:4]
.LBB2_15:
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v1, 4, v0
	v_cmp_gt_u32_e64 s0, 4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB2_17
; %bb.16:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[3:4], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v7, v[1:2]
.LBB2_17:
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s0, 2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB2_19
; %bb.18:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[3:4], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v7, v[1:2]
.LBB2_19:
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_gt_u64_e64 s0, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB2_21
; %bb.20:
	v_mov_b32_e32 v5, 0
	ds_load_2addr_b64 v[1:4], v5 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[3:4], v[1:2]
	ds_store_b64 v5, v[1:2]
.LBB2_21:                               ; %Flow30
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s1, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB2_27
; %bb.22:
	v_cmp_neq_f64_e64 s0, s[10:11], 0
	s_load_b32 s2, s[2:3], 0x4
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, s14
	s_mul_i32 s2, s2, s12
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_add_i32 s0, s2, s13
	s_cbranch_vccz .LBB2_24
; %bb.23:
	s_lshl_b64 s[2:3], s[0:1], 3
	v_mov_b32_e32 v2, 0
	s_add_u32 s4, s8, s2
	s_addc_u32 s5, s9, s3
	s_load_b64 s[2:3], s[4:5], 0x0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[0:1], s[2:3], s[10:11], v[0:1]
	s_mov_b32 s2, 0
	global_store_b64 v2, v[0:1], s[4:5]
	s_branch .LBB2_25
.LBB2_24:
	s_mov_b32 s2, -1
.LBB2_25:                               ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB2_27
; %bb.26:
	v_mov_b32_e32 v2, 0
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB2_27:                               ; %_Z11cuda_reduceILj128Ed3SumEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_sum_128_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	cuda_sum_128_double, .Lfunc_end2-cuda_sum_128_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1204
; NumSgprs: 26
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_sum_64_double      ; -- Begin function cuda_sum_64_double
	.globl	cuda_sum_64_double
	.p2align	8
	.type	cuda_sum_64_double,@function
cuda_sum_64_double:                     ; @cuda_sum_64_double
; %bb.0:
	s_clause 0x2
	s_load_b256 s[16:23], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x38
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 6, v0
	v_lshl_add_u32 v7, v0, 3, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s19
	s_mul_hi_u32 s3, s14, s18
	s_mul_i32 s19, s15, s21
	s_mul_hi_u32 s21, s15, s20
	s_mul_i32 s18, s14, s18
	s_mul_i32 s20, s15, s20
	s_add_i32 s3, s3, s2
	s_add_i32 s21, s21, s19
	s_add_u32 s18, s20, s18
	s_addc_u32 s19, s21, s3
	s_add_u32 s2, s0, 56
	s_addc_u32 s3, s1, 0
	s_lshl_b32 s0, s12, 6
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB3_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s16, 0
	s_lshl_b64 s[20:21], s[18:19], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s20, s20, s6
	s_addc_u32 s21, s21, s7
	v_mad_u64_u32 v[5:6], null, v1, s17, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s0, v1
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s20, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s21, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v7, v[3:4]
.LBB3_2:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB3_6
; %bb.3:                                ; %.lr.ph.i
	ds_load_b64 v[3:4], v7
	s_lshl_b64 s[18:19], s[18:19], 3
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, s0, v1
	s_add_u32 s6, s6, s18
	s_addc_u32 s18, s7, s19
	s_mov_b32 s7, 0
.LBB3_4:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v2, s16
	v_mul_lo_u32 v10, v1, s17
	v_mad_u64_u32 v[8:9], null, v1, s16, 0
	v_add3_u32 v9, v9, v10, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	v_add_co_u32 v1, vcc_lo, s6, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s18, v2, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[5:6]
	global_load_b64 v[1:2], v[1:2], off
	s_or_b32 s7, vcc_lo, s7
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[1:2]
	v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v2, v6
	v_add_nc_u32_e32 v5, s0, v5
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB3_4
; %bb.5:                                ; %._crit_edge.i.loopexit
	s_or_b32 exec_lo, exec_lo, s7
	ds_store_b64 v7, v[3:4]
.LBB3_6:                                ; %Flow31
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB3_19
; %bb.7:
	v_or_b32_e32 v1, 32, v0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB3_9
; %bb.8:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[3:4], v1
	ds_load_b64 v[5:6], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[5:6]
	ds_store_b64 v7, v[3:4]
.LBB3_9:
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v1, 16, v0
	v_cmp_gt_u32_e64 s0, 16, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB3_11
; %bb.10:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[3:4], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v7, v[1:2]
.LBB3_11:
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s0, 8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB3_13
; %bb.12:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[3:4], v1
	ds_load_b64 v[5:6], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[5:6]
	ds_store_b64 v7, v[3:4]
.LBB3_13:
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v1, 4, v0
	v_cmp_gt_u32_e64 s0, 4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB3_15
; %bb.14:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[3:4], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v7, v[1:2]
.LBB3_15:
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s0, 2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB3_17
; %bb.16:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[3:4], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v7, v[1:2]
.LBB3_17:
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_gt_u64_e64 s0, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB3_19
; %bb.18:
	v_mov_b32_e32 v5, 0
	ds_load_2addr_b64 v[1:4], v5 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[3:4], v[1:2]
	ds_store_b64 v5, v[1:2]
.LBB3_19:                               ; %Flow30
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s1, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB3_25
; %bb.20:
	v_cmp_neq_f64_e64 s0, s[10:11], 0
	s_load_b32 s2, s[2:3], 0x4
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, s14
	s_mul_i32 s2, s2, s12
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_add_i32 s0, s2, s13
	s_cbranch_vccz .LBB3_22
; %bb.21:
	s_lshl_b64 s[2:3], s[0:1], 3
	v_mov_b32_e32 v2, 0
	s_add_u32 s4, s8, s2
	s_addc_u32 s5, s9, s3
	s_load_b64 s[2:3], s[4:5], 0x0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[0:1], s[2:3], s[10:11], v[0:1]
	s_mov_b32 s2, 0
	global_store_b64 v2, v[0:1], s[4:5]
	s_branch .LBB3_23
.LBB3_22:
	s_mov_b32 s2, -1
.LBB3_23:                               ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB3_25
; %bb.24:
	v_mov_b32_e32 v2, 0
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB3_25:                               ; %_Z11cuda_reduceILj64Ed3SumEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_sum_64_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	cuda_sum_64_double, .Lfunc_end3-cuda_sum_64_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1104
; NumSgprs: 26
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_sum_32_double      ; -- Begin function cuda_sum_32_double
	.globl	cuda_sum_32_double
	.p2align	8
	.type	cuda_sum_32_double,@function
cuda_sum_32_double:                     ; @cuda_sum_32_double
; %bb.0:
	s_clause 0x2
	s_load_b256 s[16:23], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x38
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 5, v0
	v_lshl_add_u32 v7, v0, 3, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s19
	s_mul_hi_u32 s3, s14, s18
	s_mul_i32 s19, s15, s21
	s_mul_hi_u32 s21, s15, s20
	s_mul_i32 s18, s14, s18
	s_mul_i32 s20, s15, s20
	s_add_i32 s3, s3, s2
	s_add_i32 s21, s21, s19
	s_add_u32 s18, s20, s18
	s_addc_u32 s19, s21, s3
	s_add_u32 s2, s0, 56
	s_addc_u32 s3, s1, 0
	s_lshl_b32 s0, s12, 5
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB4_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s16, 0
	s_lshl_b64 s[20:21], s[18:19], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s20, s20, s6
	s_addc_u32 s21, s21, s7
	v_mad_u64_u32 v[5:6], null, v1, s17, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s0, v1
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s20, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s21, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v7, v[3:4]
.LBB4_2:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB4_6
; %bb.3:                                ; %.lr.ph.i
	ds_load_b64 v[3:4], v7
	s_lshl_b64 s[18:19], s[18:19], 3
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, s0, v1
	s_add_u32 s6, s6, s18
	s_addc_u32 s18, s7, s19
	s_mov_b32 s7, 0
.LBB4_4:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v2, s16
	v_mul_lo_u32 v10, v1, s17
	v_mad_u64_u32 v[8:9], null, v1, s16, 0
	v_add3_u32 v9, v9, v10, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	v_add_co_u32 v1, vcc_lo, s6, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s18, v2, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[5:6]
	global_load_b64 v[1:2], v[1:2], off
	s_or_b32 s7, vcc_lo, s7
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[1:2]
	v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v2, v6
	v_add_nc_u32_e32 v5, s0, v5
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB4_4
; %bb.5:                                ; %._crit_edge.i.loopexit
	s_or_b32 exec_lo, exec_lo, s7
	ds_store_b64 v7, v[3:4]
.LBB4_6:                                ; %Flow31
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB4_17
; %bb.7:
	v_or_b32_e32 v1, 16, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s0, 16, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB4_9
; %bb.8:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[3:4], v1
	ds_load_b64 v[5:6], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[5:6]
	ds_store_b64 v7, v[3:4]
.LBB4_9:
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v1, 8, v0
	v_cmp_gt_u32_e64 s0, 8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB4_11
; %bb.10:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[3:4], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v7, v[1:2]
.LBB4_11:
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s0, 4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB4_13
; %bb.12:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[3:4], v1
	ds_load_b64 v[5:6], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[5:6]
	ds_store_b64 v7, v[3:4]
.LBB4_13:
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v1, 2, v0
	v_cmp_gt_u32_e64 s0, 2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB4_15
; %bb.14:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[3:4], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v7, v[1:2]
.LBB4_15:
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_gt_u64_e64 s0, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB4_17
; %bb.16:
	v_mov_b32_e32 v5, 0
	ds_load_2addr_b64 v[1:4], v5 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[3:4], v[1:2]
	ds_store_b64 v5, v[1:2]
.LBB4_17:                               ; %Flow30
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s1, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB4_23
; %bb.18:
	v_cmp_neq_f64_e64 s0, s[10:11], 0
	s_load_b32 s2, s[2:3], 0x4
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, s14
	s_mul_i32 s2, s2, s12
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_add_i32 s0, s2, s13
	s_cbranch_vccz .LBB4_20
; %bb.19:
	s_lshl_b64 s[2:3], s[0:1], 3
	v_mov_b32_e32 v2, 0
	s_add_u32 s4, s8, s2
	s_addc_u32 s5, s9, s3
	s_load_b64 s[2:3], s[4:5], 0x0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[0:1], s[2:3], s[10:11], v[0:1]
	s_mov_b32 s2, 0
	global_store_b64 v2, v[0:1], s[4:5]
	s_branch .LBB4_21
.LBB4_20:
	s_mov_b32 s2, -1
.LBB4_21:                               ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB4_23
; %bb.22:
	v_mov_b32_e32 v2, 0
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB4_23:                               ; %_Z11cuda_reduceILj32Ed3SumEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_sum_32_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	cuda_sum_32_double, .Lfunc_end4-cuda_sum_32_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1028
; NumSgprs: 26
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_sum_16_double      ; -- Begin function cuda_sum_16_double
	.globl	cuda_sum_16_double
	.p2align	8
	.type	cuda_sum_16_double,@function
cuda_sum_16_double:                     ; @cuda_sum_16_double
; %bb.0:
	s_clause 0x2
	s_load_b256 s[16:23], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x38
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 4, v0
	v_lshl_add_u32 v7, v0, 3, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s19
	s_mul_hi_u32 s3, s14, s18
	s_mul_i32 s19, s15, s21
	s_mul_hi_u32 s21, s15, s20
	s_mul_i32 s18, s14, s18
	s_mul_i32 s20, s15, s20
	s_add_i32 s3, s3, s2
	s_add_i32 s21, s21, s19
	s_add_u32 s18, s20, s18
	s_addc_u32 s19, s21, s3
	s_add_u32 s2, s0, 56
	s_addc_u32 s3, s1, 0
	s_lshl_b32 s0, s12, 4
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB5_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s16, 0
	s_lshl_b64 s[20:21], s[18:19], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s20, s20, s6
	s_addc_u32 s21, s21, s7
	v_mad_u64_u32 v[5:6], null, v1, s17, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s0, v1
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s20, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s21, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v7, v[3:4]
.LBB5_2:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB5_6
; %bb.3:                                ; %.lr.ph.i
	ds_load_b64 v[3:4], v7
	s_lshl_b64 s[18:19], s[18:19], 3
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, s0, v1
	s_add_u32 s6, s6, s18
	s_addc_u32 s18, s7, s19
	s_mov_b32 s7, 0
.LBB5_4:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v2, s16
	v_mul_lo_u32 v10, v1, s17
	v_mad_u64_u32 v[8:9], null, v1, s16, 0
	v_add3_u32 v9, v9, v10, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	v_add_co_u32 v1, vcc_lo, s6, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s18, v2, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[5:6]
	global_load_b64 v[1:2], v[1:2], off
	s_or_b32 s7, vcc_lo, s7
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[1:2]
	v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v2, v6
	v_add_nc_u32_e32 v5, s0, v5
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB5_4
; %bb.5:                                ; %._crit_edge.i.loopexit
	s_or_b32 exec_lo, exec_lo, s7
	ds_store_b64 v7, v[3:4]
.LBB5_6:                                ; %Flow31
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB5_15
; %bb.7:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s0, 8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB5_9
; %bb.8:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[3:4], v1
	ds_load_b64 v[5:6], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[5:6]
	ds_store_b64 v7, v[3:4]
.LBB5_9:
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v1, 4, v0
	v_cmp_gt_u32_e64 s0, 4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB5_11
; %bb.10:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[3:4], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v7, v[1:2]
.LBB5_11:
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s0, 2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB5_13
; %bb.12:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[3:4], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v7, v[1:2]
.LBB5_13:
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_gt_u64_e64 s0, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB5_15
; %bb.14:
	v_mov_b32_e32 v5, 0
	ds_load_2addr_b64 v[1:4], v5 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[3:4], v[1:2]
	ds_store_b64 v5, v[1:2]
.LBB5_15:                               ; %Flow30
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s1, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB5_21
; %bb.16:
	v_cmp_neq_f64_e64 s0, s[10:11], 0
	s_load_b32 s2, s[2:3], 0x4
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, s14
	s_mul_i32 s2, s2, s12
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_add_i32 s0, s2, s13
	s_cbranch_vccz .LBB5_18
; %bb.17:
	s_lshl_b64 s[2:3], s[0:1], 3
	v_mov_b32_e32 v2, 0
	s_add_u32 s4, s8, s2
	s_addc_u32 s5, s9, s3
	s_load_b64 s[2:3], s[4:5], 0x0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[0:1], s[2:3], s[10:11], v[0:1]
	s_mov_b32 s2, 0
	global_store_b64 v2, v[0:1], s[4:5]
	s_branch .LBB5_19
.LBB5_18:
	s_mov_b32 s2, -1
.LBB5_19:                               ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB5_21
; %bb.20:
	v_mov_b32_e32 v2, 0
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB5_21:                               ; %_Z11cuda_reduceILj16Ed3SumEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_sum_16_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	cuda_sum_16_double, .Lfunc_end5-cuda_sum_16_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 944
; NumSgprs: 26
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_sum_8_double       ; -- Begin function cuda_sum_8_double
	.globl	cuda_sum_8_double
	.p2align	8
	.type	cuda_sum_8_double,@function
cuda_sum_8_double:                      ; @cuda_sum_8_double
; %bb.0:
	s_clause 0x2
	s_load_b256 s[16:23], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x38
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 3, v0
	v_lshl_add_u32 v7, v0, 3, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s19
	s_mul_hi_u32 s3, s14, s18
	s_mul_i32 s19, s15, s21
	s_mul_hi_u32 s21, s15, s20
	s_mul_i32 s18, s14, s18
	s_mul_i32 s20, s15, s20
	s_add_i32 s3, s3, s2
	s_add_i32 s21, s21, s19
	s_add_u32 s18, s20, s18
	s_addc_u32 s19, s21, s3
	s_add_u32 s2, s0, 56
	s_addc_u32 s3, s1, 0
	s_lshl_b32 s0, s12, 3
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB6_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s16, 0
	s_lshl_b64 s[20:21], s[18:19], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s20, s20, s6
	s_addc_u32 s21, s21, s7
	v_mad_u64_u32 v[5:6], null, v1, s17, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s0, v1
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s20, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s21, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v7, v[3:4]
.LBB6_2:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB6_6
; %bb.3:                                ; %.lr.ph.i
	ds_load_b64 v[3:4], v7
	s_lshl_b64 s[18:19], s[18:19], 3
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, s0, v1
	s_add_u32 s6, s6, s18
	s_addc_u32 s18, s7, s19
	s_mov_b32 s7, 0
.LBB6_4:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v2, s16
	v_mul_lo_u32 v10, v1, s17
	v_mad_u64_u32 v[8:9], null, v1, s16, 0
	v_add3_u32 v9, v9, v10, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	v_add_co_u32 v1, vcc_lo, s6, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s18, v2, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[5:6]
	global_load_b64 v[1:2], v[1:2], off
	s_or_b32 s7, vcc_lo, s7
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[1:2]
	v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v2, v6
	v_add_nc_u32_e32 v5, s0, v5
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB6_4
; %bb.5:                                ; %._crit_edge.i.loopexit
	s_or_b32 exec_lo, exec_lo, s7
	ds_store_b64 v7, v[3:4]
.LBB6_6:                                ; %Flow31
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB6_13
; %bb.7:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s0, 4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB6_9
; %bb.8:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[3:4], v1
	ds_load_b64 v[5:6], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[5:6]
	ds_store_b64 v7, v[3:4]
.LBB6_9:
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v1, 2, v0
	v_cmp_gt_u32_e64 s0, 2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB6_11
; %bb.10:
	v_lshl_add_u32 v1, v1, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[3:4], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v7, v[1:2]
.LBB6_11:
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_gt_u64_e64 s0, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB6_13
; %bb.12:
	v_mov_b32_e32 v5, 0
	ds_load_2addr_b64 v[1:4], v5 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[3:4], v[1:2]
	ds_store_b64 v5, v[1:2]
.LBB6_13:                               ; %Flow30
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s1, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB6_19
; %bb.14:
	v_cmp_neq_f64_e64 s0, s[10:11], 0
	s_load_b32 s2, s[2:3], 0x4
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, s14
	s_mul_i32 s2, s2, s12
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_add_i32 s0, s2, s13
	s_cbranch_vccz .LBB6_16
; %bb.15:
	s_lshl_b64 s[2:3], s[0:1], 3
	v_mov_b32_e32 v2, 0
	s_add_u32 s4, s8, s2
	s_addc_u32 s5, s9, s3
	s_load_b64 s[2:3], s[4:5], 0x0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[0:1], s[2:3], s[10:11], v[0:1]
	s_mov_b32 s2, 0
	global_store_b64 v2, v[0:1], s[4:5]
	s_branch .LBB6_17
.LBB6_16:
	s_mov_b32 s2, -1
.LBB6_17:                               ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB6_19
; %bb.18:
	v_mov_b32_e32 v2, 0
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB6_19:                               ; %_Z11cuda_reduceILj8Ed3SumEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_sum_8_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	cuda_sum_8_double, .Lfunc_end6-cuda_sum_8_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 856
; NumSgprs: 26
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_sum_4_double       ; -- Begin function cuda_sum_4_double
	.globl	cuda_sum_4_double
	.p2align	8
	.type	cuda_sum_4_double,@function
cuda_sum_4_double:                      ; @cuda_sum_4_double
; %bb.0:
	s_clause 0x2
	s_load_b256 s[16:23], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x38
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 2, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s19
	s_mul_hi_u32 s3, s14, s18
	s_mul_i32 s19, s15, s21
	s_mul_hi_u32 s21, s15, s20
	s_mul_i32 s18, s14, s18
	s_mul_i32 s20, s15, s20
	s_add_i32 s3, s3, s2
	s_add_i32 s21, s21, s19
	s_add_u32 s18, s20, s18
	s_addc_u32 s19, s21, s3
	s_add_u32 s2, s0, 56
	s_addc_u32 s3, s1, 0
	s_lshl_b32 s0, s12, 2
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB7_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s16, 0
	s_lshl_b64 s[20:21], s[18:19], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s20, s20, s6
	s_addc_u32 s21, s21, s7
	v_mad_u64_u32 v[5:6], null, v1, s17, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s0, v1
	v_lshl_add_u32 v5, v0, 3, 0
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s20, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s21, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v5, v[3:4]
.LBB7_2:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB7_6
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v7, v0, 3, 0
	s_lshl_b64 s[18:19], s[18:19], 3
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, s0, v1
	s_add_u32 s6, s6, s18
	ds_load_b64 v[3:4], v7
	s_addc_u32 s18, s7, s19
	s_mov_b32 s7, 0
.LBB7_4:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v2, s16
	v_mul_lo_u32 v10, v1, s17
	v_mad_u64_u32 v[8:9], null, v1, s16, 0
	v_add3_u32 v9, v9, v10, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	v_add_co_u32 v1, vcc_lo, s6, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s18, v2, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[5:6]
	global_load_b64 v[1:2], v[1:2], off
	s_or_b32 s7, vcc_lo, s7
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[1:2]
	v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v2, v6
	v_add_nc_u32_e32 v5, s0, v5
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB7_4
; %bb.5:                                ; %._crit_edge.i.loopexit
	s_or_b32 exec_lo, exec_lo, s7
	ds_store_b64 v7, v[3:4]
.LBB7_6:                                ; %Flow31
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB7_11
; %bb.7:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s0, 2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB7_9
; %bb.8:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v5, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[3:4], v5
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v5, v[1:2]
.LBB7_9:
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_gt_u64_e64 s0, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB7_11
; %bb.10:
	v_mov_b32_e32 v5, 0
	ds_load_2addr_b64 v[1:4], v5 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[3:4], v[1:2]
	ds_store_b64 v5, v[1:2]
.LBB7_11:                               ; %Flow30
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s1, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB7_17
; %bb.12:
	v_cmp_neq_f64_e64 s0, s[10:11], 0
	s_load_b32 s2, s[2:3], 0x4
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, s14
	s_mul_i32 s2, s2, s12
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_add_i32 s0, s2, s13
	s_cbranch_vccz .LBB7_14
; %bb.13:
	s_lshl_b64 s[2:3], s[0:1], 3
	v_mov_b32_e32 v2, 0
	s_add_u32 s4, s8, s2
	s_addc_u32 s5, s9, s3
	s_load_b64 s[2:3], s[4:5], 0x0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[0:1], s[2:3], s[10:11], v[0:1]
	s_mov_b32 s2, 0
	global_store_b64 v2, v[0:1], s[4:5]
	s_branch .LBB7_15
.LBB7_14:
	s_mov_b32 s2, -1
.LBB7_15:                               ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB7_17
; %bb.16:
	v_mov_b32_e32 v2, 0
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB7_17:                               ; %_Z11cuda_reduceILj4Ed3SumEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_sum_4_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	cuda_sum_4_double, .Lfunc_end7-cuda_sum_4_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 788
; NumSgprs: 26
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_sum_2_double       ; -- Begin function cuda_sum_2_double
	.globl	cuda_sum_2_double
	.p2align	8
	.type	cuda_sum_2_double,@function
cuda_sum_2_double:                      ; @cuda_sum_2_double
; %bb.0:
	s_clause 0x2
	s_load_b256 s[16:23], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x38
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 1, v0
	v_lshl_add_u32 v7, v0, 3, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s19
	s_mul_hi_u32 s3, s14, s18
	s_mul_i32 s19, s15, s21
	s_mul_hi_u32 s21, s15, s20
	s_mul_i32 s18, s14, s18
	s_mul_i32 s20, s15, s20
	s_add_i32 s3, s3, s2
	s_add_i32 s21, s21, s19
	s_add_u32 s2, s20, s18
	s_addc_u32 s3, s21, s3
	s_add_u32 s0, s0, 56
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s18, s12, 1
	s_mov_b32 s19, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB8_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s16, 0
	s_lshl_b64 s[20:21], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s20, s20, s6
	s_addc_u32 s21, s21, s7
	v_mad_u64_u32 v[5:6], null, v1, s17, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s18, v1
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s20, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s21, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v7, v[3:4]
.LBB8_2:
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s19, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB8_6
; %bb.3:                                ; %.lr.ph.i
	ds_load_b64 v[3:4], v7
	s_lshl_b64 s[2:3], s[2:3], 3
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, s18, v1
	s_add_u32 s2, s6, s2
	s_addc_u32 s6, s7, s3
	s_mov_b32 s3, 0
.LBB8_4:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v2, s16
	v_mul_lo_u32 v10, v1, s17
	v_mad_u64_u32 v[8:9], null, v1, s16, 0
	v_add3_u32 v9, v9, v10, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	v_add_co_u32 v1, vcc_lo, s2, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s6, v2, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[5:6]
	global_load_b64 v[1:2], v[1:2], off
	s_or_b32 s3, vcc_lo, s3
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[1:2]
	v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v2, v6
	v_add_nc_u32_e32 v5, s18, v5
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB8_4
; %bb.5:                                ; %._crit_edge.i.loopexit
	s_or_b32 exec_lo, exec_lo, s3
	ds_store_b64 v7, v[3:4]
.LBB8_6:                                ; %Flow29
	s_or_b32 exec_lo, exec_lo, s19
	v_cmp_gt_u64_e64 s2, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 s3, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB8_8
; %bb.7:
	v_mov_b32_e32 v4, 0
	ds_load_2addr_b64 v[0:3], v4 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[0:1], v[2:3], v[0:1]
	ds_store_b64 v4, v[0:1]
.LBB8_8:
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB8_14
; %bb.9:
	v_cmp_neq_f64_e64 s2, s[10:11], 0
	s_load_b32 s0, s[0:1], 0x4
	s_mov_b32 s1, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s0, s0, s13
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB8_11
; %bb.10:
	s_lshl_b64 s[2:3], s[0:1], 3
	v_mov_b32_e32 v2, 0
	s_add_u32 s4, s8, s2
	s_addc_u32 s5, s9, s3
	s_load_b64 s[2:3], s[4:5], 0x0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[0:1], s[2:3], s[10:11], v[0:1]
	s_mov_b32 s2, s1
	global_store_b64 v2, v[0:1], s[4:5]
	s_branch .LBB8_12
.LBB8_11:
	s_mov_b32 s2, -1
.LBB8_12:                               ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB8_14
; %bb.13:
	v_mov_b32_e32 v2, 0
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB8_14:                               ; %_Z11cuda_reduceILj2Ed3SumEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_sum_2_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end8:
	.size	cuda_sum_2_double, .Lfunc_end8-cuda_sum_2_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 664
; NumSgprs: 26
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_sum_512_float      ; -- Begin function cuda_sum_512_float
	.globl	cuda_sum_512_float
	.p2align	8
	.type	cuda_sum_512_float,@function
cuda_sum_512_float:                     ; @cuda_sum_512_float
; %bb.0:
	s_clause 0x4
	s_load_b128 s[8:11], s[0:1], 0x20
	s_load_b64 s[2:3], s[0:1], 0x30
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x38
	s_load_b64 s[16:17], s[0:1], 0x10
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 9, v0
	v_lshl_add_u32 v5, v0, 2, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s11, s14, s11
	s_mul_hi_u32 s18, s14, s10
	s_mul_i32 s3, s15, s3
	s_mul_hi_u32 s19, s15, s2
	s_mul_i32 s10, s14, s10
	s_mul_i32 s2, s15, s2
	s_add_i32 s18, s18, s11
	s_add_i32 s19, s19, s3
	s_add_u32 s2, s2, s10
	s_addc_u32 s3, s19, s18
	s_add_u32 s10, s0, 56
	s_addc_u32 s11, s1, 0
	s_lshl_b32 s18, s12, 9
	s_mov_b32 s19, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB9_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s8, 0
	s_lshl_b64 s[20:21], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s20, s20, s6
	s_addc_u32 s21, s21, s7
	v_mad_u64_u32 v[6:7], null, v1, s9, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v6 :: v_dual_add_nc_u32 v1, s18, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s20, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s21, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v3
.LBB9_2:
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s19, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB9_6
; %bb.3:                                ; %.lr.ph.i
	ds_load_b32 v6, v5
	s_lshl_b64 s[2:3], s[2:3], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s18, v1
	s_add_u32 s2, s6, s2
	s_addc_u32 s6, s7, s3
	s_mov_b32 s3, 0
.LBB9_4:                                ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s8
	v_mul_lo_u32 v9, v1, s9
	v_mad_u64_u32 v[7:8], null, v1, s8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s6, v2, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s18, v3
	s_or_b32 s3, vcc_lo, s3
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v6, v6, v7
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB9_4
; %bb.5:                                ; %._crit_edge.i.loopexit
	s_or_b32 exec_lo, exec_lo, s3
	ds_store_b32 v5, v6
.LBB9_6:                                ; %Flow30
	s_or_b32 exec_lo, exec_lo, s19
	v_or_b32_e32 v1, 0x100, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s2, 0x100, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s3, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB9_8
; %bb.7:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v3, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v3
	ds_store_b32 v5, v1
.LBB9_8:
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v1, 0x80, v0
	v_cmp_gt_u32_e64 s2, 0x80, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s3, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB9_10
; %bb.9:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v2, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	ds_store_b32 v5, v1
.LBB9_10:
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v1, 64, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s2, 64, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s3, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB9_12
; %bb.11:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v2, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	ds_store_b32 v5, v1
.LBB9_12:
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB9_25
; %bb.13:
	v_or_b32_e32 v1, 32, v0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB9_15
; %bb.14:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v3, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v3
	ds_store_b32 v5, v1
.LBB9_15:
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v1, 16, v0
	v_cmp_gt_u32_e64 s2, 16, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB9_17
; %bb.16:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v2, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	ds_store_b32 v5, v1
.LBB9_17:
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s2, 8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB9_19
; %bb.18:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v3, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v3
	ds_store_b32 v5, v1
.LBB9_19:
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v1, 4, v0
	v_cmp_gt_u32_e64 s2, 4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB9_21
; %bb.20:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v2, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	ds_store_b32 v5, v1
.LBB9_21:
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s2, 2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB9_23
; %bb.22:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v2, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	ds_store_b32 v5, v1
.LBB9_23:
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_gt_u64_e64 s2, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB9_25
; %bb.24:
	v_mov_b32_e32 v3, 0
	ds_load_2addr_b32 v[1:2], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v2, v1
	ds_store_b32 v3, v1
.LBB9_25:                               ; %Flow29
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB9_31
; %bb.26:
	s_load_b32 s2, s[10:11], 0x4
	s_load_b32 s0, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s2, s15
	v_cmp_neq_f32_e64 s2, s0, 0
	s_add_i32 s1, s1, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s1, s1, s12
	s_and_b32 vcc_lo, exec_lo, s2
	s_add_i32 s2, s1, s13
	s_cbranch_vccz .LBB9_28
; %bb.27:
	s_lshl_b64 s[4:5], s[2:3], 2
	v_mov_b32_e32 v6, 0
	s_add_u32 s4, s16, s4
	s_addc_u32 s5, s17, s5
	v_cvt_f64_f32_e32 v[0:1], s0
	s_load_b32 s1, s[4:5], 0x0
	ds_load_b32 v4, v6
	s_mov_b32 s0, 0
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[2:3], s1
	v_cvt_f64_f32_e32 v[4:5], v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]
	v_cvt_f32_f64_e32 v0, v[0:1]
	global_store_b32 v6, v0, s[4:5]
	s_branch .LBB9_29
.LBB9_28:
	s_mov_b32 s0, -1
.LBB9_29:                               ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB9_31
; %bb.30:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB9_31:                               ; %_Z11cuda_reduceILj512Ef3SumEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_sum_512_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end9:
	.size	cuda_sum_512_float, .Lfunc_end9-cuda_sum_512_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1412
; NumSgprs: 24
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_sum_256_float      ; -- Begin function cuda_sum_256_float
	.globl	cuda_sum_256_float
	.p2align	8
	.type	cuda_sum_256_float,@function
cuda_sum_256_float:                     ; @cuda_sum_256_float
; %bb.0:
	s_clause 0x4
	s_load_b128 s[8:11], s[0:1], 0x20
	s_load_b64 s[2:3], s[0:1], 0x30
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x38
	s_load_b64 s[16:17], s[0:1], 0x10
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 8, v0
	v_lshl_add_u32 v5, v0, 2, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s11, s14, s11
	s_mul_hi_u32 s18, s14, s10
	s_mul_i32 s3, s15, s3
	s_mul_hi_u32 s19, s15, s2
	s_mul_i32 s10, s14, s10
	s_mul_i32 s2, s15, s2
	s_add_i32 s18, s18, s11
	s_add_i32 s19, s19, s3
	s_add_u32 s2, s2, s10
	s_addc_u32 s3, s19, s18
	s_add_u32 s10, s0, 56
	s_addc_u32 s11, s1, 0
	s_lshl_b32 s18, s12, 8
	s_mov_b32 s19, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB10_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s8, 0
	s_lshl_b64 s[20:21], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s20, s20, s6
	s_addc_u32 s21, s21, s7
	v_mad_u64_u32 v[6:7], null, v1, s9, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v6 :: v_dual_add_nc_u32 v1, s18, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s20, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s21, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v3
.LBB10_2:
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s19, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB10_6
; %bb.3:                                ; %.lr.ph.i
	ds_load_b32 v6, v5
	s_lshl_b64 s[2:3], s[2:3], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s18, v1
	s_add_u32 s2, s6, s2
	s_addc_u32 s6, s7, s3
	s_mov_b32 s3, 0
.LBB10_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s8
	v_mul_lo_u32 v9, v1, s9
	v_mad_u64_u32 v[7:8], null, v1, s8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s6, v2, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s18, v3
	s_or_b32 s3, vcc_lo, s3
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v6, v6, v7
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB10_4
; %bb.5:                                ; %._crit_edge.i.loopexit
	s_or_b32 exec_lo, exec_lo, s3
	ds_store_b32 v5, v6
.LBB10_6:                               ; %Flow30
	s_or_b32 exec_lo, exec_lo, s19
	v_or_b32_e32 v1, 0x80, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s2, 0x80, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s3, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB10_8
; %bb.7:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v3, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v3
	ds_store_b32 v5, v1
.LBB10_8:
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v1, 64, v0
	v_cmp_gt_u32_e64 s2, 64, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s3, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB10_10
; %bb.9:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v2, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	ds_store_b32 v5, v1
.LBB10_10:
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB10_23
; %bb.11:
	v_or_b32_e32 v1, 32, v0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB10_13
; %bb.12:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v3, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v3
	ds_store_b32 v5, v1
.LBB10_13:
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v1, 16, v0
	v_cmp_gt_u32_e64 s2, 16, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB10_15
; %bb.14:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v2, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	ds_store_b32 v5, v1
.LBB10_15:
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s2, 8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB10_17
; %bb.16:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v3, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v3
	ds_store_b32 v5, v1
.LBB10_17:
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v1, 4, v0
	v_cmp_gt_u32_e64 s2, 4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB10_19
; %bb.18:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v2, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	ds_store_b32 v5, v1
.LBB10_19:
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s2, 2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB10_21
; %bb.20:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v2, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	ds_store_b32 v5, v1
.LBB10_21:
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_gt_u64_e64 s2, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB10_23
; %bb.22:
	v_mov_b32_e32 v3, 0
	ds_load_2addr_b32 v[1:2], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v2, v1
	ds_store_b32 v3, v1
.LBB10_23:                              ; %Flow29
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB10_29
; %bb.24:
	s_load_b32 s2, s[10:11], 0x4
	s_load_b32 s0, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s2, s15
	v_cmp_neq_f32_e64 s2, s0, 0
	s_add_i32 s1, s1, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s1, s1, s12
	s_and_b32 vcc_lo, exec_lo, s2
	s_add_i32 s2, s1, s13
	s_cbranch_vccz .LBB10_26
; %bb.25:
	s_lshl_b64 s[4:5], s[2:3], 2
	v_mov_b32_e32 v6, 0
	s_add_u32 s4, s16, s4
	s_addc_u32 s5, s17, s5
	v_cvt_f64_f32_e32 v[0:1], s0
	s_load_b32 s1, s[4:5], 0x0
	ds_load_b32 v4, v6
	s_mov_b32 s0, 0
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[2:3], s1
	v_cvt_f64_f32_e32 v[4:5], v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]
	v_cvt_f32_f64_e32 v0, v[0:1]
	global_store_b32 v6, v0, s[4:5]
	s_branch .LBB10_27
.LBB10_26:
	s_mov_b32 s0, -1
.LBB10_27:                              ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB10_29
; %bb.28:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB10_29:                              ; %_Z11cuda_reduceILj256Ef3SumEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_sum_256_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end10:
	.size	cuda_sum_256_float, .Lfunc_end10-cuda_sum_256_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1308
; NumSgprs: 24
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_sum_128_float      ; -- Begin function cuda_sum_128_float
	.globl	cuda_sum_128_float
	.p2align	8
	.type	cuda_sum_128_float,@function
cuda_sum_128_float:                     ; @cuda_sum_128_float
; %bb.0:
	s_clause 0x4
	s_load_b128 s[8:11], s[0:1], 0x20
	s_load_b64 s[2:3], s[0:1], 0x30
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x38
	s_load_b64 s[16:17], s[0:1], 0x10
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 7, v0
	v_lshl_add_u32 v5, v0, 2, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s11, s14, s11
	s_mul_hi_u32 s18, s14, s10
	s_mul_i32 s3, s15, s3
	s_mul_hi_u32 s19, s15, s2
	s_mul_i32 s10, s14, s10
	s_mul_i32 s2, s15, s2
	s_add_i32 s18, s18, s11
	s_add_i32 s19, s19, s3
	s_add_u32 s2, s2, s10
	s_addc_u32 s3, s19, s18
	s_add_u32 s10, s0, 56
	s_addc_u32 s11, s1, 0
	s_lshl_b32 s18, s12, 7
	s_mov_b32 s19, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB11_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s8, 0
	s_lshl_b64 s[20:21], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s20, s20, s6
	s_addc_u32 s21, s21, s7
	v_mad_u64_u32 v[6:7], null, v1, s9, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v6 :: v_dual_add_nc_u32 v1, s18, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s20, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s21, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v3
.LBB11_2:
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s19, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB11_6
; %bb.3:                                ; %.lr.ph.i
	ds_load_b32 v6, v5
	s_lshl_b64 s[2:3], s[2:3], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s18, v1
	s_add_u32 s2, s6, s2
	s_addc_u32 s6, s7, s3
	s_mov_b32 s3, 0
.LBB11_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s8
	v_mul_lo_u32 v9, v1, s9
	v_mad_u64_u32 v[7:8], null, v1, s8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s6, v2, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s18, v3
	s_or_b32 s3, vcc_lo, s3
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v6, v6, v7
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB11_4
; %bb.5:                                ; %._crit_edge.i.loopexit
	s_or_b32 exec_lo, exec_lo, s3
	ds_store_b32 v5, v6
.LBB11_6:                               ; %Flow30
	s_or_b32 exec_lo, exec_lo, s19
	v_or_b32_e32 v1, 64, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s2, 64, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s3, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB11_8
; %bb.7:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v2, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	ds_store_b32 v5, v1
.LBB11_8:
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB11_21
; %bb.9:
	v_or_b32_e32 v1, 32, v0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB11_11
; %bb.10:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v3, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v3
	ds_store_b32 v5, v1
.LBB11_11:
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v1, 16, v0
	v_cmp_gt_u32_e64 s2, 16, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB11_13
; %bb.12:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v2, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	ds_store_b32 v5, v1
.LBB11_13:
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s2, 8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB11_15
; %bb.14:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v3, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v3
	ds_store_b32 v5, v1
.LBB11_15:
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v1, 4, v0
	v_cmp_gt_u32_e64 s2, 4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB11_17
; %bb.16:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v2, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	ds_store_b32 v5, v1
.LBB11_17:
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s2, 2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB11_19
; %bb.18:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v2, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	ds_store_b32 v5, v1
.LBB11_19:
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_gt_u64_e64 s2, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB11_21
; %bb.20:
	v_mov_b32_e32 v3, 0
	ds_load_2addr_b32 v[1:2], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v2, v1
	ds_store_b32 v3, v1
.LBB11_21:                              ; %Flow29
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB11_27
; %bb.22:
	s_load_b32 s2, s[10:11], 0x4
	s_load_b32 s0, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s2, s15
	v_cmp_neq_f32_e64 s2, s0, 0
	s_add_i32 s1, s1, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s1, s1, s12
	s_and_b32 vcc_lo, exec_lo, s2
	s_add_i32 s2, s1, s13
	s_cbranch_vccz .LBB11_24
; %bb.23:
	s_lshl_b64 s[4:5], s[2:3], 2
	v_mov_b32_e32 v6, 0
	s_add_u32 s4, s16, s4
	s_addc_u32 s5, s17, s5
	v_cvt_f64_f32_e32 v[0:1], s0
	s_load_b32 s1, s[4:5], 0x0
	ds_load_b32 v4, v6
	s_mov_b32 s0, 0
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[2:3], s1
	v_cvt_f64_f32_e32 v[4:5], v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]
	v_cvt_f32_f64_e32 v0, v[0:1]
	global_store_b32 v6, v0, s[4:5]
	s_branch .LBB11_25
.LBB11_24:
	s_mov_b32 s0, -1
.LBB11_25:                              ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB11_27
; %bb.26:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB11_27:                              ; %_Z11cuda_reduceILj128Ef3SumEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_sum_128_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end11:
	.size	cuda_sum_128_float, .Lfunc_end11-cuda_sum_128_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1208
; NumSgprs: 24
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_sum_64_float       ; -- Begin function cuda_sum_64_float
	.globl	cuda_sum_64_float
	.p2align	8
	.type	cuda_sum_64_float,@function
cuda_sum_64_float:                      ; @cuda_sum_64_float
; %bb.0:
	s_clause 0x4
	s_load_b128 s[8:11], s[0:1], 0x20
	s_load_b64 s[2:3], s[0:1], 0x30
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x38
	s_load_b64 s[16:17], s[0:1], 0x10
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 6, v0
	v_lshl_add_u32 v5, v0, 2, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s11, s14, s11
	s_mul_hi_u32 s18, s14, s10
	s_mul_i32 s3, s15, s3
	s_mul_hi_u32 s19, s15, s2
	s_mul_i32 s10, s14, s10
	s_mul_i32 s2, s15, s2
	s_add_i32 s18, s18, s11
	s_add_i32 s19, s19, s3
	s_add_u32 s2, s2, s10
	s_addc_u32 s3, s19, s18
	s_add_u32 s10, s0, 56
	s_addc_u32 s11, s1, 0
	s_lshl_b32 s18, s12, 6
	s_mov_b32 s19, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB12_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s8, 0
	s_lshl_b64 s[20:21], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s20, s20, s6
	s_addc_u32 s21, s21, s7
	v_mad_u64_u32 v[6:7], null, v1, s9, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v6 :: v_dual_add_nc_u32 v1, s18, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s20, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s21, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v3
.LBB12_2:
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s19, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB12_6
; %bb.3:                                ; %.lr.ph.i
	ds_load_b32 v6, v5
	s_lshl_b64 s[2:3], s[2:3], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s18, v1
	s_add_u32 s2, s6, s2
	s_addc_u32 s6, s7, s3
	s_mov_b32 s3, 0
.LBB12_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s8
	v_mul_lo_u32 v9, v1, s9
	v_mad_u64_u32 v[7:8], null, v1, s8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s6, v2, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s18, v3
	s_or_b32 s3, vcc_lo, s3
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v6, v6, v7
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB12_4
; %bb.5:                                ; %._crit_edge.i.loopexit
	s_or_b32 exec_lo, exec_lo, s3
	ds_store_b32 v5, v6
.LBB12_6:                               ; %Flow30
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB12_19
; %bb.7:
	v_or_b32_e32 v1, 32, v0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB12_9
; %bb.8:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v3, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v3
	ds_store_b32 v5, v1
.LBB12_9:
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v1, 16, v0
	v_cmp_gt_u32_e64 s2, 16, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB12_11
; %bb.10:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v2, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	ds_store_b32 v5, v1
.LBB12_11:
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s2, 8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB12_13
; %bb.12:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v3, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v3
	ds_store_b32 v5, v1
.LBB12_13:
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v1, 4, v0
	v_cmp_gt_u32_e64 s2, 4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB12_15
; %bb.14:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v2, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	ds_store_b32 v5, v1
.LBB12_15:
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s2, 2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB12_17
; %bb.16:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v2, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	ds_store_b32 v5, v1
.LBB12_17:
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_gt_u64_e64 s2, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB12_19
; %bb.18:
	v_mov_b32_e32 v3, 0
	ds_load_2addr_b32 v[1:2], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v2, v1
	ds_store_b32 v3, v1
.LBB12_19:                              ; %Flow29
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB12_25
; %bb.20:
	s_load_b32 s2, s[10:11], 0x4
	s_load_b32 s0, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s2, s15
	v_cmp_neq_f32_e64 s2, s0, 0
	s_add_i32 s1, s1, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s1, s1, s12
	s_and_b32 vcc_lo, exec_lo, s2
	s_add_i32 s2, s1, s13
	s_cbranch_vccz .LBB12_22
; %bb.21:
	s_lshl_b64 s[4:5], s[2:3], 2
	v_mov_b32_e32 v6, 0
	s_add_u32 s4, s16, s4
	s_addc_u32 s5, s17, s5
	v_cvt_f64_f32_e32 v[0:1], s0
	s_load_b32 s1, s[4:5], 0x0
	ds_load_b32 v4, v6
	s_mov_b32 s0, 0
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[2:3], s1
	v_cvt_f64_f32_e32 v[4:5], v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]
	v_cvt_f32_f64_e32 v0, v[0:1]
	global_store_b32 v6, v0, s[4:5]
	s_branch .LBB12_23
.LBB12_22:
	s_mov_b32 s0, -1
.LBB12_23:                              ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB12_25
; %bb.24:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB12_25:                              ; %_Z11cuda_reduceILj64Ef3SumEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_sum_64_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end12:
	.size	cuda_sum_64_float, .Lfunc_end12-cuda_sum_64_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1112
; NumSgprs: 24
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_sum_32_float       ; -- Begin function cuda_sum_32_float
	.globl	cuda_sum_32_float
	.p2align	8
	.type	cuda_sum_32_float,@function
cuda_sum_32_float:                      ; @cuda_sum_32_float
; %bb.0:
	s_clause 0x4
	s_load_b128 s[8:11], s[0:1], 0x20
	s_load_b64 s[2:3], s[0:1], 0x30
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x38
	s_load_b64 s[16:17], s[0:1], 0x10
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 5, v0
	v_lshl_add_u32 v5, v0, 2, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s11, s14, s11
	s_mul_hi_u32 s18, s14, s10
	s_mul_i32 s3, s15, s3
	s_mul_hi_u32 s19, s15, s2
	s_mul_i32 s10, s14, s10
	s_mul_i32 s2, s15, s2
	s_add_i32 s18, s18, s11
	s_add_i32 s19, s19, s3
	s_add_u32 s2, s2, s10
	s_addc_u32 s3, s19, s18
	s_add_u32 s10, s0, 56
	s_addc_u32 s11, s1, 0
	s_lshl_b32 s18, s12, 5
	s_mov_b32 s19, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB13_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s8, 0
	s_lshl_b64 s[20:21], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s20, s20, s6
	s_addc_u32 s21, s21, s7
	v_mad_u64_u32 v[6:7], null, v1, s9, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v6 :: v_dual_add_nc_u32 v1, s18, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s20, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s21, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v3
.LBB13_2:
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s19, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB13_6
; %bb.3:                                ; %.lr.ph.i
	ds_load_b32 v6, v5
	s_lshl_b64 s[2:3], s[2:3], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s18, v1
	s_add_u32 s2, s6, s2
	s_addc_u32 s6, s7, s3
	s_mov_b32 s3, 0
.LBB13_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s8
	v_mul_lo_u32 v9, v1, s9
	v_mad_u64_u32 v[7:8], null, v1, s8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s6, v2, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s18, v3
	s_or_b32 s3, vcc_lo, s3
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v6, v6, v7
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB13_4
; %bb.5:                                ; %._crit_edge.i.loopexit
	s_or_b32 exec_lo, exec_lo, s3
	ds_store_b32 v5, v6
.LBB13_6:                               ; %Flow30
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB13_17
; %bb.7:
	v_or_b32_e32 v1, 16, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s2, 16, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB13_9
; %bb.8:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v3, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v3
	ds_store_b32 v5, v1
.LBB13_9:
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v1, 8, v0
	v_cmp_gt_u32_e64 s2, 8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB13_11
; %bb.10:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v2, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	ds_store_b32 v5, v1
.LBB13_11:
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s2, 4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB13_13
; %bb.12:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v3, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v3
	ds_store_b32 v5, v1
.LBB13_13:
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v1, 2, v0
	v_cmp_gt_u32_e64 s2, 2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB13_15
; %bb.14:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v2, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	ds_store_b32 v5, v1
.LBB13_15:
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_gt_u64_e64 s2, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB13_17
; %bb.16:
	v_mov_b32_e32 v3, 0
	ds_load_2addr_b32 v[1:2], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v2, v1
	ds_store_b32 v3, v1
.LBB13_17:                              ; %Flow29
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB13_23
; %bb.18:
	s_load_b32 s2, s[10:11], 0x4
	s_load_b32 s0, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s2, s15
	v_cmp_neq_f32_e64 s2, s0, 0
	s_add_i32 s1, s1, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s1, s1, s12
	s_and_b32 vcc_lo, exec_lo, s2
	s_add_i32 s2, s1, s13
	s_cbranch_vccz .LBB13_20
; %bb.19:
	s_lshl_b64 s[4:5], s[2:3], 2
	v_mov_b32_e32 v6, 0
	s_add_u32 s4, s16, s4
	s_addc_u32 s5, s17, s5
	v_cvt_f64_f32_e32 v[0:1], s0
	s_load_b32 s1, s[4:5], 0x0
	ds_load_b32 v4, v6
	s_mov_b32 s0, 0
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[2:3], s1
	v_cvt_f64_f32_e32 v[4:5], v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]
	v_cvt_f32_f64_e32 v0, v[0:1]
	global_store_b32 v6, v0, s[4:5]
	s_branch .LBB13_21
.LBB13_20:
	s_mov_b32 s0, -1
.LBB13_21:                              ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB13_23
; %bb.22:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB13_23:                              ; %_Z11cuda_reduceILj32Ef3SumEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_sum_32_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end13:
	.size	cuda_sum_32_float, .Lfunc_end13-cuda_sum_32_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1040
; NumSgprs: 24
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_sum_16_float       ; -- Begin function cuda_sum_16_float
	.globl	cuda_sum_16_float
	.p2align	8
	.type	cuda_sum_16_float,@function
cuda_sum_16_float:                      ; @cuda_sum_16_float
; %bb.0:
	s_clause 0x4
	s_load_b128 s[8:11], s[0:1], 0x20
	s_load_b64 s[2:3], s[0:1], 0x30
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x38
	s_load_b64 s[16:17], s[0:1], 0x10
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 4, v0
	v_lshl_add_u32 v5, v0, 2, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s11, s14, s11
	s_mul_hi_u32 s18, s14, s10
	s_mul_i32 s3, s15, s3
	s_mul_hi_u32 s19, s15, s2
	s_mul_i32 s10, s14, s10
	s_mul_i32 s2, s15, s2
	s_add_i32 s18, s18, s11
	s_add_i32 s19, s19, s3
	s_add_u32 s2, s2, s10
	s_addc_u32 s3, s19, s18
	s_add_u32 s10, s0, 56
	s_addc_u32 s11, s1, 0
	s_lshl_b32 s18, s12, 4
	s_mov_b32 s19, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB14_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s8, 0
	s_lshl_b64 s[20:21], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s20, s20, s6
	s_addc_u32 s21, s21, s7
	v_mad_u64_u32 v[6:7], null, v1, s9, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v6 :: v_dual_add_nc_u32 v1, s18, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s20, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s21, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v3
.LBB14_2:
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s19, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB14_6
; %bb.3:                                ; %.lr.ph.i
	ds_load_b32 v6, v5
	s_lshl_b64 s[2:3], s[2:3], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s18, v1
	s_add_u32 s2, s6, s2
	s_addc_u32 s6, s7, s3
	s_mov_b32 s3, 0
.LBB14_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s8
	v_mul_lo_u32 v9, v1, s9
	v_mad_u64_u32 v[7:8], null, v1, s8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s6, v2, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s18, v3
	s_or_b32 s3, vcc_lo, s3
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v6, v6, v7
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB14_4
; %bb.5:                                ; %._crit_edge.i.loopexit
	s_or_b32 exec_lo, exec_lo, s3
	ds_store_b32 v5, v6
.LBB14_6:                               ; %Flow30
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB14_15
; %bb.7:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s2, 8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB14_9
; %bb.8:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v3, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v3
	ds_store_b32 v5, v1
.LBB14_9:
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v1, 4, v0
	v_cmp_gt_u32_e64 s2, 4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB14_11
; %bb.10:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v2, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	ds_store_b32 v5, v1
.LBB14_11:
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s2, 2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB14_13
; %bb.12:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v2, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	ds_store_b32 v5, v1
.LBB14_13:
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_gt_u64_e64 s2, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB14_15
; %bb.14:
	v_mov_b32_e32 v3, 0
	ds_load_2addr_b32 v[1:2], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v2, v1
	ds_store_b32 v3, v1
.LBB14_15:                              ; %Flow29
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB14_21
; %bb.16:
	s_load_b32 s2, s[10:11], 0x4
	s_load_b32 s0, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s2, s15
	v_cmp_neq_f32_e64 s2, s0, 0
	s_add_i32 s1, s1, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s1, s1, s12
	s_and_b32 vcc_lo, exec_lo, s2
	s_add_i32 s2, s1, s13
	s_cbranch_vccz .LBB14_18
; %bb.17:
	s_lshl_b64 s[4:5], s[2:3], 2
	v_mov_b32_e32 v6, 0
	s_add_u32 s4, s16, s4
	s_addc_u32 s5, s17, s5
	v_cvt_f64_f32_e32 v[0:1], s0
	s_load_b32 s1, s[4:5], 0x0
	ds_load_b32 v4, v6
	s_mov_b32 s0, 0
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[2:3], s1
	v_cvt_f64_f32_e32 v[4:5], v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]
	v_cvt_f32_f64_e32 v0, v[0:1]
	global_store_b32 v6, v0, s[4:5]
	s_branch .LBB14_19
.LBB14_18:
	s_mov_b32 s0, -1
.LBB14_19:                              ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB14_21
; %bb.20:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB14_21:                              ; %_Z11cuda_reduceILj16Ef3SumEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_sum_16_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end14:
	.size	cuda_sum_16_float, .Lfunc_end14-cuda_sum_16_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 960
; NumSgprs: 24
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_sum_8_float        ; -- Begin function cuda_sum_8_float
	.globl	cuda_sum_8_float
	.p2align	8
	.type	cuda_sum_8_float,@function
cuda_sum_8_float:                       ; @cuda_sum_8_float
; %bb.0:
	s_clause 0x4
	s_load_b128 s[8:11], s[0:1], 0x20
	s_load_b64 s[2:3], s[0:1], 0x30
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x38
	s_load_b64 s[16:17], s[0:1], 0x10
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 3, v0
	v_lshl_add_u32 v5, v0, 2, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s11, s14, s11
	s_mul_hi_u32 s18, s14, s10
	s_mul_i32 s3, s15, s3
	s_mul_hi_u32 s19, s15, s2
	s_mul_i32 s10, s14, s10
	s_mul_i32 s2, s15, s2
	s_add_i32 s18, s18, s11
	s_add_i32 s19, s19, s3
	s_add_u32 s2, s2, s10
	s_addc_u32 s3, s19, s18
	s_add_u32 s10, s0, 56
	s_addc_u32 s11, s1, 0
	s_lshl_b32 s18, s12, 3
	s_mov_b32 s19, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB15_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s8, 0
	s_lshl_b64 s[20:21], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s20, s20, s6
	s_addc_u32 s21, s21, s7
	v_mad_u64_u32 v[6:7], null, v1, s9, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v6 :: v_dual_add_nc_u32 v1, s18, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s20, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s21, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v3
.LBB15_2:
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s19, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB15_6
; %bb.3:                                ; %.lr.ph.i
	ds_load_b32 v6, v5
	s_lshl_b64 s[2:3], s[2:3], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s18, v1
	s_add_u32 s2, s6, s2
	s_addc_u32 s6, s7, s3
	s_mov_b32 s3, 0
.LBB15_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s8
	v_mul_lo_u32 v9, v1, s9
	v_mad_u64_u32 v[7:8], null, v1, s8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s6, v2, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s18, v3
	s_or_b32 s3, vcc_lo, s3
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v6, v6, v7
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB15_4
; %bb.5:                                ; %._crit_edge.i.loopexit
	s_or_b32 exec_lo, exec_lo, s3
	ds_store_b32 v5, v6
.LBB15_6:                               ; %Flow30
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB15_13
; %bb.7:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s2, 4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB15_9
; %bb.8:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v3, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v3
	ds_store_b32 v5, v1
.LBB15_9:
	s_or_b32 exec_lo, exec_lo, s2
	v_or_b32_e32 v1, 2, v0
	v_cmp_gt_u32_e64 s2, 2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB15_11
; %bb.10:
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v2, v5
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	ds_store_b32 v5, v1
.LBB15_11:
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_gt_u64_e64 s2, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB15_13
; %bb.12:
	v_mov_b32_e32 v3, 0
	ds_load_2addr_b32 v[1:2], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v2, v1
	ds_store_b32 v3, v1
.LBB15_13:                              ; %Flow29
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB15_19
; %bb.14:
	s_load_b32 s2, s[10:11], 0x4
	s_load_b32 s0, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s2, s15
	v_cmp_neq_f32_e64 s2, s0, 0
	s_add_i32 s1, s1, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s1, s1, s12
	s_and_b32 vcc_lo, exec_lo, s2
	s_add_i32 s2, s1, s13
	s_cbranch_vccz .LBB15_16
; %bb.15:
	s_lshl_b64 s[4:5], s[2:3], 2
	v_mov_b32_e32 v6, 0
	s_add_u32 s4, s16, s4
	s_addc_u32 s5, s17, s5
	v_cvt_f64_f32_e32 v[0:1], s0
	s_load_b32 s1, s[4:5], 0x0
	ds_load_b32 v4, v6
	s_mov_b32 s0, 0
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[2:3], s1
	v_cvt_f64_f32_e32 v[4:5], v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]
	v_cvt_f32_f64_e32 v0, v[0:1]
	global_store_b32 v6, v0, s[4:5]
	s_branch .LBB15_17
.LBB15_16:
	s_mov_b32 s0, -1
.LBB15_17:                              ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB15_19
; %bb.18:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB15_19:                              ; %_Z11cuda_reduceILj8Ef3SumEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_sum_8_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end15:
	.size	cuda_sum_8_float, .Lfunc_end15-cuda_sum_8_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 876
; NumSgprs: 24
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_sum_4_float        ; -- Begin function cuda_sum_4_float
	.globl	cuda_sum_4_float
	.p2align	8
	.type	cuda_sum_4_float,@function
cuda_sum_4_float:                       ; @cuda_sum_4_float
; %bb.0:
	s_clause 0x4
	s_load_b128 s[8:11], s[0:1], 0x20
	s_load_b64 s[2:3], s[0:1], 0x30
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x38
	s_load_b64 s[16:17], s[0:1], 0x10
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 2, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s11, s14, s11
	s_mul_hi_u32 s18, s14, s10
	s_mul_i32 s3, s15, s3
	s_mul_hi_u32 s19, s15, s2
	s_mul_i32 s10, s14, s10
	s_mul_i32 s2, s15, s2
	s_add_i32 s18, s18, s11
	s_add_i32 s19, s19, s3
	s_add_u32 s2, s2, s10
	s_addc_u32 s3, s19, s18
	s_add_u32 s10, s0, 56
	s_addc_u32 s11, s1, 0
	s_lshl_b32 s18, s12, 2
	s_mov_b32 s19, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB16_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s8, 0
	s_lshl_b64 s[20:21], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s20, s20, s6
	s_addc_u32 s21, s21, s7
	v_mad_u64_u32 v[5:6], null, v1, s9, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s18, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s20, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s21, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	v_lshl_add_u32 v4, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3
.LBB16_2:
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s19, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB16_6
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v5, v0, 2, 0
	s_lshl_b64 s[2:3], s[2:3], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s18, v1
	s_add_u32 s2, s6, s2
	ds_load_b32 v6, v5
	s_addc_u32 s6, s7, s3
	s_mov_b32 s3, 0
.LBB16_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s8
	v_mul_lo_u32 v9, v1, s9
	v_mad_u64_u32 v[7:8], null, v1, s8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s6, v2, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s18, v3
	s_or_b32 s3, vcc_lo, s3
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v6, v6, v7
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB16_4
; %bb.5:                                ; %._crit_edge.i.loopexit
	s_or_b32 exec_lo, exec_lo, s3
	ds_store_b32 v5, v6
.LBB16_6:                               ; %Flow30
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB16_11
; %bb.7:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e64 s2, 2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 s6, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB16_9
; %bb.8:
	v_lshl_add_u32 v1, v1, 2, 0
	v_lshl_add_u32 v2, v0, 2, 0
	ds_load_b32 v1, v1
	ds_load_b32 v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v3
	ds_store_b32 v2, v1
.LBB16_9:
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_gt_u64_e64 s2, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB16_11
; %bb.10:
	v_mov_b32_e32 v3, 0
	ds_load_2addr_b32 v[1:2], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v2, v1
	ds_store_b32 v3, v1
.LBB16_11:                              ; %Flow29
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB16_17
; %bb.12:
	s_load_b32 s2, s[10:11], 0x4
	s_load_b32 s0, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s2, s15
	v_cmp_neq_f32_e64 s2, s0, 0
	s_add_i32 s1, s1, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s1, s1, s12
	s_and_b32 vcc_lo, exec_lo, s2
	s_add_i32 s2, s1, s13
	s_cbranch_vccz .LBB16_14
; %bb.13:
	s_lshl_b64 s[4:5], s[2:3], 2
	v_mov_b32_e32 v6, 0
	s_add_u32 s4, s16, s4
	s_addc_u32 s5, s17, s5
	v_cvt_f64_f32_e32 v[0:1], s0
	s_load_b32 s1, s[4:5], 0x0
	ds_load_b32 v4, v6
	s_mov_b32 s0, 0
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[2:3], s1
	v_cvt_f64_f32_e32 v[4:5], v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]
	v_cvt_f32_f64_e32 v0, v[0:1]
	global_store_b32 v6, v0, s[4:5]
	s_branch .LBB16_15
.LBB16_14:
	s_mov_b32 s0, -1
.LBB16_15:                              ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB16_17
; %bb.16:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB16_17:                              ; %_Z11cuda_reduceILj4Ef3SumEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_sum_4_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end16:
	.size	cuda_sum_4_float, .Lfunc_end16-cuda_sum_4_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 812
; NumSgprs: 24
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_sum_2_float        ; -- Begin function cuda_sum_2_float
	.globl	cuda_sum_2_float
	.p2align	8
	.type	cuda_sum_2_float,@function
cuda_sum_2_float:                       ; @cuda_sum_2_float
; %bb.0:
	s_clause 0x4
	s_load_b128 s[8:11], s[0:1], 0x20
	s_load_b64 s[16:17], s[0:1], 0x30
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x38
	s_load_b64 s[2:3], s[0:1], 0x10
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 1, v0
	v_lshl_add_u32 v5, v0, 2, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s11, s14, s11
	s_mul_hi_u32 s18, s14, s10
	s_mul_i32 s17, s15, s17
	s_mul_hi_u32 s19, s15, s16
	s_mul_i32 s10, s14, s10
	s_mul_i32 s16, s15, s16
	s_add_i32 s18, s18, s11
	s_add_i32 s19, s19, s17
	s_add_u32 s16, s16, s10
	s_addc_u32 s17, s19, s18
	s_add_u32 s10, s0, 56
	s_addc_u32 s11, s1, 0
	s_lshl_b32 s18, s12, 1
	s_mov_b32 s19, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB17_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s8, 0
	s_lshl_b64 s[20:21], s[16:17], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s20, s20, s6
	s_addc_u32 s21, s21, s7
	v_mad_u64_u32 v[6:7], null, v1, s9, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v6 :: v_dual_add_nc_u32 v1, s18, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s20, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s21, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v3
.LBB17_2:
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s19, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB17_6
; %bb.3:                                ; %.lr.ph.i
	ds_load_b32 v6, v5
	s_lshl_b64 s[16:17], s[16:17], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s18, v1
	s_add_u32 s6, s6, s16
	s_addc_u32 s16, s7, s17
	s_mov_b32 s7, 0
.LBB17_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s8
	v_mul_lo_u32 v9, v1, s9
	v_mad_u64_u32 v[7:8], null, v1, s8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s16, v2, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s18, v3
	s_or_b32 s7, vcc_lo, s7
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v6, v6, v7
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB17_4
; %bb.5:                                ; %._crit_edge.i.loopexit
	s_or_b32 exec_lo, exec_lo, s7
	ds_store_b32 v5, v6
.LBB17_6:                               ; %Flow28
	s_or_b32 exec_lo, exec_lo, s19
	v_cmp_gt_u64_e64 s4, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 s5, vcc_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s5
	s_cbranch_execz .LBB17_8
; %bb.7:
	v_mov_b32_e32 v2, 0
	ds_load_2addr_b32 v[0:1], v2 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v0, v1, v0
	ds_store_b32 v2, v0
.LBB17_8:
	s_or_b32 exec_lo, exec_lo, s4
	s_and_saveexec_b32 s4, vcc_lo
	s_cbranch_execz .LBB17_14
; %bb.9:
	s_load_b32 s5, s[10:11], 0x4
	s_load_b32 s4, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s5, s15
	v_cmp_neq_f32_e64 s1, s4, 0
	s_add_i32 s0, s0, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s0, s0, s12
	s_and_b32 vcc_lo, exec_lo, s1
	s_add_i32 s0, s0, s13
	s_mov_b32 s1, 0
	s_cbranch_vccz .LBB17_11
; %bb.10:
	s_lshl_b64 s[6:7], s[0:1], 2
	v_mov_b32_e32 v6, 0
	s_add_u32 s6, s2, s6
	s_addc_u32 s7, s3, s7
	v_cvt_f64_f32_e32 v[0:1], s4
	s_load_b32 s5, s[6:7], 0x0
	ds_load_b32 v4, v6
	s_mov_b32 s4, s1
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[2:3], s5
	v_cvt_f64_f32_e32 v[4:5], v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]
	v_cvt_f32_f64_e32 v0, v[0:1]
	global_store_b32 v6, v0, s[6:7]
	s_branch .LBB17_12
.LBB17_11:
	s_mov_b32 s4, -1
.LBB17_12:                              ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB17_14
; %bb.13:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[0:1], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB17_14:                              ; %_Z11cuda_reduceILj2Ef3SumEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_sum_2_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end17:
	.size	cuda_sum_2_float, .Lfunc_end17-cuda_sum_2_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 692
; NumSgprs: 24
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_maximum_512_double ; -- Begin function cuda_maximum_512_double
	.globl	cuda_maximum_512_double
	.p2align	8
	.type	cuda_maximum_512_double,@function
cuda_maximum_512_double:                ; @cuda_maximum_512_double
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 9, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 9
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB18_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshl_add_u32 v5, v0, 3, 0
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v5, v[3:4]
.LBB18_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB18_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v7, v0, 3, 0
	s_lshl_b64 s[2:3], s[2:3], 3
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b64 v[5:6], v7
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB18_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v10, v1, s11
	v_mad_u64_u32 v[8:9], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v9, v10, v2
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_lt_f64_e32 v[5:6], v[1:2]
	s_cbranch_execz .LBB18_6
; %bb.5:                                ;   in Loop: Header=BB18_4 Depth=1
	v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
	ds_store_b64 v7, v[1:2]
.LBB18_6:                               ; %_ZN3MaxclIdEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB18_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB18_4
.LBB18_7:                               ; %Flow42
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x100, v0
	s_cbranch_execz .LBB18_11
; %bb.8:
	v_or_b32_e32 v1, 0x100, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB18_11
; %bb.9:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB18_11
; %bb.10:
	ds_store_b64 v3, v[1:2]
.LBB18_11:                              ; %_ZN3MaxclIdEEvRT_S1_.exit116.i
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB18_15
; %bb.12:
	v_or_b32_e32 v1, 0x80, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB18_15
; %bb.13:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB18_15
; %bb.14:
	ds_store_b64 v3, v[1:2]
.LBB18_15:                              ; %_ZN3MaxclIdEEvRT_S1_.exit117.i
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB18_19
; %bb.16:
	v_or_b32_e32 v1, 64, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB18_19
; %bb.17:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB18_19
; %bb.18:
	ds_store_b64 v3, v[1:2]
.LBB18_19:                              ; %_ZN3MaxclIdEEvRT_S1_.exit118.i
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB18_42
; %bb.20:
	v_or_b32_e32 v1, 32, v0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB18_23
; %bb.21:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB18_23
; %bb.22:
	ds_store_b64 v3, v[1:2]
.LBB18_23:                              ; %_ZN3MaxclIdEEvRT_S1_.exit119.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB18_27
; %bb.24:
	v_or_b32_e32 v1, 16, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB18_27
; %bb.25:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB18_27
; %bb.26:
	ds_store_b64 v3, v[1:2]
.LBB18_27:                              ; %_ZN3MaxclIdEEvRT_S1_.exit120.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB18_31
; %bb.28:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB18_31
; %bb.29:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB18_31
; %bb.30:
	ds_store_b64 v3, v[1:2]
.LBB18_31:                              ; %_ZN3MaxclIdEEvRT_S1_.exit121.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB18_35
; %bb.32:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB18_35
; %bb.33:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB18_35
; %bb.34:
	ds_store_b64 v3, v[1:2]
.LBB18_35:                              ; %_ZN3MaxclIdEEvRT_S1_.exit122.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB18_39
; %bb.36:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB18_39
; %bb.37:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB18_39
; %bb.38:
	ds_store_b64 v3, v[1:2]
.LBB18_39:                              ; %_ZN3MaxclIdEEvRT_S1_.exit123.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB18_42
; %bb.40:
	v_mov_b32_e32 v5, 0
	ds_load_2addr_b64 v[1:4], v5 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f64_e32 vcc_lo, v[1:2], v[3:4]
	s_cbranch_vccnz .LBB18_42
; %bb.41:
	ds_store_b64 v5, v[3:4]
.LBB18_42:                              ; %Flow34
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB18_44
; %bb.43:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v2, 0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b64 v2, v[0:1], s[0:1]
.LBB18_44:                              ; %_Z11cuda_reduceILj512Ed3MaxEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_maximum_512_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end18:
	.size	cuda_maximum_512_double, .Lfunc_end18-cuda_maximum_512_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1460
; NumSgprs: 22
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_maximum_256_double ; -- Begin function cuda_maximum_256_double
	.globl	cuda_maximum_256_double
	.p2align	8
	.type	cuda_maximum_256_double,@function
cuda_maximum_256_double:                ; @cuda_maximum_256_double
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 8, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 8
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB19_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshl_add_u32 v5, v0, 3, 0
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v5, v[3:4]
.LBB19_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB19_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v7, v0, 3, 0
	s_lshl_b64 s[2:3], s[2:3], 3
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b64 v[5:6], v7
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB19_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v10, v1, s11
	v_mad_u64_u32 v[8:9], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v9, v10, v2
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_lt_f64_e32 v[5:6], v[1:2]
	s_cbranch_execz .LBB19_6
; %bb.5:                                ;   in Loop: Header=BB19_4 Depth=1
	v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
	ds_store_b64 v7, v[1:2]
.LBB19_6:                               ; %_ZN3MaxclIdEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB19_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB19_4
.LBB19_7:                               ; %Flow40
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB19_11
; %bb.8:
	v_or_b32_e32 v1, 0x80, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB19_11
; %bb.9:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB19_11
; %bb.10:
	ds_store_b64 v3, v[1:2]
.LBB19_11:                              ; %_ZN3MaxclIdEEvRT_S1_.exit108.i
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB19_15
; %bb.12:
	v_or_b32_e32 v1, 64, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB19_15
; %bb.13:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB19_15
; %bb.14:
	ds_store_b64 v3, v[1:2]
.LBB19_15:                              ; %_ZN3MaxclIdEEvRT_S1_.exit109.i
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB19_38
; %bb.16:
	v_or_b32_e32 v1, 32, v0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB19_19
; %bb.17:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB19_19
; %bb.18:
	ds_store_b64 v3, v[1:2]
.LBB19_19:                              ; %_ZN3MaxclIdEEvRT_S1_.exit110.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB19_23
; %bb.20:
	v_or_b32_e32 v1, 16, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB19_23
; %bb.21:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB19_23
; %bb.22:
	ds_store_b64 v3, v[1:2]
.LBB19_23:                              ; %_ZN3MaxclIdEEvRT_S1_.exit111.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB19_27
; %bb.24:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB19_27
; %bb.25:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB19_27
; %bb.26:
	ds_store_b64 v3, v[1:2]
.LBB19_27:                              ; %_ZN3MaxclIdEEvRT_S1_.exit112.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB19_31
; %bb.28:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB19_31
; %bb.29:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB19_31
; %bb.30:
	ds_store_b64 v3, v[1:2]
.LBB19_31:                              ; %_ZN3MaxclIdEEvRT_S1_.exit113.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB19_35
; %bb.32:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB19_35
; %bb.33:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB19_35
; %bb.34:
	ds_store_b64 v3, v[1:2]
.LBB19_35:                              ; %_ZN3MaxclIdEEvRT_S1_.exit114.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB19_38
; %bb.36:
	v_mov_b32_e32 v5, 0
	ds_load_2addr_b64 v[1:4], v5 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f64_e32 vcc_lo, v[1:2], v[3:4]
	s_cbranch_vccnz .LBB19_38
; %bb.37:
	ds_store_b64 v5, v[3:4]
.LBB19_38:                              ; %Flow34
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB19_40
; %bb.39:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v2, 0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b64 v2, v[0:1], s[0:1]
.LBB19_40:                              ; %_Z11cuda_reduceILj256Ed3MaxEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_maximum_256_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end19:
	.size	cuda_maximum_256_double, .Lfunc_end19-cuda_maximum_256_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1336
; NumSgprs: 22
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_maximum_128_double ; -- Begin function cuda_maximum_128_double
	.globl	cuda_maximum_128_double
	.p2align	8
	.type	cuda_maximum_128_double,@function
cuda_maximum_128_double:                ; @cuda_maximum_128_double
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 7, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 7
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB20_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshl_add_u32 v5, v0, 3, 0
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v5, v[3:4]
.LBB20_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB20_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v7, v0, 3, 0
	s_lshl_b64 s[2:3], s[2:3], 3
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b64 v[5:6], v7
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB20_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v10, v1, s11
	v_mad_u64_u32 v[8:9], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v9, v10, v2
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_lt_f64_e32 v[5:6], v[1:2]
	s_cbranch_execz .LBB20_6
; %bb.5:                                ;   in Loop: Header=BB20_4 Depth=1
	v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
	ds_store_b64 v7, v[1:2]
.LBB20_6:                               ; %_ZN3MaxclIdEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB20_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB20_4
.LBB20_7:                               ; %Flow38
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB20_11
; %bb.8:
	v_or_b32_e32 v1, 64, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB20_11
; %bb.9:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB20_11
; %bb.10:
	ds_store_b64 v3, v[1:2]
.LBB20_11:                              ; %_ZN3MaxclIdEEvRT_S1_.exit100.i
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB20_34
; %bb.12:
	v_or_b32_e32 v1, 32, v0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB20_15
; %bb.13:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB20_15
; %bb.14:
	ds_store_b64 v3, v[1:2]
.LBB20_15:                              ; %_ZN3MaxclIdEEvRT_S1_.exit101.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB20_19
; %bb.16:
	v_or_b32_e32 v1, 16, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB20_19
; %bb.17:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB20_19
; %bb.18:
	ds_store_b64 v3, v[1:2]
.LBB20_19:                              ; %_ZN3MaxclIdEEvRT_S1_.exit102.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB20_23
; %bb.20:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB20_23
; %bb.21:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB20_23
; %bb.22:
	ds_store_b64 v3, v[1:2]
.LBB20_23:                              ; %_ZN3MaxclIdEEvRT_S1_.exit103.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB20_27
; %bb.24:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB20_27
; %bb.25:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB20_27
; %bb.26:
	ds_store_b64 v3, v[1:2]
.LBB20_27:                              ; %_ZN3MaxclIdEEvRT_S1_.exit104.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB20_31
; %bb.28:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB20_31
; %bb.29:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB20_31
; %bb.30:
	ds_store_b64 v3, v[1:2]
.LBB20_31:                              ; %_ZN3MaxclIdEEvRT_S1_.exit105.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB20_34
; %bb.32:
	v_mov_b32_e32 v5, 0
	ds_load_2addr_b64 v[1:4], v5 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f64_e32 vcc_lo, v[1:2], v[3:4]
	s_cbranch_vccnz .LBB20_34
; %bb.33:
	ds_store_b64 v5, v[3:4]
.LBB20_34:                              ; %Flow34
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB20_36
; %bb.35:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v2, 0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b64 v2, v[0:1], s[0:1]
.LBB20_36:                              ; %_Z11cuda_reduceILj128Ed3MaxEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_maximum_128_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end20:
	.size	cuda_maximum_128_double, .Lfunc_end20-cuda_maximum_128_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1212
; NumSgprs: 22
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_maximum_64_double  ; -- Begin function cuda_maximum_64_double
	.globl	cuda_maximum_64_double
	.p2align	8
	.type	cuda_maximum_64_double,@function
cuda_maximum_64_double:                 ; @cuda_maximum_64_double
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 6, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 6
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB21_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshl_add_u32 v5, v0, 3, 0
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v5, v[3:4]
.LBB21_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB21_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v7, v0, 3, 0
	s_lshl_b64 s[2:3], s[2:3], 3
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b64 v[5:6], v7
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB21_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v10, v1, s11
	v_mad_u64_u32 v[8:9], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v9, v10, v2
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_lt_f64_e32 v[5:6], v[1:2]
	s_cbranch_execz .LBB21_6
; %bb.5:                                ;   in Loop: Header=BB21_4 Depth=1
	v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
	ds_store_b64 v7, v[1:2]
.LBB21_6:                               ; %_ZN3MaxclIdEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB21_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB21_4
.LBB21_7:                               ; %Flow36
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB21_30
; %bb.8:
	v_or_b32_e32 v1, 32, v0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB21_11
; %bb.9:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB21_11
; %bb.10:
	ds_store_b64 v3, v[1:2]
.LBB21_11:                              ; %_ZN3MaxclIdEEvRT_S1_.exit91.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB21_15
; %bb.12:
	v_or_b32_e32 v1, 16, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB21_15
; %bb.13:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB21_15
; %bb.14:
	ds_store_b64 v3, v[1:2]
.LBB21_15:                              ; %_ZN3MaxclIdEEvRT_S1_.exit92.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB21_19
; %bb.16:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB21_19
; %bb.17:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB21_19
; %bb.18:
	ds_store_b64 v3, v[1:2]
.LBB21_19:                              ; %_ZN3MaxclIdEEvRT_S1_.exit93.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB21_23
; %bb.20:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB21_23
; %bb.21:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB21_23
; %bb.22:
	ds_store_b64 v3, v[1:2]
.LBB21_23:                              ; %_ZN3MaxclIdEEvRT_S1_.exit94.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB21_27
; %bb.24:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB21_27
; %bb.25:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB21_27
; %bb.26:
	ds_store_b64 v3, v[1:2]
.LBB21_27:                              ; %_ZN3MaxclIdEEvRT_S1_.exit95.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB21_30
; %bb.28:
	v_mov_b32_e32 v5, 0
	ds_load_2addr_b64 v[1:4], v5 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f64_e32 vcc_lo, v[1:2], v[3:4]
	s_cbranch_vccnz .LBB21_30
; %bb.29:
	ds_store_b64 v5, v[3:4]
.LBB21_30:                              ; %Flow34
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB21_32
; %bb.31:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v2, 0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b64 v2, v[0:1], s[0:1]
.LBB21_32:                              ; %_Z11cuda_reduceILj64Ed3MaxEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_maximum_64_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end21:
	.size	cuda_maximum_64_double, .Lfunc_end21-cuda_maximum_64_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1096
; NumSgprs: 22
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_maximum_32_double  ; -- Begin function cuda_maximum_32_double
	.globl	cuda_maximum_32_double
	.p2align	8
	.type	cuda_maximum_32_double,@function
cuda_maximum_32_double:                 ; @cuda_maximum_32_double
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 5, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 5
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB22_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshl_add_u32 v5, v0, 3, 0
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v5, v[3:4]
.LBB22_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB22_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v7, v0, 3, 0
	s_lshl_b64 s[2:3], s[2:3], 3
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b64 v[5:6], v7
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB22_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v10, v1, s11
	v_mad_u64_u32 v[8:9], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v9, v10, v2
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_lt_f64_e32 v[5:6], v[1:2]
	s_cbranch_execz .LBB22_6
; %bb.5:                                ;   in Loop: Header=BB22_4 Depth=1
	v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
	ds_store_b64 v7, v[1:2]
.LBB22_6:                               ; %_ZN3MaxclIdEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB22_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB22_4
.LBB22_7:                               ; %Flow35
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB22_27
; %bb.8:
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB22_12
; %bb.9:
	v_or_b32_e32 v1, 16, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB22_12
; %bb.10:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB22_12
; %bb.11:
	ds_store_b64 v3, v[1:2]
.LBB22_12:                              ; %_ZN3MaxclIdEEvRT_S1_.exit83.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB22_16
; %bb.13:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB22_16
; %bb.14:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB22_16
; %bb.15:
	ds_store_b64 v3, v[1:2]
.LBB22_16:                              ; %_ZN3MaxclIdEEvRT_S1_.exit84.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB22_20
; %bb.17:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB22_20
; %bb.18:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB22_20
; %bb.19:
	ds_store_b64 v3, v[1:2]
.LBB22_20:                              ; %_ZN3MaxclIdEEvRT_S1_.exit85.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB22_24
; %bb.21:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB22_24
; %bb.22:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB22_24
; %bb.23:
	ds_store_b64 v3, v[1:2]
.LBB22_24:                              ; %_ZN3MaxclIdEEvRT_S1_.exit86.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB22_27
; %bb.25:
	v_mov_b32_e32 v5, 0
	ds_load_2addr_b64 v[1:4], v5 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f64_e32 vcc_lo, v[1:2], v[3:4]
	s_cbranch_vccnz .LBB22_27
; %bb.26:
	ds_store_b64 v5, v[3:4]
.LBB22_27:                              ; %Flow33
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB22_29
; %bb.28:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v2, 0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b64 v2, v[0:1], s[0:1]
.LBB22_29:                              ; %_Z11cuda_reduceILj32Ed3MaxEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_maximum_32_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end22:
	.size	cuda_maximum_32_double, .Lfunc_end22-cuda_maximum_32_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1004
; NumSgprs: 22
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_maximum_16_double  ; -- Begin function cuda_maximum_16_double
	.globl	cuda_maximum_16_double
	.p2align	8
	.type	cuda_maximum_16_double,@function
cuda_maximum_16_double:                 ; @cuda_maximum_16_double
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 4, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 4
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB23_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshl_add_u32 v5, v0, 3, 0
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v5, v[3:4]
.LBB23_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB23_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v7, v0, 3, 0
	s_lshl_b64 s[2:3], s[2:3], 3
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b64 v[5:6], v7
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB23_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v10, v1, s11
	v_mad_u64_u32 v[8:9], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v9, v10, v2
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_lt_f64_e32 v[5:6], v[1:2]
	s_cbranch_execz .LBB23_6
; %bb.5:                                ;   in Loop: Header=BB23_4 Depth=1
	v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
	ds_store_b64 v7, v[1:2]
.LBB23_6:                               ; %_ZN3MaxclIdEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB23_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB23_4
.LBB23_7:                               ; %Flow33
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB23_23
; %bb.8:
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB23_12
; %bb.9:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB23_12
; %bb.10:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB23_12
; %bb.11:
	ds_store_b64 v3, v[1:2]
.LBB23_12:                              ; %_ZN3MaxclIdEEvRT_S1_.exit75.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB23_16
; %bb.13:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB23_16
; %bb.14:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB23_16
; %bb.15:
	ds_store_b64 v3, v[1:2]
.LBB23_16:                              ; %_ZN3MaxclIdEEvRT_S1_.exit76.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB23_20
; %bb.17:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB23_20
; %bb.18:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB23_20
; %bb.19:
	ds_store_b64 v3, v[1:2]
.LBB23_20:                              ; %_ZN3MaxclIdEEvRT_S1_.exit77.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB23_23
; %bb.21:
	v_mov_b32_e32 v5, 0
	ds_load_2addr_b64 v[1:4], v5 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f64_e32 vcc_lo, v[1:2], v[3:4]
	s_cbranch_vccnz .LBB23_23
; %bb.22:
	ds_store_b64 v5, v[3:4]
.LBB23_23:                              ; %Flow31
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB23_25
; %bb.24:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v2, 0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b64 v2, v[0:1], s[0:1]
.LBB23_25:                              ; %_Z11cuda_reduceILj16Ed3MaxEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_maximum_16_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end23:
	.size	cuda_maximum_16_double, .Lfunc_end23-cuda_maximum_16_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 904
; NumSgprs: 22
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_maximum_8_double   ; -- Begin function cuda_maximum_8_double
	.globl	cuda_maximum_8_double
	.p2align	8
	.type	cuda_maximum_8_double,@function
cuda_maximum_8_double:                  ; @cuda_maximum_8_double
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 3, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 3
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB24_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshl_add_u32 v5, v0, 3, 0
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v5, v[3:4]
.LBB24_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB24_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v7, v0, 3, 0
	s_lshl_b64 s[2:3], s[2:3], 3
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b64 v[5:6], v7
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB24_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v10, v1, s11
	v_mad_u64_u32 v[8:9], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v9, v10, v2
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_lt_f64_e32 v[5:6], v[1:2]
	s_cbranch_execz .LBB24_6
; %bb.5:                                ;   in Loop: Header=BB24_4 Depth=1
	v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
	ds_store_b64 v7, v[1:2]
.LBB24_6:                               ; %_ZN3MaxclIdEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB24_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB24_4
.LBB24_7:                               ; %Flow31
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB24_19
; %bb.8:
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB24_12
; %bb.9:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB24_12
; %bb.10:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB24_12
; %bb.11:
	ds_store_b64 v3, v[1:2]
.LBB24_12:                              ; %_ZN3MaxclIdEEvRT_S1_.exit67.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB24_16
; %bb.13:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB24_16
; %bb.14:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB24_16
; %bb.15:
	ds_store_b64 v3, v[1:2]
.LBB24_16:                              ; %_ZN3MaxclIdEEvRT_S1_.exit68.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB24_19
; %bb.17:
	v_mov_b32_e32 v5, 0
	ds_load_2addr_b64 v[1:4], v5 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f64_e32 vcc_lo, v[1:2], v[3:4]
	s_cbranch_vccnz .LBB24_19
; %bb.18:
	ds_store_b64 v5, v[3:4]
.LBB24_19:                              ; %Flow29
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB24_21
; %bb.20:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v2, 0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b64 v2, v[0:1], s[0:1]
.LBB24_21:                              ; %_Z11cuda_reduceILj8Ed3MaxEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_maximum_8_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end24:
	.size	cuda_maximum_8_double, .Lfunc_end24-cuda_maximum_8_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 804
; NumSgprs: 22
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_maximum_4_double   ; -- Begin function cuda_maximum_4_double
	.globl	cuda_maximum_4_double
	.p2align	8
	.type	cuda_maximum_4_double,@function
cuda_maximum_4_double:                  ; @cuda_maximum_4_double
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 2, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 2
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB25_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshl_add_u32 v5, v0, 3, 0
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v5, v[3:4]
.LBB25_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB25_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v7, v0, 3, 0
	s_lshl_b64 s[2:3], s[2:3], 3
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b64 v[5:6], v7
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB25_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v10, v1, s11
	v_mad_u64_u32 v[8:9], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v9, v10, v2
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_lt_f64_e32 v[5:6], v[1:2]
	s_cbranch_execz .LBB25_6
; %bb.5:                                ;   in Loop: Header=BB25_4 Depth=1
	v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
	ds_store_b64 v7, v[1:2]
.LBB25_6:                               ; %_ZN3MaxclIdEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB25_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB25_4
.LBB25_7:                               ; %Flow29
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB25_15
; %bb.8:
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB25_12
; %bb.9:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB25_12
; %bb.10:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB25_12
; %bb.11:
	ds_store_b64 v3, v[1:2]
.LBB25_12:                              ; %_ZN3MaxclIdEEvRT_S1_.exit59.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB25_15
; %bb.13:
	v_mov_b32_e32 v5, 0
	ds_load_2addr_b64 v[1:4], v5 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f64_e32 vcc_lo, v[1:2], v[3:4]
	s_cbranch_vccnz .LBB25_15
; %bb.14:
	ds_store_b64 v5, v[3:4]
.LBB25_15:                              ; %Flow27
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB25_17
; %bb.16:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v2, 0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b64 v2, v[0:1], s[0:1]
.LBB25_17:                              ; %_Z11cuda_reduceILj4Ed3MaxEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_maximum_4_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end25:
	.size	cuda_maximum_4_double, .Lfunc_end25-cuda_maximum_4_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 704
; NumSgprs: 22
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_maximum_2_double   ; -- Begin function cuda_maximum_2_double
	.globl	cuda_maximum_2_double
	.p2align	8
	.type	cuda_maximum_2_double,@function
cuda_maximum_2_double:                  ; @cuda_maximum_2_double
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 1, v0
	v_lshl_add_u32 v7, v0, 3, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s16, s18, s16
	s_addc_u32 s17, s19, s3
	s_add_u32 s2, s0, 48
	s_addc_u32 s3, s1, 0
	s_lshl_b32 s0, s12, 1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB26_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[16:17], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s0, v1
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v7, v[3:4]
.LBB26_2:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB26_7
; %bb.3:                                ; %.lr.ph.i
	ds_load_b64 v[5:6], v7
	s_lshl_b64 s[16:17], s[16:17], 3
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s0, v1
	s_add_u32 s6, s6, s16
	s_addc_u32 s7, s7, s17
	s_mov_b32 s16, 0
.LBB26_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v10, v1, s11
	v_mad_u64_u32 v[8:9], null, v1, s10, 0
	s_mov_b32 s17, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v9, v10, v2
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_lt_f64_e32 v[5:6], v[1:2]
	s_cbranch_execz .LBB26_6
; %bb.5:                                ;   in Loop: Header=BB26_4 Depth=1
	v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
	ds_store_b64 v7, v[1:2]
.LBB26_6:                               ; %_ZN3MaxclIdEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB26_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s0, v3
	s_or_b32 s16, vcc_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB26_4
.LBB26_7:                               ; %Flow25
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_gt_u64_e64 s1, s[4:5], 1
	v_cmp_eq_u32_e64 s0, 0, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 s4, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s4
	s_cbranch_execz .LBB26_10
; %bb.8:
	v_mov_b32_e32 v4, 0
	ds_load_2addr_b64 v[0:3], v4 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f64_e32 vcc_lo, v[0:1], v[2:3]
	s_cbranch_vccnz .LBB26_10
; %bb.9:
	ds_store_b64 v4, v[2:3]
.LBB26_10:                              ; %_ZN3MaxclIdEEvRT_S1_.exit52.i
	s_or_b32 exec_lo, exec_lo, s1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB26_12
; %bb.11:
	s_load_b32 s0, s[2:3], 0x4
	v_mov_b32_e32 v2, 0
	s_mov_b32 s1, 0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s13
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b64 v2, v[0:1], s[0:1]
.LBB26_12:                              ; %_Z11cuda_reduceILj2Ed3MaxEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_maximum_2_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end26:
	.size	cuda_maximum_2_double, .Lfunc_end26-cuda_maximum_2_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 584
; NumSgprs: 22
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_maximum_512_float  ; -- Begin function cuda_maximum_512_float
	.globl	cuda_maximum_512_float
	.p2align	8
	.type	cuda_maximum_512_float,@function
cuda_maximum_512_float:                 ; @cuda_maximum_512_float
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 9, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 9
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB27_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	v_lshl_add_u32 v4, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3
.LBB27_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB27_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v5, v0, 2, 0
	s_lshl_b64 s[2:3], s[2:3], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b32 v6, v5
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB27_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v9, v1, s11
	v_mad_u64_u32 v[7:8], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_lt_f32_e32 v6, v1
	s_cbranch_execz .LBB27_6
; %bb.5:                                ;   in Loop: Header=BB27_4 Depth=1
	v_mov_b32_e32 v6, v1
	ds_store_b32 v5, v1
.LBB27_6:                               ; %_ZN3MaxclIfEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB27_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB27_4
.LBB27_7:                               ; %Flow42
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x100, v0
	s_cbranch_execz .LBB27_11
; %bb.8:
	v_or_b32_e32 v1, 0x100, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB27_11
; %bb.9:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB27_11
; %bb.10:
	ds_store_b32 v1, v2
.LBB27_11:                              ; %_ZN3MaxclIfEEvRT_S1_.exit116.i
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB27_15
; %bb.12:
	v_or_b32_e32 v1, 0x80, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB27_15
; %bb.13:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB27_15
; %bb.14:
	ds_store_b32 v1, v2
.LBB27_15:                              ; %_ZN3MaxclIfEEvRT_S1_.exit117.i
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB27_19
; %bb.16:
	v_or_b32_e32 v1, 64, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB27_19
; %bb.17:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB27_19
; %bb.18:
	ds_store_b32 v1, v2
.LBB27_19:                              ; %_ZN3MaxclIfEEvRT_S1_.exit118.i
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB27_42
; %bb.20:
	v_or_b32_e32 v1, 32, v0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB27_23
; %bb.21:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB27_23
; %bb.22:
	ds_store_b32 v1, v2
.LBB27_23:                              ; %_ZN3MaxclIfEEvRT_S1_.exit119.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB27_27
; %bb.24:
	v_or_b32_e32 v1, 16, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB27_27
; %bb.25:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB27_27
; %bb.26:
	ds_store_b32 v1, v2
.LBB27_27:                              ; %_ZN3MaxclIfEEvRT_S1_.exit120.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB27_31
; %bb.28:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB27_31
; %bb.29:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB27_31
; %bb.30:
	ds_store_b32 v1, v2
.LBB27_31:                              ; %_ZN3MaxclIfEEvRT_S1_.exit121.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB27_35
; %bb.32:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB27_35
; %bb.33:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB27_35
; %bb.34:
	ds_store_b32 v1, v2
.LBB27_35:                              ; %_ZN3MaxclIfEEvRT_S1_.exit122.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB27_39
; %bb.36:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB27_39
; %bb.37:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB27_39
; %bb.38:
	ds_store_b32 v1, v2
.LBB27_39:                              ; %_ZN3MaxclIfEEvRT_S1_.exit123.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB27_42
; %bb.40:
	v_mov_b32_e32 v3, 0
	ds_load_2addr_b32 v[1:2], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f32_e32 vcc_lo, v1, v2
	s_cbranch_vccnz .LBB27_42
; %bb.41:
	ds_store_b32 v3, v2
.LBB27_42:                              ; %Flow34
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB27_44
; %bb.43:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v0, 0
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b32 v0, v1, s[0:1]
.LBB27_44:                              ; %_Z11cuda_reduceILj512Ef3MaxEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_maximum_512_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end27:
	.size	cuda_maximum_512_float, .Lfunc_end27-cuda_maximum_512_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1456
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_maximum_256_float  ; -- Begin function cuda_maximum_256_float
	.globl	cuda_maximum_256_float
	.p2align	8
	.type	cuda_maximum_256_float,@function
cuda_maximum_256_float:                 ; @cuda_maximum_256_float
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 8, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 8
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB28_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	v_lshl_add_u32 v4, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3
.LBB28_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB28_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v5, v0, 2, 0
	s_lshl_b64 s[2:3], s[2:3], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b32 v6, v5
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB28_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v9, v1, s11
	v_mad_u64_u32 v[7:8], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_lt_f32_e32 v6, v1
	s_cbranch_execz .LBB28_6
; %bb.5:                                ;   in Loop: Header=BB28_4 Depth=1
	v_mov_b32_e32 v6, v1
	ds_store_b32 v5, v1
.LBB28_6:                               ; %_ZN3MaxclIfEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB28_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB28_4
.LBB28_7:                               ; %Flow40
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB28_11
; %bb.8:
	v_or_b32_e32 v1, 0x80, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB28_11
; %bb.9:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB28_11
; %bb.10:
	ds_store_b32 v1, v2
.LBB28_11:                              ; %_ZN3MaxclIfEEvRT_S1_.exit108.i
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB28_15
; %bb.12:
	v_or_b32_e32 v1, 64, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB28_15
; %bb.13:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB28_15
; %bb.14:
	ds_store_b32 v1, v2
.LBB28_15:                              ; %_ZN3MaxclIfEEvRT_S1_.exit109.i
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB28_38
; %bb.16:
	v_or_b32_e32 v1, 32, v0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB28_19
; %bb.17:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB28_19
; %bb.18:
	ds_store_b32 v1, v2
.LBB28_19:                              ; %_ZN3MaxclIfEEvRT_S1_.exit110.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB28_23
; %bb.20:
	v_or_b32_e32 v1, 16, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB28_23
; %bb.21:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB28_23
; %bb.22:
	ds_store_b32 v1, v2
.LBB28_23:                              ; %_ZN3MaxclIfEEvRT_S1_.exit111.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB28_27
; %bb.24:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB28_27
; %bb.25:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB28_27
; %bb.26:
	ds_store_b32 v1, v2
.LBB28_27:                              ; %_ZN3MaxclIfEEvRT_S1_.exit112.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB28_31
; %bb.28:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB28_31
; %bb.29:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB28_31
; %bb.30:
	ds_store_b32 v1, v2
.LBB28_31:                              ; %_ZN3MaxclIfEEvRT_S1_.exit113.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB28_35
; %bb.32:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB28_35
; %bb.33:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB28_35
; %bb.34:
	ds_store_b32 v1, v2
.LBB28_35:                              ; %_ZN3MaxclIfEEvRT_S1_.exit114.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB28_38
; %bb.36:
	v_mov_b32_e32 v3, 0
	ds_load_2addr_b32 v[1:2], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f32_e32 vcc_lo, v1, v2
	s_cbranch_vccnz .LBB28_38
; %bb.37:
	ds_store_b32 v3, v2
.LBB28_38:                              ; %Flow34
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB28_40
; %bb.39:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v0, 0
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b32 v0, v1, s[0:1]
.LBB28_40:                              ; %_Z11cuda_reduceILj256Ef3MaxEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_maximum_256_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end28:
	.size	cuda_maximum_256_float, .Lfunc_end28-cuda_maximum_256_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1332
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_maximum_128_float  ; -- Begin function cuda_maximum_128_float
	.globl	cuda_maximum_128_float
	.p2align	8
	.type	cuda_maximum_128_float,@function
cuda_maximum_128_float:                 ; @cuda_maximum_128_float
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 7, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 7
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB29_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	v_lshl_add_u32 v4, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3
.LBB29_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB29_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v5, v0, 2, 0
	s_lshl_b64 s[2:3], s[2:3], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b32 v6, v5
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB29_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v9, v1, s11
	v_mad_u64_u32 v[7:8], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_lt_f32_e32 v6, v1
	s_cbranch_execz .LBB29_6
; %bb.5:                                ;   in Loop: Header=BB29_4 Depth=1
	v_mov_b32_e32 v6, v1
	ds_store_b32 v5, v1
.LBB29_6:                               ; %_ZN3MaxclIfEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB29_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB29_4
.LBB29_7:                               ; %Flow38
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB29_11
; %bb.8:
	v_or_b32_e32 v1, 64, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB29_11
; %bb.9:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB29_11
; %bb.10:
	ds_store_b32 v1, v2
.LBB29_11:                              ; %_ZN3MaxclIfEEvRT_S1_.exit100.i
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB29_34
; %bb.12:
	v_or_b32_e32 v1, 32, v0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB29_15
; %bb.13:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB29_15
; %bb.14:
	ds_store_b32 v1, v2
.LBB29_15:                              ; %_ZN3MaxclIfEEvRT_S1_.exit101.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB29_19
; %bb.16:
	v_or_b32_e32 v1, 16, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB29_19
; %bb.17:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB29_19
; %bb.18:
	ds_store_b32 v1, v2
.LBB29_19:                              ; %_ZN3MaxclIfEEvRT_S1_.exit102.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB29_23
; %bb.20:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB29_23
; %bb.21:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB29_23
; %bb.22:
	ds_store_b32 v1, v2
.LBB29_23:                              ; %_ZN3MaxclIfEEvRT_S1_.exit103.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB29_27
; %bb.24:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB29_27
; %bb.25:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB29_27
; %bb.26:
	ds_store_b32 v1, v2
.LBB29_27:                              ; %_ZN3MaxclIfEEvRT_S1_.exit104.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB29_31
; %bb.28:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB29_31
; %bb.29:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB29_31
; %bb.30:
	ds_store_b32 v1, v2
.LBB29_31:                              ; %_ZN3MaxclIfEEvRT_S1_.exit105.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB29_34
; %bb.32:
	v_mov_b32_e32 v3, 0
	ds_load_2addr_b32 v[1:2], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f32_e32 vcc_lo, v1, v2
	s_cbranch_vccnz .LBB29_34
; %bb.33:
	ds_store_b32 v3, v2
.LBB29_34:                              ; %Flow34
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB29_36
; %bb.35:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v0, 0
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b32 v0, v1, s[0:1]
.LBB29_36:                              ; %_Z11cuda_reduceILj128Ef3MaxEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_maximum_128_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end29:
	.size	cuda_maximum_128_float, .Lfunc_end29-cuda_maximum_128_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1208
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_maximum_64_float   ; -- Begin function cuda_maximum_64_float
	.globl	cuda_maximum_64_float
	.p2align	8
	.type	cuda_maximum_64_float,@function
cuda_maximum_64_float:                  ; @cuda_maximum_64_float
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 6, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 6
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB30_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	v_lshl_add_u32 v4, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3
.LBB30_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB30_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v5, v0, 2, 0
	s_lshl_b64 s[2:3], s[2:3], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b32 v6, v5
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB30_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v9, v1, s11
	v_mad_u64_u32 v[7:8], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_lt_f32_e32 v6, v1
	s_cbranch_execz .LBB30_6
; %bb.5:                                ;   in Loop: Header=BB30_4 Depth=1
	v_mov_b32_e32 v6, v1
	ds_store_b32 v5, v1
.LBB30_6:                               ; %_ZN3MaxclIfEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB30_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB30_4
.LBB30_7:                               ; %Flow36
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB30_30
; %bb.8:
	v_or_b32_e32 v1, 32, v0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB30_11
; %bb.9:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB30_11
; %bb.10:
	ds_store_b32 v1, v2
.LBB30_11:                              ; %_ZN3MaxclIfEEvRT_S1_.exit91.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB30_15
; %bb.12:
	v_or_b32_e32 v1, 16, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB30_15
; %bb.13:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB30_15
; %bb.14:
	ds_store_b32 v1, v2
.LBB30_15:                              ; %_ZN3MaxclIfEEvRT_S1_.exit92.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB30_19
; %bb.16:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB30_19
; %bb.17:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB30_19
; %bb.18:
	ds_store_b32 v1, v2
.LBB30_19:                              ; %_ZN3MaxclIfEEvRT_S1_.exit93.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB30_23
; %bb.20:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB30_23
; %bb.21:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB30_23
; %bb.22:
	ds_store_b32 v1, v2
.LBB30_23:                              ; %_ZN3MaxclIfEEvRT_S1_.exit94.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB30_27
; %bb.24:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB30_27
; %bb.25:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB30_27
; %bb.26:
	ds_store_b32 v1, v2
.LBB30_27:                              ; %_ZN3MaxclIfEEvRT_S1_.exit95.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB30_30
; %bb.28:
	v_mov_b32_e32 v3, 0
	ds_load_2addr_b32 v[1:2], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f32_e32 vcc_lo, v1, v2
	s_cbranch_vccnz .LBB30_30
; %bb.29:
	ds_store_b32 v3, v2
.LBB30_30:                              ; %Flow34
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB30_32
; %bb.31:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v0, 0
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b32 v0, v1, s[0:1]
.LBB30_32:                              ; %_Z11cuda_reduceILj64Ef3MaxEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_maximum_64_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end30:
	.size	cuda_maximum_64_float, .Lfunc_end30-cuda_maximum_64_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1092
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_maximum_32_float   ; -- Begin function cuda_maximum_32_float
	.globl	cuda_maximum_32_float
	.p2align	8
	.type	cuda_maximum_32_float,@function
cuda_maximum_32_float:                  ; @cuda_maximum_32_float
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 5, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 5
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB31_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	v_lshl_add_u32 v4, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3
.LBB31_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB31_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v5, v0, 2, 0
	s_lshl_b64 s[2:3], s[2:3], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b32 v6, v5
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB31_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v9, v1, s11
	v_mad_u64_u32 v[7:8], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_lt_f32_e32 v6, v1
	s_cbranch_execz .LBB31_6
; %bb.5:                                ;   in Loop: Header=BB31_4 Depth=1
	v_mov_b32_e32 v6, v1
	ds_store_b32 v5, v1
.LBB31_6:                               ; %_ZN3MaxclIfEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB31_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB31_4
.LBB31_7:                               ; %Flow35
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB31_27
; %bb.8:
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB31_12
; %bb.9:
	v_or_b32_e32 v1, 16, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB31_12
; %bb.10:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB31_12
; %bb.11:
	ds_store_b32 v1, v2
.LBB31_12:                              ; %_ZN3MaxclIfEEvRT_S1_.exit83.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB31_16
; %bb.13:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB31_16
; %bb.14:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB31_16
; %bb.15:
	ds_store_b32 v1, v2
.LBB31_16:                              ; %_ZN3MaxclIfEEvRT_S1_.exit84.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB31_20
; %bb.17:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB31_20
; %bb.18:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB31_20
; %bb.19:
	ds_store_b32 v1, v2
.LBB31_20:                              ; %_ZN3MaxclIfEEvRT_S1_.exit85.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB31_24
; %bb.21:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB31_24
; %bb.22:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB31_24
; %bb.23:
	ds_store_b32 v1, v2
.LBB31_24:                              ; %_ZN3MaxclIfEEvRT_S1_.exit86.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB31_27
; %bb.25:
	v_mov_b32_e32 v3, 0
	ds_load_2addr_b32 v[1:2], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f32_e32 vcc_lo, v1, v2
	s_cbranch_vccnz .LBB31_27
; %bb.26:
	ds_store_b32 v3, v2
.LBB31_27:                              ; %Flow33
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB31_29
; %bb.28:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v0, 0
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b32 v0, v1, s[0:1]
.LBB31_29:                              ; %_Z11cuda_reduceILj32Ef3MaxEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_maximum_32_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end31:
	.size	cuda_maximum_32_float, .Lfunc_end31-cuda_maximum_32_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1000
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_maximum_16_float   ; -- Begin function cuda_maximum_16_float
	.globl	cuda_maximum_16_float
	.p2align	8
	.type	cuda_maximum_16_float,@function
cuda_maximum_16_float:                  ; @cuda_maximum_16_float
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 4, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 4
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB32_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	v_lshl_add_u32 v4, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3
.LBB32_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB32_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v5, v0, 2, 0
	s_lshl_b64 s[2:3], s[2:3], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b32 v6, v5
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB32_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v9, v1, s11
	v_mad_u64_u32 v[7:8], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_lt_f32_e32 v6, v1
	s_cbranch_execz .LBB32_6
; %bb.5:                                ;   in Loop: Header=BB32_4 Depth=1
	v_mov_b32_e32 v6, v1
	ds_store_b32 v5, v1
.LBB32_6:                               ; %_ZN3MaxclIfEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB32_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB32_4
.LBB32_7:                               ; %Flow33
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB32_23
; %bb.8:
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB32_12
; %bb.9:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB32_12
; %bb.10:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB32_12
; %bb.11:
	ds_store_b32 v1, v2
.LBB32_12:                              ; %_ZN3MaxclIfEEvRT_S1_.exit75.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB32_16
; %bb.13:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB32_16
; %bb.14:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB32_16
; %bb.15:
	ds_store_b32 v1, v2
.LBB32_16:                              ; %_ZN3MaxclIfEEvRT_S1_.exit76.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB32_20
; %bb.17:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB32_20
; %bb.18:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB32_20
; %bb.19:
	ds_store_b32 v1, v2
.LBB32_20:                              ; %_ZN3MaxclIfEEvRT_S1_.exit77.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB32_23
; %bb.21:
	v_mov_b32_e32 v3, 0
	ds_load_2addr_b32 v[1:2], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f32_e32 vcc_lo, v1, v2
	s_cbranch_vccnz .LBB32_23
; %bb.22:
	ds_store_b32 v3, v2
.LBB32_23:                              ; %Flow31
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB32_25
; %bb.24:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v0, 0
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b32 v0, v1, s[0:1]
.LBB32_25:                              ; %_Z11cuda_reduceILj16Ef3MaxEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_maximum_16_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end32:
	.size	cuda_maximum_16_float, .Lfunc_end32-cuda_maximum_16_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 900
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_maximum_8_float    ; -- Begin function cuda_maximum_8_float
	.globl	cuda_maximum_8_float
	.p2align	8
	.type	cuda_maximum_8_float,@function
cuda_maximum_8_float:                   ; @cuda_maximum_8_float
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 3, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 3
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB33_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	v_lshl_add_u32 v4, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3
.LBB33_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB33_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v5, v0, 2, 0
	s_lshl_b64 s[2:3], s[2:3], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b32 v6, v5
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB33_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v9, v1, s11
	v_mad_u64_u32 v[7:8], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_lt_f32_e32 v6, v1
	s_cbranch_execz .LBB33_6
; %bb.5:                                ;   in Loop: Header=BB33_4 Depth=1
	v_mov_b32_e32 v6, v1
	ds_store_b32 v5, v1
.LBB33_6:                               ; %_ZN3MaxclIfEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB33_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB33_4
.LBB33_7:                               ; %Flow31
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB33_19
; %bb.8:
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB33_12
; %bb.9:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB33_12
; %bb.10:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB33_12
; %bb.11:
	ds_store_b32 v1, v2
.LBB33_12:                              ; %_ZN3MaxclIfEEvRT_S1_.exit67.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB33_16
; %bb.13:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB33_16
; %bb.14:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB33_16
; %bb.15:
	ds_store_b32 v1, v2
.LBB33_16:                              ; %_ZN3MaxclIfEEvRT_S1_.exit68.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB33_19
; %bb.17:
	v_mov_b32_e32 v3, 0
	ds_load_2addr_b32 v[1:2], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f32_e32 vcc_lo, v1, v2
	s_cbranch_vccnz .LBB33_19
; %bb.18:
	ds_store_b32 v3, v2
.LBB33_19:                              ; %Flow29
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB33_21
; %bb.20:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v0, 0
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b32 v0, v1, s[0:1]
.LBB33_21:                              ; %_Z11cuda_reduceILj8Ef3MaxEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_maximum_8_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end33:
	.size	cuda_maximum_8_float, .Lfunc_end33-cuda_maximum_8_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 800
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_maximum_4_float    ; -- Begin function cuda_maximum_4_float
	.globl	cuda_maximum_4_float
	.p2align	8
	.type	cuda_maximum_4_float,@function
cuda_maximum_4_float:                   ; @cuda_maximum_4_float
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 2, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 2
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB34_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	v_lshl_add_u32 v4, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3
.LBB34_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB34_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v5, v0, 2, 0
	s_lshl_b64 s[2:3], s[2:3], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b32 v6, v5
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB34_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v9, v1, s11
	v_mad_u64_u32 v[7:8], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_lt_f32_e32 v6, v1
	s_cbranch_execz .LBB34_6
; %bb.5:                                ;   in Loop: Header=BB34_4 Depth=1
	v_mov_b32_e32 v6, v1
	ds_store_b32 v5, v1
.LBB34_6:                               ; %_ZN3MaxclIfEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB34_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB34_4
.LBB34_7:                               ; %Flow29
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB34_15
; %bb.8:
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB34_12
; %bb.9:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB34_12
; %bb.10:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB34_12
; %bb.11:
	ds_store_b32 v1, v2
.LBB34_12:                              ; %_ZN3MaxclIfEEvRT_S1_.exit59.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB34_15
; %bb.13:
	v_mov_b32_e32 v3, 0
	ds_load_2addr_b32 v[1:2], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f32_e32 vcc_lo, v1, v2
	s_cbranch_vccnz .LBB34_15
; %bb.14:
	ds_store_b32 v3, v2
.LBB34_15:                              ; %Flow27
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB34_17
; %bb.16:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v0, 0
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b32 v0, v1, s[0:1]
.LBB34_17:                              ; %_Z11cuda_reduceILj4Ef3MaxEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_maximum_4_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end34:
	.size	cuda_maximum_4_float, .Lfunc_end34-cuda_maximum_4_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 700
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_maximum_2_float    ; -- Begin function cuda_maximum_2_float
	.globl	cuda_maximum_2_float
	.p2align	8
	.type	cuda_maximum_2_float,@function
cuda_maximum_2_float:                   ; @cuda_maximum_2_float
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 1, v0
	v_lshl_add_u32 v5, v0, 2, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s16, s18, s16
	s_addc_u32 s17, s19, s3
	s_add_u32 s2, s0, 48
	s_addc_u32 s3, s1, 0
	s_lshl_b32 s0, s12, 1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB35_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[16:17], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[6:7], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v6 :: v_dual_add_nc_u32 v1, s0, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v3
.LBB35_2:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB35_7
; %bb.3:                                ; %.lr.ph.i
	ds_load_b32 v6, v5
	s_lshl_b64 s[16:17], s[16:17], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s0, v1
	s_add_u32 s6, s6, s16
	s_addc_u32 s7, s7, s17
	s_mov_b32 s16, 0
.LBB35_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v9, v1, s11
	v_mad_u64_u32 v[7:8], null, v1, s10, 0
	s_mov_b32 s17, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_lt_f32_e32 v6, v1
	s_cbranch_execz .LBB35_6
; %bb.5:                                ;   in Loop: Header=BB35_4 Depth=1
	v_mov_b32_e32 v6, v1
	ds_store_b32 v5, v1
.LBB35_6:                               ; %_ZN3MaxclIfEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB35_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s0, v3
	s_or_b32 s16, vcc_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB35_4
.LBB35_7:                               ; %Flow25
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_gt_u64_e64 s1, s[4:5], 1
	v_cmp_eq_u32_e64 s0, 0, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 s4, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s4
	s_cbranch_execz .LBB35_10
; %bb.8:
	v_mov_b32_e32 v2, 0
	ds_load_2addr_b32 v[0:1], v2 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_nlt_f32_e32 vcc_lo, v0, v1
	s_cbranch_vccnz .LBB35_10
; %bb.9:
	ds_store_b32 v2, v1
.LBB35_10:                              ; %_ZN3MaxclIfEEvRT_S1_.exit52.i
	s_or_b32 exec_lo, exec_lo, s1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB35_12
; %bb.11:
	s_load_b32 s0, s[2:3], 0x4
	v_mov_b32_e32 v0, 0
	s_mov_b32 s1, 0
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s13
	s_lshl_b64 s[0:1], s[0:1], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b32 v0, v1, s[0:1]
.LBB35_12:                              ; %_Z11cuda_reduceILj2Ef3MaxEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_maximum_2_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end35:
	.size	cuda_maximum_2_float, .Lfunc_end35-cuda_maximum_2_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 580
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_minimum_512_double ; -- Begin function cuda_minimum_512_double
	.globl	cuda_minimum_512_double
	.p2align	8
	.type	cuda_minimum_512_double,@function
cuda_minimum_512_double:                ; @cuda_minimum_512_double
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 9, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 9
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB36_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshl_add_u32 v5, v0, 3, 0
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v5, v[3:4]
.LBB36_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB36_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v7, v0, 3, 0
	s_lshl_b64 s[2:3], s[2:3], 3
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b64 v[5:6], v7
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB36_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v10, v1, s11
	v_mad_u64_u32 v[8:9], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v9, v10, v2
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_gt_f64_e32 v[5:6], v[1:2]
	s_cbranch_execz .LBB36_6
; %bb.5:                                ;   in Loop: Header=BB36_4 Depth=1
	v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
	ds_store_b64 v7, v[1:2]
.LBB36_6:                               ; %_ZN3MinclIdEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB36_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB36_4
.LBB36_7:                               ; %Flow42
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x100, v0
	s_cbranch_execz .LBB36_11
; %bb.8:
	v_or_b32_e32 v1, 0x100, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB36_11
; %bb.9:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB36_11
; %bb.10:
	ds_store_b64 v3, v[1:2]
.LBB36_11:                              ; %_ZN3MinclIdEEvRT_S1_.exit116.i
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB36_15
; %bb.12:
	v_or_b32_e32 v1, 0x80, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB36_15
; %bb.13:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB36_15
; %bb.14:
	ds_store_b64 v3, v[1:2]
.LBB36_15:                              ; %_ZN3MinclIdEEvRT_S1_.exit117.i
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB36_19
; %bb.16:
	v_or_b32_e32 v1, 64, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB36_19
; %bb.17:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB36_19
; %bb.18:
	ds_store_b64 v3, v[1:2]
.LBB36_19:                              ; %_ZN3MinclIdEEvRT_S1_.exit118.i
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB36_42
; %bb.20:
	v_or_b32_e32 v1, 32, v0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB36_23
; %bb.21:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB36_23
; %bb.22:
	ds_store_b64 v3, v[1:2]
.LBB36_23:                              ; %_ZN3MinclIdEEvRT_S1_.exit119.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB36_27
; %bb.24:
	v_or_b32_e32 v1, 16, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB36_27
; %bb.25:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB36_27
; %bb.26:
	ds_store_b64 v3, v[1:2]
.LBB36_27:                              ; %_ZN3MinclIdEEvRT_S1_.exit120.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB36_31
; %bb.28:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB36_31
; %bb.29:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB36_31
; %bb.30:
	ds_store_b64 v3, v[1:2]
.LBB36_31:                              ; %_ZN3MinclIdEEvRT_S1_.exit121.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB36_35
; %bb.32:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB36_35
; %bb.33:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB36_35
; %bb.34:
	ds_store_b64 v3, v[1:2]
.LBB36_35:                              ; %_ZN3MinclIdEEvRT_S1_.exit122.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB36_39
; %bb.36:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB36_39
; %bb.37:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB36_39
; %bb.38:
	ds_store_b64 v3, v[1:2]
.LBB36_39:                              ; %_ZN3MinclIdEEvRT_S1_.exit123.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB36_42
; %bb.40:
	v_mov_b32_e32 v5, 0
	ds_load_2addr_b64 v[1:4], v5 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f64_e32 vcc_lo, v[1:2], v[3:4]
	s_cbranch_vccnz .LBB36_42
; %bb.41:
	ds_store_b64 v5, v[3:4]
.LBB36_42:                              ; %Flow34
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB36_44
; %bb.43:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v2, 0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b64 v2, v[0:1], s[0:1]
.LBB36_44:                              ; %_Z11cuda_reduceILj512Ed3MinEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_minimum_512_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end36:
	.size	cuda_minimum_512_double, .Lfunc_end36-cuda_minimum_512_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1460
; NumSgprs: 22
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_minimum_256_double ; -- Begin function cuda_minimum_256_double
	.globl	cuda_minimum_256_double
	.p2align	8
	.type	cuda_minimum_256_double,@function
cuda_minimum_256_double:                ; @cuda_minimum_256_double
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 8, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 8
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB37_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshl_add_u32 v5, v0, 3, 0
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v5, v[3:4]
.LBB37_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB37_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v7, v0, 3, 0
	s_lshl_b64 s[2:3], s[2:3], 3
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b64 v[5:6], v7
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB37_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v10, v1, s11
	v_mad_u64_u32 v[8:9], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v9, v10, v2
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_gt_f64_e32 v[5:6], v[1:2]
	s_cbranch_execz .LBB37_6
; %bb.5:                                ;   in Loop: Header=BB37_4 Depth=1
	v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
	ds_store_b64 v7, v[1:2]
.LBB37_6:                               ; %_ZN3MinclIdEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB37_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB37_4
.LBB37_7:                               ; %Flow40
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB37_11
; %bb.8:
	v_or_b32_e32 v1, 0x80, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB37_11
; %bb.9:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB37_11
; %bb.10:
	ds_store_b64 v3, v[1:2]
.LBB37_11:                              ; %_ZN3MinclIdEEvRT_S1_.exit108.i
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB37_15
; %bb.12:
	v_or_b32_e32 v1, 64, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB37_15
; %bb.13:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB37_15
; %bb.14:
	ds_store_b64 v3, v[1:2]
.LBB37_15:                              ; %_ZN3MinclIdEEvRT_S1_.exit109.i
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB37_38
; %bb.16:
	v_or_b32_e32 v1, 32, v0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB37_19
; %bb.17:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB37_19
; %bb.18:
	ds_store_b64 v3, v[1:2]
.LBB37_19:                              ; %_ZN3MinclIdEEvRT_S1_.exit110.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB37_23
; %bb.20:
	v_or_b32_e32 v1, 16, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB37_23
; %bb.21:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB37_23
; %bb.22:
	ds_store_b64 v3, v[1:2]
.LBB37_23:                              ; %_ZN3MinclIdEEvRT_S1_.exit111.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB37_27
; %bb.24:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB37_27
; %bb.25:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB37_27
; %bb.26:
	ds_store_b64 v3, v[1:2]
.LBB37_27:                              ; %_ZN3MinclIdEEvRT_S1_.exit112.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB37_31
; %bb.28:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB37_31
; %bb.29:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB37_31
; %bb.30:
	ds_store_b64 v3, v[1:2]
.LBB37_31:                              ; %_ZN3MinclIdEEvRT_S1_.exit113.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB37_35
; %bb.32:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB37_35
; %bb.33:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB37_35
; %bb.34:
	ds_store_b64 v3, v[1:2]
.LBB37_35:                              ; %_ZN3MinclIdEEvRT_S1_.exit114.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB37_38
; %bb.36:
	v_mov_b32_e32 v5, 0
	ds_load_2addr_b64 v[1:4], v5 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f64_e32 vcc_lo, v[1:2], v[3:4]
	s_cbranch_vccnz .LBB37_38
; %bb.37:
	ds_store_b64 v5, v[3:4]
.LBB37_38:                              ; %Flow34
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB37_40
; %bb.39:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v2, 0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b64 v2, v[0:1], s[0:1]
.LBB37_40:                              ; %_Z11cuda_reduceILj256Ed3MinEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_minimum_256_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end37:
	.size	cuda_minimum_256_double, .Lfunc_end37-cuda_minimum_256_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1336
; NumSgprs: 22
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_minimum_128_double ; -- Begin function cuda_minimum_128_double
	.globl	cuda_minimum_128_double
	.p2align	8
	.type	cuda_minimum_128_double,@function
cuda_minimum_128_double:                ; @cuda_minimum_128_double
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 7, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 7
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB38_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshl_add_u32 v5, v0, 3, 0
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v5, v[3:4]
.LBB38_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB38_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v7, v0, 3, 0
	s_lshl_b64 s[2:3], s[2:3], 3
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b64 v[5:6], v7
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB38_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v10, v1, s11
	v_mad_u64_u32 v[8:9], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v9, v10, v2
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_gt_f64_e32 v[5:6], v[1:2]
	s_cbranch_execz .LBB38_6
; %bb.5:                                ;   in Loop: Header=BB38_4 Depth=1
	v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
	ds_store_b64 v7, v[1:2]
.LBB38_6:                               ; %_ZN3MinclIdEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB38_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB38_4
.LBB38_7:                               ; %Flow38
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB38_11
; %bb.8:
	v_or_b32_e32 v1, 64, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB38_11
; %bb.9:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB38_11
; %bb.10:
	ds_store_b64 v3, v[1:2]
.LBB38_11:                              ; %_ZN3MinclIdEEvRT_S1_.exit100.i
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB38_34
; %bb.12:
	v_or_b32_e32 v1, 32, v0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB38_15
; %bb.13:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB38_15
; %bb.14:
	ds_store_b64 v3, v[1:2]
.LBB38_15:                              ; %_ZN3MinclIdEEvRT_S1_.exit101.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB38_19
; %bb.16:
	v_or_b32_e32 v1, 16, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB38_19
; %bb.17:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB38_19
; %bb.18:
	ds_store_b64 v3, v[1:2]
.LBB38_19:                              ; %_ZN3MinclIdEEvRT_S1_.exit102.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB38_23
; %bb.20:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB38_23
; %bb.21:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB38_23
; %bb.22:
	ds_store_b64 v3, v[1:2]
.LBB38_23:                              ; %_ZN3MinclIdEEvRT_S1_.exit103.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB38_27
; %bb.24:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB38_27
; %bb.25:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB38_27
; %bb.26:
	ds_store_b64 v3, v[1:2]
.LBB38_27:                              ; %_ZN3MinclIdEEvRT_S1_.exit104.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB38_31
; %bb.28:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB38_31
; %bb.29:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB38_31
; %bb.30:
	ds_store_b64 v3, v[1:2]
.LBB38_31:                              ; %_ZN3MinclIdEEvRT_S1_.exit105.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB38_34
; %bb.32:
	v_mov_b32_e32 v5, 0
	ds_load_2addr_b64 v[1:4], v5 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f64_e32 vcc_lo, v[1:2], v[3:4]
	s_cbranch_vccnz .LBB38_34
; %bb.33:
	ds_store_b64 v5, v[3:4]
.LBB38_34:                              ; %Flow34
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB38_36
; %bb.35:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v2, 0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b64 v2, v[0:1], s[0:1]
.LBB38_36:                              ; %_Z11cuda_reduceILj128Ed3MinEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_minimum_128_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end38:
	.size	cuda_minimum_128_double, .Lfunc_end38-cuda_minimum_128_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1212
; NumSgprs: 22
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_minimum_64_double  ; -- Begin function cuda_minimum_64_double
	.globl	cuda_minimum_64_double
	.p2align	8
	.type	cuda_minimum_64_double,@function
cuda_minimum_64_double:                 ; @cuda_minimum_64_double
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 6, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 6
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB39_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshl_add_u32 v5, v0, 3, 0
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v5, v[3:4]
.LBB39_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB39_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v7, v0, 3, 0
	s_lshl_b64 s[2:3], s[2:3], 3
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b64 v[5:6], v7
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB39_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v10, v1, s11
	v_mad_u64_u32 v[8:9], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v9, v10, v2
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_gt_f64_e32 v[5:6], v[1:2]
	s_cbranch_execz .LBB39_6
; %bb.5:                                ;   in Loop: Header=BB39_4 Depth=1
	v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
	ds_store_b64 v7, v[1:2]
.LBB39_6:                               ; %_ZN3MinclIdEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB39_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB39_4
.LBB39_7:                               ; %Flow36
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB39_30
; %bb.8:
	v_or_b32_e32 v1, 32, v0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB39_11
; %bb.9:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB39_11
; %bb.10:
	ds_store_b64 v3, v[1:2]
.LBB39_11:                              ; %_ZN3MinclIdEEvRT_S1_.exit91.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB39_15
; %bb.12:
	v_or_b32_e32 v1, 16, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB39_15
; %bb.13:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB39_15
; %bb.14:
	ds_store_b64 v3, v[1:2]
.LBB39_15:                              ; %_ZN3MinclIdEEvRT_S1_.exit92.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB39_19
; %bb.16:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB39_19
; %bb.17:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB39_19
; %bb.18:
	ds_store_b64 v3, v[1:2]
.LBB39_19:                              ; %_ZN3MinclIdEEvRT_S1_.exit93.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB39_23
; %bb.20:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB39_23
; %bb.21:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB39_23
; %bb.22:
	ds_store_b64 v3, v[1:2]
.LBB39_23:                              ; %_ZN3MinclIdEEvRT_S1_.exit94.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB39_27
; %bb.24:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB39_27
; %bb.25:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB39_27
; %bb.26:
	ds_store_b64 v3, v[1:2]
.LBB39_27:                              ; %_ZN3MinclIdEEvRT_S1_.exit95.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB39_30
; %bb.28:
	v_mov_b32_e32 v5, 0
	ds_load_2addr_b64 v[1:4], v5 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f64_e32 vcc_lo, v[1:2], v[3:4]
	s_cbranch_vccnz .LBB39_30
; %bb.29:
	ds_store_b64 v5, v[3:4]
.LBB39_30:                              ; %Flow34
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB39_32
; %bb.31:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v2, 0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b64 v2, v[0:1], s[0:1]
.LBB39_32:                              ; %_Z11cuda_reduceILj64Ed3MinEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_minimum_64_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end39:
	.size	cuda_minimum_64_double, .Lfunc_end39-cuda_minimum_64_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1096
; NumSgprs: 22
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_minimum_32_double  ; -- Begin function cuda_minimum_32_double
	.globl	cuda_minimum_32_double
	.p2align	8
	.type	cuda_minimum_32_double,@function
cuda_minimum_32_double:                 ; @cuda_minimum_32_double
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 5, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 5
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB40_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshl_add_u32 v5, v0, 3, 0
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v5, v[3:4]
.LBB40_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB40_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v7, v0, 3, 0
	s_lshl_b64 s[2:3], s[2:3], 3
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b64 v[5:6], v7
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB40_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v10, v1, s11
	v_mad_u64_u32 v[8:9], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v9, v10, v2
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_gt_f64_e32 v[5:6], v[1:2]
	s_cbranch_execz .LBB40_6
; %bb.5:                                ;   in Loop: Header=BB40_4 Depth=1
	v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
	ds_store_b64 v7, v[1:2]
.LBB40_6:                               ; %_ZN3MinclIdEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB40_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB40_4
.LBB40_7:                               ; %Flow35
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB40_27
; %bb.8:
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB40_12
; %bb.9:
	v_or_b32_e32 v1, 16, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB40_12
; %bb.10:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB40_12
; %bb.11:
	ds_store_b64 v3, v[1:2]
.LBB40_12:                              ; %_ZN3MinclIdEEvRT_S1_.exit83.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB40_16
; %bb.13:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB40_16
; %bb.14:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB40_16
; %bb.15:
	ds_store_b64 v3, v[1:2]
.LBB40_16:                              ; %_ZN3MinclIdEEvRT_S1_.exit84.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB40_20
; %bb.17:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB40_20
; %bb.18:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB40_20
; %bb.19:
	ds_store_b64 v3, v[1:2]
.LBB40_20:                              ; %_ZN3MinclIdEEvRT_S1_.exit85.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB40_24
; %bb.21:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB40_24
; %bb.22:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB40_24
; %bb.23:
	ds_store_b64 v3, v[1:2]
.LBB40_24:                              ; %_ZN3MinclIdEEvRT_S1_.exit86.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB40_27
; %bb.25:
	v_mov_b32_e32 v5, 0
	ds_load_2addr_b64 v[1:4], v5 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f64_e32 vcc_lo, v[1:2], v[3:4]
	s_cbranch_vccnz .LBB40_27
; %bb.26:
	ds_store_b64 v5, v[3:4]
.LBB40_27:                              ; %Flow33
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB40_29
; %bb.28:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v2, 0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b64 v2, v[0:1], s[0:1]
.LBB40_29:                              ; %_Z11cuda_reduceILj32Ed3MinEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_minimum_32_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end40:
	.size	cuda_minimum_32_double, .Lfunc_end40-cuda_minimum_32_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1004
; NumSgprs: 22
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_minimum_16_double  ; -- Begin function cuda_minimum_16_double
	.globl	cuda_minimum_16_double
	.p2align	8
	.type	cuda_minimum_16_double,@function
cuda_minimum_16_double:                 ; @cuda_minimum_16_double
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 4, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 4
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB41_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshl_add_u32 v5, v0, 3, 0
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v5, v[3:4]
.LBB41_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB41_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v7, v0, 3, 0
	s_lshl_b64 s[2:3], s[2:3], 3
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b64 v[5:6], v7
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB41_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v10, v1, s11
	v_mad_u64_u32 v[8:9], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v9, v10, v2
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_gt_f64_e32 v[5:6], v[1:2]
	s_cbranch_execz .LBB41_6
; %bb.5:                                ;   in Loop: Header=BB41_4 Depth=1
	v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
	ds_store_b64 v7, v[1:2]
.LBB41_6:                               ; %_ZN3MinclIdEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB41_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB41_4
.LBB41_7:                               ; %Flow33
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB41_23
; %bb.8:
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB41_12
; %bb.9:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB41_12
; %bb.10:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB41_12
; %bb.11:
	ds_store_b64 v3, v[1:2]
.LBB41_12:                              ; %_ZN3MinclIdEEvRT_S1_.exit75.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB41_16
; %bb.13:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB41_16
; %bb.14:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB41_16
; %bb.15:
	ds_store_b64 v3, v[1:2]
.LBB41_16:                              ; %_ZN3MinclIdEEvRT_S1_.exit76.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB41_20
; %bb.17:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB41_20
; %bb.18:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB41_20
; %bb.19:
	ds_store_b64 v3, v[1:2]
.LBB41_20:                              ; %_ZN3MinclIdEEvRT_S1_.exit77.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB41_23
; %bb.21:
	v_mov_b32_e32 v5, 0
	ds_load_2addr_b64 v[1:4], v5 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f64_e32 vcc_lo, v[1:2], v[3:4]
	s_cbranch_vccnz .LBB41_23
; %bb.22:
	ds_store_b64 v5, v[3:4]
.LBB41_23:                              ; %Flow31
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB41_25
; %bb.24:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v2, 0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b64 v2, v[0:1], s[0:1]
.LBB41_25:                              ; %_Z11cuda_reduceILj16Ed3MinEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_minimum_16_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end41:
	.size	cuda_minimum_16_double, .Lfunc_end41-cuda_minimum_16_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 904
; NumSgprs: 22
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_minimum_8_double   ; -- Begin function cuda_minimum_8_double
	.globl	cuda_minimum_8_double
	.p2align	8
	.type	cuda_minimum_8_double,@function
cuda_minimum_8_double:                  ; @cuda_minimum_8_double
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 3, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 3
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB42_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshl_add_u32 v5, v0, 3, 0
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v5, v[3:4]
.LBB42_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB42_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v7, v0, 3, 0
	s_lshl_b64 s[2:3], s[2:3], 3
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b64 v[5:6], v7
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB42_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v10, v1, s11
	v_mad_u64_u32 v[8:9], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v9, v10, v2
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_gt_f64_e32 v[5:6], v[1:2]
	s_cbranch_execz .LBB42_6
; %bb.5:                                ;   in Loop: Header=BB42_4 Depth=1
	v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
	ds_store_b64 v7, v[1:2]
.LBB42_6:                               ; %_ZN3MinclIdEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB42_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB42_4
.LBB42_7:                               ; %Flow31
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB42_19
; %bb.8:
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB42_12
; %bb.9:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB42_12
; %bb.10:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB42_12
; %bb.11:
	ds_store_b64 v3, v[1:2]
.LBB42_12:                              ; %_ZN3MinclIdEEvRT_S1_.exit67.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB42_16
; %bb.13:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB42_16
; %bb.14:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB42_16
; %bb.15:
	ds_store_b64 v3, v[1:2]
.LBB42_16:                              ; %_ZN3MinclIdEEvRT_S1_.exit68.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB42_19
; %bb.17:
	v_mov_b32_e32 v5, 0
	ds_load_2addr_b64 v[1:4], v5 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f64_e32 vcc_lo, v[1:2], v[3:4]
	s_cbranch_vccnz .LBB42_19
; %bb.18:
	ds_store_b64 v5, v[3:4]
.LBB42_19:                              ; %Flow29
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB42_21
; %bb.20:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v2, 0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b64 v2, v[0:1], s[0:1]
.LBB42_21:                              ; %_Z11cuda_reduceILj8Ed3MinEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_minimum_8_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end42:
	.size	cuda_minimum_8_double, .Lfunc_end42-cuda_minimum_8_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 804
; NumSgprs: 22
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_minimum_4_double   ; -- Begin function cuda_minimum_4_double
	.globl	cuda_minimum_4_double
	.p2align	8
	.type	cuda_minimum_4_double,@function
cuda_minimum_4_double:                  ; @cuda_minimum_4_double
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 2, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 2
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB43_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshl_add_u32 v5, v0, 3, 0
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v5, v[3:4]
.LBB43_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB43_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v7, v0, 3, 0
	s_lshl_b64 s[2:3], s[2:3], 3
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b64 v[5:6], v7
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB43_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v10, v1, s11
	v_mad_u64_u32 v[8:9], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v9, v10, v2
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_gt_f64_e32 v[5:6], v[1:2]
	s_cbranch_execz .LBB43_6
; %bb.5:                                ;   in Loop: Header=BB43_4 Depth=1
	v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
	ds_store_b64 v7, v[1:2]
.LBB43_6:                               ; %_ZN3MinclIdEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB43_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB43_4
.LBB43_7:                               ; %Flow29
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB43_15
; %bb.8:
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB43_12
; %bb.9:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB43_12
; %bb.10:
	v_lshl_add_u32 v1, v1, 3, 0
	v_lshl_add_u32 v3, v0, 3, 0
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB43_12
; %bb.11:
	ds_store_b64 v3, v[1:2]
.LBB43_12:                              ; %_ZN3MinclIdEEvRT_S1_.exit59.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB43_15
; %bb.13:
	v_mov_b32_e32 v5, 0
	ds_load_2addr_b64 v[1:4], v5 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f64_e32 vcc_lo, v[1:2], v[3:4]
	s_cbranch_vccnz .LBB43_15
; %bb.14:
	ds_store_b64 v5, v[3:4]
.LBB43_15:                              ; %Flow27
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB43_17
; %bb.16:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v2, 0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b64 v2, v[0:1], s[0:1]
.LBB43_17:                              ; %_Z11cuda_reduceILj4Ed3MinEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_minimum_4_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end43:
	.size	cuda_minimum_4_double, .Lfunc_end43-cuda_minimum_4_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 704
; NumSgprs: 22
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_minimum_2_double   ; -- Begin function cuda_minimum_2_double
	.globl	cuda_minimum_2_double
	.p2align	8
	.type	cuda_minimum_2_double,@function
cuda_minimum_2_double:                  ; @cuda_minimum_2_double
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 1, v0
	v_lshl_add_u32 v7, v0, 3, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s16, s18, s16
	s_addc_u32 s17, s19, s3
	s_add_u32 s2, s0, 48
	s_addc_u32 s3, s1, 0
	s_lshl_b32 s0, s12, 1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB44_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[16:17], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s0, v1
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v7, v[3:4]
.LBB44_2:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB44_7
; %bb.3:                                ; %.lr.ph.i
	ds_load_b64 v[5:6], v7
	s_lshl_b64 s[16:17], s[16:17], 3
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s0, v1
	s_add_u32 s6, s6, s16
	s_addc_u32 s7, s7, s17
	s_mov_b32 s16, 0
.LBB44_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v10, v1, s11
	v_mad_u64_u32 v[8:9], null, v1, s10, 0
	s_mov_b32 s17, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v9, v10, v2
	v_lshlrev_b64 v[1:2], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_gt_f64_e32 v[5:6], v[1:2]
	s_cbranch_execz .LBB44_6
; %bb.5:                                ;   in Loop: Header=BB44_4 Depth=1
	v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
	ds_store_b64 v7, v[1:2]
.LBB44_6:                               ; %_ZN3MinclIdEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB44_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s0, v3
	s_or_b32 s16, vcc_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB44_4
.LBB44_7:                               ; %Flow25
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_gt_u64_e64 s1, s[4:5], 1
	v_cmp_eq_u32_e64 s0, 0, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 s4, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s4
	s_cbranch_execz .LBB44_10
; %bb.8:
	v_mov_b32_e32 v4, 0
	ds_load_2addr_b64 v[0:3], v4 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f64_e32 vcc_lo, v[0:1], v[2:3]
	s_cbranch_vccnz .LBB44_10
; %bb.9:
	ds_store_b64 v4, v[2:3]
.LBB44_10:                              ; %_ZN3MinclIdEEvRT_S1_.exit52.i
	s_or_b32 exec_lo, exec_lo, s1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB44_12
; %bb.11:
	s_load_b32 s0, s[2:3], 0x4
	v_mov_b32_e32 v2, 0
	s_mov_b32 s1, 0
	ds_load_b64 v[0:1], v2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s13
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b64 v2, v[0:1], s[0:1]
.LBB44_12:                              ; %_Z11cuda_reduceILj2Ed3MinEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_minimum_2_double
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end44:
	.size	cuda_minimum_2_double, .Lfunc_end44-cuda_minimum_2_double
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 584
; NumSgprs: 22
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_minimum_512_float  ; -- Begin function cuda_minimum_512_float
	.globl	cuda_minimum_512_float
	.p2align	8
	.type	cuda_minimum_512_float,@function
cuda_minimum_512_float:                 ; @cuda_minimum_512_float
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 9, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 9
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB45_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	v_lshl_add_u32 v4, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3
.LBB45_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB45_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v5, v0, 2, 0
	s_lshl_b64 s[2:3], s[2:3], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b32 v6, v5
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB45_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v9, v1, s11
	v_mad_u64_u32 v[7:8], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_gt_f32_e32 v6, v1
	s_cbranch_execz .LBB45_6
; %bb.5:                                ;   in Loop: Header=BB45_4 Depth=1
	v_mov_b32_e32 v6, v1
	ds_store_b32 v5, v1
.LBB45_6:                               ; %_ZN3MinclIfEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB45_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB45_4
.LBB45_7:                               ; %Flow42
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x100, v0
	s_cbranch_execz .LBB45_11
; %bb.8:
	v_or_b32_e32 v1, 0x100, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB45_11
; %bb.9:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB45_11
; %bb.10:
	ds_store_b32 v1, v2
.LBB45_11:                              ; %_ZN3MinclIfEEvRT_S1_.exit116.i
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB45_15
; %bb.12:
	v_or_b32_e32 v1, 0x80, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB45_15
; %bb.13:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB45_15
; %bb.14:
	ds_store_b32 v1, v2
.LBB45_15:                              ; %_ZN3MinclIfEEvRT_S1_.exit117.i
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB45_19
; %bb.16:
	v_or_b32_e32 v1, 64, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB45_19
; %bb.17:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB45_19
; %bb.18:
	ds_store_b32 v1, v2
.LBB45_19:                              ; %_ZN3MinclIfEEvRT_S1_.exit118.i
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB45_42
; %bb.20:
	v_or_b32_e32 v1, 32, v0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB45_23
; %bb.21:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB45_23
; %bb.22:
	ds_store_b32 v1, v2
.LBB45_23:                              ; %_ZN3MinclIfEEvRT_S1_.exit119.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB45_27
; %bb.24:
	v_or_b32_e32 v1, 16, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB45_27
; %bb.25:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB45_27
; %bb.26:
	ds_store_b32 v1, v2
.LBB45_27:                              ; %_ZN3MinclIfEEvRT_S1_.exit120.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB45_31
; %bb.28:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB45_31
; %bb.29:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB45_31
; %bb.30:
	ds_store_b32 v1, v2
.LBB45_31:                              ; %_ZN3MinclIfEEvRT_S1_.exit121.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB45_35
; %bb.32:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB45_35
; %bb.33:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB45_35
; %bb.34:
	ds_store_b32 v1, v2
.LBB45_35:                              ; %_ZN3MinclIfEEvRT_S1_.exit122.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB45_39
; %bb.36:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB45_39
; %bb.37:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB45_39
; %bb.38:
	ds_store_b32 v1, v2
.LBB45_39:                              ; %_ZN3MinclIfEEvRT_S1_.exit123.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB45_42
; %bb.40:
	v_mov_b32_e32 v3, 0
	ds_load_2addr_b32 v[1:2], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f32_e32 vcc_lo, v1, v2
	s_cbranch_vccnz .LBB45_42
; %bb.41:
	ds_store_b32 v3, v2
.LBB45_42:                              ; %Flow34
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB45_44
; %bb.43:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v0, 0
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b32 v0, v1, s[0:1]
.LBB45_44:                              ; %_Z11cuda_reduceILj512Ef3MinEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_minimum_512_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end45:
	.size	cuda_minimum_512_float, .Lfunc_end45-cuda_minimum_512_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1456
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_minimum_256_float  ; -- Begin function cuda_minimum_256_float
	.globl	cuda_minimum_256_float
	.p2align	8
	.type	cuda_minimum_256_float,@function
cuda_minimum_256_float:                 ; @cuda_minimum_256_float
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 8, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 8
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB46_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	v_lshl_add_u32 v4, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3
.LBB46_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB46_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v5, v0, 2, 0
	s_lshl_b64 s[2:3], s[2:3], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b32 v6, v5
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB46_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v9, v1, s11
	v_mad_u64_u32 v[7:8], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_gt_f32_e32 v6, v1
	s_cbranch_execz .LBB46_6
; %bb.5:                                ;   in Loop: Header=BB46_4 Depth=1
	v_mov_b32_e32 v6, v1
	ds_store_b32 v5, v1
.LBB46_6:                               ; %_ZN3MinclIfEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB46_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB46_4
.LBB46_7:                               ; %Flow40
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB46_11
; %bb.8:
	v_or_b32_e32 v1, 0x80, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB46_11
; %bb.9:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB46_11
; %bb.10:
	ds_store_b32 v1, v2
.LBB46_11:                              ; %_ZN3MinclIfEEvRT_S1_.exit108.i
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB46_15
; %bb.12:
	v_or_b32_e32 v1, 64, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB46_15
; %bb.13:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB46_15
; %bb.14:
	ds_store_b32 v1, v2
.LBB46_15:                              ; %_ZN3MinclIfEEvRT_S1_.exit109.i
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB46_38
; %bb.16:
	v_or_b32_e32 v1, 32, v0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB46_19
; %bb.17:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB46_19
; %bb.18:
	ds_store_b32 v1, v2
.LBB46_19:                              ; %_ZN3MinclIfEEvRT_S1_.exit110.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB46_23
; %bb.20:
	v_or_b32_e32 v1, 16, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB46_23
; %bb.21:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB46_23
; %bb.22:
	ds_store_b32 v1, v2
.LBB46_23:                              ; %_ZN3MinclIfEEvRT_S1_.exit111.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB46_27
; %bb.24:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB46_27
; %bb.25:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB46_27
; %bb.26:
	ds_store_b32 v1, v2
.LBB46_27:                              ; %_ZN3MinclIfEEvRT_S1_.exit112.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB46_31
; %bb.28:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB46_31
; %bb.29:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB46_31
; %bb.30:
	ds_store_b32 v1, v2
.LBB46_31:                              ; %_ZN3MinclIfEEvRT_S1_.exit113.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB46_35
; %bb.32:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB46_35
; %bb.33:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB46_35
; %bb.34:
	ds_store_b32 v1, v2
.LBB46_35:                              ; %_ZN3MinclIfEEvRT_S1_.exit114.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB46_38
; %bb.36:
	v_mov_b32_e32 v3, 0
	ds_load_2addr_b32 v[1:2], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f32_e32 vcc_lo, v1, v2
	s_cbranch_vccnz .LBB46_38
; %bb.37:
	ds_store_b32 v3, v2
.LBB46_38:                              ; %Flow34
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB46_40
; %bb.39:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v0, 0
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b32 v0, v1, s[0:1]
.LBB46_40:                              ; %_Z11cuda_reduceILj256Ef3MinEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_minimum_256_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end46:
	.size	cuda_minimum_256_float, .Lfunc_end46-cuda_minimum_256_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1332
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_minimum_128_float  ; -- Begin function cuda_minimum_128_float
	.globl	cuda_minimum_128_float
	.p2align	8
	.type	cuda_minimum_128_float,@function
cuda_minimum_128_float:                 ; @cuda_minimum_128_float
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 7, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 7
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB47_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	v_lshl_add_u32 v4, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3
.LBB47_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB47_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v5, v0, 2, 0
	s_lshl_b64 s[2:3], s[2:3], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b32 v6, v5
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB47_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v9, v1, s11
	v_mad_u64_u32 v[7:8], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_gt_f32_e32 v6, v1
	s_cbranch_execz .LBB47_6
; %bb.5:                                ;   in Loop: Header=BB47_4 Depth=1
	v_mov_b32_e32 v6, v1
	ds_store_b32 v5, v1
.LBB47_6:                               ; %_ZN3MinclIfEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB47_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB47_4
.LBB47_7:                               ; %Flow38
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB47_11
; %bb.8:
	v_or_b32_e32 v1, 64, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB47_11
; %bb.9:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB47_11
; %bb.10:
	ds_store_b32 v1, v2
.LBB47_11:                              ; %_ZN3MinclIfEEvRT_S1_.exit100.i
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB47_34
; %bb.12:
	v_or_b32_e32 v1, 32, v0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB47_15
; %bb.13:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB47_15
; %bb.14:
	ds_store_b32 v1, v2
.LBB47_15:                              ; %_ZN3MinclIfEEvRT_S1_.exit101.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB47_19
; %bb.16:
	v_or_b32_e32 v1, 16, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB47_19
; %bb.17:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB47_19
; %bb.18:
	ds_store_b32 v1, v2
.LBB47_19:                              ; %_ZN3MinclIfEEvRT_S1_.exit102.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB47_23
; %bb.20:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB47_23
; %bb.21:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB47_23
; %bb.22:
	ds_store_b32 v1, v2
.LBB47_23:                              ; %_ZN3MinclIfEEvRT_S1_.exit103.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB47_27
; %bb.24:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB47_27
; %bb.25:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB47_27
; %bb.26:
	ds_store_b32 v1, v2
.LBB47_27:                              ; %_ZN3MinclIfEEvRT_S1_.exit104.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB47_31
; %bb.28:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB47_31
; %bb.29:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB47_31
; %bb.30:
	ds_store_b32 v1, v2
.LBB47_31:                              ; %_ZN3MinclIfEEvRT_S1_.exit105.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB47_34
; %bb.32:
	v_mov_b32_e32 v3, 0
	ds_load_2addr_b32 v[1:2], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f32_e32 vcc_lo, v1, v2
	s_cbranch_vccnz .LBB47_34
; %bb.33:
	ds_store_b32 v3, v2
.LBB47_34:                              ; %Flow34
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB47_36
; %bb.35:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v0, 0
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b32 v0, v1, s[0:1]
.LBB47_36:                              ; %_Z11cuda_reduceILj128Ef3MinEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_minimum_128_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end47:
	.size	cuda_minimum_128_float, .Lfunc_end47-cuda_minimum_128_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1208
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_minimum_64_float   ; -- Begin function cuda_minimum_64_float
	.globl	cuda_minimum_64_float
	.p2align	8
	.type	cuda_minimum_64_float,@function
cuda_minimum_64_float:                  ; @cuda_minimum_64_float
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 6, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 6
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB48_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	v_lshl_add_u32 v4, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3
.LBB48_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB48_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v5, v0, 2, 0
	s_lshl_b64 s[2:3], s[2:3], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b32 v6, v5
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB48_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v9, v1, s11
	v_mad_u64_u32 v[7:8], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_gt_f32_e32 v6, v1
	s_cbranch_execz .LBB48_6
; %bb.5:                                ;   in Loop: Header=BB48_4 Depth=1
	v_mov_b32_e32 v6, v1
	ds_store_b32 v5, v1
.LBB48_6:                               ; %_ZN3MinclIfEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB48_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB48_4
.LBB48_7:                               ; %Flow36
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB48_30
; %bb.8:
	v_or_b32_e32 v1, 32, v0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB48_11
; %bb.9:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB48_11
; %bb.10:
	ds_store_b32 v1, v2
.LBB48_11:                              ; %_ZN3MinclIfEEvRT_S1_.exit91.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB48_15
; %bb.12:
	v_or_b32_e32 v1, 16, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB48_15
; %bb.13:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB48_15
; %bb.14:
	ds_store_b32 v1, v2
.LBB48_15:                              ; %_ZN3MinclIfEEvRT_S1_.exit92.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB48_19
; %bb.16:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB48_19
; %bb.17:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB48_19
; %bb.18:
	ds_store_b32 v1, v2
.LBB48_19:                              ; %_ZN3MinclIfEEvRT_S1_.exit93.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB48_23
; %bb.20:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB48_23
; %bb.21:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB48_23
; %bb.22:
	ds_store_b32 v1, v2
.LBB48_23:                              ; %_ZN3MinclIfEEvRT_S1_.exit94.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB48_27
; %bb.24:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB48_27
; %bb.25:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB48_27
; %bb.26:
	ds_store_b32 v1, v2
.LBB48_27:                              ; %_ZN3MinclIfEEvRT_S1_.exit95.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB48_30
; %bb.28:
	v_mov_b32_e32 v3, 0
	ds_load_2addr_b32 v[1:2], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f32_e32 vcc_lo, v1, v2
	s_cbranch_vccnz .LBB48_30
; %bb.29:
	ds_store_b32 v3, v2
.LBB48_30:                              ; %Flow34
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB48_32
; %bb.31:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v0, 0
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b32 v0, v1, s[0:1]
.LBB48_32:                              ; %_Z11cuda_reduceILj64Ef3MinEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_minimum_64_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end48:
	.size	cuda_minimum_64_float, .Lfunc_end48-cuda_minimum_64_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1092
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_minimum_32_float   ; -- Begin function cuda_minimum_32_float
	.globl	cuda_minimum_32_float
	.p2align	8
	.type	cuda_minimum_32_float,@function
cuda_minimum_32_float:                  ; @cuda_minimum_32_float
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 5, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 5
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB49_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	v_lshl_add_u32 v4, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3
.LBB49_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB49_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v5, v0, 2, 0
	s_lshl_b64 s[2:3], s[2:3], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b32 v6, v5
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB49_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v9, v1, s11
	v_mad_u64_u32 v[7:8], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_gt_f32_e32 v6, v1
	s_cbranch_execz .LBB49_6
; %bb.5:                                ;   in Loop: Header=BB49_4 Depth=1
	v_mov_b32_e32 v6, v1
	ds_store_b32 v5, v1
.LBB49_6:                               ; %_ZN3MinclIfEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB49_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB49_4
.LBB49_7:                               ; %Flow35
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB49_27
; %bb.8:
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB49_12
; %bb.9:
	v_or_b32_e32 v1, 16, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB49_12
; %bb.10:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB49_12
; %bb.11:
	ds_store_b32 v1, v2
.LBB49_12:                              ; %_ZN3MinclIfEEvRT_S1_.exit83.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB49_16
; %bb.13:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB49_16
; %bb.14:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB49_16
; %bb.15:
	ds_store_b32 v1, v2
.LBB49_16:                              ; %_ZN3MinclIfEEvRT_S1_.exit84.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB49_20
; %bb.17:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB49_20
; %bb.18:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB49_20
; %bb.19:
	ds_store_b32 v1, v2
.LBB49_20:                              ; %_ZN3MinclIfEEvRT_S1_.exit85.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB49_24
; %bb.21:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB49_24
; %bb.22:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB49_24
; %bb.23:
	ds_store_b32 v1, v2
.LBB49_24:                              ; %_ZN3MinclIfEEvRT_S1_.exit86.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB49_27
; %bb.25:
	v_mov_b32_e32 v3, 0
	ds_load_2addr_b32 v[1:2], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f32_e32 vcc_lo, v1, v2
	s_cbranch_vccnz .LBB49_27
; %bb.26:
	ds_store_b32 v3, v2
.LBB49_27:                              ; %Flow33
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB49_29
; %bb.28:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v0, 0
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b32 v0, v1, s[0:1]
.LBB49_29:                              ; %_Z11cuda_reduceILj32Ef3MinEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_minimum_32_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end49:
	.size	cuda_minimum_32_float, .Lfunc_end49-cuda_minimum_32_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1000
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_minimum_16_float   ; -- Begin function cuda_minimum_16_float
	.globl	cuda_minimum_16_float
	.p2align	8
	.type	cuda_minimum_16_float,@function
cuda_minimum_16_float:                  ; @cuda_minimum_16_float
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 4, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 4
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB50_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	v_lshl_add_u32 v4, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3
.LBB50_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB50_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v5, v0, 2, 0
	s_lshl_b64 s[2:3], s[2:3], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b32 v6, v5
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB50_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v9, v1, s11
	v_mad_u64_u32 v[7:8], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_gt_f32_e32 v6, v1
	s_cbranch_execz .LBB50_6
; %bb.5:                                ;   in Loop: Header=BB50_4 Depth=1
	v_mov_b32_e32 v6, v1
	ds_store_b32 v5, v1
.LBB50_6:                               ; %_ZN3MinclIfEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB50_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB50_4
.LBB50_7:                               ; %Flow33
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB50_23
; %bb.8:
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB50_12
; %bb.9:
	v_or_b32_e32 v1, 8, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB50_12
; %bb.10:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB50_12
; %bb.11:
	ds_store_b32 v1, v2
.LBB50_12:                              ; %_ZN3MinclIfEEvRT_S1_.exit75.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB50_16
; %bb.13:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB50_16
; %bb.14:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB50_16
; %bb.15:
	ds_store_b32 v1, v2
.LBB50_16:                              ; %_ZN3MinclIfEEvRT_S1_.exit76.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB50_20
; %bb.17:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB50_20
; %bb.18:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB50_20
; %bb.19:
	ds_store_b32 v1, v2
.LBB50_20:                              ; %_ZN3MinclIfEEvRT_S1_.exit77.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB50_23
; %bb.21:
	v_mov_b32_e32 v3, 0
	ds_load_2addr_b32 v[1:2], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f32_e32 vcc_lo, v1, v2
	s_cbranch_vccnz .LBB50_23
; %bb.22:
	ds_store_b32 v3, v2
.LBB50_23:                              ; %Flow31
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB50_25
; %bb.24:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v0, 0
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b32 v0, v1, s[0:1]
.LBB50_25:                              ; %_Z11cuda_reduceILj16Ef3MinEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_minimum_16_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end50:
	.size	cuda_minimum_16_float, .Lfunc_end50-cuda_minimum_16_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 900
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_minimum_8_float    ; -- Begin function cuda_minimum_8_float
	.globl	cuda_minimum_8_float
	.p2align	8
	.type	cuda_minimum_8_float,@function
cuda_minimum_8_float:                   ; @cuda_minimum_8_float
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 3, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 3
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB51_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	v_lshl_add_u32 v4, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3
.LBB51_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB51_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v5, v0, 2, 0
	s_lshl_b64 s[2:3], s[2:3], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b32 v6, v5
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB51_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v9, v1, s11
	v_mad_u64_u32 v[7:8], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_gt_f32_e32 v6, v1
	s_cbranch_execz .LBB51_6
; %bb.5:                                ;   in Loop: Header=BB51_4 Depth=1
	v_mov_b32_e32 v6, v1
	ds_store_b32 v5, v1
.LBB51_6:                               ; %_ZN3MinclIfEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB51_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB51_4
.LBB51_7:                               ; %Flow31
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB51_19
; %bb.8:
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB51_12
; %bb.9:
	v_or_b32_e32 v1, 4, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB51_12
; %bb.10:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB51_12
; %bb.11:
	ds_store_b32 v1, v2
.LBB51_12:                              ; %_ZN3MinclIfEEvRT_S1_.exit67.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB51_16
; %bb.13:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB51_16
; %bb.14:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB51_16
; %bb.15:
	ds_store_b32 v1, v2
.LBB51_16:                              ; %_ZN3MinclIfEEvRT_S1_.exit68.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB51_19
; %bb.17:
	v_mov_b32_e32 v3, 0
	ds_load_2addr_b32 v[1:2], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f32_e32 vcc_lo, v1, v2
	s_cbranch_vccnz .LBB51_19
; %bb.18:
	ds_store_b32 v3, v2
.LBB51_19:                              ; %Flow29
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB51_21
; %bb.20:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v0, 0
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b32 v0, v1, s[0:1]
.LBB51_21:                              ; %_Z11cuda_reduceILj8Ef3MinEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_minimum_8_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end51:
	.size	cuda_minimum_8_float, .Lfunc_end51-cuda_minimum_8_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 800
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_minimum_4_float    ; -- Begin function cuda_minimum_4_float
	.globl	cuda_minimum_4_float
	.p2align	8
	.type	cuda_minimum_4_float,@function
cuda_minimum_4_float:                   ; @cuda_minimum_4_float
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 2, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s2, s18, s16
	s_addc_u32 s3, s19, s3
	s_add_u32 s0, s0, 48
	s_addc_u32 s1, s1, 0
	s_lshl_b32 s16, s12, 2
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB52_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[5:6], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v5 :: v_dual_add_nc_u32 v1, s16, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	v_lshl_add_u32 v4, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3
.LBB52_2:
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s17, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB52_7
; %bb.3:                                ; %.lr.ph.i
	v_lshl_add_u32 v5, v0, 2, 0
	s_lshl_b64 s[2:3], s[2:3], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s16, v1
	s_add_u32 s2, s6, s2
	ds_load_b32 v6, v5
	s_addc_u32 s3, s7, s3
	s_mov_b32 s6, 0
.LBB52_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v9, v1, s11
	v_mad_u64_u32 v[7:8], null, v1, s10, 0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_gt_f32_e32 v6, v1
	s_cbranch_execz .LBB52_6
; %bb.5:                                ;   in Loop: Header=BB52_4 Depth=1
	v_mov_b32_e32 v6, v1
	ds_store_b32 v5, v1
.LBB52_6:                               ; %_ZN3MinclIfEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB52_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s16, v3
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB52_4
.LBB52_7:                               ; %Flow29
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB52_15
; %bb.8:
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB52_12
; %bb.9:
	v_or_b32_e32 v1, 2, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB52_12
; %bb.10:
	v_lshl_add_u32 v2, v1, 2, 0
	v_lshl_add_u32 v1, v0, 2, 0
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB52_12
; %bb.11:
	ds_store_b32 v1, v2
.LBB52_12:                              ; %_ZN3MinclIfEEvRT_S1_.exit59.i
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u64_e64 s3, s[4:5], 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB52_15
; %bb.13:
	v_mov_b32_e32 v3, 0
	ds_load_2addr_b32 v[1:2], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f32_e32 vcc_lo, v1, v2
	s_cbranch_vccnz .LBB52_15
; %bb.14:
	ds_store_b32 v3, v2
.LBB52_15:                              ; %Flow27
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB52_17
; %bb.16:
	s_load_b32 s0, s[0:1], 0x4
	v_mov_b32_e32 v0, 0
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s0, s13
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b32 v0, v1, s[0:1]
.LBB52_17:                              ; %_Z11cuda_reduceILj4Ef3MinEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_minimum_4_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end52:
	.size	cuda_minimum_4_float, .Lfunc_end52-cuda_minimum_4_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 700
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	cuda_minimum_2_float    ; -- Begin function cuda_minimum_2_float
	.globl	cuda_minimum_2_float
	.p2align	8
	.type	cuda_minimum_2_float,@function
cuda_minimum_2_float:                   ; @cuda_minimum_2_float
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v1, s13, 1, v0
	v_lshl_add_u32 v5, v0, 2, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s17
	s_mul_hi_u32 s3, s14, s16
	s_mul_i32 s17, s15, s19
	s_mul_hi_u32 s19, s15, s18
	s_mul_i32 s16, s14, s16
	s_mul_i32 s18, s15, s18
	s_add_i32 s3, s3, s2
	s_add_i32 s19, s19, s17
	s_add_u32 s16, s18, s16
	s_addc_u32 s17, s19, s3
	s_add_u32 s2, s0, 48
	s_addc_u32 s3, s1, 0
	s_lshl_b32 s0, s12, 1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB53_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v1, s10, 0
	s_lshl_b64 s[18:19], s[16:17], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s18, s18, s6
	s_addc_u32 s19, s19, s7
	v_mad_u64_u32 v[6:7], null, v1, s11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v6 :: v_dual_add_nc_u32 v1, s0, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v3
.LBB53_2:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB53_7
; %bb.3:                                ; %.lr.ph.i
	ds_load_b32 v6, v5
	s_lshl_b64 s[16:17], s[16:17], 2
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s0, v1
	s_add_u32 s6, s6, s16
	s_addc_u32 s7, s7, s17
	s_mov_b32 s16, 0
.LBB53_4:                               ; =>This Inner Loop Header: Depth=1
	v_mul_lo_u32 v2, v2, s10
	v_mul_lo_u32 v9, v1, s11
	v_mad_u64_u32 v[7:8], null, v1, s10, 0
	s_mov_b32 s17, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v2
	v_lshlrev_b64 v[1:2], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_gt_f32_e32 v6, v1
	s_cbranch_execz .LBB53_6
; %bb.5:                                ;   in Loop: Header=BB53_4 Depth=1
	v_mov_b32_e32 v6, v1
	ds_store_b32 v5, v1
.LBB53_6:                               ; %_ZN3MinclIfEEvRT_S1_.exit.i
                                        ;   in Loop: Header=BB53_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[3:4]
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v3, s0, v3
	s_or_b32 s16, vcc_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB53_4
.LBB53_7:                               ; %Flow25
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_gt_u64_e64 s1, s[4:5], 1
	v_cmp_eq_u32_e64 s0, 0, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 s4, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s4
	s_cbranch_execz .LBB53_10
; %bb.8:
	v_mov_b32_e32 v2, 0
	ds_load_2addr_b32 v[0:1], v2 offset1:1
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f32_e32 vcc_lo, v0, v1
	s_cbranch_vccnz .LBB53_10
; %bb.9:
	ds_store_b32 v2, v1
.LBB53_10:                              ; %_ZN3MinclIfEEvRT_S1_.exit52.i
	s_or_b32 exec_lo, exec_lo, s1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB53_12
; %bb.11:
	s_load_b32 s0, s[2:3], 0x4
	v_mov_b32_e32 v0, 0
	s_mov_b32 s1, 0
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s13
	s_lshl_b64 s[0:1], s[0:1], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	global_store_b32 v0, v1, s[0:1]
.LBB53_12:                              ; %_Z11cuda_reduceILj2Ef3MinEvT1_mPT0_S3_llld.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel cuda_minimum_2_float
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end53:
	.size	cuda_minimum_2_float, .Lfunc_end53-cuda_minimum_2_float
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 580
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         176
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_sum_512_double
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         cuda_sum_512_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         176
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_sum_256_double
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         cuda_sum_256_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         176
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_sum_128_double
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         cuda_sum_128_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         176
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_sum_64_double
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         cuda_sum_64_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         176
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_sum_32_double
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         cuda_sum_32_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         176
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_sum_16_double
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         cuda_sum_16_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         176
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_sum_8_double
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         cuda_sum_8_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         176
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_sum_4_double
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         cuda_sum_4_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         176
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_sum_2_double
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         cuda_sum_2_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         176
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_sum_512_float
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         cuda_sum_512_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         176
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_sum_256_float
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         cuda_sum_256_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         176
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_sum_128_float
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         cuda_sum_128_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         176
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_sum_64_float
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         cuda_sum_64_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         176
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_sum_32_float
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         cuda_sum_32_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         176
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_sum_16_float
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         cuda_sum_16_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         176
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_sum_8_float
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         cuda_sum_8_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         176
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_sum_4_float
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         cuda_sum_4_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         176
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_sum_2_float
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         cuda_sum_2_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_maximum_512_double
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_maximum_512_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_maximum_256_double
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_maximum_256_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_maximum_128_double
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_maximum_128_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_maximum_64_double
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_maximum_64_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_maximum_32_double
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_maximum_32_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_maximum_16_double
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_maximum_16_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_maximum_8_double
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_maximum_8_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_maximum_4_double
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_maximum_4_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_maximum_2_double
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_maximum_2_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_maximum_512_float
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_maximum_512_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_maximum_256_float
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_maximum_256_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_maximum_128_float
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_maximum_128_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_maximum_64_float
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_maximum_64_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_maximum_32_float
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_maximum_32_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_maximum_16_float
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_maximum_16_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_maximum_8_float
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_maximum_8_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_maximum_4_float
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_maximum_4_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_maximum_2_float
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_maximum_2_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_minimum_512_double
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_minimum_512_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_minimum_256_double
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_minimum_256_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_minimum_128_double
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_minimum_128_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_minimum_64_double
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_minimum_64_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_minimum_32_double
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_minimum_32_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_minimum_16_double
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_minimum_16_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_minimum_8_double
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_minimum_8_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_minimum_4_double
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_minimum_4_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_minimum_2_double
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_minimum_2_double.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_minimum_512_float
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_minimum_512_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_minimum_256_float
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_minimum_256_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_minimum_128_float
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_minimum_128_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_minimum_64_float
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_minimum_64_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_minimum_32_float
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_minimum_32_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_minimum_16_float
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_minimum_16_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_minimum_8_float
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_minimum_8_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_minimum_4_float
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_minimum_4_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           cuda_minimum_2_float
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         cuda_minimum_2_float.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
