#include <stdio.h>
#include <fstream>
#include <time.h>


// Generic utils

typedef float3 pixel;

void check_result(cudaError_t value) {
	cudaError_t status = value;
	if (status != cudaSuccess) {
		printf("Error %s at line %d in file %s\n",
			cudaGetErrorString(status), __LINE__, __FILE__);
		// exit(1);
	}
}

__device__ float3 operator+(const float3 &a, const float3 &b) {
	return make_float3(a.x + b.x,a.y + b.y,a.z + b.z);
}

__device__ float3 operator*(const float3 &a, const float &b) {
	return make_float3(a.x * b, a.y * b, a.z * b);
}

__device__ float length(const float3 &vec) {
	return sqrt(vec.x * vec.x + vec.y * vec.y + vec.z * vec.z);
}

__device__ float3 normalize(const float3 vec) {
	float inverted_len = 1.0f / length(vec);
	return vec * inverted_len;
}


// Raymarcher

typedef struct {
	float3 o;
	float3 d;
} ray;

__device__ ray get_ray(const float& u, const float& v) {
	ray r;
	r.o = make_float3(-5.0, 0.0, 0.0);
	r.d = normalize(make_float3(1.0, u, v));
	return r;
}

__device__ float mandelbulb_de(float3 pos) {
	// pos = fmod(fabs(pos), 4.0) - 2.0;
	float3 z = pos;
	float dr = 1.0;
	float r = 0.0;
	int Iterations = 4;
	float Bailout = 4.0;
	float Power = 16.0;
	for(int i = 0; i < Iterations; i++) {
		r = length(z);
		if (r > Bailout) break;

		// convert to polar coordinates
		float theta = acos(z.z / r);
		float phi = atan2(z.y, z.x);
		dr = powf(r, Power - 1.0) * Power * dr + 1.0;

		// scale and rotate the point
		float zr = pow(r, Power);
		theta = theta * Power;
		phi = phi * Power;

		// convert back to cartesian coordinates
		z = make_float3(sin(theta) * cos(phi),
				sin(phi) * sin(theta), cos(theta)) * zr;
		z = z + pos;
		//z += pos * cos(time * 2.0);
	}
	return 0.5 * log(r) * r / dr;
}

__device__ float march(ray r) {
	float total_dist = 0.0;
	int max_ray_steps = 64;
	float min_distance = 0.002;

	int steps;
	for (steps = 0; steps < max_ray_steps; ++steps) {
		float3 p = r.o + r.d * total_dist;
		float distance = mandelbulb_de(p);
		total_dist += distance;
		if (distance < min_distance) break;
	}
	return 1.0 - (float) steps / (float) max_ray_steps;
}


// Main kernel

__global__ void d_main(
	pixel* screen_buffer,
	const size_t width,
	const size_t height
) {
	size_t x = (blockIdx.x * blockDim.x) + threadIdx.x;
	size_t y = (blockIdx.y * blockDim.y) + threadIdx.y;
	
	if(x < width && y < height) {
		float min_w_h = (float) min(width, height);

		float ar = (float) width / (float) height;
		float u = (float) x / min_w_h - ar * 0.5f;
		float v = (float) y / min_w_h - 0.5f;

		ray r = get_ray(u, v);
		float c = march(r) * 255.0f;
		float3 color = make_float3(c, c, c);
	
		screen_buffer[y * width + x] = color;
	}
}

void write_image(
	char* file_name,
	pixel* screen_buff,
	size_t width,
	size_t height
) {
	FILE* image = fopen(file_name, "w");
	fprintf(image, "P3\n");
	fprintf(image, "%i %i\n", width, height);
	fprintf(image, "%i\n", 255);
	for (size_t y = 0; y < height; y++) {
		for (size_t x = 0; x < width; x++) {
			float3 pixel = screen_buff[y * width + x];
			fprintf(image, "%i %i %i\n", (int) pixel.x, (int) pixel.y, (int) pixel.z);
		}
	}
	fclose(image);
}

int main(int argc, char** argv) {
	// printf("Mandelbulb\n");

	if(argc < 7) {
		printf("Not enought params.\n");
		return 1;
	}
	
	char* file_name = argv[1];
	size_t width = atoi(argv[2]);
	size_t height = atoi(argv[3]);
	size_t num_pixels = width * height;

	size_t group_width = atoi(argv[4]);
	size_t group_height = atoi(argv[5]);

	bool test = false;

	if (*argv[6] == 't') {
		test = true;
	}

	// Setup buffers
	pixel* h_screen_buff;
	pixel* d_screen_buff;
	check_result(cudaMallocHost(&h_screen_buff, num_pixels * sizeof(pixel)));
	check_result(cudaMalloc(&d_screen_buff, num_pixels * sizeof(pixel)));

	dim3 block_dim(width / group_width, height / group_height);
	dim3 group_dim(group_width, group_height);

	// Execute on devicie
	clock_t t_start = clock();
	
	if(!test)
		printf("Starting kernel execution...\n");
	d_main<<<block_dim, group_dim>>>(d_screen_buff, width, height);
	if(!test)
		printf("Kernel execution ended.\n");
	
	if(!test)
		printf("Reading screan buffer from device...\n");
	check_result(cudaMemcpy(h_screen_buff, d_screen_buff, num_pixels * sizeof(pixel), cudaMemcpyDeviceToHost));
	if(!test)
		printf("Done.\n");

	printf("Time taken (ms): %i\n", (int) ((double) (clock() - t_start) / CLOCKS_PER_SEC * 1000.0f));	

	if(!test){
		printf("Writing to file...\n");
		write_image(file_name, h_screen_buff, width, height);
		printf("Done\n");
	}

	//for(size_t y = 0;y < height;y++) {
	//	for(size_t x = 0;x < width;x++) {
	//		printf("%i ", (int) h_screen_buff[y * width + x].x);
	//	}
	//	printf("\n");
	//}

	cudaFreeHost(h_screen_buff);
	cudaFree(d_screen_buff);

	return 0;
}


	.file	"tmpxft_0024bc8d_00000000-6_main.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3778:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3778:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/ichko/cuda-mandelbulb/master/main.cu"
.LC1:
	.string	"Error %s at line %d in file %s\n"
	.text
	.globl	_Z12check_result9cudaError
	.type	_Z12check_result9cudaError, @function
_Z12check_result9cudaError:
.LFB3766:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L2
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	cudaGetErrorString@PLT
	leaq	.LC0(%rip), %r8
	movl	$14, %ecx
	popq	%r9
	.cfi_def_cfa_offset 8
	movq	%rax, %rdx
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	jmp	__printf_chk@PLT
.L2:
	ret
	.cfi_endproc
.LFE3766:
	.size	_Z12check_result9cudaError, .-_Z12check_result9cudaError
	.globl	_ZplRK6float3S1_
	.type	_ZplRK6float3S1_, @function
_ZplRK6float3S1_:
.LFB3767:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3767:
	.size	_ZplRK6float3S1_, .-_ZplRK6float3S1_
	.globl	_ZmlRK6float3RKf
	.type	_ZmlRK6float3RKf, @function
_ZmlRK6float3RKf:
.LFB4444:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_ZplRK6float3S1_
	.cfi_endproc
.LFE4444:
	.size	_ZmlRK6float3RKf, .-_ZmlRK6float3RKf
	.globl	_Z6lengthRK6float3
	.type	_Z6lengthRK6float3, @function
_Z6lengthRK6float3:
.LFB3769:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3769:
	.size	_Z6lengthRK6float3, .-_Z6lengthRK6float3
	.globl	_Z9normalize6float3
	.type	_Z9normalize6float3, @function
_Z9normalize6float3:
.LFB3770:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movl	$1, 28(%rsp)
	movl	28(%rsp), %edi
	movq	%xmm0, (%rsp)
	movss	%xmm1, 8(%rsp)
	call	exit@PLT
	.cfi_endproc
.LFE3770:
	.size	_Z9normalize6float3, .-_Z9normalize6float3
	.globl	_Z7get_rayRKfS0_
	.type	_Z7get_rayRKfS0_, @function
_Z7get_rayRKfS0_:
.LFB3771:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3771:
	.size	_Z7get_rayRKfS0_, .-_Z7get_rayRKfS0_
	.globl	_Z13mandelbulb_de6float3
	.type	_Z13mandelbulb_de6float3, @function
_Z13mandelbulb_de6float3:
.LFB3772:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movl	$1, 28(%rsp)
	movl	28(%rsp), %edi
	movq	%xmm0, (%rsp)
	movss	%xmm1, 8(%rsp)
	call	exit@PLT
	.cfi_endproc
.LFE3772:
	.size	_Z13mandelbulb_de6float3, .-_Z13mandelbulb_de6float3
	.globl	_Z5march3ray
	.type	_Z5march3ray, @function
_Z5march3ray:
.LFB3773:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3773:
	.size	_Z5march3ray, .-_Z5march3ray
	.section	.rodata.str1.1
.LC2:
	.string	"w"
.LC3:
	.string	"P3\n"
.LC4:
	.string	"%i %i\n"
.LC5:
	.string	"%i\n"
.LC6:
	.string	"%i %i %i\n"
	.text
	.globl	_Z11write_imagePcP6float3mm
	.type	_Z11write_imagePcP6float3mm, @function
_Z11write_imagePcP6float3mm:
.LFB3774:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%r15d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	leaq	.LC2(%rip), %rsi
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rcx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdx, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	call	fopen@PLT
	leaq	.LC3(%rip), %rdx
	movl	$2, %esi
	movq	%rax, %rdi
	movq	%rax, (%rsp)
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movq	(%rsp), %rdi
	movq	%r12, %r8
	movq	%rbp, %rcx
	leaq	.LC4(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movq	(%rsp), %rdi
	movl	$255, %ecx
	xorl	%eax, %eax
	leaq	.LC5(%rip), %rdx
	movl	$2, %esi
	call	__fprintf_chk@PLT
	xorl	%r11d, %r11d
.L23:
	cmpq	%r12, %r11
	je	.L25
	imulq	$12, %r15, %rbx
	xorl	%r13d, %r13d
	addq	%r14, %rbx
.L26:
	cmpq	%rbp, %r13
	je	.L28
	cvttss2sil	(%rbx), %ecx
	movq	(%rsp), %rdi
	movl	$2, %esi
	xorl	%eax, %eax
	cvttss2sil	8(%rbx), %r9d
	leaq	.LC6(%rip), %rdx
	incq	%r13
	addq	$12, %rbx
	cvttss2sil	-8(%rbx), %r8d
	movq	%r11, 8(%rsp)
	call	__fprintf_chk@PLT
	movq	8(%rsp), %r11
	jmp	.L26
.L28:
	incq	%r11
	addq	%rbp, %r15
	jmp	.L23
.L25:
	movq	(%rsp), %rdi
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	fclose@PLT
	.cfi_endproc
.LFE3774:
	.size	_Z11write_imagePcP6float3mm, .-_Z11write_imagePcP6float3mm
	.globl	_Z33__device_stub__Z6d_mainP6float3mmP6float3mm
	.type	_Z33__device_stub__Z6d_mainP6float3mmP6float3mm, @function
_Z33__device_stub__Z6d_mainP6float3mmP6float3mm:
.LFB3800:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z6d_mainP6float3mm(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L29:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3800:
	.size	_Z33__device_stub__Z6d_mainP6float3mmP6float3mm, .-_Z33__device_stub__Z6d_mainP6float3mmP6float3mm
	.globl	_Z6d_mainP6float3mm
	.type	_Z6d_mainP6float3mm, @function
_Z6d_mainP6float3mm:
.LFB3801:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z6d_mainP6float3mmP6float3mm
	.cfi_endproc
.LFE3801:
	.size	_Z6d_mainP6float3mm, .-_Z6d_mainP6float3mm
	.section	.rodata.str1.1
.LC7:
	.string	"Not enought params.\n"
.LC8:
	.string	"Starting kernel execution...\n"
.LC9:
	.string	"Kernel execution ended.\n"
.LC10:
	.string	"Reading screan buffer from device...\n"
.LC11:
	.string	"Done.\n"
.LC14:
	.string	"Time taken (ms): %i\n"
.LC15:
	.string	"Writing to file...\n"
.LC16:
	.string	"Done\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3775:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	cmpl	$6, %edi
	jg	.L35
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	$1, %eax
	jmp	.L34
.L35:
	movq	8(%rsi), %rax
	movq	16(%rsi), %rdi
	movq	%rsi, %r13
	movq	%rax, 8(%rsp)
	call	atoi@PLT
	movq	24(%r13), %rdi
	movslq	%eax, %rbx
	call	atoi@PLT
	movq	%rbx, %r12
	movq	32(%r13), %rdi
	movslq	%eax, %rbp
	call	atoi@PLT
	imulq	%rbp, %r12
	movq	40(%r13), %rdi
	movl	%eax, %r15d
	cltq
	movq	%rax, 16(%rsp)
	call	atoi@PLT
	imulq	$12, %r12, %r12
	xorl	%edx, %edx
	leaq	32(%rsp), %rdi
	movl	%eax, %r14d
	cltq
	movq	%rax, 24(%rsp)
	movq	48(%r13), %rax
	movq	%r12, %rsi
	movb	(%rax), %r13b
	call	cudaHostAlloc@PLT
	movl	%eax, %edi
	call	_Z12check_result9cudaError
	movq	%r12, %rsi
	leaq	40(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	%eax, %edi
	call	_Z12check_result9cudaError
	movq	%rbx, %rax
	xorl	%edx, %edx
	movl	%r14d, 64(%rsp)
	divq	16(%rsp)
	movl	$1, 56(%rsp)
	movl	%r15d, 60(%rsp)
	movl	$1, 68(%rsp)
	xorl	%edx, %edx
	movl	%eax, 48(%rsp)
	movq	%rbp, %rax
	divq	24(%rsp)
	movl	%eax, 52(%rsp)
	call	clock@PLT
	movq	%rax, %r14
	cmpb	$116, %r13b
	je	.L37
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L37:
	movl	68(%rsp), %ecx
	movq	60(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	48(%rsp), %rdi
	movl	56(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	movq	40(%rsp), %rdi
	movq	%rbp, %rdx
	movq	%rbx, %rsi
	call	_Z33__device_stub__Z6d_mainP6float3mmP6float3mm
.L38:
	cmpb	$116, %r13b
	je	.L39
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC10(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L39:
	movq	32(%rsp), %rdi
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movq	%r12, %rdx
	call	cudaMemcpy@PLT
	movl	%eax, %edi
	call	_Z12check_result9cudaError
	cmpb	$116, %r13b
	je	.L40
	leaq	.LC11(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L40:
	call	clock@PLT
	leaq	.LC14(%rip), %rsi
	movl	$2, %edi
	subq	%r14, %rax
	cvtsi2sdq	%rax, %xmm0
	divsd	.LC12(%rip), %xmm0
	xorl	%eax, %eax
	mulsd	.LC13(%rip), %xmm0
	cvttsd2sil	%xmm0, %edx
	call	__printf_chk@PLT
	cmpb	$116, %r13b
	je	.L41
	leaq	.LC15(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	32(%rsp), %rsi
	movq	%rbp, %rcx
	movq	%rbx, %rdx
	movq	8(%rsp), %rdi
	call	_Z11write_imagePcP6float3mm
	leaq	.LC16(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L41:
	movq	32(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	xorl	%eax, %eax
.L34:
	movq	72(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L42
	call	__stack_chk_fail@PLT
.L42:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3775:
	.size	main, .-main
	.section	.rodata.str1.1
.LC17:
	.string	"_Z6d_mainP6float3mm"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3803:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC17(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6d_mainP6float3mm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3803:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC12:
	.long	0
	.long	1093567616
	.align 8
.LC13:
	.long	0
	.long	1083129856
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <fstream>
#include <time.h>


// Generic utils

typedef float3 pixel;

void check_result(hipError_t value) {
	hipError_t status = value;
	if (status != hipSuccess) {
		printf("Error %s at line %d in file %s\n",
			hipGetErrorString(status), __LINE__, __FILE__);
		// exit(1);
	}
}

__device__ float3 operator+(const float3 &a, const float3 &b) {
	return make_float3(a.x + b.x,a.y + b.y,a.z + b.z);
}

__device__ float3 operator*(const float3 &a, const float &b) {
	return make_float3(a.x * b, a.y * b, a.z * b);
}

__device__ float length(const float3 &vec) {
	return sqrt(vec.x * vec.x + vec.y * vec.y + vec.z * vec.z);
}

__device__ float3 normalize(const float3 vec) {
	float inverted_len = 1.0f / length(vec);
	return vec * inverted_len;
}


// Raymarcher

typedef struct {
	float3 o;
	float3 d;
} ray;

__device__ ray get_ray(const float& u, const float& v) {
	ray r;
	r.o = make_float3(-5.0, 0.0, 0.0);
	r.d = normalize(make_float3(1.0, u, v));
	return r;
}

__device__ float mandelbulb_de(float3 pos) {
	// pos = fmod(fabs(pos), 4.0) - 2.0;
	float3 z = pos;
	float dr = 1.0;
	float r = 0.0;
	int Iterations = 4;
	float Bailout = 4.0;
	float Power = 16.0;
	for(int i = 0; i < Iterations; i++) {
		r = length(z);
		if (r > Bailout) break;

		// convert to polar coordinates
		float theta = acos(z.z / r);
		float phi = atan2(z.y, z.x);
		dr = powf(r, Power - 1.0) * Power * dr + 1.0;

		// scale and rotate the point
		float zr = pow(r, Power);
		theta = theta * Power;
		phi = phi * Power;

		// convert back to cartesian coordinates
		z = make_float3(sin(theta) * cos(phi),
				sin(phi) * sin(theta), cos(theta)) * zr;
		z = z + pos;
		//z += pos * cos(time * 2.0);
	}
	return 0.5 * log(r) * r / dr;
}

__device__ float march(ray r) {
	float total_dist = 0.0;
	int max_ray_steps = 64;
	float min_distance = 0.002;

	int steps;
	for (steps = 0; steps < max_ray_steps; ++steps) {
		float3 p = r.o + r.d * total_dist;
		float distance = mandelbulb_de(p);
		total_dist += distance;
		if (distance < min_distance) break;
	}
	return 1.0 - (float) steps / (float) max_ray_steps;
}


// Main kernel

__global__ void d_main(
	pixel* screen_buffer,
	const size_t width,
	const size_t height
) {
	size_t x = (blockIdx.x * blockDim.x) + threadIdx.x;
	size_t y = (blockIdx.y * blockDim.y) + threadIdx.y;
	
	if(x < width && y < height) {
		float min_w_h = (float) min(width, height);

		float ar = (float) width / (float) height;
		float u = (float) x / min_w_h - ar * 0.5f;
		float v = (float) y / min_w_h - 0.5f;

		ray r = get_ray(u, v);
		float c = march(r) * 255.0f;
		float3 color = make_float3(c, c, c);
	
		screen_buffer[y * width + x] = color;
	}
}

void write_image(
	char* file_name,
	pixel* screen_buff,
	size_t width,
	size_t height
) {
	FILE* image = fopen(file_name, "w");
	fprintf(image, "P3\n");
	fprintf(image, "%i %i\n", width, height);
	fprintf(image, "%i\n", 255);
	for (size_t y = 0; y < height; y++) {
		for (size_t x = 0; x < width; x++) {
			float3 pixel = screen_buff[y * width + x];
			fprintf(image, "%i %i %i\n", (int) pixel.x, (int) pixel.y, (int) pixel.z);
		}
	}
	fclose(image);
}

int main(int argc, char** argv) {
	// printf("Mandelbulb\n");

	if(argc < 7) {
		printf("Not enought params.\n");
		return 1;
	}
	
	char* file_name = argv[1];
	size_t width = atoi(argv[2]);
	size_t height = atoi(argv[3]);
	size_t num_pixels = width * height;

	size_t group_width = atoi(argv[4]);
	size_t group_height = atoi(argv[5]);

	bool test = false;

	if (*argv[6] == 't') {
		test = true;
	}

	// Setup buffers
	pixel* h_screen_buff;
	pixel* d_screen_buff;
	check_result(hipHostMalloc(&h_screen_buff, num_pixels * sizeof(pixel), hipHostMallocDefault));
	check_result(hipMalloc(&d_screen_buff, num_pixels * sizeof(pixel)));

	dim3 block_dim(width / group_width, height / group_height);
	dim3 group_dim(group_width, group_height);

	// Execute on devicie
	clock_t t_start = clock();
	
	if(!test)
		printf("Starting kernel execution...\n");
	d_main<<<block_dim, group_dim>>>(d_screen_buff, width, height);
	if(!test)
		printf("Kernel execution ended.\n");
	
	if(!test)
		printf("Reading screan buffer from device...\n");
	check_result(hipMemcpy(h_screen_buff, d_screen_buff, num_pixels * sizeof(pixel), hipMemcpyDeviceToHost));
	if(!test)
		printf("Done.\n");

	printf("Time taken (ms): %i\n", (int) ((double) (clock() - t_start) / CLOCKS_PER_SEC * 1000.0f));	

	if(!test){
		printf("Writing to file...\n");
		write_image(file_name, h_screen_buff, width, height);
		printf("Done\n");
	}

	//for(size_t y = 0;y < height;y++) {
	//	for(size_t x = 0;x < width;x++) {
	//		printf("%i ", (int) h_screen_buff[y * width + x].x);
	//	}
	//	printf("\n");
	//}

	hipHostFree(h_screen_buff);
	hipFree(d_screen_buff);

	return 0;
}


	.text
	.file	"main.hip"
	.globl	_Z12check_result10hipError_t    # -- Begin function _Z12check_result10hipError_t
	.type	_Z12check_result10hipError_t,@function
_Z12check_result10hipError_t:           # @_Z12check_result10hipError_t
	.cfi_startproc
# %bb.0:
	testl	%edi, %edi
	je	.LBB0_1
# %bb.2:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	hipGetErrorString
	movl	$.L.str, %edi
	movl	$.L.str.1, %ecx
	movq	%rax, %rsi
	movl	$16, %edx
	xorl	%eax, %eax
	popq	%r8
	.cfi_def_cfa_offset 8
	jmp	printf                          # TAILCALL
.LBB0_1:
	retq
.Lfunc_end0:
	.size	_Z12check_result10hipError_t, .Lfunc_end0-_Z12check_result10hipError_t
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__d_mainP15HIP_vector_typeIfLj3EEmm # -- Begin function _Z21__device_stub__d_mainP15HIP_vector_typeIfLj3EEmm
	.type	_Z21__device_stub__d_mainP15HIP_vector_typeIfLj3EEmm,@function
_Z21__device_stub__d_mainP15HIP_vector_typeIfLj3EEmm: # @_Z21__device_stub__d_mainP15HIP_vector_typeIfLj3EEmm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6d_mainP15HIP_vector_typeIfLj3EEmm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z21__device_stub__d_mainP15HIP_vector_typeIfLj3EEmm, .Lfunc_end1-_Z21__device_stub__d_mainP15HIP_vector_typeIfLj3EEmm
	.cfi_endproc
                                        # -- End function
	.globl	_Z11write_imagePcP15HIP_vector_typeIfLj3EEmm # -- Begin function _Z11write_imagePcP15HIP_vector_typeIfLj3EEmm
	.type	_Z11write_imagePcP15HIP_vector_typeIfLj3EEmm,@function
_Z11write_imagePcP15HIP_vector_typeIfLj3EEmm: # @_Z11write_imagePcP15HIP_vector_typeIfLj3EEmm
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rcx, %r14
	movq	%rdx, %r13
	movq	%rsi, %rbx
	movl	$.L.str.2, %esi
	callq	fopen
	movq	%rax, %r12
	movl	$.L.str.3, %edi
	movl	$3, %esi
	movl	$1, %edx
	movq	%rax, %rcx
	callq	fwrite@PLT
	movl	$.L.str.4, %esi
	movq	%r12, %rdi
	movq	%r13, %rdx
	movq	%r14, %rcx
	xorl	%eax, %eax
	callq	fprintf
	movl	$.L.str.5, %esi
	movq	%r12, %rdi
	movl	$255, %edx
	xorl	%eax, %eax
	callq	fprintf
	movq	%r14, 16(%rsp)                  # 8-byte Spill
	testq	%r14, %r14
	je	.LBB2_4
# %bb.1:                                # %.preheader.lr.ph
	addq	$8, %rbx
	leaq	(,%r13,4), %rax
	leaq	(%rax,%rax,2), %rax
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	xorl	%ebp, %ebp
.LBB2_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_5 Depth 2
	movq	%rbx, %r15
	movq	%r13, %r14
	testq	%r13, %r13
	je	.LBB2_3
.LBB2_5:                                #   Parent Loop BB2_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	cvttss2si	-8(%r15), %edx
	cvttss2si	-4(%r15), %ecx
	cvttss2si	(%r15), %r8d
	movl	$.L.str.6, %esi
	movq	%r12, %rdi
	xorl	%eax, %eax
	callq	fprintf
	addq	$12, %r15
	decq	%r14
	jne	.LBB2_5
.LBB2_3:                                # %._crit_edge
                                        #   in Loop: Header=BB2_2 Depth=1
	incq	%rbp
	addq	8(%rsp), %rbx                   # 8-byte Folded Reload
	cmpq	16(%rsp), %rbp                  # 8-byte Folded Reload
	jne	.LBB2_2
.LBB2_4:                                # %._crit_edge21
	movq	%r12, %rdi
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	fclose                          # TAILCALL
.Lfunc_end2:
	.size	_Z11write_imagePcP15HIP_vector_typeIfLj3EEmm, .Lfunc_end2-_Z11write_imagePcP15HIP_vector_typeIfLj3EEmm
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI3_0:
	.quad	0x412e848000000000              # double 1.0E+6
.LCPI3_1:
	.quad	0x408f400000000000              # double 1000
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	cmpl	$6, %edi
	jg	.LBB3_2
# %bb.1:
	movl	$.Lstr.6, %edi
	callq	puts@PLT
	movl	$1, %ebp
	jmp	.LBB3_12
.LBB3_2:
	movq	%rsi, %rbx
	movq	8(%rsi), %rax
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	movq	16(%rsi), %rdi
	callq	atoi
	movslq	%eax, %r15
	movq	24(%rbx), %rdi
	callq	atoi
	movslq	%eax, %r14
	movq	32(%rbx), %rdi
	callq	atoi
	movslq	%eax, %r13
	movq	40(%rbx), %rdi
	callq	atoi
	movslq	%eax, %rbp
	movq	48(%rbx), %rax
	movb	(%rax), %bl
	movq	%r15, %rax
	imulq	%r14, %rax
	shlq	$2, %rax
	leaq	(%rax,%rax,2), %r12
	leaq	16(%rsp), %rdi
	movq	%r12, %rsi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movl	%eax, %edi
	callq	_Z12check_result10hipError_t
	leaq	8(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	%eax, %edi
	callq	_Z12check_result10hipError_t
	movq	%r15, 24(%rsp)                  # 8-byte Spill
	movq	%r15, %rax
	movq	%r14, %r15
	movl	%ebx, %r14d
	xorl	%edx, %edx
	divq	%r13
	movq	%rax, %rcx
	movq	%r15, %rax
	xorl	%edx, %edx
	divq	%rbp
	movq	%rax, %rbx
	movl	%ecx, %eax
	shlq	$32, %rbx
	orq	%rax, %rbx
	movl	%r13d, %eax
	shlq	$32, %rbp
	orq	%rax, %rbp
	callq	clock
	movq	%rax, %r13
	cmpb	$116, %r14b
	je	.LBB3_4
# %bb.3:
	movl	$.Lstr, %edi
	callq	puts@PLT
.LBB3_4:
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_6
# %bb.5:
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movq	%r15, %rdx
	callq	_Z21__device_stub__d_mainP15HIP_vector_typeIfLj3EEmm
.LBB3_6:
	cmpb	$116, %r14b
	jne	.LBB3_7
# %bb.8:                                # %.critedge41
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movl	%eax, %edi
	callq	_Z12check_result10hipError_t
	jmp	.LBB3_9
.LBB3_7:                                # %.critedge
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movl	%eax, %edi
	callq	_Z12check_result10hipError_t
	movl	$.Lstr.3, %edi
	callq	puts@PLT
.LBB3_9:
	callq	clock
	subq	%r13, %rax
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI3_0(%rip), %xmm0
	mulsd	.LCPI3_1(%rip), %xmm0
	cvttsd2si	%xmm0, %esi
	xorl	%ebp, %ebp
	movl	$.L.str.12, %edi
	xorl	%eax, %eax
	callq	printf
	cmpb	$116, %r14b
	je	.LBB3_11
# %bb.10:
	movl	$.Lstr.4, %edi
	callq	puts@PLT
	movq	16(%rsp), %rsi
	movq	32(%rsp), %rdi                  # 8-byte Reload
	movq	24(%rsp), %rdx                  # 8-byte Reload
	movq	%r15, %rcx
	callq	_Z11write_imagePcP15HIP_vector_typeIfLj3EEmm
	movl	$.Lstr.5, %edi
	callq	puts@PLT
.LBB3_11:
	movq	16(%rsp), %rdi
	callq	hipHostFree
	movq	8(%rsp), %rdi
	callq	hipFree
.LBB3_12:
	movl	%ebp, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6d_mainP15HIP_vector_typeIfLj3EEmm, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Error %s at line %d in file %s\n"
	.size	.L.str, 32

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/ichko/cuda-mandelbulb/master/main.hip"
	.size	.L.str.1, 100

	.type	_Z6d_mainP15HIP_vector_typeIfLj3EEmm,@object # @_Z6d_mainP15HIP_vector_typeIfLj3EEmm
	.section	.rodata,"a",@progbits
	.globl	_Z6d_mainP15HIP_vector_typeIfLj3EEmm
	.p2align	3, 0x0
_Z6d_mainP15HIP_vector_typeIfLj3EEmm:
	.quad	_Z21__device_stub__d_mainP15HIP_vector_typeIfLj3EEmm
	.size	_Z6d_mainP15HIP_vector_typeIfLj3EEmm, 8

	.type	.L.str.2,@object                # @.str.2
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.2:
	.asciz	"w"
	.size	.L.str.2, 2

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"P3\n"
	.size	.L.str.3, 4

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"%i %i\n"
	.size	.L.str.4, 7

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"%i\n"
	.size	.L.str.5, 4

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"%i %i %i\n"
	.size	.L.str.6, 10

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"Time taken (ms): %i\n"
	.size	.L.str.12, 21

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6d_mainP15HIP_vector_typeIfLj3EEmm"
	.size	.L__unnamed_1, 37

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Starting kernel execution..."
	.size	.Lstr, 29

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"Kernel execution ended."
	.size	.Lstr.1, 24

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"Reading screan buffer from device..."
	.size	.Lstr.2, 37

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"Done."
	.size	.Lstr.3, 6

	.type	.Lstr.4,@object                 # @str.4
.Lstr.4:
	.asciz	"Writing to file..."
	.size	.Lstr.4, 19

	.type	.Lstr.5,@object                 # @str.5
.Lstr.5:
	.asciz	"Done"
	.size	.Lstr.5, 5

	.type	.Lstr.6,@object                 # @str.6
.Lstr.6:
	.asciz	"Not enought params."
	.size	.Lstr.6, 20

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__d_mainP15HIP_vector_typeIfLj3EEmm
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6d_mainP15HIP_vector_typeIfLj3EEmm
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6d_mainP15HIP_vector_typeIfLj3EEmm ; -- Begin function _Z6d_mainP15HIP_vector_typeIfLj3EEmm
	.globl	_Z6d_mainP15HIP_vector_typeIfLj3EEmm
	.p2align	8
	.type	_Z6d_mainP15HIP_vector_typeIfLj3EEmm,@function
_Z6d_mainP15HIP_vector_typeIfLj3EEmm:   ; @_Z6d_mainP15HIP_vector_typeIfLj3EEmm
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_mov_b32_e32 v4, 0
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v5, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s8, 16
	s_and_b32 s1, s8, 0xffff
	s_mov_b32 s8, 0
	v_mad_u64_u32 v[0:1], null, s14, s1, v[2:3]
	v_mov_b32_e32 v1, v4
	v_mad_u64_u32 v[2:3], null, s15, s0, v[5:6]
	v_mov_b32_e32 v3, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[6:7], v[0:1]
	v_cmp_gt_u64_e64 s0, s[2:3], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_30
; %bb.1:
	v_cmp_lt_u64_e64 s0, s[6:7], s[2:3]
	s_clz_i32_u32 s9, s7
	s_clz_i32_u32 s10, s3
	v_cvt_f32_u32_e32 v6, v0
	v_cvt_f32_u32_e32 v8, v2
	s_mov_b32 s14, 0x3e76c4e1
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s1, s7, s3
	s_cselect_b32 s0, s6, s2
	s_clz_i32_u32 s13, s1
	s_min_u32 s9, s9, 32
	s_min_u32 s12, s10, 32
	s_min_u32 s13, s13, 32
	s_lshl_b64 s[10:11], s[6:7], s9
	s_lshl_b64 s[2:3], s[2:3], s12
	s_lshl_b64 s[0:1], s[0:1], s13
	s_min_u32 s10, s10, 1
	s_min_u32 s2, s2, 1
	s_min_u32 s0, s0, 1
	s_or_b32 s10, s11, s10
	s_or_b32 s0, s1, s0
	s_or_b32 s1, s3, s2
	v_cvt_f32_u32_e32 v3, s10
	v_cvt_f32_u32_e32 v5, s1
	v_cvt_f32_u32_e32 v1, s0
	s_sub_i32 s1, 32, s9
	s_sub_i32 s2, 32, s12
	s_sub_i32 s0, 32, s13
	v_ldexp_f32 v3, v3, s1
	v_ldexp_f32 v5, v5, s2
	v_ldexp_f32 v1, v1, s0
	s_mov_b32 s9, 0x3d1c21a7
	s_mov_b32 s10, 0x7fffff
	s_mov_b32 s11, 0x3b2d2a58
	v_div_scale_f32 v7, null, v5, v5, v3
	v_div_scale_f32 v9, null, v1, v1, v6
	v_div_scale_f32 v11, null, v1, v1, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v10, v7
	v_rcp_f32_e32 v12, v9
	v_div_scale_f32 v15, vcc_lo, v3, v5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(TRANS32_DEP_3)
	v_rcp_f32_e32 v13, v11
	v_div_scale_f32 v17, s0, v6, v1, v6
	s_mov_b32 s12, 0xb94c1982
	s_mov_b32 s13, 0x37d75334
	s_mov_b32 s15, 0
	v_fma_f32 v14, -v7, v10, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v16, -v9, v12, 1.0
	v_fmac_f32_e32 v10, v14, v10
	v_fma_f32 v14, -v11, v13, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v12, v16, v12
	v_div_scale_f32 v16, s1, v8, v1, v8
	v_dual_mul_f32 v18, v15, v10 :: v_dual_fmac_f32 v13, v14, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v14, v17, v12
	v_fma_f32 v19, -v7, v18, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v20, v16, v13
	v_fma_f32 v21, -v9, v14, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v18, v19, v10
	v_fma_f32 v19, -v11, v20, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v14, v21, v12
	v_fma_f32 v7, -v7, v18, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v20, v19, v13
	v_fma_f32 v9, -v9, v14, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v7, v7, v10, v18
	s_mov_b32 vcc_lo, s0
	v_fma_f32 v10, -v11, v20, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v9, v9, v12, v14
	s_mov_b32 vcc_lo, s1
	v_div_fixup_f32 v3, v7, v5, v3
	v_div_fmas_f32 v5, v10, v13, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v6, v9, v1, v6
	v_div_fixup_f32 v1, v5, v1, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v6, -0.5, v3 :: v_dual_add_f32 v3, -0.5, v1
	v_fma_f32 v1, v6, v6, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v1, v3, v3
	v_mul_f32_e32 v5, 0x4f800000, v1
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, v1, v5, vcc_lo
	v_sqrt_f32_e32 v5, v1
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v7, -1, v5
	v_add_nc_u32_e32 v8, 1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v9, -v7, v5, v1
	v_fma_f32 v10, -v8, v5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s0, 0, v9
	v_cndmask_b32_e64 v5, v5, v7, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, 0, v10
	v_cndmask_b32_e64 v5, v5, v8, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, 0x37800000, v5
	v_cndmask_b32_e32 v5, v5, v7, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v1, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, v5, v1, vcc_lo
	v_div_scale_f32 v5, null, v1, v1, 1.0
	v_div_scale_f32 v9, vcc_lo, 1.0, v1, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v7, v5
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, -v5, v7, 1.0
	v_fmac_f32_e32 v7, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v8, v9, v7
	v_fma_f32 v10, -v5, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, v10, v7
	v_fma_f32 v5, -v5, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v5, v5, v7, v8
	v_mov_b32_e32 v8, 0
	v_div_fixup_f32 v1, v5, v1, 1.0
	v_mov_b32_e32 v5, 0x4016cbe4
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f32_e32 v7, v3, v1
	v_mul_f32_e32 v6, v6, v1
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v10, v7, v8, 0
	v_fma_f32 v11, v6, v8, 0
	v_dual_fmaak_f32 v12, v1, v8, 0xc0a00000 :: v_dual_mov_b32 v9, 1.0
	s_mov_b32 s17, 4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v3, v10
	v_dual_mov_b32 v17, v11 :: v_dual_mov_b32 v18, v12
	s_mov_b32 s16, 0
                                        ; implicit-def: $sgpr18
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, v18, v18
	s_or_b32 s18, s18, exec_lo
	s_mov_b32 s19, exec_lo
	v_fmac_f32_e32 v13, v17, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v3, v3
	v_mul_f32_e32 v14, 0x4f800000, v13
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v13, v13, v14, vcc_lo
	v_sqrt_f32_e32 v14, v13
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v15, -1, v14
	v_add_nc_u32_e32 v16, 1, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v19, -v15, v14, v13
	v_fma_f32 v20, -v16, v14, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s0, 0, v19
	v_cndmask_b32_e64 v14, v14, v15, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, 0, v20
	v_cndmask_b32_e64 v14, v14, v16, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v15, 0x37800000, v14
	v_cndmask_b32_e32 v14, v14, v15, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v13, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v13, v14, v13, vcc_lo
	v_cmpx_nlt_f32_e32 4.0, v13
	s_cbranch_execz .LBB0_25
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=2
	v_div_scale_f32 v14, null, v13, v13, v3
	v_div_scale_f32 v19, vcc_lo, v3, v13, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v15, v14
	s_waitcnt_depctr 0xfff
	v_fma_f32 v16, -v14, v15, 1.0
	v_fmac_f32_e32 v15, v16, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v16, v19, v15
	v_fma_f32 v20, -v14, v16, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v16, v20, v15
	v_fma_f32 v14, -v14, v16, v19
                                        ; implicit-def: $vgpr19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v14, v14, v15, v16
	v_div_fixup_f32 v3, v14, v13, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f32 v14, |v3|, -0.5, 0.5
	v_mul_f32_e32 v15, v3, v3
	v_cmp_gt_f32_e64 vcc_lo, |v3|, 0.5
	v_cmp_gt_f32_e64 s0, 0, v3
	v_cndmask_b32_e32 v14, v15, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmaak_f32 v15, s9, v14, 0x3c5fc5da
	v_sqrt_f32_e32 v16, v14
	v_fmaak_f32 v15, v14, v15, 0x3d034c3c
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v15, v14, v15, 0x3d3641b1
	v_fmaak_f32 v15, v14, v15, 0x3d999bc8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v15, v14, v15, 0x3e2aaaac
	v_mul_f32_e32 v14, v14, v15
	s_waitcnt_depctr 0xfff
	v_fmac_f32_e32 v16, v16, v14
	v_fmac_f32_e32 v3, v3, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v15, v16, v16
	v_sub_f32_e32 v3, 0x3fc90fdb, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v16, 0x40490fdb, v15
	v_cndmask_b32_e64 v14, v15, v16, s0
                                        ; implicit-def: $vgpr16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v14, vcc_lo
	v_mul_f32_e32 v14, 0x41800000, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_b32_e32 v15, 0x7fffffff, v14
	v_cmp_ngt_f32_e64 s2, 0x48000000, |v14|
	v_lshrrev_b32_e32 v3, 23, v15
	v_and_or_b32 v22, v15, s10, 0x800000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v23, 0xffffff88, v3
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_3 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e32 vcc_lo, 63, v23
	v_mad_u64_u32 v[19:20], null, 0xfe5163ab, v22, 0
	v_cndmask_b32_e64 v16, 0, 0xffffffc0, vcc_lo
	v_add_nc_u32_e32 v16, v16, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v3, v20
	v_cmp_lt_u32_e64 s0, 31, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[20:21], null, 0x3c439041, v22, v[3:4]
	v_mov_b32_e32 v3, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v21, 0, 0xffffffe0, s0
	v_mad_u64_u32 v[24:25], null, 0xdb629599, v22, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v16, v21, v16
	v_cmp_lt_u32_e64 s1, 31, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v3, v25
	v_cndmask_b32_e32 v19, v24, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[25:26], null, 0xf534ddc0, v22, v[3:4]
	v_mov_b32_e32 v3, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[26:27], null, 0xfc2757d1, v22, v[3:4]
	v_mov_b32_e32 v3, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[27:28], null, 0x4e441529, v22, v[3:4]
	v_mov_b32_e32 v3, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v21, v27, v25, vcc_lo
	v_mad_u64_u32 v[28:29], null, 0xa2f9836e, v22, v[3:4]
	v_cndmask_b32_e64 v3, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v28, v28, v26 :: v_dual_add_nc_u32 v3, v3, v16
	v_dual_cndmask_b32 v27, v29, v27 :: v_dual_cndmask_b32 v26, v26, v24
	v_cndmask_b32_e32 v16, v25, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e64 v20, v28, v21, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v25, v27, v28, s0
	v_cndmask_b32_e64 v21, v21, v26, s0
	v_sub_nc_u32_e32 v27, 32, v3
	v_cndmask_b32_e64 v26, v26, v16, s0
	v_cndmask_b32_e64 v16, v16, v19, s0
	v_cndmask_b32_e64 v25, v25, v20, s1
	v_cndmask_b32_e64 v20, v20, v21, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v21, v21, v26, s1
	v_cndmask_b32_e64 v16, v26, v16, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v28, v25, v20, v27
	v_alignbit_b32 v24, v20, v21, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v26, v21, v16, v27
	v_cndmask_b32_e32 v3, v28, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v19, v24, v20, vcc_lo
	v_cndmask_b32_e32 v21, v26, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v20, v3, 29, 1
	v_alignbit_b32 v24, v3, v19, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v19, v19, v21, 30
	v_alignbit_b32 v16, v21, v16, 30
	v_sub_nc_u32_e32 v25, 0, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v24, v24, v25
	v_xor_b32_e32 v19, v19, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v16, v16, v25
	v_clz_i32_u32_e32 v26, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v26, 32, v26
	v_sub_nc_u32_e32 v21, 31, v26
	v_lshlrev_b32_e32 v28, 23, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_alignbit_b32 v24, v24, v19, v21
	v_alignbit_b32 v16, v19, v16, v21
	v_lshrrev_b32_e32 v21, 29, v3
	v_lshrrev_b32_e32 v3, 30, v3
	v_alignbit_b32 v19, v24, v16, 9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v21, 31, v21
	v_lshrrev_b32_e32 v24, 9, v24
	v_clz_i32_u32_e32 v25, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v27, 0.5, v21
	v_min_u32_e32 v25, 32, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v27, v27, v28
	v_sub_nc_u32_e32 v29, 31, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v16, v19, v16, v29
	v_or_b32_e32 v19, v24, v27
	v_add_lshl_u32 v24, v25, v26, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v16, 9, v16
	v_mul_f32_e32 v25, 0x3fc90fda, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v16, v16, v24
	v_fma_f32 v24, 0x3fc90fda, v19, -v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v16, 0x33000000, v16
	v_fmac_f32_e32 v24, 0x33a22168, v19
	v_add_nc_u32_e32 v19, v20, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v16, v16, v21
	v_fmac_f32_e32 v24, 0x3fc90fda, v16
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v16, v25, v24
.LBB0_6:                                ; %Flow74
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_saveexec_b32 s0, s3
	v_mul_f32_e64 v3, 0x3f22f983, |v14|
	s_delay_alu instid0(VALU_DEP_1)
	v_rndne_f32_e32 v26, v3
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.7:                                ;   in Loop: Header=BB0_3 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v16, 0xbfc90fda, v26, |v14|
	v_cvt_i32_f32_e32 v19, v26
	v_fmac_f32_e32 v16, 0xb3a22168, v26
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v16, 0xa7c234c4, v26
; %bb.8:                                ; %_ZL3sinf.exit.i.i
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_max_f32_e64 v3, |v17|, |v17|
	v_max_f32_e64 v20, |v18|, |v18|
	v_cmp_gt_f32_e64 vcc_lo, |v17|, |v18|
	v_cmp_eq_f32_e64 s0, 0, v17
	v_cmp_class_f32_e64 s1, v18, 0x204
	v_cmp_class_f32_e64 s3, v17, 0x204
	v_max_f32_e32 v21, v20, v3
	v_min_f32_e32 v3, v20, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_frexp_mant_f32_e32 v24, v21
	v_frexp_exp_i32_f32_e32 v21, v21
	v_rcp_f32_e32 v20, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_frexp_exp_i32_f32_e32 v24, v3
	v_frexp_mant_f32_e32 v3, v3
	v_sub_nc_u32_e32 v21, v24, v21
                                        ; implicit-def: $vgpr24
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, v3, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v3, v3, v21
	v_mul_f32_e32 v20, v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v21, s11, v20, 0xbc7a590c
	v_fmaak_f32 v21, v20, v21, 0x3d29fb3f
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v21, v20, v21, 0xbd97d4d7
	v_fmaak_f32 v21, v20, v21, 0x3dd931b2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v21, v20, v21, 0xbe1160e6
	v_fmaak_f32 v21, v20, v21, 0x3e4cb8bf
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v21, v20, v21, 0xbeaaaa62
	v_mul_f32_e32 v20, v20, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v3, v20
	v_sub_f32_e32 v20, 0x3fc90fdb, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v20, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, 0, v18
	v_sub_f32_e32 v20, 0x40490fdb, v3
	v_cndmask_b32_e64 v21, 0, 0x40490fdb, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v20, vcc_lo
	v_cndmask_b32_e32 v20, 0x3f490fdb, v5, vcc_lo
	s_and_b32 vcc_lo, s3, s1
	v_cndmask_b32_e64 v3, v3, v21, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v20, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v18, v17
                                        ; implicit-def: $vgpr18
	v_cndmask_b32_e32 v3, 0x7fc00000, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_bfi_b32 v3, 0x7fffffff, v3, v17
	v_mul_f32_e32 v17, 0x41800000, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_b32_e32 v21, 0x7fffffff, v17
	v_cmp_ngt_f32_e64 s3, 0x48000000, |v17|
	v_lshrrev_b32_e32 v3, 23, v21
	v_and_or_b32 v25, v21, s10, 0x800000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v28, 0xffffff88, v3
	s_and_saveexec_b32 s0, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s20, exec_lo, s0
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_3 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e32 vcc_lo, 63, v28
	v_mad_u64_u32 v[29:30], null, 0xfe5163ab, v25, 0
	v_cndmask_b32_e64 v18, 0, 0xffffffc0, vcc_lo
	v_add_nc_u32_e32 v18, v18, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e64 s0, 31, v18
	v_cndmask_b32_e64 v20, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v3, v30 :: v_dual_add_nc_u32 v18, v20, v18
	v_mad_u64_u32 v[30:31], null, 0x3c439041, v25, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v18
	v_mov_b32_e32 v3, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[31:32], null, 0xdb629599, v25, v[3:4]
	v_mov_b32_e32 v3, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v29, v31, v29, vcc_lo
	v_mad_u64_u32 v[32:33], null, 0xf534ddc0, v25, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v3, v33
	v_mad_u64_u32 v[33:34], null, 0xfc2757d1, v25, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v3, v34
	v_mad_u64_u32 v[34:35], null, 0x4e441529, v25, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v3, v35 :: v_dual_cndmask_b32 v20, v34, v32
	v_mad_u64_u32 v[35:36], null, 0xa2f9836e, v25, v[3:4]
	v_cndmask_b32_e64 v3, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v3, v3, v18
	v_dual_cndmask_b32 v24, v35, v33 :: v_dual_cndmask_b32 v27, v36, v34
	v_dual_cndmask_b32 v33, v33, v31 :: v_dual_cndmask_b32 v18, v32, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e64 v30, v24, v20, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v24, v27, v24, s0
	v_cndmask_b32_e64 v20, v20, v33, s0
	v_sub_nc_u32_e32 v27, 32, v3
	v_cndmask_b32_e64 v32, v33, v18, s0
	v_cndmask_b32_e64 v18, v18, v29, s0
	v_cndmask_b32_e64 v24, v24, v30, s1
	v_cndmask_b32_e64 v30, v30, v20, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v20, v20, v32, s1
	v_cndmask_b32_e64 v18, v32, v18, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v33, v24, v30, v27
	v_alignbit_b32 v31, v30, v20, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v27, v20, v18, v27
	v_dual_cndmask_b32 v3, v33, v24 :: v_dual_cndmask_b32 v24, v31, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v20, v27, v20, vcc_lo
	v_bfe_u32 v29, v3, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v30, v3, v24, 30
	v_alignbit_b32 v24, v24, v20, 30
	v_alignbit_b32 v18, v20, v18, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v31, 0, v29
	v_xor_b32_e32 v30, v30, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v20, v24, v31
	v_xor_b32_e32 v18, v18, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v27, v30
	v_min_u32_e32 v27, 32, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v24, 31, v27
	v_lshlrev_b32_e32 v33, 23, v27
	v_alignbit_b32 v30, v30, v20, v24
	v_alignbit_b32 v18, v20, v18, v24
	v_lshrrev_b32_e32 v24, 29, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v20, v30, v18, 9
	v_lshlrev_b32_e32 v24, 31, v24
	v_lshrrev_b32_e32 v30, 9, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v31, v20
	v_or_b32_e32 v32, 0.5, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v31, 32, v31
	v_sub_nc_u32_e32 v32, v32, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v34, 31, v31
	v_add_lshl_u32 v27, v31, v27, 23
	v_alignbit_b32 v18, v20, v18, v34
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v20, v30, v32
	v_lshrrev_b32_e32 v18, 9, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v30, 0x3fc90fda, v20
	v_sub_nc_u32_e32 v18, v18, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v27, 0x3fc90fda, v20, -v30
	v_add_nc_u32_e32 v18, 0x33000000, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v27, 0x33a22168, v20
	v_or_b32_e32 v18, v18, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v27, 0x3fc90fda, v18
	v_add_f32_e32 v18, v30, v27
	v_lshrrev_b32_e32 v3, 30, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v24, v29, v3
.LBB0_10:                               ; %Flow73
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_saveexec_b32 s0, s20
	v_mul_f32_e64 v3, 0x3f22f983, |v17|
	s_delay_alu instid0(VALU_DEP_1)
	v_rndne_f32_e32 v3, v3
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.11:                               ;   in Loop: Header=BB0_3 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v18, 0xbfc90fda, v3, |v17|
	v_cvt_i32_f32_e32 v24, v3
	v_fmac_f32_e32 v18, 0xb3a22168, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v18, 0xa7c234c4, v3
; %bb.12:                               ; %_ZL3cosf.exit.i.i
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr27
                                        ; implicit-def: $vgpr20
	s_and_saveexec_b32 s0, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB0_14
; %bb.13:                               ;   in Loop: Header=BB0_3 Depth=2
	v_mad_u64_u32 v[29:30], null, 0xfe5163ab, v25, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v28
	v_cndmask_b32_e64 v20, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v3, v30 :: v_dual_add_nc_u32 v20, v20, v28
	v_mad_u64_u32 v[30:31], null, 0x3c439041, v25, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 31, v20
	v_mov_b32_e32 v3, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[31:32], null, 0xdb629599, v25, v[3:4]
	v_mov_b32_e32 v3, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v29, v31, v29, vcc_lo
	v_mad_u64_u32 v[32:33], null, 0xf534ddc0, v25, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v3, v33
	v_mad_u64_u32 v[33:34], null, 0xfc2757d1, v25, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v3, v34
	v_cndmask_b32_e64 v34, 0, 0xffffffe0, s0
	v_mad_u64_u32 v[27:28], null, 0x4e441529, v25, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v20, v34, v20
	v_cmp_lt_u32_e64 s1, 31, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v3, v28
	v_mad_u64_u32 v[34:35], null, 0xa2f9836e, v25, v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, 0, 0xffffffe0, s1
	v_cndmask_b32_e32 v25, v27, v32, vcc_lo
	v_dual_cndmask_b32 v28, v34, v33 :: v_dual_add_nc_u32 v3, v3, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v27, v35, v27, vcc_lo
	v_dual_cndmask_b32 v33, v33, v31 :: v_dual_cndmask_b32 v20, v32, v30
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v30, v28, v25, s0
	v_cndmask_b32_e64 v27, v27, v28, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v25, v25, v33, s0
	v_sub_nc_u32_e32 v28, 32, v3
	v_cndmask_b32_e64 v32, v33, v20, s0
	v_cndmask_b32_e64 v20, v20, v29, s0
	v_cndmask_b32_e64 v27, v27, v30, s1
	v_cndmask_b32_e64 v30, v30, v25, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v25, v25, v32, s1
	v_cndmask_b32_e64 v20, v32, v20, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v33, v27, v30, v28
	v_alignbit_b32 v31, v30, v25, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v28, v25, v20, v28
	v_cndmask_b32_e32 v3, v33, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v27, v31, v30, vcc_lo
	v_cndmask_b32_e32 v25, v28, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v29, v3, 29, 1
	v_alignbit_b32 v30, v3, v27, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v27, v27, v25, 30
	v_alignbit_b32 v20, v25, v20, 30
	v_sub_nc_u32_e32 v31, 0, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v30, v30, v31
	v_xor_b32_e32 v25, v27, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v20, v20, v31
	v_clz_i32_u32_e32 v28, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v28, 32, v28
	v_sub_nc_u32_e32 v27, 31, v28
	v_lshlrev_b32_e32 v33, 23, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_alignbit_b32 v30, v30, v25, v27
	v_alignbit_b32 v20, v25, v20, v27
	v_lshrrev_b32_e32 v27, 29, v3
	v_lshrrev_b32_e32 v3, 30, v3
	v_alignbit_b32 v25, v30, v20, 9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v27, 31, v27
	v_lshrrev_b32_e32 v30, 9, v30
	v_clz_i32_u32_e32 v31, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v32, 0.5, v27
	v_min_u32_e32 v31, 32, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v32, v32, v33
	v_sub_nc_u32_e32 v34, 31, v31
	v_add_lshl_u32 v28, v31, v28, 23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v20, v25, v20, v34
	v_or_b32_e32 v25, v30, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v20, 9, v20
	v_mul_f32_e32 v30, 0x3fc90fda, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v20, v20, v28
	v_fma_f32 v28, 0x3fc90fda, v25, -v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v20, 0x33000000, v20
	v_fmac_f32_e32 v28, 0x33a22168, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or_b32_e32 v20, v20, v27
	v_add_nc_u32_e32 v27, v29, v3
                                        ; implicit-def: $vgpr3
	v_fmac_f32_e32 v28, 0x3fc90fda, v20
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v20, v30, v28
.LBB0_14:                               ; %Flow72
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_and_not1_saveexec_b32 s0, s3
; %bb.15:                               ;   in Loop: Header=BB0_3 Depth=2
	v_fma_f32 v20, 0xbfc90fda, v3, |v17|
	v_cvt_i32_f32_e32 v27, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v20, 0xb3a22168, v3
	v_fmac_f32_e32 v20, 0xa7c234c4, v3
; %bb.16:                               ; %_ZL3sinf.exit51.i.i
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr29
                                        ; implicit-def: $vgpr25
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_3 Depth=2
	v_mad_u64_u32 v[28:29], null, 0xfe5163ab, v22, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v23
	v_cndmask_b32_e64 v25, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v3, v29
	v_add_nc_u32_e32 v25, v25, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[29:30], null, 0x3c439041, v22, v[3:4]
	v_cmp_lt_u32_e64 s0, 31, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v3, v30
	v_cndmask_b32_e64 v35, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[30:31], null, 0xdb629599, v22, v[3:4]
	v_add_nc_u32_e32 v25, v35, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v25
	v_dual_mov_b32 v3, v31 :: v_dual_cndmask_b32 v28, v30, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[31:32], null, 0xf534ddc0, v22, v[3:4]
	v_mov_b32_e32 v3, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[32:33], null, 0xfc2757d1, v22, v[3:4]
	v_mov_b32_e32 v3, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[33:34], null, 0x4e441529, v22, v[3:4]
	v_dual_mov_b32 v3, v34 :: v_dual_cndmask_b32 v36, v33, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[34:35], null, 0xa2f9836e, v22, v[3:4]
	v_cndmask_b32_e64 v3, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v34, v34, v32 :: v_dual_add_nc_u32 v3, v3, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v33, v35, v33 :: v_dual_cndmask_b32 v32, v32, v30
	v_cndmask_b32_e32 v25, v31, v29, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v29, v34, v36, s0
	v_cndmask_b32_e64 v31, v33, v34, s0
	v_cndmask_b32_e64 v33, v36, v32, s0
	v_sub_nc_u32_e32 v34, 32, v3
	v_cndmask_b32_e64 v32, v32, v25, s0
	v_cndmask_b32_e64 v25, v25, v28, s0
	v_cndmask_b32_e64 v31, v31, v29, s1
	v_cndmask_b32_e64 v29, v29, v33, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v33, v33, v32, s1
	v_cndmask_b32_e64 v25, v32, v25, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v35, v31, v29, v34
	v_alignbit_b32 v30, v29, v33, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v32, v33, v25, v34
	v_dual_cndmask_b32 v3, v35, v31 :: v_dual_cndmask_b32 v28, v30, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v32, v32, v33, vcc_lo
	v_bfe_u32 v29, v3, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v30, v3, v28, 30
	v_alignbit_b32 v28, v28, v32, 30
	v_alignbit_b32 v25, v32, v25, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v31, 0, v29
	v_xor_b32_e32 v30, v30, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v28, v28, v31
	v_xor_b32_e32 v25, v25, v31
	v_lshrrev_b32_e32 v31, 29, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_clz_i32_u32_e32 v33, v30
	v_lshlrev_b32_e32 v31, 31, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v33, 32, v33
	v_or_b32_e32 v34, 0.5, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v32, 31, v33
	v_lshlrev_b32_e32 v35, 23, v33
	v_alignbit_b32 v30, v30, v28, v32
	v_alignbit_b32 v25, v28, v25, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v34, v34, v35
	v_alignbit_b32 v28, v30, v25, 9
	v_lshrrev_b32_e32 v30, 9, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v32, v28
	v_min_u32_e32 v32, 32, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v36, 31, v32
	v_alignbit_b32 v25, v28, v25, v36
	v_or_b32_e32 v28, v30, v34
	v_add_lshl_u32 v30, v32, v33, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v25, 9, v25
	v_mul_f32_e32 v32, 0x3fc90fda, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v25, v25, v30
	v_fma_f32 v30, 0x3fc90fda, v28, -v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v25, 0x33000000, v25
	v_fmac_f32_e32 v30, 0x33a22168, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v25, v25, v31
	v_fmac_f32_e32 v30, 0x3fc90fda, v25
	v_lshrrev_b32_e32 v3, 30, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v25, v32, v30
	v_add_nc_u32_e32 v29, v29, v3
.LBB0_18:                               ; %Flow70
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_and_not1_saveexec_b32 s0, s3
; %bb.19:                               ;   in Loop: Header=BB0_3 Depth=2
	v_fma_f32 v25, 0xbfc90fda, v26, |v14|
	v_cvt_i32_f32_e32 v29, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v25, 0xb3a22168, v26
	v_fmac_f32_e32 v25, 0xa7c234c4, v26
; %bb.20:                               ; %_ZL3sinf.exit59.i.i
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr28
                                        ; implicit-def: $vgpr3
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB0_22
; %bb.21:                               ;   in Loop: Header=BB0_3 Depth=2
	v_mad_u64_u32 v[30:31], null, 0xfe5163ab, v22, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v23
	v_cndmask_b32_e64 v26, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v3, v31
	v_add_nc_u32_e32 v23, v26, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[31:32], null, 0x3c439041, v22, v[3:4]
	v_cmp_lt_u32_e64 s0, 31, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v3, v32
	v_cndmask_b32_e64 v26, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[32:33], null, 0xdb629599, v22, v[3:4]
	v_add_nc_u32_e32 v23, v26, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v23
	v_dual_mov_b32 v3, v33 :: v_dual_cndmask_b32 v30, v32, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[33:34], null, 0xf534ddc0, v22, v[3:4]
	v_mov_b32_e32 v3, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[34:35], null, 0xfc2757d1, v22, v[3:4]
	v_mov_b32_e32 v3, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[35:36], null, 0x4e441529, v22, v[3:4]
	v_mov_b32_e32 v3, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[36:37], null, 0xa2f9836e, v22, v[3:4]
	v_cndmask_b32_e64 v3, 0, 0xffffffe0, s1
	v_cndmask_b32_e32 v22, v35, v33, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v26, v36, v34 :: v_dual_add_nc_u32 v3, v3, v23
	v_cndmask_b32_e32 v28, v37, v35, vcc_lo
	v_dual_cndmask_b32 v34, v34, v32 :: v_dual_cndmask_b32 v23, v33, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e64 v31, v26, v22, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v26, v28, v26, s0
	v_cndmask_b32_e64 v22, v22, v34, s0
	v_sub_nc_u32_e32 v28, 32, v3
	v_cndmask_b32_e64 v33, v34, v23, s0
	v_cndmask_b32_e64 v23, v23, v30, s0
	v_cndmask_b32_e64 v26, v26, v31, s1
	v_cndmask_b32_e64 v31, v31, v22, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v22, v22, v33, s1
	v_cndmask_b32_e64 v23, v33, v23, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v34, v26, v31, v28
	v_alignbit_b32 v32, v31, v22, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v28, v22, v23, v28
	v_dual_cndmask_b32 v3, v34, v26 :: v_dual_cndmask_b32 v26, v32, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v22, v28, v22, vcc_lo
	v_bfe_u32 v30, v3, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v31, v3, v26, 30
	v_alignbit_b32 v26, v26, v22, 30
	v_alignbit_b32 v22, v22, v23, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v32, 0, v30
	v_xor_b32_e32 v31, v31, v32
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v23, v26, v32
	v_xor_b32_e32 v22, v22, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v28, v31
	v_min_u32_e32 v28, 32, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v26, 31, v28
	v_lshlrev_b32_e32 v34, 23, v28
	v_alignbit_b32 v31, v31, v23, v26
	v_alignbit_b32 v22, v23, v22, v26
	v_lshrrev_b32_e32 v26, 29, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v23, v31, v22, 9
	v_lshlrev_b32_e32 v26, 31, v26
	v_lshrrev_b32_e32 v31, 9, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v32, v23
	v_or_b32_e32 v33, 0.5, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v32, 32, v32
	v_sub_nc_u32_e32 v33, v33, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v35, 31, v32
	v_add_lshl_u32 v28, v32, v28, 23
	v_alignbit_b32 v22, v23, v22, v35
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v23, v31, v33
	v_lshrrev_b32_e32 v22, 9, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v31, 0x3fc90fda, v23
	v_sub_nc_u32_e32 v22, v22, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v28, 0x3fc90fda, v23, -v31
	v_add_nc_u32_e32 v22, 0x33000000, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v28, 0x33a22168, v23
	v_or_b32_e32 v22, v22, v26
                                        ; implicit-def: $vgpr26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v28, 0x3fc90fda, v22
	v_lshrrev_b32_e32 v22, 30, v3
	v_dual_add_f32 v3, v31, v28 :: v_dual_add_nc_u32 v28, v30, v22
.LBB0_22:                               ; %Flow
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_and_not1_saveexec_b32 s0, s2
; %bb.23:                               ;   in Loop: Header=BB0_3 Depth=2
	v_fma_f32 v3, 0xbfc90fda, v26, |v14|
	v_cvt_i32_f32_e32 v28, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, 0xb3a22168, v26
	v_fmac_f32_e32 v3, 0xa7c234c4, v26
; %bb.24:                               ; %_ZL3cosf.exit65.i.i
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_frexp_mant_f32_e64 v22, |v13|
	v_and_b32_e32 v38, 1, v27
	v_and_b32_e32 v40, 1, v19
	v_frexp_exp_i32_f32_e32 v45, v13
	v_cmp_eq_f32_e64 s1, 1.0, v13
	v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v22
	v_cmp_class_f32_e64 s20, v13, 0x204
	v_cmp_eq_f32_e32 vcc_lo, 0, v13
	v_xor_b32_e32 v21, v21, v17
	v_cndmask_b32_e64 v56, 0x41800000, 1.0, s1
	v_cndmask_b32_e64 v23, 0, 1, s0
	v_cndmask_b32_e64 v44, 0x41700000, 1.0, s1
	s_add_i32 s17, s17, -1
	v_mul_f32_e32 v37, v20, v20
	v_lshlrev_b32_e32 v19, 30, v19
	v_ldexp_f32 v22, v22, v23
	v_trunc_f32_e32 v53, v44
	v_lshlrev_b32_e32 v27, 30, v27
	v_and_b32_e32 v43, 1, v24
	v_mul_f32_e32 v41, v18, v18
	v_add_f32_e32 v23, 1.0, v22
	v_dual_add_f32 v30, -1.0, v22 :: v_dual_fmaak_f32 v47, s13, v37, 0xbab64f3b
	v_and_b32_e32 v27, 0x80000000, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v52, s13, v41, 0xbab64f3b
	v_add_f32_e32 v32, -1.0, v23
	v_and_b32_e32 v19, 0x80000000, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v47, v37, v47, 0x3d2aabf7 :: v_dual_sub_f32 v22, v22, v32
	v_rcp_f32_e32 v26, v23
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v31, v30, v26
	v_mul_f32_e32 v33, v23, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v23, v31, v23, -v33
	v_fmac_f32_e32 v23, v31, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v22, v33, v23
	v_sub_f32_e32 v33, v22, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v32, v30, v22 :: v_dual_sub_f32 v23, v33, v23
	v_sub_f32_e32 v30, v30, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v22, v30, v22
	v_add_f32_e32 v22, v23, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v22, v32, v22
	v_mul_f32_e32 v22, v26, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v23, v31, v22
	v_sub_f32_e32 v26, v23, v31
	v_mul_f32_e32 v30, v23, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v22, v22, v26
	v_fma_f32 v26, v23, v23, -v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v31, v22, v22
	v_fmac_f32_e32 v26, v23, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v31, v30, v26
	v_fmaak_f32 v32, s14, v31, 0x3e91f4c4
	v_sub_f32_e32 v30, v31, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v32, v31, v32, 0x3ecccdef
	v_dual_sub_f32 v26, v26, v30 :: v_dual_mul_f32 v33, v31, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v30, v31, v32, -v33
	v_fmac_f32_e32 v30, v26, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v32, v33, v30
	v_dual_add_f32 v34, 0x3f2aaaaa, v32 :: v_dual_mul_f32 v35, v23, v31
	v_sub_f32_e32 v33, v32, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v36, v31, v23, -v35
	v_fmac_f32_e32 v36, v31, v22
	v_ldexp_f32 v22, v22, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v31, v25, v25 :: v_dual_fmac_f32 v36, v26, v23
	v_and_b32_e32 v26, 1, v29
	v_lshlrev_b32_e32 v29, 30, v29
	v_ldexp_f32 v23, v23, 1
	v_and_b32_e32 v29, 0x80000000, v29
	v_add_f32_e32 v39, v35, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v29, v15, v29
	v_dual_sub_f32 v35, v39, v35 :: v_dual_sub_f32 v30, v30, v33
	v_add_f32_e32 v33, 0xbf2aaaaa, v34
	v_xor_b32_e32 v15, v15, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v35, v36, v35 :: v_dual_add_f32 v30, 0x31739010, v30
	v_sub_f32_e32 v32, v32, v33
	v_mul_f32_e32 v36, v3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v30, v30, v32
	v_add_f32_e32 v33, v34, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v34, v34, v33
	v_mul_f32_e32 v42, v39, v33
	v_add_f32_e32 v30, v30, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v34, v39, v33, -v42
	v_fmac_f32_e32 v34, v39, v30
	v_cndmask_b32_e64 v30, 0x7f800000, 0, vcc_lo
	s_or_b32 vcc_lo, vcc_lo, s20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v34, v35, v33
	v_subrev_co_ci_u32_e64 v35, s0, 0, v45, s0
	v_fmaak_f32 v45, s12, v37, 0x3c0881c4
	v_and_b32_e32 v33, 1, v28
	v_cmp_eq_f32_e64 s0, v53, v44
	v_cvt_f32_i32_e32 v35, v35
	v_trunc_f32_e32 v53, v56
	v_fmaak_f32 v45, v37, v45, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v48, 0x3f317218, v35
	v_cmp_eq_f32_e64 s2, v53, v56
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v45, v37, v45
	v_fma_f32 v49, 0x3f317218, v35, -v48
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_fmac_f32 v20, v20, v45 :: v_dual_fmac_f32 v49, 0xb102e308, v35
	v_add_f32_e32 v39, v42, v34
	v_fmaak_f32 v35, s12, v41, 0x3c0881c4
	v_fmaak_f32 v57, s12, v36, 0x3c0881c4
	v_fmaak_f32 v58, s13, v36, 0xbab64f3b
	v_add_f32_e32 v50, v48, v49
	v_add_f32_e32 v46, v23, v39
	v_sub_f32_e32 v42, v39, v42
	v_dual_mul_f32 v32, v16, v16 :: v_dual_fmaak_f32 v19, v41, v35, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v23, v46, v23
	v_sub_f32_e32 v34, v34, v42
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v19, v41, v19 :: v_dual_lshlrev_b32 v24, 30, v24
	v_sub_f32_e32 v23, v39, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v39, s12, v32, 0x3c0881c4 :: v_dual_add_f32 v22, v22, v34
	v_fmac_f32_e32 v18, v18, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v39, v32, v39, 0xbe2aaa9d
	v_dual_add_f32 v22, v22, v23 :: v_dual_fmaak_f32 v23, s13, v32, 0xbab64f3b
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v54, 0.5, v44 :: v_dual_mul_f32 v39, v32, v39
	v_add_f32_e32 v51, v46, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v23, v32, v23, 0x3d2aabf7 :: v_dual_lshlrev_b32 v28, 30, v28
	v_fmac_f32_e32 v16, v16, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v55, v50, v51 :: v_dual_sub_f32 v46, v51, v46
	v_fmaak_f32 v23, v32, v23, 0xbf000004
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v59, v55, v50 :: v_dual_and_b32 v28, 0x80000000, v28
	v_sub_f32_e32 v48, v50, v48
	v_sub_f32_e32 v22, v22, v46
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v23, v32, v23, 1.0
	v_sub_f32_e32 v60, v55, v59
	v_fmaak_f32 v42, s12, v31, 0x3c0881c4
	v_sub_f32_e32 v48, v49, v48
	v_dual_sub_f32 v46, v51, v59 :: v_dual_mul_f32 v59, 0.5, v56
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v49, v50, v60 :: v_dual_fmaak_f32 v42, v31, v42, 0xbe2aaa9d
	v_add_f32_e32 v50, v48, v22
	v_fmaak_f32 v34, s13, v31, 0xbab64f3b
	v_trunc_f32_e32 v51, v54
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_f32_e32 v42, v31, v42
	v_add_f32_e32 v46, v46, v49
	v_sub_f32_e32 v35, v50, v48
	v_fmaak_f32 v49, v41, v52, 0x3d2aabf7
	v_cmp_neq_f32_e64 s1, v51, v54
	v_fmac_f32_e32 v25, v25, v42
	v_add_f32_e32 v46, v50, v46
	v_sub_f32_e32 v50, v50, v35
	v_and_b32_e32 v24, 0x80000000, v24
	v_sub_f32_e32 v22, v22, v35
	s_and_b32 s0, s0, s1
	v_add_f32_e32 v52, v55, v46
	v_sub_f32_e32 v35, v48, v50
	v_cndmask_b32_e64 v32, 1.0, v13, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v48, v52, v55
	v_dual_add_f32 v22, v22, v35 :: v_dual_fmaak_f32 v55, v36, v58, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v35, v46, v48 :: v_dual_fmaak_f32 v46, v37, v47, 0xbf000004
	v_trunc_f32_e32 v48, v59
	v_add_f32_e32 v22, v22, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v37, v37, v46, 1.0
	v_fmaak_f32 v35, v41, v49, 0xbf000004
	v_add_f32_e32 v47, v52, v22
	v_fmaak_f32 v34, v31, v34, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v19, v41, v35, 1.0
	v_mul_f32_e32 v45, v56, v47
	v_dual_sub_f32 v51, v47, v52 :: v_dual_mul_f32 v52, v44, v47
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v34, v31, v34, 0xbf000004
	v_cmp_class_f32_e64 s3, v45, 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v22, v22, v51
	v_fma_f32 v46, v44, v47, -v52
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f32 v31, v31, v34, 1.0
	v_fma_f32 v34, v56, v47, -v45
	v_cmp_class_f32_e64 s1, v52, 0x204
	v_cndmask_b32_e64 v47, 0, v13, s0
	v_fmac_f32_e32 v46, v44, v22
	v_cmp_eq_u32_e64 s0, 0, v38
	v_fmac_f32_e32 v34, v56, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v22, v52, v46
	v_cndmask_b32_e64 v20, v37, v20, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f32_e32 v35, v45, v34
	v_cmp_eq_u32_e64 s0, 0, v26
	v_cndmask_b32_e64 v39, v22, v52, s1
	v_cmp_neq_f32_e64 s1, v48, v59
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v41, v35, v45, s3
	v_cndmask_b32_e64 v25, v31, v25, s0
	v_cmp_eq_u32_e64 s0, 0, v40
	v_cmp_eq_f32_e64 s3, 0x42b17218, v39
	v_dual_sub_f32 v22, v22, v52 :: v_dual_sub_f32 v35, v35, v45
	v_xor3_b32 v20, v21, v27, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v16, v23, v16, s0
	v_cndmask_b32_e64 v42, 0, 0x37000000, s3
	v_cmp_eq_f32_e64 s3, 0x42b17218, v41
	v_cmp_eq_u32_e64 s0, 0, v43
	v_sub_f32_e32 v22, v46, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v27, v34, v35 :: v_dual_sub_f32 v48, v39, v42
	v_cndmask_b32_e64 v44, 0, 0x37000000, s3
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v18, -v18, v19, s0
	s_and_b32 s0, s2, s1
	v_cmp_eq_u32_e64 s1, 0, v33
	v_mul_f32_e32 v26, 0x3fb8aa3b, v48
	v_sub_f32_e32 v37, v41, v44
	v_cndmask_b32_e64 v43, 1.0, v13, s0
	v_cndmask_b32_e64 v33, 0, v13, s0
	v_cmp_neq_f32_e64 s0, 0x7f800000, |v39|
	v_fma_f32 v19, 0x3fb8aa3b, v48, -v26
	v_mul_f32_e32 v23, 0x3fb8aa3b, v37
	v_rndne_f32_e32 v31, v26
	v_xor3_b32 v25, v29, v25, v14
	v_cndmask_b32_e64 v22, 0, v22, s0
	v_fmac_f32_e32 v19, 0x32a5705f, v48
	v_fma_f32 v38, 0x3fb8aa3b, v37, -v23
	v_rndne_f32_e32 v40, v23
	v_sub_f32_e32 v26, v26, v31
	v_fmaak_f32 v50, v36, v57, 0xbe2aaa9d
	v_cmp_neq_f32_e64 s0, 0x7f800000, |v41|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v38, 0x32a5705f, v37 :: v_dual_sub_f32 v23, v23, v40
	v_add_f32_e32 v19, v26, v19
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_f32_e32 v49, v36, v50
	v_fmaak_f32 v50, v36, v55, 0xbf000004
	v_add_f32_e32 v22, v42, v22
	v_add_f32_e32 v23, v23, v38
	v_exp_f32_e32 v19, v19
	v_fmac_f32_e32 v3, v3, v49
	v_fma_f32 v36, v36, v50, 1.0
	v_bfi_b32 v26, 0x7fffffff, v30, v47
	v_exp_f32_e32 v21, v23
	v_cvt_i32_f32_e32 v23, v31
	v_cvt_i32_f32_e32 v31, v40
	v_cndmask_b32_e64 v3, -v3, v36, s1
	v_xor_b32_e32 v18, v24, v18
	s_cmp_eq_u32 s17, 0
	v_ldexp_f32 v19, v19, v23
	v_cndmask_b32_e64 v23, 0, v27, s0
	v_cmp_ngt_f32_e64 s0, 0xc2ce8ed0, v48
	v_xor_b32_e32 v3, v28, v3
	v_ldexp_f32 v21, v21, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v23, v44, v23
	v_cndmask_b32_e64 v19, 0, v19, s0
	v_cmp_ngt_f32_e64 s0, 0xc2ce8ed0, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v21, 0, v21, s0
	v_cmp_nlt_f32_e64 s0, 0x42b17218, v48
	v_cndmask_b32_e64 v19, 0x7f800000, v19, s0
	v_cmp_nlt_f32_e64 s0, 0x42b17218, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v22, v19, v22, v19
	v_cndmask_b32_e64 v21, 0x7f800000, v21, s0
	v_cmp_eq_f32_e64 s1, 0x7f800000, v19
	v_cmp_class_f32_e64 s0, v14, 0x1f8
	v_xor3_b32 v14, v15, v16, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v15, v21, v23, v21
	v_cndmask_b32_e64 v16, v22, v19, s1
	v_cmp_eq_f32_e64 s1, 0x7f800000, v21
	v_bfi_b32 v19, 0x7fffffff, v30, v33
	v_cndmask_b32_e64 v14, 0x7fc00000, v14, s0
	v_cndmask_b32_e64 v3, 0x7fc00000, v3, s0
	v_bfi_b32 v16, 0x7fffffff, v16, v32
	v_cndmask_b32_e64 v15, v15, v21, s1
	v_cmp_class_f32_e64 s1, v17, 0x1f8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v16, v16, v26, vcc_lo
	v_bfi_b32 v15, 0x7fffffff, v15, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v17, 0x7fc00000, v20, s1
	v_cndmask_b32_e64 v20, 0x7fc00000, v25, s0
	v_cndmask_b32_e64 v18, 0x7fc00000, v18, s1
	v_dual_mul_f32 v16, 0x41800000, v16 :: v_dual_cndmask_b32 v15, v15, v19
	v_cmp_u_f32_e32 vcc_lo, v13, v13
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mul_f32 v17, v17, v20 :: v_dual_mul_f32 v14, v14, v18
	s_cselect_b32 s0, -1, 0
	s_and_not1_b32 s1, s18, exec_lo
	v_cndmask_b32_e64 v16, v16, 0x7fc00000, vcc_lo
	v_cndmask_b32_e64 v15, v15, 0x7fc00000, vcc_lo
	s_and_b32 s0, s0, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_or_b32 s18, s1, s0
	v_fma_f32 v9, v9, v16, 1.0
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f32 v18, v15, v14, v12
	v_fma_f32 v17, v15, v17, v11
	v_fma_f32 v3, v15, v3, v10
.LBB0_25:                               ; %Flow75
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s18
	s_or_b32 s16, s0, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB0_3
; %bb.26:                               ; %_Z13mandelbulb_de15HIP_vector_typeIfLj3EE.exit.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v13
	v_cvt_f64_f32_e32 v[14:15], v9
	s_mov_b32 s0, -1
	s_mov_b32 s1, exec_lo
	v_cndmask_b32_e64 v3, 1.0, 0x4f800000, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v3, v13, v3
	v_cvt_f64_f32_e32 v[12:13], v13
	v_log_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v10, 0x3f317217, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v11, 0x3f317217, v3, -v10
	v_fmac_f32_e32 v11, 0x3377d1cf, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v10, v10, v11
	v_cndmask_b32_e64 v11, 0, 0x41b17218, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3|
	v_cndmask_b32_e32 v3, v3, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v3, v3, v11
	v_cvt_f64_f32_e32 v[10:11], v3
	v_mov_b32_e32 v3, s15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], v[10:11], 0.5
	v_mul_f64 v[9:10], v[10:11], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[11:12], null, v[14:15], v[14:15], v[9:10]
	v_div_scale_f64 v[20:21], vcc_lo, v[9:10], v[14:15], v[9:10]
	v_rcp_f64_e32 v[16:17], v[11:12]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[11:12], v[16:17], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
	v_fma_f64 v[18:19], -v[11:12], v[16:17], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
	v_mul_f64 v[18:19], v[20:21], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], -v[11:12], v[18:19], v[20:21]
	v_div_fmas_f64 v[11:12], v[11:12], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[9:10], v[11:12], v[14:15], v[9:10]
	v_cvt_f32_f64_e32 v9, v[9:10]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e32 0x3b03126f, v9
; %bb.27:                               ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s15, s15, 1
	v_dual_add_f32 v8, v8, v9 :: v_dual_mov_b32 v3, 64
	s_cmp_eq_u32 s15, 64
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s0, s0, exec_lo
; %bb.28:                               ; %Flow76
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s0
	s_or_b32 s8, s0, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB0_2
; %bb.29:                               ; %_Z5march3ray.exit
	s_or_b32 exec_lo, exec_lo, s8
	v_mad_u64_u32 v[4:5], null, v2, s6, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v1, v5
	v_mad_u64_u32 v[5:6], null, v4, 12, s[4:5]
	v_cvt_f32_i32_e32 v4, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[7:8], null, v2, s7, v[1:2]
	v_dual_mov_b32 v1, v6 :: v_dual_mov_b32 v6, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v7, 12, v[1:2]
	v_dual_fmamk_f32 v1, v4, 0xbc800000, v6 :: v_dual_mov_b32 v6, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v1, 0x437f0000, v1
	v_mad_u64_u32 v[7:8], null, v0, 12, v[5:6]
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v2, v1
	v_mov_b32_e32 v3, v1
	global_store_b96 v[7:8], v[1:3], off
.LBB0_30:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6d_mainP15HIP_vector_typeIfLj3EEmm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 61
		.amdhsa_next_free_sgpr 21
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6d_mainP15HIP_vector_typeIfLj3EEmm, .Lfunc_end0-_Z6d_mainP15HIP_vector_typeIfLj3EEmm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 7948
; NumSgprs: 23
; NumVgprs: 61
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 7
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 61
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           8
        .value_kind:     by_value
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6d_mainP15HIP_vector_typeIfLj3EEmm
    .private_segment_fixed_size: 0
    .sgpr_count:     23
    .sgpr_spill_count: 0
    .symbol:         _Z6d_mainP15HIP_vector_typeIfLj3EEmm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     61
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
