#include <iostream>

__device__ int compute_layer(float tx, float ty, float radius) {
    int x = int(std::abs(tx) / radius + 0.5);
    int y = int(std::abs(ty) / radius + 0.5);
    if (x == 1 && y == 1)
        return 2;
    int c = 0;
    if (x + y < 2)
        c = x + y;
    else
        c = x + y + 1;
    if (c > 5)
        c = 5;
    return c;
}

__global__ void five_kernel(int batch_size, int num_points, int num_featdim, int num_neighbors, int num_groups, int num_feat_per_threads,
    const float* points, const float* tex, const int* idx, float* out, float radius)
{
    int b = blockIdx.y;
    int group_idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (group_idx >= num_groups)
        return;
    int feat_start = num_feat_per_threads * blockIdx.z;
    int feat_end = feat_start + num_feat_per_threads;
    if (feat_end >= num_featdim)
        feat_end = num_featdim;
    const int* group_array = idx + (b * num_groups + group_idx) * num_neighbors;
    const float* tex_array = tex + 2 * num_points * b;
    const float* points_array = points + (b * num_points * num_featdim);
    float* out_array = out + (b * num_groups + group_idx) * (6 * num_featdim);
    int layers_counts[6] = {0, 0, 0, 0, 0, 0};
    for (int i = 0; i < num_neighbors; ++i) {
        int index = group_array[i];
        if (tex_array[index * 2] > 1e20)
            continue;
        int layer = compute_layer(tex_array[index * 2], tex_array[index * 2 + 1], radius);
        layers_counts[layer] += 1;
    }

    for (int i = 0; i < num_neighbors; ++i) {
        int index = group_array[i];
        if (tex_array[index * 2] > 1e20)
            continue;
        int layer = compute_layer(tex_array[index * 2], tex_array[index * 2 + 1], radius);
        float* out_temp = out_array + layer * num_featdim;

        const float* point_temp = points_array + index * num_featdim;
        for (int j = feat_start; j < feat_end; ++j) {
            out_temp[j] += point_temp[j] / layers_counts[layer];
        }
    }
    for (int i = 0; i < 6; ++i) {
        if (layers_counts[i] == 0) {
            int front = i;
            int rear = i;
            float weight_front = 0.0f;
            float weight_rear = 0.0f;
            while (front >= 0 && layers_counts[front] == 0)
                front -= 1;
            while (rear < 6 && layers_counts[rear] == 0)
                rear += 1;
            if (front >= 0 && rear < 6) {
                weight_rear = (i - front) / (rear - front + 0.0f);
                weight_front = 1.0f - weight_rear;
            }
            else if (front >= 0) {
                weight_front = 1.0f;
                weight_rear = 0.0f;
                rear = 5;
            }
            else {
                weight_front = 0.0f;
                weight_rear = 1.0f;
                front = 0;
            }
            float* out_temp = out_array + i * num_featdim;
            float* out_front = out_array + front * num_featdim;
            float* out_rear = out_array + rear * num_featdim;
            for (int j = feat_start; j < feat_end; ++j) {
                out_temp[j] = out_front[j] * weight_front + out_rear[j] * weight_rear;
            }
        }
    }
}

__global__ void fivegrad_kernel(int batch_size, int num_points, int num_featdim, int num_neighbors, int num_groups, int num_feat_per_threads,
    const float* points, const float* tex, const int* idx, const float* grad_out, float* grad_points, float radius)
{
    int b = blockIdx.y;
    int group_idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (group_idx >= num_groups)
        return;
    int feat_start = num_feat_per_threads * blockIdx.z;
    int feat_end = feat_start + num_feat_per_threads;
    if (feat_end >= num_featdim)
        feat_end = num_featdim;
    const int* group_array = idx + (b * num_groups + group_idx) * num_neighbors;
    const float* tex_array = tex + 2 * num_points * b;
    float* points_array = grad_points + (b * num_points * num_featdim);
    const float* out_array = grad_out + (b * num_groups + group_idx) * (6 * num_featdim);
    int layers_counts[6] = {0, 0, 0, 0, 0, 0};
    float weights_front[6] = {0, 0, 0, 0, 0, 0};
    float weights_rear[6] = {0, 0, 0, 0, 0, 0};
    for (int i = 0; i < num_neighbors; ++i) {
        int index = group_array[i];
        if (tex_array[index * 2] > 1e20)
            continue;
        int layer = compute_layer(tex_array[index * 2], tex_array[index * 2 + 1], radius);
        layers_counts[layer] += 1;
    }

    for (int i = 0; i < 6; ++i) {
        if (layers_counts[i] == 0) {
            int front = i;
            int rear = i;
            float weight_front = 0.0f;
            float weight_rear = 0.0f;
            while (front >= 0 && layers_counts[front] == 0)
                front -= 1;
            while (rear < 6 && layers_counts[rear] == 0)
                rear += 1;
            if (front >= 0 && rear < 6) {
                weight_rear = (i - front) / (rear - front + 0.0f);
                weight_front = 1.0f - weight_rear;
            }
            else if (front >= 0) {
                weight_front = 1.0f;
                weight_rear = 0.0f;
                rear = 5;
            }
            else {
                weight_front = 0.0f;
                weight_rear = 1.0f;
                front = 0;
            }
            weights_front[i] = weight_front;
            weights_rear[i] = weight_rear;
        }
    }

    for (int i = 0; i < num_neighbors; ++i) {
        int index = group_array[i];
        if (tex_array[index * 2] > 1e20)
            continue;
        int layer = compute_layer(tex_array[index * 2], tex_array[index * 2 + 1], radius);
        const float* out_temp = out_array + layer * num_featdim;
        float* point_temp = points_array + index * num_featdim;
        for (int j = feat_start; j < feat_end; ++j) {
            float signal = out_temp[j];
            int l = layer - 1;
            const float* out_temp_step = out_temp - num_featdim;
            while (l >= 0 && layers_counts[l] == 0) {
                signal += out_temp_step[j] * weights_rear[l];
                out_temp_step -= num_featdim;
                l -= 1;
            }
            l = layer + 1;
            out_temp_step = out_temp + num_featdim;
            while (l < 6 && layers_counts[l] == 0) {
                signal += out_temp_step[j] * weights_front[l];
                out_temp_step += num_featdim;
                l += 1;
            }
            atomicAdd(&point_temp[j], signal / layers_counts[layer]);
        }
    }
}

void fivekernel_gpu(int batch_size, int num_points, int num_featdim, int num_neighbors, int num_groups, const float* points, const float* tex, const int* idx, float* out, float radius) {
    int num_threads_for_feat = (num_groups + 255) / num_groups;
    int num_feat_per_threads = (num_featdim + num_threads_for_feat - 1) / num_threads_for_feat;
    five_kernel<<<dim3((num_groups + 255) / 256, batch_size, num_threads_for_feat), dim3(256, 1, 1)>>>(batch_size, num_points, num_featdim, num_neighbors, num_groups, num_feat_per_threads, points, tex, idx, out, radius);
}

void fivekernelgrad_gpu(int batch_size, int num_points, int num_featdim, int num_neighbors, int num_groups, const float* points, const float* tex, const int* idx, const float* grad_out, float* grad_points, float radius) {
    int num_threads_for_feat = (num_groups + 255) / num_groups;
    int num_feat_per_threads = (num_featdim + num_threads_for_feat - 1) / num_threads_for_feat;
    fivegrad_kernel<<<dim3((num_groups + 255) / 256, batch_size, num_threads_for_feat), dim3(256, 1, 1)>>>(
        batch_size, num_points, num_featdim, num_neighbors, num_groups, num_feat_per_threads, points, tex, idx, grad_out, grad_points, radius);
    
}
	.file	"tmpxft_00271d62_00000000-6_tf_interpolate_g.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3640:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3640:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z13compute_layerfff
	.type	_Z13compute_layerfff, @function
_Z13compute_layerfff:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3635:
	.size	_Z13compute_layerfff, .-_Z13compute_layerfff
	.globl	_Z47__device_stub__Z11five_kerneliiiiiiPKfS0_PKiPffiiiiiiPKfS0_PKiPff
	.type	_Z47__device_stub__Z11five_kerneliiiiiiPKfS0_PKiPffiiiiiiPKfS0_PKiPff, @function
_Z47__device_stub__Z11five_kerneliiiiiiPKfS0_PKiPffiiiiiiPKfS0_PKiPff:
.LFB3662:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	240(%rsp), %rax
	movl	%edi, 60(%rsp)
	leaq	80(%rsp), %rdi
	movl	%esi, 56(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rax, 32(%rsp)
	movq	248(%rsp), %rax
	movl	%edx, 52(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rax, 24(%rsp)
	movq	256(%rsp), %rax
	movl	%ecx, 48(%rsp)
	leaq	72(%rsp), %rcx
	movq	%rax, 16(%rsp)
	movq	264(%rsp), %rax
	movl	%r8d, 44(%rsp)
	movl	%r9d, 40(%rsp)
	movq	%rax, 8(%rsp)
	movss	%xmm0, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	60(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	72(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z11five_kerneliiiiiiPKfS0_PKiPff(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 256
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L4:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3662:
	.size	_Z47__device_stub__Z11five_kerneliiiiiiPKfS0_PKiPffiiiiiiPKfS0_PKiPff, .-_Z47__device_stub__Z11five_kerneliiiiiiPKfS0_PKiPffiiiiiiPKfS0_PKiPff
	.globl	_Z11five_kerneliiiiiiPKfS0_PKiPff
	.type	_Z11five_kerneliiiiiiPKfS0_PKiPff, @function
_Z11five_kerneliiiiiiPKfS0_PKiPff:
.LFB3663:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z11five_kerneliiiiiiPKfS0_PKiPffiiiiiiPKfS0_PKiPff
	.cfi_endproc
.LFE3663:
	.size	_Z11five_kerneliiiiiiPKfS0_PKiPff, .-_Z11five_kerneliiiiiiPKfS0_PKiPff
	.globl	_Z14fivekernel_gpuiiiiiPKfS0_PKiPff
	.type	_Z14fivekernel_gpuiiiiiPKfS0_PKiPff, @function
_Z14fivekernel_gpuiiiiiPKfS0_PKiPff:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%edx, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%ecx, %r14d
	leal	255(%r8), %ecx
	movl	%ecx, %eax
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r9, %r13
	xorl	%r9d, %r9d
	cltd
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	idivl	%r8d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movl	%edi, %ebp
	movl	%r8d, %ebx
	xorl	%r8d, %r8d
	movl	%esi, 8(%rsp)
	movl	$256, %esi
	movl	%edi, 28(%rsp)
	movss	%xmm0, 12(%rsp)
	movl	%eax, %r12d
	movl	%ecx, %eax
	movl	$1, %ecx
	cltd
	idivl	%esi
	movl	$16777217, %edx
	movl	%r12d, %esi
	salq	$8, %rdx
	movl	%eax, 24(%rsp)
	movq	24(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	movss	12(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L10
	leal	-1(%r15,%r12), %eax
	movl	%ebx, %r8d
	movl	%r14d, %ecx
	movl	%ebp, %edi
	cltd
	pushq	128(%rsp)
	.cfi_def_cfa_offset 120
	idivl	%r12d
	pushq	128(%rsp)
	.cfi_def_cfa_offset 128
	pushq	128(%rsp)
	.cfi_def_cfa_offset 136
	pushq	%r13
	.cfi_def_cfa_offset 144
	movl	40(%rsp), %esi
	movl	%r15d, %edx
	movl	%eax, %r9d
	call	_Z47__device_stub__Z11five_kerneliiiiiiPKfS0_PKiPffiiiiiiPKfS0_PKiPff
	addq	$32, %rsp
	.cfi_def_cfa_offset 112
.L10:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	_Z14fivekernel_gpuiiiiiPKfS0_PKiPff, .-_Z14fivekernel_gpuiiiiiPKfS0_PKiPff
	.globl	_Z54__device_stub__Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_PffiiiiiiPKfS0_PKiS0_Pff
	.type	_Z54__device_stub__Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_PffiiiiiiPKfS0_PKiS0_Pff, @function
_Z54__device_stub__Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_PffiiiiiiPKfS0_PKiS0_Pff:
.LFB3664:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	272(%rsp), %rax
	movl	%edi, 76(%rsp)
	leaq	104(%rsp), %rdi
	movl	%esi, 72(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rax, 48(%rsp)
	movq	280(%rsp), %rax
	movl	%edx, 68(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rax, 40(%rsp)
	movq	288(%rsp), %rax
	movl	%ecx, 64(%rsp)
	leaq	96(%rsp), %rcx
	movq	%rax, 32(%rsp)
	movq	296(%rsp), %rax
	movl	%r8d, 60(%rsp)
	movq	%rax, 24(%rsp)
	movq	304(%rsp), %rax
	movl	%r9d, 56(%rsp)
	movq	%rax, 16(%rsp)
	movss	%xmm0, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	76(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	68(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	60(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movl	$1, 112(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	96(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 288
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L13:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3664:
	.size	_Z54__device_stub__Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_PffiiiiiiPKfS0_PKiS0_Pff, .-_Z54__device_stub__Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_PffiiiiiiPKfS0_PKiS0_Pff
	.globl	_Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff
	.type	_Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff, @function
_Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff:
.LFB3665:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_PffiiiiiiPKfS0_PKiS0_Pff
	.cfi_endproc
.LFE3665:
	.size	_Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff, .-_Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff
	.globl	_Z18fivekernelgrad_gpuiiiiiPKfS0_PKiS0_Pff
	.type	_Z18fivekernelgrad_gpuiiiiiPKfS0_PKiS0_Pff, @function
_Z18fivekernelgrad_gpuiiiiiPKfS0_PKiS0_Pff:
.LFB3637:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%edx, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%ecx, %r14d
	leal	255(%r8), %ecx
	movl	%ecx, %eax
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r9, %r13
	xorl	%r9d, %r9d
	cltd
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	idivl	%r8d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movl	%edi, %ebp
	movl	%r8d, %ebx
	xorl	%r8d, %r8d
	movl	%esi, 8(%rsp)
	movl	$256, %esi
	movl	%edi, 28(%rsp)
	movss	%xmm0, 12(%rsp)
	movl	%eax, %r12d
	movl	%ecx, %eax
	movl	$1, %ecx
	cltd
	idivl	%esi
	movl	$16777217, %edx
	movl	%r12d, %esi
	salq	$8, %rdx
	movl	%eax, 24(%rsp)
	movq	24(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	movss	12(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L18
	leal	-1(%r15,%r12), %eax
	movl	%ebx, %r8d
	movl	%r14d, %ecx
	movl	%ebp, %edi
	cltd
	idivl	%r12d
	pushq	%rdx
	.cfi_def_cfa_offset 120
	movl	%eax, %r9d
	movl	%r15d, %edx
	pushq	144(%rsp)
	.cfi_def_cfa_offset 128
	pushq	144(%rsp)
	.cfi_def_cfa_offset 136
	pushq	144(%rsp)
	.cfi_def_cfa_offset 144
	pushq	144(%rsp)
	.cfi_def_cfa_offset 152
	pushq	%r13
	.cfi_def_cfa_offset 160
	movl	56(%rsp), %esi
	call	_Z54__device_stub__Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_PffiiiiiiPKfS0_PKiS0_Pff
	addq	$48, %rsp
	.cfi_def_cfa_offset 112
.L18:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3637:
	.size	_Z18fivekernelgrad_gpuiiiiiPKfS0_PKiS0_Pff, .-_Z18fivekernelgrad_gpuiiiiiPKfS0_PKiS0_Pff
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff"
.LC1:
	.string	"_Z11five_kerneliiiiiiPKfS0_PKiPff"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3667:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11five_kerneliiiiiiPKfS0_PKiPff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3667:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>

__device__ int compute_layer(float tx, float ty, float radius) {
    int x = int(std::abs(tx) / radius + 0.5);
    int y = int(std::abs(ty) / radius + 0.5);
    if (x == 1 && y == 1)
        return 2;
    int c = 0;
    if (x + y < 2)
        c = x + y;
    else
        c = x + y + 1;
    if (c > 5)
        c = 5;
    return c;
}

__global__ void five_kernel(int batch_size, int num_points, int num_featdim, int num_neighbors, int num_groups, int num_feat_per_threads,
    const float* points, const float* tex, const int* idx, float* out, float radius)
{
    int b = blockIdx.y;
    int group_idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (group_idx >= num_groups)
        return;
    int feat_start = num_feat_per_threads * blockIdx.z;
    int feat_end = feat_start + num_feat_per_threads;
    if (feat_end >= num_featdim)
        feat_end = num_featdim;
    const int* group_array = idx + (b * num_groups + group_idx) * num_neighbors;
    const float* tex_array = tex + 2 * num_points * b;
    const float* points_array = points + (b * num_points * num_featdim);
    float* out_array = out + (b * num_groups + group_idx) * (6 * num_featdim);
    int layers_counts[6] = {0, 0, 0, 0, 0, 0};
    for (int i = 0; i < num_neighbors; ++i) {
        int index = group_array[i];
        if (tex_array[index * 2] > 1e20)
            continue;
        int layer = compute_layer(tex_array[index * 2], tex_array[index * 2 + 1], radius);
        layers_counts[layer] += 1;
    }

    for (int i = 0; i < num_neighbors; ++i) {
        int index = group_array[i];
        if (tex_array[index * 2] > 1e20)
            continue;
        int layer = compute_layer(tex_array[index * 2], tex_array[index * 2 + 1], radius);
        float* out_temp = out_array + layer * num_featdim;

        const float* point_temp = points_array + index * num_featdim;
        for (int j = feat_start; j < feat_end; ++j) {
            out_temp[j] += point_temp[j] / layers_counts[layer];
        }
    }
    for (int i = 0; i < 6; ++i) {
        if (layers_counts[i] == 0) {
            int front = i;
            int rear = i;
            float weight_front = 0.0f;
            float weight_rear = 0.0f;
            while (front >= 0 && layers_counts[front] == 0)
                front -= 1;
            while (rear < 6 && layers_counts[rear] == 0)
                rear += 1;
            if (front >= 0 && rear < 6) {
                weight_rear = (i - front) / (rear - front + 0.0f);
                weight_front = 1.0f - weight_rear;
            }
            else if (front >= 0) {
                weight_front = 1.0f;
                weight_rear = 0.0f;
                rear = 5;
            }
            else {
                weight_front = 0.0f;
                weight_rear = 1.0f;
                front = 0;
            }
            float* out_temp = out_array + i * num_featdim;
            float* out_front = out_array + front * num_featdim;
            float* out_rear = out_array + rear * num_featdim;
            for (int j = feat_start; j < feat_end; ++j) {
                out_temp[j] = out_front[j] * weight_front + out_rear[j] * weight_rear;
            }
        }
    }
}

__global__ void fivegrad_kernel(int batch_size, int num_points, int num_featdim, int num_neighbors, int num_groups, int num_feat_per_threads,
    const float* points, const float* tex, const int* idx, const float* grad_out, float* grad_points, float radius)
{
    int b = blockIdx.y;
    int group_idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (group_idx >= num_groups)
        return;
    int feat_start = num_feat_per_threads * blockIdx.z;
    int feat_end = feat_start + num_feat_per_threads;
    if (feat_end >= num_featdim)
        feat_end = num_featdim;
    const int* group_array = idx + (b * num_groups + group_idx) * num_neighbors;
    const float* tex_array = tex + 2 * num_points * b;
    float* points_array = grad_points + (b * num_points * num_featdim);
    const float* out_array = grad_out + (b * num_groups + group_idx) * (6 * num_featdim);
    int layers_counts[6] = {0, 0, 0, 0, 0, 0};
    float weights_front[6] = {0, 0, 0, 0, 0, 0};
    float weights_rear[6] = {0, 0, 0, 0, 0, 0};
    for (int i = 0; i < num_neighbors; ++i) {
        int index = group_array[i];
        if (tex_array[index * 2] > 1e20)
            continue;
        int layer = compute_layer(tex_array[index * 2], tex_array[index * 2 + 1], radius);
        layers_counts[layer] += 1;
    }

    for (int i = 0; i < 6; ++i) {
        if (layers_counts[i] == 0) {
            int front = i;
            int rear = i;
            float weight_front = 0.0f;
            float weight_rear = 0.0f;
            while (front >= 0 && layers_counts[front] == 0)
                front -= 1;
            while (rear < 6 && layers_counts[rear] == 0)
                rear += 1;
            if (front >= 0 && rear < 6) {
                weight_rear = (i - front) / (rear - front + 0.0f);
                weight_front = 1.0f - weight_rear;
            }
            else if (front >= 0) {
                weight_front = 1.0f;
                weight_rear = 0.0f;
                rear = 5;
            }
            else {
                weight_front = 0.0f;
                weight_rear = 1.0f;
                front = 0;
            }
            weights_front[i] = weight_front;
            weights_rear[i] = weight_rear;
        }
    }

    for (int i = 0; i < num_neighbors; ++i) {
        int index = group_array[i];
        if (tex_array[index * 2] > 1e20)
            continue;
        int layer = compute_layer(tex_array[index * 2], tex_array[index * 2 + 1], radius);
        const float* out_temp = out_array + layer * num_featdim;
        float* point_temp = points_array + index * num_featdim;
        for (int j = feat_start; j < feat_end; ++j) {
            float signal = out_temp[j];
            int l = layer - 1;
            const float* out_temp_step = out_temp - num_featdim;
            while (l >= 0 && layers_counts[l] == 0) {
                signal += out_temp_step[j] * weights_rear[l];
                out_temp_step -= num_featdim;
                l -= 1;
            }
            l = layer + 1;
            out_temp_step = out_temp + num_featdim;
            while (l < 6 && layers_counts[l] == 0) {
                signal += out_temp_step[j] * weights_front[l];
                out_temp_step += num_featdim;
                l += 1;
            }
            atomicAdd(&point_temp[j], signal / layers_counts[layer]);
        }
    }
}

void fivekernel_gpu(int batch_size, int num_points, int num_featdim, int num_neighbors, int num_groups, const float* points, const float* tex, const int* idx, float* out, float radius) {
    int num_threads_for_feat = (num_groups + 255) / num_groups;
    int num_feat_per_threads = (num_featdim + num_threads_for_feat - 1) / num_threads_for_feat;
    five_kernel<<<dim3((num_groups + 255) / 256, batch_size, num_threads_for_feat), dim3(256, 1, 1)>>>(batch_size, num_points, num_featdim, num_neighbors, num_groups, num_feat_per_threads, points, tex, idx, out, radius);
}

void fivekernelgrad_gpu(int batch_size, int num_points, int num_featdim, int num_neighbors, int num_groups, const float* points, const float* tex, const int* idx, const float* grad_out, float* grad_points, float radius) {
    int num_threads_for_feat = (num_groups + 255) / num_groups;
    int num_feat_per_threads = (num_featdim + num_threads_for_feat - 1) / num_threads_for_feat;
    fivegrad_kernel<<<dim3((num_groups + 255) / 256, batch_size, num_threads_for_feat), dim3(256, 1, 1)>>>(
        batch_size, num_points, num_featdim, num_neighbors, num_groups, num_feat_per_threads, points, tex, idx, grad_out, grad_points, radius);
    
}
	.text
	.file	"tf_interpolate_g.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z26__device_stub__five_kerneliiiiiiPKfS0_PKiPff # -- Begin function _Z26__device_stub__five_kerneliiiiiiPKfS0_PKiPff
	.type	_Z26__device_stub__five_kerneliiiiiiPKfS0_PKiPff,@function
_Z26__device_stub__five_kerneliiiiiiPKfS0_PKiPff: # @_Z26__device_stub__five_kerneliiiiiiPKfS0_PKiPff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	4(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	movq	%r9, 80(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11five_kerneliiiiiiPKfS0_PKiPff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z26__device_stub__five_kerneliiiiiiPKfS0_PKiPff, .Lfunc_end0-_Z26__device_stub__five_kerneliiiiiiPKfS0_PKiPff
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff # -- Begin function _Z30__device_stub__fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff
	.type	_Z30__device_stub__fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff,@function
_Z30__device_stub__fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff: # @_Z30__device_stub__fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	4(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 80(%rbx)
	movq	%r9, 88(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z30__device_stub__fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff, .Lfunc_end1-_Z30__device_stub__fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff
	.cfi_endproc
                                        # -- End function
	.globl	_Z14fivekernel_gpuiiiiiPKfS0_PKiPff # -- Begin function _Z14fivekernel_gpuiiiiiPKfS0_PKiPff
	.type	_Z14fivekernel_gpuiiiiiPKfS0_PKiPff,@function
_Z14fivekernel_gpuiiiiiPKfS0_PKiPff:    # @_Z14fivekernel_gpuiiiiiPKfS0_PKiPff
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	%r9, 16(%rsp)                   # 8-byte Spill
	movl	%r8d, %r14d
	movl	%ecx, %ebp
	movl	%edx, %r15d
	movl	%esi, %r12d
	movl	%edi, %r13d
	leal	255(%r14), %ecx
	movl	%ecx, %eax
	cltd
	idivl	%r8d
	movl	%eax, %ebx
	leal	510(%r14), %edi
	testl	%ecx, %ecx
	cmovnsl	%ecx, %edi
	sarl	$8, %edi
	movq	%r13, %rax
	shlq	$32, %rax
	orq	%rax, %rdi
	movabsq	$4294967552, %rdx               # imm = 0x100000100
	movl	%ebx, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB2_1
# %bb.2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	jmp	.LBB2_3
.LBB2_1:
	.cfi_def_cfa_offset 80
	movq	96(%rsp), %r10
	movq	88(%rsp), %r11
	leal	(%r15,%rbx), %eax
	decl	%eax
	cltd
	idivl	%ebx
	movl	%r13d, %edi
	movl	%r12d, %esi
	movl	%r15d, %edx
	movl	%ebp, %ecx
	movl	%r14d, %r8d
	movl	%eax, %r9d
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	pushq	%r11
	.cfi_adjust_cfa_offset 8
	pushq	96(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	40(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	callq	_Z26__device_stub__five_kerneliiiiiiPKfS0_PKiPff
	addq	$56, %rsp
	.cfi_adjust_cfa_offset -56
.LBB2_3:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z14fivekernel_gpuiiiiiPKfS0_PKiPff, .Lfunc_end2-_Z14fivekernel_gpuiiiiiPKfS0_PKiPff
	.cfi_endproc
                                        # -- End function
	.globl	_Z18fivekernelgrad_gpuiiiiiPKfS0_PKiS0_Pff # -- Begin function _Z18fivekernelgrad_gpuiiiiiPKfS0_PKiS0_Pff
	.type	_Z18fivekernelgrad_gpuiiiiiPKfS0_PKiS0_Pff,@function
_Z18fivekernelgrad_gpuiiiiiPKfS0_PKiS0_Pff: # @_Z18fivekernelgrad_gpuiiiiiPKfS0_PKiS0_Pff
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	%r9, 16(%rsp)                   # 8-byte Spill
	movl	%r8d, %r14d
	movl	%ecx, %ebp
	movl	%edx, %r15d
	movl	%esi, %r12d
	movl	%edi, %r13d
	leal	255(%r14), %ecx
	movl	%ecx, %eax
	cltd
	idivl	%r8d
	movl	%eax, %ebx
	leal	510(%r14), %edi
	testl	%ecx, %ecx
	cmovnsl	%ecx, %edi
	sarl	$8, %edi
	movq	%r13, %rax
	shlq	$32, %rax
	orq	%rax, %rdi
	movabsq	$4294967552, %rdx               # imm = 0x100000100
	movl	%ebx, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB3_1
# %bb.2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	jmp	.LBB3_3
.LBB3_1:
	.cfi_def_cfa_offset 80
	movq	104(%rsp), %r10
	movq	96(%rsp), %r11
	leal	(%r15,%rbx), %eax
	decl	%eax
	cltd
	idivl	%ebx
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	%r13d, %edi
	movl	%r12d, %esi
	movl	%r15d, %edx
	movl	%ebp, %ecx
	movl	%r14d, %r8d
	movl	%eax, %r9d
	movss	20(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	pushq	%r11
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	56(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	callq	_Z30__device_stub__fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff
	addq	$72, %rsp
	.cfi_adjust_cfa_offset -72
.LBB3_3:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z18fivekernelgrad_gpuiiiiiPKfS0_PKiS0_Pff, .Lfunc_end3-_Z18fivekernelgrad_gpuiiiiiPKfS0_PKiS0_Pff
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11five_kerneliiiiiiPKfS0_PKiPff, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z11five_kerneliiiiiiPKfS0_PKiPff,@object # @_Z11five_kerneliiiiiiPKfS0_PKiPff
	.section	.rodata,"a",@progbits
	.globl	_Z11five_kerneliiiiiiPKfS0_PKiPff
	.p2align	3, 0x0
_Z11five_kerneliiiiiiPKfS0_PKiPff:
	.quad	_Z26__device_stub__five_kerneliiiiiiPKfS0_PKiPff
	.size	_Z11five_kerneliiiiiiPKfS0_PKiPff, 8

	.type	_Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff,@object # @_Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff
	.globl	_Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff
	.p2align	3, 0x0
_Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff:
	.quad	_Z30__device_stub__fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff
	.size	_Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z11five_kerneliiiiiiPKfS0_PKiPff"
	.size	.L__unnamed_1, 34

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff"
	.size	.L__unnamed_2, 41

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__five_kerneliiiiiiPKfS0_PKiPff
	.addrsig_sym _Z30__device_stub__fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z11five_kerneliiiiiiPKfS0_PKiPff
	.addrsig_sym _Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11five_kerneliiiiiiPKfS0_PKiPff ; -- Begin function _Z11five_kerneliiiiiiPKfS0_PKiPff
	.globl	_Z11five_kerneliiiiiiPKfS0_PKiPff
	.p2align	8
	.type	_Z11five_kerneliiiiiiPKfS0_PKiPff,@function
_Z11five_kerneliiiiiiPKfS0_PKiPff:      ; @_Z11five_kerneliiiiiiPKfS0_PKiPff
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b128 s[4:7], s[0:1], 0x4
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s13, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s7, v1
	s_cbranch_execz .LBB0_27
; %bb.1:
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, s14, s7, v[1:2]
	s_clause 0x2
	s_load_b256 s[16:23], s[0:1], 0x18
	s_load_b32 s10, s[0:1], 0x14
	s_load_b32 s7, s[0:1], 0x38
	s_mul_i32 s11, s14, s4
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, 0
	s_lshl_b32 s0, s11, 1
	v_mul_lo_u32 v0, v2, s6
	s_ashr_i32 s1, s0, 31
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, 0
	s_lshl_b64 s[0:1], s[0:1], 2
	v_dual_mov_b32 v13, 0 :: v_dual_mov_b32 v12, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_add_u32 s13, s18, s0
	s_addc_u32 s14, s19, s1
	s_cmp_gt_i32 s6, 0
	s_cselect_b32 s12, -1, 0
	v_add_co_u32 v0, vcc_lo, s20, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s21, v1, vcc_lo
	s_cmp_lt_i32 s6, 1
	s_cbranch_scc1 .LBB0_6
; %bb.2:                                ; %.lr.ph.preheader
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v13, 0
	v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v3, v0
	v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v10, 0
	v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v8, 0
	s_mov_b32 s8, 0x78b58c40
	s_mov_b32 s9, 0x4415af1d
	s_mov_b32 s18, s6
.LBB0_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v5, v[3:4], off
	s_mov_b32 s19, exec_lo
	s_waitcnt vmcnt(0)
	v_lshlrev_b32_e32 v5, 1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s13, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s14, v6, vcc_lo
	global_load_b32 v7, v[5:6], off
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[14:15], v7
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_nlt_f64_e32 s[8:9], v[14:15]
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	global_load_b32 v5, v[5:6], off offset:4
	v_and_b32_e32 v6, 0x7fffffff, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v15, null, s7, s7, v6
	v_rcp_f32_e32 v17, v15
	s_waitcnt_depctr 0xfff
	v_fma_f32 v19, -v15, v17, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v19, v17
	v_div_scale_f32 v6, vcc_lo, v6, s7, v6
	v_mul_f32_e32 v19, v6, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v21, -v15, v19, v6
	v_fmac_f32_e32 v19, v21, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, -v15, v19, v6
	v_div_fmas_f32 v6, v6, v17, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v6, v6, s7, |v7|
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v14, 0x7fffffff, v5
	v_div_scale_f32 v16, null, s7, s7, v14
	v_div_scale_f32 v14, s0, v14, s7, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_mov_b32 vcc_lo, s0
	v_rcp_f32_e32 v18, v16
	s_waitcnt_depctr 0xfff
	v_fma_f32 v20, -v16, v18, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, v20, v18
	v_mul_f32_e32 v20, v14, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v22, -v16, v20, v14
	v_fmac_f32_e32 v20, v22, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, -v16, v20, v14
	v_div_fmas_f32 v14, v14, v18, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v7, v14, s7, |v5|
	v_cvt_f64_f32_e32 v[5:6], v6
	v_cvt_f64_f32_e32 v[14:15], v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[5:6], 0.5
	v_add_f64 v[14:15], v[14:15], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v5, v[5:6]
	v_cvt_i32_f64_e32 v6, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, v6, v5
	v_cmp_eq_u32_e64 s0, 1, v6
	v_cmp_lt_i32_e32 vcc_lo, 1, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, v6, v5, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 1, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_min_i32_e32 v5, 5, v7
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e64 v5, v5, 2, s0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 1, v5
	v_cmp_eq_u32_e64 s0, 2, v5
	v_cmp_eq_u32_e64 s1, 3, v5
	v_cmp_eq_u32_e64 s2, 4, v5
	v_cmp_eq_u32_e64 s3, 5, v5
	v_cndmask_b32_e32 v6, v12, v13, vcc_lo
	v_cmp_eq_u32_e64 s4, 0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v6, v6, v11, s0
	v_cndmask_b32_e64 v6, v6, v10, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v6, v6, v9, s2
	v_cndmask_b32_e64 v6, v6, v8, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, 1, v6
	v_cndmask_b32_e64 v12, v12, v6, s4
	v_cndmask_b32_e32 v13, v13, v6, vcc_lo
	v_cndmask_b32_e64 v11, v11, v6, s0
	v_cndmask_b32_e64 v10, v10, v6, s1
	v_cndmask_b32_e64 v9, v9, v6, s2
	v_cndmask_b32_e64 v8, v8, v6, s3
.LBB0_5:                                ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
	v_add_co_u32 v3, vcc_lo, v3, 4
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_add_i32 s18, s18, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s18, 0
	s_cbranch_scc0 .LBB0_3
.LBB0_6:                                ; %.preheader142
	s_mul_i32 s0, s5, 6
	s_mul_i32 s2, s15, s10
	v_mul_lo_u32 v2, s0, v2
	s_add_i32 s0, s2, s10
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_min_i32 s4, s0, s5
	s_mov_b32 s12, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_cbranch_vccnz .LBB0_13
; %bb.7:                                ; %.lr.ph149
	s_mul_i32 s8, s11, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_ashr_i32 s9, s8, 31
	s_cmp_lt_i32 s2, s4
	s_cselect_b32 s1, -1, 0
	s_ashr_i32 s3, s2, 31
	s_lshl_b64 s[8:9], s[8:9], 2
	s_lshl_b64 s[10:11], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s8, s10
	s_addc_u32 s8, s9, s11
	s_add_u32 s3, s16, s0
	s_addc_u32 s15, s17, s8
	s_add_u32 s0, s22, s10
	s_addc_u32 s8, s23, s11
	v_add_co_u32 v14, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v15, vcc_lo, s8, v3, vcc_lo
	s_mov_b32 s11, 0
	s_mov_b32 s8, 0x78b58c40
	s_mov_b32 s9, 0x4415af1d
	s_mov_b32 s10, s11
.LBB0_8:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_11 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[16:17], s[10:11], 2
	v_add_co_u32 v4, vcc_lo, v0, s16
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v1, vcc_lo
	s_mov_b32 s16, exec_lo
	global_load_b32 v6, v[4:5], off
	s_waitcnt vmcnt(0)
	v_lshlrev_b32_e32 v4, 1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s13, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s14, v5, vcc_lo
	global_load_b32 v7, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[16:17], v7
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_nlt_f64_e32 s[8:9], v[16:17]
	s_cbranch_execz .LBB0_12
; %bb.9:                                ;   in Loop: Header=BB0_8 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_12
; %bb.10:                               ; %.lr.ph147
                                        ;   in Loop: Header=BB0_8 Depth=1
	global_load_b32 v4, v[4:5], off offset:4
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v16, 0x7fffffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v18, null, s7, s7, v16
	v_rcp_f32_e32 v20, v18
	s_waitcnt_depctr 0xfff
	v_fma_f32 v22, -v18, v20, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v20, v22, v20 :: v_dual_and_b32 v5, 0x7fffffff, v7
	v_div_scale_f32 v17, null, s7, s7, v5
	v_div_scale_f32 v5, vcc_lo, v5, s7, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v19, v17
	s_waitcnt_depctr 0xfff
	v_fma_f32 v21, -v17, v19, 1.0
	v_fmac_f32_e32 v19, v21, v19
	v_div_scale_f32 v16, s0, v16, s7, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v21, v5, v19 :: v_dual_mul_f32 v22, v16, v20
	v_fma_f32 v23, -v17, v21, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v24, -v18, v22, v16
	v_dual_fmac_f32 v21, v23, v19 :: v_dual_fmac_f32 v22, v24, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v5, -v17, v21, v5
	v_fma_f32 v16, -v18, v22, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v5, v5, v19, v21
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f32 v16, v16, v20, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v5, v5, s7, |v7|
	v_div_fixup_f32 v7, v16, s7, |v4|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[4:5], v5
	v_cvt_f64_f32_e32 v[16:17], v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], 0.5
	v_add_f64 v[16:17], v[16:17], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v4, v[4:5]
	v_cvt_i32_f64_e32 v5, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, v5, v4
	v_cmp_eq_u32_e64 s0, 1, v5
	v_cmp_lt_i32_e32 vcc_lo, 1, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, v5, v4, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 1, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_min_i32_e32 v4, 5, v7
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e64 v16, v4, 2, s0
	v_mul_lo_u32 v4, v6, s5
	s_mov_b32 s0, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 1, v16
	v_mul_lo_u32 v6, v16, s5
	v_cndmask_b32_e32 v5, v12, v13, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 2, v16
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v5, v5, v11, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 3, v16
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v17, v5, v10, vcc_lo
	v_ashrrev_i32_e32 v5, 31, v4
	v_cmp_eq_u32_e32 vcc_lo, 4, v16
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v17, v17, v9, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 5, v16
	v_cndmask_b32_e32 v16, v17, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s3, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s15, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, v14, v6
	v_cvt_f32_i32_e32 v16, v16
	v_add_co_ci_u32_e32 v7, vcc_lo, v15, v7, vcc_lo
.LBB0_11:                               ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v17, v[4:5], off
	global_load_b32 v18, v[6:7], off
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_cmp_lt_i32 s0, s4
	s_waitcnt vmcnt(1)
	v_div_scale_f32 v19, null, v16, v16, v17
	v_div_scale_f32 v21, vcc_lo, v17, v16, v17
	v_rcp_f32_e32 v20, v19
	s_waitcnt_depctr 0xfff
	v_fma_f32 v22, -v19, v20, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v20, v22, v20
	v_mul_f32_e32 v22, v21, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v23, -v19, v22, v21
	v_fmac_f32_e32 v22, v23, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v19, -v19, v22, v21
	v_div_fmas_f32 v19, v19, v20, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v17, v19, v16, v17
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v17, v18, v17
	global_store_b32 v[6:7], v17, off
	v_add_co_u32 v6, vcc_lo, v6, 4
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_cbranch_scc1 .LBB0_11
.LBB0_12:                               ; %.loopexit141
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_add_i32 s10, s10, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s10, s6
	s_cbranch_scc0 .LBB0_8
.LBB0_13:                               ; %.preheader139
	s_cmp_lt_i32 s2, s4
	s_mov_b32 s6, 0
	s_cselect_b32 s10, -1, 0
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 2
	s_add_u32 s0, s22, s0
	s_addc_u32 s1, s23, s1
	v_add_co_u32 v6, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo
	s_mov_b64 s[0:1], 0
.LBB0_14:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_16 Depth 2
                                        ;     Child Loop BB0_18 Depth 2
                                        ;     Child Loop BB0_25 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 1
	s_mov_b32 s3, exec_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 2
	v_cndmask_b32_e32 v0, v12, v13, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v11, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 4
	v_cndmask_b32_e32 v0, v0, v10, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v9, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e32 v0, v0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_26
; %bb.15:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_mov_b32 s8, 0
	s_mov_b32 s9, s12
                                        ; implicit-def: $sgpr7
.LBB0_16:                               ; %.preheader
                                        ;   Parent Loop BB0_14 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s9, s9, -1
	s_cmp_gt_i32 s9, -1
	v_mov_b32_e32 v2, s9
	s_cselect_b32 s11, -1, 0
	s_cmp_lt_i32 s9, 0
	s_cselect_b32 s13, -1, 0
	s_cmp_eq_u32 s9, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s9, 2
	v_cndmask_b32_e32 v0, v12, v13, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s9, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v11, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s9, 4
	v_cndmask_b32_e32 v0, v0, v10, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s9, 5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v9, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e32 v0, v0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
	s_or_b32 s13, s13, vcc_lo
	s_and_b32 s13, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s8, s13, s8
	s_and_not1_b32 s7, s7, exec_lo
	s_and_b32 s11, s11, exec_lo
	s_or_b32 s7, s7, s11
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB0_16
; %bb.17:                               ; %.critedge.preheader
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	s_mov_b32 s11, 0
	s_mov_b64 s[8:9], s[0:1]
                                        ; implicit-def: $sgpr13
.LBB0_18:                               ; %.critedge
                                        ;   Parent Loop BB0_14 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_u32 s8, 6
	s_cselect_b32 s14, -1, 0
	s_cmp_gt_u32 s8, 5
	s_cselect_b32 s15, -1, 0
	s_cmp_eq_u32 s8, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s8, 2
	v_cndmask_b32_e32 v0, v12, v13, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s8, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v11, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s8, 4
	v_cndmask_b32_e32 v0, v0, v10, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s8, 5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v9, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e32 v0, v0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
	s_or_b32 s15, s15, vcc_lo
	s_add_u32 s8, s8, 1
	s_addc_u32 s9, s9, 0
	s_and_b32 s15, exec_lo, s15
	v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
	s_or_b32 s11, s15, s11
	s_and_not1_b32 s13, s13, exec_lo
	s_and_b32 s14, s14, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s13, s13, s14
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_18
; %bb.19:                               ; %.critedge2
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	v_add_nc_u32_e32 v0, -1, v0
	s_and_b32 s8, s7, s13
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s8, s8, -1
	s_and_saveexec_b32 s9, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s8, exec_lo, s9
; %bb.20:                               ;   in Loop: Header=BB0_14 Depth=1
	v_cndmask_b32_e64 v1, 0, v2, s7
	v_cndmask_b32_e64 v0, v0, 5, s7
	v_cndmask_b32_e64 v15, 0, 1.0, s7
	v_cndmask_b32_e64 v14, 1.0, 0, s7
; %bb.21:                               ; %Flow251
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_and_not1_saveexec_b32 s7, s8
	s_cbranch_execz .LBB0_23
; %bb.22:                               ;   in Loop: Header=BB0_14 Depth=1
	v_sub_nc_u32_e32 v1, s0, v2
	v_sub_nc_u32_e32 v3, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v1, v1
	v_cvt_f32_i32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v4, null, v3, v3, v1
	v_div_scale_f32 v15, vcc_lo, v1, v3, v1
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v14, -v4, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v14, v5
	v_mul_f32_e32 v14, v15, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v16, -v4, v14, v15
	v_fmac_f32_e32 v14, v16, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, -v4, v14, v15
	v_div_fmas_f32 v4, v4, v5, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v14, v4, v3, v1
	v_mov_b32_e32 v1, v2
	v_sub_f32_e32 v15, 1.0, v14
.LBB0_23:                               ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_26
; %bb.24:                               ; %.lr.ph151.preheader
                                        ;   in Loop: Header=BB0_14 Depth=1
	v_mul_lo_u32 v1, v1, s5
	v_mul_lo_u32 v3, v0, s5
	s_ashr_i32 s7, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	s_lshl_b64 s[8:9], s[6:7], 2
	s_mov_b32 s7, s2
	v_add_co_u32 v0, vcc_lo, v6, s8
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[16:17], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[4:5], 2, v[3:4]
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v7, vcc_lo
	v_add_co_u32 v2, vcc_lo, v6, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, v7, v17, vcc_lo
	v_add_co_u32 v4, vcc_lo, v6, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, v7, v5, vcc_lo
.LBB0_25:                               ; %.lr.ph151
                                        ;   Parent Loop BB0_14 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v16, v[4:5], off
	global_load_b32 v17, v[2:3], off
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_add_i32 s7, s7, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_cmp_lt_i32 s7, s4
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v16, v14, v16
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v16, v15, v17
	global_store_b32 v[0:1], v16, off
	v_add_co_u32 v0, vcc_lo, v0, 4
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_cbranch_scc1 .LBB0_25
.LBB0_26:                               ; %Flow252
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_add_i32 s12, s12, 1
	s_add_i32 s6, s6, s5
	s_cmp_lg_u32 s0, 6
	s_cbranch_scc1 .LBB0_14
.LBB0_27:                               ; %.loopexit140
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11five_kerneliiiiiiPKfS0_PKiPff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 25
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11five_kerneliiiiiiPKfS0_PKiPff, .Lfunc_end0-_Z11five_kerneliiiiiiPKfS0_PKiPff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2612
; NumSgprs: 26
; NumVgprs: 25
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 25
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff ; -- Begin function _Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff
	.globl	_Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff
	.p2align	8
	.type	_Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff,@function
_Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff: ; @_Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x54
	s_load_b128 s[16:19], s[0:1], 0x4
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s13, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s19, v1
	s_cbranch_execz .LBB1_39
; %bb.1:
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u64_u32 v[14:15], null, s14, s19, v[1:2]
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x20
	s_load_b32 s12, s[0:1], 0x14
	s_mul_i32 s13, s14, s16
	s_load_b32 s16, s[0:1], 0x40
	s_lshl_b32 s2, s13, 1
	v_mov_b32_e32 v26, 0
	v_mul_lo_u32 v0, v14, s18
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v29, v26
	v_mov_b32_e32 v28, v26
	v_mov_b32_e32 v27, v26
	v_mov_b32_e32 v31, v26
	v_ashrrev_i32_e32 v1, 31, v0
	v_mov_b32_e32 v30, v26
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_add_u32 s19, s4, s0
	s_addc_u32 s20, s5, s1
	s_cmp_gt_i32 s18, 0
	s_cselect_b32 s5, -1, 0
	v_add_co_u32 v12, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v13, vcc_lo, s7, v1, vcc_lo
	s_cmp_lt_i32 s18, 1
	s_cbranch_scc1 .LBB1_6
; %bb.2:                                ; %.lr.ph.preheader
	v_mov_b32_e32 v30, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v0, v12 :: v_dual_mov_b32 v1, v13
	s_mov_b32 s6, 0x78b58c40
	s_mov_b32 s7, 0x4415af1d
	v_mov_b32_e32 v31, v30
	v_mov_b32_e32 v27, v30
	v_mov_b32_e32 v28, v30
	v_mov_b32_e32 v29, v30
	v_mov_b32_e32 v26, v30
	s_mov_b32 s14, s18
.LBB1_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v2, v[0:1], off
	s_mov_b32 s21, exec_lo
	s_waitcnt vmcnt(0)
	v_lshlrev_b32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s19, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s20, v3, vcc_lo
	global_load_b32 v4, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[5:6], v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_nlt_f64_e32 s[6:7], v[5:6]
	s_cbranch_execz .LBB1_5
; %bb.4:                                ;   in Loop: Header=BB1_3 Depth=1
	global_load_b32 v2, v[2:3], off offset:4
	v_and_b32_e32 v3, 0x7fffffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v6, null, s16, s16, v3
	v_div_scale_f32 v3, vcc_lo, v3, s16, v3
	v_rcp_f32_e32 v8, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v10, -v6, v8, 1.0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v8, v10, v8 :: v_dual_and_b32 v5, 0x7fffffff, v2
	v_div_scale_f32 v7, null, s16, s16, v5
	v_div_scale_f32 v5, s0, v5, s16, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v9, v7
	s_waitcnt_depctr 0xfff
	v_fma_f32 v11, -v7, v9, 1.0
	v_fmac_f32_e32 v9, v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v10, v3, v8 :: v_dual_mul_f32 v11, v5, v9
	v_fma_f32 v15, -v6, v10, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v16, -v7, v11, v5
	v_dual_fmac_f32 v10, v15, v8 :: v_dual_fmac_f32 v11, v16, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v3, -v6, v10, v3
	v_fma_f32 v5, -v7, v11, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v3, v3, v8, v10
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f32 v5, v5, v9, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v3, v3, s16, |v4|
	v_div_fixup_f32 v4, v5, s16, |v2|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[2:3], v3
	v_cvt_f64_f32_e32 v[4:5], v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[2:3], v[2:3], 0.5
	v_add_f64 v[4:5], v[4:5], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v2, v[2:3]
	v_cvt_i32_f64_e32 v3, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v3, v2
	v_cmp_eq_u32_e64 s0, 1, v3
	v_cmp_lt_i32_e32 vcc_lo, 1, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, v3, v2, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 1, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_min_i32_e32 v2, 5, v4
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e64 v2, v2, 2, s0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 1, v2
	v_cmp_eq_u32_e64 s0, 2, v2
	v_cmp_eq_u32_e64 s1, 3, v2
	v_cmp_eq_u32_e64 s2, 4, v2
	v_cmp_eq_u32_e64 s3, 5, v2
	v_cndmask_b32_e32 v3, v30, v31, vcc_lo
	v_cmp_eq_u32_e64 s4, 0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v3, v27, s0
	v_cndmask_b32_e64 v3, v3, v28, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v3, v29, s2
	v_cndmask_b32_e64 v3, v3, v26, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, 1, v3
	v_cndmask_b32_e64 v30, v30, v3, s4
	v_cndmask_b32_e32 v31, v31, v3, vcc_lo
	v_cndmask_b32_e64 v27, v27, v3, s0
	v_cndmask_b32_e64 v28, v28, v3, s1
	v_cndmask_b32_e64 v29, v29, v3, s2
	v_cndmask_b32_e64 v26, v26, v3, s3
.LBB1_5:                                ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	v_add_co_u32 v0, vcc_lo, v0, 4
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_add_i32 s14, s14, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc0 .LBB1_3
.LBB1_6:                                ; %Flow298
	s_mov_b32 s24, 0
	s_mov_b32 s14, 1
	s_mov_b32 s28, s24
	s_mov_b32 s29, s24
	s_mov_b32 s25, s24
	s_mov_b32 s26, s24
	s_mov_b32 s27, s24
	v_dual_mov_b32 v0, s24 :: v_dual_mov_b32 v1, s25
	v_dual_mov_b32 v4, s28 :: v_dual_mov_b32 v5, s29
	v_dual_mov_b32 v2, s26 :: v_dual_mov_b32 v3, s27
	s_mov_b64 s[6:7], 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v11, v5 :: v_dual_mov_b32 v10, v4
	v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
	v_dual_mov_b32 v7, v1 :: v_dual_mov_b32 v6, v0
.LBB1_7:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_9 Depth 2
                                        ;     Child Loop BB1_11 Depth 2
	s_cmp_eq_u32 s6, 1
	s_mov_b32 s21, exec_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 2
	v_cndmask_b32_e32 v15, v30, v31, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v15, v15, v27, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 4
	v_cndmask_b32_e32 v15, v15, v28, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v15, v15, v29, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e32 v15, v15, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v15
	s_cbranch_execz .LBB1_17
; %bb.8:                                ; %.preheader161.preheader
                                        ;   in Loop: Header=BB1_7 Depth=1
	s_mov_b32 s0, 0
	s_mov_b32 s1, s14
                                        ; implicit-def: $sgpr2
.LBB1_9:                                ; %.preheader161
                                        ;   Parent Loop BB1_7 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s1, s1, -1
	s_cmp_gt_i32 s1, -1
	v_mov_b32_e32 v17, s1
	s_cselect_b32 s3, -1, 0
	s_cmp_lt_i32 s1, 0
	s_cselect_b32 s4, -1, 0
	s_cmp_eq_u32 s1, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 2
	v_cndmask_b32_e32 v15, v30, v31, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v15, v15, v27, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 4
	v_cndmask_b32_e32 v15, v15, v28, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v15, v15, v29, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e32 v15, v15, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v15
	s_or_b32 s4, s4, vcc_lo
	s_and_b32 s4, exec_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s4, s0
	s_and_not1_b32 s2, s2, exec_lo
	s_and_b32 s3, s3, exec_lo
	s_or_b32 s2, s2, s3
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_9
; %bb.10:                               ; %.critedge.preheader
                                        ;   in Loop: Header=BB1_7 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b64 s[0:1], s[6:7]
                                        ; implicit-def: $sgpr4
.LBB1_11:                               ; %.critedge
                                        ;   Parent Loop BB1_7 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_u32 s0, 6
	s_cselect_b32 s22, -1, 0
	s_cmp_gt_u32 s0, 5
	s_cselect_b32 s23, -1, 0
	s_cmp_eq_u32 s0, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 2
	v_cndmask_b32_e32 v15, v30, v31, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v15, v15, v27, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 4
	v_cndmask_b32_e32 v15, v15, v28, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v15, v15, v29, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e32 v15, v15, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v15
	s_or_b32 s23, s23, vcc_lo
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_and_b32 s23, exec_lo, s23
	v_dual_mov_b32 v16, s1 :: v_dual_mov_b32 v15, s0
	s_or_b32 s3, s23, s3
	s_and_not1_b32 s4, s4, exec_lo
	s_and_b32 s22, s22, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s4, s4, s22
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_11
; %bb.12:                               ; %.critedge2
                                        ;   in Loop: Header=BB1_7 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_and_b32 s0, s2, s4
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr18
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s0, s0, -1
	s_and_saveexec_b32 s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s1
; %bb.13:                               ;   in Loop: Header=BB1_7 Depth=1
	v_cndmask_b32_e64 v18, 0, 1.0, s2
	v_cndmask_b32_e64 v16, 1.0, 0, s2
; %bb.14:                               ; %Flow295
                                        ;   in Loop: Header=BB1_7 Depth=1
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB1_16
; %bb.15:                               ;   in Loop: Header=BB1_7 Depth=1
	v_sub_nc_u32_e32 v16, s6, v17
	v_xad_u32 v15, v17, -1, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v16, v16
	v_cvt_f32_i32_e32 v15, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v17, null, v15, v15, v16
	v_rcp_f32_e32 v18, v17
	s_waitcnt_depctr 0xfff
	v_fma_f32 v19, -v17, v18, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, v19, v18
	v_div_scale_f32 v19, vcc_lo, v16, v15, v16
	v_mul_f32_e32 v20, v19, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v21, -v17, v20, v19
	v_fmac_f32_e32 v20, v21, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v17, -v17, v20, v19
	v_div_fmas_f32 v17, v17, v18, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v16, v17, v15, v16
	v_sub_f32_e32 v18, 1.0, v16
.LBB1_16:                               ;   in Loop: Header=BB1_7 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_cmp_eq_u32 s6, 5
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 4
	v_cndmask_b32_e32 v5, v5, v18, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s6, 3
	v_cndmask_b32_e64 v4, v4, v18, s0
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s6, 2
	v_cndmask_b32_e64 v3, v3, v18, s1
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s6, 1
	v_cndmask_b32_e64 v2, v2, v18, s2
	s_cselect_b32 s3, -1, 0
	s_cmp_eq_u32 s6, 0
	v_cndmask_b32_e64 v1, v1, v18, s3
	s_cselect_b32 s4, -1, 0
	v_cndmask_b32_e32 v11, v11, v16, vcc_lo
	v_cndmask_b32_e64 v0, v0, v18, s4
	v_cndmask_b32_e64 v10, v10, v16, s0
	v_cndmask_b32_e64 v9, v9, v16, s1
	v_cndmask_b32_e64 v8, v8, v16, s2
	v_cndmask_b32_e64 v7, v7, v16, s3
	v_cndmask_b32_e64 v6, v6, v16, s4
.LBB1_17:                               ; %Flow296
                                        ;   in Loop: Header=BB1_7 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	s_add_u32 s6, s6, 1
	s_addc_u32 s7, s7, 0
	s_add_i32 s14, s14, 1
	s_cmp_eq_u32 s6, 6
	s_cbranch_scc0 .LBB1_7
; %bb.18:                               ; %.preheader
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB1_39
; %bb.19:                               ; %.lr.ph191
	s_mul_i32 s0, s17, 6
	s_mul_i32 s4, s15, s12
	v_mul_lo_u32 v14, s0, v14
	s_mul_i32 s0, s13, s17
	s_add_i32 s2, s4, s12
	s_ashr_i32 s1, s0, 31
	s_min_i32 s3, s2, s17
	s_lshl_b64 s[0:1], s[0:1], 2
	s_mov_b32 s6, s17
	s_add_u32 s21, s10, s0
	v_ashrrev_i32_e32 v15, 31, v14
	s_addc_u32 s22, s11, s1
	s_cmp_lt_i32 s4, s3
	s_mov_b32 s11, 0
	s_cselect_b32 s23, -1, 0
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	s_ashr_i32 s5, s4, 31
	s_ashr_i32 s7, s17, 31
	s_lshl_b64 s[0:1], s[4:5], 2
	s_lshl_b64 s[6:7], s[6:7], 2
	s_mov_b32 s10, s11
	v_add_co_u32 v16, vcc_lo, v14, s0
	v_add_co_ci_u32_e32 v17, vcc_lo, s1, v15, vcc_lo
	s_sub_u32 s5, 0, s6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v16, vcc_lo, v16, s6
	v_subrev_co_ci_u32_e32 v17, vcc_lo, s7, v17, vcc_lo
	v_add_co_u32 v32, vcc_lo, s8, v14
	s_subb_u32 s24, 0, s7
	v_add_co_ci_u32_e32 v33, vcc_lo, s9, v15, vcc_lo
	s_add_u32 s0, s8, s0
	v_add_co_u32 v34, vcc_lo, s8, v16
	s_addc_u32 s1, s9, s1
	s_add_u32 s0, s0, s6
	v_add_co_ci_u32_e32 v35, vcc_lo, s9, v17, vcc_lo
	s_addc_u32 s1, s1, s7
	v_add_co_u32 v36, vcc_lo, s0, v14
	v_add_co_ci_u32_e32 v37, vcc_lo, s1, v15, vcc_lo
	v_mov_b32_e32 v15, 0
	s_mov_b32 s8, 0x78b58c40
	s_mov_b32 s9, 0x4415af1d
.LBB1_20:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_23 Depth 2
                                        ;       Child Loop BB1_25 Depth 3
                                        ;       Child Loop BB1_31 Depth 3
                                        ;       Child Loop BB1_36 Depth 3
	s_lshl_b64 s[0:1], s[10:11], 2
	s_mov_b32 s25, exec_lo
	v_add_co_u32 v16, vcc_lo, v12, s0
	v_add_co_ci_u32_e32 v17, vcc_lo, s1, v13, vcc_lo
	global_load_b32 v14, v[16:17], off
	s_waitcnt vmcnt(0)
	v_lshlrev_b32_e32 v16, 1, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v17, 31, v16
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v16, vcc_lo, s19, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s20, v17, vcc_lo
	global_load_b32 v18, v[16:17], off
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[19:20], v18
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_nlt_f64_e32 s[8:9], v[19:20]
	s_cbranch_execz .LBB1_38
; %bb.21:                               ;   in Loop: Header=BB1_20 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s23
	s_cbranch_vccnz .LBB1_38
; %bb.22:                               ; %.lr.ph189
                                        ;   in Loop: Header=BB1_20 Depth=1
	global_load_b32 v16, v[16:17], off offset:4
	v_and_b32_e32 v17, 0x7fffffff, v18
	s_mov_b32 s12, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v20, null, s16, s16, v17
	v_div_scale_f32 v17, vcc_lo, v17, s16, v17
	v_rcp_f32_e32 v22, v20
	s_waitcnt_depctr 0xfff
	v_fma_f32 v24, -v20, v22, 1.0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v22, v24, v22 :: v_dual_and_b32 v19, 0x7fffffff, v16
	v_div_scale_f32 v21, null, s16, s16, v19
	v_div_scale_f32 v19, s0, v19, s16, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v24, v17, v22
	v_rcp_f32_e32 v23, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v38, -v20, v24, v17
	v_fmac_f32_e32 v24, v38, v22
	s_waitcnt_depctr 0xfff
	v_fma_f32 v25, -v21, v23, 1.0
	v_fma_f32 v17, -v20, v24, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v23, v25, v23
	v_div_fmas_f32 v17, v17, v22, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v25, v19, v23
	s_mov_b32 vcc_lo, s0
	v_div_fixup_f32 v17, v17, s16, |v18|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v39, -v21, v25, v19
	v_fmac_f32_e32 v25, v39, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v19, -v21, v25, v19
	v_div_fmas_f32 v19, v19, v23, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v18, v19, s16, |v16|
	v_cvt_f64_f32_e32 v[16:17], v17
	v_cvt_f64_f32_e32 v[18:19], v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[16:17], 0.5
	v_add_f64 v[18:19], v[18:19], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cvt_i32_f64_e32 v20, v[16:17]
	v_mul_lo_u32 v16, v14, s17
	v_cvt_i32_f64_e32 v18, v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v17, 31, v16
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v14, v18, v20
	v_cmp_eq_u32_e64 s0, 1, v18
	v_cmp_lt_i32_e32 vcc_lo, 1, v14
	v_add_co_ci_u32_e32 v14, vcc_lo, v18, v20, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 1, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_min_i32_e32 v14, 5, v14
	s_and_b32 s0, vcc_lo, s0
	v_add_co_u32 v38, vcc_lo, s21, v16
	v_cndmask_b32_e64 v18, v14, 2, s0
	v_add_co_ci_u32_e32 v39, vcc_lo, s22, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_eq_u32_e32 vcc_lo, 1, v18
	v_mul_lo_u32 v16, v18, s17
	v_ashrrev_i32_e32 v19, 31, v18
	v_cmp_lt_i32_e64 s0, 0, v18
	v_cmp_gt_i32_e64 s1, 5, v18
	v_cndmask_b32_e32 v14, v30, v31, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 2, v18
	v_ashrrev_i32_e32 v17, 31, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v20, v14, v27, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 3, v18
	v_add_nc_u32_e32 v14, -1, v18
	v_cndmask_b32_e32 v22, v20, v28, vcc_lo
	v_lshlrev_b64 v[20:21], 2, v[16:17]
	v_add_co_u32 v16, vcc_lo, v18, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v19, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 4, v18
	v_dual_cndmask_b32 v19, v22, v29 :: v_dual_add_nc_u32 v40, 1, v18
	v_add_co_u32 v41, vcc_lo, v32, v20
	v_add_co_ci_u32_e32 v42, vcc_lo, v33, v21, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 5, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v22, v19, v26, vcc_lo
	v_add_co_u32 v18, vcc_lo, v34, v20
	v_add_co_ci_u32_e32 v19, vcc_lo, v35, v21, vcc_lo
	v_add_co_u32 v20, vcc_lo, v36, v20
	v_cvt_f32_i32_e32 v43, v22
	v_add_co_ci_u32_e32 v21, vcc_lo, v37, v21, vcc_lo
.LBB1_23:                               ;   Parent Loop BB1_20 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_25 Depth 3
                                        ;       Child Loop BB1_31 Depth 3
                                        ;       Child Loop BB1_36 Depth 3
	s_ashr_i32 s13, s12, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[14:15], s[12:13], 2
	v_add_co_u32 v22, vcc_lo, v41, s14
	v_add_co_ci_u32_e32 v23, vcc_lo, s15, v42, vcc_lo
	global_load_b32 v44, v[22:23], off
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB1_29
; %bb.24:                               ; %.lr.ph175.preheader
                                        ;   in Loop: Header=BB1_23 Depth=2
	v_mov_b32_e32 v25, v19
	v_dual_mov_b32 v23, v15 :: v_dual_mov_b32 v22, v14
	v_dual_mov_b32 v45, v40 :: v_dual_mov_b32 v24, v18
	s_mov_b32 s26, 0
                                        ; implicit-def: $sgpr27
.LBB1_25:                               ; %.lr.ph175
                                        ;   Parent Loop BB1_20 Depth=1
                                        ;     Parent Loop BB1_23 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e32 vcc_lo, 1, v22
	s_or_b32 s27, s27, exec_lo
	s_mov_b32 s28, exec_lo
	v_cndmask_b32_e32 v46, v30, v31, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 2, v22
	v_cndmask_b32_e32 v46, v46, v27, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 3, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v46, v46, v28, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 4, v22
	v_cndmask_b32_e32 v46, v46, v29, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 5, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v46, v46, v26, vcc_lo
	v_cmpx_eq_u32_e32 0, v46
	s_cbranch_execz .LBB1_27
; %bb.26:                               ;   in Loop: Header=BB1_25 Depth=3
	global_load_b32 v46, v[24:25], off
	v_cmp_eq_u32_e32 vcc_lo, 1, v22
	v_cmp_eq_u32_e64 s2, 5, v22
	v_cndmask_b32_e32 v47, v6, v7, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 2, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v47, v47, v8, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 3, v22
	v_cndmask_b32_e32 v47, v47, v9, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 4, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v47, v47, v10, vcc_lo
	v_add_co_u32 v24, vcc_lo, v24, s5
	v_add_co_ci_u32_e32 v25, vcc_lo, s24, v25, vcc_lo
	v_cndmask_b32_e64 v47, v47, v11, s2
	v_add_nc_u32_e32 v45, -1, v45
	v_add_co_u32 v22, s2, v22, -1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v23, s2, -1, v23, s2
	s_and_not1_b32 s2, s27, exec_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v44, v47, v46
	v_cmp_gt_u32_e32 vcc_lo, 2, v45
	s_and_b32 s27, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s27, s2, s27
.LBB1_27:                               ; %Flow288
                                        ;   in Loop: Header=BB1_25 Depth=3
	s_or_b32 exec_lo, exec_lo, s28
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, exec_lo, s27
	s_or_b32 s26, s2, s26
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s26
	s_cbranch_execnz .LBB1_25
; %bb.28:                               ; %Flow289
                                        ;   in Loop: Header=BB1_23 Depth=2
	s_or_b32 exec_lo, exec_lo, s26
.LBB1_29:                               ; %Flow290
                                        ;   in Loop: Header=BB1_23 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s13
	s_and_saveexec_b32 s13, s1
	s_cbranch_execz .LBB1_35
; %bb.30:                               ; %.lr.ph184.preheader
                                        ;   in Loop: Header=BB1_23 Depth=2
	v_dual_mov_b32 v23, v21 :: v_dual_mov_b32 v22, v20
	v_dual_mov_b32 v25, v17 :: v_dual_mov_b32 v24, v16
	s_mov_b32 s26, 0
                                        ; implicit-def: $sgpr27
.LBB1_31:                               ; %.lr.ph184
                                        ;   Parent Loop BB1_20 Depth=1
                                        ;     Parent Loop BB1_23 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e32 vcc_lo, 1, v24
	s_or_b32 s27, s27, exec_lo
	s_mov_b32 s28, exec_lo
	v_cndmask_b32_e32 v45, v30, v31, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 2, v24
	v_cndmask_b32_e32 v45, v45, v27, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 3, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v45, v45, v28, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 4, v24
	v_cndmask_b32_e32 v45, v45, v29, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 5, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v45, v45, v26, vcc_lo
	v_cmpx_eq_u32_e32 0, v45
	s_cbranch_execz .LBB1_33
; %bb.32:                               ;   in Loop: Header=BB1_31 Depth=3
	global_load_b32 v45, v[22:23], off
	v_cmp_eq_u32_e32 vcc_lo, 1, v24
	v_cndmask_b32_e32 v46, v0, v1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 2, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v46, v46, v2, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 3, v24
	v_cndmask_b32_e32 v46, v46, v3, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 4, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v46, v46, v4, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 5, v24
	v_add_co_u32 v24, s2, v24, 1
	v_add_co_ci_u32_e64 v25, s2, 0, v25, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v46, v46, v5 :: v_dual_add_nc_u32 v47, -2, v24
	v_add_co_u32 v22, s2, v22, s6
	v_add_co_ci_u32_e64 v23, s2, s7, v23, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_lt_i32_e32 vcc_lo, 3, v47
	s_and_not1_b32 s2, s27, exec_lo
	s_and_b32 s27, vcc_lo, exec_lo
	s_or_b32 s27, s2, s27
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v44, v46, v45
.LBB1_33:                               ; %Flow
                                        ;   in Loop: Header=BB1_31 Depth=3
	s_or_b32 exec_lo, exec_lo, s28
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, exec_lo, s27
	s_or_b32 s26, s2, s26
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s26
	s_cbranch_execnz .LBB1_31
; %bb.34:                               ; %Flow286
                                        ;   in Loop: Header=BB1_23 Depth=2
	s_or_b32 exec_lo, exec_lo, s26
.LBB1_35:                               ; %Flow287
                                        ;   in Loop: Header=BB1_23 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s13
	v_add_co_u32 v22, vcc_lo, v38, s14
	v_add_co_ci_u32_e32 v23, vcc_lo, s15, v39, vcc_lo
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v24, null, v43, v43, v44
	s_mov_b32 s2, 0
	global_load_b32 v25, v[22:23], off
	v_rcp_f32_e32 v45, v24
	s_waitcnt_depctr 0xfff
	v_fma_f32 v46, -v24, v45, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v45, v46, v45
	v_div_scale_f32 v46, vcc_lo, v44, v43, v44
	v_mul_f32_e32 v47, v46, v45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v48, -v24, v47, v46
	v_fmac_f32_e32 v47, v48, v45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v24, -v24, v47, v46
	v_div_fmas_f32 v24, v24, v45, v47
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v44, v24, v43, v44
.LBB1_36:                               ; %atomicrmw.start
                                        ;   Parent Loop BB1_20 Depth=1
                                        ;     Parent Loop BB1_23 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v24, v25, v44
	global_atomic_cmpswap_b32 v24, v[22:23], v[24:25], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v24, v25
	v_mov_b32_e32 v25, v24
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB1_36
; %bb.37:                               ; %atomicrmw.end
                                        ;   in Loop: Header=BB1_23 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
	v_add_co_u32 v18, vcc_lo, v18, 4
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v19, vcc_lo
	v_add_co_u32 v20, vcc_lo, v20, 4
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v21, vcc_lo
	s_add_i32 s12, s12, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s12, s3
	s_cbranch_scc1 .LBB1_23
.LBB1_38:                               ; %.loopexit
                                        ;   in Loop: Header=BB1_20 Depth=1
	s_or_b32 exec_lo, exec_lo, s25
	s_add_i32 s10, s10, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s10, s18
	s_cbranch_scc1 .LBB1_20
.LBB1_39:                               ; %.loopexit160
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 49
		.amdhsa_next_free_sgpr 30
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff, .Lfunc_end1-_Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3256
; NumSgprs: 32
; NumVgprs: 49
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 32
; NumVGPRsForWavesPerEU: 49
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11five_kerneliiiiiiPKfS0_PKiPff
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z11five_kerneliiiiiiPKfS0_PKiPff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     25
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         76
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         84
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         86
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         88
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         90
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         92
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         94
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         136
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 328
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff
    .private_segment_fixed_size: 0
    .sgpr_count:     32
    .sgpr_spill_count: 0
    .symbol:         _Z15fivegrad_kerneliiiiiiPKfS0_PKiS0_Pff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     49
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
