#include <iostream>
#include <math.h>
#include <stdio.h>
#include <algorithm>
#include <stdlib.h>
#include <time.h>

using namespace std;

__device__
int xgcd(int a, int b, int *x, int *y)
{

  // Base Case
   if (a == 0)
   {
       *x = 0, *y = 1;
       return b;
   }

   int x1, y1; // To store results of recursive call
   int gcd = xgcd(b%a, a, &x1, &y1);

   // Update x and y using results of recursive
   // call
   *x = y1 - (b/a) * x1;
   *y = x1;

   return gcd;

}

__global__
void modinv(int *x, int *y, int n)
{

  int index = blockIdx.x * blockDim.x + threadIdx.x;
  int stride = blockDim.x * gridDim.x;
  for (int i = index; i < n; i += stride)
  {

    int a, b;
    int g = xgcd(x[i], y[i], &a, &b);

    if (g != 1) return;
    else (a%y[i] + y[i]) % y[i];

  }
}

int main(void)
{
  int N = 1<<22;
  int *x, *y;

  // Allocate Unified Memory – accessible from CPU or GPU
  cudaMallocManaged(&x, N*sizeof(int));
  cudaMallocManaged(&y, N*sizeof(int));

  srand((unsigned)time(NULL));

  // initialize x and y arrays on the host
  for (int i = 0; i < N; i++) {
    x[i] = rand()%10+1;
    y[i] = 11;

  }

  // Run kernel on 1M elements on the GPU
  int blockSize = 256;
  int numBlocks = (N + blockSize - 1) / blockSize;
  modinv<<<numBlocks, blockSize>>>(x, y, N);

  // Wait for GPU to finish before accessing on host
  cudaDeviceSynchronize();

  // Free memory
  cudaFree(x);
  cudaFree(y);

  return 0;
}

	.file	"tmpxft_0037bbbd_00000000-6_GPU_Recursive.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3893:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3893:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z4xgcdiiPiS_
	.type	_Z4xgcdiiPiS_, @function
_Z4xgcdiiPiS_:
.LFB3889:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3889:
	.size	_Z4xgcdiiPiS_, .-_Z4xgcdiiPiS_
	.globl	_Z28__device_stub__Z6modinvPiS_iPiS_i
	.type	_Z28__device_stub__Z6modinvPiS_iPiS_i, @function
_Z28__device_stub__Z6modinvPiS_iPiS_i:
.LFB3915:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z6modinvPiS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L4:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3915:
	.size	_Z28__device_stub__Z6modinvPiS_iPiS_i, .-_Z28__device_stub__Z6modinvPiS_iPiS_i
	.globl	_Z6modinvPiS_i
	.type	_Z6modinvPiS_i, @function
_Z6modinvPiS_i:
.LFB3916:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z6modinvPiS_iPiS_i
	.cfi_endproc
.LFE3916:
	.size	_Z6modinvPiS_i, .-_Z6modinvPiS_i
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3890:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	$1, %edx
	movl	$16777216, %esi
	movl	$10, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	xorl	%ebx, %ebx
	subq	$56, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	call	cudaMallocManaged@PLT
	movl	$1, %edx
	movl	$16777216, %esi
	leaq	8(%rsp), %rdi
	call	cudaMallocManaged@PLT
	xorl	%edi, %edi
	call	time@PLT
	movl	%eax, %edi
	call	srand@PLT
.L11:
	call	rand@PLT
	cltd
	idivl	%ebp
	movq	(%rsp), %rax
	incl	%edx
	movl	%edx, (%rax,%rbx)
	movq	8(%rsp), %rax
	movl	$11, (%rax,%rbx)
	addq	$4, %rbx
	cmpq	$16777216, %rbx
	jne	.L11
	movl	$16777217, %edx
	movl	$262145, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$8, %rdx
	salq	$14, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$4194304, %edx
	call	_Z28__device_stub__Z6modinvPiS_iPiS_i
.L12:
	call	cudaDeviceSynchronize@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$56, %rsp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3890:
	.size	main, .-main
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z6modinvPiS_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3918:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6modinvPiS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3918:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <stdio.h>
#include <algorithm>
#include <stdlib.h>
#include <time.h>

using namespace std;

__device__
int xgcd(int a, int b, int *x, int *y)
{

  // Base Case
   if (a == 0)
   {
       *x = 0, *y = 1;
       return b;
   }

   int x1, y1; // To store results of recursive call
   int gcd = xgcd(b%a, a, &x1, &y1);

   // Update x and y using results of recursive
   // call
   *x = y1 - (b/a) * x1;
   *y = x1;

   return gcd;

}

__global__
void modinv(int *x, int *y, int n)
{

  int index = blockIdx.x * blockDim.x + threadIdx.x;
  int stride = blockDim.x * gridDim.x;
  for (int i = index; i < n; i += stride)
  {

    int a, b;
    int g = xgcd(x[i], y[i], &a, &b);

    if (g != 1) return;
    else (a%y[i] + y[i]) % y[i];

  }
}

int main(void)
{
  int N = 1<<22;
  int *x, *y;

  // Allocate Unified Memory – accessible from CPU or GPU
  hipMallocManaged(&x, N*sizeof(int));
  hipMallocManaged(&y, N*sizeof(int));

  srand((unsigned)time(NULL));

  // initialize x and y arrays on the host
  for (int i = 0; i < N; i++) {
    x[i] = rand()%10+1;
    y[i] = 11;

  }

  // Run kernel on 1M elements on the GPU
  int blockSize = 256;
  int numBlocks = (N + blockSize - 1) / blockSize;
  modinv<<<numBlocks, blockSize>>>(x, y, N);

  // Wait for GPU to finish before accessing on host
  hipDeviceSynchronize();

  // Free memory
  hipFree(x);
  hipFree(y);

  return 0;
}

	.text
	.file	"GPU_Recursive.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z21__device_stub__modinvPiS_i  # -- Begin function _Z21__device_stub__modinvPiS_i
	.type	_Z21__device_stub__modinvPiS_i,@function
_Z21__device_stub__modinvPiS_i:         # @_Z21__device_stub__modinvPiS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6modinvPiS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__modinvPiS_i, .Lfunc_end0-_Z21__device_stub__modinvPiS_i
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -16
	leaq	8(%rsp), %rdi
	movl	$16777216, %esi                 # imm = 0x1000000
	movl	$1, %edx
	callq	hipMallocManaged
	movq	%rsp, %rdi
	movl	$16777216, %esi                 # imm = 0x1000000
	movl	$1, %edx
	callq	hipMallocManaged
	xorl	%ebx, %ebx
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$34, %rcx
	addl	%edx, %ecx
	addl	%ecx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	negl	%ecx
	addl	%ecx, %eax
	incl	%eax
	movq	8(%rsp), %rcx
	movl	%eax, (%rcx,%rbx,4)
	movq	(%rsp), %rax
	movl	$11, (%rax,%rbx,4)
	incq	%rbx
	cmpq	$4194304, %rbx                  # imm = 0x400000
	jne	.LBB1_1
# %bb.2:
	movabsq	$4294967552, %rdx               # imm = 0x100000100
	leaq	16128(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.3:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	movl	$4194304, %edx                  # imm = 0x400000
	callq	_Z21__device_stub__modinvPiS_i
.LBB1_4:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6modinvPiS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6modinvPiS_i,@object          # @_Z6modinvPiS_i
	.section	.rodata,"a",@progbits
	.globl	_Z6modinvPiS_i
	.p2align	3, 0x0
_Z6modinvPiS_i:
	.quad	_Z21__device_stub__modinvPiS_i
	.size	_Z6modinvPiS_i, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z6modinvPiS_i"
	.size	.L__unnamed_1, 15

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__modinvPiS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6modinvPiS_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.p2align	2                               ; -- Begin function _Z4xgcdiiPiS_
	.type	_Z4xgcdiiPiS_,@function
_Z4xgcdiiPiS_:                          ; @_Z4xgcdiiPiS_
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	s_mov_b32 s0, s33
	s_mov_b32 s33, s32
	s_or_saveexec_b32 s1, -1
	scratch_store_b32 off, v45, s33 offset:28 ; 4-byte Folded Spill
	s_mov_b32 exec_lo, s1
	v_writelane_b32 v45, s0, 3
	s_add_i32 s32, s32, 48
	s_clause 0x4
	scratch_store_b32 off, v40, s33 offset:16
	; meta instruction
	scratch_store_b32 off, v41, s33 offset:12
	; meta instruction
	scratch_store_b32 off, v42, s33 offset:8
	; meta instruction
	scratch_store_b32 off, v43, s33 offset:4
	; meta instruction
	scratch_store_b32 off, v44, s33
	v_writelane_b32 v45, s34, 0
	v_writelane_b32 v45, s30, 1
	v_writelane_b32 v45, s31, 2
	v_dual_mov_b32 v41, v5 :: v_dual_mov_b32 v40, v4
	v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v42, v2
	v_dual_mov_b32 v43, v3 :: v_dual_mov_b32 v0, v1
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, 1
	s_mov_b32 s34, exec_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cmpx_ne_u32_e32 0, v5
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_ashrrev_i32_e32 v1, 31, v5
	v_ashrrev_i32_e32 v6, 31, v0
	s_mov_b64 s[0:1], src_private_base
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, _Z4xgcdiiPiS_@rel32@lo+4
	s_addc_u32 s3, s3, _Z4xgcdiiPiS_@rel32@hi+12
	s_add_i32 s0, s33, 20
	v_add_nc_u32_e32 v2, v5, v1
	v_add_nc_u32_e32 v7, v0, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v2, v2, v1
	v_xor_b32_e32 v7, v7, v6
	v_xor_b32_e32 v1, v6, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v3, v2
	v_sub_nc_u32_e32 v4, 0, v2
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v3
	v_mul_lo_u32 v4, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v3, v4
	v_add_nc_u32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v7, v3
	v_mul_lo_u32 v4, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v7, v4
	v_sub_nc_u32_e32 v8, v4, v2
	v_cmp_ge_u32_e32 vcc_lo, v4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v4, v4, v8 :: v_dual_add_nc_u32 v7, 1, v3
	v_cndmask_b32_e32 v3, v3, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_u32_e32 vcc_lo, v4, v2
	v_add_nc_u32_e32 v7, 1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v2, v3, v7 :: v_dual_mov_b32 v3, s1
	v_xor_b32_e32 v2, v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_sub_nc_u32_e32 v44, v2, v1
	v_mov_b32_e32 v2, s0
	s_add_i32 s0, s33, 24
	v_mov_b32_e32 v4, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, v44, v5
	v_sub_nc_u32_e32 v0, v0, v1
	v_mov_b32_e32 v1, v5
	v_mov_b32_e32 v5, s1
	s_swappc_b64 s[30:31], s[2:3]
	s_clause 0x1
	scratch_load_b32 v1, off, s33 offset:20
	scratch_load_b32 v2, off, s33 offset:24
	s_waitcnt vmcnt(1)
	v_mul_lo_u32 v3, v1, v44
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v2, v3
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s34
	flat_store_b32 v[42:43], v2
	flat_store_b32 v[40:41], v1
	s_clause 0x4
	scratch_load_b32 v44, off, s33
	scratch_load_b32 v43, off, s33 offset:4
	scratch_load_b32 v42, off, s33 offset:8
	scratch_load_b32 v41, off, s33 offset:12
	scratch_load_b32 v40, off, s33 offset:16
	v_readlane_b32 s30, v45, 1
	v_readlane_b32 s31, v45, 2
	v_readlane_b32 s34, v45, 0
	v_readlane_b32 s0, v45, 3
	s_or_saveexec_b32 s1, -1
	scratch_load_b32 v45, off, s33 offset:28 ; 4-byte Folded Reload
	s_mov_b32 exec_lo, s1
	s_addk_i32 s32, 0xffd0
	s_mov_b32 s33, s0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end0:
	.size	_Z4xgcdiiPiS_, .Lfunc_end0-_Z4xgcdiiPiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 576
; NumSgprs: 37
; NumVgprs: 46
; ScratchSize: 48
; MemoryBound: 0
	.text
	.protected	_Z6modinvPiS_i          ; -- Begin function _Z6modinvPiS_i
	.globl	_Z6modinvPiS_i
	.p2align	8
	.type	_Z6modinvPiS_i,@function
_Z6modinvPiS_i:                         ; @_Z6modinvPiS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s6, s[2:3], 0x24
	s_load_b32 s35, s[2:3], 0x10
	v_and_b32_e32 v1, 0x3ff, v0
	s_add_u32 s4, s2, 24
	s_addc_u32 s5, s3, 0
	s_mov_b32 s32, 0
	s_mov_b32 s7, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s6, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s15, s6, v[1:2]
	v_cmpx_gt_i32_e64 s35, v2
	s_cbranch_execz .LBB1_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b64 s[0:1], s[0:1], 0x4
	s_load_b32 s4, s[4:5], 0x0
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_load_b128 s[36:39], s[2:3], 0x0
	s_mov_b32 s44, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s0, 16
	s_add_i32 s15, s15, s4
	s_mul_i32 s0, s0, s1
	v_mad_u64_u32 v[56:57], null, s15, s6, v[1:2]
	v_mul_lo_u32 v3, s0, v1
	s_mul_i32 s40, s4, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s41, s40, 31
	s_lshl_b64 s[42:43], s[40:41], 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v3, v4, s1, v3
	s_mov_b64 s[0:1], src_shared_base
	v_add_lshl_u32 v0, v3, v0, 2
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v4, 0x1000, v0
	v_cmp_ne_u32_e64 s0, -1, v0
	v_lshlrev_b64 v[46:47], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e64 v40, 0, v0, s0
	v_cndmask_b32_e64 v43, 0, s1, s0
	v_cndmask_b32_e32 v41, 0, v4, vcc_lo
	v_cndmask_b32_e64 v42, 0, s1, vcc_lo
.LBB1_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v0, vcc_lo, s36, v46
	v_add_co_ci_u32_e32 v1, vcc_lo, s37, v47, vcc_lo
	v_add_co_u32 v2, vcc_lo, s38, v46
	v_add_co_ci_u32_e32 v3, vcc_lo, s39, v47, vcc_lo
	v_dual_mov_b32 v4, v40 :: v_dual_mov_b32 v5, v43
	global_load_b32 v0, v[0:1], off
	global_load_b32 v1, v[2:3], off
	v_dual_mov_b32 v2, v41 :: v_dual_mov_b32 v3, v42
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z4xgcdiiPiS_@rel32@lo+4
	s_addc_u32 s1, s1, _Z4xgcdiiPiS_@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	s_swappc_b64 s[30:31], s[0:1]
	v_cmp_le_i32_e32 vcc_lo, s35, v56
	v_cmp_ne_u32_e64 s0, 1, v0
	v_add_co_u32 v46, s1, v46, s42
	v_add_nc_u32_e32 v56, s40, v56
	s_or_b32 s0, s0, vcc_lo
	v_add_co_ci_u32_e64 v47, vcc_lo, s43, v47, s1
	s_and_b32 s0, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s44, s0, s44
	s_and_not1_b32 exec_lo, exec_lo, s44
	s_cbranch_execnz .LBB1_2
.LBB1_3:                                ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6modinvPiS_i
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 48
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 1
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 1
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 58
		.amdhsa_next_free_sgpr 45
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z6modinvPiS_i, .Lfunc_end1-_Z6modinvPiS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 408
; NumSgprs: 47
; NumVgprs: 58
; ScratchSize: 48
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 7
; NumSGPRsForWavesPerEU: 47
; NumVGPRsForWavesPerEU: 58
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 8192
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6modinvPiS_i
    .private_segment_fixed_size: 48
    .sgpr_count:     47
    .sgpr_spill_count: 0
    .symbol:         _Z6modinvPiS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: true
    .vgpr_count:     58
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
