#include "includes.h"
__device__ unsigned int getGid3d3d(){
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.y * blockDim.x)
+ (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x;
return threadId;
}
__global__ void cMultPhi(double2* in1, double* in2, double2* out){
double2 result;
unsigned int gid = getGid3d3d();
result.x = cos(in2[gid])*in1[gid].x - in1[gid].y*sin(in2[gid]);
result.y = in1[gid].x*sin(in2[gid]) + in1[gid].y*cos(in2[gid]);
out[gid] = result;
}
	.file	"tmpxft_00275ecf_00000000-6_cMultPhi.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z10getGid3d3dv
	.type	_Z10getGid3d3dv, @function
_Z10getGid3d3dv:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z10getGid3d3dv, .-_Z10getGid3d3dv
	.globl	_Z39__device_stub__Z8cMultPhiP7double2PdS0_P7double2PdS0_
	.type	_Z39__device_stub__Z8cMultPhiP7double2PdS0_P7double2PdS0_, @function
_Z39__device_stub__Z8cMultPhiP7double2PdS0_P7double2PdS0_:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z8cMultPhiP7double2PdS0_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L4:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z39__device_stub__Z8cMultPhiP7double2PdS0_P7double2PdS0_, .-_Z39__device_stub__Z8cMultPhiP7double2PdS0_P7double2PdS0_
	.globl	_Z8cMultPhiP7double2PdS0_
	.type	_Z8cMultPhiP7double2PdS0_, @function
_Z8cMultPhiP7double2PdS0_:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z8cMultPhiP7double2PdS0_P7double2PdS0_
	.cfi_endproc
.LFE2034:
	.size	_Z8cMultPhiP7double2PdS0_, .-_Z8cMultPhiP7double2PdS0_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z8cMultPhiP7double2PdS0_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z8cMultPhiP7double2PdS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__device__ unsigned int getGid3d3d(){
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.y * blockDim.x)
+ (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x;
return threadId;
}
__global__ void cMultPhi(double2* in1, double* in2, double2* out){
double2 result;
unsigned int gid = getGid3d3d();
result.x = cos(in2[gid])*in1[gid].x - in1[gid].y*sin(in2[gid]);
result.y = in1[gid].x*sin(in2[gid]) + in1[gid].y*cos(in2[gid]);
out[gid] = result;
}
	.text
	.file	"cMultPhi.hip"
	.globl	_Z23__device_stub__cMultPhiP15HIP_vector_typeIdLj2EEPdS1_ # -- Begin function _Z23__device_stub__cMultPhiP15HIP_vector_typeIdLj2EEPdS1_
	.type	_Z23__device_stub__cMultPhiP15HIP_vector_typeIdLj2EEPdS1_,@function
_Z23__device_stub__cMultPhiP15HIP_vector_typeIdLj2EEPdS1_: # @_Z23__device_stub__cMultPhiP15HIP_vector_typeIdLj2EEPdS1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8cMultPhiP15HIP_vector_typeIdLj2EEPdS1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z23__device_stub__cMultPhiP15HIP_vector_typeIdLj2EEPdS1_, .Lfunc_end0-_Z23__device_stub__cMultPhiP15HIP_vector_typeIdLj2EEPdS1_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8cMultPhiP15HIP_vector_typeIdLj2EEPdS1_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z8cMultPhiP15HIP_vector_typeIdLj2EEPdS1_,@object # @_Z8cMultPhiP15HIP_vector_typeIdLj2EEPdS1_
	.section	.rodata,"a",@progbits
	.globl	_Z8cMultPhiP15HIP_vector_typeIdLj2EEPdS1_
	.p2align	3, 0x0
_Z8cMultPhiP15HIP_vector_typeIdLj2EEPdS1_:
	.quad	_Z23__device_stub__cMultPhiP15HIP_vector_typeIdLj2EEPdS1_
	.size	_Z8cMultPhiP15HIP_vector_typeIdLj2EEPdS1_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z8cMultPhiP15HIP_vector_typeIdLj2EEPdS1_"
	.size	.L__unnamed_1, 42

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__cMultPhiP15HIP_vector_typeIdLj2EEPdS1_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8cMultPhiP15HIP_vector_typeIdLj2EEPdS1_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8cMultPhiP15HIP_vector_typeIdLj2EEPdS1_ ; -- Begin function _Z8cMultPhiP15HIP_vector_typeIdLj2EEPdS1_
	.globl	_Z8cMultPhiP15HIP_vector_typeIdLj2EEPdS1_
	.p2align	8
	.type	_Z8cMultPhiP15HIP_vector_typeIdLj2EEPdS1_,@function
_Z8cMultPhiP15HIP_vector_typeIdLj2EEPdS1_: ; @_Z8cMultPhiP15HIP_vector_typeIdLj2EEPdS1_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_mov_b32_e32 v1, 0
                                        ; implicit-def: $vgpr32
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $vgpr10_vgpr11
	global_load_b32 v5, v1, s[0:1] offset:38
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s11, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, s14
	s_mul_i32 s2, s2, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, s13
	s_cmp_lt_u32 s13, s10
	s_cselect_b32 s3, 12, 18
	v_mov_b32_e32 v2, s3
	global_load_u16 v6, v2, s[0:1]
	v_bfe_u32 v2, v0, 20, 10
	s_waitcnt vmcnt(1)
	v_lshrrev_b32_e32 v7, 16, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[3:4], null, s2, v7, v[2:3]
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v7, 0xffff, v5
	v_and_b32_e32 v0, 0x3ff, v0
	v_mad_u64_u32 v[4:5], null, v3, v7, v[2:3]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v4, v6, v[0:1]
	v_mov_b32_e32 v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[0:1]
	v_add_co_u32 v2, vcc_lo, s6, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	global_load_b64 v[4:5], v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f64_e64 s1, 0x41d00000, |v[4:5]|
	v_trig_preop_f64 v[20:21], |v[4:5]|, 0
	v_trig_preop_f64 v[18:19], |v[4:5]|, 1
	v_ldexp_f64 v[22:23], |v[4:5]|, 0xffffff80
	v_trig_preop_f64 v[16:17], |v[4:5]|, 2
	v_and_b32_e32 v34, 0x7fffffff, v5
	s_and_saveexec_b32 s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[4:5]|
	v_mov_b32_e32 v32, v1
	s_mov_b32 s6, 0x54442d18
	s_mov_b32 s7, 0x3ff921fb
	s_mov_b32 s10, 0x33145c07
	s_mov_b32 s11, 0x3c91a626
	v_dual_cndmask_b32 v3, v34, v23 :: v_dual_cndmask_b32 v2, v4, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[6:7], v[20:21], v[2:3]
	v_mul_f64 v[8:9], v[18:19], v[2:3]
	v_mul_f64 v[28:29], v[16:17], v[2:3]
	v_fma_f64 v[10:11], v[20:21], v[2:3], -v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[30:31], v[18:19], v[2:3], -v[8:9]
	v_fma_f64 v[2:3], v[16:17], v[2:3], -v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[8:9], v[10:11]
	v_add_f64 v[14:15], v[12:13], -v[8:9]
	v_add_f64 v[26:27], v[6:7], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[12:13], -v[14:15]
	v_add_f64 v[10:11], v[10:11], -v[14:15]
	v_ldexp_f64 v[14:15], v[26:27], -2
	v_add_f64 v[6:7], v[26:27], -v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[8:9], v[8:9], -v[24:25]
	v_add_f64 v[24:25], v[28:29], v[30:31]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[14:15]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[6:7], v[12:13], -v[6:7]
	v_add_f64 v[8:9], v[10:11], v[8:9]
	v_fract_f64_e32 v[10:11], v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[24:25], v[8:9]
	v_dual_cndmask_b32 v11, 0, v11 :: v_dual_cndmask_b32 v10, 0, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[10:11], v[10:11], 2
	v_add_f64 v[14:15], v[6:7], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[26:27], v[14:15], v[10:11]
	v_add_f64 v[6:7], v[14:15], -v[6:7]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[26:27]
	v_add_f64 v[26:27], v[24:25], -v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[6:7], v[12:13], -v[6:7]
	v_cndmask_b32_e64 v33, 0, 0x40100000, vcc_lo
	v_add_f64 v[37:38], v[24:25], -v[26:27]
	v_add_f64 v[26:27], v[30:31], -v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[10:11], v[10:11], v[32:33]
	v_add_f64 v[32:33], v[12:13], -v[24:25]
	v_add_f64 v[30:31], v[28:29], -v[37:38]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[35:36], v[14:15], v[10:11]
	v_add_f64 v[39:40], v[12:13], -v[32:33]
	v_add_f64 v[8:9], v[8:9], -v[32:33]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[26:27], v[26:27], v[30:31]
	v_cvt_i32_f64_e32 v35, v[35:36]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[24:25], -v[39:40]
	v_cvt_f64_i32_e32 v[32:33], v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[8:9], v[24:25]
	v_add_f64 v[10:11], v[10:11], -v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[26:27], v[8:9]
	v_add_f64 v[24:25], v[14:15], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[2:3], v[2:3], v[8:9]
	v_add_f64 v[8:9], v[24:25], -v[10:11]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[2:3], v[6:7], v[2:3]
	v_add_f64 v[6:7], v[14:15], -v[8:9]
	v_mov_b32_e32 v8, v1
	v_cndmask_b32_e64 v9, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v32, s0, 0, v35, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[2:3], v[2:3], v[6:7]
	v_add_f64 v[6:7], v[24:25], -v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[6:7], v[2:3]
	v_mul_f64 v[10:11], v[8:9], s[6:7]
	v_add_f64 v[6:7], v[8:9], -v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[12:13], v[8:9], s[6:7], -v[10:11]
	v_add_f64 v[2:3], v[2:3], -v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[8:9], s[10:11], v[12:13]
	v_fma_f64 v[2:3], v[2:3], s[6:7], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[10:11], v[2:3]
	v_add_f64 v[6:7], v[8:9], -v[10:11]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[10:11], v[2:3], -v[6:7]
.LBB0_2:                                ; %Flow46
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_4
; %bb.3:
	s_mov_b32 s2, 0x6dc9c883
	s_mov_b32 s3, 0x3fe45f30
	s_mov_b32 s7, 0xbc91a626
	v_mul_f64 v[2:3], |v[4:5]|, s[2:3]
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0xbff921fb
	s_mov_b32 s6, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[2:3], v[2:3]
	v_fma_f64 v[6:7], v[2:3], s[2:3], |v[4:5]|
	v_mul_f64 v[8:9], v[2:3], s[6:7]
	s_mov_b32 s2, 0x252049c0
	s_mov_b32 s3, 0xb97b839a
	v_cvt_i32_f64_e32 v32, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[12:13], v[2:3], s[6:7], v[6:7]
	v_add_f64 v[10:11], v[6:7], v[8:9]
	s_mov_b32 s7, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[6:7], v[6:7], -v[10:11]
	v_add_f64 v[10:11], v[10:11], -v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], v[8:9]
	v_fma_f64 v[8:9], v[2:3], s[6:7], v[8:9]
	v_add_f64 v[6:7], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[8:9]
	v_fma_f64 v[6:7], v[2:3], s[2:3], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[12:13], v[6:7]
	v_add_f64 v[10:11], v[8:9], -v[12:13]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[10:11], v[6:7], -v[10:11]
.LBB0_4:                                ; %_ZL3cosd.exit
	s_or_b32 exec_lo, exec_lo, s0
	v_lshlrev_b64 v[6:7], 4, v[0:1]
                                        ; implicit-def: $vgpr33
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $vgpr14_vgpr15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v7, vcc_lo
	global_load_b128 v[0:3], v[0:1], off
	s_and_saveexec_b32 s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB0_6
; %bb.5:
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[4:5]|
	v_mov_b32_e32 v43, 0
	s_mov_b32 s4, 0x54442d18
	s_mov_b32 s5, 0x3ff921fb
	s_mov_b32 s6, 0x33145c07
	s_mov_b32 s7, 0x3c91a626
	v_dual_cndmask_b32 v13, v34, v23 :: v_dual_cndmask_b32 v12, v4, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[14:15], v[20:21], v[12:13]
	v_mul_f64 v[24:25], v[18:19], v[12:13]
	v_mul_f64 v[39:40], v[16:17], v[12:13]
	v_fma_f64 v[26:27], v[20:21], v[12:13], -v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[41:42], v[18:19], v[12:13], -v[24:25]
	v_fma_f64 v[12:13], v[16:17], v[12:13], -v[39:40]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[28:29], v[24:25], v[26:27]
	v_add_f64 v[30:31], v[28:29], -v[24:25]
	v_add_f64 v[37:38], v[14:15], v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[35:36], v[28:29], -v[30:31]
	v_add_f64 v[26:27], v[26:27], -v[30:31]
	v_ldexp_f64 v[30:31], v[37:38], -2
	v_add_f64 v[14:15], v[37:38], -v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[24:25], v[24:25], -v[35:36]
	v_add_f64 v[35:36], v[39:40], v[41:42]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[30:31]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[14:15], v[28:29], -v[14:15]
	v_add_f64 v[24:25], v[26:27], v[24:25]
	v_fract_f64_e32 v[26:27], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[28:29], v[35:36], v[24:25]
	v_dual_cndmask_b32 v27, 0, v27 :: v_dual_cndmask_b32 v26, 0, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[26:27], v[26:27], 2
	v_add_f64 v[30:31], v[14:15], v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[37:38], v[30:31], v[26:27]
	v_add_f64 v[14:15], v[30:31], -v[14:15]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[37:38]
	v_add_f64 v[37:38], v[35:36], -v[39:40]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[28:29], -v[14:15]
	v_cndmask_b32_e64 v44, 0, 0x40100000, vcc_lo
	v_add_f64 v[48:49], v[35:36], -v[37:38]
	v_add_f64 v[37:38], v[41:42], -v[37:38]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[26:27], v[26:27], v[43:44]
	v_add_f64 v[44:45], v[28:29], -v[35:36]
	v_add_f64 v[41:42], v[39:40], -v[48:49]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[46:47], v[30:31], v[26:27]
	v_add_f64 v[50:51], v[28:29], -v[44:45]
	v_add_f64 v[24:25], v[24:25], -v[44:45]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[37:38], v[37:38], v[41:42]
	v_cvt_i32_f64_e32 v33, v[46:47]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[35:36], v[35:36], -v[50:51]
	v_cvt_f64_i32_e32 v[44:45], v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[24:25], v[35:36]
	v_add_f64 v[26:27], v[26:27], -v[44:45]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[37:38], v[24:25]
	v_add_f64 v[35:36], v[30:31], v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[12:13], v[24:25]
	v_add_f64 v[24:25], v[35:36], -v[26:27]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[35:36]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[14:15], v[12:13]
	v_add_f64 v[14:15], v[30:31], -v[24:25]
	v_cndmask_b32_e64 v44, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v33, s0, 0, v33, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[12:13], v[14:15]
	v_add_f64 v[14:15], v[35:36], -v[43:44]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[14:15], v[12:13]
	v_mul_f64 v[26:27], v[24:25], s[4:5]
	v_add_f64 v[14:15], v[24:25], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[28:29], v[24:25], s[4:5], -v[26:27]
	v_add_f64 v[12:13], v[12:13], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[24:25], s[6:7], v[28:29]
	v_fma_f64 v[14:15], v[12:13], s[4:5], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[26:27], v[14:15]
	v_add_f64 v[24:25], v[12:13], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[14:15], v[14:15], -v[24:25]
.LBB0_6:                                ; %Flow45
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_8
; %bb.7:
	s_mov_b32 s2, 0x6dc9c883
	s_mov_b32 s3, 0x3fe45f30
	s_mov_b32 s5, 0xbc91a626
	v_mul_f64 v[12:13], |v[4:5]|, s[2:3]
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0xbff921fb
	s_mov_b32 s4, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[24:25], v[12:13]
	v_fma_f64 v[12:13], v[24:25], s[2:3], |v[4:5]|
	v_mul_f64 v[14:15], v[24:25], s[4:5]
	s_mov_b32 s2, 0x252049c0
	s_mov_b32 s3, 0xb97b839a
	v_cvt_i32_f64_e32 v33, v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[28:29], v[24:25], s[4:5], v[12:13]
	v_add_f64 v[26:27], v[12:13], v[14:15]
	s_mov_b32 s5, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[12:13], -v[26:27]
	v_add_f64 v[26:27], v[26:27], -v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[12:13], v[14:15]
	v_fma_f64 v[14:15], v[24:25], s[4:5], v[14:15]
	v_add_f64 v[12:13], v[26:27], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[12:13], -v[14:15]
	v_fma_f64 v[14:15], v[24:25], s[2:3], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[28:29], v[14:15]
	v_add_f64 v[26:27], v[12:13], -v[28:29]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[14:15], v[14:15], -v[26:27]
.LBB0_8:                                ; %_ZL3sind.exit
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr35
                                        ; implicit-def: $vgpr24_vgpr25
                                        ; implicit-def: $vgpr26_vgpr27
	s_and_saveexec_b32 s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB0_10
; %bb.9:
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[4:5]|
	v_mov_b32_e32 v47, 0
	s_mov_b32 s4, 0x54442d18
	s_mov_b32 s5, 0x3ff921fb
	s_mov_b32 s6, 0x33145c07
	s_mov_b32 s7, 0x3c91a626
	v_dual_cndmask_b32 v25, v34, v23 :: v_dual_cndmask_b32 v24, v4, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[26:27], v[20:21], v[24:25]
	v_mul_f64 v[28:29], v[18:19], v[24:25]
	v_mul_f64 v[43:44], v[16:17], v[24:25]
	v_fma_f64 v[30:31], v[20:21], v[24:25], -v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[45:46], v[18:19], v[24:25], -v[28:29]
	v_fma_f64 v[24:25], v[16:17], v[24:25], -v[43:44]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[35:36], v[28:29], v[30:31]
	v_add_f64 v[37:38], v[35:36], -v[28:29]
	v_add_f64 v[41:42], v[26:27], v[35:36]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[39:40], v[35:36], -v[37:38]
	v_add_f64 v[30:31], v[30:31], -v[37:38]
	v_ldexp_f64 v[37:38], v[41:42], -2
	v_add_f64 v[26:27], v[41:42], -v[26:27]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[28:29], v[28:29], -v[39:40]
	v_add_f64 v[39:40], v[43:44], v[45:46]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[37:38]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[26:27], v[35:36], -v[26:27]
	v_add_f64 v[28:29], v[30:31], v[28:29]
	v_fract_f64_e32 v[30:31], v[37:38]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[35:36], v[39:40], v[28:29]
	v_dual_cndmask_b32 v31, 0, v31 :: v_dual_cndmask_b32 v30, 0, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[30:31], v[30:31], 2
	v_add_f64 v[37:38], v[26:27], v[35:36]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[41:42], v[37:38], v[30:31]
	v_add_f64 v[26:27], v[37:38], -v[26:27]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[41:42]
	v_add_f64 v[41:42], v[39:40], -v[43:44]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[35:36], -v[26:27]
	v_cndmask_b32_e64 v48, 0, 0x40100000, vcc_lo
	v_add_f64 v[52:53], v[39:40], -v[41:42]
	v_add_f64 v[41:42], v[45:46], -v[41:42]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[30:31], v[30:31], v[47:48]
	v_add_f64 v[48:49], v[35:36], -v[39:40]
	v_add_f64 v[45:46], v[43:44], -v[52:53]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[50:51], v[37:38], v[30:31]
	v_add_f64 v[54:55], v[35:36], -v[48:49]
	v_add_f64 v[28:29], v[28:29], -v[48:49]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[41:42], v[41:42], v[45:46]
	v_cvt_i32_f64_e32 v50, v[50:51]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[39:40], v[39:40], -v[54:55]
	v_cvt_f64_i32_e32 v[48:49], v50
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[28:29], v[28:29], v[39:40]
	v_add_f64 v[30:31], v[30:31], -v[48:49]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[28:29], v[41:42], v[28:29]
	v_add_f64 v[39:40], v[37:38], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[24:25], v[28:29]
	v_add_f64 v[28:29], v[39:40], -v[30:31]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[39:40]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[26:27], v[24:25]
	v_add_f64 v[26:27], v[37:38], -v[28:29]
	v_cndmask_b32_e64 v48, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v35, s0, 0, v50, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[24:25], v[26:27]
	v_add_f64 v[26:27], v[39:40], -v[47:48]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[28:29], v[26:27], v[24:25]
	v_mul_f64 v[30:31], v[28:29], s[4:5]
	v_add_f64 v[26:27], v[28:29], -v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[36:37], v[28:29], s[4:5], -v[30:31]
	v_add_f64 v[24:25], v[24:25], -v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[28:29], s[6:7], v[36:37]
	v_fma_f64 v[26:27], v[24:25], s[4:5], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[30:31], v[26:27]
	v_add_f64 v[28:29], v[24:25], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[26:27], v[26:27], -v[28:29]
.LBB0_10:                               ; %Flow44
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_12
; %bb.11:
	s_mov_b32 s2, 0x6dc9c883
	s_mov_b32 s3, 0x3fe45f30
	s_mov_b32 s5, 0xbc91a626
	v_mul_f64 v[24:25], |v[4:5]|, s[2:3]
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0xbff921fb
	s_mov_b32 s4, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[28:29], v[24:25]
	v_fma_f64 v[24:25], v[28:29], s[2:3], |v[4:5]|
	v_mul_f64 v[26:27], v[28:29], s[4:5]
	s_mov_b32 s2, 0x252049c0
	s_mov_b32 s3, 0xb97b839a
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[35:36], v[28:29], s[4:5], v[24:25]
	v_add_f64 v[30:31], v[24:25], v[26:27]
	s_mov_b32 s5, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[24:25], -v[30:31]
	v_add_f64 v[30:31], v[30:31], -v[35:36]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[24:25], v[26:27]
	v_fma_f64 v[26:27], v[28:29], s[4:5], v[26:27]
	v_add_f64 v[24:25], v[30:31], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[24:25], -v[26:27]
	v_fma_f64 v[26:27], v[28:29], s[2:3], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[24:25], v[35:36], v[26:27]
	v_add_f64 v[30:31], v[24:25], -v[35:36]
	v_cvt_i32_f64_e32 v35, v[28:29]
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[26:27], v[26:27], -v[30:31]
.LBB0_12:                               ; %_ZL3sind.exit28
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr36
                                        ; implicit-def: $vgpr28_vgpr29
                                        ; implicit-def: $vgpr30_vgpr31
	s_and_saveexec_b32 s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB0_14
; %bb.13:
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[4:5]|
	v_mov_b32_e32 v46, 0
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0x3ff921fb
	s_mov_b32 s4, 0x33145c07
	s_mov_b32 s5, 0x3c91a626
	v_dual_cndmask_b32 v23, v34, v23 :: v_dual_cndmask_b32 v22, v4, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[28:29], v[20:21], v[22:23]
	v_mul_f64 v[30:31], v[18:19], v[22:23]
	v_mul_f64 v[44:45], v[16:17], v[22:23]
	v_fma_f64 v[20:21], v[20:21], v[22:23], -v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[18:19], v[18:19], v[22:23], -v[30:31]
	v_fma_f64 v[16:17], v[16:17], v[22:23], -v[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[36:37], v[30:31], v[20:21]
	v_add_f64 v[38:39], v[36:37], -v[30:31]
	v_add_f64 v[42:43], v[28:29], v[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[40:41], v[36:37], -v[38:39]
	v_add_f64 v[20:21], v[20:21], -v[38:39]
	v_ldexp_f64 v[38:39], v[42:43], -2
	v_add_f64 v[28:29], v[42:43], -v[28:29]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[30:31], v[30:31], -v[40:41]
	v_add_f64 v[40:41], v[44:45], v[18:19]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[38:39]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[28:29], v[36:37], -v[28:29]
	v_add_f64 v[20:21], v[20:21], v[30:31]
	v_fract_f64_e32 v[30:31], v[38:39]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[36:37], v[40:41], v[20:21]
	v_dual_cndmask_b32 v31, 0, v31 :: v_dual_cndmask_b32 v30, 0, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[30:31], v[30:31], 2
	v_add_f64 v[38:39], v[28:29], v[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[42:43], v[38:39], v[30:31]
	v_add_f64 v[22:23], v[38:39], -v[28:29]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[42:43]
	v_add_f64 v[42:43], v[40:41], -v[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[22:23], v[36:37], -v[22:23]
	v_cndmask_b32_e64 v47, 0, 0x40100000, vcc_lo
	v_add_f64 v[51:52], v[40:41], -v[42:43]
	v_add_f64 v[18:19], v[18:19], -v[42:43]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[30:31], v[30:31], v[46:47]
	v_add_f64 v[47:48], v[36:37], -v[40:41]
	v_add_f64 v[42:43], v[44:45], -v[51:52]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[49:50], v[38:39], v[30:31]
	v_add_f64 v[53:54], v[36:37], -v[47:48]
	v_add_f64 v[20:21], v[20:21], -v[47:48]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[18:19], v[18:19], v[42:43]
	v_cvt_i32_f64_e32 v34, v[49:50]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[40:41], v[40:41], -v[53:54]
	v_cvt_f64_i32_e32 v[47:48], v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[20:21], v[40:41]
	v_add_f64 v[30:31], v[30:31], -v[47:48]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[18:19], v[20:21]
	v_add_f64 v[20:21], v[38:39], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[16:17], v[18:19]
	v_add_f64 v[18:19], v[20:21], -v[30:31]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[22:23], v[16:17]
	v_add_f64 v[18:19], v[38:39], -v[18:19]
	v_cndmask_b32_e64 v47, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v36, s0, 0, v34, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[16:17], v[18:19]
	v_add_f64 v[18:19], v[20:21], -v[46:47]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[18:19], v[16:17]
	v_mul_f64 v[22:23], v[20:21], s[2:3]
	v_add_f64 v[18:19], v[20:21], -v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[28:29], v[20:21], s[2:3], -v[22:23]
	v_add_f64 v[16:17], v[16:17], -v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[20:21], s[4:5], v[28:29]
	v_fma_f64 v[16:17], v[16:17], s[2:3], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[28:29], v[22:23], v[16:17]
	v_add_f64 v[18:19], v[28:29], -v[22:23]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[30:31], v[16:17], -v[18:19]
.LBB0_14:                               ; %Flow
	s_and_not1_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_16
; %bb.15:
	s_mov_b32 s2, 0x6dc9c883
	s_mov_b32 s3, 0x3fe45f30
	s_mov_b32 s5, 0xbc91a626
	v_mul_f64 v[16:17], |v[4:5]|, s[2:3]
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0xbff921fb
	s_mov_b32 s4, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[16:17], v[16:17]
	v_fma_f64 v[18:19], v[16:17], s[2:3], |v[4:5]|
	v_mul_f64 v[20:21], v[16:17], s[4:5]
	s_mov_b32 s2, 0x252049c0
	s_mov_b32 s3, 0xb97b839a
	v_cvt_i32_f64_e32 v36, v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[30:31], v[16:17], s[4:5], v[18:19]
	v_add_f64 v[22:23], v[18:19], v[20:21]
	s_mov_b32 s5, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	v_add_f64 v[22:23], v[22:23], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[18:19], v[20:21]
	v_fma_f64 v[20:21], v[16:17], s[4:5], v[20:21]
	v_add_f64 v[18:19], v[22:23], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], -v[20:21]
	v_fma_f64 v[18:19], v[16:17], s[2:3], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[28:29], v[30:31], v[18:19]
	v_add_f64 v[20:21], v[28:29], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[30:31], v[18:19], -v[20:21]
.LBB0_16:                               ; %_ZL3cosd.exit33
	s_or_b32 exec_lo, exec_lo, s0
	v_mul_f64 v[16:17], v[24:25], v[24:25]
	v_mul_f64 v[18:19], v[28:29], v[28:29]
	v_mul_f64 v[20:21], v[12:13], v[12:13]
	s_mov_b32 s0, 0xb42fdfa7
	s_mov_b32 s2, 0xf9a43bb8
	s_mov_b32 s1, 0xbe5ae600
	s_mov_b32 s3, 0x3de5e0b2
	v_mul_f64 v[37:38], v[8:9], v[8:9]
	s_mov_b32 s4, 0x9037ab78
	s_mov_b32 s6, 0x46cc5e42
	s_mov_b32 s10, 0x796cde01
	s_mov_b32 s5, 0x3e21eeb6
	s_mov_b32 s7, 0xbda907db
	s_mov_b32 s11, 0x3ec71de3
	v_mul_f64 v[67:68], v[26:27], 0.5
	v_mul_f64 v[75:76], v[30:31], 0.5
	v_mul_f64 v[73:74], v[14:15], 0.5
	v_fma_f64 v[22:23], v[16:17], s[2:3], s[0:1]
	v_fma_f64 v[39:40], v[18:19], s[2:3], s[0:1]
	v_fma_f64 v[41:42], v[20:21], s[2:3], s[0:1]
	v_fma_f64 v[43:44], v[16:17], s[6:7], s[4:5]
	v_mul_f64 v[45:46], v[16:17], 0.5
	v_mul_f64 v[49:50], v[20:21], 0.5
	v_fma_f64 v[51:52], v[20:21], s[6:7], s[4:5]
	v_fma_f64 v[47:48], v[37:38], s[2:3], s[0:1]
	v_mul_f64 v[53:54], v[18:19], 0.5
	v_fma_f64 v[55:56], v[18:19], s[6:7], s[4:5]
	s_mov_b32 s0, 0xa17f65f6
	s_mov_b32 s2, 0x19e83e5c
	s_mov_b32 s1, 0xbe927e4f
	s_mov_b32 s3, 0xbf2a01a0
	v_mul_f64 v[59:60], v[37:38], 0.5
	v_fma_f64 v[61:62], v[37:38], s[6:7], s[4:5]
	s_mov_b32 s4, 0x11110bb3
	s_mov_b32 s6, 0x19f4ec90
	s_mov_b32 s5, 0x3f811111
	s_mov_b32 s7, 0x3efa01a0
	v_mul_f64 v[69:70], v[24:25], -v[16:17]
	v_mul_f64 v[79:80], v[28:29], -v[18:19]
	v_mul_f64 v[77:78], v[12:13], -v[20:21]
	v_fma_f64 v[22:23], v[16:17], v[22:23], s[10:11]
	v_fma_f64 v[39:40], v[18:19], v[39:40], s[10:11]
	v_fma_f64 v[41:42], v[20:21], v[41:42], s[10:11]
	v_fma_f64 v[43:44], v[16:17], v[43:44], s[0:1]
	v_add_f64 v[57:58], -v[45:46], 1.0
	v_add_f64 v[63:64], -v[49:50], 1.0
	v_fma_f64 v[51:52], v[20:21], v[51:52], s[0:1]
	v_fma_f64 v[47:48], v[37:38], v[47:48], s[10:11]
	v_add_f64 v[65:66], -v[53:54], 1.0
	v_fma_f64 v[55:56], v[18:19], v[55:56], s[0:1]
	v_add_f64 v[81:82], -v[59:60], 1.0
	v_fma_f64 v[61:62], v[37:38], v[61:62], s[0:1]
	s_mov_b32 s0, 0x16c16967
	s_mov_b32 s1, 0xbf56c16c
	v_fma_f64 v[22:23], v[16:17], v[22:23], s[2:3]
	v_fma_f64 v[39:40], v[18:19], v[39:40], s[2:3]
	v_fma_f64 v[41:42], v[20:21], v[41:42], s[2:3]
	v_fma_f64 v[43:44], v[16:17], v[43:44], s[6:7]
	v_add_f64 v[71:72], -v[57:58], 1.0
	v_add_f64 v[83:84], -v[63:64], 1.0
	v_fma_f64 v[51:52], v[20:21], v[51:52], s[6:7]
	v_fma_f64 v[47:48], v[37:38], v[47:48], s[2:3]
	v_add_f64 v[85:86], -v[65:66], 1.0
	v_fma_f64 v[55:56], v[18:19], v[55:56], s[6:7]
	s_mov_b32 s2, 0x55555555
	s_mov_b32 s3, 0xbfc55555
	v_add_f64 v[87:88], -v[81:82], 1.0
	v_fma_f64 v[61:62], v[37:38], v[61:62], s[6:7]
	v_fma_f64 v[22:23], v[16:17], v[22:23], s[4:5]
	v_fma_f64 v[39:40], v[18:19], v[39:40], s[4:5]
	v_fma_f64 v[41:42], v[20:21], v[41:42], s[4:5]
	v_fma_f64 v[43:44], v[16:17], v[43:44], s[0:1]
	v_add_f64 v[45:46], v[71:72], -v[45:46]
	v_mul_f64 v[71:72], v[8:9], -v[37:38]
	v_fma_f64 v[51:52], v[20:21], v[51:52], s[0:1]
	v_fma_f64 v[47:48], v[37:38], v[47:48], s[4:5]
	v_add_f64 v[49:50], v[83:84], -v[49:50]
	v_add_f64 v[53:54], v[85:86], -v[53:54]
	v_fma_f64 v[55:56], v[18:19], v[55:56], s[0:1]
	s_mov_b32 s5, 0x3fa55555
	s_mov_b32 s4, s2
	v_add_f64 v[59:60], v[87:88], -v[59:60]
	v_fma_f64 v[61:62], v[37:38], v[61:62], s[0:1]
	v_cmp_class_f64_e64 s0, v[4:5], 0x1f8
	v_lshlrev_b32_e32 v4, 30, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v4, v4, v5
	v_and_b32_e32 v4, 0x80000000, v4
	v_fma_f64 v[22:23], v[69:70], v[22:23], v[67:68]
	v_mul_f64 v[67:68], v[10:11], 0.5
	v_fma_f64 v[39:40], v[79:80], v[39:40], v[75:76]
	v_fma_f64 v[41:42], v[77:78], v[41:42], v[73:74]
	v_mul_f64 v[73:74], v[16:17], v[16:17]
	v_fma_f64 v[43:44], v[16:17], v[43:44], s[4:5]
	v_fma_f64 v[45:46], v[24:25], -v[26:27], v[45:46]
	v_fma_f64 v[51:52], v[20:21], v[51:52], s[4:5]
	v_fma_f64 v[49:50], v[12:13], -v[14:15], v[49:50]
	v_fma_f64 v[16:17], v[16:17], v[22:23], -v[26:27]
	v_fma_f64 v[47:48], v[71:72], v[47:48], v[67:68]
	v_fma_f64 v[39:40], v[18:19], v[39:40], -v[30:31]
	v_mul_f64 v[22:23], v[20:21], v[20:21]
	v_mul_f64 v[26:27], v[18:19], v[18:19]
	v_fma_f64 v[14:15], v[20:21], v[41:42], -v[14:15]
	v_fma_f64 v[18:19], v[18:19], v[55:56], s[4:5]
	v_fma_f64 v[20:21], v[28:29], -v[30:31], v[53:54]
	v_fma_f64 v[30:31], v[73:74], v[43:44], v[45:46]
	v_mul_f64 v[41:42], v[37:38], v[37:38]
	v_fma_f64 v[16:17], v[69:70], s[2:3], v[16:17]
	v_fma_f64 v[43:44], v[37:38], v[47:48], -v[10:11]
	v_fma_f64 v[39:40], v[79:80], s[2:3], v[39:40]
	v_fma_f64 v[37:38], v[37:38], v[61:62], s[4:5]
	v_fma_f64 v[10:11], v[8:9], -v[10:11], v[59:60]
	v_fma_f64 v[22:23], v[22:23], v[51:52], v[49:50]
	v_fma_f64 v[14:15], v[77:78], s[2:3], v[14:15]
	v_fma_f64 v[18:19], v[26:27], v[18:19], v[20:21]
	v_add_f64 v[20:21], v[57:58], v[30:31]
	v_add_f64 v[16:17], v[24:25], -v[16:17]
	v_fma_f64 v[24:25], v[71:72], s[2:3], v[43:44]
	v_add_f64 v[26:27], v[28:29], -v[39:40]
	v_fma_f64 v[10:11], v[41:42], v[37:38], v[10:11]
	v_add_f64 v[22:23], v[63:64], v[22:23]
	v_add_f64 v[12:13], v[12:13], -v[14:15]
	v_add_f64 v[14:15], v[65:66], v[18:19]
	v_and_b32_e32 v18, 1, v35
	v_and_b32_e32 v19, 1, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v18
	v_lshlrev_b32_e32 v18, 30, v36
	v_cmp_eq_u32_e64 s1, 0, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_and_b32_e32 v18, 0x80000000, v18
	v_cndmask_b32_e32 v16, v20, v16, vcc_lo
	v_and_b32_e32 v20, 1, v36
	v_add_f64 v[8:9], v[8:9], -v[24:25]
	v_xor_b32_e32 v19, 0x80000000, v27
	v_add_f64 v[10:11], v[81:82], v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e64 s2, 0, v20
	v_cndmask_b32_e64 v13, v23, v13, s1
	v_cndmask_b32_e64 v12, v22, v12, s1
	v_cndmask_b32_e64 v15, v19, v15, s2
	v_cndmask_b32_e64 v14, v26, v14, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v13, v13, v4
	v_cndmask_b32_e64 v12, 0, v12, s0
	v_cndmask_b32_e64 v4, 0, v16, s0
	v_xor_b32_e32 v15, v15, v18
	v_cndmask_b32_e64 v14, 0, v14, s0
	v_lshlrev_b32_e32 v16, 30, v32
	v_cndmask_b32_e64 v13, 0x7ff80000, v13, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v15, 0x7ff80000, v15, s0
	s_waitcnt vmcnt(0)
	v_mul_f64 v[12:13], v[2:3], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f64 v[14:15], v[2:3], v[14:15]
	v_lshlrev_b32_e32 v2, 30, v35
	v_and_b32_e32 v3, 1, v32
	v_xor_b32_e32 v2, v2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e64 s1, 0, v3
	v_and_b32_e32 v3, 0x80000000, v16
	v_and_b32_e32 v2, 0x80000000, v2
	v_xor_b32_e32 v5, 0x80000000, v9
	v_cndmask_b32_e32 v9, v21, v17, vcc_lo
	v_cndmask_b32_e64 v8, v8, v10, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v5, v5, v11, s1
	v_xor_b32_e32 v3, v5, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v5, v9, v2
	v_cndmask_b32_e64 v2, 0, v8, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v3, 0x7ff80000, v3, s0
	v_cndmask_b32_e64 v5, 0x7ff80000, v5, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[2:3], v[0:1], v[2:3], -v[12:13]
	v_fma_f64 v[4:5], v[0:1], v[4:5], v[14:15]
	v_add_co_u32 v0, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v7, vcc_lo
	global_store_b128 v[0:1], v[2:5], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8cMultPhiP15HIP_vector_typeIdLj2EEPdS1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 89
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8cMultPhiP15HIP_vector_typeIdLj2EEPdS1_, .Lfunc_end0-_Z8cMultPhiP15HIP_vector_typeIdLj2EEPdS1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5288
; NumSgprs: 18
; NumVgprs: 89
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 11
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 89
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8cMultPhiP15HIP_vector_typeIdLj2EEPdS1_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8cMultPhiP15HIP_vector_typeIdLj2EEPdS1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     89
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
