#include <stdio.h>
#include <time.h>
#define N 10

float max(float *timer, int n){
	int i = 0;
	float maxTimer=0.0;
	for( ; i < n ; i ++){
		if(timer[i] > maxTimer)maxTimer = timer[i];
	}
	return maxTimer;
}

void flush(float *a, int n){
	int i = 0;
	for( ; i < n ; i++){
		a[i] = 0.0;
	}
}

float sum(float *a, int n){
	float s = 0.0;
	int i = 0;
	for( ; i < N ; i++){
		s += a[i];
	}
	return s;	
}


__global__ void Sort(float *a, int n, float *ts, float *tx, int *signal){
	clock_t start0, finish0;
	clock_t start1, finish1;
	clock_t start2, finish2;

	int blockId = blockIdx.z * (gridDim.x * gridDim.y)
		    + blockIdx.y * gridDim.x
		    + blockIdx.x;
	
	start0 = clock();
	int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
		    + threadIdx.z * (blockDim.x * blockDim.y)
		    + threadIdx.y * blockDim.x
		    + threadIdx.x;
	finish0 = clock();
	ts[threadId] = finish0 - start0;

	float tmp = 0.0;
	float swap = 0.0;
	//even
	if(*signal > 0){
		if(threadId < n){
			if(threadId % 2 == 0){
				start1 = clock();
				tmp = a[threadId] - a[threadId + 1];
				finish1 = clock();
				swap = a[threadId + 1];
				if(tmp <= 0){
					start2 = clock();
					a[threadId + 1] = swap;
					finish2 = clock();
				}
				else{
					a[threadId + 1] = a[threadId];
					start2 = clock();
					a[threadId] = swap;
					finish2 = clock();
				}
				tx[threadId] = (finish2 - start2) + (finish1 - start1);
			}
		}
	}
	//odd
	if(*signal < 0){
		if(threadId + 1 < n){
			if(threadId % 2 == 1){
				start1 = clock();
				tmp = a[threadId] - a[threadId + 1];
				finish1 = clock();
				swap = a[threadId + 1];
				if(tmp <= 0){
					start2 = clock();
					a[threadId + 1] = swap;
					finish2 = clock();
				}
				else{
					a[threadId + 1] = a[threadId];	
					start2 = clock();
					a[threadId] = swap;
					finish2 = clock();
				}
				tx[threadId] = (finish2 - start2) + (finish1 - start1);
			}
		}
	}
}

int main(){
	float overhead = 0.0, TxSum = 0.0, TsSum = 0.0;
	int *signal = (int*)malloc(sizeof(int) * 1);
	float *a = (float*)malloc(sizeof(float) * N);
	float *Tx = (float*)malloc(sizeof(float) * N);
	float *Ts = (float*)malloc(sizeof(float) * N);
	float *ts = (float*)malloc(sizeof(float) * N);
	float *tx = (float*)malloc(sizeof(float) * N);
	signal[0] = 1;
	//intialization array a, Tx, Ts, tx, ts
	int i = 0, x = N-1;
	for( ; i < N ; i++){
		a[i] = (float)x;
		x--;
		Tx[i] = 0.0;
		Ts[i] = 0.0;
		tx[i] = 0.0;
		ts[i] = 0.0;
	}
	
	float *d_a, *d_ts, *d_tx;
	int *d_signal;	
	cudaMalloc(&d_a, sizeof(float) * N);
	cudaMalloc(&d_tx, sizeof(float) * N);
	cudaMalloc(&d_ts, sizeof(float) * N);
	cudaMalloc(&d_signal, sizeof(int) * 1);

	cudaMemcpy(d_a, a, sizeof(float)*N, cudaMemcpyHostToDevice);
	cudaMemcpy(d_tx, tx, sizeof(float)*N, cudaMemcpyHostToDevice);
	cudaMemcpy(d_ts, ts, sizeof(float)*N, cudaMemcpyHostToDevice);
	cudaMemcpy(d_signal, signal, sizeof(int)*1, cudaMemcpyHostToDevice);

	dim3 grid(1,1,1);
	dim3 block(N,1,1);
	//GPU 'warm up'
	Sort<<<grid, block>>>(d_a, N, d_ts, d_tx, d_signal);
	
	cudaMemcpy(d_a, a, sizeof(float)*N, cudaMemcpyHostToDevice);
	cudaMemcpy(d_tx, tx, sizeof(float)*N, cudaMemcpyHostToDevice);
	cudaMemcpy(d_ts, ts, sizeof(float)*N, cudaMemcpyHostToDevice);
	cudaMemcpy(d_signal, signal, sizeof(int) * 1, cudaMemcpyHostToDevice);
	
	i=0;
	int j = N - 1;	
	for( ; i < N ; i++, j--){

		Sort<<<grid, block>>>(d_a, N, d_ts, d_tx, d_signal);
		
		cudaMemcpy(ts, d_ts, sizeof(float) * N, cudaMemcpyDeviceToHost);
		Ts[j] = max(ts, N);
		flush(ts, N);
		cudaMemcpy(d_ts, ts, sizeof(float) * N, cudaMemcpyHostToDevice);	

		cudaMemcpy(tx, d_tx, sizeof(float) * N, cudaMemcpyDeviceToHost);
		Tx[j] = max(tx, N);
		flush(tx, N);
		cudaMemcpy(d_tx, tx, sizeof(float) * N, cudaMemcpyHostToDevice);

		*signal = *signal * (-1);
		cudaMemcpy(d_signal, signal, sizeof(int) * 1, cudaMemcpyHostToDevice);	
	}
	
	cudaMemcpy(a, d_a, sizeof(float) * N, cudaMemcpyDeviceToHost);
/*
	i = 0;
	for( ; i < N ; i ++){
		printf("a[%d] = %f ; ",i,a[i]);
		printf("\n");
	}
	
	i = 0;
	for( ; i < N ; i ++){
		printf("Tx[%d] = %f ; ",i,Tx[i]);
		printf("\n");
	}
	
	i = 0;
	for( ; i < N ; i ++){
		printf("Ts[%d] = %f ; ",i,Ts[i]);
		printf("\n");
	}
*/
	TxSum = sum(Tx, N);
	TsSum = sum(Ts, N);
	overhead = TxSum + TsSum;
	printf("TxSum = %f, TsSum = %f, overhead = %f \n", TxSum, TsSum, overhead);
	free(a); free(signal); free(Tx); free(Ts); free(ts); free(tx);
	cudaFree(d_a); cudaFree(d_ts); cudaFree(d_tx); cudaFree(d_signal);
	
		
	return 0;
}	





















	.file	"tmpxft_00257abb_00000000-6_sort.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2033:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z3maxPfi
	.type	_Z3maxPfi, @function
_Z3maxPfi:
.LFB2027:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
	xorps	%xmm0, %xmm0
.L3:
	cmpl	%eax, %esi
	jle	.L7
	movss	(%rdi,%rax,4), %xmm1
	incq	%rax
	maxss	%xmm0, %xmm1
	movaps	%xmm1, %xmm0
	jmp	.L3
.L7:
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z3maxPfi, .-_Z3maxPfi
	.globl	_Z5flushPfi
	.type	_Z5flushPfi, @function
_Z5flushPfi:
.LFB2028:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
.L9:
	cmpl	%eax, %esi
	jle	.L11
	movl	$0x00000000, (%rdi,%rax,4)
	incq	%rax
	jmp	.L9
.L11:
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z5flushPfi, .-_Z5flushPfi
	.globl	_Z3sumPfi
	.type	_Z3sumPfi, @function
_Z3sumPfi:
.LFB2029:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
	xorps	%xmm0, %xmm0
.L13:
	addss	(%rdi,%rax,4), %xmm0
	incq	%rax
	cmpq	$10, %rax
	jne	.L13
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z3sumPfi, .-_Z3sumPfi
	.globl	_Z30__device_stub__Z4SortPfiS_S_PiPfiS_S_Pi
	.type	_Z30__device_stub__Z4SortPfiS_S_PiPfiS_S_Pi, @function
_Z30__device_stub__Z4SortPfiS_S_PiPfiS_S_Pi:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z4SortPfiS_S_Pi(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L15:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z30__device_stub__Z4SortPfiS_S_PiPfiS_S_Pi, .-_Z30__device_stub__Z4SortPfiS_S_PiPfiS_S_Pi
	.globl	_Z4SortPfiS_S_Pi
	.type	_Z4SortPfiS_S_Pi, @function
_Z4SortPfiS_S_Pi:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z4SortPfiS_S_PiPfiS_S_Pi
	.cfi_endproc
.LFE2056:
	.size	_Z4SortPfiS_S_Pi, .-_Z4SortPfiS_S_Pi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"TxSum = %f, TsSum = %f, overhead = %f \n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$4, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$40, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$40, %edi
	movq	%rax, %r14
	call	malloc@PLT
	movl	$40, %edi
	movq	%rax, %r13
	call	malloc@PLT
	movl	$40, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$40, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movl	$1, 0(%rbp)
	xorl	%edx, %edx
	movl	$9, %ecx
	movq	%rax, 8(%rsp)
.L21:
	movl	%ecx, %eax
	subl	%edx, %eax
	cvtsi2ssl	%eax, %xmm0
	movss	%xmm0, (%r14,%rdx,4)
	incq	%rdx
	cmpq	$10, %rdx
	jne	.L21
	xorl	%eax, %eax
	movq	%rdx, %rcx
	movq	%r13, %rdi
	movl	$40, %esi
	rep stosl
	movq	%rdx, %rcx
	movq	%r12, %rdi
	rep stosl
	movq	8(%rsp), %rdi
	movq	%rdx, %rcx
	rep stosl
	movq	%rdx, %rcx
	movq	%rbx, %rdi
	rep stosl
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$40, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$40, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	$40, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rsi
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movl	$40, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$40, %edx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	$2147483653, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	addq	%rdx, %rdx
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rdi, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rdx, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	movq	40(%rsp), %r8
	movq	32(%rsp), %rcx
	movl	$10, %esi
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rdi
	call	_Z30__device_stub__Z4SortPfiS_S_PiPfiS_S_Pi
.L22:
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movl	$40, %edx
	movq	%r14, %rsi
	movl	$36, %r15d
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rsi
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movl	$40, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$40, %edx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$4, %edx
	call	cudaMemcpy@PLT
.L24:
	movl	68(%rsp), %ecx
	movq	60(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	48(%rsp), %rdi
	movl	56(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	movq	40(%rsp), %r8
	movq	32(%rsp), %rcx
	movl	$10, %esi
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rdi
	call	_Z30__device_stub__Z4SortPfiS_S_PiPfiS_S_Pi
.L23:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movl	$40, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	movl	$10, %esi
	movq	%rbx, %rdi
	movl	$1, %ecx
	call	_Z3maxPfi
	movl	$40, %edx
	movss	%xmm0, (%r12,%r15)
	call	_Z5flushPfi
	movq	24(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	$40, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	movl	$10, %esi
	movl	$1, %ecx
	movl	$40, %edx
	call	_Z3maxPfi
	movss	%xmm0, 0(%r13,%r15)
	subq	$4, %r15
	call	_Z5flushPfi
	movq	8(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	cudaMemcpy@PLT
	negl	0(%rbp)
	movq	40(%rsp), %rdi
	movq	%rbp, %rsi
	movl	$1, %ecx
	movl	$4, %edx
	call	cudaMemcpy@PLT
	cmpq	$-4, %r15
	jne	.L24
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movl	$40, %edx
	movq	%r14, %rdi
	call	cudaMemcpy@PLT
	movl	$10, %esi
	movq	%r13, %rdi
	call	_Z3sumPfi
	movq	%r12, %rdi
	movaps	%xmm0, %xmm3
	call	_Z3sumPfi
	movaps	%xmm3, %xmm2
	movl	$2, %edi
	movb	$3, %al
	addss	%xmm0, %xmm2
	leaq	.LC1(%rip), %rsi
	movaps	%xmm0, %xmm1
	cvtss2sd	%xmm3, %xmm0
	cvtss2sd	%xmm1, %xmm1
	cvtss2sd	%xmm2, %xmm2
	call	__printf_chk@PLT
	movq	%r14, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	free@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z4SortPfiS_S_Pi"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z4SortPfiS_S_Pi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2058:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#define N 10

float max(float *timer, int n){
	int i = 0;
	float maxTimer=0.0;
	for( ; i < n ; i ++){
		if(timer[i] > maxTimer)maxTimer = timer[i];
	}
	return maxTimer;
}

void flush(float *a, int n){
	int i = 0;
	for( ; i < n ; i++){
		a[i] = 0.0;
	}
}

float sum(float *a, int n){
	float s = 0.0;
	int i = 0;
	for( ; i < N ; i++){
		s += a[i];
	}
	return s;	
}


__global__ void Sort(float *a, int n, float *ts, float *tx, int *signal){
	clock_t start0, finish0;
	clock_t start1, finish1;
	clock_t start2, finish2;

	int blockId = blockIdx.z * (gridDim.x * gridDim.y)
		    + blockIdx.y * gridDim.x
		    + blockIdx.x;
	
	start0 = clock();
	int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
		    + threadIdx.z * (blockDim.x * blockDim.y)
		    + threadIdx.y * blockDim.x
		    + threadIdx.x;
	finish0 = clock();
	ts[threadId] = finish0 - start0;

	float tmp = 0.0;
	float swap = 0.0;
	//even
	if(*signal > 0){
		if(threadId < n){
			if(threadId % 2 == 0){
				start1 = clock();
				tmp = a[threadId] - a[threadId + 1];
				finish1 = clock();
				swap = a[threadId + 1];
				if(tmp <= 0){
					start2 = clock();
					a[threadId + 1] = swap;
					finish2 = clock();
				}
				else{
					a[threadId + 1] = a[threadId];
					start2 = clock();
					a[threadId] = swap;
					finish2 = clock();
				}
				tx[threadId] = (finish2 - start2) + (finish1 - start1);
			}
		}
	}
	//odd
	if(*signal < 0){
		if(threadId + 1 < n){
			if(threadId % 2 == 1){
				start1 = clock();
				tmp = a[threadId] - a[threadId + 1];
				finish1 = clock();
				swap = a[threadId + 1];
				if(tmp <= 0){
					start2 = clock();
					a[threadId + 1] = swap;
					finish2 = clock();
				}
				else{
					a[threadId + 1] = a[threadId];	
					start2 = clock();
					a[threadId] = swap;
					finish2 = clock();
				}
				tx[threadId] = (finish2 - start2) + (finish1 - start1);
			}
		}
	}
}

int main(){
	float overhead = 0.0, TxSum = 0.0, TsSum = 0.0;
	int *signal = (int*)malloc(sizeof(int) * 1);
	float *a = (float*)malloc(sizeof(float) * N);
	float *Tx = (float*)malloc(sizeof(float) * N);
	float *Ts = (float*)malloc(sizeof(float) * N);
	float *ts = (float*)malloc(sizeof(float) * N);
	float *tx = (float*)malloc(sizeof(float) * N);
	signal[0] = 1;
	//intialization array a, Tx, Ts, tx, ts
	int i = 0, x = N-1;
	for( ; i < N ; i++){
		a[i] = (float)x;
		x--;
		Tx[i] = 0.0;
		Ts[i] = 0.0;
		tx[i] = 0.0;
		ts[i] = 0.0;
	}
	
	float *d_a, *d_ts, *d_tx;
	int *d_signal;	
	hipMalloc(&d_a, sizeof(float) * N);
	hipMalloc(&d_tx, sizeof(float) * N);
	hipMalloc(&d_ts, sizeof(float) * N);
	hipMalloc(&d_signal, sizeof(int) * 1);

	hipMemcpy(d_a, a, sizeof(float)*N, hipMemcpyHostToDevice);
	hipMemcpy(d_tx, tx, sizeof(float)*N, hipMemcpyHostToDevice);
	hipMemcpy(d_ts, ts, sizeof(float)*N, hipMemcpyHostToDevice);
	hipMemcpy(d_signal, signal, sizeof(int)*1, hipMemcpyHostToDevice);

	dim3 grid(1,1,1);
	dim3 block(N,1,1);
	//GPU 'warm up'
	Sort<<<grid, block>>>(d_a, N, d_ts, d_tx, d_signal);
	
	hipMemcpy(d_a, a, sizeof(float)*N, hipMemcpyHostToDevice);
	hipMemcpy(d_tx, tx, sizeof(float)*N, hipMemcpyHostToDevice);
	hipMemcpy(d_ts, ts, sizeof(float)*N, hipMemcpyHostToDevice);
	hipMemcpy(d_signal, signal, sizeof(int) * 1, hipMemcpyHostToDevice);
	
	i=0;
	int j = N - 1;	
	for( ; i < N ; i++, j--){

		Sort<<<grid, block>>>(d_a, N, d_ts, d_tx, d_signal);
		
		hipMemcpy(ts, d_ts, sizeof(float) * N, hipMemcpyDeviceToHost);
		Ts[j] = max(ts, N);
		flush(ts, N);
		hipMemcpy(d_ts, ts, sizeof(float) * N, hipMemcpyHostToDevice);	

		hipMemcpy(tx, d_tx, sizeof(float) * N, hipMemcpyDeviceToHost);
		Tx[j] = max(tx, N);
		flush(tx, N);
		hipMemcpy(d_tx, tx, sizeof(float) * N, hipMemcpyHostToDevice);

		*signal = *signal * (-1);
		hipMemcpy(d_signal, signal, sizeof(int) * 1, hipMemcpyHostToDevice);	
	}
	
	hipMemcpy(a, d_a, sizeof(float) * N, hipMemcpyDeviceToHost);
/*
	i = 0;
	for( ; i < N ; i ++){
		printf("a[%d] = %f ; ",i,a[i]);
		printf("\n");
	}
	
	i = 0;
	for( ; i < N ; i ++){
		printf("Tx[%d] = %f ; ",i,Tx[i]);
		printf("\n");
	}
	
	i = 0;
	for( ; i < N ; i ++){
		printf("Ts[%d] = %f ; ",i,Ts[i]);
		printf("\n");
	}
*/
	TxSum = sum(Tx, N);
	TsSum = sum(Ts, N);
	overhead = TxSum + TsSum;
	printf("TxSum = %f, TsSum = %f, overhead = %f \n", TxSum, TsSum, overhead);
	free(a); free(signal); free(Tx); free(Ts); free(ts); free(tx);
	hipFree(d_a); hipFree(d_ts); hipFree(d_tx); hipFree(d_signal);
	
		
	return 0;
}	





















	.text
	.file	"sort.hip"
	.globl	_Z3maxPfi                       # -- Begin function _Z3maxPfi
	.type	_Z3maxPfi,@function
_Z3maxPfi:                              # @_Z3maxPfi
	.cfi_startproc
# %bb.0:
	testl	%esi, %esi
	jle	.LBB0_1
# %bb.2:                                # %.lr.ph.preheader
	movl	%esi, %eax
	xorps	%xmm1, %xmm1
	xorl	%ecx, %ecx
.LBB0_3:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movss	(%rdi,%rcx,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	maxss	%xmm1, %xmm0
	incq	%rcx
	movaps	%xmm0, %xmm1
	cmpq	%rcx, %rax
	jne	.LBB0_3
# %bb.4:                                # %._crit_edge
	retq
.LBB0_1:
	xorps	%xmm0, %xmm0
	retq
.Lfunc_end0:
	.size	_Z3maxPfi, .Lfunc_end0-_Z3maxPfi
	.cfi_endproc
                                        # -- End function
	.globl	_Z5flushPfi                     # -- Begin function _Z5flushPfi
	.type	_Z5flushPfi,@function
_Z5flushPfi:                            # @_Z5flushPfi
	.cfi_startproc
# %bb.0:
	testl	%esi, %esi
	jle	.LBB1_1
# %bb.2:                                # %.lr.ph.preheader
	movl	%esi, %edx
	shlq	$2, %rdx
	xorl	%esi, %esi
	jmp	memset@PLT                      # TAILCALL
.LBB1_1:                                # %._crit_edge
	retq
.Lfunc_end1:
	.size	_Z5flushPfi, .Lfunc_end1-_Z5flushPfi
	.cfi_endproc
                                        # -- End function
	.globl	_Z3sumPfi                       # -- Begin function _Z3sumPfi
	.type	_Z3sumPfi,@function
_Z3sumPfi:                              # @_Z3sumPfi
	.cfi_startproc
# %bb.0:
	xorps	%xmm0, %xmm0
	xorl	%eax, %eax
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	addss	(%rdi,%rax,4), %xmm0
	incq	%rax
	cmpq	$10, %rax
	jne	.LBB2_1
# %bb.2:
	retq
.Lfunc_end2:
	.size	_Z3sumPfi, .Lfunc_end2-_Z3sumPfi
	.cfi_endproc
                                        # -- End function
	.globl	_Z19__device_stub__SortPfiS_S_Pi # -- Begin function _Z19__device_stub__SortPfiS_S_Pi
	.type	_Z19__device_stub__SortPfiS_S_Pi,@function
_Z19__device_stub__SortPfiS_S_Pi:       # @_Z19__device_stub__SortPfiS_S_Pi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4SortPfiS_S_Pi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z19__device_stub__SortPfiS_S_Pi, .Lfunc_end3-_Z19__device_stub__SortPfiS_S_Pi
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$4, %edi
	callq	malloc
	movq	%rax, %rbx
	movl	$40, %edi
	callq	malloc
	movq	%rax, %r15
	movl	$1, %edi
	movl	$40, %esi
	callq	calloc@PLT
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	movl	$1, %edi
	movl	$40, %esi
	callq	calloc@PLT
	movq	%rax, %r12
	movl	$1, %edi
	movl	$40, %esi
	callq	calloc@PLT
	movq	%rax, %r13
	movl	$1, %edi
	movl	$40, %esi
	callq	calloc@PLT
	movq	%rax, %rbp
	movl	$1, (%rbx)
	movl	$9, %eax
	xorl	%ecx, %ecx
.LBB4_1:                                # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movss	%xmm0, (%r15,%rcx,4)
	decl	%eax
	incq	%rcx
	cmpq	$10, %rcx
	jne	.LBB4_1
# %bb.2:
	leaq	24(%rsp), %r14
	movl	$40, %esi
	movq	%r14, %rdi
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$40, %esi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$40, %esi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
	movq	(%r14), %rdi
	movl	$40, %edx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rsp, %rax
	movq	(%rax), %rdi
	movl	$40, %edx
	movq	%rbp, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rax
	movq	(%rax), %rdi
	movl	$40, %edx
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movl	$4, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	9(%rdi), %rdx
	xorl	%r14d, %r14d
	movl	$1, %esi
	movq	%rdx, 48(%rsp)                  # 8-byte Spill
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_4
# %bb.3:
	movq	24(%rsp), %rdi
	movq	8(%rsp), %rdx
	movq	(%rsp), %rcx
	movq	16(%rsp), %r8
	movl	$10, %esi
	callq	_Z19__device_stub__SortPfiS_S_Pi
.LBB4_4:
	movq	24(%rsp), %rdi
	movl	$40, %edx
	movq	%r15, 40(%rsp)                  # 8-byte Spill
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rdi
	movl	$40, %edx
	movq	%rbp, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	movl	$40, %edx
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	movl	$4, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$9, %r15d
.LBB4_5:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_8 Depth 2
                                        #     Child Loop BB4_10 Depth 2
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movq	48(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_7
# %bb.6:                                #   in Loop: Header=BB4_5 Depth=1
	movq	24(%rsp), %rdi
	movq	8(%rsp), %rdx
	movq	(%rsp), %rcx
	movq	16(%rsp), %r8
	movl	$10, %esi
	callq	_Z19__device_stub__SortPfiS_S_Pi
.LBB4_7:                                #   in Loop: Header=BB4_5 Depth=1
	movq	8(%rsp), %rsi
	movl	$40, %edx
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorps	%xmm0, %xmm0
	xorl	%eax, %eax
.LBB4_8:                                # %.lr.ph.i
                                        #   Parent Loop BB4_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movaps	%xmm0, %xmm1
	movss	(%r13,%rax,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	maxss	%xmm1, %xmm0
	incq	%rax
	cmpq	$10, %rax
	jne	.LBB4_8
# %bb.9:                                # %_Z3maxPfi.exit
                                        #   in Loop: Header=BB4_5 Depth=1
	movss	%xmm0, (%r12,%r15,4)
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%r13)
	movups	%xmm0, (%r13)
	movq	$0, 32(%r13)
	movq	8(%rsp), %rdi
	movl	$40, %edx
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rsi
	movl	$40, %edx
	movq	%rbp, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorps	%xmm0, %xmm0
	xorl	%eax, %eax
.LBB4_10:                               # %.lr.ph.i71
                                        #   Parent Loop BB4_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movaps	%xmm0, %xmm1
	movss	(%rbp,%rax,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	maxss	%xmm1, %xmm0
	incq	%rax
	cmpq	$10, %rax
	jne	.LBB4_10
# %bb.11:                               # %_Z3maxPfi.exit77
                                        #   in Loop: Header=BB4_5 Depth=1
	movq	32(%rsp), %rax                  # 8-byte Reload
	movss	%xmm0, (%rax,%r15,4)
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rbp)
	movups	%xmm0, (%rbp)
	movq	$0, 32(%rbp)
	movq	(%rsp), %rdi
	movl	$40, %edx
	movq	%rbp, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	negl	(%rbx)
	movq	16(%rsp), %rdi
	movl	$4, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	incl	%r14d
	decq	%r15
	cmpl	$10, %r14d
	jne	.LBB4_5
# %bb.12:
	movq	24(%rsp), %rsi
	movl	$40, %edx
	movq	40(%rsp), %r14                  # 8-byte Reload
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorps	%xmm2, %xmm2
	xorl	%eax, %eax
	movq	32(%rsp), %r15                  # 8-byte Reload
.LBB4_13:                               # =>This Inner Loop Header: Depth=1
	addss	(%r15,%rax,4), %xmm2
	incq	%rax
	cmpq	$10, %rax
	jne	.LBB4_13
# %bb.14:                               # %_Z3sumPfi.exit.preheader
	xorps	%xmm1, %xmm1
	xorl	%eax, %eax
.LBB4_15:                               # %_Z3sumPfi.exit
                                        # =>This Inner Loop Header: Depth=1
	addss	(%r12,%rax,4), %xmm1
	incq	%rax
	cmpq	$10, %rax
	jne	.LBB4_15
# %bb.16:                               # %_Z3sumPfi.exit85
	xorps	%xmm0, %xmm0
	cvtss2sd	%xmm2, %xmm0
	addss	%xmm1, %xmm2
	cvtss2sd	%xmm1, %xmm1
	cvtss2sd	%xmm2, %xmm2
	movl	$.L.str, %edi
	movb	$3, %al
	callq	printf
	movq	%r14, %rdi
	callq	free
	movq	%rbx, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	%r12, %rdi
	callq	free
	movq	%r13, %rdi
	callq	free
	movq	%rbp, %rdi
	callq	free
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4SortPfiS_S_Pi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z4SortPfiS_S_Pi,@object        # @_Z4SortPfiS_S_Pi
	.section	.rodata,"a",@progbits
	.globl	_Z4SortPfiS_S_Pi
	.p2align	3, 0x0
_Z4SortPfiS_S_Pi:
	.quad	_Z19__device_stub__SortPfiS_S_Pi
	.size	_Z4SortPfiS_S_Pi, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"TxSum = %f, TsSum = %f, overhead = %f \n"
	.size	.L.str, 40

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z4SortPfiS_S_Pi"
	.size	.L__unnamed_1, 17

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z19__device_stub__SortPfiS_S_Pi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z4SortPfiS_S_Pi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z4SortPfiS_S_Pi        ; -- Begin function _Z4SortPfiS_S_Pi
	.globl	_Z4SortPfiS_S_Pi
	.p2align	8
	.type	_Z4SortPfiS_S_Pi,@function
_Z4SortPfiS_S_Pi:                       ; @_Z4SortPfiS_S_Pi
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x10
	v_mov_b32_e32 v1, 0
	s_load_b64 s[2:3], s[0:1], 0x34
	s_getreg_b32 s12, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
	s_getreg_b32 s16, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
	s_waitcnt lgkmcnt(0)
	global_load_b32 v4, v1, s[8:9]
	s_mul_i32 s11, s11, s15
	v_bfe_u32 v1, v0, 20, 10
	s_add_i32 s11, s11, s14
	s_and_b32 s3, s3, 0xffff
	s_mul_i32 s10, s11, s10
	s_and_b32 s11, s2, 0xffff
	s_add_i32 s10, s10, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s10, s3, v[1:2]
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_lshr_b32 s10, s2, 16
	s_sub_u32 s2, s16, s12
	s_subb_u32 s3, 0, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_u64_u32 v[5:6], null, v2, s10, v[1:2]
	s_xor_b32 s10, s2, s3
	s_cls_i32 s12, s3
	s_ashr_i32 s10, s10, 31
	s_add_i32 s12, s12, -1
	s_add_i32 s10, s10, 32
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, v5, s11, v[0:1]
	s_min_u32 s11, s12, s10
	s_load_b32 s10, s[0:1], 0x8
	s_lshl_b64 s[2:3], s[2:3], s11
	s_min_u32 s2, s2, 1
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_or_b32 s2, s3, s2
	v_and_b32_e32 v7, 1, v2
	v_cvt_f32_i32_e32 v5, s2
	s_load_b64 s[2:3], s[0:1], 0x0
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_sub_i32 s0, 32, s11
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_ldexp_f32 v3, v5, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, s10, v2
	global_store_b32 v[5:6], v3, off
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_cmp_gt_i32 s0, 0
	v_cmp_eq_u32_e64 s0, 0, v7
	s_cselect_b32 s1, -1, 0
	s_and_b32 s1, s1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_4
; %bb.1:
	v_or_b32_e32 v3, 1, v2
	v_add_co_u32 v5, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	s_getreg_b32 s1, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
	s_mov_b32 s5, exec_lo
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s2, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	s_clause 0x1
	global_load_b32 v8, v[5:6], off
	global_load_b32 v9, v[3:4], off
	s_getreg_b32 s4, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
	global_load_b32 v7, v[3:4], off
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_nge_f32_e32 0, v8
	s_cbranch_execz .LBB0_3
; %bb.2:
	global_load_b32 v8, v[5:6], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[3:4], v8, off
	v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v6
.LBB0_3:
	s_or_b32 exec_lo, exec_lo, s5
	v_mov_b32_e32 v5, 0
	s_getreg_b32 s5, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
	s_waitcnt vmcnt(0)
	global_store_b32 v[3:4], v7, off
	s_getreg_b32 s11, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
	s_add_u32 s1, s1, s5
	global_load_b32 v4, v5, s[8:9]
	s_addc_u32 s5, 0, 0
	s_sub_u32 s1, s4, s1
	s_subb_u32 s5, 0, s5
	s_add_u32 s4, s1, s11
	s_addc_u32 s5, s5, 0
	v_add_co_u32 v5, vcc_lo, s6, v0
	s_xor_b32 s1, s4, s5
	s_cls_i32 s8, s5
	s_ashr_i32 s1, s1, 31
	s_add_i32 s8, s8, -1
	s_add_i32 s1, s1, 32
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v1, vcc_lo
	s_min_u32 s1, s8, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[4:5], s1
	s_sub_i32 s1, 32, s1
	s_min_u32 s4, s4, 1
	s_or_b32 s4, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v3, s4
	v_ldexp_f32 v3, v3, s1
	global_store_b32 v[5:6], v3, off
.LBB0_4:                                ; %Flow100
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_gt_i32_e32 0, v4
	s_cbranch_execz .LBB0_9
; %bb.5:
	v_add_nc_u32_e32 v3, 1, v2
	v_and_b32_e32 v2, 0x80000001, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s10, v3
	v_cmp_eq_u32_e64 s0, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_9
; %bb.6:
	v_mov_b32_e32 v4, 0
	s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	v_add_co_u32 v4, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s2, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	s_mov_b32 s2, exec_lo
	s_clause 0x1
	global_load_b32 v7, v[4:5], off
	global_load_b32 v8, v[2:3], off
	s_getreg_b32 s1, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
	global_load_b32 v6, v[2:3], off
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_nge_f32_e32 0, v7
	s_cbranch_execz .LBB0_8
; %bb.7:
	global_load_b32 v7, v[4:5], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[2:3], v7, off
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s2
	s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
	s_waitcnt vmcnt(0)
	global_store_b32 v[2:3], v6, off
	s_add_u32 s0, s0, s2
	s_addc_u32 s2, 0, 0
	s_getreg_b32 s3, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
	s_sub_u32 s0, s1, s0
	s_subb_u32 s1, 0, s2
	s_add_u32 s0, s0, s3
	s_addc_u32 s1, s1, 0
	v_add_co_u32 v0, vcc_lo, s6, v0
	s_xor_b32 s2, s0, s1
	s_cls_i32 s3, s1
	s_ashr_i32 s2, s2, 31
	s_add_i32 s3, s3, -1
	s_add_i32 s2, s2, 32
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_min_u32 s2, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[0:1], s2
	s_min_u32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s1, s0
	v_cvt_f32_i32_e32 v2, s0
	s_sub_i32 s0, 32, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_ldexp_f32 v2, v2, s0
	global_store_b32 v[0:1], v2, off
.LBB0_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4SortPfiS_S_Pi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 17
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z4SortPfiS_S_Pi, .Lfunc_end0-_Z4SortPfiS_S_Pi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 940
; NumSgprs: 19
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4SortPfiS_S_Pi
    .private_segment_fixed_size: 0
    .sgpr_count:     19
    .sgpr_spill_count: 0
    .symbol:         _Z4SortPfiS_S_Pi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
