# include <math.h>
# include <time.h>
# include <stdio.h>
# include <stdlib.h>
# include <iostream>
# include <sys/time.h>

# include "cuda_runtime.h"

using namespace std;

const int DIM = 1024, AS = 32, BS = 32;
const float sigma = 1.0;
const bool PRINT_RESULT = false;

/*
RBF Kernel Implementation on CPU.
Param @ sigma: the parameter sigma of RBF kernel;
      @ a, b, c: the input arrays and the output array;
      @ dim, as, bs: the size of the array, a should be of size as * dim, and b should be of size bs * dim.
*/
void RBF_CPU(float sigma, float a[][DIM], float b[][DIM], float c[], int dim, int as, int bs) {
    for (int i = 0; i < as; ++ i)
        for (int j = 0; j < bs; ++ j) {
            float Pvalue = 0.0;
            for (int k = 0; k < dim; ++ k)
                Pvalue += (a[i][k] - b[j][k]) * (a[i][k] - b[j][k]);
            c[i * bs + j] = exp(- Pvalue / (2 * sigma * sigma));
        }
}

/* 
Simple RBF Kernel Implementation.
Param @ sigma: the parameter sigma of RBF kernel;
      @ Md, Nd, Pd: the input values and the output array;
      @ dim: the dimension of features;
      @ Pdim: the width of the result array.
*/
__global__ void RBFKernel_Simple(float sigma, float *Md, float *Nd, float *Pd, int dim, int Pdim) {
    int tx = threadIdx.x;
    int ty = threadIdx.y;
    float Pvalue = 0.0;

    for (int k = 0; k < dim; ++ k) {
        float Mds = Md[tx * dim + k];
        float Nds = Nd[ty * dim + k];
        Pvalue += (Mds - Nds) * (Mds - Nds);
    }
    Pd[tx * Pdim + ty] = exp(- Pvalue / (2 * sigma * sigma));
}

/*
Wrapper function of Simple RBF Kernel Implementation.
Param @ sigma: the parameter sigma of RBF kernel;
      @ a, b, c: the input arrays and the output array;
      @ dim, as, bs: the size of the array, a should be of size as * dim, and b should be of size bs * dim.
Return @ the elapsed time of GPU calculation.
*/
float RBF_CUDA_Simple(float sigma, float a[][DIM], float b[][DIM], float c[], int dim, int as, int bs) {
    cudaEvent_t start, stop;
    float elapsedTime = 0;
    cudaEventCreate(&start);
    cudaEventCreate(&stop);

    dim3 block(as, bs);
    float *M, *N, *P;
    cudaMalloc((void **)&M, as * dim * sizeof(float));
    cudaMalloc((void **)&N, bs * dim * sizeof(float));
    cudaMalloc((void **)&P, as * bs * sizeof(float));

    cudaMemcpy(M, a, as * dim * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(N, b, bs * dim * sizeof(float), cudaMemcpyHostToDevice);

    cudaEventRecord(start, 0);
    RBFKernel_Simple <<<1, block>>> (sigma, M, N, P, dim, bs);
    cudaDeviceSynchronize();
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&elapsedTime, start, stop);

    cudaMemcpy(c, P, as * bs * sizeof(float), cudaMemcpyDeviceToHost);

    cudaEventDestroy(start);
    cudaEventDestroy(stop);

    cudaFree(M);
    cudaFree(N);
    cudaFree(P);

    return elapsedTime;
}

/* 
RBF Kernel Implementation based on tilling (width 2).
Param @ sigma: the parameter sigma of RBF kernel;
      @ Md, Nd, Pd: the input values and the output array;
      @ dim: the dimension of features;
      @ Pdim: the width of the result array.
*/
const int TILE_WIDTH_2 = 2;
__global__ void RBFKernel_Tilling_2(float sigma, float *Md, float *Nd, float *Pd, int dim, int Pdim) {
    int bx = blockIdx.x;
    int by = blockIdx.y;
    int tx = threadIdx.x;
    int ty = threadIdx.y;
    float Pvalue = 0.0;
    int Mrow = bx * TILE_WIDTH_2 + tx;
    int Nrow = by * TILE_WIDTH_2 + ty;
    __shared__ float Mds[TILE_WIDTH_2][TILE_WIDTH_2];
    __shared__ float Nds[TILE_WIDTH_2][TILE_WIDTH_2];

    for (int i = 0; i < dim / TILE_WIDTH_2; ++ i) {
        Mds[tx][ty] = Md[Mrow * dim + i * TILE_WIDTH_2 + ty];
        Nds[ty][tx] = Nd[Nrow * dim + i * TILE_WIDTH_2 + tx];
        __syncthreads();
        for (int k = 0; k < TILE_WIDTH_2; ++ k)
            Pvalue += (Mds[tx][k] - Nds[ty][k]) * (Mds[tx][k] - Nds[ty][k]);
        __syncthreads();
    }
    Pd[Mrow * Pdim + Nrow] = exp(- Pvalue / (2 * sigma * sigma));
}

/*
Wrapper function of RBF Kernel Implementation based on tilling (width 2).
Param @ sigma: the parameter sigma of RBF kernel;
      @ a, b, c: the input arrays and the output array;
      @ dim, as, bs: the size of the array, a should be of size as * dim, and b should be of size bs * dim.
Return @ the elapsed time of GPU calculation.
*/
float RBF_CUDA_Tilling_2(float sigma, float a[][DIM], float b[][DIM], float c[], int dim, int as, int bs) {
    cudaEvent_t start, stop;
    float elapsedTime = 0;
    cudaEventCreate(&start);
    cudaEventCreate(&stop);

    dim3 grid(as / TILE_WIDTH_2, bs / TILE_WIDTH_2);
    dim3 block(TILE_WIDTH_2, TILE_WIDTH_2);
    float *M, *N, *P;
    cudaMalloc((void **)&M, as * dim * sizeof(float));
    cudaMalloc((void **)&N, bs * dim * sizeof(float));
    cudaMalloc((void **)&P, as * bs * sizeof(float));

    cudaMemcpy(M, a, as * dim * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(N, b, bs * dim * sizeof(float), cudaMemcpyHostToDevice);

    cudaEventRecord(start, 0);
    RBFKernel_Tilling_2 <<<grid, block>>> (sigma, M, N, P, dim, bs);
    cudaDeviceSynchronize();
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&elapsedTime, start, stop);

    cudaMemcpy(c, P, as * bs * sizeof(float), cudaMemcpyDeviceToHost);

    cudaEventDestroy(start);
    cudaEventDestroy(stop);

    cudaFree(M);
    cudaFree(N);
    cudaFree(P);

    return elapsedTime;
}

/* 
RBF Kernel Implementation based on tilling (width 4).
Param @ sigma: the parameter sigma of RBF kernel;
      @ Md, Nd, Pd: the input values and the output array;
      @ dim: the dimension of features;
      @ Pdim: the width of the result array.
*/
const int TILE_WIDTH_4 = 4;
__global__ void RBFKernel_Tilling_4(float sigma, float *Md, float *Nd, float *Pd, int dim, int Pdim) {
    int bx = blockIdx.x;
    int by = blockIdx.y;
    int tx = threadIdx.x;
    int ty = threadIdx.y;
    float Pvalue = 0.0;
    int Mrow = bx * TILE_WIDTH_4 + tx;
    int Nrow = by * TILE_WIDTH_4 + ty;
    __shared__ float Mds[TILE_WIDTH_4][TILE_WIDTH_4];
    __shared__ float Nds[TILE_WIDTH_4][TILE_WIDTH_4];

    for (int i = 0; i < dim / TILE_WIDTH_4; ++ i) {
        Mds[tx][ty] = Md[Mrow * dim + i * TILE_WIDTH_4 + ty];
        Nds[ty][tx] = Nd[Nrow * dim + i * TILE_WIDTH_4 + tx];
        __syncthreads();
        for (int k = 0; k < TILE_WIDTH_4; ++ k)
            Pvalue += (Mds[tx][k] - Nds[ty][k]) * (Mds[tx][k] - Nds[ty][k]);
        __syncthreads();
    }
    Pd[Mrow * Pdim + Nrow] = exp(- Pvalue / (2 * sigma * sigma));
}

/*
Wrapper function of RBF Kernel Implementation based on tilling (width 4).
Param @ sigma: the parameter sigma of RBF kernel;
      @ a, b, c: the input arrays and the output array;
      @ dim, as, bs: the size of the array, a should be of size as * dim, and b should be of size bs * dim.
Return @ the elapsed time of GPU calculation.
*/
float RBF_CUDA_Tilling_4(float sigma, float a[][DIM], float b[][DIM], float c[], int dim, int as, int bs) {
    cudaEvent_t start, stop;
    float elapsedTime = 0;
    cudaEventCreate(&start);
    cudaEventCreate(&stop);

    dim3 grid(as / TILE_WIDTH_4, bs / TILE_WIDTH_4);
    dim3 block(TILE_WIDTH_4, TILE_WIDTH_4);
    float *M, *N, *P;
    cudaMalloc((void **)&M, as * dim * sizeof(float));
    cudaMalloc((void **)&N, bs * dim * sizeof(float));
    cudaMalloc((void **)&P, as * bs * sizeof(float));

    cudaMemcpy(M, a, as * dim * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(N, b, bs * dim * sizeof(float), cudaMemcpyHostToDevice);

    cudaEventRecord(start, 0);
    RBFKernel_Tilling_4 <<<grid, block>>> (sigma, M, N, P, dim, bs);
    cudaDeviceSynchronize();
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&elapsedTime, start, stop);

    cudaMemcpy(c, P, as * bs * sizeof(float), cudaMemcpyDeviceToHost);

    cudaEventDestroy(start);
    cudaEventDestroy(stop);

    cudaFree(M);
    cudaFree(N);
    cudaFree(P);

    return elapsedTime;
}

/* 
RBF Kernel Implementation based on tilling (width 8).
Param @ sigma: the parameter sigma of RBF kernel;
      @ Md, Nd, Pd: the input values and the output array;
      @ dim: the dimension of features;
      @ Pdim: the width of the result array.
*/
const int TILE_WIDTH_8 = 8;
__global__ void RBFKernel_Tilling_8(float sigma, float *Md, float *Nd, float *Pd, int dim, int Pdim) {
    int bx = blockIdx.x;
    int by = blockIdx.y;
    int tx = threadIdx.x;
    int ty = threadIdx.y;
    float Pvalue = 0.0;
    int Mrow = bx * TILE_WIDTH_8 + tx;
    int Nrow = by * TILE_WIDTH_8 + ty;
    __shared__ float Mds[TILE_WIDTH_8][TILE_WIDTH_8];
    __shared__ float Nds[TILE_WIDTH_8][TILE_WIDTH_8];

    for (int i = 0; i < dim / TILE_WIDTH_8; ++ i) {
        Mds[tx][ty] = Md[Mrow * dim + i * TILE_WIDTH_8 + ty];
        Nds[ty][tx] = Nd[Nrow * dim + i * TILE_WIDTH_8 + tx];
        __syncthreads();
        for (int k = 0; k < TILE_WIDTH_8; ++ k)
            Pvalue += (Mds[tx][k] - Nds[ty][k]) * (Mds[tx][k] - Nds[ty][k]);
        __syncthreads();
    }
    Pd[Mrow * Pdim + Nrow] = exp(- Pvalue / (2 * sigma * sigma));
}

/*
Wrapper function of RBF Kernel Implementation based on tilling (width 8).
Param @ sigma: the parameter sigma of RBF kernel;
      @ a, b, c: the input arrays and the output array;
      @ dim, as, bs: the size of the array, a should be of size as * dim, and b should be of size bs * dim.
Return @ the elapsed time of GPU calculation.
*/
float RBF_CUDA_Tilling_8(float sigma, float a[][DIM], float b[][DIM], float c[], int dim, int as, int bs) {
    cudaEvent_t start, stop;
    float elapsedTime = 0;
    cudaEventCreate(&start);
    cudaEventCreate(&stop);

    dim3 grid(as / TILE_WIDTH_8, bs / TILE_WIDTH_8);
    dim3 block(TILE_WIDTH_8, TILE_WIDTH_8);
    float *M, *N, *P;
    cudaMalloc((void **)&M, as * dim * sizeof(float));
    cudaMalloc((void **)&N, bs * dim * sizeof(float));
    cudaMalloc((void **)&P, as * bs * sizeof(float));

    cudaMemcpy(M, a, as * dim * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(N, b, bs * dim * sizeof(float), cudaMemcpyHostToDevice);

    cudaEventRecord(start, 0);
    RBFKernel_Tilling_8 <<<grid, block>>> (sigma, M, N, P, dim, bs);
    cudaDeviceSynchronize();
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&elapsedTime, start, stop);

    cudaMemcpy(c, P, as * bs * sizeof(float), cudaMemcpyDeviceToHost);

    cudaEventDestroy(start);
    cudaEventDestroy(stop);

    cudaFree(M);
    cudaFree(N);
    cudaFree(P);

    return elapsedTime;
}

/* 
RBF Kernel Implementation based on tilling (width 16).
Param @ sigma: the parameter sigma of RBF kernel;
      @ Md, Nd, Pd: the input values and the output array;
      @ dim: the dimension of features;
      @ Pdim: the width of the result array.
*/
const int TILE_WIDTH_16 = 16;
__global__ void RBFKernel_Tilling_16(float sigma, float *Md, float *Nd, float *Pd, int dim, int Pdim) {
    int bx = blockIdx.x;
    int by = blockIdx.y;
    int tx = threadIdx.x;
    int ty = threadIdx.y;
    float Pvalue = 0.0;
    int Mrow = bx * TILE_WIDTH_16 + tx;
    int Nrow = by * TILE_WIDTH_16 + ty;
    __shared__ float Mds[TILE_WIDTH_16][TILE_WIDTH_16];
    __shared__ float Nds[TILE_WIDTH_16][TILE_WIDTH_16];

    for (int i = 0; i < dim / TILE_WIDTH_16; ++ i) {
        Mds[tx][ty] = Md[Mrow * dim + i * TILE_WIDTH_16 + ty];
        Nds[ty][tx] = Nd[Nrow * dim + i * TILE_WIDTH_16 + tx];
        __syncthreads();
        for (int k = 0; k < TILE_WIDTH_16; ++ k)
            Pvalue += (Mds[tx][k] - Nds[ty][k]) * (Mds[tx][k] - Nds[ty][k]);
        __syncthreads();
    }
    Pd[Mrow * Pdim + Nrow] = exp(- Pvalue / (2 * sigma * sigma));
}

/*
Wrapper function of RBF Kernel Implementation based on tilling (width 16).
Param @ sigma: the parameter sigma of RBF kernel;
      @ a, b, c: the input arrays and the output array;
      @ dim, as, bs: the size of the array, a should be of size as * dim, and b should be of size bs * dim.
Return @ the elapsed time of GPU calculation.
*/
float RBF_CUDA_Tilling_16(float sigma, float a[][DIM], float b[][DIM], float c[], int dim, int as, int bs) {
    cudaEvent_t start, stop;
    float elapsedTime = 0;
    cudaEventCreate(&start);
    cudaEventCreate(&stop);

    dim3 grid(as / TILE_WIDTH_16, bs / TILE_WIDTH_16);
    dim3 block(TILE_WIDTH_16, TILE_WIDTH_16);
    float *M, *N, *P;
    cudaMalloc((void **)&M, as * dim * sizeof(float));
    cudaMalloc((void **)&N, bs * dim * sizeof(float));
    cudaMalloc((void **)&P, as * bs * sizeof(float));

    cudaMemcpy(M, a, as * dim * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(N, b, bs * dim * sizeof(float), cudaMemcpyHostToDevice);

    cudaEventRecord(start, 0);
    RBFKernel_Tilling_16 <<<grid, block>>> (sigma, M, N, P, dim, bs);
    cudaDeviceSynchronize();
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&elapsedTime, start, stop);

    cudaMemcpy(c, P, as * bs * sizeof(float), cudaMemcpyDeviceToHost);

    cudaEventDestroy(start);
    cudaEventDestroy(stop);

    cudaFree(M);
    cudaFree(N);
    cudaFree(P);

    return elapsedTime;
}

/* 
RBF Kernel Implementation based on tilling (width 32).
Param @ sigma: the parameter sigma of RBF kernel;
      @ Md, Nd, Pd: the input values and the output array;
      @ dim: the dimension of features;
      @ Pdim: the width of the result array.
*/
const int TILE_WIDTH_32 = 32;
__global__ void RBFKernel_Tilling_32(float sigma, float *Md, float *Nd, float *Pd, int dim, int Pdim) {
    int bx = blockIdx.x;
    int by = blockIdx.y;
    int tx = threadIdx.x;
    int ty = threadIdx.y;
    float Pvalue = 0.0;
    int Mrow = bx * TILE_WIDTH_32 + tx;
    int Nrow = by * TILE_WIDTH_32 + ty;
    __shared__ float Mds[TILE_WIDTH_32][TILE_WIDTH_32];
    __shared__ float Nds[TILE_WIDTH_32][TILE_WIDTH_32];

    for (int i = 0; i < dim / TILE_WIDTH_32; ++ i) {
        Mds[tx][ty] = Md[Mrow * dim + i * TILE_WIDTH_32 + ty];
        Nds[ty][tx] = Nd[Nrow * dim + i * TILE_WIDTH_32 + tx];
        __syncthreads();
        for (int k = 0; k < TILE_WIDTH_32; ++ k)
            Pvalue += (Mds[tx][k] - Nds[ty][k]) * (Mds[tx][k] - Nds[ty][k]);
        __syncthreads();
    }
    Pd[Mrow * Pdim + Nrow] = exp(- Pvalue / (2 * sigma * sigma));
}

/*
Wrapper function of RBF Kernel Implementation based on tilling (width 32).
Param @ sigma: the parameter sigma of RBF kernel;
      @ a, b, c: the input arrays and the output array;
      @ dim, as, bs: the size of the array, a should be of size as * dim, and b should be of size bs * dim.
Return @ the elapsed time of GPU calculation.
*/
float RBF_CUDA_Tilling_32(float sigma, float a[][DIM], float b[][DIM], float c[], int dim, int as, int bs) {
    cudaEvent_t start, stop;
    float elapsedTime = 0;
    cudaEventCreate(&start);
    cudaEventCreate(&stop);

    dim3 grid(as / TILE_WIDTH_32, bs / TILE_WIDTH_32);
    dim3 block(TILE_WIDTH_32, TILE_WIDTH_32);
    float *M, *N, *P;
    cudaMalloc((void **)&M, as * dim * sizeof(float));
    cudaMalloc((void **)&N, bs * dim * sizeof(float));
    cudaMalloc((void **)&P, as * bs * sizeof(float));

    cudaMemcpy(M, a, as * dim * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(N, b, bs * dim * sizeof(float), cudaMemcpyHostToDevice);

    cudaEventRecord(start, 0);
    RBFKernel_Tilling_32 <<<grid, block>>> (sigma, M, N, P, dim, bs);
    cudaDeviceSynchronize();
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&elapsedTime, start, stop);

    cudaMemcpy(c, P, as * bs * sizeof(float), cudaMemcpyDeviceToHost);

    cudaEventDestroy(start);
    cudaEventDestroy(stop);

    cudaFree(M);
    cudaFree(N);
    cudaFree(P);

    return elapsedTime;
}

// Print the result array.
void prtResult(float res[], int n, int m) {
    if (PRINT_RESULT) {
        printf("Result: \n");
        for (int i = 0; i < n; ++ i, printf("\n"))
            for (int j = 0; j < m; ++ j) 
                printf("%.2lf ", res[i * m + j]);
    } else {
        float sum = 0.0;
        for (int i = 0; i < n * m; ++ i)
            sum += res[i];
        printf("The sum of the matrix: %.2lf\n", sum);
    }
}

int main() {
    // Randomly generate array for testing.
    srand(time(0));
    float a[AS][DIM], b[BS][DIM];

    for (int i = 0; i < AS; ++ i)
        for (int j = 0; j < DIM; ++ j)
            a[i][j] = 1.0 / (rand() % 500 + 1.0);
    for (int i = 0; i < BS; ++ i)
        for (int j = 0; j < DIM; ++ j)
            b[i][j] = 1.0 / (rand() % 500 + 1.0);
    
    // ============================================================ //
    double duration; // execution time
    timeval start, end; // since clock() is not accurate, we use gettimeofday(...) in 'sys/time.h' to calculate running time.

    // => Baseline: CPU
    float c_CPU[AS * BS];
    gettimeofday(&start, 0);
    RBF_CPU(sigma, a, b, c_CPU, DIM, AS, BS);
    gettimeofday(&end, 0);
    duration = (end.tv_sec - start.tv_sec) * 1e6 + (end.tv_usec - start.tv_usec);
    prtResult(c_CPU, AS, BS);
    printf("CPU method running time: %.2f us\n", duration);
    
    // ==> CUDA, Simple
    float c_GPU_simple[AS * BS];
    float elapsedTime_simple = RBF_CUDA_Simple(sigma, a, b, c_GPU_simple, DIM, AS, BS);
    prtResult(c_GPU_simple, AS, BS);
    printf("GPU simple method running time: %.2f us\n", elapsedTime_simple * 1e3);

    // ===> CUDA, Tilling (tile width = 2)
    float c_GPU_tilling_2[AS * BS];
    float elapsedTime_tilling_2 = RBF_CUDA_Tilling_2(sigma, a, b, c_GPU_tilling_2, DIM, AS, BS);
    prtResult(c_GPU_tilling_2, AS, BS);
    printf("GPU tilling method (width 2) running time: %.2f us\n", elapsedTime_tilling_2 * 1e3);

    // ===> CUDA, Tilling (tile width = 4)
    float c_GPU_tilling_4[AS * BS];
    float elapsedTime_tilling_4 = RBF_CUDA_Tilling_4(sigma, a, b, c_GPU_tilling_4, DIM, AS, BS);
    prtResult(c_GPU_tilling_4, AS, BS);
    printf("GPU tilling method (width 4) running time: %.2f us\n", elapsedTime_tilling_4 * 1e3);

    // ===> CUDA, Tilling (tile width = 8)
    float c_GPU_tilling_8[AS * BS];
    float elapsedTime_tilling_8 = RBF_CUDA_Tilling_8(sigma, a, b, c_GPU_tilling_8, DIM, AS, BS);
    prtResult(c_GPU_tilling_8, AS, BS);
    printf("GPU tilling method (width 8) running time: %.2f us\n", elapsedTime_tilling_8 * 1e3);

    // ===> CUDA, Tilling (tile width = 16)
    float c_GPU_tilling_16[AS * BS];
    float elapsedTime_tilling_16 = RBF_CUDA_Tilling_16(sigma, a, b, c_GPU_tilling_16, DIM, AS, BS);
    prtResult(c_GPU_tilling_16, AS, BS);
    printf("GPU tilling method (width 16) running time: %.2f us\n", elapsedTime_tilling_16 * 1e3);

    // ===> CUDA, Tilling (tile width = 32)
    float c_GPU_tilling_32[AS * BS];
    float elapsedTime_tilling_32 = RBF_CUDA_Tilling_32(sigma, a, b, c_GPU_tilling_32, DIM, AS, BS);
    prtResult(c_GPU_tilling_32, AS, BS);
    printf("GPU tilling method (width 32) running time: %.2f us\n", elapsedTime_tilling_32 * 1e3);

    return 0;
}

	.file	"tmpxft_00395590_00000000-6_rbf.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3646:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3646:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z7RBF_CPUfPA1024_fS0_Pfiii
	.type	_Z7RBF_CPUfPA1024_fS0_Pfiii, @function
_Z7RBF_CPUfPA1024_fS0_Pfiii:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movaps	%xmm0, %xmm2
	movq	%rdx, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%r9d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rdi, %rbx
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	movl	%ecx, 8(%rsp)
	movq	%rsi, (%rsp)
	xorl	%esi, %esi
.L3:
	cmpl	%r8d, %esi
	jge	.L2
	movslq	%r12d, %rax
	movq	(%rsp), %rcx
	xorl	%r13d, %r13d
	leaq	(%r15,%rax,4), %rbp
.L8:
	cmpl	%r13d, %r14d
	jle	.L5
	xorl	%eax, %eax
	xorps	%xmm0, %xmm0
.L6:
	cmpl	%eax, 8(%rsp)
	jle	.L11
	movss	(%rbx,%rax,4), %xmm1
	subss	(%rcx,%rax,4), %xmm1
	incq	%rax
	mulss	%xmm1, %xmm1
	addss	%xmm1, %xmm0
	jmp	.L6
.L11:
	movaps	%xmm2, %xmm1
	xorps	.LC1(%rip), %xmm0
	movl	%r8d, 28(%rsp)
	addss	%xmm2, %xmm1
	movq	%rcx, 16(%rsp)
	movl	%esi, 24(%rsp)
	movss	%xmm2, 12(%rsp)
	mulss	%xmm2, %xmm1
	divss	%xmm1, %xmm0
	call	expf@PLT
	movq	16(%rsp), %rcx
	movl	28(%rsp), %r8d
	movss	%xmm0, 0(%rbp,%r13,4)
	movl	24(%rsp), %esi
	movss	12(%rsp), %xmm2
	incq	%r13
	addq	$4096, %rcx
	jmp	.L8
.L5:
	incl	%esi
	addl	%r14d, %r12d
	addq	$4096, %rbx
	jmp	.L3
.L2:
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z7RBF_CPUfPA1024_fS0_Pfiii, .-_Z7RBF_CPUfPA1024_fS0_Pfiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"The sum of the matrix: %.2lf\n"
	.text
	.globl	_Z9prtResultPfii
	.type	_Z9prtResultPfii, @function
_Z9prtResultPfii:
.LFB3642:
	.cfi_startproc
	endbr64
	imull	%edx, %esi
	xorl	%eax, %eax
	xorps	%xmm0, %xmm0
.L13:
	cmpl	%eax, %esi
	jle	.L15
	addss	(%rdi,%rax,4), %xmm0
	incq	%rax
	jmp	.L13
.L15:
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	%xmm0, %xmm0
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE3642:
	.size	_Z9prtResultPfii, .-_Z9prtResultPfii
	.globl	_Z43__device_stub__Z16RBFKernel_SimplefPfS_S_iifPfS_S_ii
	.type	_Z43__device_stub__Z16RBFKernel_SimplefPfS_S_iifPfS_S_ii, @function
_Z43__device_stub__Z16RBFKernel_SimplefPfS_S_iifPfS_S_ii:
.LFB3668:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 32(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 24(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 40(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movss	%xmm0, 44(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z16RBFKernel_SimplefPfS_S_ii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L16:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3668:
	.size	_Z43__device_stub__Z16RBFKernel_SimplefPfS_S_iifPfS_S_ii, .-_Z43__device_stub__Z16RBFKernel_SimplefPfS_S_iifPfS_S_ii
	.globl	_Z16RBFKernel_SimplefPfS_S_ii
	.type	_Z16RBFKernel_SimplefPfS_S_ii, @function
_Z16RBFKernel_SimplefPfS_S_ii:
.LFB3669:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z16RBFKernel_SimplefPfS_S_iifPfS_S_ii
	.cfi_endproc
.LFE3669:
	.size	_Z16RBFKernel_SimplefPfS_S_ii, .-_Z16RBFKernel_SimplefPfS_S_ii
	.globl	_Z15RBF_CUDA_SimplefPA1024_fS0_Pfiii
	.type	_Z15RBF_CUDA_SimplefPA1024_fS0_Pfiii, @function
_Z15RBF_CUDA_SimplefPA1024_fS0_Pfiii:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%r8d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%r9d, %ebx
	movl	%ebx, %ebp
	imull	%r12d, %ebp
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdi
	movss	%xmm0, 28(%rsp)
	movslq	%ebp, %rbp
	salq	$2, %rbp
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	movl	$0x00000000, 36(%rsp)
	call	cudaEventCreate@PLT
	leaq	48(%rsp), %rdi
	call	cudaEventCreate@PLT
	movl	%r13d, %edx
	leaq	56(%rsp), %rdi
	movl	%r13d, 80(%rsp)
	imull	%r12d, %edx
	movl	%ebx, 84(%rsp)
	movl	$1, 88(%rsp)
	movslq	%edx, %rdx
	salq	$2, %rdx
	movq	%rdx, %rsi
	movq	%rdx, 16(%rsp)
	call	cudaMalloc@PLT
	leaq	64(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	movl	%r13d, %r8d
	leaq	72(%rsp), %rdi
	imull	%ebx, %r8d
	movslq	%r8d, %r8
	leaq	0(,%r8,4), %rax
	movq	%rax, %rsi
	movq	%rax, %r13
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdx
	movq	56(%rsp), %rdi
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	64(%rsp), %rdi
	movq	%rbp, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	88(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	80(%rsp), %rdx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	call	__cudaPushCallConfiguration@PLT
	movss	28(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L22
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	%ebx, %r8d
	movl	%r12d, %ecx
	movq	56(%rsp), %rdi
	call	_Z43__device_stub__Z16RBFKernel_SimplefPfS_S_iifPfS_S_ii
.L22:
	call	cudaDeviceSynchronize@PLT
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	48(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rsi
	leaq	36(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	72(%rsp), %rsi
	movq	8(%rsp), %rdi
	movq	%r13, %rdx
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	48(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movss	36(%rsp), %xmm0
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L23
	call	__stack_chk_fail@PLT
.L23:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	_Z15RBF_CUDA_SimplefPA1024_fS0_Pfiii, .-_Z15RBF_CUDA_SimplefPA1024_fS0_Pfiii
	.globl	_Z46__device_stub__Z19RBFKernel_Tilling_2fPfS_S_iifPfS_S_ii
	.type	_Z46__device_stub__Z19RBFKernel_Tilling_2fPfS_S_iifPfS_S_ii, @function
_Z46__device_stub__Z19RBFKernel_Tilling_2fPfS_S_iifPfS_S_ii:
.LFB3670:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 32(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 24(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 40(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movss	%xmm0, 44(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z19RBFKernel_Tilling_2fPfS_S_ii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L25:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3670:
	.size	_Z46__device_stub__Z19RBFKernel_Tilling_2fPfS_S_iifPfS_S_ii, .-_Z46__device_stub__Z19RBFKernel_Tilling_2fPfS_S_iifPfS_S_ii
	.globl	_Z19RBFKernel_Tilling_2fPfS_S_ii
	.type	_Z19RBFKernel_Tilling_2fPfS_S_ii, @function
_Z19RBFKernel_Tilling_2fPfS_S_ii:
.LFB3671:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z19RBFKernel_Tilling_2fPfS_S_iifPfS_S_ii
	.cfi_endproc
.LFE3671:
	.size	_Z19RBFKernel_Tilling_2fPfS_S_ii, .-_Z19RBFKernel_Tilling_2fPfS_S_ii
	.globl	_Z18RBF_CUDA_Tilling_2fPA1024_fS0_Pfiii
	.type	_Z18RBF_CUDA_Tilling_2fPA1024_fS0_Pfiii, @function
_Z18RBF_CUDA_Tilling_2fPA1024_fS0_Pfiii:
.LFB3637:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%r9d, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%r8d, %ebx
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movss	%xmm0, 28(%rsp)
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	movl	$0x00000000, 36(%rsp)
	call	cudaEventCreate@PLT
	leaq	48(%rsp), %rdi
	call	cudaEventCreate@PLT
	movl	%ebx, %eax
	movl	$2, %ecx
	leaq	56(%rsp), %rdi
	cltd
	movl	$1, 88(%rsp)
	idivl	%ecx
	movl	$1, 100(%rsp)
	movl	%eax, 80(%rsp)
	movl	%ebp, %eax
	cltd
	idivl	%ecx
	movl	%ebx, %edx
	imull	%ebp, %ebx
	imull	%r12d, %edx
	movslq	%ebx, %rbx
	movslq	%edx, %rdx
	salq	$2, %rbx
	salq	$2, %rdx
	movq	%rdx, %rsi
	movq	%rdx, 16(%rsp)
	movl	%eax, 84(%rsp)
	movabsq	$8589934594, %rax
	movq	%rax, 92(%rsp)
	call	cudaMalloc@PLT
	movl	%ebp, %eax
	leaq	64(%rsp), %rdi
	imull	%r12d, %eax
	cltq
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	leaq	72(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdx
	movq	56(%rsp), %rdi
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	64(%rsp), %rdi
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	100(%rsp), %ecx
	movl	88(%rsp), %esi
	xorl	%r9d, %r9d
	movq	92(%rsp), %rdx
	movq	80(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	movss	28(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L31
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	%ebp, %r8d
	movl	%r12d, %ecx
	movq	56(%rsp), %rdi
	call	_Z46__device_stub__Z19RBFKernel_Tilling_2fPfS_S_iifPfS_S_ii
.L31:
	call	cudaDeviceSynchronize@PLT
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	48(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rsi
	leaq	36(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	72(%rsp), %rsi
	movq	%rbx, %rdx
	movq	%r13, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	48(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movss	36(%rsp), %xmm0
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L32
	call	__stack_chk_fail@PLT
.L32:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3637:
	.size	_Z18RBF_CUDA_Tilling_2fPA1024_fS0_Pfiii, .-_Z18RBF_CUDA_Tilling_2fPA1024_fS0_Pfiii
	.globl	_Z46__device_stub__Z19RBFKernel_Tilling_4fPfS_S_iifPfS_S_ii
	.type	_Z46__device_stub__Z19RBFKernel_Tilling_4fPfS_S_iifPfS_S_ii, @function
_Z46__device_stub__Z19RBFKernel_Tilling_4fPfS_S_iifPfS_S_ii:
.LFB3672:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 32(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 24(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 40(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movss	%xmm0, 44(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z19RBFKernel_Tilling_4fPfS_S_ii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L34:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3672:
	.size	_Z46__device_stub__Z19RBFKernel_Tilling_4fPfS_S_iifPfS_S_ii, .-_Z46__device_stub__Z19RBFKernel_Tilling_4fPfS_S_iifPfS_S_ii
	.globl	_Z19RBFKernel_Tilling_4fPfS_S_ii
	.type	_Z19RBFKernel_Tilling_4fPfS_S_ii, @function
_Z19RBFKernel_Tilling_4fPfS_S_ii:
.LFB3673:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z19RBFKernel_Tilling_4fPfS_S_iifPfS_S_ii
	.cfi_endproc
.LFE3673:
	.size	_Z19RBFKernel_Tilling_4fPfS_S_ii, .-_Z19RBFKernel_Tilling_4fPfS_S_ii
	.globl	_Z18RBF_CUDA_Tilling_4fPA1024_fS0_Pfiii
	.type	_Z18RBF_CUDA_Tilling_4fPA1024_fS0_Pfiii, @function
_Z18RBF_CUDA_Tilling_4fPA1024_fS0_Pfiii:
.LFB3638:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%r9d, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%r8d, %ebx
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movss	%xmm0, 28(%rsp)
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	movl	$0x00000000, 36(%rsp)
	call	cudaEventCreate@PLT
	leaq	48(%rsp), %rdi
	call	cudaEventCreate@PLT
	movl	%ebx, %eax
	movl	$4, %ecx
	leaq	56(%rsp), %rdi
	cltd
	movl	$1, 88(%rsp)
	idivl	%ecx
	movl	$1, 100(%rsp)
	movl	%eax, 80(%rsp)
	movl	%ebp, %eax
	cltd
	idivl	%ecx
	movl	%ebx, %edx
	imull	%ebp, %ebx
	imull	%r12d, %edx
	movslq	%ebx, %rbx
	movslq	%edx, %rdx
	salq	$2, %rbx
	salq	$2, %rdx
	movq	%rdx, %rsi
	movq	%rdx, 16(%rsp)
	movl	%eax, 84(%rsp)
	movabsq	$17179869188, %rax
	movq	%rax, 92(%rsp)
	call	cudaMalloc@PLT
	movl	%ebp, %eax
	leaq	64(%rsp), %rdi
	imull	%r12d, %eax
	cltq
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	leaq	72(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdx
	movq	56(%rsp), %rdi
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	64(%rsp), %rdi
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	100(%rsp), %ecx
	movl	88(%rsp), %esi
	xorl	%r9d, %r9d
	movq	92(%rsp), %rdx
	movq	80(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	movss	28(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L40
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	%ebp, %r8d
	movl	%r12d, %ecx
	movq	56(%rsp), %rdi
	call	_Z46__device_stub__Z19RBFKernel_Tilling_4fPfS_S_iifPfS_S_ii
.L40:
	call	cudaDeviceSynchronize@PLT
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	48(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rsi
	leaq	36(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	72(%rsp), %rsi
	movq	%rbx, %rdx
	movq	%r13, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	48(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movss	36(%rsp), %xmm0
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L41
	call	__stack_chk_fail@PLT
.L41:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3638:
	.size	_Z18RBF_CUDA_Tilling_4fPA1024_fS0_Pfiii, .-_Z18RBF_CUDA_Tilling_4fPA1024_fS0_Pfiii
	.globl	_Z46__device_stub__Z19RBFKernel_Tilling_8fPfS_S_iifPfS_S_ii
	.type	_Z46__device_stub__Z19RBFKernel_Tilling_8fPfS_S_iifPfS_S_ii, @function
_Z46__device_stub__Z19RBFKernel_Tilling_8fPfS_S_iifPfS_S_ii:
.LFB3674:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 32(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 24(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 40(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movss	%xmm0, 44(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L43
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z19RBFKernel_Tilling_8fPfS_S_ii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L43:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L45
	call	__stack_chk_fail@PLT
.L45:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3674:
	.size	_Z46__device_stub__Z19RBFKernel_Tilling_8fPfS_S_iifPfS_S_ii, .-_Z46__device_stub__Z19RBFKernel_Tilling_8fPfS_S_iifPfS_S_ii
	.globl	_Z19RBFKernel_Tilling_8fPfS_S_ii
	.type	_Z19RBFKernel_Tilling_8fPfS_S_ii, @function
_Z19RBFKernel_Tilling_8fPfS_S_ii:
.LFB3675:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z19RBFKernel_Tilling_8fPfS_S_iifPfS_S_ii
	.cfi_endproc
.LFE3675:
	.size	_Z19RBFKernel_Tilling_8fPfS_S_ii, .-_Z19RBFKernel_Tilling_8fPfS_S_ii
	.globl	_Z18RBF_CUDA_Tilling_8fPA1024_fS0_Pfiii
	.type	_Z18RBF_CUDA_Tilling_8fPA1024_fS0_Pfiii, @function
_Z18RBF_CUDA_Tilling_8fPA1024_fS0_Pfiii:
.LFB3639:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%r9d, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%r8d, %ebx
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movss	%xmm0, 28(%rsp)
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	movl	$0x00000000, 36(%rsp)
	call	cudaEventCreate@PLT
	leaq	48(%rsp), %rdi
	call	cudaEventCreate@PLT
	movl	%ebx, %eax
	movl	$8, %ecx
	leaq	56(%rsp), %rdi
	cltd
	movl	$1, 88(%rsp)
	idivl	%ecx
	movl	$1, 100(%rsp)
	movl	%eax, 80(%rsp)
	movl	%ebp, %eax
	cltd
	idivl	%ecx
	movl	%ebx, %edx
	imull	%ebp, %ebx
	imull	%r12d, %edx
	movslq	%ebx, %rbx
	movslq	%edx, %rdx
	salq	$2, %rbx
	salq	$2, %rdx
	movq	%rdx, %rsi
	movq	%rdx, 16(%rsp)
	movl	%eax, 84(%rsp)
	movabsq	$34359738376, %rax
	movq	%rax, 92(%rsp)
	call	cudaMalloc@PLT
	movl	%ebp, %eax
	leaq	64(%rsp), %rdi
	imull	%r12d, %eax
	cltq
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	leaq	72(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdx
	movq	56(%rsp), %rdi
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	64(%rsp), %rdi
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	100(%rsp), %ecx
	movl	88(%rsp), %esi
	xorl	%r9d, %r9d
	movq	92(%rsp), %rdx
	movq	80(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	movss	28(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L49
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	%ebp, %r8d
	movl	%r12d, %ecx
	movq	56(%rsp), %rdi
	call	_Z46__device_stub__Z19RBFKernel_Tilling_8fPfS_S_iifPfS_S_ii
.L49:
	call	cudaDeviceSynchronize@PLT
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	48(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rsi
	leaq	36(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	72(%rsp), %rsi
	movq	%rbx, %rdx
	movq	%r13, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	48(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movss	36(%rsp), %xmm0
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L50
	call	__stack_chk_fail@PLT
.L50:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3639:
	.size	_Z18RBF_CUDA_Tilling_8fPA1024_fS0_Pfiii, .-_Z18RBF_CUDA_Tilling_8fPA1024_fS0_Pfiii
	.globl	_Z47__device_stub__Z20RBFKernel_Tilling_16fPfS_S_iifPfS_S_ii
	.type	_Z47__device_stub__Z20RBFKernel_Tilling_16fPfS_S_iifPfS_S_ii, @function
_Z47__device_stub__Z20RBFKernel_Tilling_16fPfS_S_iifPfS_S_ii:
.LFB3676:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 32(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 24(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 40(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movss	%xmm0, 44(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L52
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z20RBFKernel_Tilling_16fPfS_S_ii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L52:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L54
	call	__stack_chk_fail@PLT
.L54:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3676:
	.size	_Z47__device_stub__Z20RBFKernel_Tilling_16fPfS_S_iifPfS_S_ii, .-_Z47__device_stub__Z20RBFKernel_Tilling_16fPfS_S_iifPfS_S_ii
	.globl	_Z20RBFKernel_Tilling_16fPfS_S_ii
	.type	_Z20RBFKernel_Tilling_16fPfS_S_ii, @function
_Z20RBFKernel_Tilling_16fPfS_S_ii:
.LFB3677:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z20RBFKernel_Tilling_16fPfS_S_iifPfS_S_ii
	.cfi_endproc
.LFE3677:
	.size	_Z20RBFKernel_Tilling_16fPfS_S_ii, .-_Z20RBFKernel_Tilling_16fPfS_S_ii
	.globl	_Z19RBF_CUDA_Tilling_16fPA1024_fS0_Pfiii
	.type	_Z19RBF_CUDA_Tilling_16fPA1024_fS0_Pfiii, @function
_Z19RBF_CUDA_Tilling_16fPA1024_fS0_Pfiii:
.LFB3640:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%r9d, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%r8d, %ebx
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movss	%xmm0, 28(%rsp)
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	movl	$0x00000000, 36(%rsp)
	call	cudaEventCreate@PLT
	leaq	48(%rsp), %rdi
	call	cudaEventCreate@PLT
	movl	%ebx, %eax
	movl	$16, %ecx
	leaq	56(%rsp), %rdi
	cltd
	movl	$1, 88(%rsp)
	idivl	%ecx
	movl	$1, 100(%rsp)
	movl	%eax, 80(%rsp)
	movl	%ebp, %eax
	cltd
	idivl	%ecx
	movl	%ebx, %edx
	imull	%ebp, %ebx
	imull	%r12d, %edx
	movslq	%ebx, %rbx
	movslq	%edx, %rdx
	salq	$2, %rbx
	salq	$2, %rdx
	movq	%rdx, %rsi
	movq	%rdx, 16(%rsp)
	movl	%eax, 84(%rsp)
	movabsq	$68719476752, %rax
	movq	%rax, 92(%rsp)
	call	cudaMalloc@PLT
	movl	%ebp, %eax
	leaq	64(%rsp), %rdi
	imull	%r12d, %eax
	cltq
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	leaq	72(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdx
	movq	56(%rsp), %rdi
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	64(%rsp), %rdi
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	100(%rsp), %ecx
	movl	88(%rsp), %esi
	xorl	%r9d, %r9d
	movq	92(%rsp), %rdx
	movq	80(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	movss	28(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L58
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	%ebp, %r8d
	movl	%r12d, %ecx
	movq	56(%rsp), %rdi
	call	_Z47__device_stub__Z20RBFKernel_Tilling_16fPfS_S_iifPfS_S_ii
.L58:
	call	cudaDeviceSynchronize@PLT
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	48(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rsi
	leaq	36(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	72(%rsp), %rsi
	movq	%rbx, %rdx
	movq	%r13, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	48(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movss	36(%rsp), %xmm0
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L59
	call	__stack_chk_fail@PLT
.L59:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3640:
	.size	_Z19RBF_CUDA_Tilling_16fPA1024_fS0_Pfiii, .-_Z19RBF_CUDA_Tilling_16fPA1024_fS0_Pfiii
	.globl	_Z47__device_stub__Z20RBFKernel_Tilling_32fPfS_S_iifPfS_S_ii
	.type	_Z47__device_stub__Z20RBFKernel_Tilling_32fPfS_S_iifPfS_S_ii, @function
_Z47__device_stub__Z20RBFKernel_Tilling_32fPfS_S_iifPfS_S_ii:
.LFB3678:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 32(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 24(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 40(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movss	%xmm0, 44(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L61
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z20RBFKernel_Tilling_32fPfS_S_ii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L61:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L63
	call	__stack_chk_fail@PLT
.L63:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3678:
	.size	_Z47__device_stub__Z20RBFKernel_Tilling_32fPfS_S_iifPfS_S_ii, .-_Z47__device_stub__Z20RBFKernel_Tilling_32fPfS_S_iifPfS_S_ii
	.globl	_Z20RBFKernel_Tilling_32fPfS_S_ii
	.type	_Z20RBFKernel_Tilling_32fPfS_S_ii, @function
_Z20RBFKernel_Tilling_32fPfS_S_ii:
.LFB3679:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z20RBFKernel_Tilling_32fPfS_S_iifPfS_S_ii
	.cfi_endproc
.LFE3679:
	.size	_Z20RBFKernel_Tilling_32fPfS_S_ii, .-_Z20RBFKernel_Tilling_32fPfS_S_ii
	.globl	_Z19RBF_CUDA_Tilling_32fPA1024_fS0_Pfiii
	.type	_Z19RBF_CUDA_Tilling_32fPA1024_fS0_Pfiii, @function
_Z19RBF_CUDA_Tilling_32fPA1024_fS0_Pfiii:
.LFB3641:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%r9d, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%r8d, %ebx
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movss	%xmm0, 28(%rsp)
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	movl	$0x00000000, 36(%rsp)
	call	cudaEventCreate@PLT
	leaq	48(%rsp), %rdi
	call	cudaEventCreate@PLT
	movl	%ebx, %eax
	movl	$32, %ecx
	leaq	56(%rsp), %rdi
	cltd
	movl	$1, 88(%rsp)
	idivl	%ecx
	movl	$1, 100(%rsp)
	movl	%eax, 80(%rsp)
	movl	%ebp, %eax
	cltd
	idivl	%ecx
	movl	%ebx, %edx
	imull	%ebp, %ebx
	imull	%r12d, %edx
	movslq	%ebx, %rbx
	movslq	%edx, %rdx
	salq	$2, %rbx
	salq	$2, %rdx
	movq	%rdx, %rsi
	movq	%rdx, 16(%rsp)
	movl	%eax, 84(%rsp)
	movabsq	$137438953504, %rax
	movq	%rax, 92(%rsp)
	call	cudaMalloc@PLT
	movl	%ebp, %eax
	leaq	64(%rsp), %rdi
	imull	%r12d, %eax
	cltq
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	leaq	72(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdx
	movq	56(%rsp), %rdi
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	64(%rsp), %rdi
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	100(%rsp), %ecx
	movl	88(%rsp), %esi
	xorl	%r9d, %r9d
	movq	92(%rsp), %rdx
	movq	80(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	movss	28(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L67
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	%ebp, %r8d
	movl	%r12d, %ecx
	movq	56(%rsp), %rdi
	call	_Z47__device_stub__Z20RBFKernel_Tilling_32fPfS_S_iifPfS_S_ii
.L67:
	call	cudaDeviceSynchronize@PLT
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	48(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rsi
	leaq	36(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	72(%rsp), %rsi
	movq	%rbx, %rdx
	movq	%r13, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	48(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movss	36(%rsp), %xmm0
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L68
	call	__stack_chk_fail@PLT
.L68:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3641:
	.size	_Z19RBF_CUDA_Tilling_32fPA1024_fS0_Pfiii, .-_Z19RBF_CUDA_Tilling_32fPA1024_fS0_Pfiii
	.section	.rodata.str1.1
.LC6:
	.string	"CPU method running time: %.2f us\n"
.LC8:
	.string	"GPU simple method running time: %.2f us\n"
.LC9:
	.string	"GPU tilling method (width 2) running time: %.2f us\n"
.LC10:
	.string	"GPU tilling method (width 4) running time: %.2f us\n"
.LC11:
	.string	"GPU tilling method (width 8) running time: %.2f us\n"
.LC12:
	.string	"GPU tilling method (width 16) running time: %.2f us\n"
.LC13:
	.string	"GPU tilling method (width 32) running time: %.2f us\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3643:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	leaq	-290816(%rsp), %r11
	.cfi_def_cfa 11, 290872
.LPSRL0:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL0
	.cfi_def_cfa_register 7
	subq	$72, %rsp
	.cfi_def_cfa_offset 290944
	xorl	%edi, %edi
	movq	%fs:40, %rax
	movq	%rax, 290872(%rsp)
	xorl	%eax, %eax
	leaq	28728(%rsp), %r12
	leaq	159800(%rsp), %rbx
	call	time@PLT
	movq	%r12, %rbp
	movl	%eax, %edi
	call	srand@PLT
.L71:
	xorl	%r13d, %r13d
.L72:
	call	rand@PLT
	movl	$500, %ecx
	movsd	.LC3(%rip), %xmm0
	cltd
	idivl	%ecx
	cvtsi2sdl	%edx, %xmm1
	addsd	.LC3(%rip), %xmm1
	divsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%r12,%r13,4)
	incq	%r13
	cmpq	$1024, %r13
	jne	.L72
	addq	$4096, %r12
	cmpq	%rbx, %r12
	jne	.L71
	movq	%rbx, %r13
	leaq	290872(%rsp), %r15
	movl	$500, %r14d
.L73:
	xorl	%r12d, %r12d
.L74:
	call	rand@PLT
	movsd	.LC3(%rip), %xmm0
	cltd
	idivl	%r14d
	cvtsi2sdl	%edx, %xmm1
	addsd	.LC3(%rip), %xmm1
	divsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, 0(%r13,%r12,4)
	incq	%r12
	cmpq	$1024, %r12
	jne	.L74
	addq	$4096, %r13
	cmpq	%r15, %r13
	jne	.L73
	xorl	%esi, %esi
	leaq	24(%rsp), %rdi
	leaq	56(%rsp), %r12
	call	gettimeofday@PLT
	movl	$1024, %ecx
	movq	%r12, %rdx
	movq	%rbx, %rsi
	movl	$32, %r9d
	movss	.LC4(%rip), %xmm0
	movl	$32, %r8d
	movq	%rbp, %rdi
	call	_Z7RBF_CPUfPA1024_fS0_Pfiii
	xorl	%esi, %esi
	leaq	40(%rsp), %rdi
	call	gettimeofday@PLT
	movq	40(%rsp), %rax
	subq	24(%rsp), %rax
	movl	$32, %edx
	cvtsi2sdq	%rax, %xmm0
	movq	48(%rsp), %rax
	subq	32(%rsp), %rax
	movq	%r12, %rdi
	mulsd	.LC5(%rip), %xmm0
	cvtsi2sdq	%rax, %xmm1
	movl	$32, %esi
	leaq	4152(%rsp), %r12
	addsd	%xmm1, %xmm0
	movsd	%xmm0, 8(%rsp)
	call	_Z9prtResultPfii
	movsd	8(%rsp), %xmm0
	leaq	.LC6(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	$1024, %ecx
	movq	%r12, %rdx
	movq	%rbx, %rsi
	movl	$32, %r9d
	movss	.LC4(%rip), %xmm0
	movl	$32, %r8d
	movq	%rbp, %rdi
	call	_Z15RBF_CUDA_SimplefPA1024_fS0_Pfiii
	movl	$32, %edx
	movq	%r12, %rdi
	movl	$32, %esi
	movss	%xmm0, 8(%rsp)
	leaq	8248(%rsp), %r12
	call	_Z9prtResultPfii
	movss	8(%rsp), %xmm0
	leaq	.LC8(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	cvtss2sd	%xmm0, %xmm0
	mulsd	.LC7(%rip), %xmm0
	call	__printf_chk@PLT
	movl	$1024, %ecx
	movq	%r12, %rdx
	movq	%rbx, %rsi
	movl	$32, %r9d
	movss	.LC4(%rip), %xmm0
	movl	$32, %r8d
	movq	%rbp, %rdi
	call	_Z18RBF_CUDA_Tilling_2fPA1024_fS0_Pfiii
	movl	$32, %edx
	movq	%r12, %rdi
	movl	$32, %esi
	movss	%xmm0, 8(%rsp)
	leaq	12344(%rsp), %r12
	call	_Z9prtResultPfii
	movss	8(%rsp), %xmm0
	leaq	.LC9(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	cvtss2sd	%xmm0, %xmm0
	mulsd	.LC7(%rip), %xmm0
	call	__printf_chk@PLT
	movl	$1024, %ecx
	movq	%r12, %rdx
	movq	%rbx, %rsi
	movl	$32, %r9d
	movss	.LC4(%rip), %xmm0
	movl	$32, %r8d
	movq	%rbp, %rdi
	call	_Z18RBF_CUDA_Tilling_4fPA1024_fS0_Pfiii
	movl	$32, %edx
	movq	%r12, %rdi
	movl	$32, %esi
	movss	%xmm0, 8(%rsp)
	leaq	16440(%rsp), %r12
	call	_Z9prtResultPfii
	movss	8(%rsp), %xmm0
	leaq	.LC10(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	cvtss2sd	%xmm0, %xmm0
	mulsd	.LC7(%rip), %xmm0
	call	__printf_chk@PLT
	movl	$1024, %ecx
	movq	%r12, %rdx
	movq	%rbx, %rsi
	movl	$32, %r9d
	movss	.LC4(%rip), %xmm0
	movl	$32, %r8d
	movq	%rbp, %rdi
	call	_Z18RBF_CUDA_Tilling_8fPA1024_fS0_Pfiii
	movl	$32, %edx
	movq	%r12, %rdi
	movl	$32, %esi
	movss	%xmm0, 8(%rsp)
	leaq	20536(%rsp), %r12
	call	_Z9prtResultPfii
	movss	8(%rsp), %xmm0
	leaq	.LC11(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	cvtss2sd	%xmm0, %xmm0
	mulsd	.LC7(%rip), %xmm0
	call	__printf_chk@PLT
	movl	$1024, %ecx
	movq	%r12, %rdx
	movq	%rbx, %rsi
	movl	$32, %r9d
	movss	.LC4(%rip), %xmm0
	movl	$32, %r8d
	movq	%rbp, %rdi
	call	_Z19RBF_CUDA_Tilling_16fPA1024_fS0_Pfiii
	movl	$32, %edx
	movq	%r12, %rdi
	movl	$32, %esi
	movss	%xmm0, 8(%rsp)
	leaq	24632(%rsp), %r12
	call	_Z9prtResultPfii
	movss	8(%rsp), %xmm0
	leaq	.LC12(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	cvtss2sd	%xmm0, %xmm0
	mulsd	.LC7(%rip), %xmm0
	call	__printf_chk@PLT
	movl	$1024, %ecx
	movq	%r12, %rdx
	movq	%rbx, %rsi
	movl	$32, %r9d
	movss	.LC4(%rip), %xmm0
	movl	$32, %r8d
	movq	%rbp, %rdi
	call	_Z19RBF_CUDA_Tilling_32fPA1024_fS0_Pfiii
	movl	$32, %esi
	movq	%r12, %rdi
	movl	$32, %edx
	movss	%xmm0, 8(%rsp)
	call	_Z9prtResultPfii
	movss	8(%rsp), %xmm0
	leaq	.LC13(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	cvtss2sd	%xmm0, %xmm0
	mulsd	.LC7(%rip), %xmm0
	call	__printf_chk@PLT
	movq	290872(%rsp), %rax
	subq	%fs:40, %rax
	je	.L76
	call	__stack_chk_fail@PLT
.L76:
	addq	$290888, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3643:
	.size	main, .-main
	.section	.rodata.str1.1
.LC14:
	.string	"_Z20RBFKernel_Tilling_32fPfS_S_ii"
.LC15:
	.string	"_Z20RBFKernel_Tilling_16fPfS_S_ii"
.LC16:
	.string	"_Z19RBFKernel_Tilling_8fPfS_S_ii"
.LC17:
	.string	"_Z19RBFKernel_Tilling_4fPfS_S_ii"
.LC18:
	.string	"_Z19RBFKernel_Tilling_2fPfS_S_ii"
.LC19:
	.string	"_Z16RBFKernel_SimplefPfS_S_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3681:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC14(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z20RBFKernel_Tilling_32fPfS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC15(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z20RBFKernel_Tilling_16fPfS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC16(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z19RBFKernel_Tilling_8fPfS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC17(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z19RBFKernel_Tilling_4fPfS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC18(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z19RBFKernel_Tilling_2fPfS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC19(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z16RBFKernel_SimplefPfS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3681:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC1:
	.long	-2147483648
	.long	0
	.long	0
	.long	0
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC3:
	.long	0
	.long	1072693248
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC4:
	.long	1065353216
	.section	.rodata.cst8
	.align 8
.LC5:
	.long	0
	.long	1093567616
	.align 8
.LC7:
	.long	0
	.long	1083129856
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

# include <math.h>
# include <time.h>
# include <stdio.h>
# include <stdlib.h>
# include <iostream>
# include <sys/time.h>

# include "hip/hip_runtime.h"

using namespace std;

const int DIM = 1024, AS = 32, BS = 32;
const float sigma = 1.0;
const bool PRINT_RESULT = false;

/*
RBF Kernel Implementation on CPU.
Param @ sigma: the parameter sigma of RBF kernel;
      @ a, b, c: the input arrays and the output array;
      @ dim, as, bs: the size of the array, a should be of size as * dim, and b should be of size bs * dim.
*/
void RBF_CPU(float sigma, float a[][DIM], float b[][DIM], float c[], int dim, int as, int bs) {
    for (int i = 0; i < as; ++ i)
        for (int j = 0; j < bs; ++ j) {
            float Pvalue = 0.0;
            for (int k = 0; k < dim; ++ k)
                Pvalue += (a[i][k] - b[j][k]) * (a[i][k] - b[j][k]);
            c[i * bs + j] = exp(- Pvalue / (2 * sigma * sigma));
        }
}

/* 
Simple RBF Kernel Implementation.
Param @ sigma: the parameter sigma of RBF kernel;
      @ Md, Nd, Pd: the input values and the output array;
      @ dim: the dimension of features;
      @ Pdim: the width of the result array.
*/
__global__ void RBFKernel_Simple(float sigma, float *Md, float *Nd, float *Pd, int dim, int Pdim) {
    int tx = threadIdx.x;
    int ty = threadIdx.y;
    float Pvalue = 0.0;

    for (int k = 0; k < dim; ++ k) {
        float Mds = Md[tx * dim + k];
        float Nds = Nd[ty * dim + k];
        Pvalue += (Mds - Nds) * (Mds - Nds);
    }
    Pd[tx * Pdim + ty] = exp(- Pvalue / (2 * sigma * sigma));
}

/*
Wrapper function of Simple RBF Kernel Implementation.
Param @ sigma: the parameter sigma of RBF kernel;
      @ a, b, c: the input arrays and the output array;
      @ dim, as, bs: the size of the array, a should be of size as * dim, and b should be of size bs * dim.
Return @ the elapsed time of GPU calculation.
*/
float RBF_CUDA_Simple(float sigma, float a[][DIM], float b[][DIM], float c[], int dim, int as, int bs) {
    hipEvent_t start, stop;
    float elapsedTime = 0;
    hipEventCreate(&start);
    hipEventCreate(&stop);

    dim3 block(as, bs);
    float *M, *N, *P;
    hipMalloc((void **)&M, as * dim * sizeof(float));
    hipMalloc((void **)&N, bs * dim * sizeof(float));
    hipMalloc((void **)&P, as * bs * sizeof(float));

    hipMemcpy(M, a, as * dim * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(N, b, bs * dim * sizeof(float), hipMemcpyHostToDevice);

    hipEventRecord(start, 0);
    RBFKernel_Simple <<<1, block>>> (sigma, M, N, P, dim, bs);
    hipDeviceSynchronize();
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&elapsedTime, start, stop);

    hipMemcpy(c, P, as * bs * sizeof(float), hipMemcpyDeviceToHost);

    hipEventDestroy(start);
    hipEventDestroy(stop);

    hipFree(M);
    hipFree(N);
    hipFree(P);

    return elapsedTime;
}

/* 
RBF Kernel Implementation based on tilling (width 2).
Param @ sigma: the parameter sigma of RBF kernel;
      @ Md, Nd, Pd: the input values and the output array;
      @ dim: the dimension of features;
      @ Pdim: the width of the result array.
*/
const int TILE_WIDTH_2 = 2;
__global__ void RBFKernel_Tilling_2(float sigma, float *Md, float *Nd, float *Pd, int dim, int Pdim) {
    int bx = blockIdx.x;
    int by = blockIdx.y;
    int tx = threadIdx.x;
    int ty = threadIdx.y;
    float Pvalue = 0.0;
    int Mrow = bx * TILE_WIDTH_2 + tx;
    int Nrow = by * TILE_WIDTH_2 + ty;
    __shared__ float Mds[TILE_WIDTH_2][TILE_WIDTH_2];
    __shared__ float Nds[TILE_WIDTH_2][TILE_WIDTH_2];

    for (int i = 0; i < dim / TILE_WIDTH_2; ++ i) {
        Mds[tx][ty] = Md[Mrow * dim + i * TILE_WIDTH_2 + ty];
        Nds[ty][tx] = Nd[Nrow * dim + i * TILE_WIDTH_2 + tx];
        __syncthreads();
        for (int k = 0; k < TILE_WIDTH_2; ++ k)
            Pvalue += (Mds[tx][k] - Nds[ty][k]) * (Mds[tx][k] - Nds[ty][k]);
        __syncthreads();
    }
    Pd[Mrow * Pdim + Nrow] = exp(- Pvalue / (2 * sigma * sigma));
}

/*
Wrapper function of RBF Kernel Implementation based on tilling (width 2).
Param @ sigma: the parameter sigma of RBF kernel;
      @ a, b, c: the input arrays and the output array;
      @ dim, as, bs: the size of the array, a should be of size as * dim, and b should be of size bs * dim.
Return @ the elapsed time of GPU calculation.
*/
float RBF_CUDA_Tilling_2(float sigma, float a[][DIM], float b[][DIM], float c[], int dim, int as, int bs) {
    hipEvent_t start, stop;
    float elapsedTime = 0;
    hipEventCreate(&start);
    hipEventCreate(&stop);

    dim3 grid(as / TILE_WIDTH_2, bs / TILE_WIDTH_2);
    dim3 block(TILE_WIDTH_2, TILE_WIDTH_2);
    float *M, *N, *P;
    hipMalloc((void **)&M, as * dim * sizeof(float));
    hipMalloc((void **)&N, bs * dim * sizeof(float));
    hipMalloc((void **)&P, as * bs * sizeof(float));

    hipMemcpy(M, a, as * dim * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(N, b, bs * dim * sizeof(float), hipMemcpyHostToDevice);

    hipEventRecord(start, 0);
    RBFKernel_Tilling_2 <<<grid, block>>> (sigma, M, N, P, dim, bs);
    hipDeviceSynchronize();
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&elapsedTime, start, stop);

    hipMemcpy(c, P, as * bs * sizeof(float), hipMemcpyDeviceToHost);

    hipEventDestroy(start);
    hipEventDestroy(stop);

    hipFree(M);
    hipFree(N);
    hipFree(P);

    return elapsedTime;
}

/* 
RBF Kernel Implementation based on tilling (width 4).
Param @ sigma: the parameter sigma of RBF kernel;
      @ Md, Nd, Pd: the input values and the output array;
      @ dim: the dimension of features;
      @ Pdim: the width of the result array.
*/
const int TILE_WIDTH_4 = 4;
__global__ void RBFKernel_Tilling_4(float sigma, float *Md, float *Nd, float *Pd, int dim, int Pdim) {
    int bx = blockIdx.x;
    int by = blockIdx.y;
    int tx = threadIdx.x;
    int ty = threadIdx.y;
    float Pvalue = 0.0;
    int Mrow = bx * TILE_WIDTH_4 + tx;
    int Nrow = by * TILE_WIDTH_4 + ty;
    __shared__ float Mds[TILE_WIDTH_4][TILE_WIDTH_4];
    __shared__ float Nds[TILE_WIDTH_4][TILE_WIDTH_4];

    for (int i = 0; i < dim / TILE_WIDTH_4; ++ i) {
        Mds[tx][ty] = Md[Mrow * dim + i * TILE_WIDTH_4 + ty];
        Nds[ty][tx] = Nd[Nrow * dim + i * TILE_WIDTH_4 + tx];
        __syncthreads();
        for (int k = 0; k < TILE_WIDTH_4; ++ k)
            Pvalue += (Mds[tx][k] - Nds[ty][k]) * (Mds[tx][k] - Nds[ty][k]);
        __syncthreads();
    }
    Pd[Mrow * Pdim + Nrow] = exp(- Pvalue / (2 * sigma * sigma));
}

/*
Wrapper function of RBF Kernel Implementation based on tilling (width 4).
Param @ sigma: the parameter sigma of RBF kernel;
      @ a, b, c: the input arrays and the output array;
      @ dim, as, bs: the size of the array, a should be of size as * dim, and b should be of size bs * dim.
Return @ the elapsed time of GPU calculation.
*/
float RBF_CUDA_Tilling_4(float sigma, float a[][DIM], float b[][DIM], float c[], int dim, int as, int bs) {
    hipEvent_t start, stop;
    float elapsedTime = 0;
    hipEventCreate(&start);
    hipEventCreate(&stop);

    dim3 grid(as / TILE_WIDTH_4, bs / TILE_WIDTH_4);
    dim3 block(TILE_WIDTH_4, TILE_WIDTH_4);
    float *M, *N, *P;
    hipMalloc((void **)&M, as * dim * sizeof(float));
    hipMalloc((void **)&N, bs * dim * sizeof(float));
    hipMalloc((void **)&P, as * bs * sizeof(float));

    hipMemcpy(M, a, as * dim * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(N, b, bs * dim * sizeof(float), hipMemcpyHostToDevice);

    hipEventRecord(start, 0);
    RBFKernel_Tilling_4 <<<grid, block>>> (sigma, M, N, P, dim, bs);
    hipDeviceSynchronize();
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&elapsedTime, start, stop);

    hipMemcpy(c, P, as * bs * sizeof(float), hipMemcpyDeviceToHost);

    hipEventDestroy(start);
    hipEventDestroy(stop);

    hipFree(M);
    hipFree(N);
    hipFree(P);

    return elapsedTime;
}

/* 
RBF Kernel Implementation based on tilling (width 8).
Param @ sigma: the parameter sigma of RBF kernel;
      @ Md, Nd, Pd: the input values and the output array;
      @ dim: the dimension of features;
      @ Pdim: the width of the result array.
*/
const int TILE_WIDTH_8 = 8;
__global__ void RBFKernel_Tilling_8(float sigma, float *Md, float *Nd, float *Pd, int dim, int Pdim) {
    int bx = blockIdx.x;
    int by = blockIdx.y;
    int tx = threadIdx.x;
    int ty = threadIdx.y;
    float Pvalue = 0.0;
    int Mrow = bx * TILE_WIDTH_8 + tx;
    int Nrow = by * TILE_WIDTH_8 + ty;
    __shared__ float Mds[TILE_WIDTH_8][TILE_WIDTH_8];
    __shared__ float Nds[TILE_WIDTH_8][TILE_WIDTH_8];

    for (int i = 0; i < dim / TILE_WIDTH_8; ++ i) {
        Mds[tx][ty] = Md[Mrow * dim + i * TILE_WIDTH_8 + ty];
        Nds[ty][tx] = Nd[Nrow * dim + i * TILE_WIDTH_8 + tx];
        __syncthreads();
        for (int k = 0; k < TILE_WIDTH_8; ++ k)
            Pvalue += (Mds[tx][k] - Nds[ty][k]) * (Mds[tx][k] - Nds[ty][k]);
        __syncthreads();
    }
    Pd[Mrow * Pdim + Nrow] = exp(- Pvalue / (2 * sigma * sigma));
}

/*
Wrapper function of RBF Kernel Implementation based on tilling (width 8).
Param @ sigma: the parameter sigma of RBF kernel;
      @ a, b, c: the input arrays and the output array;
      @ dim, as, bs: the size of the array, a should be of size as * dim, and b should be of size bs * dim.
Return @ the elapsed time of GPU calculation.
*/
float RBF_CUDA_Tilling_8(float sigma, float a[][DIM], float b[][DIM], float c[], int dim, int as, int bs) {
    hipEvent_t start, stop;
    float elapsedTime = 0;
    hipEventCreate(&start);
    hipEventCreate(&stop);

    dim3 grid(as / TILE_WIDTH_8, bs / TILE_WIDTH_8);
    dim3 block(TILE_WIDTH_8, TILE_WIDTH_8);
    float *M, *N, *P;
    hipMalloc((void **)&M, as * dim * sizeof(float));
    hipMalloc((void **)&N, bs * dim * sizeof(float));
    hipMalloc((void **)&P, as * bs * sizeof(float));

    hipMemcpy(M, a, as * dim * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(N, b, bs * dim * sizeof(float), hipMemcpyHostToDevice);

    hipEventRecord(start, 0);
    RBFKernel_Tilling_8 <<<grid, block>>> (sigma, M, N, P, dim, bs);
    hipDeviceSynchronize();
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&elapsedTime, start, stop);

    hipMemcpy(c, P, as * bs * sizeof(float), hipMemcpyDeviceToHost);

    hipEventDestroy(start);
    hipEventDestroy(stop);

    hipFree(M);
    hipFree(N);
    hipFree(P);

    return elapsedTime;
}

/* 
RBF Kernel Implementation based on tilling (width 16).
Param @ sigma: the parameter sigma of RBF kernel;
      @ Md, Nd, Pd: the input values and the output array;
      @ dim: the dimension of features;
      @ Pdim: the width of the result array.
*/
const int TILE_WIDTH_16 = 16;
__global__ void RBFKernel_Tilling_16(float sigma, float *Md, float *Nd, float *Pd, int dim, int Pdim) {
    int bx = blockIdx.x;
    int by = blockIdx.y;
    int tx = threadIdx.x;
    int ty = threadIdx.y;
    float Pvalue = 0.0;
    int Mrow = bx * TILE_WIDTH_16 + tx;
    int Nrow = by * TILE_WIDTH_16 + ty;
    __shared__ float Mds[TILE_WIDTH_16][TILE_WIDTH_16];
    __shared__ float Nds[TILE_WIDTH_16][TILE_WIDTH_16];

    for (int i = 0; i < dim / TILE_WIDTH_16; ++ i) {
        Mds[tx][ty] = Md[Mrow * dim + i * TILE_WIDTH_16 + ty];
        Nds[ty][tx] = Nd[Nrow * dim + i * TILE_WIDTH_16 + tx];
        __syncthreads();
        for (int k = 0; k < TILE_WIDTH_16; ++ k)
            Pvalue += (Mds[tx][k] - Nds[ty][k]) * (Mds[tx][k] - Nds[ty][k]);
        __syncthreads();
    }
    Pd[Mrow * Pdim + Nrow] = exp(- Pvalue / (2 * sigma * sigma));
}

/*
Wrapper function of RBF Kernel Implementation based on tilling (width 16).
Param @ sigma: the parameter sigma of RBF kernel;
      @ a, b, c: the input arrays and the output array;
      @ dim, as, bs: the size of the array, a should be of size as * dim, and b should be of size bs * dim.
Return @ the elapsed time of GPU calculation.
*/
float RBF_CUDA_Tilling_16(float sigma, float a[][DIM], float b[][DIM], float c[], int dim, int as, int bs) {
    hipEvent_t start, stop;
    float elapsedTime = 0;
    hipEventCreate(&start);
    hipEventCreate(&stop);

    dim3 grid(as / TILE_WIDTH_16, bs / TILE_WIDTH_16);
    dim3 block(TILE_WIDTH_16, TILE_WIDTH_16);
    float *M, *N, *P;
    hipMalloc((void **)&M, as * dim * sizeof(float));
    hipMalloc((void **)&N, bs * dim * sizeof(float));
    hipMalloc((void **)&P, as * bs * sizeof(float));

    hipMemcpy(M, a, as * dim * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(N, b, bs * dim * sizeof(float), hipMemcpyHostToDevice);

    hipEventRecord(start, 0);
    RBFKernel_Tilling_16 <<<grid, block>>> (sigma, M, N, P, dim, bs);
    hipDeviceSynchronize();
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&elapsedTime, start, stop);

    hipMemcpy(c, P, as * bs * sizeof(float), hipMemcpyDeviceToHost);

    hipEventDestroy(start);
    hipEventDestroy(stop);

    hipFree(M);
    hipFree(N);
    hipFree(P);

    return elapsedTime;
}

/* 
RBF Kernel Implementation based on tilling (width 32).
Param @ sigma: the parameter sigma of RBF kernel;
      @ Md, Nd, Pd: the input values and the output array;
      @ dim: the dimension of features;
      @ Pdim: the width of the result array.
*/
const int TILE_WIDTH_32 = 32;
__global__ void RBFKernel_Tilling_32(float sigma, float *Md, float *Nd, float *Pd, int dim, int Pdim) {
    int bx = blockIdx.x;
    int by = blockIdx.y;
    int tx = threadIdx.x;
    int ty = threadIdx.y;
    float Pvalue = 0.0;
    int Mrow = bx * TILE_WIDTH_32 + tx;
    int Nrow = by * TILE_WIDTH_32 + ty;
    __shared__ float Mds[TILE_WIDTH_32][TILE_WIDTH_32];
    __shared__ float Nds[TILE_WIDTH_32][TILE_WIDTH_32];

    for (int i = 0; i < dim / TILE_WIDTH_32; ++ i) {
        Mds[tx][ty] = Md[Mrow * dim + i * TILE_WIDTH_32 + ty];
        Nds[ty][tx] = Nd[Nrow * dim + i * TILE_WIDTH_32 + tx];
        __syncthreads();
        for (int k = 0; k < TILE_WIDTH_32; ++ k)
            Pvalue += (Mds[tx][k] - Nds[ty][k]) * (Mds[tx][k] - Nds[ty][k]);
        __syncthreads();
    }
    Pd[Mrow * Pdim + Nrow] = exp(- Pvalue / (2 * sigma * sigma));
}

/*
Wrapper function of RBF Kernel Implementation based on tilling (width 32).
Param @ sigma: the parameter sigma of RBF kernel;
      @ a, b, c: the input arrays and the output array;
      @ dim, as, bs: the size of the array, a should be of size as * dim, and b should be of size bs * dim.
Return @ the elapsed time of GPU calculation.
*/
float RBF_CUDA_Tilling_32(float sigma, float a[][DIM], float b[][DIM], float c[], int dim, int as, int bs) {
    hipEvent_t start, stop;
    float elapsedTime = 0;
    hipEventCreate(&start);
    hipEventCreate(&stop);

    dim3 grid(as / TILE_WIDTH_32, bs / TILE_WIDTH_32);
    dim3 block(TILE_WIDTH_32, TILE_WIDTH_32);
    float *M, *N, *P;
    hipMalloc((void **)&M, as * dim * sizeof(float));
    hipMalloc((void **)&N, bs * dim * sizeof(float));
    hipMalloc((void **)&P, as * bs * sizeof(float));

    hipMemcpy(M, a, as * dim * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(N, b, bs * dim * sizeof(float), hipMemcpyHostToDevice);

    hipEventRecord(start, 0);
    RBFKernel_Tilling_32 <<<grid, block>>> (sigma, M, N, P, dim, bs);
    hipDeviceSynchronize();
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&elapsedTime, start, stop);

    hipMemcpy(c, P, as * bs * sizeof(float), hipMemcpyDeviceToHost);

    hipEventDestroy(start);
    hipEventDestroy(stop);

    hipFree(M);
    hipFree(N);
    hipFree(P);

    return elapsedTime;
}

// Print the result array.
void prtResult(float res[], int n, int m) {
    if (PRINT_RESULT) {
        printf("Result: \n");
        for (int i = 0; i < n; ++ i, printf("\n"))
            for (int j = 0; j < m; ++ j) 
                printf("%.2lf ", res[i * m + j]);
    } else {
        float sum = 0.0;
        for (int i = 0; i < n * m; ++ i)
            sum += res[i];
        printf("The sum of the matrix: %.2lf\n", sum);
    }
}

int main() {
    // Randomly generate array for testing.
    srand(time(0));
    float a[AS][DIM], b[BS][DIM];

    for (int i = 0; i < AS; ++ i)
        for (int j = 0; j < DIM; ++ j)
            a[i][j] = 1.0 / (rand() % 500 + 1.0);
    for (int i = 0; i < BS; ++ i)
        for (int j = 0; j < DIM; ++ j)
            b[i][j] = 1.0 / (rand() % 500 + 1.0);
    
    // ============================================================ //
    double duration; // execution time
    timeval start, end; // since clock() is not accurate, we use gettimeofday(...) in 'sys/time.h' to calculate running time.

    // => Baseline: CPU
    float c_CPU[AS * BS];
    gettimeofday(&start, 0);
    RBF_CPU(sigma, a, b, c_CPU, DIM, AS, BS);
    gettimeofday(&end, 0);
    duration = (end.tv_sec - start.tv_sec) * 1e6 + (end.tv_usec - start.tv_usec);
    prtResult(c_CPU, AS, BS);
    printf("CPU method running time: %.2f us\n", duration);
    
    // ==> CUDA, Simple
    float c_GPU_simple[AS * BS];
    float elapsedTime_simple = RBF_CUDA_Simple(sigma, a, b, c_GPU_simple, DIM, AS, BS);
    prtResult(c_GPU_simple, AS, BS);
    printf("GPU simple method running time: %.2f us\n", elapsedTime_simple * 1e3);

    // ===> CUDA, Tilling (tile width = 2)
    float c_GPU_tilling_2[AS * BS];
    float elapsedTime_tilling_2 = RBF_CUDA_Tilling_2(sigma, a, b, c_GPU_tilling_2, DIM, AS, BS);
    prtResult(c_GPU_tilling_2, AS, BS);
    printf("GPU tilling method (width 2) running time: %.2f us\n", elapsedTime_tilling_2 * 1e3);

    // ===> CUDA, Tilling (tile width = 4)
    float c_GPU_tilling_4[AS * BS];
    float elapsedTime_tilling_4 = RBF_CUDA_Tilling_4(sigma, a, b, c_GPU_tilling_4, DIM, AS, BS);
    prtResult(c_GPU_tilling_4, AS, BS);
    printf("GPU tilling method (width 4) running time: %.2f us\n", elapsedTime_tilling_4 * 1e3);

    // ===> CUDA, Tilling (tile width = 8)
    float c_GPU_tilling_8[AS * BS];
    float elapsedTime_tilling_8 = RBF_CUDA_Tilling_8(sigma, a, b, c_GPU_tilling_8, DIM, AS, BS);
    prtResult(c_GPU_tilling_8, AS, BS);
    printf("GPU tilling method (width 8) running time: %.2f us\n", elapsedTime_tilling_8 * 1e3);

    // ===> CUDA, Tilling (tile width = 16)
    float c_GPU_tilling_16[AS * BS];
    float elapsedTime_tilling_16 = RBF_CUDA_Tilling_16(sigma, a, b, c_GPU_tilling_16, DIM, AS, BS);
    prtResult(c_GPU_tilling_16, AS, BS);
    printf("GPU tilling method (width 16) running time: %.2f us\n", elapsedTime_tilling_16 * 1e3);

    // ===> CUDA, Tilling (tile width = 32)
    float c_GPU_tilling_32[AS * BS];
    float elapsedTime_tilling_32 = RBF_CUDA_Tilling_32(sigma, a, b, c_GPU_tilling_32, DIM, AS, BS);
    prtResult(c_GPU_tilling_32, AS, BS);
    printf("GPU tilling method (width 32) running time: %.2f us\n", elapsedTime_tilling_32 * 1e3);

    return 0;
}

	.text
	.file	"rbf.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z7RBF_CPUfPA1024_fS0_Pfiii
.LCPI0_0:
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.text
	.globl	_Z7RBF_CPUfPA1024_fS0_Pfiii
	.type	_Z7RBF_CPUfPA1024_fS0_Pfiii,@function
_Z7RBF_CPUfPA1024_fS0_Pfiii:            # @_Z7RBF_CPUfPA1024_fS0_Pfiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, 8(%rsp)                   # 4-byte Spill
	movl	%ecx, 12(%rsp)                  # 4-byte Spill
	movq	%rdx, 40(%rsp)                  # 8-byte Spill
	movq	%rsi, 32(%rsp)                  # 8-byte Spill
	testl	%r8d, %r8d
	jle	.LBB0_7
# %bb.1:                                # %.preheader32.lr.ph
	movq	%rdi, %r12
	movaps	%xmm0, %xmm1
	addss	%xmm0, %xmm1
	mulss	%xmm0, %xmm1
	movss	%xmm1, 28(%rsp)                 # 4-byte Spill
	movl	%r8d, %eax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movl	8(%rsp), %r14d                  # 4-byte Reload
	movl	12(%rsp), %r15d                 # 4-byte Reload
	xorl	%eax, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
.LBB0_2:                                # %.preheader32
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_4 Depth 2
                                        #       Child Loop BB0_9 Depth 3
	cmpl	$0, 8(%rsp)                     # 4-byte Folded Reload
	jle	.LBB0_6
# %bb.3:                                # %.preheader.lr.ph
                                        #   in Loop: Header=BB0_2 Depth=1
	movq	16(%rsp), %rax                  # 8-byte Reload
                                        # kill: def $eax killed $eax killed $rax def $rax
	imull	8(%rsp), %eax                   # 4-byte Folded Reload
	movq	40(%rsp), %rcx                  # 8-byte Reload
	leaq	(%rcx,%rax,4), %rbx
	movq	32(%rsp), %r13                  # 8-byte Reload
	xorl	%ebp, %ebp
.LBB0_4:                                # %.preheader
                                        #   Parent Loop BB0_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB0_9 Depth 3
	cmpl	$0, 12(%rsp)                    # 4-byte Folded Reload
	jle	.LBB0_5
# %bb.8:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB0_4 Depth=2
	xorps	%xmm0, %xmm0
	xorl	%eax, %eax
.LBB0_9:                                # %.lr.ph
                                        #   Parent Loop BB0_2 Depth=1
                                        #     Parent Loop BB0_4 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%r12,%rax,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	subss	(%r13,%rax,4), %xmm1
	mulss	%xmm1, %xmm1
	addss	%xmm1, %xmm0
	incq	%rax
	cmpq	%rax, %r15
	jne	.LBB0_9
	jmp	.LBB0_10
.LBB0_5:                                #   in Loop: Header=BB0_4 Depth=2
	xorps	%xmm0, %xmm0
.LBB0_10:                               # %._crit_edge
                                        #   in Loop: Header=BB0_4 Depth=2
	xorps	.LCPI0_0(%rip), %xmm0
	divss	28(%rsp), %xmm0                 # 4-byte Folded Reload
	callq	expf
	movss	%xmm0, (%rbx,%rbp,4)
	incq	%rbp
	addq	$4096, %r13                     # imm = 0x1000
	cmpq	%r14, %rbp
	jne	.LBB0_4
.LBB0_6:                                # %._crit_edge36
                                        #   in Loop: Header=BB0_2 Depth=1
	movq	16(%rsp), %rcx                  # 8-byte Reload
	incq	%rcx
	addq	$4096, %r12                     # imm = 0x1000
	movq	%rcx, %rax
	movq	%rcx, 16(%rsp)                  # 8-byte Spill
	cmpq	48(%rsp), %rcx                  # 8-byte Folded Reload
	jne	.LBB0_2
.LBB0_7:                                # %._crit_edge38
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z7RBF_CPUfPA1024_fS0_Pfiii, .Lfunc_end0-_Z7RBF_CPUfPA1024_fS0_Pfiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z31__device_stub__RBFKernel_SimplefPfS_S_ii # -- Begin function _Z31__device_stub__RBFKernel_SimplefPfS_S_ii
	.type	_Z31__device_stub__RBFKernel_SimplefPfS_S_ii,@function
_Z31__device_stub__RBFKernel_SimplefPfS_S_ii: # @_Z31__device_stub__RBFKernel_SimplefPfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movss	%xmm0, (%rax)
	leaq	56(%rsp), %r9
	movq	%rdi, (%r9)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%r9, 8(%rbx)
	movq	%rdi, 16(%rbx)
	movq	%rsi, 24(%rbx)
	movq	%rdx, 32(%rbx)
	movq	%rcx, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16RBFKernel_SimplefPfS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z31__device_stub__RBFKernel_SimplefPfS_S_ii, .Lfunc_end1-_Z31__device_stub__RBFKernel_SimplefPfS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z15RBF_CUDA_SimplefPA1024_fS0_Pfiii # -- Begin function _Z15RBF_CUDA_SimplefPA1024_fS0_Pfiii
	.type	_Z15RBF_CUDA_SimplefPA1024_fS0_Pfiii,@function
_Z15RBF_CUDA_SimplefPA1024_fS0_Pfiii:   # @_Z15RBF_CUDA_SimplefPA1024_fS0_Pfiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %ebx
	movl	%r8d, %r15d
	movl	%ecx, %ebp
	movq	%rdx, 80(%rsp)                  # 8-byte Spill
	movq	%rsi, 72(%rsp)                  # 8-byte Spill
	movq	%rdi, 64(%rsp)                  # 8-byte Spill
	movss	%xmm0, 44(%rsp)                 # 4-byte Spill
	movl	$0, 52(%rsp)
	leaq	32(%rsp), %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movl	%r15d, %eax
	movq	%rbx, %r14
	shlq	$32, %r14
	orq	%rax, %r14
	movl	%r15d, %eax
	imull	%ebp, %eax
	movslq	%eax, %r12
	shlq	$2, %r12
	leaq	24(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	%ebx, %eax
	movl	%ebp, 48(%rsp)                  # 4-byte Spill
	imull	%ebp, %eax
	movslq	%eax, %r13
	shlq	$2, %r13
	leaq	56(%rsp), %rbp
	movq	%rbp, %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	imull	%ebx, %r15d
	movslq	%r15d, %r15
	shlq	$2, %r15
	leaq	16(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movq	64(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movq	72(%rsp), %rsi                  # 8-byte Reload
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	32(%rsp), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	movq	24(%rsp), %rdi
	movq	56(%rsp), %rsi
	movq	16(%rsp), %rdx
	movss	44(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movl	48(%rsp), %ecx                  # 4-byte Reload
	movl	%ebx, %r8d
	callq	_Z31__device_stub__RBFKernel_SimplefPfS_S_ii
.LBB2_2:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	52(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movq	16(%rsp), %rsi
	movq	80(%rsp), %rdi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdi
	callq	hipEventDestroy
	movq	8(%rsp), %rdi
	callq	hipEventDestroy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movss	(%rbx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z15RBF_CUDA_SimplefPA1024_fS0_Pfiii, .Lfunc_end2-_Z15RBF_CUDA_SimplefPA1024_fS0_Pfiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__RBFKernel_Tilling_2fPfS_S_ii # -- Begin function _Z34__device_stub__RBFKernel_Tilling_2fPfS_S_ii
	.type	_Z34__device_stub__RBFKernel_Tilling_2fPfS_S_ii,@function
_Z34__device_stub__RBFKernel_Tilling_2fPfS_S_ii: # @_Z34__device_stub__RBFKernel_Tilling_2fPfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movss	%xmm0, (%rax)
	leaq	56(%rsp), %r9
	movq	%rdi, (%r9)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%r9, 8(%rbx)
	movq	%rdi, 16(%rbx)
	movq	%rsi, 24(%rbx)
	movq	%rdx, 32(%rbx)
	movq	%rcx, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19RBFKernel_Tilling_2fPfS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z34__device_stub__RBFKernel_Tilling_2fPfS_S_ii, .Lfunc_end3-_Z34__device_stub__RBFKernel_Tilling_2fPfS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z18RBF_CUDA_Tilling_2fPA1024_fS0_Pfiii # -- Begin function _Z18RBF_CUDA_Tilling_2fPA1024_fS0_Pfiii
	.type	_Z18RBF_CUDA_Tilling_2fPA1024_fS0_Pfiii,@function
_Z18RBF_CUDA_Tilling_2fPA1024_fS0_Pfiii: # @_Z18RBF_CUDA_Tilling_2fPA1024_fS0_Pfiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %ebp
	movl	%r8d, %r15d
	movl	%ecx, %r14d
	movq	%rdx, 80(%rsp)                  # 8-byte Spill
	movq	%rsi, 72(%rsp)                  # 8-byte Spill
	movq	%rdi, 64(%rsp)                  # 8-byte Spill
	movss	%xmm0, 44(%rsp)                 # 4-byte Spill
	movl	$0, 52(%rsp)
	leaq	32(%rsp), %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movl	%r15d, %eax
	shrl	$31, %eax
	addl	%r15d, %eax
	sarl	%eax
	movl	%ebp, %ebx
	shrl	$31, %ebx
	addl	%ebp, %ebx
	sarl	%ebx
	shlq	$32, %rbx
	orq	%rax, %rbx
	movl	%r15d, %eax
	imull	%r14d, %eax
	movslq	%eax, %r12
	shlq	$2, %r12
	leaq	24(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	%ebp, %eax
	movl	%r14d, 48(%rsp)                 # 4-byte Spill
	imull	%r14d, %eax
	movslq	%eax, %r13
	shlq	$2, %r13
	leaq	56(%rsp), %r14
	movq	%r14, %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	imull	%ebp, %r15d
	movslq	%r15d, %r15
	shlq	$2, %r15
	leaq	16(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movq	64(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r14), %rdi
	movq	72(%rsp), %rsi                  # 8-byte Reload
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	32(%rsp), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$8589934594, %rdx               # imm = 0x200000002
	movq	%rbx, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_2
# %bb.1:
	movq	24(%rsp), %rdi
	movq	56(%rsp), %rsi
	movq	16(%rsp), %rdx
	movss	44(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movl	48(%rsp), %ecx                  # 4-byte Reload
	movl	%ebp, %r8d
	callq	_Z34__device_stub__RBFKernel_Tilling_2fPfS_S_ii
.LBB4_2:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	52(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movq	16(%rsp), %rsi
	movq	80(%rsp), %rdi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdi
	callq	hipEventDestroy
	movq	8(%rsp), %rdi
	callq	hipEventDestroy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movss	(%rbx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z18RBF_CUDA_Tilling_2fPA1024_fS0_Pfiii, .Lfunc_end4-_Z18RBF_CUDA_Tilling_2fPA1024_fS0_Pfiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__RBFKernel_Tilling_4fPfS_S_ii # -- Begin function _Z34__device_stub__RBFKernel_Tilling_4fPfS_S_ii
	.type	_Z34__device_stub__RBFKernel_Tilling_4fPfS_S_ii,@function
_Z34__device_stub__RBFKernel_Tilling_4fPfS_S_ii: # @_Z34__device_stub__RBFKernel_Tilling_4fPfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movss	%xmm0, (%rax)
	leaq	56(%rsp), %r9
	movq	%rdi, (%r9)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%r9, 8(%rbx)
	movq	%rdi, 16(%rbx)
	movq	%rsi, 24(%rbx)
	movq	%rdx, 32(%rbx)
	movq	%rcx, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19RBFKernel_Tilling_4fPfS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z34__device_stub__RBFKernel_Tilling_4fPfS_S_ii, .Lfunc_end5-_Z34__device_stub__RBFKernel_Tilling_4fPfS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z18RBF_CUDA_Tilling_4fPA1024_fS0_Pfiii # -- Begin function _Z18RBF_CUDA_Tilling_4fPA1024_fS0_Pfiii
	.type	_Z18RBF_CUDA_Tilling_4fPA1024_fS0_Pfiii,@function
_Z18RBF_CUDA_Tilling_4fPA1024_fS0_Pfiii: # @_Z18RBF_CUDA_Tilling_4fPA1024_fS0_Pfiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %r14d
	movl	%r8d, %r15d
	movl	%ecx, %ebp
	movq	%rdx, 80(%rsp)                  # 8-byte Spill
	movq	%rsi, 72(%rsp)                  # 8-byte Spill
	movq	%rdi, 64(%rsp)                  # 8-byte Spill
	movss	%xmm0, 44(%rsp)                 # 4-byte Spill
	movl	$0, 52(%rsp)
	leaq	32(%rsp), %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	leal	3(%r15), %eax
	testl	%r15d, %r15d
	cmovnsl	%r15d, %eax
	sarl	$2, %eax
	leal	3(%r14), %ebx
	testl	%r14d, %r14d
	cmovnsl	%r14d, %ebx
	sarl	$2, %ebx
	shlq	$32, %rbx
	orq	%rax, %rbx
	movl	%r15d, %eax
	imull	%ebp, %eax
	movslq	%eax, %r12
	shlq	$2, %r12
	leaq	24(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	%r14d, %eax
	movl	%ebp, 48(%rsp)                  # 4-byte Spill
	imull	%ebp, %eax
	movslq	%eax, %r13
	shlq	$2, %r13
	leaq	56(%rsp), %rbp
	movq	%rbp, %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	imull	%r14d, %r15d
	movslq	%r15d, %r15
	shlq	$2, %r15
	leaq	16(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movq	64(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movq	72(%rsp), %rsi                  # 8-byte Reload
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	32(%rsp), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$17179869188, %rdx              # imm = 0x400000004
	movq	%rbx, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_2
# %bb.1:
	movq	24(%rsp), %rdi
	movq	56(%rsp), %rsi
	movq	16(%rsp), %rdx
	movss	44(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movl	48(%rsp), %ecx                  # 4-byte Reload
	movl	%r14d, %r8d
	callq	_Z34__device_stub__RBFKernel_Tilling_4fPfS_S_ii
.LBB6_2:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	52(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movq	16(%rsp), %rsi
	movq	80(%rsp), %rdi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdi
	callq	hipEventDestroy
	movq	8(%rsp), %rdi
	callq	hipEventDestroy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movss	(%rbx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z18RBF_CUDA_Tilling_4fPA1024_fS0_Pfiii, .Lfunc_end6-_Z18RBF_CUDA_Tilling_4fPA1024_fS0_Pfiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__RBFKernel_Tilling_8fPfS_S_ii # -- Begin function _Z34__device_stub__RBFKernel_Tilling_8fPfS_S_ii
	.type	_Z34__device_stub__RBFKernel_Tilling_8fPfS_S_ii,@function
_Z34__device_stub__RBFKernel_Tilling_8fPfS_S_ii: # @_Z34__device_stub__RBFKernel_Tilling_8fPfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movss	%xmm0, (%rax)
	leaq	56(%rsp), %r9
	movq	%rdi, (%r9)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%r9, 8(%rbx)
	movq	%rdi, 16(%rbx)
	movq	%rsi, 24(%rbx)
	movq	%rdx, 32(%rbx)
	movq	%rcx, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19RBFKernel_Tilling_8fPfS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z34__device_stub__RBFKernel_Tilling_8fPfS_S_ii, .Lfunc_end7-_Z34__device_stub__RBFKernel_Tilling_8fPfS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z18RBF_CUDA_Tilling_8fPA1024_fS0_Pfiii # -- Begin function _Z18RBF_CUDA_Tilling_8fPA1024_fS0_Pfiii
	.type	_Z18RBF_CUDA_Tilling_8fPA1024_fS0_Pfiii,@function
_Z18RBF_CUDA_Tilling_8fPA1024_fS0_Pfiii: # @_Z18RBF_CUDA_Tilling_8fPA1024_fS0_Pfiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %r14d
	movl	%r8d, %r15d
	movl	%ecx, %ebp
	movq	%rdx, 80(%rsp)                  # 8-byte Spill
	movq	%rsi, 72(%rsp)                  # 8-byte Spill
	movq	%rdi, 64(%rsp)                  # 8-byte Spill
	movss	%xmm0, 44(%rsp)                 # 4-byte Spill
	movl	$0, 52(%rsp)
	leaq	32(%rsp), %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	leal	7(%r15), %eax
	testl	%r15d, %r15d
	cmovnsl	%r15d, %eax
	sarl	$3, %eax
	leal	7(%r14), %ebx
	testl	%r14d, %r14d
	cmovnsl	%r14d, %ebx
	sarl	$3, %ebx
	shlq	$32, %rbx
	orq	%rax, %rbx
	movl	%r15d, %eax
	imull	%ebp, %eax
	movslq	%eax, %r12
	shlq	$2, %r12
	leaq	24(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	%r14d, %eax
	movl	%ebp, 48(%rsp)                  # 4-byte Spill
	imull	%ebp, %eax
	movslq	%eax, %r13
	shlq	$2, %r13
	leaq	56(%rsp), %rbp
	movq	%rbp, %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	imull	%r14d, %r15d
	movslq	%r15d, %r15
	shlq	$2, %r15
	leaq	16(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movq	64(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movq	72(%rsp), %rsi                  # 8-byte Reload
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	32(%rsp), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$34359738376, %rdx              # imm = 0x800000008
	movq	%rbx, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB8_2
# %bb.1:
	movq	24(%rsp), %rdi
	movq	56(%rsp), %rsi
	movq	16(%rsp), %rdx
	movss	44(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movl	48(%rsp), %ecx                  # 4-byte Reload
	movl	%r14d, %r8d
	callq	_Z34__device_stub__RBFKernel_Tilling_8fPfS_S_ii
.LBB8_2:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	52(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movq	16(%rsp), %rsi
	movq	80(%rsp), %rdi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdi
	callq	hipEventDestroy
	movq	8(%rsp), %rdi
	callq	hipEventDestroy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movss	(%rbx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z18RBF_CUDA_Tilling_8fPA1024_fS0_Pfiii, .Lfunc_end8-_Z18RBF_CUDA_Tilling_8fPA1024_fS0_Pfiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__RBFKernel_Tilling_16fPfS_S_ii # -- Begin function _Z35__device_stub__RBFKernel_Tilling_16fPfS_S_ii
	.type	_Z35__device_stub__RBFKernel_Tilling_16fPfS_S_ii,@function
_Z35__device_stub__RBFKernel_Tilling_16fPfS_S_ii: # @_Z35__device_stub__RBFKernel_Tilling_16fPfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movss	%xmm0, (%rax)
	leaq	56(%rsp), %r9
	movq	%rdi, (%r9)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%r9, 8(%rbx)
	movq	%rdi, 16(%rbx)
	movq	%rsi, 24(%rbx)
	movq	%rdx, 32(%rbx)
	movq	%rcx, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20RBFKernel_Tilling_16fPfS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_Z35__device_stub__RBFKernel_Tilling_16fPfS_S_ii, .Lfunc_end9-_Z35__device_stub__RBFKernel_Tilling_16fPfS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z19RBF_CUDA_Tilling_16fPA1024_fS0_Pfiii # -- Begin function _Z19RBF_CUDA_Tilling_16fPA1024_fS0_Pfiii
	.type	_Z19RBF_CUDA_Tilling_16fPA1024_fS0_Pfiii,@function
_Z19RBF_CUDA_Tilling_16fPA1024_fS0_Pfiii: # @_Z19RBF_CUDA_Tilling_16fPA1024_fS0_Pfiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %r14d
	movl	%r8d, %r15d
	movl	%ecx, %ebp
	movq	%rdx, 80(%rsp)                  # 8-byte Spill
	movq	%rsi, 72(%rsp)                  # 8-byte Spill
	movq	%rdi, 64(%rsp)                  # 8-byte Spill
	movss	%xmm0, 44(%rsp)                 # 4-byte Spill
	movl	$0, 52(%rsp)
	leaq	32(%rsp), %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	leal	15(%r15), %eax
	testl	%r15d, %r15d
	cmovnsl	%r15d, %eax
	sarl	$4, %eax
	leal	15(%r14), %ebx
	testl	%r14d, %r14d
	cmovnsl	%r14d, %ebx
	sarl	$4, %ebx
	shlq	$32, %rbx
	orq	%rax, %rbx
	movl	%r15d, %eax
	imull	%ebp, %eax
	movslq	%eax, %r12
	shlq	$2, %r12
	leaq	24(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	%r14d, %eax
	movl	%ebp, 48(%rsp)                  # 4-byte Spill
	imull	%ebp, %eax
	movslq	%eax, %r13
	shlq	$2, %r13
	leaq	56(%rsp), %rbp
	movq	%rbp, %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	imull	%r14d, %r15d
	movslq	%r15d, %r15
	shlq	$2, %r15
	leaq	16(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movq	64(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movq	72(%rsp), %rsi                  # 8-byte Reload
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	32(%rsp), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movq	%rbx, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB10_2
# %bb.1:
	movq	24(%rsp), %rdi
	movq	56(%rsp), %rsi
	movq	16(%rsp), %rdx
	movss	44(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movl	48(%rsp), %ecx                  # 4-byte Reload
	movl	%r14d, %r8d
	callq	_Z35__device_stub__RBFKernel_Tilling_16fPfS_S_ii
.LBB10_2:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	52(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movq	16(%rsp), %rsi
	movq	80(%rsp), %rdi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdi
	callq	hipEventDestroy
	movq	8(%rsp), %rdi
	callq	hipEventDestroy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movss	(%rbx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_Z19RBF_CUDA_Tilling_16fPA1024_fS0_Pfiii, .Lfunc_end10-_Z19RBF_CUDA_Tilling_16fPA1024_fS0_Pfiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__RBFKernel_Tilling_32fPfS_S_ii # -- Begin function _Z35__device_stub__RBFKernel_Tilling_32fPfS_S_ii
	.type	_Z35__device_stub__RBFKernel_Tilling_32fPfS_S_ii,@function
_Z35__device_stub__RBFKernel_Tilling_32fPfS_S_ii: # @_Z35__device_stub__RBFKernel_Tilling_32fPfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movss	%xmm0, (%rax)
	leaq	56(%rsp), %r9
	movq	%rdi, (%r9)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%r9, 8(%rbx)
	movq	%rdi, 16(%rbx)
	movq	%rsi, 24(%rbx)
	movq	%rdx, 32(%rbx)
	movq	%rcx, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20RBFKernel_Tilling_32fPfS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	_Z35__device_stub__RBFKernel_Tilling_32fPfS_S_ii, .Lfunc_end11-_Z35__device_stub__RBFKernel_Tilling_32fPfS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z19RBF_CUDA_Tilling_32fPA1024_fS0_Pfiii # -- Begin function _Z19RBF_CUDA_Tilling_32fPA1024_fS0_Pfiii
	.type	_Z19RBF_CUDA_Tilling_32fPA1024_fS0_Pfiii,@function
_Z19RBF_CUDA_Tilling_32fPA1024_fS0_Pfiii: # @_Z19RBF_CUDA_Tilling_32fPA1024_fS0_Pfiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %r14d
	movl	%r8d, %r15d
	movl	%ecx, %ebp
	movq	%rdx, 80(%rsp)                  # 8-byte Spill
	movq	%rsi, 72(%rsp)                  # 8-byte Spill
	movq	%rdi, 64(%rsp)                  # 8-byte Spill
	movss	%xmm0, 44(%rsp)                 # 4-byte Spill
	movl	$0, 52(%rsp)
	leaq	32(%rsp), %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	leal	31(%r15), %eax
	testl	%r15d, %r15d
	cmovnsl	%r15d, %eax
	sarl	$5, %eax
	leal	31(%r14), %ebx
	testl	%r14d, %r14d
	cmovnsl	%r14d, %ebx
	sarl	$5, %ebx
	shlq	$32, %rbx
	orq	%rax, %rbx
	movl	%r15d, %eax
	imull	%ebp, %eax
	movslq	%eax, %r12
	shlq	$2, %r12
	leaq	24(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	%r14d, %eax
	movl	%ebp, 48(%rsp)                  # 4-byte Spill
	imull	%ebp, %eax
	movslq	%eax, %r13
	shlq	$2, %r13
	leaq	56(%rsp), %rbp
	movq	%rbp, %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	imull	%r14d, %r15d
	movslq	%r15d, %r15
	shlq	$2, %r15
	leaq	16(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movq	64(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movq	72(%rsp), %rsi                  # 8-byte Reload
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	32(%rsp), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movq	%rbx, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_2
# %bb.1:
	movq	24(%rsp), %rdi
	movq	56(%rsp), %rsi
	movq	16(%rsp), %rdx
	movss	44(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movl	48(%rsp), %ecx                  # 4-byte Reload
	movl	%r14d, %r8d
	callq	_Z35__device_stub__RBFKernel_Tilling_32fPfS_S_ii
.LBB12_2:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	52(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movq	16(%rsp), %rsi
	movq	80(%rsp), %rdi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdi
	callq	hipEventDestroy
	movq	8(%rsp), %rdi
	callq	hipEventDestroy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movss	(%rbx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end12:
	.size	_Z19RBF_CUDA_Tilling_32fPA1024_fS0_Pfiii, .Lfunc_end12-_Z19RBF_CUDA_Tilling_32fPA1024_fS0_Pfiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z9prtResultPfii                # -- Begin function _Z9prtResultPfii
	.type	_Z9prtResultPfii,@function
_Z9prtResultPfii:                       # @_Z9prtResultPfii
	.cfi_startproc
# %bb.0:
	imull	%edx, %esi
	testl	%esi, %esi
	jle	.LBB13_1
# %bb.4:                                # %.lr.ph.preheader
	movl	%esi, %eax
	xorps	%xmm0, %xmm0
	xorl	%ecx, %ecx
.LBB13_5:                               # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	addss	(%rdi,%rcx,4), %xmm0
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB13_5
# %bb.2:                                # %._crit_edge.loopexit
	cvtss2sd	%xmm0, %xmm0
	jmp	.LBB13_3
.LBB13_1:
	xorps	%xmm0, %xmm0
.LBB13_3:                               # %._crit_edge
	movl	$.L.str, %edi
	movb	$1, %al
	jmp	printf                          # TAILCALL
.Lfunc_end13:
	.size	_Z9prtResultPfii, .Lfunc_end13-_Z9prtResultPfii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI14_0:
	.quad	0x3ff0000000000000              # double 1
.LCPI14_2:
	.quad	0x412e848000000000              # double 1.0E+6
.LCPI14_3:
	.quad	0x408f400000000000              # double 1000
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0
.LCPI14_1:
	.long	0x3f800000                      # float 1
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$290864, %rsp                   # imm = 0x47030
	.cfi_def_cfa_offset 290896
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	xorl	%ebx, %ebx
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
	leaq	159792(%rsp), %r14
.LBB14_1:                               # %.preheader60
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB14_2 Depth 2
	xorl	%r15d, %r15d
.LBB14_2:                               #   Parent Loop BB14_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	movsd	.LCPI14_0(%rip), %xmm1          # xmm1 = mem[0],zero
	cltq
	imulq	$274877907, %rax, %rcx          # imm = 0x10624DD3
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$37, %rcx
	addl	%edx, %ecx
	imull	$500, %ecx, %ecx                # imm = 0x1F4
	negl	%ecx
	addl	%ecx, %eax
	incl	%eax
	xorps	%xmm0, %xmm0
	cvtsi2sd	%eax, %xmm0
	divsd	%xmm0, %xmm1
	xorps	%xmm0, %xmm0
	cvtsd2ss	%xmm1, %xmm0
	movss	%xmm0, (%r14,%r15,4)
	incq	%r15
	cmpq	$1024, %r15                     # imm = 0x400
	jne	.LBB14_2
# %bb.3:                                #   in Loop: Header=BB14_1 Depth=1
	incq	%rbx
	addq	$4096, %r14                     # imm = 0x1000
	cmpq	$32, %rbx
	jne	.LBB14_1
# %bb.4:                                # %.preheader.preheader
	leaq	28720(%rsp), %rbx
	xorl	%r14d, %r14d
.LBB14_5:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB14_6 Depth 2
	xorl	%r15d, %r15d
.LBB14_6:                               #   Parent Loop BB14_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	cltq
	imulq	$274877907, %rax, %rcx          # imm = 0x10624DD3
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$37, %rcx
	addl	%edx, %ecx
	imull	$500, %ecx, %ecx                # imm = 0x1F4
	negl	%ecx
	addl	%ecx, %eax
	incl	%eax
	xorps	%xmm0, %xmm0
	cvtsi2sd	%eax, %xmm0
	movsd	.LCPI14_0(%rip), %xmm1          # xmm1 = mem[0],zero
	divsd	%xmm0, %xmm1
	xorps	%xmm0, %xmm0
	cvtsd2ss	%xmm1, %xmm0
	movss	%xmm0, (%rbx,%r15,4)
	incq	%r15
	cmpq	$1024, %r15                     # imm = 0x400
	jne	.LBB14_6
# %bb.7:                                #   in Loop: Header=BB14_5 Depth=1
	incq	%r14
	addq	$4096, %rbx                     # imm = 0x1000
	cmpq	$32, %r14
	jne	.LBB14_5
# %bb.8:
	xorl	%r15d, %r15d
	leaq	32(%rsp), %rbx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movss	.LCPI14_1(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	leaq	159792(%rsp), %rdi
	leaq	28720(%rsp), %rsi
	leaq	24624(%rsp), %rdx
	movl	$1024, %ecx                     # imm = 0x400
	movl	$32, %r8d
	movl	$32, %r9d
	callq	_Z7RBF_CPUfPA1024_fS0_Pfiii
	leaq	16(%rsp), %r14
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	(%r14), %rax
	movq	8(%r14), %rcx
	subq	(%rbx), %rax
	cvtsi2sd	%rax, %xmm2
	subq	8(%rbx), %rcx
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rcx, %xmm0
	xorps	%xmm1, %xmm1
.LBB14_9:                               # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	addss	24624(%rsp,%r15,4), %xmm1
	incq	%r15
	cmpq	$1024, %r15                     # imm = 0x400
	jne	.LBB14_9
# %bb.10:                               # %_Z9prtResultPfii.exit
	mulsd	.LCPI14_2(%rip), %xmm2
	addsd	%xmm0, %xmm2
	movsd	%xmm2, 8(%rsp)                  # 8-byte Spill
	xorps	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	movl	$.L.str.1, %edi
	movsd	8(%rsp), %xmm0                  # 8-byte Reload
                                        # xmm0 = mem[0],zero
	movb	$1, %al
	callq	printf
	movss	.LCPI14_1(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	leaq	159792(%rsp), %rdi
	leaq	28720(%rsp), %rsi
	leaq	20528(%rsp), %rdx
	movl	$1024, %ecx                     # imm = 0x400
	movl	$32, %r8d
	movl	$32, %r9d
	callq	_Z15RBF_CUDA_SimplefPA1024_fS0_Pfiii
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	xorps	%xmm0, %xmm0
	xorl	%eax, %eax
.LBB14_11:                              # %.lr.ph.i23
                                        # =>This Inner Loop Header: Depth=1
	addss	20528(%rsp,%rax,4), %xmm0
	incq	%rax
	cmpq	$1024, %rax                     # imm = 0x400
	jne	.LBB14_11
# %bb.12:                               # %_Z9prtResultPfii.exit28
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	8(%rsp), %xmm0                  # 4-byte Folded Reload
	mulsd	.LCPI14_3(%rip), %xmm0
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	movss	.LCPI14_1(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	leaq	159792(%rsp), %rdi
	leaq	28720(%rsp), %rsi
	leaq	16432(%rsp), %rdx
	movl	$1024, %ecx                     # imm = 0x400
	movl	$32, %r8d
	movl	$32, %r9d
	callq	_Z18RBF_CUDA_Tilling_2fPA1024_fS0_Pfiii
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	xorps	%xmm0, %xmm0
	xorl	%eax, %eax
.LBB14_13:                              # %.lr.ph.i29
                                        # =>This Inner Loop Header: Depth=1
	addss	16432(%rsp,%rax,4), %xmm0
	incq	%rax
	cmpq	$1024, %rax                     # imm = 0x400
	jne	.LBB14_13
# %bb.14:                               # %_Z9prtResultPfii.exit34
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	8(%rsp), %xmm0                  # 4-byte Folded Reload
	mulsd	.LCPI14_3(%rip), %xmm0
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	movss	.LCPI14_1(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	leaq	159792(%rsp), %rdi
	leaq	28720(%rsp), %rsi
	leaq	12336(%rsp), %rdx
	movl	$1024, %ecx                     # imm = 0x400
	movl	$32, %r8d
	movl	$32, %r9d
	callq	_Z18RBF_CUDA_Tilling_4fPA1024_fS0_Pfiii
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	xorps	%xmm0, %xmm0
	xorl	%eax, %eax
.LBB14_15:                              # %.lr.ph.i35
                                        # =>This Inner Loop Header: Depth=1
	addss	12336(%rsp,%rax,4), %xmm0
	incq	%rax
	cmpq	$1024, %rax                     # imm = 0x400
	jne	.LBB14_15
# %bb.16:                               # %_Z9prtResultPfii.exit40
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	8(%rsp), %xmm0                  # 4-byte Folded Reload
	mulsd	.LCPI14_3(%rip), %xmm0
	movl	$.L.str.4, %edi
	movb	$1, %al
	callq	printf
	movss	.LCPI14_1(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	leaq	159792(%rsp), %rdi
	leaq	28720(%rsp), %rsi
	leaq	8240(%rsp), %rdx
	movl	$1024, %ecx                     # imm = 0x400
	movl	$32, %r8d
	movl	$32, %r9d
	callq	_Z18RBF_CUDA_Tilling_8fPA1024_fS0_Pfiii
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	xorps	%xmm0, %xmm0
	xorl	%eax, %eax
.LBB14_17:                              # %.lr.ph.i41
                                        # =>This Inner Loop Header: Depth=1
	addss	8240(%rsp,%rax,4), %xmm0
	incq	%rax
	cmpq	$1024, %rax                     # imm = 0x400
	jne	.LBB14_17
# %bb.18:                               # %_Z9prtResultPfii.exit46
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	8(%rsp), %xmm0                  # 4-byte Folded Reload
	mulsd	.LCPI14_3(%rip), %xmm0
	movl	$.L.str.5, %edi
	movb	$1, %al
	callq	printf
	movss	.LCPI14_1(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	leaq	159792(%rsp), %rdi
	leaq	28720(%rsp), %rsi
	leaq	4144(%rsp), %rdx
	movl	$1024, %ecx                     # imm = 0x400
	movl	$32, %r8d
	movl	$32, %r9d
	callq	_Z19RBF_CUDA_Tilling_16fPA1024_fS0_Pfiii
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	xorps	%xmm0, %xmm0
	xorl	%eax, %eax
.LBB14_19:                              # %.lr.ph.i47
                                        # =>This Inner Loop Header: Depth=1
	addss	4144(%rsp,%rax,4), %xmm0
	incq	%rax
	cmpq	$1024, %rax                     # imm = 0x400
	jne	.LBB14_19
# %bb.20:                               # %_Z9prtResultPfii.exit52
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	8(%rsp), %xmm0                  # 4-byte Folded Reload
	mulsd	.LCPI14_3(%rip), %xmm0
	movl	$.L.str.6, %edi
	movb	$1, %al
	callq	printf
	movss	.LCPI14_1(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	leaq	159792(%rsp), %rdi
	leaq	28720(%rsp), %rsi
	leaq	48(%rsp), %rdx
	movl	$1024, %ecx                     # imm = 0x400
	movl	$32, %r8d
	movl	$32, %r9d
	callq	_Z19RBF_CUDA_Tilling_32fPA1024_fS0_Pfiii
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	xorps	%xmm0, %xmm0
	xorl	%eax, %eax
.LBB14_21:                              # %.lr.ph.i53
                                        # =>This Inner Loop Header: Depth=1
	addss	48(%rsp,%rax,4), %xmm0
	incq	%rax
	cmpq	$1024, %rax                     # imm = 0x400
	jne	.LBB14_21
# %bb.22:                               # %_Z9prtResultPfii.exit58
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	8(%rsp), %xmm0                  # 4-byte Folded Reload
	mulsd	.LCPI14_3(%rip), %xmm0
	movl	$.L.str.7, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$290864, %rsp                   # imm = 0x47030
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end14:
	.size	main, .Lfunc_end14-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB15_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB15_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16RBFKernel_SimplefPfS_S_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19RBFKernel_Tilling_2fPfS_S_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19RBFKernel_Tilling_4fPfS_S_ii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19RBFKernel_Tilling_8fPfS_S_ii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20RBFKernel_Tilling_16fPfS_S_ii, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20RBFKernel_Tilling_32fPfS_S_ii, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end15:
	.size	__hip_module_ctor, .Lfunc_end15-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB16_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB16_2:
	retq
.Lfunc_end16:
	.size	__hip_module_dtor, .Lfunc_end16-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z16RBFKernel_SimplefPfS_S_ii,@object # @_Z16RBFKernel_SimplefPfS_S_ii
	.section	.rodata,"a",@progbits
	.globl	_Z16RBFKernel_SimplefPfS_S_ii
	.p2align	3, 0x0
_Z16RBFKernel_SimplefPfS_S_ii:
	.quad	_Z31__device_stub__RBFKernel_SimplefPfS_S_ii
	.size	_Z16RBFKernel_SimplefPfS_S_ii, 8

	.type	_Z19RBFKernel_Tilling_2fPfS_S_ii,@object # @_Z19RBFKernel_Tilling_2fPfS_S_ii
	.globl	_Z19RBFKernel_Tilling_2fPfS_S_ii
	.p2align	3, 0x0
_Z19RBFKernel_Tilling_2fPfS_S_ii:
	.quad	_Z34__device_stub__RBFKernel_Tilling_2fPfS_S_ii
	.size	_Z19RBFKernel_Tilling_2fPfS_S_ii, 8

	.type	_Z19RBFKernel_Tilling_4fPfS_S_ii,@object # @_Z19RBFKernel_Tilling_4fPfS_S_ii
	.globl	_Z19RBFKernel_Tilling_4fPfS_S_ii
	.p2align	3, 0x0
_Z19RBFKernel_Tilling_4fPfS_S_ii:
	.quad	_Z34__device_stub__RBFKernel_Tilling_4fPfS_S_ii
	.size	_Z19RBFKernel_Tilling_4fPfS_S_ii, 8

	.type	_Z19RBFKernel_Tilling_8fPfS_S_ii,@object # @_Z19RBFKernel_Tilling_8fPfS_S_ii
	.globl	_Z19RBFKernel_Tilling_8fPfS_S_ii
	.p2align	3, 0x0
_Z19RBFKernel_Tilling_8fPfS_S_ii:
	.quad	_Z34__device_stub__RBFKernel_Tilling_8fPfS_S_ii
	.size	_Z19RBFKernel_Tilling_8fPfS_S_ii, 8

	.type	_Z20RBFKernel_Tilling_16fPfS_S_ii,@object # @_Z20RBFKernel_Tilling_16fPfS_S_ii
	.globl	_Z20RBFKernel_Tilling_16fPfS_S_ii
	.p2align	3, 0x0
_Z20RBFKernel_Tilling_16fPfS_S_ii:
	.quad	_Z35__device_stub__RBFKernel_Tilling_16fPfS_S_ii
	.size	_Z20RBFKernel_Tilling_16fPfS_S_ii, 8

	.type	_Z20RBFKernel_Tilling_32fPfS_S_ii,@object # @_Z20RBFKernel_Tilling_32fPfS_S_ii
	.globl	_Z20RBFKernel_Tilling_32fPfS_S_ii
	.p2align	3, 0x0
_Z20RBFKernel_Tilling_32fPfS_S_ii:
	.quad	_Z35__device_stub__RBFKernel_Tilling_32fPfS_S_ii
	.size	_Z20RBFKernel_Tilling_32fPfS_S_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"The sum of the matrix: %.2lf\n"
	.size	.L.str, 30

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"CPU method running time: %.2f us\n"
	.size	.L.str.1, 34

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"GPU simple method running time: %.2f us\n"
	.size	.L.str.2, 41

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"GPU tilling method (width 2) running time: %.2f us\n"
	.size	.L.str.3, 52

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"GPU tilling method (width 4) running time: %.2f us\n"
	.size	.L.str.4, 52

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"GPU tilling method (width 8) running time: %.2f us\n"
	.size	.L.str.5, 52

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"GPU tilling method (width 16) running time: %.2f us\n"
	.size	.L.str.6, 53

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"GPU tilling method (width 32) running time: %.2f us\n"
	.size	.L.str.7, 53

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z16RBFKernel_SimplefPfS_S_ii"
	.size	.L__unnamed_1, 30

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z19RBFKernel_Tilling_2fPfS_S_ii"
	.size	.L__unnamed_2, 33

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z19RBFKernel_Tilling_4fPfS_S_ii"
	.size	.L__unnamed_3, 33

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z19RBFKernel_Tilling_8fPfS_S_ii"
	.size	.L__unnamed_4, 33

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z20RBFKernel_Tilling_16fPfS_S_ii"
	.size	.L__unnamed_5, 34

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z20RBFKernel_Tilling_32fPfS_S_ii"
	.size	.L__unnamed_6, 34

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z31__device_stub__RBFKernel_SimplefPfS_S_ii
	.addrsig_sym _Z34__device_stub__RBFKernel_Tilling_2fPfS_S_ii
	.addrsig_sym _Z34__device_stub__RBFKernel_Tilling_4fPfS_S_ii
	.addrsig_sym _Z34__device_stub__RBFKernel_Tilling_8fPfS_S_ii
	.addrsig_sym _Z35__device_stub__RBFKernel_Tilling_16fPfS_S_ii
	.addrsig_sym _Z35__device_stub__RBFKernel_Tilling_32fPfS_S_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z16RBFKernel_SimplefPfS_S_ii
	.addrsig_sym _Z19RBFKernel_Tilling_2fPfS_S_ii
	.addrsig_sym _Z19RBFKernel_Tilling_4fPfS_S_ii
	.addrsig_sym _Z19RBFKernel_Tilling_8fPfS_S_ii
	.addrsig_sym _Z20RBFKernel_Tilling_16fPfS_S_ii
	.addrsig_sym _Z20RBFKernel_Tilling_32fPfS_S_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z16RBFKernel_SimplefPfS_S_ii ; -- Begin function _Z16RBFKernel_SimplefPfS_S_ii
	.globl	_Z16RBFKernel_SimplefPfS_S_ii
	.p2align	8
	.type	_Z16RBFKernel_SimplefPfS_S_ii,@function
_Z16RBFKernel_SimplefPfS_S_ii:          ; @_Z16RBFKernel_SimplefPfS_S_ii
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x8
	v_and_b32_e32 v7, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s10, 1
	s_cbranch_scc1 .LBB0_3
; %bb.1:                                ; %.lr.ph
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v0, s10
	v_mov_b32_e32 v2, 0
	v_mul_lo_u32 v3, v7, s10
	v_mov_b32_e32 v4, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	v_lshlrev_b64 v[8:9], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s6, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v9, vcc_lo
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v1, v[5:6], off
	global_load_b32 v8, v[3:4], off
	v_add_co_u32 v3, vcc_lo, v3, 4
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	v_add_co_u32 v5, vcc_lo, v5, 4
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_add_i32 s10, s10, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s10, 0
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v1, v1, v8
	v_fmac_f32_e32 v2, v1, v1
	s_cbranch_scc0 .LBB0_2
	s_branch .LBB0_4
.LBB0_3:
	v_mov_b32_e32 v2, 0
.LBB0_4:                                ; %Flow50
	s_load_b32 s0, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f32_e64 v1, s0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, s0, v1
	v_div_scale_f32 v3, null, v1, v1, -v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	v_fmac_f32_e32 v4, v5, v4
	v_div_scale_f32 v6, vcc_lo, -v2, v1, -v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v6, v4
	v_fma_f32 v8, -v3, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v8, v4
	v_fma_f32 v3, -v3, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v3, v3, v4, v5
	v_div_fixup_f32 v3, v3, v1, -v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v3
	v_mul_f32_e32 v1, 0x3fb8aa3b, v3
	v_fma_f32 v2, 0x3fb8aa3b, v3, -v1
	v_rndne_f32_e32 v4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmamk_f32 v2, v3, 0x32a5705f, v2 :: v_dual_sub_f32 v1, v1, v4
	v_add_f32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v5, v1
	v_mad_u64_u32 v[1:2], null, v7, s11, v[0:1]
	v_cvt_i32_f32_e32 v0, v4
	v_ashrrev_i32_e32 v2, 31, v1
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v0, v5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, 0, v0, vcc_lo
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v3
	v_cndmask_b32_e32 v2, 0x7f800000, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16RBFKernel_SimplefPfS_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 12
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z16RBFKernel_SimplefPfS_S_ii, .Lfunc_end0-_Z16RBFKernel_SimplefPfS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 472
; NumSgprs: 14
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 14
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z19RBFKernel_Tilling_2fPfS_S_ii ; -- Begin function _Z19RBFKernel_Tilling_2fPfS_S_ii
	.globl	_Z19RBFKernel_Tilling_2fPfS_S_ii
	.p2align	8
	.type	_Z19RBFKernel_Tilling_2fPfS_S_ii,@function
_Z19RBFKernel_Tilling_2fPfS_S_ii:       ; @_Z19RBFKernel_Tilling_2fPfS_S_ii
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x8
	v_dual_mov_b32 v8, 0 :: v_dual_and_b32 v5, 0x3ff, v0
	v_bfe_u32 v6, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v7, s14, 1, v5
	v_lshl_add_u32 v0, s15, 1, v6
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s10, 2
	s_cbranch_scc1 .LBB1_3
; %bb.1:                                ; %.lr.ph
	v_dual_mov_b32 v8, 0 :: v_dual_lshlrev_b32 v9, 3, v5
	v_lshl_add_u32 v10, v6, 3, 16
	v_mad_u64_u32 v[1:2], null, v0, s10, v[5:6]
	v_mad_u64_u32 v[3:4], null, v7, s10, v[6:7]
	s_lshr_b32 s2, s10, 31
	v_lshl_add_u32 v6, v6, 2, v9
	v_lshl_add_u32 v5, v5, 2, v10
	s_add_i32 s2, s10, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_ashr_i32 s2, s2, 1
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s2, s2, -1
	s_cmp_eq_u32 s2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[11:12], 2, v[3:4]
	v_lshlrev_b64 v[13:14], 2, v[1:2]
	v_add_nc_u32_e32 v3, 2, v3
	v_add_nc_u32_e32 v1, 2, v1
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v11, vcc_lo, s4, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
	v_add_co_u32 v13, vcc_lo, s6, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s7, v14, vcc_lo
	global_load_b32 v2, v[11:12], off
	global_load_b32 v4, v[13:14], off
	s_waitcnt vmcnt(1)
	ds_store_b32 v6, v2
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b64 v[11:12], v9
	ds_load_b64 v[13:14], v10
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_sub_f32_e32 v2, v11, v13
	v_sub_f32_e32 v4, v12, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, v2, v2
	v_fmac_f32_e32 v8, v4, v4
	s_cbranch_scc0 .LBB1_2
.LBB1_3:                                ; %Flow68
	s_load_b32 s0, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f32_e64 v1, s0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, s0, v1
	v_div_scale_f32 v2, null, v1, v1, -v8
	v_div_scale_f32 v5, vcc_lo, -v8, v1, -v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v4, -v2, v3, 1.0
	v_fmac_f32_e32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, v5, v3
	v_fma_f32 v6, -v2, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v6, v3
	v_fma_f32 v2, -v2, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v2, v2, v3, v4
	v_div_fixup_f32 v3, v2, v1, -v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v1, 0x3fb8aa3b, v3
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v3
	v_fma_f32 v2, 0x3fb8aa3b, v3, -v1
	v_rndne_f32_e32 v4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmamk_f32 v2, v3, 0x32a5705f, v2 :: v_dual_sub_f32 v1, v1, v4
	v_add_f32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v5, v1
	v_mad_u64_u32 v[1:2], null, v7, s11, v[0:1]
	v_cvt_i32_f32_e32 v0, v4
	v_ashrrev_i32_e32 v2, 31, v1
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v0, v5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, 0, v0, vcc_lo
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v3
	v_cndmask_b32_e32 v2, 0x7f800000, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19RBFKernel_Tilling_2fPfS_S_ii
		.amdhsa_group_segment_fixed_size 32
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z19RBFKernel_Tilling_2fPfS_S_ii, .Lfunc_end1-_Z19RBFKernel_Tilling_2fPfS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 592
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 32 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z19RBFKernel_Tilling_4fPfS_S_ii ; -- Begin function _Z19RBFKernel_Tilling_4fPfS_S_ii
	.globl	_Z19RBFKernel_Tilling_4fPfS_S_ii
	.p2align	8
	.type	_Z19RBFKernel_Tilling_4fPfS_S_ii,@function
_Z19RBFKernel_Tilling_4fPfS_S_ii:       ; @_Z19RBFKernel_Tilling_4fPfS_S_ii
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x8
	v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v4, 0x3ff, v0
	v_bfe_u32 v5, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v6, s14, 2, v4
	v_lshl_add_u32 v0, s15, 2, v5
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s10, 4
	s_cbranch_scc1 .LBB2_5
; %bb.1:                                ; %.lr.ph
	v_lshlrev_b32_e32 v7, 4, v4
	v_lshl_add_u32 v8, v5, 4, 64
	v_mad_u64_u32 v[1:2], null, v6, s10, v[5:6]
	s_ashr_i32 s2, s10, 31
	v_mad_u64_u32 v[2:3], null, v0, s10, v[4:5]
	s_lshr_b32 s2, s2, 30
	v_lshl_add_u32 v5, v5, 2, v7
	v_lshl_add_u32 v4, v4, 2, v8
	v_mov_b32_e32 v3, 0
	s_add_i32 s2, s10, s2
	s_mov_b32 s3, 0
	s_ashr_i32 s2, s2, 2
.LBB2_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_3 Depth 2
	s_lshl_b32 s10, s3, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, s10, v1
	v_add_nc_u32_e32 v11, s10, v2
	s_mov_b32 s10, 0
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v12, 31, v11
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_add_co_u32 v9, vcc_lo, s4, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
	v_add_co_u32 v11, vcc_lo, s6, v11
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
	global_load_b32 v9, v[9:10], off
	global_load_b32 v10, v[11:12], off
	s_waitcnt vmcnt(1)
	ds_store_b32 v5, v9
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v10
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB2_3:                                ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v9, s10, v7
	v_add_nc_u32_e32 v10, s10, v8
	s_add_i32 s10, s10, 4
	ds_load_b32 v9, v9
	ds_load_b32 v10, v10
	s_cmp_eq_u32 s10, 16
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v9, v9, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v3, v9, v9
	s_cbranch_scc0 .LBB2_3
; %bb.4:                                ;   in Loop: Header=BB2_2 Depth=1
	s_add_i32 s3, s3, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s3, s2
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB2_2
.LBB2_5:                                ; %Flow67
	s_load_b32 s0, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f32_e64 v1, s0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, s0, v1
	v_div_scale_f32 v2, null, v1, v1, -v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v2, v4, 1.0
	v_fmac_f32_e32 v4, v5, v4
	v_div_scale_f32 v7, vcc_lo, -v3, v1, -v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v7, v4
	v_fma_f32 v8, -v2, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v8, v4
	v_fma_f32 v2, -v2, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v2, v2, v4, v5
	v_div_fixup_f32 v3, v2, v1, -v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v3
	v_mul_f32_e32 v1, 0x3fb8aa3b, v3
	v_fma_f32 v2, 0x3fb8aa3b, v3, -v1
	v_rndne_f32_e32 v4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmamk_f32 v2, v3, 0x32a5705f, v2 :: v_dual_sub_f32 v1, v1, v4
	v_add_f32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v5, v1
	v_mad_u64_u32 v[1:2], null, v6, s11, v[0:1]
	v_cvt_i32_f32_e32 v0, v4
	v_ashrrev_i32_e32 v2, 31, v1
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v0, v5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, 0, v0, vcc_lo
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v3
	v_cndmask_b32_e32 v2, 0x7f800000, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19RBFKernel_Tilling_4fPfS_S_ii
		.amdhsa_group_segment_fixed_size 128
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z19RBFKernel_Tilling_4fPfS_S_ii, .Lfunc_end2-_Z19RBFKernel_Tilling_4fPfS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 628
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 128 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z19RBFKernel_Tilling_8fPfS_S_ii ; -- Begin function _Z19RBFKernel_Tilling_8fPfS_S_ii
	.globl	_Z19RBFKernel_Tilling_8fPfS_S_ii
	.p2align	8
	.type	_Z19RBFKernel_Tilling_8fPfS_S_ii,@function
_Z19RBFKernel_Tilling_8fPfS_S_ii:       ; @_Z19RBFKernel_Tilling_8fPfS_S_ii
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x8
	v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v4, 0x3ff, v0
	v_bfe_u32 v5, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v6, s14, 3, v4
	v_lshl_add_u32 v0, s15, 3, v5
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s10, 8
	s_cbranch_scc1 .LBB3_5
; %bb.1:                                ; %.lr.ph
	v_lshlrev_b32_e32 v7, 5, v4
	v_lshl_add_u32 v8, v5, 5, 0x100
	v_mad_u64_u32 v[1:2], null, v6, s10, v[5:6]
	s_ashr_i32 s2, s10, 31
	v_mad_u64_u32 v[2:3], null, v0, s10, v[4:5]
	s_lshr_b32 s2, s2, 29
	v_lshl_add_u32 v5, v5, 2, v7
	v_lshl_add_u32 v4, v4, 2, v8
	v_mov_b32_e32 v3, 0
	s_add_i32 s2, s10, s2
	s_mov_b32 s3, 0
	s_ashr_i32 s2, s2, 3
.LBB3_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_3 Depth 2
	s_lshl_b32 s10, s3, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, s10, v1
	v_add_nc_u32_e32 v11, s10, v2
	s_mov_b32 s10, 0
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v12, 31, v11
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_add_co_u32 v9, vcc_lo, s4, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
	v_add_co_u32 v11, vcc_lo, s6, v11
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
	global_load_b32 v9, v[9:10], off
	global_load_b32 v10, v[11:12], off
	s_waitcnt vmcnt(1)
	ds_store_b32 v5, v9
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v10
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB3_3:                                ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v9, s10, v7
	v_add_nc_u32_e32 v10, s10, v8
	s_add_i32 s10, s10, 4
	ds_load_b32 v9, v9
	ds_load_b32 v10, v10
	s_cmp_eq_u32 s10, 32
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v9, v9, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v3, v9, v9
	s_cbranch_scc0 .LBB3_3
; %bb.4:                                ;   in Loop: Header=BB3_2 Depth=1
	s_add_i32 s3, s3, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s3, s2
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB3_2
.LBB3_5:                                ; %Flow67
	s_load_b32 s0, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f32_e64 v1, s0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, s0, v1
	v_div_scale_f32 v2, null, v1, v1, -v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v2, v4, 1.0
	v_fmac_f32_e32 v4, v5, v4
	v_div_scale_f32 v7, vcc_lo, -v3, v1, -v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v7, v4
	v_fma_f32 v8, -v2, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v8, v4
	v_fma_f32 v2, -v2, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v2, v2, v4, v5
	v_div_fixup_f32 v3, v2, v1, -v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v3
	v_mul_f32_e32 v1, 0x3fb8aa3b, v3
	v_fma_f32 v2, 0x3fb8aa3b, v3, -v1
	v_rndne_f32_e32 v4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmamk_f32 v2, v3, 0x32a5705f, v2 :: v_dual_sub_f32 v1, v1, v4
	v_add_f32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v5, v1
	v_mad_u64_u32 v[1:2], null, v6, s11, v[0:1]
	v_cvt_i32_f32_e32 v0, v4
	v_ashrrev_i32_e32 v2, 31, v1
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v0, v5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, 0, v0, vcc_lo
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v3
	v_cndmask_b32_e32 v2, 0x7f800000, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19RBFKernel_Tilling_8fPfS_S_ii
		.amdhsa_group_segment_fixed_size 512
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z19RBFKernel_Tilling_8fPfS_S_ii, .Lfunc_end3-_Z19RBFKernel_Tilling_8fPfS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 632
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 512 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z20RBFKernel_Tilling_16fPfS_S_ii ; -- Begin function _Z20RBFKernel_Tilling_16fPfS_S_ii
	.globl	_Z20RBFKernel_Tilling_16fPfS_S_ii
	.p2align	8
	.type	_Z20RBFKernel_Tilling_16fPfS_S_ii,@function
_Z20RBFKernel_Tilling_16fPfS_S_ii:      ; @_Z20RBFKernel_Tilling_16fPfS_S_ii
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x8
	v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v4, 0x3ff, v0
	v_bfe_u32 v5, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v6, s14, 4, v4
	v_lshl_add_u32 v0, s15, 4, v5
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s10, 16
	s_cbranch_scc1 .LBB4_5
; %bb.1:                                ; %.lr.ph
	v_lshlrev_b32_e32 v7, 6, v4
	v_lshl_add_u32 v8, v5, 6, 0x400
	v_mad_u64_u32 v[1:2], null, v6, s10, v[5:6]
	s_ashr_i32 s2, s10, 31
	v_mad_u64_u32 v[2:3], null, v0, s10, v[4:5]
	s_lshr_b32 s2, s2, 28
	v_lshl_add_u32 v5, v5, 2, v7
	v_lshl_add_u32 v4, v4, 2, v8
	v_mov_b32_e32 v3, 0
	s_add_i32 s2, s10, s2
	s_mov_b32 s3, 0
	s_ashr_i32 s2, s2, 4
.LBB4_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB4_3 Depth 2
	s_lshl_b32 s10, s3, 4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, s10, v1
	v_add_nc_u32_e32 v11, s10, v2
	s_mov_b32 s10, 0
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v12, 31, v11
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_add_co_u32 v9, vcc_lo, s4, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
	v_add_co_u32 v11, vcc_lo, s6, v11
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
	global_load_b32 v9, v[9:10], off
	global_load_b32 v10, v[11:12], off
	s_waitcnt vmcnt(1)
	ds_store_b32 v5, v9
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v10
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB4_3:                                ;   Parent Loop BB4_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v9, s10, v7
	v_add_nc_u32_e32 v10, s10, v8
	s_add_i32 s10, s10, 4
	ds_load_b32 v9, v9
	ds_load_b32 v10, v10
	s_cmp_eq_u32 s10, 64
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v9, v9, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v3, v9, v9
	s_cbranch_scc0 .LBB4_3
; %bb.4:                                ;   in Loop: Header=BB4_2 Depth=1
	s_add_i32 s3, s3, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s3, s2
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB4_2
.LBB4_5:                                ; %Flow67
	s_load_b32 s0, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f32_e64 v1, s0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, s0, v1
	v_div_scale_f32 v2, null, v1, v1, -v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v2, v4, 1.0
	v_fmac_f32_e32 v4, v5, v4
	v_div_scale_f32 v7, vcc_lo, -v3, v1, -v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v7, v4
	v_fma_f32 v8, -v2, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v8, v4
	v_fma_f32 v2, -v2, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v2, v2, v4, v5
	v_div_fixup_f32 v3, v2, v1, -v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v3
	v_mul_f32_e32 v1, 0x3fb8aa3b, v3
	v_fma_f32 v2, 0x3fb8aa3b, v3, -v1
	v_rndne_f32_e32 v4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmamk_f32 v2, v3, 0x32a5705f, v2 :: v_dual_sub_f32 v1, v1, v4
	v_add_f32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v5, v1
	v_mad_u64_u32 v[1:2], null, v6, s11, v[0:1]
	v_cvt_i32_f32_e32 v0, v4
	v_ashrrev_i32_e32 v2, 31, v1
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v0, v5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, 0, v0, vcc_lo
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v3
	v_cndmask_b32_e32 v2, 0x7f800000, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20RBFKernel_Tilling_16fPfS_S_ii
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z20RBFKernel_Tilling_16fPfS_S_ii, .Lfunc_end4-_Z20RBFKernel_Tilling_16fPfS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 632
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z20RBFKernel_Tilling_32fPfS_S_ii ; -- Begin function _Z20RBFKernel_Tilling_32fPfS_S_ii
	.globl	_Z20RBFKernel_Tilling_32fPfS_S_ii
	.p2align	8
	.type	_Z20RBFKernel_Tilling_32fPfS_S_ii,@function
_Z20RBFKernel_Tilling_32fPfS_S_ii:      ; @_Z20RBFKernel_Tilling_32fPfS_S_ii
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x8
	v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v4, 0x3ff, v0
	v_bfe_u32 v5, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v6, s14, 5, v4
	v_lshl_add_u32 v0, s15, 5, v5
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s10, 32
	s_cbranch_scc1 .LBB5_5
; %bb.1:                                ; %.lr.ph
	v_lshlrev_b32_e32 v7, 7, v4
	v_lshl_add_u32 v8, v5, 7, 0x1000
	v_mad_u64_u32 v[1:2], null, v6, s10, v[5:6]
	s_ashr_i32 s2, s10, 31
	v_mad_u64_u32 v[2:3], null, v0, s10, v[4:5]
	s_lshr_b32 s2, s2, 27
	v_lshl_add_u32 v5, v5, 2, v7
	v_lshl_add_u32 v4, v4, 2, v8
	v_mov_b32_e32 v3, 0
	s_add_i32 s2, s10, s2
	s_mov_b32 s3, 0
	s_ashr_i32 s2, s2, 5
.LBB5_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB5_3 Depth 2
	s_lshl_b32 s10, s3, 5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, s10, v1
	v_add_nc_u32_e32 v11, s10, v2
	s_mov_b32 s10, 0
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v12, 31, v11
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_add_co_u32 v9, vcc_lo, s4, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
	v_add_co_u32 v11, vcc_lo, s6, v11
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
	global_load_b32 v9, v[9:10], off
	global_load_b32 v10, v[11:12], off
	s_waitcnt vmcnt(1)
	ds_store_b32 v5, v9
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v10
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB5_3:                                ;   Parent Loop BB5_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v9, s10, v7
	v_add_nc_u32_e32 v10, s10, v8
	s_add_i32 s10, s10, 4
	ds_load_b32 v9, v9
	ds_load_b32 v10, v10
	s_cmpk_eq_i32 s10, 0x80
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v9, v9, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v3, v9, v9
	s_cbranch_scc0 .LBB5_3
; %bb.4:                                ;   in Loop: Header=BB5_2 Depth=1
	s_add_i32 s3, s3, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s3, s2
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB5_2
.LBB5_5:                                ; %Flow67
	s_load_b32 s0, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f32_e64 v1, s0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, s0, v1
	v_div_scale_f32 v2, null, v1, v1, -v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v2, v4, 1.0
	v_fmac_f32_e32 v4, v5, v4
	v_div_scale_f32 v7, vcc_lo, -v3, v1, -v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v7, v4
	v_fma_f32 v8, -v2, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v8, v4
	v_fma_f32 v2, -v2, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v2, v2, v4, v5
	v_div_fixup_f32 v3, v2, v1, -v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v3
	v_mul_f32_e32 v1, 0x3fb8aa3b, v3
	v_fma_f32 v2, 0x3fb8aa3b, v3, -v1
	v_rndne_f32_e32 v4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmamk_f32 v2, v3, 0x32a5705f, v2 :: v_dual_sub_f32 v1, v1, v4
	v_add_f32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v5, v1
	v_mad_u64_u32 v[1:2], null, v6, s11, v[0:1]
	v_cvt_i32_f32_e32 v0, v4
	v_ashrrev_i32_e32 v2, 31, v1
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v0, v5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, 0, v0, vcc_lo
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v3
	v_cndmask_b32_e32 v2, 0x7f800000, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20RBFKernel_Tilling_32fPfS_S_ii
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z20RBFKernel_Tilling_32fPfS_S_ii, .Lfunc_end5-_Z20RBFKernel_Tilling_32fPfS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 632
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16RBFKernel_SimplefPfS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     14
    .sgpr_spill_count: 0
    .symbol:         _Z16RBFKernel_SimplefPfS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 32
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19RBFKernel_Tilling_2fPfS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19RBFKernel_Tilling_2fPfS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 128
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19RBFKernel_Tilling_4fPfS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19RBFKernel_Tilling_4fPfS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
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        .size:           8
        .value_kind:     global_buffer
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      - .offset:         32
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        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 512
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19RBFKernel_Tilling_8fPfS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19RBFKernel_Tilling_8fPfS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
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        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
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        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 2048
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20RBFKernel_Tilling_16fPfS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z20RBFKernel_Tilling_16fPfS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
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        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 8192
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20RBFKernel_Tilling_32fPfS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z20RBFKernel_Tilling_32fPfS_S_ii.kd
    .uniform_work_group_size: 1
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    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
