#include <cuda_runtime_api.h>

#define OFFSET_BANK(idx) ({ __typeof__ (idx) _idx = idx; ((_idx) + ((_idx) / 32)); })

__global__ void conv_diag_affine_white_var_fwd_batch_kernel(
    const float *in_act,
    int spatial_dim,
    int num_channels,
    int batch_size,
    const float *mean,
    const float *var,
    float epsilon,
    float *out_act)
{
  int idx = threadIdx.x + blockIdx.x * blockDim.x;
  int u = idx % spatial_dim;
  int c = (idx / spatial_dim) % num_channels;
  int batch_idx = idx / (spatial_dim * num_channels);
  if (u < spatial_dim && c < num_channels && batch_idx < batch_size) {
    float m = mean[c];
    float v = var[c];
    float y = (in_act[idx] - m) * rsqrtf(v + epsilon);
    out_act[idx] = y;
  }
}

extern "C" void neuralops_cuda_conv2d_whiten_fwd(
    const float *in_act,
    size_t spatial_dim,
    size_t num_channels,
    size_t batch_size,
    const float *mean,
    const float *var,
    float epsilon,
    float *out_act,
    cudaStream_t stream)
{
  int n = spatial_dim * num_channels * batch_size;
  conv_diag_affine_white_var_fwd_batch_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      in_act, spatial_dim, num_channels, batch_size, mean, var, epsilon, out_act);
}

__global__ void estimate_conv_mean_fast2_batch_kernel(
    const float *src,
    int spatial_dim,
    int num_channels,
    int batch_size,
    float *mean)
{
  __shared__ float mean_cache[1024+32];
  int idx = threadIdx.x + blockIdx.x * blockDim.x;
  int bank_idx = OFFSET_BANK(threadIdx.x);
  int block_spatial_dim = (spatial_dim+16*32-1)/(16*32);
  int warp_idx = idx % 32;
  int c = (idx / 32) % num_channels;
  //int u0 = warp_idx + ((idx / (32 * num_channels)) % block_spatial_dim) * (16*32);
  int u0 = ((idx / (32 * num_channels)) % block_spatial_dim) * (16*32);
  int batch_idx = idx / (32 * num_channels * block_spatial_dim);
  if (c < num_channels && u0 < spatial_dim && batch_idx < batch_size) {
    float y = 0.0f;
    /*int i0 = c * spatial_dim + batch_idx * spatial_dim * num_channels;
    int u_limit = min(spatial_dim, u0 + 16*32);
    for (int u = u0; u < u_limit; u += 32) {
      int i = i0 + u;
      y += src[i];
    }*/
    int i0 = warp_idx + u0 + c * spatial_dim + batch_idx * spatial_dim * num_channels;
    int i_limit = i0 + min(spatial_dim - warp_idx - u0, 16*32);
    for (int v = 0; v < 16*32; v += 32) {
      int i = i0 + v;
      if (i < i_limit) {
        y += src[i];
      }
    }
    mean_cache[bank_idx] = y;
  } else {
    mean_cache[bank_idx] = 0.0f;
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 2 == 0) {
      mean_cache[bank_idx] += mean_cache[bank_idx+1];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 4 == 0) {
      mean_cache[bank_idx] += mean_cache[bank_idx+2];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 8 == 0) {
      mean_cache[bank_idx] += mean_cache[bank_idx+4];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 16 == 0) {
      mean_cache[bank_idx] += mean_cache[bank_idx+8];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 32 == 0 && u0 < spatial_dim) {
      float y = (mean_cache[bank_idx] + mean_cache[bank_idx+16]) / ((float)(spatial_dim) * (float)(batch_size));
      atomicAdd(&mean[c], y);
    }
  }
}

extern "C" void neuralops_cuda_conv2d_mean_fwd(
    const float *src,
    size_t spatial_dim,
    size_t num_channels,
    size_t batch_size,
    float *mean,
    cudaStream_t stream)
{
  //int n = ((spatial_dim+32-1)/32) * channels * batch_size;
  int block_spatial_dim = (spatial_dim+16*32-1)/(16*32);
  int n = 32 * num_channels * block_spatial_dim * batch_size;
  estimate_conv_mean_fast2_batch_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      src, spatial_dim, num_channels, batch_size, mean);
}

__global__ void estimate_conv_var_fast2_batch_kernel(
    const float *src,
    int spatial_dim,
    int num_channels,
    int batch_size,
    const float *mean,
    float *var)
{
  __shared__ float var_cache[1024+32];
  int idx = threadIdx.x + blockIdx.x * blockDim.x;
  int bank_idx = OFFSET_BANK(threadIdx.x);
  int block_spatial_dim = (spatial_dim+16*32-1)/(16*32);
  int warp_idx = idx % 32;
  int c = (idx / 32) % num_channels;
  //int u0 = warp_idx + ((idx / (32 * num_channels)) % block_spatial_dim) * (16*32);
  int u0 = ((idx / (32 * num_channels)) % block_spatial_dim) * (16*32);
  int batch_idx = idx / (32 * num_channels * block_spatial_dim);
  if (c < num_channels && u0 < spatial_dim && batch_idx < batch_size) {
    float mean_c = mean[c];
    float y = 0.0f;
    /*int i0 = c * spatial_dim + batch_idx * spatial_dim * num_channels;
    int u_limit = min(spatial_dim, u0 + 16*32);
    for (int u = u0; u < u_limit; u += 32) {
      int i = i0 + u;
      float delta = src[i] - mean_c;
      y += delta * delta;
    }*/
    int i0 = warp_idx + u0 + c * spatial_dim + batch_idx * spatial_dim * num_channels;
    int i_limit = i0 + min(spatial_dim - warp_idx - u0, 16*32);
    for (int v = 0; v < 16*32; v += 32) {
      int i = i0 + v;
      if (i < i_limit) {
        float delta = src[i] - mean_c;
        y += delta * delta;
      }
    }
    var_cache[bank_idx] = y;
  } else {
    var_cache[bank_idx] = 0.0f;
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 2 == 0) {
      var_cache[bank_idx] += var_cache[bank_idx+1];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 4 == 0) {
      var_cache[bank_idx] += var_cache[bank_idx+2];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 8 == 0) {
      var_cache[bank_idx] += var_cache[bank_idx+4];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 16 == 0) {
      var_cache[bank_idx] += var_cache[bank_idx+8];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 32 == 0 && u0 < spatial_dim) {
      float y = (var_cache[bank_idx] + var_cache[bank_idx+16]) / ((float)(spatial_dim-1) * (float)(batch_size-1));
      atomicAdd(&var[c], y);
    }
  }
}

extern "C" void neuralops_cuda_conv2d_var_fwd(
    const float *src,
    size_t spatial_dim,
    size_t num_channels,
    size_t batch_size,
    const float *mean,
    float *var,
    cudaStream_t stream)
{
  //int n = ((spatial_dim+32-1)/32) * channels * batch_size;
  int block_spatial_dim = (spatial_dim+16*32-1)/(16*32);
  int n = 32 * num_channels * block_spatial_dim * batch_size;
  estimate_conv_var_fast2_batch_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      src, spatial_dim, num_channels, batch_size, mean, var);
}

__global__ void conv_bnorm_bwd_var_batch_kernel(
    const float *in_act,
    int spatial_dim,
    int num_channels,
    int batch_size,
    const float *out_delta,
    const float *mean,
    const float *var,
    float epsilon,
    float *var_grad)
{
  __shared__ float d_sigma_cache[1024+32];
  int idx = threadIdx.x + blockIdx.x * blockDim.x;
  int bank_idx = OFFSET_BANK(threadIdx.x);
  int block_spatial_dim = (spatial_dim+16*32-1)/(16*32);
  int warp_idx = idx % 32;
  int c = (idx / 32) % num_channels;
  int u0 = warp_idx + ((idx / (32 * num_channels)) % block_spatial_dim) * (16*32);
  int batch_idx = idx / (32 * num_channels * block_spatial_dim);
  if (c < num_channels && u0 < spatial_dim && batch_idx < batch_size) {
    float mu = mean[c];
    float sigma = var[c];
    float inv_sqrt_sigma = rsqrtf(sigma + epsilon);
    float d_sigma = 0.0f;
    int i0 = c * spatial_dim + batch_idx * spatial_dim * num_channels;
    int u_limit = min(spatial_dim, u0 + 16*32);
    for (int u = u0; u < u_limit; u += 32) {
      int i = i0 + u;
      d_sigma += out_delta[i] * -0.5f * inv_sqrt_sigma / (sigma + epsilon) * (in_act[i] - mu);
    }
    d_sigma_cache[bank_idx] = d_sigma;
  } else {
    d_sigma_cache[bank_idx] = 0.0f;
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 2 == 0) {
      d_sigma_cache[bank_idx] += d_sigma_cache[bank_idx+1];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 4 == 0) {
      d_sigma_cache[bank_idx] += d_sigma_cache[bank_idx+2];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 8 == 0) {
      d_sigma_cache[bank_idx] += d_sigma_cache[bank_idx+4];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 16 == 0) {
      d_sigma_cache[bank_idx] += d_sigma_cache[bank_idx+8];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 32 == 0 && u0 < spatial_dim) {
      float d_sigma = d_sigma_cache[bank_idx] + d_sigma_cache[bank_idx+16];
      atomicAdd(&var_grad[c], d_sigma);
    }
  }
}

__global__ void conv_bnorm_bwd_mean_batch_kernel(
    const float *in_act,
    int spatial_dim,
    int num_channels,
    int batch_size,
    const float *out_delta,
    const float *mean,
    const float *var,
    const float *var_grad,
    float epsilon,
    float *mean_grad)
{
  __shared__ float d_mu_cache[1024+32];
  int idx = threadIdx.x + blockIdx.x * blockDim.x;
  int bank_idx = OFFSET_BANK(threadIdx.x);
  int block_spatial_dim = (spatial_dim+16*32-1)/(16*32);
  int warp_idx = idx % 32;
  int c = (idx / 32) % num_channels;
  int u0 = warp_idx + ((idx / (32 * num_channels)) % block_spatial_dim) * (16*32);
  int batch_idx = idx / (32 * num_channels * block_spatial_dim);
  if (c < num_channels && u0 < spatial_dim && batch_idx < batch_size) {
    float inv_var_norm = 1.0f / ((float)(spatial_dim - 1) * (float)(batch_size - 1));
    float mu = mean[c];
    float sigma = var[c];
    float inv_sqrt_sigma = rsqrtf(sigma + epsilon);
    float d_sigma = var_grad[c];
    float d_mu = 0.0f;
    int i0 = c * spatial_dim + batch_idx * spatial_dim * num_channels;
    int u_limit = min(spatial_dim, u0 + 16*32);
    for (int u = u0; u < u_limit; u += 32) {
      int i = i0 + u;
      d_mu += out_delta[i] * -inv_sqrt_sigma + d_sigma * -2.0f * inv_var_norm * (in_act[i] - mu);
    }
    d_mu_cache[bank_idx] = d_mu;
  } else {
    d_mu_cache[bank_idx] = 0.0f;
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 2 == 0) {
      d_mu_cache[bank_idx] += d_mu_cache[bank_idx+1];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 4 == 0) {
      d_mu_cache[bank_idx] += d_mu_cache[bank_idx+2];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 8 == 0) {
      d_mu_cache[bank_idx] += d_mu_cache[bank_idx+4];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 16 == 0) {
      d_mu_cache[bank_idx] += d_mu_cache[bank_idx+8];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 32 == 0 && u0 < spatial_dim) {
      float d_mu = d_mu_cache[bank_idx] + d_mu_cache[bank_idx+16];
      atomicAdd(&mean_grad[c], d_mu);
    }
  }
}

__global__ void conv_bnorm_bwd_data_batch_kernel(
    const float *in_act,
    int spatial_dim,
    int num_channels,
    int batch_size,
    const float *out_delta,
    const float *mean,
    const float *mean_grad,
    const float *var,
    const float *var_grad,
    float epsilon,
    float *in_delta)
{
  int idx = threadIdx.x + blockIdx.x * blockDim.x;
  int bank_idx = OFFSET_BANK(threadIdx.x);
  int block_spatial_dim = (spatial_dim+16*32-1)/(16*32);
  int warp_idx = idx % 32;
  int c = (idx / 32) % num_channels;
  int u0 = warp_idx + ((idx / (32 * num_channels)) % block_spatial_dim) * (16*32);
  int batch_idx = idx / (32 * num_channels * block_spatial_dim);
  if (c < num_channels && u0 < spatial_dim && batch_idx < batch_size) {
    float inv_mean_norm = 1.0f / ((float)(spatial_dim) * (float)(batch_size));
    float inv_var_norm = 1.0f / ((float)(spatial_dim - 1) * (float)(batch_size - 1));
    float mu = mean[c];
    float d_mu = mean_grad[c];
    float sigma = var[c];
    float d_sigma = var_grad[c];
    int i0 = c * spatial_dim + batch_idx * spatial_dim * num_channels;
    int u_limit = min(spatial_dim, u0 + 16*32);
    for (int u = u0; u < u_limit; u += 32) {
      int i = i0 + u;
      in_delta[i] = out_delta[i] * rsqrtf(sigma + epsilon) + d_mu * inv_mean_norm + d_sigma * 2.0f * inv_var_norm * (in_act[i] - mu);
    }
  }
}

extern "C" void neuralops_cuda_conv2d_batchnorm_bwd(
    const float *in_act,
    size_t spatial_dim,
    size_t num_channels,
    size_t batch_size,
    const float *out_delta,
    const float *mean,
    const float *var,
    float epsilon,
    float *mean_grad,
    float *var_grad,
    float *in_delta,
    cudaStream_t stream)
{
  int block_spatial_dim = (spatial_dim+16*32-1)/(16*32);
  int n = 32 * num_channels * block_spatial_dim * batch_size;
  conv_bnorm_bwd_var_batch_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      in_act, spatial_dim, num_channels, batch_size, out_delta, mean, var, epsilon, var_grad);
  conv_bnorm_bwd_mean_batch_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      in_act, spatial_dim, num_channels, batch_size, out_delta, mean, var, var_grad, epsilon, mean_grad);
  conv_bnorm_bwd_data_batch_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      in_act, spatial_dim, num_channels, batch_size, out_delta, mean, mean_grad, var, var_grad, epsilon, in_delta);
}

	.file	"tmpxft_00241b13_00000000-6_conv_batchnorm.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2014:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2014:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z76__device_stub__Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPfPKfiiiS0_S0_fPf
	.type	_Z76__device_stub__Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPfPKfiiiS0_S0_fPf, @function
_Z76__device_stub__Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPfPKfiiiS0_S0_fPf:
.LFB2036:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 32(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 28(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%rax, (%rsp)
	movss	%xmm0, 24(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	%rsp, %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	_Z76__device_stub__Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPfPKfiiiS0_S0_fPf, .-_Z76__device_stub__Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPfPKfiiiS0_S0_fPf
	.globl	_Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf
	.type	_Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf, @function
_Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf:
.LFB2037:
	.cfi_startproc
	endbr64
	jmp	_Z76__device_stub__Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPfPKfiiiS0_S0_fPf
	.cfi_endproc
.LFE2037:
	.size	_Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf, .-_Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf
	.globl	neuralops_cuda_conv2d_whiten_fwd
	.type	neuralops_cuda_conv2d_whiten_fwd, @function
neuralops_cuda_conv2d_whiten_fwd:
.LFB2008:
	.cfi_startproc
	endbr64
	movl	%edx, %eax
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rcx, %r15
	imull	%ecx, %eax
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	$1024, %ecx
	movq	%r9, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r8, %r13
	xorl	%r8d, %r8d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	imull	%esi, %eax
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdx, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rsi, %rbx
	addl	$1023, %eax
	cltd
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	idivl	%ecx
	movq	120(%rsp), %r9
	movq	112(%rsp), %r12
	movq	%rdi, (%rsp)
	movss	%xmm0, 12(%rsp)
	movl	$4194305, %edx
	movl	$1, %ecx
	salq	$10, %rdx
	movl	%eax, 24(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 28(%rsp)
	movq	24(%rsp), %rdi
	movl	32(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	movss	12(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L8
	movq	%r12, 112(%rsp)
	movq	(%rsp), %rdi
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movq	%r14, %r9
	movq	%r13, %r8
	movl	%r15d, %ecx
	movl	%ebp, %edx
	movl	%ebx, %esi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z76__device_stub__Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPfPKfiiiS0_S0_fPf
.L8:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2008:
	.size	neuralops_cuda_conv2d_whiten_fwd, .-neuralops_cuda_conv2d_whiten_fwd
	.globl	_Z63__device_stub__Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPfPKfiiiPf
	.type	_Z63__device_stub__Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPfPKfiiiPf, @function
_Z63__device_stub__Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPfPKfiiiPf:
.LFB2038:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L11:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2038:
	.size	_Z63__device_stub__Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPfPKfiiiPf, .-_Z63__device_stub__Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPfPKfiiiPf
	.globl	_Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf
	.type	_Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf, @function
_Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf:
.LFB2039:
	.cfi_startproc
	endbr64
	jmp	_Z63__device_stub__Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPfPKfiiiPf
	.cfi_endproc
.LFE2039:
	.size	_Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf, .-_Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf
	.globl	neuralops_cuda_conv2d_mean_fwd
	.type	neuralops_cuda_conv2d_mean_fwd, @function
neuralops_cuda_conv2d_mean_fwd:
.LFB2009:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movq	%rcx, %r14
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rdx, %r13
	leaq	511(%rsi), %rdx
	movl	%r13d, %eax
	shrq	$9, %rdx
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%r8, %r12
	imull	%ecx, %eax
	movl	$1024, %ecx
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movq	%rsi, %rbx
	xorl	%r8d, %r8d
	imull	%edx, %eax
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	sall	$5, %eax
	addl	$1023, %eax
	cltd
	idivl	%ecx
	movl	$4194305, %edx
	movl	$1, %ecx
	salq	$10, %rdx
	movl	%eax, 8(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 48
	movq	%r12, %r8
	movl	%r14d, %ecx
	movl	%r13d, %edx
	movl	%ebx, %esi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_Z63__device_stub__Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPfPKfiiiPf
.L16:
	.cfi_restore_state
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2009:
	.size	neuralops_cuda_conv2d_mean_fwd, .-neuralops_cuda_conv2d_mean_fwd
	.globl	_Z65__device_stub__Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_PfPKfiiiS0_Pf
	.type	_Z65__device_stub__Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_PfPKfiiiS0_Pf, @function
_Z65__device_stub__Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_PfPKfiiiS0_Pf:
.LFB2040:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 32(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 28(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L19:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	_Z65__device_stub__Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_PfPKfiiiS0_Pf, .-_Z65__device_stub__Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_PfPKfiiiS0_Pf
	.globl	_Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf
	.type	_Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf, @function
_Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf:
.LFB2041:
	.cfi_startproc
	endbr64
	jmp	_Z65__device_stub__Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_PfPKfiiiS0_Pf
	.cfi_endproc
.LFE2041:
	.size	_Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf, .-_Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf
	.globl	neuralops_cuda_conv2d_var_fwd
	.type	neuralops_cuda_conv2d_var_fwd, @function
neuralops_cuda_conv2d_var_fwd:
.LFB2010:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rcx, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rdx, %r14
	leaq	511(%rsi), %rdx
	movl	%r14d, %eax
	shrq	$9, %rdx
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r9, %r13
	imull	%ecx, %eax
	movl	$1024, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%r8, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdi, %rbp
	xorl	%r8d, %r8d
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rsi, %rbx
	imull	%edx, %eax
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	sall	$5, %eax
	movq	96(%rsp), %r9
	addl	$1023, %eax
	cltd
	idivl	%ecx
	movl	$4194305, %edx
	movl	$1, %ecx
	salq	$10, %rdx
	movl	%eax, 8(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movq	%r13, %r9
	movq	%r12, %r8
	movl	%r15d, %ecx
	movl	%r14d, %edx
	movl	%ebx, %esi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z65__device_stub__Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_PfPKfiiiS0_Pf
.L24:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2010:
	.size	neuralops_cuda_conv2d_var_fwd, .-neuralops_cuda_conv2d_var_fwd
	.globl	_Z67__device_stub__Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPfPKfiiiS0_S0_S0_fPf
	.type	_Z67__device_stub__Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPfPKfiiiS0_S0_S0_fPf, @function
_Z67__device_stub__Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPfPKfiiiS0_S0_S0_fPf:
.LFB2042:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	224(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movl	%esi, 52(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	232(%rsp), %rax
	movl	%edx, 48(%rsp)
	leaq	64(%rsp), %rdx
	movl	%ecx, 44(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 32(%rsp)
	movq	%r9, 24(%rsp)
	movq	%rax, 8(%rsp)
	movss	%xmm0, 40(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	pushq	72(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 240
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L27:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2042:
	.size	_Z67__device_stub__Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPfPKfiiiS0_S0_S0_fPf, .-_Z67__device_stub__Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPfPKfiiiS0_S0_S0_fPf
	.globl	_Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf
	.type	_Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf, @function
_Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf:
.LFB2043:
	.cfi_startproc
	endbr64
	jmp	_Z67__device_stub__Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPfPKfiiiS0_S0_S0_fPf
	.cfi_endproc
.LFE2043:
	.size	_Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf, .-_Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf
	.globl	_Z71__device_stub__Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPfPKfiiiS0_S0_S0_S0_fPf
	.type	_Z71__device_stub__Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPfPKfiiiS0_S0_S0_S0_fPf, @function
_Z71__device_stub__Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPfPKfiiiS0_S0_S0_S0_fPf:
.LFB2044:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	240(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movl	%esi, 52(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	248(%rsp), %rax
	movl	%edx, 48(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rax, 8(%rsp)
	movq	256(%rsp), %rax
	movl	%ecx, 44(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 32(%rsp)
	movq	%r9, 24(%rsp)
	movq	%rax, (%rsp)
	movss	%xmm0, 40(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 200(%rsp)
	movq	%rsp, %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	pushq	80(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 256
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L32:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L34
	call	__stack_chk_fail@PLT
.L34:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2044:
	.size	_Z71__device_stub__Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPfPKfiiiS0_S0_S0_S0_fPf, .-_Z71__device_stub__Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPfPKfiiiS0_S0_S0_S0_fPf
	.globl	_Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf
	.type	_Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf, @function
_Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf:
.LFB2045:
	.cfi_startproc
	endbr64
	jmp	_Z71__device_stub__Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPfPKfiiiS0_S0_S0_S0_fPf
	.cfi_endproc
.LFE2045:
	.size	_Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf, .-_Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf
	.globl	_Z74__device_stub__Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPfPKfiiiS0_S0_S0_S0_S0_fPf
	.type	_Z74__device_stub__Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPfPKfiiiS0_S0_S0_S0_S0_fPf, @function
_Z74__device_stub__Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPfPKfiiiS0_S0_S0_S0_S0_fPf:
.LFB2046:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	256(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	96(%rsp), %rdi
	movl	%esi, 68(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rax, 32(%rsp)
	movq	264(%rsp), %rax
	movl	%edx, 64(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rax, 24(%rsp)
	movq	272(%rsp), %rax
	movl	%ecx, 60(%rsp)
	leaq	88(%rsp), %rcx
	movq	%rax, 16(%rsp)
	movq	280(%rsp), %rax
	movq	%r8, 48(%rsp)
	movq	%r9, 40(%rsp)
	movq	%rax, 8(%rsp)
	movss	%xmm0, 56(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 104(%rsp)
	movq	%rax, 144(%rsp)
	leaq	68(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	60(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L37
	pushq	88(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 272
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L37:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L39
	call	__stack_chk_fail@PLT
.L39:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2046:
	.size	_Z74__device_stub__Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPfPKfiiiS0_S0_S0_S0_S0_fPf, .-_Z74__device_stub__Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPfPKfiiiS0_S0_S0_S0_S0_fPf
	.globl	_Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf
	.type	_Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf, @function
_Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf:
.LFB2047:
	.cfi_startproc
	endbr64
	jmp	_Z74__device_stub__Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPfPKfiiiS0_S0_S0_S0_S0_fPf
	.cfi_endproc
.LFE2047:
	.size	_Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf, .-_Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf
	.globl	neuralops_cuda_conv2d_batchnorm_bwd
	.type	neuralops_cuda_conv2d_batchnorm_bwd, @function
neuralops_cuda_conv2d_batchnorm_bwd:
.LFB2011:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdx, %r12
	leaq	511(%rsi), %rdx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	shrq	$9, %rdx
	movq	%rsi, %rbp
	movl	$1024, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rcx, %rbx
	movl	$4194305, %ecx
	salq	$10, %rcx
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	168(%rsp), %rax
	movq	%rdi, (%rsp)
	movq	%r8, 8(%rsp)
	movq	144(%rsp), %r13
	xorl	%r8d, %r8d
	movq	%rax, 40(%rsp)
	movq	176(%rsp), %rax
	movq	%r9, 16(%rsp)
	movq	152(%rsp), %r15
	movq	%rax, 24(%rsp)
	movl	%r12d, %eax
	movq	160(%rsp), %r14
	imull	%ebx, %eax
	movq	%rcx, 68(%rsp)
	movq	24(%rsp), %r9
	movl	$1, 76(%rsp)
	movss	%xmm0, 32(%rsp)
	imull	%edx, %eax
	sall	$5, %eax
	addl	$1023, %eax
	cltd
	idivl	%esi
	movq	%rcx, %rdx
	movl	$1, %ecx
	movl	%eax, 56(%rsp)
	movl	%eax, 36(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 60(%rsp)
	movq	56(%rsp), %rdi
	movl	64(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L43
	pushq	%r14
	.cfi_def_cfa_offset 152
	movl	%ebx, %ecx
	movl	%r12d, %edx
	movl	%ebp, %esi
	pushq	%r13
	.cfi_def_cfa_offset 160
	movss	48(%rsp), %xmm0
	movq	32(%rsp), %r9
	movq	24(%rsp), %r8
	movq	16(%rsp), %rdi
	call	_Z67__device_stub__Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPfPKfiiiS0_S0_S0_fPf
	popq	%rdx
	.cfi_def_cfa_offset 152
	popq	%rcx
	.cfi_def_cfa_offset 144
.L43:
	movl	36(%rsp), %eax
	movl	$4194305, %edx
	movq	24(%rsp), %r9
	xorl	%r8d, %r8d
	salq	$10, %rdx
	movl	$1, %ecx
	movl	$1, 76(%rsp)
	movl	%eax, 56(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 60(%rsp)
	movq	56(%rsp), %rdi
	movl	64(%rsp), %esi
	movq	%rdx, 68(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L44
	pushq	%rax
	.cfi_def_cfa_offset 152
	movl	%ebx, %ecx
	movl	%r12d, %edx
	movl	%ebp, %esi
	pushq	%r15
	.cfi_def_cfa_offset 160
	pushq	%r14
	.cfi_def_cfa_offset 168
	pushq	%r13
	.cfi_def_cfa_offset 176
	movss	64(%rsp), %xmm0
	movq	48(%rsp), %r9
	movq	40(%rsp), %r8
	movq	32(%rsp), %rdi
	call	_Z71__device_stub__Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPfPKfiiiS0_S0_S0_S0_fPf
	addq	$32, %rsp
	.cfi_def_cfa_offset 144
.L44:
	movl	36(%rsp), %eax
	movl	$4194305, %edx
	movq	24(%rsp), %r9
	xorl	%r8d, %r8d
	salq	$10, %rdx
	movl	$1, %ecx
	movl	$1, 76(%rsp)
	movl	%eax, 56(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 60(%rsp)
	movq	56(%rsp), %rdi
	movl	64(%rsp), %esi
	movq	%rdx, 68(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L42
	movq	40(%rsp), %rax
	movss	32(%rsp), %xmm0
	movl	%ebx, %ecx
	movl	%r12d, %edx
	movq	%r14, 160(%rsp)
	movq	16(%rsp), %r9
	movl	%ebp, %esi
	movq	%r13, 152(%rsp)
	movq	8(%rsp), %r8
	movq	%r15, 144(%rsp)
	movq	(%rsp), %rdi
	movq	%rax, 168(%rsp)
	addq	$88, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z74__device_stub__Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPfPKfiiiS0_S0_S0_S0_S0_fPf
.L42:
	.cfi_restore_state
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2011:
	.size	neuralops_cuda_conv2d_batchnorm_bwd, .-neuralops_cuda_conv2d_batchnorm_bwd
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf"
.LC1:
	.string	"_Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf"
.LC2:
	.string	"_Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf"
.LC3:
	.string	"_Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf"
.LC4:
	.string	"_Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf"
.LC5:
	.string	"_Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2049:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2049:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>

#define OFFSET_BANK(idx) ({ __typeof__ (idx) _idx = idx; ((_idx) + ((_idx) / 32)); })

__global__ void conv_diag_affine_white_var_fwd_batch_kernel(
    const float *in_act,
    int spatial_dim,
    int num_channels,
    int batch_size,
    const float *mean,
    const float *var,
    float epsilon,
    float *out_act)
{
  int idx = threadIdx.x + blockIdx.x * blockDim.x;
  int u = idx % spatial_dim;
  int c = (idx / spatial_dim) % num_channels;
  int batch_idx = idx / (spatial_dim * num_channels);
  if (u < spatial_dim && c < num_channels && batch_idx < batch_size) {
    float m = mean[c];
    float v = var[c];
    float y = (in_act[idx] - m) * rsqrtf(v + epsilon);
    out_act[idx] = y;
  }
}

extern "C" void neuralops_cuda_conv2d_whiten_fwd(
    const float *in_act,
    size_t spatial_dim,
    size_t num_channels,
    size_t batch_size,
    const float *mean,
    const float *var,
    float epsilon,
    float *out_act,
    hipStream_t stream)
{
  int n = spatial_dim * num_channels * batch_size;
  conv_diag_affine_white_var_fwd_batch_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      in_act, spatial_dim, num_channels, batch_size, mean, var, epsilon, out_act);
}

__global__ void estimate_conv_mean_fast2_batch_kernel(
    const float *src,
    int spatial_dim,
    int num_channels,
    int batch_size,
    float *mean)
{
  __shared__ float mean_cache[1024+32];
  int idx = threadIdx.x + blockIdx.x * blockDim.x;
  int bank_idx = OFFSET_BANK(threadIdx.x);
  int block_spatial_dim = (spatial_dim+16*32-1)/(16*32);
  int warp_idx = idx % 32;
  int c = (idx / 32) % num_channels;
  //int u0 = warp_idx + ((idx / (32 * num_channels)) % block_spatial_dim) * (16*32);
  int u0 = ((idx / (32 * num_channels)) % block_spatial_dim) * (16*32);
  int batch_idx = idx / (32 * num_channels * block_spatial_dim);
  if (c < num_channels && u0 < spatial_dim && batch_idx < batch_size) {
    float y = 0.0f;
    /*int i0 = c * spatial_dim + batch_idx * spatial_dim * num_channels;
    int u_limit = min(spatial_dim, u0 + 16*32);
    for (int u = u0; u < u_limit; u += 32) {
      int i = i0 + u;
      y += src[i];
    }*/
    int i0 = warp_idx + u0 + c * spatial_dim + batch_idx * spatial_dim * num_channels;
    int i_limit = i0 + min(spatial_dim - warp_idx - u0, 16*32);
    for (int v = 0; v < 16*32; v += 32) {
      int i = i0 + v;
      if (i < i_limit) {
        y += src[i];
      }
    }
    mean_cache[bank_idx] = y;
  } else {
    mean_cache[bank_idx] = 0.0f;
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 2 == 0) {
      mean_cache[bank_idx] += mean_cache[bank_idx+1];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 4 == 0) {
      mean_cache[bank_idx] += mean_cache[bank_idx+2];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 8 == 0) {
      mean_cache[bank_idx] += mean_cache[bank_idx+4];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 16 == 0) {
      mean_cache[bank_idx] += mean_cache[bank_idx+8];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 32 == 0 && u0 < spatial_dim) {
      float y = (mean_cache[bank_idx] + mean_cache[bank_idx+16]) / ((float)(spatial_dim) * (float)(batch_size));
      atomicAdd(&mean[c], y);
    }
  }
}

extern "C" void neuralops_cuda_conv2d_mean_fwd(
    const float *src,
    size_t spatial_dim,
    size_t num_channels,
    size_t batch_size,
    float *mean,
    hipStream_t stream)
{
  //int n = ((spatial_dim+32-1)/32) * channels * batch_size;
  int block_spatial_dim = (spatial_dim+16*32-1)/(16*32);
  int n = 32 * num_channels * block_spatial_dim * batch_size;
  estimate_conv_mean_fast2_batch_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      src, spatial_dim, num_channels, batch_size, mean);
}

__global__ void estimate_conv_var_fast2_batch_kernel(
    const float *src,
    int spatial_dim,
    int num_channels,
    int batch_size,
    const float *mean,
    float *var)
{
  __shared__ float var_cache[1024+32];
  int idx = threadIdx.x + blockIdx.x * blockDim.x;
  int bank_idx = OFFSET_BANK(threadIdx.x);
  int block_spatial_dim = (spatial_dim+16*32-1)/(16*32);
  int warp_idx = idx % 32;
  int c = (idx / 32) % num_channels;
  //int u0 = warp_idx + ((idx / (32 * num_channels)) % block_spatial_dim) * (16*32);
  int u0 = ((idx / (32 * num_channels)) % block_spatial_dim) * (16*32);
  int batch_idx = idx / (32 * num_channels * block_spatial_dim);
  if (c < num_channels && u0 < spatial_dim && batch_idx < batch_size) {
    float mean_c = mean[c];
    float y = 0.0f;
    /*int i0 = c * spatial_dim + batch_idx * spatial_dim * num_channels;
    int u_limit = min(spatial_dim, u0 + 16*32);
    for (int u = u0; u < u_limit; u += 32) {
      int i = i0 + u;
      float delta = src[i] - mean_c;
      y += delta * delta;
    }*/
    int i0 = warp_idx + u0 + c * spatial_dim + batch_idx * spatial_dim * num_channels;
    int i_limit = i0 + min(spatial_dim - warp_idx - u0, 16*32);
    for (int v = 0; v < 16*32; v += 32) {
      int i = i0 + v;
      if (i < i_limit) {
        float delta = src[i] - mean_c;
        y += delta * delta;
      }
    }
    var_cache[bank_idx] = y;
  } else {
    var_cache[bank_idx] = 0.0f;
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 2 == 0) {
      var_cache[bank_idx] += var_cache[bank_idx+1];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 4 == 0) {
      var_cache[bank_idx] += var_cache[bank_idx+2];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 8 == 0) {
      var_cache[bank_idx] += var_cache[bank_idx+4];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 16 == 0) {
      var_cache[bank_idx] += var_cache[bank_idx+8];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 32 == 0 && u0 < spatial_dim) {
      float y = (var_cache[bank_idx] + var_cache[bank_idx+16]) / ((float)(spatial_dim-1) * (float)(batch_size-1));
      atomicAdd(&var[c], y);
    }
  }
}

extern "C" void neuralops_cuda_conv2d_var_fwd(
    const float *src,
    size_t spatial_dim,
    size_t num_channels,
    size_t batch_size,
    const float *mean,
    float *var,
    hipStream_t stream)
{
  //int n = ((spatial_dim+32-1)/32) * channels * batch_size;
  int block_spatial_dim = (spatial_dim+16*32-1)/(16*32);
  int n = 32 * num_channels * block_spatial_dim * batch_size;
  estimate_conv_var_fast2_batch_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      src, spatial_dim, num_channels, batch_size, mean, var);
}

__global__ void conv_bnorm_bwd_var_batch_kernel(
    const float *in_act,
    int spatial_dim,
    int num_channels,
    int batch_size,
    const float *out_delta,
    const float *mean,
    const float *var,
    float epsilon,
    float *var_grad)
{
  __shared__ float d_sigma_cache[1024+32];
  int idx = threadIdx.x + blockIdx.x * blockDim.x;
  int bank_idx = OFFSET_BANK(threadIdx.x);
  int block_spatial_dim = (spatial_dim+16*32-1)/(16*32);
  int warp_idx = idx % 32;
  int c = (idx / 32) % num_channels;
  int u0 = warp_idx + ((idx / (32 * num_channels)) % block_spatial_dim) * (16*32);
  int batch_idx = idx / (32 * num_channels * block_spatial_dim);
  if (c < num_channels && u0 < spatial_dim && batch_idx < batch_size) {
    float mu = mean[c];
    float sigma = var[c];
    float inv_sqrt_sigma = rsqrtf(sigma + epsilon);
    float d_sigma = 0.0f;
    int i0 = c * spatial_dim + batch_idx * spatial_dim * num_channels;
    int u_limit = min(spatial_dim, u0 + 16*32);
    for (int u = u0; u < u_limit; u += 32) {
      int i = i0 + u;
      d_sigma += out_delta[i] * -0.5f * inv_sqrt_sigma / (sigma + epsilon) * (in_act[i] - mu);
    }
    d_sigma_cache[bank_idx] = d_sigma;
  } else {
    d_sigma_cache[bank_idx] = 0.0f;
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 2 == 0) {
      d_sigma_cache[bank_idx] += d_sigma_cache[bank_idx+1];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 4 == 0) {
      d_sigma_cache[bank_idx] += d_sigma_cache[bank_idx+2];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 8 == 0) {
      d_sigma_cache[bank_idx] += d_sigma_cache[bank_idx+4];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 16 == 0) {
      d_sigma_cache[bank_idx] += d_sigma_cache[bank_idx+8];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 32 == 0 && u0 < spatial_dim) {
      float d_sigma = d_sigma_cache[bank_idx] + d_sigma_cache[bank_idx+16];
      atomicAdd(&var_grad[c], d_sigma);
    }
  }
}

__global__ void conv_bnorm_bwd_mean_batch_kernel(
    const float *in_act,
    int spatial_dim,
    int num_channels,
    int batch_size,
    const float *out_delta,
    const float *mean,
    const float *var,
    const float *var_grad,
    float epsilon,
    float *mean_grad)
{
  __shared__ float d_mu_cache[1024+32];
  int idx = threadIdx.x + blockIdx.x * blockDim.x;
  int bank_idx = OFFSET_BANK(threadIdx.x);
  int block_spatial_dim = (spatial_dim+16*32-1)/(16*32);
  int warp_idx = idx % 32;
  int c = (idx / 32) % num_channels;
  int u0 = warp_idx + ((idx / (32 * num_channels)) % block_spatial_dim) * (16*32);
  int batch_idx = idx / (32 * num_channels * block_spatial_dim);
  if (c < num_channels && u0 < spatial_dim && batch_idx < batch_size) {
    float inv_var_norm = 1.0f / ((float)(spatial_dim - 1) * (float)(batch_size - 1));
    float mu = mean[c];
    float sigma = var[c];
    float inv_sqrt_sigma = rsqrtf(sigma + epsilon);
    float d_sigma = var_grad[c];
    float d_mu = 0.0f;
    int i0 = c * spatial_dim + batch_idx * spatial_dim * num_channels;
    int u_limit = min(spatial_dim, u0 + 16*32);
    for (int u = u0; u < u_limit; u += 32) {
      int i = i0 + u;
      d_mu += out_delta[i] * -inv_sqrt_sigma + d_sigma * -2.0f * inv_var_norm * (in_act[i] - mu);
    }
    d_mu_cache[bank_idx] = d_mu;
  } else {
    d_mu_cache[bank_idx] = 0.0f;
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 2 == 0) {
      d_mu_cache[bank_idx] += d_mu_cache[bank_idx+1];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 4 == 0) {
      d_mu_cache[bank_idx] += d_mu_cache[bank_idx+2];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 8 == 0) {
      d_mu_cache[bank_idx] += d_mu_cache[bank_idx+4];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 16 == 0) {
      d_mu_cache[bank_idx] += d_mu_cache[bank_idx+8];
    }
  }
  __syncthreads();
  if (c < num_channels && batch_idx < batch_size) {
    if (threadIdx.x % 32 == 0 && u0 < spatial_dim) {
      float d_mu = d_mu_cache[bank_idx] + d_mu_cache[bank_idx+16];
      atomicAdd(&mean_grad[c], d_mu);
    }
  }
}

__global__ void conv_bnorm_bwd_data_batch_kernel(
    const float *in_act,
    int spatial_dim,
    int num_channels,
    int batch_size,
    const float *out_delta,
    const float *mean,
    const float *mean_grad,
    const float *var,
    const float *var_grad,
    float epsilon,
    float *in_delta)
{
  int idx = threadIdx.x + blockIdx.x * blockDim.x;
  int bank_idx = OFFSET_BANK(threadIdx.x);
  int block_spatial_dim = (spatial_dim+16*32-1)/(16*32);
  int warp_idx = idx % 32;
  int c = (idx / 32) % num_channels;
  int u0 = warp_idx + ((idx / (32 * num_channels)) % block_spatial_dim) * (16*32);
  int batch_idx = idx / (32 * num_channels * block_spatial_dim);
  if (c < num_channels && u0 < spatial_dim && batch_idx < batch_size) {
    float inv_mean_norm = 1.0f / ((float)(spatial_dim) * (float)(batch_size));
    float inv_var_norm = 1.0f / ((float)(spatial_dim - 1) * (float)(batch_size - 1));
    float mu = mean[c];
    float d_mu = mean_grad[c];
    float sigma = var[c];
    float d_sigma = var_grad[c];
    int i0 = c * spatial_dim + batch_idx * spatial_dim * num_channels;
    int u_limit = min(spatial_dim, u0 + 16*32);
    for (int u = u0; u < u_limit; u += 32) {
      int i = i0 + u;
      in_delta[i] = out_delta[i] * rsqrtf(sigma + epsilon) + d_mu * inv_mean_norm + d_sigma * 2.0f * inv_var_norm * (in_act[i] - mu);
    }
  }
}

extern "C" void neuralops_cuda_conv2d_batchnorm_bwd(
    const float *in_act,
    size_t spatial_dim,
    size_t num_channels,
    size_t batch_size,
    const float *out_delta,
    const float *mean,
    const float *var,
    float epsilon,
    float *mean_grad,
    float *var_grad,
    float *in_delta,
    hipStream_t stream)
{
  int block_spatial_dim = (spatial_dim+16*32-1)/(16*32);
  int n = 32 * num_channels * block_spatial_dim * batch_size;
  conv_bnorm_bwd_var_batch_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      in_act, spatial_dim, num_channels, batch_size, out_delta, mean, var, epsilon, var_grad);
  conv_bnorm_bwd_mean_batch_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      in_act, spatial_dim, num_channels, batch_size, out_delta, mean, var, var_grad, epsilon, mean_grad);
  conv_bnorm_bwd_data_batch_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      in_act, spatial_dim, num_channels, batch_size, out_delta, mean, mean_grad, var, var_grad, epsilon, in_delta);
}

	.text
	.file	"conv_batchnorm.hip"
	.globl	_Z58__device_stub__conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf # -- Begin function _Z58__device_stub__conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf
	.type	_Z58__device_stub__conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf,@function
_Z58__device_stub__conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf: # @_Z58__device_stub__conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	8(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z58__device_stub__conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf, .Lfunc_end0-_Z58__device_stub__conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf
	.cfi_endproc
                                        # -- End function
	.globl	neuralops_cuda_conv2d_whiten_fwd # -- Begin function neuralops_cuda_conv2d_whiten_fwd
	.type	neuralops_cuda_conv2d_whiten_fwd,@function
neuralops_cuda_conv2d_whiten_fwd:       # @neuralops_cuda_conv2d_whiten_fwd
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	movq	%r9, %rbx
	movq	%r8, %r14
	movq	%rcx, %r15
	movq	%rdx, %r12
	movq	%rsi, %r13
	movq	%rdi, %rbp
	movq	72(%rsp), %r9
	movl	%r12d, %eax
	imull	%r13d, %eax
	movl	%r15d, %edi
	imull	%eax, %edi
	leal	1023(%rdi), %eax
	addl	$2046, %edi                     # imm = 0x7FE
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$10, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB1_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_2:
	.cfi_def_cfa_offset 64
	movq	%rbp, %rdi
	movl	%r13d, %esi
	movl	%r12d, %edx
	movl	%r15d, %ecx
	movq	%r14, %r8
	movq	%rbx, %r9
	movss	4(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z58__device_stub__conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf # TAILCALL
.Lfunc_end1:
	.size	neuralops_cuda_conv2d_whiten_fwd, .Lfunc_end1-neuralops_cuda_conv2d_whiten_fwd
	.cfi_endproc
                                        # -- End function
	.globl	_Z52__device_stub__estimate_conv_mean_fast2_batch_kernelPKfiiiPf # -- Begin function _Z52__device_stub__estimate_conv_mean_fast2_batch_kernelPKfiiiPf
	.type	_Z52__device_stub__estimate_conv_mean_fast2_batch_kernelPKfiiiPf,@function
_Z52__device_stub__estimate_conv_mean_fast2_batch_kernelPKfiiiPf: # @_Z52__device_stub__estimate_conv_mean_fast2_batch_kernelPKfiiiPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z52__device_stub__estimate_conv_mean_fast2_batch_kernelPKfiiiPf, .Lfunc_end2-_Z52__device_stub__estimate_conv_mean_fast2_batch_kernelPKfiiiPf
	.cfi_endproc
                                        # -- End function
	.globl	neuralops_cuda_conv2d_mean_fwd  # -- Begin function neuralops_cuda_conv2d_mean_fwd
	.type	neuralops_cuda_conv2d_mean_fwd,@function
neuralops_cuda_conv2d_mean_fwd:         # @neuralops_cuda_conv2d_mean_fwd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%r8, %rbx
	movq	%rcx, %r14
	movq	%rdx, %r15
	movq	%rsi, %r12
	movq	%rsi, %rax
	shlq	$23, %rax
	movl	$4286578688, %edx               # imm = 0xFF800000
	addq	%rdx, %rax
	shrq	$32, %rax
	imull	%r15d, %ecx
	imull	%ecx, %eax
	shll	$5, %eax
	leal	1023(%rax), %ecx
	addl	$2046, %eax                     # imm = 0x7FE
	testl	%ecx, %ecx
	cmovnsl	%ecx, %eax
	movq	%rdi, %r13
	sarl	$10, %eax
	leaq	(%rax,%rdx), %rdi
	addq	$8388608, %rdi                  # imm = 0x800000
	addq	$8389632, %rdx                  # imm = 0x800400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB3_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB3_2:
	.cfi_def_cfa_offset 48
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%r15d, %edx
	movl	%r14d, %ecx
	movq	%rbx, %r8
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z52__device_stub__estimate_conv_mean_fast2_batch_kernelPKfiiiPf # TAILCALL
.Lfunc_end3:
	.size	neuralops_cuda_conv2d_mean_fwd, .Lfunc_end3-neuralops_cuda_conv2d_mean_fwd
	.cfi_endproc
                                        # -- End function
	.globl	_Z51__device_stub__estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf # -- Begin function _Z51__device_stub__estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf
	.type	_Z51__device_stub__estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf,@function
_Z51__device_stub__estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf: # @_Z51__device_stub__estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z51__device_stub__estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf, .Lfunc_end4-_Z51__device_stub__estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf
	.cfi_endproc
                                        # -- End function
	.globl	neuralops_cuda_conv2d_var_fwd   # -- Begin function neuralops_cuda_conv2d_var_fwd
	.type	neuralops_cuda_conv2d_var_fwd,@function
neuralops_cuda_conv2d_var_fwd:          # @neuralops_cuda_conv2d_var_fwd
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movq	%r8, %r14
	movq	%rcx, %r15
	movq	%rdx, %r12
	movq	%rsi, %r13
	movq	%rdi, %rbp
	movq	%rsi, %rax
	shlq	$23, %rax
	movl	$4286578688, %edx               # imm = 0xFF800000
	addq	%rdx, %rax
	shrq	$32, %rax
	imull	%r12d, %ecx
	imull	%ecx, %eax
	shll	$5, %eax
	leal	1023(%rax), %ecx
	addl	$2046, %eax                     # imm = 0x7FE
	testl	%ecx, %ecx
	cmovnsl	%ecx, %eax
	movq	64(%rsp), %r9
	sarl	$10, %eax
	leaq	(%rax,%rdx), %rdi
	addq	$8388608, %rdi                  # imm = 0x800000
	addq	$8389632, %rdx                  # imm = 0x800400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB5_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB5_2:
	.cfi_def_cfa_offset 64
	movq	%rbp, %rdi
	movl	%r13d, %esi
	movl	%r12d, %edx
	movl	%r15d, %ecx
	movq	%r14, %r8
	movq	%rbx, %r9
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z51__device_stub__estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf # TAILCALL
.Lfunc_end5:
	.size	neuralops_cuda_conv2d_var_fwd, .Lfunc_end5-neuralops_cuda_conv2d_var_fwd
	.cfi_endproc
                                        # -- End function
	.globl	_Z46__device_stub__conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf # -- Begin function _Z46__device_stub__conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf
	.type	_Z46__device_stub__conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf,@function
_Z46__device_stub__conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf: # @_Z46__device_stub__conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	8(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	movq	%r9, 56(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z46__device_stub__conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf, .Lfunc_end6-_Z46__device_stub__conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z47__device_stub__conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf # -- Begin function _Z47__device_stub__conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf
	.type	_Z47__device_stub__conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf,@function
_Z47__device_stub__conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf: # @_Z47__device_stub__conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	8(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	movq	%r9, 64(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z47__device_stub__conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf, .Lfunc_end7-_Z47__device_stub__conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z47__device_stub__conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf # -- Begin function _Z47__device_stub__conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf
	.type	_Z47__device_stub__conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf,@function
_Z47__device_stub__conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf: # @_Z47__device_stub__conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	8(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	movq	%r9, 72(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z47__device_stub__conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf, .Lfunc_end8-_Z47__device_stub__conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf
	.cfi_endproc
                                        # -- End function
	.globl	neuralops_cuda_conv2d_batchnorm_bwd # -- Begin function neuralops_cuda_conv2d_batchnorm_bwd
	.type	neuralops_cuda_conv2d_batchnorm_bwd,@function
neuralops_cuda_conv2d_batchnorm_bwd:    # @neuralops_cuda_conv2d_batchnorm_bwd
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	%r9, 32(%rsp)                   # 8-byte Spill
	movq	%r8, 24(%rsp)                   # 8-byte Spill
	movq	%rcx, %r15
	movq	%rdx, %r12
	movq	%rsi, %r13
	movq	%rdi, 16(%rsp)                  # 8-byte Spill
	movq	128(%rsp), %rbx
	movabsq	$4294968320, %r14               # imm = 0x100000400
	movq	%rsi, %rax
	shlq	$23, %rax
	addq	%r14, %rax
	addq	$-8389632, %rax                 # imm = 0xFF7FFC00
	shrq	$32, %rax
	imull	%r12d, %ecx
	imull	%ecx, %eax
	shll	$5, %eax
	leal	1023(%rax), %ecx
	addl	$2046, %eax                     # imm = 0x7FE
	testl	%ecx, %ecx
	cmovnsl	%ecx, %eax
	sarl	$10, %eax
	leaq	(%rax,%r14), %rbp
	addq	$-1024, %rbp                    # imm = 0xFC00
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	movq	%rbx, %r9
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB9_2
# %bb.1:
	movq	16(%rsp), %rdi                  # 8-byte Reload
	movl	%r13d, %esi
	movl	%r12d, %edx
	movl	%r15d, %ecx
	movq	24(%rsp), %r8                   # 8-byte Reload
	movq	32(%rsp), %r9                   # 8-byte Reload
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z46__device_stub__conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB9_2:
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	movq	%rbx, %r9
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB9_4
# %bb.3:
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movq	24(%rsp), %rdi                  # 8-byte Reload
	movl	%r13d, %esi
	movl	%r12d, %edx
	movl	%r15d, %ecx
	movq	32(%rsp), %r8                   # 8-byte Reload
	movq	40(%rsp), %r9                   # 8-byte Reload
	movss	20(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	128(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	120(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z47__device_stub__conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB9_4:
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	movq	%rbx, %r9
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB9_5
# %bb.6:
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	jmp	.LBB9_7
.LBB9_5:
	.cfi_def_cfa_offset 96
	movq	16(%rsp), %rdi                  # 8-byte Reload
	movl	%r13d, %esi
	movl	%r12d, %edx
	movl	%r15d, %ecx
	movq	24(%rsp), %r8                   # 8-byte Reload
	movq	32(%rsp), %r9                   # 8-byte Reload
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	pushq	120(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	120(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	128(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z47__device_stub__conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf
	addq	$72, %rsp
	.cfi_adjust_cfa_offset -72
.LBB9_7:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	neuralops_cuda_conv2d_batchnorm_bwd, .Lfunc_end9-neuralops_cuda_conv2d_batchnorm_bwd
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB10_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB10_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end10:
	.size	__hip_module_ctor, .Lfunc_end10-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB11_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB11_2:
	retq
.Lfunc_end11:
	.size	__hip_module_dtor, .Lfunc_end11-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf,@object # @_Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf
	.section	.rodata,"a",@progbits
	.globl	_Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf
	.p2align	3, 0x0
_Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf:
	.quad	_Z58__device_stub__conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf
	.size	_Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf, 8

	.type	_Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf,@object # @_Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf
	.globl	_Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf
	.p2align	3, 0x0
_Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf:
	.quad	_Z52__device_stub__estimate_conv_mean_fast2_batch_kernelPKfiiiPf
	.size	_Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf, 8

	.type	_Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf,@object # @_Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf
	.globl	_Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf
	.p2align	3, 0x0
_Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf:
	.quad	_Z51__device_stub__estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf
	.size	_Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf, 8

	.type	_Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf,@object # @_Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf
	.globl	_Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf
	.p2align	3, 0x0
_Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf:
	.quad	_Z46__device_stub__conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf
	.size	_Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf, 8

	.type	_Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf,@object # @_Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf
	.globl	_Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf
	.p2align	3, 0x0
_Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf:
	.quad	_Z47__device_stub__conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf
	.size	_Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf, 8

	.type	_Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf,@object # @_Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf
	.globl	_Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf
	.p2align	3, 0x0
_Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf:
	.quad	_Z47__device_stub__conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf
	.size	_Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf"
	.size	.L__unnamed_1, 63

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf"
	.size	.L__unnamed_2, 50

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf"
	.size	.L__unnamed_3, 52

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf"
	.size	.L__unnamed_4, 54

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf"
	.size	.L__unnamed_5, 58

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf"
	.size	.L__unnamed_6, 61

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z58__device_stub__conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf
	.addrsig_sym _Z52__device_stub__estimate_conv_mean_fast2_batch_kernelPKfiiiPf
	.addrsig_sym _Z51__device_stub__estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf
	.addrsig_sym _Z46__device_stub__conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf
	.addrsig_sym _Z47__device_stub__conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf
	.addrsig_sym _Z47__device_stub__conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf
	.addrsig_sym _Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf
	.addrsig_sym _Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf
	.addrsig_sym _Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf
	.addrsig_sym _Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf
	.addrsig_sym _Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf ; -- Begin function _Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf
	.globl	_Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf
	.p2align	8
	.type	_Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf,@function
_Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf: ; @_Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b32 s2, s[0:1], 0x44
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s5, s4
	s_and_b32 s2, s2, 0xffff
	s_ashr_i32 s7, s3, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s3, s7
	s_xor_b32 s3, s3, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, s3
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v1
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_sub_i32 s2, 0, s3
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v0, s2, v3
	s_or_b32 s2, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_gt_i32 s2, -1
	v_ashrrev_i32_e32 v2, 31, v1
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, v0
	v_add_nc_u32_e32 v0, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v0, v0, v2
	v_add_nc_u32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v0, v3
	v_mul_lo_u32 v4, v3, s3
	v_add_nc_u32_e32 v5, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v0, v4
	v_subrev_nc_u32_e32 v6, s3, v4
	v_cmp_le_u32_e32 vcc_lo, s3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v4, v4, v6
	v_xor_b32_e32 v6, s7, v2
	v_add_nc_u32_e32 v5, 1, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s3, v4
	v_cndmask_b32_e32 v3, v3, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v3, v6
	v_sub_nc_u32_e32 v3, v3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s6, v3
	s_and_b32 s2, s2, vcc_lo
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_ashr_i32 s2, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s4, s2
	s_xor_b32 s3, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v3, s3
	s_sub_i32 s4, 0, s3
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v3
	v_mul_lo_u32 v4, s4, v3
	s_ashr_i32 s4, s5, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s5, s5, s4
	s_xor_b32 s4, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v5, s4
	v_mul_hi_u32 v4, v3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v5, v5
	v_add_nc_u32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v0, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, 0x4f7ffffe, v5
	v_mul_lo_u32 v4, v3, s3
	v_sub_nc_u32_e32 v0, v0, v4
	v_add_nc_u32_e32 v4, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v6, s3, v0
	v_cmp_le_u32_e32 vcc_lo, s3, v0
	v_dual_cndmask_b32 v3, v3, v4 :: v_dual_cndmask_b32 v0, v0, v6
	v_xor_b32_e32 v6, s2, v2
	s_sub_i32 s2, 0, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v4, 1, v3
	v_cmp_le_u32_e32 vcc_lo, s3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v3, v4, vcc_lo
	v_cvt_u32_f32_e32 v3, v5
	v_xor_b32_e32 v0, v0, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, s2, v3
	s_load_b64 s[2:3], s[0:1], 0x0
	v_sub_nc_u32_e32 v0, v0, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, v4
	v_ashrrev_i32_e32 v5, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v0, v0, v5
	v_add_nc_u32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v5
	v_mul_hi_u32 v3, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v3, s4
	v_sub_nc_u32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v3, s4, v0
	v_cmp_le_u32_e32 vcc_lo, s4, v0
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v3, s4, v0
	v_cmp_le_u32_e32 vcc_lo, s4, v0
	s_load_b128 s[4:7], s[0:1], 0x18
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v5
	v_sub_nc_u32_e32 v3, v0, v5
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
	global_load_b32 v7, v[5:6], off
	v_add_co_u32 v5, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[5:6], off
	global_load_b32 v2, v[2:3], off
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x28
	s_load_b64 s[0:1], s[0:1], 0x30
	s_waitcnt vmcnt(2) lgkmcnt(0)
	v_add_f32_e32 v3, s2, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v5, 0x4b800000, v3
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v3
	s_waitcnt vmcnt(0)
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_sub_f32 v2, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rsq_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, 0x45800000, v3
	v_cndmask_b32_e32 v3, v3, v5, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf, .Lfunc_end0-_Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 812
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf ; -- Begin function _Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf
	.globl	_Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf
	.p2align	8
	.type	_Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf,@function
_Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf: ; @_Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b32 s2, s[0:1], 0x2c
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s3, s5, 5
	s_bfe_i32 s7, s5, 0x1001a
	s_and_b32 s2, s2, 0xffff
	s_add_i32 s8, s3, s7
	s_ashr_i32 s10, s5, 31
	s_xor_b32 s8, s8, s7
	s_add_i32 s11, s5, s10
	v_cvt_f32_u32_e32 v1, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
	s_sub_i32 s2, 0, s8
	v_mul_lo_u32 v3, s2, v1
	s_add_i32 s2, s4, 0x1ff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_ashr_i32 s9, s2, 31
	v_ashrrev_i32_e32 v5, 31, v2
	s_lshr_b32 s9, s9, 23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_add_i32 s2, s2, s9
	v_mul_hi_u32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v2, v5
	s_xor_b32 s9, s11, s10
	s_ashr_i32 s10, s2, 9
	s_ashr_i32 s2, s2, 31
	s_mul_i32 s3, s3, s10
	v_xor_b32_e32 v6, v4, v5
	s_add_i32 s11, s10, s2
	v_add_nc_u32_e32 v1, v1, v3
	s_xor_b32 s2, s11, s2
	s_ashr_i32 s10, s3, 31
	v_cvt_f32_u32_e32 v7, s2
	s_add_i32 s3, s3, s10
	v_mul_hi_u32 v1, v6, v1
	s_xor_b32 s3, s3, s10
	v_cvt_f32_u32_e32 v4, s9
	v_rcp_iflag_f32_e32 v7, v7
	v_xor_b32_e32 v10, s7, v5
	s_sub_i32 s7, 0, s2
	s_mov_b32 s11, 0
	v_rcp_iflag_f32_e32 v4, v4
	v_mul_lo_u32 v3, v1, s8
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v7, 0x4f7ffffe, v7 :: v_dual_add_nc_u32 v8, 1, v1
	v_sub_nc_u32_e32 v3, v6, v3
	v_mul_f32_e32 v4, 0x4f7ffffe, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_u32_f32_e32 v7, v7
	v_subrev_nc_u32_e32 v9, s8, v3
	v_cmp_le_u32_e32 vcc_lo, s8, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cvt_u32_f32_e32 v11, v4
	v_cndmask_b32_e32 v1, v1, v8, vcc_lo
	v_cndmask_b32_e32 v3, v3, v9, vcc_lo
	v_cvt_f32_u32_e32 v8, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v9, 1, v1
	v_cmp_le_u32_e32 vcc_lo, s8, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_iflag_f32_e32 v8, v8
	v_cndmask_b32_e32 v1, v1, v9, vcc_lo
	v_lshrrev_b32_e32 v9, 27, v5
	v_xor_b32_e32 v5, s10, v5
	s_delay_alu instid0(VALU_DEP_3)
	v_xor_b32_e32 v1, v1, v10
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v8
	v_mul_lo_u32 v8, s7, v7
	s_sub_i32 s7, 0, s3
	v_add_nc_u32_e32 v9, v2, v9
	v_sub_nc_u32_e32 v1, v1, v10
	v_cvt_u32_f32_e32 v10, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v4, 5, v9
	v_ashrrev_i32_e32 v3, 31, v1
	v_mul_hi_u32 v8, v7, v8
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v12, s7, v10
	s_sub_i32 s7, 0, s9
	v_ashrrev_i32_e32 v9, 31, v9
	v_add_nc_u32_e32 v1, v1, v3
	v_mul_lo_u32 v13, s7, v11
	s_cmp_gt_i32 s5, -1
	v_add_nc_u32_e32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v1, v1, v3
	v_mul_hi_u32 v8, v10, v12
	s_cselect_b32 s7, -1, 0
	v_mul_hi_u32 v12, v11, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v7, v1, v7
	v_add_nc_u32_e32 v13, v4, v9
	v_add_nc_u32_e32 v8, v10, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v10, v13, v9
	v_add_nc_u32_e32 v11, v11, v12
	v_mul_lo_u32 v7, v7, s2
	v_mul_hi_u32 v8, v6, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v11, v10, v11
	v_sub_nc_u32_e32 v1, v1, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v7, v8, s3
	v_mul_lo_u32 v11, v11, s9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v12, s2, v1
	v_cmp_le_u32_e32 vcc_lo, s2, v1
	v_sub_nc_u32_e32 v6, v6, v7
	v_add_nc_u32_e32 v7, 1, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v1, v1, v12, vcc_lo
	v_sub_nc_u32_e32 v10, v10, v11
	v_subrev_nc_u32_e32 v11, s3, v6
	v_cmp_le_u32_e32 vcc_lo, s3, v6
	s_delay_alu instid0(VALU_DEP_4)
	v_subrev_nc_u32_e32 v12, s2, v1
	v_cmp_le_u32_e64 s2, s2, v1
	v_cndmask_b32_e32 v7, v8, v7, vcc_lo
	v_subrev_nc_u32_e32 v8, s9, v10
	v_cndmask_b32_e32 v11, v6, v11, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s9, v10
	v_cndmask_b32_e64 v1, v1, v12, s2
	v_add_nc_u32_e32 v12, 1, v7
	v_cndmask_b32_e32 v8, v10, v8, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s3, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v6, v1, v3
	v_cndmask_b32_e32 v1, v7, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v7, s9, v8
	v_cmp_le_u32_e32 vcc_lo, s9, v8
	v_sub_nc_u32_e32 v10, v6, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v1, v1, v5
	v_cndmask_b32_e32 v11, v8, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v7, 9, v10
	v_sub_nc_u32_e32 v8, v1, v5
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v1, v11, v9
	v_cmp_gt_i32_e32 vcc_lo, s4, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e64 s2, s6, v8
	v_sub_nc_u32_e32 v1, v1, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s2
	s_and_b32 s3, s3, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s10, s3
	s_cbranch_execz .LBB1_6
; %bb.1:
	v_mad_u64_u32 v[9:10], null, v8, s5, v[1:2]
	v_lshlrev_b32_e32 v4, 5, v4
	v_lshlrev_b32_e32 v6, 9, v6
	s_load_b64 s[8:9], s[0:1], 0x0
	v_lshlrev_b32_e32 v3, 9, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v8, v2, v4
	v_mul_lo_u32 v5, v9, s4
	v_add3_u32 v2, v2, v5, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v8, v7
	v_sub_nc_u32_e32 v4, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v2, s4, v5
	v_mov_b32_e32 v5, 0
	v_sub_nc_u32_e32 v3, v4, v3
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cmpx_lt_i32_e64 s11, v2
	s_cbranch_execz .LBB1_4
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, s11, v3
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, s3, s8, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, s3, s9, v7, s3
	global_load_b32 v4, v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v4
.LBB1_4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s3, s11, 32
	s_cmpk_lt_u32 s11, 0x1e0
	s_cbranch_scc0 .LBB1_6
; %bb.5:                                ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b32 s11, s3
	s_branch .LBB1_2
.LBB1_6:                                ; %Flow122
	s_or_b32 exec_lo, exec_lo, s10
	v_and_b32_e32 v3, 1, v0
	v_lshrrev_b32_e32 v2, 5, v0
	s_and_b32 s5, s7, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s3, 0, v3
	v_add_lshl_u32 v4, v2, v0, 2
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s3, s3, s5
	ds_store_b32 v4, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB1_8
; %bb.7:
	ds_load_2addr_b32 v[2:3], v4 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v4, v2
.LBB1_8:
	s_or_b32 exec_lo, exec_lo, s2
	v_and_b32_e32 v2, 3, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_eq_u32_e64 s2, 0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s2, s5
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB1_10
; %bb.9:
	ds_load_2addr_b32 v[2:3], v4 offset1:2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v4, v2
.LBB1_10:
	s_or_b32 exec_lo, exec_lo, s2
	v_and_b32_e32 v2, 7, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_eq_u32_e64 s2, 0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s2, s5
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB1_12
; %bb.11:
	ds_load_2addr_b32 v[2:3], v4 offset1:4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v4, v2
.LBB1_12:
	s_or_b32 exec_lo, exec_lo, s2
	v_and_b32_e32 v2, 15, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_eq_u32_e64 s2, 0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s2, s5
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB1_14
; %bb.13:
	ds_load_2addr_b32 v[2:3], v4 offset1:8
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v4, v2
.LBB1_14:
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s2, s5
	s_cbranch_execz .LBB1_18
; %bb.15:
	v_and_b32_e32 v0, 31, v0
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s2, 0, v0
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB1_18
; %bb.16:
	s_load_b64 s[0:1], s[0:1], 0x18
	v_ashrrev_i32_e32 v2, 31, v1
	ds_load_2addr_b32 v[4:5], v4 offset1:16
	v_cvt_f32_i32_e32 v6, s6
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_cvt_f32_i32_e32 v2, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v2, v2, v6
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	v_add_f32_e32 v4, v4, v5
	global_load_b32 v3, v[0:1], off
	v_div_scale_f32 v5, null, v2, v2, v4
	v_rcp_f32_e32 v6, v5
	s_waitcnt_depctr 0xfff
	v_fma_f32 v7, -v5, v6, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v7, v6
	v_div_scale_f32 v7, vcc_lo, v4, v2, v4
	v_mul_f32_e32 v8, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, -v5, v8, v7
	v_fmac_f32_e32 v8, v9, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, -v5, v8, v7
	v_div_fmas_f32 v5, v5, v6, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v4, v5, v2, v4
.LBB1_17:                               ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v2, v3, v4
	global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v2, v3
	v_mov_b32_e32 v3, v2
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_17
.LBB1_18:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf
		.amdhsa_group_segment_fixed_size 4224
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf, .Lfunc_end1-_Z37estimate_conv_mean_fast2_batch_kernelPKfiiiPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1548
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4224 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf ; -- Begin function _Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf
	.globl	_Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf
	.p2align	8
	.type	_Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf,@function
_Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf: ; @_Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf
; %bb.0:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x8
	s_load_b32 s12, s[0:1], 0x34
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s2, s5, 5
	s_bfe_i32 s3, s5, 0x1001a
	s_and_b32 s12, s12, 0xffff
	s_add_i32 s7, s2, s3
	s_ashr_i32 s14, s5, 31
	s_xor_b32 s7, s7, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, s7
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_mad_u64_u32 v[3:4], null, s15, s12, v[0:1]
	s_sub_i32 s12, 0, s7
	s_add_i32 s15, s5, s14
	v_mul_lo_u32 v2, s12, v1
	s_add_i32 s12, s4, 0x1ff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_ashr_i32 s13, s12, 31
	v_ashrrev_i32_e32 v6, 31, v3
	s_lshr_b32 s13, s13, 23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_add_i32 s12, s12, s13
	v_mul_hi_u32 v2, v1, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v3, v6
	s_xor_b32 s13, s15, s14
	s_ashr_i32 s14, s12, 9
	s_ashr_i32 s12, s12, 31
	s_mul_i32 s2, s2, s14
	v_xor_b32_e32 v7, v4, v6
	s_add_i32 s15, s14, s12
	v_add_nc_u32_e32 v1, v1, v2
	s_xor_b32 s12, s15, s12
	v_cvt_f32_u32_e32 v4, s13
	v_cvt_f32_u32_e32 v5, s12
	s_ashr_i32 s14, s2, 31
	v_mul_hi_u32 v1, v7, v1
	s_add_i32 s2, s2, s14
	v_rcp_iflag_f32_e32 v4, v4
	v_rcp_iflag_f32_e32 v5, v5
	s_xor_b32 s15, s2, s14
	v_xor_b32_e32 v10, s3, v6
	s_sub_i32 s2, 0, s12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v1, s7
	v_add_nc_u32_e32 v8, 1, v1
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v4, 0x4f7ffffe, v4 :: v_dual_mul_f32 v5, 0x4f7ffffe, v5
	v_sub_nc_u32_e32 v2, v7, v2
	v_cvt_u32_f32_e32 v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v9, s7, v2
	v_cmp_le_u32_e32 vcc_lo, s7, v2
	v_dual_cndmask_b32 v1, v1, v8 :: v_dual_cndmask_b32 v2, v2, v9
	v_cvt_f32_u32_e32 v8, s15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v9, 1, v1
	v_cmp_le_u32_e32 vcc_lo, s7, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_rcp_iflag_f32_e32 v8, v8
	v_cvt_u32_f32_e32 v2, v5
	v_cndmask_b32_e32 v1, v1, v9, vcc_lo
	v_lshrrev_b32_e32 v9, 27, v6
	v_xor_b32_e32 v6, s14, v6
	s_delay_alu instid0(VALU_DEP_3)
	v_xor_b32_e32 v1, v1, v10
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, 0x4f7ffffe, v8
	v_mul_lo_u32 v8, s2, v2
	s_sub_i32 s2, 0, s15
	v_add_nc_u32_e32 v9, v3, v9
	v_sub_nc_u32_e32 v1, v1, v10
	v_cvt_u32_f32_e32 v10, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v5, 5, v9
	v_ashrrev_i32_e32 v4, 31, v1
	v_mul_hi_u32 v8, v2, v8
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v12, s2, v10
	s_sub_i32 s2, 0, s13
	v_ashrrev_i32_e32 v14, 31, v9
	v_add_nc_u32_e32 v1, v1, v4
	v_mul_lo_u32 v13, s2, v11
	s_cmp_gt_i32 s5, -1
	v_add_nc_u32_e32 v2, v2, v8
	s_delay_alu instid0(VALU_DEP_3)
	v_xor_b32_e32 v1, v1, v4
	v_mul_hi_u32 v8, v10, v12
	v_add_nc_u32_e32 v12, v5, v14
	s_cselect_b32 s7, -1, 0
	v_mul_hi_u32 v9, v11, v13
	v_mul_hi_u32 v2, v1, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v8, v10, v8
	v_xor_b32_e32 v10, v12, v14
	v_add_nc_u32_e32 v9, v11, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v2, v2, s12
	v_mul_hi_u32 v8, v7, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v9, v10, v9
	v_sub_nc_u32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v2, v8, s15
	v_mul_lo_u32 v9, v9, s13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v11, s12, v1
	v_cmp_le_u32_e32 vcc_lo, s12, v1
	v_sub_nc_u32_e32 v2, v7, v2
	v_add_nc_u32_e32 v7, 1, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v1, v1, v11, vcc_lo
	v_sub_nc_u32_e32 v9, v10, v9
	v_subrev_nc_u32_e32 v10, s15, v2
	v_cmp_le_u32_e32 vcc_lo, s15, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v11, s12, v1
	v_cmp_le_u32_e64 s2, s12, v1
	v_cndmask_b32_e32 v8, v8, v7, vcc_lo
	v_subrev_nc_u32_e32 v7, s13, v9
	v_cndmask_b32_e64 v1, v1, v11, s2
	v_cndmask_b32_e32 v2, v2, v10, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s13, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v9, v9, v7 :: v_dual_add_nc_u32 v10, 1, v8
	v_xor_b32_e32 v7, v1, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s15, v2
	v_subrev_nc_u32_e32 v2, s13, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v1, v8, v10, vcc_lo
	v_sub_nc_u32_e32 v8, v7, v4
	v_cmp_le_u32_e32 vcc_lo, s13, v9
	s_mov_b32 s13, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v8, 9, v8
	v_xor_b32_e32 v1, v1, v6
	v_cndmask_b32_e32 v2, v9, v2, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s4, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v9, v1, v6
	v_xor_b32_e32 v1, v2, v14
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e64 s2, s6, v9
	v_sub_nc_u32_e32 v1, v1, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s2
	s_and_b32 s3, s3, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s12, s3
	s_cbranch_execz .LBB2_6
; %bb.1:
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b32_e32 v7, 9, v7
	v_lshlrev_b32_e32 v5, 5, v5
	v_lshlrev_b32_e32 v4, 9, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[1:2]
	v_add_co_u32 v10, s3, s8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s3, s9, v11, s3
	s_load_b64 s[8:9], s[0:1], 0x0
	global_load_b32 v6, v[10:11], off
	v_mad_u64_u32 v[10:11], null, v9, s5, v[1:2]
	v_mul_lo_u32 v2, v10, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v2, v3, v2, v7
	v_sub_nc_u32_e32 v2, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v2, v4
	v_mov_b32_e32 v2, 0
	v_sub_nc_u32_e32 v9, v3, v5
	v_add_nc_u32_e32 v3, v9, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, s4, v3
.LBB2_2:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 s13, v3
	s_cbranch_execz .LBB2_4
; %bb.3:                                ;   in Loop: Header=BB2_2 Depth=1
	v_add_nc_u32_e32 v7, s13, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v7, s0, s8, v7
	v_add_co_ci_u32_e64 v8, s0, s9, v8, s0
	global_load_b32 v5, v[7:8], off
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v2, v5, v5
.LBB2_4:                                ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_add_i32 s0, s13, 32
	s_cmpk_lt_u32 s13, 0x1e0
	s_cbranch_scc0 .LBB2_6
; %bb.5:                                ;   in Loop: Header=BB2_2 Depth=1
	s_mov_b32 s13, s0
	s_branch .LBB2_2
.LBB2_6:                                ; %Flow132
	s_or_b32 exec_lo, exec_lo, s12
	v_and_b32_e32 v5, 1, v0
	v_lshrrev_b32_e32 v3, 5, v0
	s_and_b32 s1, s7, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s0, 0, v5
	v_add_lshl_u32 v4, v3, v0, 2
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, s0, s1
	ds_store_b32 v4, v2
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB2_8
; %bb.7:
	ds_load_2addr_b32 v[2:3], v4 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v4, v2
.LBB2_8:
	s_or_b32 exec_lo, exec_lo, s0
	v_and_b32_e32 v2, 3, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_eq_u32_e64 s0, 0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s0, s1
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB2_10
; %bb.9:
	ds_load_2addr_b32 v[2:3], v4 offset1:2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v4, v2
.LBB2_10:
	s_or_b32 exec_lo, exec_lo, s0
	v_and_b32_e32 v2, 7, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_eq_u32_e64 s0, 0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s0, s1
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB2_12
; %bb.11:
	ds_load_2addr_b32 v[2:3], v4 offset1:4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v4, v2
.LBB2_12:
	s_or_b32 exec_lo, exec_lo, s0
	v_and_b32_e32 v2, 15, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_eq_u32_e64 s0, 0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s0, s1
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB2_14
; %bb.13:
	ds_load_2addr_b32 v[2:3], v4 offset1:8
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v4, v2
.LBB2_14:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB2_18
; %bb.15:
	v_and_b32_e32 v0, 31, v0
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, 0, v0
	s_and_b32 s0, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB2_18
; %bb.16:
	v_ashrrev_i32_e32 v2, 31, v1
	ds_load_2addr_b32 v[4:5], v4 offset1:16
	s_add_i32 s0, s4, -1
	s_add_i32 s2, s6, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v6, s2
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_cvt_f32_i32_e32 v2, s0
	v_mul_f32_e32 v2, v2, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	global_load_b32 v3, v[0:1], off
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v5, null, v2, v2, v4
	v_rcp_f32_e32 v6, v5
	s_waitcnt_depctr 0xfff
	v_fma_f32 v7, -v5, v6, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v7, v6
	v_div_scale_f32 v7, vcc_lo, v4, v2, v4
	v_mul_f32_e32 v8, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, -v5, v8, v7
	v_fmac_f32_e32 v8, v9, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, -v5, v8, v7
	v_div_fmas_f32 v5, v5, v6, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v4, v5, v2, v4
.LBB2_17:                               ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v2, v3, v4
	global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v2, v3
	v_mov_b32_e32 v3, v2
	s_or_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB2_17
.LBB2_18:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf
		.amdhsa_group_segment_fixed_size 4224
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf, .Lfunc_end2-_Z36estimate_conv_var_fast2_batch_kernelPKfiiiS0_Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1596
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4224 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf ; -- Begin function _Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf
	.globl	_Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf
	.p2align	8
	.type	_Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf,@function
_Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf: ; @_Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b32 s2, s[0:1], 0x4c
	s_mov_b32 s14, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s3, s5, 5
	s_bfe_i32 s7, s5, 0x1001a
	s_and_b32 s2, s2, 0xffff
	s_add_i32 s8, s3, s7
	s_ashr_i32 s10, s5, 31
	s_xor_b32 s8, s8, s7
	s_add_i32 s11, s5, s10
	v_cvt_f32_u32_e32 v1, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v3, v1
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_sub_i32 s2, 0, s8
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v2, s2, v3
	s_add_i32 s2, s4, 0x1ff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_ashr_i32 s9, s2, 31
	v_ashrrev_i32_e32 v4, 31, v1
	s_lshr_b32 s9, s9, 23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_add_i32 s2, s2, s9
	v_mul_hi_u32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v1, v4
	s_xor_b32 s9, s11, s10
	s_ashr_i32 s10, s2, 9
	s_ashr_i32 s2, s2, 31
	s_mul_i32 s3, s3, s10
	v_xor_b32_e32 v5, v5, v4
	s_add_i32 s11, s10, s2
	v_add_nc_u32_e32 v2, v3, v2
	s_xor_b32 s2, s11, s2
	s_ashr_i32 s10, s3, 31
	v_cvt_f32_u32_e32 v7, s2
	s_add_i32 s3, s3, s10
	v_mul_hi_u32 v2, v5, v2
	s_xor_b32 s3, s3, s10
	v_cvt_f32_u32_e32 v6, s9
	v_rcp_iflag_f32_e32 v7, v7
	v_xor_b32_e32 v10, s7, v4
	s_sub_i32 s7, 0, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_iflag_f32_e32 v6, v6
	v_mul_lo_u32 v3, v2, s8
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v7, 0x4f7ffffe, v7
	v_sub_nc_u32_e32 v3, v5, v3
	v_mul_f32_e32 v6, 0x4f7ffffe, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v9, s8, v3
	v_cmp_le_u32_e32 vcc_lo, s8, v3
	v_add_nc_u32_e32 v8, 1, v2
	v_cvt_u32_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, v3, v9 :: v_dual_cndmask_b32 v2, v2, v8
	v_cvt_f32_u32_e32 v8, s3
	v_cmp_le_u32_e32 vcc_lo, s8, v3
	v_cvt_u32_f32_e32 v3, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v8, v8
	v_add_nc_u32_e32 v9, 1, v2
	v_cndmask_b32_e32 v2, v2, v9, vcc_lo
	v_lshrrev_b32_e32 v9, 27, v4
	v_xor_b32_e32 v4, s10, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v7, 0x4f7ffffe, v8
	v_mul_lo_u32 v8, s7, v3
	s_sub_i32 s7, 0, s3
	v_xor_b32_e32 v2, v2, v10
	v_add_nc_u32_e32 v9, v1, v9
	v_cvt_u32_f32_e32 v7, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v2, v2, v10
	v_mul_hi_u32 v8, v3, v8
	v_mul_lo_u32 v11, s7, v7
	s_sub_i32 s7, 0, s9
	v_ashrrev_i32_e32 v13, 5, v9
	v_ashrrev_i32_e32 v10, 31, v2
	v_mul_lo_u32 v12, s7, v6
	v_ashrrev_i32_e32 v14, 31, v9
	s_cmp_gt_i32 s5, -1
	v_add_nc_u32_e32 v3, v3, v8
	v_mul_hi_u32 v8, v7, v11
	s_cselect_b32 s12, -1, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v6, v12
	v_add_nc_u32_e32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v6, v11
	v_mul_hi_u32 v7, v5, v7
	v_add_nc_u32_e32 v2, v2, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v2, v10
	v_mul_hi_u32 v3, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v3, s2
	v_sub_nc_u32_e32 v2, v2, v3
	v_mul_lo_u32 v3, v7, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v11, s2, v2
	v_cmp_le_u32_e32 vcc_lo, s2, v2
	v_sub_nc_u32_e32 v3, v5, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v2, v2, v11 :: v_dual_and_b32 v5, 0xffffffe0, v9
	v_add_nc_u32_e32 v9, 1, v7
	v_cmp_le_u32_e32 vcc_lo, s3, v3
	v_add_nc_u32_e32 v12, v13, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v11, s2, v2
	v_cmp_le_u32_e64 s2, s2, v2
	v_sub_nc_u32_e32 v1, v1, v5
	v_cndmask_b32_e32 v7, v7, v9, vcc_lo
	v_xor_b32_e32 v8, v12, v14
	v_cndmask_b32_e64 v2, v2, v11, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v8, v6
	v_xor_b32_e32 v2, v2, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v2, v2, v10
	v_mul_lo_u32 v6, v6, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v8, v6
	v_subrev_nc_u32_e32 v8, s3, v3
	v_subrev_nc_u32_e32 v9, s9, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v3, v3, v8, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s9, v6
	v_add_nc_u32_e32 v8, 1, v7
	v_cndmask_b32_e32 v6, v6, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s3, v3
	v_cndmask_b32_e32 v3, v7, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v7, s9, v6
	v_cmp_le_u32_e32 vcc_lo, s9, v6
	v_xor_b32_e32 v5, v3, v4
	v_lshl_add_u32 v3, v2, 9, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v7, v6, v7 :: v_dual_mov_b32 v2, 0
	v_sub_nc_u32_e32 v6, v5, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e64 s2, s4, v3
	v_xor_b32_e32 v1, v7, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s3, s6, v6
	v_sub_nc_u32_e32 v1, v1, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s6, s2, s3
	s_and_b32 s6, s6, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s13, s6
	s_cbranch_execz .LBB3_4
; %bb.1:                                ; %.lr.ph
	s_clause 0x1
	s_load_b64 s[6:7], s[0:1], 0x28
	s_load_b32 s15, s[0:1], 0x30
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b128 s[8:11], s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v7, vcc_lo, s6, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v5, vcc_lo
	s_load_b64 s[6:7], s[0:1], 0x0
	v_add_co_u32 v4, vcc_lo, s10, v4
	global_load_b32 v2, v[7:8], off
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v5, s15, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v2, 0x4b800000, v5
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v5
	v_cndmask_b32_e32 v2, v5, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_rsq_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mad_u64_u32 v[7:8], null, v6, s5, v[1:2]
	v_add_nc_u32_e32 v8, 0x200, v3
	v_mul_f32_e32 v9, 0x45800000, v2
	v_mul_lo_u32 v6, v7, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min_i32_e32 v7, s4, v8
	v_cndmask_b32_e32 v8, v2, v9, vcc_lo
	v_mov_b32_e32 v2, 0
.LBB3_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v6, v3
	v_add_nc_u32_e32 v3, 32, v3
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	v_add_co_u32 v11, vcc_lo, s8, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v10, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v9, vcc_lo, s6, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	global_load_b32 v11, v[11:12], off
	global_load_b32 v9, v[9:10], off
	s_waitcnt vmcnt(0)
	v_dual_mul_f32 v10, -0.5, v11 :: v_dual_sub_f32 v9, v9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v10, v8, v10
	v_div_scale_f32 v11, null, v5, v5, v10
	v_div_scale_f32 v14, vcc_lo, v10, v5, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v12, v11
	s_waitcnt_depctr 0xfff
	v_fma_f32 v13, -v11, v12, 1.0
	v_fmac_f32_e32 v12, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, v14, v12
	v_fma_f32 v15, -v11, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v15, v12
	v_fma_f32 v11, -v11, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v11, v11, v12, v13
	v_cmp_ge_i32_e32 vcc_lo, v3, v7
	v_div_fixup_f32 v10, v11, v5, v10
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v2, v9, v10
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB3_2
; %bb.3:                                ; %Flow138
	s_or_b32 exec_lo, exec_lo, s14
.LBB3_4:                                ; %Flow139
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s13
	v_and_b32_e32 v5, 1, v0
	v_lshrrev_b32_e32 v3, 5, v0
	s_and_b32 s3, s12, s3
	v_cmp_eq_u32_e32 vcc_lo, 0, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_lshl_u32 v4, v3, v0, 2
	s_and_b32 s5, vcc_lo, s3
	ds_store_b32 v4, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s4, s5
	s_cbranch_execz .LBB3_6
; %bb.5:
	ds_load_2addr_b32 v[2:3], v4 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v4, v2
.LBB3_6:
	s_or_b32 exec_lo, exec_lo, s4
	v_and_b32_e32 v2, 3, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	s_and_b32 s5, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s5
	s_cbranch_execz .LBB3_8
; %bb.7:
	ds_load_2addr_b32 v[2:3], v4 offset1:2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v4, v2
.LBB3_8:
	s_or_b32 exec_lo, exec_lo, s4
	v_and_b32_e32 v2, 7, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	s_and_b32 s5, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s5
	s_cbranch_execz .LBB3_10
; %bb.9:
	ds_load_2addr_b32 v[2:3], v4 offset1:4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v4, v2
.LBB3_10:
	s_or_b32 exec_lo, exec_lo, s4
	v_and_b32_e32 v2, 15, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	s_and_b32 s5, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s5
	s_cbranch_execz .LBB3_12
; %bb.11:
	ds_load_2addr_b32 v[2:3], v4 offset1:8
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v4, v2
.LBB3_12:
	s_or_b32 exec_lo, exec_lo, s4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s4, s3
	s_cbranch_execz .LBB3_16
; %bb.13:
	v_and_b32_e32 v0, 31, v0
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_and_b32 s2, vcc_lo, s2
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB3_16
; %bb.14:
	s_load_b64 s[0:1], s[0:1], 0x38
	v_ashrrev_i32_e32 v2, 31, v1
	ds_load_2addr_b32 v[4:5], v4 offset1:16
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	v_add_f32_e32 v4, v4, v5
	global_load_b32 v3, v[0:1], off
.LBB3_15:                               ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v3, v4
	global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v2, v3
	v_mov_b32_e32 v3, v2
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB3_15
.LBB3_16:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf
		.amdhsa_group_segment_fixed_size 4224
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf, .Lfunc_end3-_Z31conv_bnorm_bwd_var_batch_kernelPKfiiiS0_S0_S0_fPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1652
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4224 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf ; -- Begin function _Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf
	.globl	_Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf
	.p2align	8
	.type	_Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf,@function
_Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf: ; @_Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf
; %bb.0:
	s_clause 0x1
	s_load_b128 s[16:19], s[0:1], 0x8
	s_load_b32 s2, s[0:1], 0x54
	s_mov_b32 s20, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s3, s17, 5
	s_bfe_i32 s4, s17, 0x1001a
	s_and_b32 s2, s2, 0xffff
	s_add_i32 s5, s3, s4
	s_ashr_i32 s7, s17, 31
	s_xor_b32 s5, s5, s4
	s_add_i32 s8, s17, s7
	v_cvt_f32_u32_e32 v1, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v3, v1
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_sub_i32 s2, 0, s5
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v2, s2, v3
	s_add_i32 s2, s16, 0x1ff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_ashr_i32 s6, s2, 31
	v_ashrrev_i32_e32 v4, 31, v1
	s_lshr_b32 s6, s6, 23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_add_i32 s2, s2, s6
	v_mul_hi_u32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v1, v4
	s_xor_b32 s6, s8, s7
	s_ashr_i32 s7, s2, 9
	s_ashr_i32 s2, s2, 31
	s_mul_i32 s3, s3, s7
	v_xor_b32_e32 v5, v5, v4
	s_add_i32 s8, s7, s2
	v_add_nc_u32_e32 v2, v3, v2
	s_xor_b32 s2, s8, s2
	s_ashr_i32 s7, s3, 31
	v_cvt_f32_u32_e32 v7, s2
	s_add_i32 s3, s3, s7
	v_mul_hi_u32 v2, v5, v2
	s_xor_b32 s3, s3, s7
	v_cvt_f32_u32_e32 v6, s6
	v_rcp_iflag_f32_e32 v7, v7
	v_xor_b32_e32 v10, s4, v4
	s_sub_i32 s4, 0, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_iflag_f32_e32 v6, v6
	v_mul_lo_u32 v3, v2, s5
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v7, 0x4f7ffffe, v7
	v_sub_nc_u32_e32 v3, v5, v3
	v_mul_f32_e32 v6, 0x4f7ffffe, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v9, s5, v3
	v_cmp_le_u32_e32 vcc_lo, s5, v3
	v_add_nc_u32_e32 v8, 1, v2
	v_cvt_u32_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, v3, v9 :: v_dual_cndmask_b32 v2, v2, v8
	v_cvt_f32_u32_e32 v8, s3
	v_cmp_le_u32_e32 vcc_lo, s5, v3
	v_cvt_u32_f32_e32 v3, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v8, v8
	v_add_nc_u32_e32 v9, 1, v2
	v_cndmask_b32_e32 v2, v2, v9, vcc_lo
	v_lshrrev_b32_e32 v9, 27, v4
	v_xor_b32_e32 v4, s7, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v7, 0x4f7ffffe, v8
	v_mul_lo_u32 v8, s4, v3
	s_sub_i32 s4, 0, s3
	v_xor_b32_e32 v2, v2, v10
	v_add_nc_u32_e32 v9, v1, v9
	v_cvt_u32_f32_e32 v7, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v2, v2, v10
	v_mul_hi_u32 v8, v3, v8
	v_mul_lo_u32 v11, s4, v7
	s_sub_i32 s4, 0, s6
	v_ashrrev_i32_e32 v13, 5, v9
	v_ashrrev_i32_e32 v10, 31, v2
	v_mul_lo_u32 v12, s4, v6
	v_ashrrev_i32_e32 v14, 31, v9
	s_cmp_gt_i32 s17, -1
	v_add_nc_u32_e32 v3, v3, v8
	v_mul_hi_u32 v8, v7, v11
	s_cselect_b32 s5, -1, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v6, v12
	v_add_nc_u32_e32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v6, v11
	v_mul_hi_u32 v7, v5, v7
	v_add_nc_u32_e32 v2, v2, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v2, v10
	v_mul_hi_u32 v3, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v3, s2
	v_sub_nc_u32_e32 v2, v2, v3
	v_mul_lo_u32 v3, v7, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v11, s2, v2
	v_cmp_le_u32_e32 vcc_lo, s2, v2
	v_sub_nc_u32_e32 v3, v5, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v2, v2, v11 :: v_dual_and_b32 v5, 0xffffffe0, v9
	v_add_nc_u32_e32 v9, 1, v7
	v_cmp_le_u32_e32 vcc_lo, s3, v3
	v_add_nc_u32_e32 v12, v13, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v11, s2, v2
	v_cmp_le_u32_e64 s2, s2, v2
	v_sub_nc_u32_e32 v1, v1, v5
	v_cndmask_b32_e32 v7, v7, v9, vcc_lo
	v_xor_b32_e32 v8, v12, v14
	v_cndmask_b32_e64 v2, v2, v11, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v8, v6
	v_xor_b32_e32 v2, v2, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v2, v2, v10
	v_mul_lo_u32 v6, v6, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v8, v6
	v_subrev_nc_u32_e32 v8, s3, v3
	v_subrev_nc_u32_e32 v9, s6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v3, v3, v8, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s6, v6
	v_add_nc_u32_e32 v8, 1, v7
	v_cndmask_b32_e32 v6, v6, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s3, v3
	v_cndmask_b32_e32 v3, v7, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v7, s6, v6
	v_cmp_le_u32_e32 vcc_lo, s6, v6
	v_xor_b32_e32 v5, v3, v4
	v_lshl_add_u32 v3, v2, 9, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v6, v6, v7, vcc_lo
	v_sub_nc_u32_e32 v4, v5, v4
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v1, v6, v14
	v_cmp_gt_i32_e64 s2, s16, v3
	v_cmp_gt_i32_e64 s3, s18, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v1, v1, v14
	s_and_b32 s4, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s4, s4, s5
	s_and_saveexec_b32 s19, s4
	s_cbranch_execz .LBB4_4
; %bb.1:                                ; %.lr.ph
	s_load_b256 s[8:15], s[0:1], 0x18
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s4, s16, -1
	s_add_i32 s6, s18, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v7, vcc_lo, s12, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s13, v6, vcc_lo
	global_load_b32 v9, v[7:8], off
	v_add_co_u32 v7, vcc_lo, s14, v5
	v_add_co_ci_u32_e32 v8, vcc_lo, s15, v6, vcc_lo
	v_add_co_u32 v5, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	global_load_b32 v7, v[7:8], off
	global_load_b32 v2, v[5:6], off
	v_cvt_f32_i32_e32 v5, s4
	s_load_b32 s4, s[0:1], 0x38
	v_cvt_f32_i32_e32 v6, s6
	s_load_b64 s[6:7], s[0:1], 0x0
	s_waitcnt vmcnt(2) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v8, v5, v6 :: v_dual_add_f32 v9, s4, v9
	v_div_scale_f32 v5, null, v8, v8, 1.0
	v_div_scale_f32 v11, vcc_lo, 1.0, v8, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_f32_e64 s4, 0x800000, v9
	v_rcp_f32_e32 v6, v5
	v_mul_f32_e32 v13, 0x4b800000, v9
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v7, -2.0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v9, v9, v13, s4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v10, -v5, v6, 1.0
	v_rsq_f32_e32 v9, v9
	v_fmac_f32_e32 v6, v10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v10, v11, v6
	v_fma_f32 v12, -v5, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v12, v6
	v_fma_f32 v5, -v5, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v10, v5, v6, v10
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[5:6], null, v4, s17, v[1:2]
	v_add_nc_u32_e32 v4, 0x200, v3
	v_div_fixup_f32 v8, v10, v8, 1.0
	v_mul_f32_e32 v10, 0x45800000, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_min_i32_e32 v4, s16, v4
	v_mul_lo_u32 v6, v5, s16
	v_mul_f32_e32 v7, v8, v7
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v8, v9, v10, s4
	v_mov_b32_e32 v5, 0
.LBB4_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v6, v3
	v_add_nc_u32_e32 v3, 32, v3
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	v_add_co_u32 v11, vcc_lo, s6, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v10, vcc_lo
	v_add_co_u32 v9, vcc_lo, s8, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
	v_cmp_ge_i32_e32 vcc_lo, v3, v4
	global_load_b32 v11, v[11:12], off
	global_load_b32 v9, v[9:10], off
	s_or_b32 s20, vcc_lo, s20
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v10, v11, v2 :: v_dual_mul_f32 v9, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, v7, v10, -v9
	v_add_f32_e32 v5, v5, v9
	s_and_not1_b32 exec_lo, exec_lo, s20
	s_cbranch_execnz .LBB4_2
; %bb.3:                                ; %Flow147
	s_or_b32 exec_lo, exec_lo, s20
.LBB4_4:                                ; %Flow148
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s19
	v_and_b32_e32 v3, 1, v0
	v_lshrrev_b32_e32 v2, 5, v0
	s_and_b32 s3, s5, s3
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_lshl_u32 v4, v2, v0, 2
	s_and_b32 s5, vcc_lo, s3
	ds_store_b32 v4, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s4, s5
	s_cbranch_execz .LBB4_6
; %bb.5:
	ds_load_2addr_b32 v[2:3], v4 offset1:1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v4, v2
.LBB4_6:
	s_or_b32 exec_lo, exec_lo, s4
	v_and_b32_e32 v2, 3, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	s_and_b32 s5, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s5
	s_cbranch_execz .LBB4_8
; %bb.7:
	ds_load_2addr_b32 v[2:3], v4 offset1:2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v4, v2
.LBB4_8:
	s_or_b32 exec_lo, exec_lo, s4
	v_and_b32_e32 v2, 7, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	s_and_b32 s5, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s5
	s_cbranch_execz .LBB4_10
; %bb.9:
	ds_load_2addr_b32 v[2:3], v4 offset1:4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v4, v2
.LBB4_10:
	s_or_b32 exec_lo, exec_lo, s4
	v_and_b32_e32 v2, 15, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	s_and_b32 s5, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s5
	s_cbranch_execz .LBB4_12
; %bb.11:
	ds_load_2addr_b32 v[2:3], v4 offset1:8
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v4, v2
.LBB4_12:
	s_or_b32 exec_lo, exec_lo, s4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s4, s3
	s_cbranch_execz .LBB4_16
; %bb.13:
	v_and_b32_e32 v0, 31, v0
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_and_b32 s2, vcc_lo, s2
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB4_16
; %bb.14:
	s_load_b64 s[0:1], s[0:1], 0x40
	v_ashrrev_i32_e32 v2, 31, v1
	ds_load_2addr_b32 v[4:5], v4 offset1:16
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	v_add_f32_e32 v4, v4, v5
	global_load_b32 v3, v[0:1], off
.LBB4_15:                               ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v3, v4
	global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v2, v3
	v_mov_b32_e32 v3, v2
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB4_15
.LBB4_16:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf
		.amdhsa_group_segment_fixed_size 4224
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 21
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf, .Lfunc_end4-_Z32conv_bnorm_bwd_mean_batch_kernelPKfiiiS0_S0_S0_S0_fPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1700
; NumSgprs: 23
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4224 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf ; -- Begin function _Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf
	.globl	_Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf
	.p2align	8
	.type	_Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf,@function
_Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf: ; @_Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf
; %bb.0:
	s_clause 0x1
	s_load_b128 s[16:19], s[0:1], 0x8
	s_load_b32 s2, s[0:1], 0x5c
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s3, s17, 5
	s_bfe_i32 s4, s17, 0x1001a
	s_and_b32 s2, s2, 0xffff
	s_add_i32 s5, s3, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s5, s5, s4
	v_cvt_f32_u32_e32 v1, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v3, v1
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_sub_i32 s2, 0, s5
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v0, s2, v3
	s_add_i32 s2, s16, 0x1ff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_ashr_i32 s6, s2, 31
	v_ashrrev_i32_e32 v4, 31, v1
	s_lshr_b32 s6, s6, 23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_add_i32 s2, s2, s6
	v_mul_hi_u32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v1, v4
	s_ashr_i32 s6, s2, 9
	s_ashr_i32 s2, s2, 31
	s_mul_i32 s3, s3, s6
	s_add_i32 s7, s6, s2
	v_xor_b32_e32 v2, v2, v4
	s_xor_b32 s2, s7, s2
	v_add_nc_u32_e32 v0, v3, v0
	v_cvt_f32_u32_e32 v5, s2
	s_ashr_i32 s6, s3, 31
	v_xor_b32_e32 v8, s4, v4
	s_add_i32 s3, s3, s6
	v_mul_hi_u32 v0, v2, v0
	v_rcp_iflag_f32_e32 v5, v5
	s_xor_b32 s3, s3, s6
	s_sub_i32 s4, 0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v0, s5
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v5, 0x4f7ffffe, v5 :: v_dual_add_nc_u32 v6, 1, v0
	v_sub_nc_u32_e32 v3, v2, v3
	v_cmp_le_u32_e32 vcc_lo, s5, v3
	v_subrev_nc_u32_e32 v7, s5, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, v0, v6, vcc_lo
	v_cvt_f32_u32_e32 v6, s3
	v_cndmask_b32_e32 v3, v3, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, 1, v0
	v_rcp_iflag_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s5, v3
	v_cvt_u32_f32_e32 v3, v5
	s_waitcnt_depctr 0xfff
	v_dual_cndmask_b32 v0, v0, v7 :: v_dual_mul_f32 v5, 0x4f7ffffe, v6
	v_mul_lo_u32 v6, s4, v3
	v_xor_b32_e32 v0, v0, v8
	s_sub_i32 s4, 0, s3
	s_cmp_gt_i32 s17, -1
	v_cvt_u32_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v0, v0, v8
	v_mul_hi_u32 v6, v3, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v8, s4, v5
	s_cselect_b32 s4, -1, 0
	v_ashrrev_i32_e32 v7, 31, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v3, v3, v6
	v_mul_hi_u32 v6, v5, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, v5, v6
	v_mul_hi_u32 v5, v2, v5
	v_add_nc_u32_e32 v0, v0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v7
	v_mul_hi_u32 v3, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v3, s2
	v_sub_nc_u32_e32 v0, v0, v3
	v_mul_lo_u32 v3, v5, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v6, s2, v0
	v_cmp_le_u32_e32 vcc_lo, s2, v0
	v_sub_nc_u32_e32 v3, v2, v3
	v_add_nc_u32_e32 v2, 1, v5
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e32 v0, v0, v6, vcc_lo
	v_lshrrev_b32_e32 v6, 27, v4
	v_xor_b32_e32 v4, s6, v4
	v_subrev_nc_u32_e32 v8, s3, v3
	v_cmp_le_u32_e32 vcc_lo, s3, v3
	v_subrev_nc_u32_e32 v9, s2, v0
	v_cmp_le_u32_e64 s2, s2, v0
	v_cndmask_b32_e32 v5, v5, v2, vcc_lo
	v_dual_cndmask_b32 v3, v3, v8 :: v_dual_add_nc_u32 v2, v1, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v0, v0, v9, s2
	v_add_nc_u32_e32 v6, 1, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_le_u32_e32 vcc_lo, s3, v3
	v_and_b32_e32 v8, 0xffffffe0, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v0, v0, v7
	s_mov_b32 s3, 0
	v_cndmask_b32_e32 v3, v5, v6, vcc_lo
	v_sub_nc_u32_e32 v1, v1, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v0, v0, v7
	v_xor_b32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v0, v0, 9, v1
	v_sub_nc_u32_e32 v1, v3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s16, v0
	v_cmp_gt_i32_e64 s2, s18, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_b32 s2, s2, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s2
	s_cbranch_execz .LBB5_3
; %bb.1:                                ; %.lr.ph
	s_ashr_i32 s2, s17, 31
	v_ashrrev_i32_e32 v2, 5, v2
	s_add_i32 s4, s17, s2
	s_load_b64 s[12:13], s[0:1], 0x38
	s_xor_b32 s2, s4, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v2
	v_cvt_f32_u32_e32 v3, s2
	s_sub_i32 s4, 0, s2
	v_add_nc_u32_e32 v2, v2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v3, v3
	v_xor_b32_e32 v2, v2, v5
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v3
	v_mul_lo_u32 v4, s4, v3
	s_load_b256 s[4:11], s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v3, v4
	v_add_nc_u32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v2, v3
	v_mul_lo_u32 v3, v3, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v2, v3
	v_subrev_nc_u32_e32 v3, s2, v2
	v_cmp_le_u32_e32 vcc_lo, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, v2, v3, vcc_lo
	v_subrev_nc_u32_e32 v3, s2, v2
	v_cmp_le_u32_e32 vcc_lo, s2, v2
	s_add_i32 s2, s16, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, v2, v3, vcc_lo
	v_xor_b32_e32 v2, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v2, v5
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s10, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v5, vcc_lo
	global_load_b32 v10, v[6:7], off
	v_add_co_u32 v6, vcc_lo, s12, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, s13, v5, vcc_lo
	v_add_co_u32 v8, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v5, vcc_lo
	s_clause 0x1
	s_load_b32 s14, s[0:1], 0x40
	s_load_b64 s[10:11], s[0:1], 0x48
	global_load_b32 v6, v[6:7], off
	global_load_b32 v7, v[8:9], off
	v_add_co_u32 v4, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	s_add_i32 s6, s18, -1
	v_cvt_f32_i32_e32 v8, s16
	v_cvt_f32_i32_e32 v9, s18
	global_load_b32 v2, v[4:5], off
	v_cvt_f32_i32_e32 v4, s2
	v_cvt_f32_i32_e32 v5, s6
	s_load_b64 s[6:7], s[0:1], 0x0
	v_mul_f32_e32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v11, v4, v5
	v_div_scale_f32 v5, null, v8, v8, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v4, null, v11, v11, 1.0
	v_rcp_f32_e32 v12, v5
	v_div_scale_f32 v15, vcc_lo, 1.0, v11, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v9, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v14, -v5, v12, 1.0
	v_fma_f32 v13, -v4, v9, 1.0
	v_fmac_f32_e32 v9, v13, v9
	v_div_scale_f32 v13, s2, 1.0, v8, 1.0
	s_waitcnt vmcnt(3) lgkmcnt(0)
	v_add_f32_e32 v10, s14, v10
	v_fmac_f32_e32 v12, v14, v12
	v_mul_f32_e32 v14, v15, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f32_e64 s0, 0x800000, v10
	v_fma_f32 v17, -v4, v14, v15
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v6, v6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v14, v17, v9 :: v_dual_mul_f32 v17, 0x4b800000, v10
	v_mul_f32_e32 v16, v13, v12
	v_fma_f32 v4, -v4, v14, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, v10, v17, s0
	v_fma_f32 v18, -v5, v16, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v9, v4, v9, v14
	v_rsq_f32_e32 v10, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v16, v18, v12
	s_mov_b32 vcc_lo, s2
	v_div_fixup_f32 v9, v9, v11, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v5, -v5, v16, v13
	v_mul_f32_e32 v6, v9, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v12, v5, v12, v16
	v_mad_u64_u32 v[4:5], null, v1, s17, v[3:4]
	v_add_nc_u32_e32 v1, 0x200, v0
	v_div_fixup_f32 v5, v12, v8, 1.0
	v_mul_f32_e32 v8, 0x45800000, v10
	s_delay_alu instid0(VALU_DEP_3)
	v_min_i32_e32 v1, s16, v1
	v_mul_lo_u32 v3, v4, s16
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v4, v5, v7
	v_cndmask_b32_e64 v5, v10, v8, s0
.LBB5_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, v3, v0
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_add_co_u32 v9, vcc_lo, s4, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v8, vcc_lo
	v_add_co_u32 v11, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v8, vcc_lo
	v_add_co_u32 v7, s0, s10, v7
	global_load_b32 v9, v[9:10], off
	global_load_b32 v10, v[11:12], off
	v_add_co_ci_u32_e64 v8, s0, s11, v8, s0
	s_waitcnt vmcnt(1)
	v_fma_f32 v9, v5, v9, v4
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v10, v10, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v9, v6, v10 :: v_dual_add_nc_u32 v0, 32, v0
	v_cmp_ge_i32_e32 vcc_lo, v0, v1
	global_store_b32 v[7:8], v9, off
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB5_2
.LBB5_3:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf, .Lfunc_end5-_Z32conv_bnorm_bwd_data_batch_kernelPKfiiiS0_S0_S0_S0_S0_fPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1440
; NumSgprs: 22
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z43conv_diag_affine_white_var_fwd_batch_kernelPKfiiiS0_S0_fPf.kd
    .uniform_work_group_size: 1
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...

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