__device__ float fracf(float x) {
    return x - floorf(x);
}
__device__ float random (float s, float t, float *rSeed) {
    return fracf(sinf(s*12.98123198*rSeed[0] + t*78.231233*rSeed[1])*43758.5453123);
}

__device__ float fitness(
    float p1x, float p1y, float p2x, float p2y, float p3x, float p3y,
    float *obs, int nObs) {

    float ox, oy, ux, uy, vx, vy, wx, wy, pux, puy, pvx, pvy, pwx, pwy, cross1, cross2, cross3, fit;

    ux = p2x-p1x; uy = p2y-p1y;
    vx = p3x-p1x; vy = p3y-p1y;
    fit = ux*vy - uy*vx;
    if(fit<0) fit = -fit;

    for (int i=0; i<nObs; i++) {
        ox = obs[i*2+0];
        oy = obs[i*2+1];
        ux = p2x-p1x; uy=p2y-p1y;
        pux = ox-p1x; puy=oy-p1y;
        vx = p3x-p2x; vy=p3y-p2y;
        pvx = ox-p2x; pvy=oy-p2y;
        wx = p1x-p3x; wy=p1y-p3y;
        pwx = ox-p3x; pwy=oy-p3y;
        cross1 = ux*puy-uy*pux;
        cross2 = vx*pvy-vy*pvx;
        cross3 = wx*pwy-wy*pwx;
        if( cross1 > 0 && cross2 > 0 && cross3 > 0){ fit /= 2.0; }
        if( cross1 < 0 && cross2 < 0 && cross3 < 0){ fit /= 2.0; }
    }

    if(p1x > 1 || p1x < -1) { fit = 0; }
    if(p1y > 1 || p1y < -1) { fit = 0; }
    if(p2x > 1 || p2x < -1) { fit = 0; }
    if(p2y > 1 || p2y < -1) { fit = 0; }
    if(p3x > 1 || p3x < -1) { fit = 0; }
    if(p3y > 1 || p3y < -1) { fit = 0; }

    return fit;
}

__global__ void computeFitness(float *obs, float *gene, float *fit, int* metaData)
{
    const int idx = threadIdx.x + blockDim.x*blockIdx.x;
    if(idx>metaData[1]) return;

    fit[idx] = fitness(
        gene[idx*6], gene[idx*6+1], gene[idx*6+2], gene[idx*6+3], gene[idx*6+4], gene[idx*6+5],
        obs, metaData[0]);

}

__global__ void rearrangePopulation(float *gene, float *fit, int* metaData)
{
    const int idx = threadIdx.x + blockDim.x*blockIdx.x;
    int nGene = metaData[1];
    int nHalf = nGene / 2;
    if(idx> nHalf) return;

    int j = nGene - 1 - idx;

    if (fit[idx] < fit[j]) {
        for(int k=0; k<6; k++) {
            float t = gene[idx*6+k];
            gene[idx*6+k] = gene[j*6+k];
            gene[j*6+k] = t;
            t = fit[idx];
            fit[idx] = fit[j];
            fit[j] = t;
        }
    }
}

__global__ void crossOver(float *gene, float *rSeed, int* metaData)
{
    const int idx = 2 * (threadIdx.x + blockDim.x*blockIdx.x);
    int nGene = metaData[1];
    int nHalf = nGene / 2;
    if(idx> nHalf) return;

    int childStart = int(nGene / 2);
    int j = idx + 1;
    int mutRegion = int(nHalf*1.5);
    int idx2 = idx + mutRegion;
    float w[6] = {
        random(gene[idx2*6], gene[j*6+1], rSeed),
        random(gene[idx2*6+1], gene[j*6], rSeed),
        random(gene[j*6], gene[idx2*6+1], rSeed),
        random(gene[idx2*6+1], gene[j*6+1], rSeed),
        random(gene[idx2*6], gene[j*6], rSeed),
        random(gene[j*6+1], gene[idx2*6+1], rSeed)
        };

    int childIdx = childStart + int(idx/2);
    for(int i=0; i<6; i++) {
        gene[childIdx*6 + i] = (1.0-w[i])*gene[idx*6+i] + w[i]*gene[j*6+i];
    }
}

__global__ void mutate(float *gene, float *rSeed, int* metaData)
{
    const int idx = (threadIdx.x + blockDim.x*blockIdx.x);
    int nGene = metaData[1];
    int nQuater = int(nGene / 4);
    if(idx> nQuater) return;

    int mutStart = int(nGene / 2) + nQuater;
    int i = mutStart + idx;

    float mut1 = 1.0 + (random(gene[i*6], gene[i*6], rSeed) - 0.5);
    float mut2 = 1.0 + (random(gene[i*6+1], gene[i*6], rSeed) - 0.5);
    float mut3 = 1.0 + (random(gene[i*6], gene[i*6+1], rSeed) - 0.5);

    gene[i*6+0] = mut1 * gene[idx*6+0];
    gene[i*6+1] = mut1 * gene[idx*6+1];
    gene[i*6+2] = mut2 * gene[idx*6+2];
    gene[i*6+3] = mut2 * gene[idx*6+3];
    gene[i*6+4] = mut3 * gene[idx*6+4];
    gene[i*6+5] = mut3 * gene[idx*6+5];

}

__global__ void shuffleGene(float *gene, float *fit, float *rSeed, int* metaData) {
    const int idx = threadIdx.x + blockDim.x*blockIdx.x;
    int nGene = metaData[1];
    int nHalf = nGene / 2;
    if(idx> nHalf) return;

    int Offset = int(nHalf/5.3);
    int j = nHalf + (idx + Offset)%nHalf;

    for(int k=0; k<6; k++) {
        float t = gene[idx*6+k];
        gene[idx*6+k] = gene[j*6+k];
        gene[j*6+k] = t;
        t = fit[idx];
        fit[idx] = fit[j];
        fit[j] = t;
    }
}
	.file	"tmpxft_002a6fcd_00000000-6_cudaKernels.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2013:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2013:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z5fracff
	.type	_Z5fracff, @function
_Z5fracff:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z5fracff, .-_Z5fracff
	.globl	_Z6randomffPf
	.type	_Z6randomffPf, @function
_Z6randomffPf:
.LFB2009:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2009:
	.size	_Z6randomffPf, .-_Z6randomffPf
	.globl	_Z7fitnessffffffPfi
	.type	_Z7fitnessffffffPfi, @function
_Z7fitnessffffffPfi:
.LFB2010:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2010:
	.size	_Z7fitnessffffffPfi, .-_Z7fitnessffffffPfi
	.globl	_Z40__device_stub__Z14computeFitnessPfS_S_PiPfS_S_Pi
	.type	_Z40__device_stub__Z14computeFitnessPfS_S_PiPfS_S_Pi, @function
_Z40__device_stub__Z14computeFitnessPfS_S_PiPfS_S_Pi:
.LFB2035:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z14computeFitnessPfS_S_Pi(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z40__device_stub__Z14computeFitnessPfS_S_PiPfS_S_Pi, .-_Z40__device_stub__Z14computeFitnessPfS_S_PiPfS_S_Pi
	.globl	_Z14computeFitnessPfS_S_Pi
	.type	_Z14computeFitnessPfS_S_Pi, @function
_Z14computeFitnessPfS_S_Pi:
.LFB2036:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z14computeFitnessPfS_S_PiPfS_S_Pi
	.cfi_endproc
.LFE2036:
	.size	_Z14computeFitnessPfS_S_Pi, .-_Z14computeFitnessPfS_S_Pi
	.globl	_Z43__device_stub__Z19rearrangePopulationPfS_PiPfS_Pi
	.type	_Z43__device_stub__Z19rearrangePopulationPfS_PiPfS_Pi, @function
_Z43__device_stub__Z19rearrangePopulationPfS_PiPfS_Pi:
.LFB2037:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z19rearrangePopulationPfS_Pi(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L14:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2037:
	.size	_Z43__device_stub__Z19rearrangePopulationPfS_PiPfS_Pi, .-_Z43__device_stub__Z19rearrangePopulationPfS_PiPfS_Pi
	.globl	_Z19rearrangePopulationPfS_Pi
	.type	_Z19rearrangePopulationPfS_Pi, @function
_Z19rearrangePopulationPfS_Pi:
.LFB2038:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z19rearrangePopulationPfS_PiPfS_Pi
	.cfi_endproc
.LFE2038:
	.size	_Z19rearrangePopulationPfS_Pi, .-_Z19rearrangePopulationPfS_Pi
	.globl	_Z32__device_stub__Z9crossOverPfS_PiPfS_Pi
	.type	_Z32__device_stub__Z9crossOverPfS_PiPfS_Pi, @function
_Z32__device_stub__Z9crossOverPfS_PiPfS_Pi:
.LFB2039:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z9crossOverPfS_Pi(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L19:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2039:
	.size	_Z32__device_stub__Z9crossOverPfS_PiPfS_Pi, .-_Z32__device_stub__Z9crossOverPfS_PiPfS_Pi
	.globl	_Z9crossOverPfS_Pi
	.type	_Z9crossOverPfS_Pi, @function
_Z9crossOverPfS_Pi:
.LFB2040:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z9crossOverPfS_PiPfS_Pi
	.cfi_endproc
.LFE2040:
	.size	_Z9crossOverPfS_Pi, .-_Z9crossOverPfS_Pi
	.globl	_Z29__device_stub__Z6mutatePfS_PiPfS_Pi
	.type	_Z29__device_stub__Z6mutatePfS_PiPfS_Pi, @function
_Z29__device_stub__Z6mutatePfS_PiPfS_Pi:
.LFB2041:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z6mutatePfS_Pi(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L24:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2041:
	.size	_Z29__device_stub__Z6mutatePfS_PiPfS_Pi, .-_Z29__device_stub__Z6mutatePfS_PiPfS_Pi
	.globl	_Z6mutatePfS_Pi
	.type	_Z6mutatePfS_Pi, @function
_Z6mutatePfS_Pi:
.LFB2042:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z6mutatePfS_PiPfS_Pi
	.cfi_endproc
.LFE2042:
	.size	_Z6mutatePfS_Pi, .-_Z6mutatePfS_Pi
	.globl	_Z37__device_stub__Z11shuffleGenePfS_S_PiPfS_S_Pi
	.type	_Z37__device_stub__Z11shuffleGenePfS_S_PiPfS_S_Pi, @function
_Z37__device_stub__Z11shuffleGenePfS_S_PiPfS_S_Pi:
.LFB2043:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z11shuffleGenePfS_S_Pi(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L29:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2043:
	.size	_Z37__device_stub__Z11shuffleGenePfS_S_PiPfS_S_Pi, .-_Z37__device_stub__Z11shuffleGenePfS_S_PiPfS_S_Pi
	.globl	_Z11shuffleGenePfS_S_Pi
	.type	_Z11shuffleGenePfS_S_Pi, @function
_Z11shuffleGenePfS_S_Pi:
.LFB2044:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z11shuffleGenePfS_S_PiPfS_S_Pi
	.cfi_endproc
.LFE2044:
	.size	_Z11shuffleGenePfS_S_Pi, .-_Z11shuffleGenePfS_S_Pi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z11shuffleGenePfS_S_Pi"
.LC1:
	.string	"_Z6mutatePfS_Pi"
.LC2:
	.string	"_Z9crossOverPfS_Pi"
.LC3:
	.string	"_Z19rearrangePopulationPfS_Pi"
.LC4:
	.string	"_Z14computeFitnessPfS_S_Pi"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2046:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z11shuffleGenePfS_S_Pi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z6mutatePfS_Pi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9crossOverPfS_Pi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z19rearrangePopulationPfS_Pi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z14computeFitnessPfS_S_Pi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2046:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
__device__ float fracf(float x) {
    return x - floorf(x);
}
__device__ float random (float s, float t, float *rSeed) {
    return fracf(sinf(s*12.98123198*rSeed[0] + t*78.231233*rSeed[1])*43758.5453123);
}

__device__ float fitness(
    float p1x, float p1y, float p2x, float p2y, float p3x, float p3y,
    float *obs, int nObs) {

    float ox, oy, ux, uy, vx, vy, wx, wy, pux, puy, pvx, pvy, pwx, pwy, cross1, cross2, cross3, fit;

    ux = p2x-p1x; uy = p2y-p1y;
    vx = p3x-p1x; vy = p3y-p1y;
    fit = ux*vy - uy*vx;
    if(fit<0) fit = -fit;

    for (int i=0; i<nObs; i++) {
        ox = obs[i*2+0];
        oy = obs[i*2+1];
        ux = p2x-p1x; uy=p2y-p1y;
        pux = ox-p1x; puy=oy-p1y;
        vx = p3x-p2x; vy=p3y-p2y;
        pvx = ox-p2x; pvy=oy-p2y;
        wx = p1x-p3x; wy=p1y-p3y;
        pwx = ox-p3x; pwy=oy-p3y;
        cross1 = ux*puy-uy*pux;
        cross2 = vx*pvy-vy*pvx;
        cross3 = wx*pwy-wy*pwx;
        if( cross1 > 0 && cross2 > 0 && cross3 > 0){ fit /= 2.0; }
        if( cross1 < 0 && cross2 < 0 && cross3 < 0){ fit /= 2.0; }
    }

    if(p1x > 1 || p1x < -1) { fit = 0; }
    if(p1y > 1 || p1y < -1) { fit = 0; }
    if(p2x > 1 || p2x < -1) { fit = 0; }
    if(p2y > 1 || p2y < -1) { fit = 0; }
    if(p3x > 1 || p3x < -1) { fit = 0; }
    if(p3y > 1 || p3y < -1) { fit = 0; }

    return fit;
}

__global__ void computeFitness(float *obs, float *gene, float *fit, int* metaData)
{
    const int idx = threadIdx.x + blockDim.x*blockIdx.x;
    if(idx>metaData[1]) return;

    fit[idx] = fitness(
        gene[idx*6], gene[idx*6+1], gene[idx*6+2], gene[idx*6+3], gene[idx*6+4], gene[idx*6+5],
        obs, metaData[0]);

}

__global__ void rearrangePopulation(float *gene, float *fit, int* metaData)
{
    const int idx = threadIdx.x + blockDim.x*blockIdx.x;
    int nGene = metaData[1];
    int nHalf = nGene / 2;
    if(idx> nHalf) return;

    int j = nGene - 1 - idx;

    if (fit[idx] < fit[j]) {
        for(int k=0; k<6; k++) {
            float t = gene[idx*6+k];
            gene[idx*6+k] = gene[j*6+k];
            gene[j*6+k] = t;
            t = fit[idx];
            fit[idx] = fit[j];
            fit[j] = t;
        }
    }
}

__global__ void crossOver(float *gene, float *rSeed, int* metaData)
{
    const int idx = 2 * (threadIdx.x + blockDim.x*blockIdx.x);
    int nGene = metaData[1];
    int nHalf = nGene / 2;
    if(idx> nHalf) return;

    int childStart = int(nGene / 2);
    int j = idx + 1;
    int mutRegion = int(nHalf*1.5);
    int idx2 = idx + mutRegion;
    float w[6] = {
        random(gene[idx2*6], gene[j*6+1], rSeed),
        random(gene[idx2*6+1], gene[j*6], rSeed),
        random(gene[j*6], gene[idx2*6+1], rSeed),
        random(gene[idx2*6+1], gene[j*6+1], rSeed),
        random(gene[idx2*6], gene[j*6], rSeed),
        random(gene[j*6+1], gene[idx2*6+1], rSeed)
        };

    int childIdx = childStart + int(idx/2);
    for(int i=0; i<6; i++) {
        gene[childIdx*6 + i] = (1.0-w[i])*gene[idx*6+i] + w[i]*gene[j*6+i];
    }
}

__global__ void mutate(float *gene, float *rSeed, int* metaData)
{
    const int idx = (threadIdx.x + blockDim.x*blockIdx.x);
    int nGene = metaData[1];
    int nQuater = int(nGene / 4);
    if(idx> nQuater) return;

    int mutStart = int(nGene / 2) + nQuater;
    int i = mutStart + idx;

    float mut1 = 1.0 + (random(gene[i*6], gene[i*6], rSeed) - 0.5);
    float mut2 = 1.0 + (random(gene[i*6+1], gene[i*6], rSeed) - 0.5);
    float mut3 = 1.0 + (random(gene[i*6], gene[i*6+1], rSeed) - 0.5);

    gene[i*6+0] = mut1 * gene[idx*6+0];
    gene[i*6+1] = mut1 * gene[idx*6+1];
    gene[i*6+2] = mut2 * gene[idx*6+2];
    gene[i*6+3] = mut2 * gene[idx*6+3];
    gene[i*6+4] = mut3 * gene[idx*6+4];
    gene[i*6+5] = mut3 * gene[idx*6+5];

}

__global__ void shuffleGene(float *gene, float *fit, float *rSeed, int* metaData) {
    const int idx = threadIdx.x + blockDim.x*blockIdx.x;
    int nGene = metaData[1];
    int nHalf = nGene / 2;
    if(idx> nHalf) return;

    int Offset = int(nHalf/5.3);
    int j = nHalf + (idx + Offset)%nHalf;

    for(int k=0; k<6; k++) {
        float t = gene[idx*6+k];
        gene[idx*6+k] = gene[j*6+k];
        gene[j*6+k] = t;
        t = fit[idx];
        fit[idx] = fit[j];
        fit[j] = t;
    }
}
	.text
	.file	"cudaKernels.hip"
	.globl	_Z29__device_stub__computeFitnessPfS_S_Pi # -- Begin function _Z29__device_stub__computeFitnessPfS_S_Pi
	.type	_Z29__device_stub__computeFitnessPfS_S_Pi,@function
_Z29__device_stub__computeFitnessPfS_S_Pi: # @_Z29__device_stub__computeFitnessPfS_S_Pi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14computeFitnessPfS_S_Pi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z29__device_stub__computeFitnessPfS_S_Pi, .Lfunc_end0-_Z29__device_stub__computeFitnessPfS_S_Pi
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__rearrangePopulationPfS_Pi # -- Begin function _Z34__device_stub__rearrangePopulationPfS_Pi
	.type	_Z34__device_stub__rearrangePopulationPfS_Pi,@function
_Z34__device_stub__rearrangePopulationPfS_Pi: # @_Z34__device_stub__rearrangePopulationPfS_Pi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19rearrangePopulationPfS_Pi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z34__device_stub__rearrangePopulationPfS_Pi, .Lfunc_end1-_Z34__device_stub__rearrangePopulationPfS_Pi
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__crossOverPfS_Pi # -- Begin function _Z24__device_stub__crossOverPfS_Pi
	.type	_Z24__device_stub__crossOverPfS_Pi,@function
_Z24__device_stub__crossOverPfS_Pi:     # @_Z24__device_stub__crossOverPfS_Pi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9crossOverPfS_Pi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z24__device_stub__crossOverPfS_Pi, .Lfunc_end2-_Z24__device_stub__crossOverPfS_Pi
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__mutatePfS_Pi # -- Begin function _Z21__device_stub__mutatePfS_Pi
	.type	_Z21__device_stub__mutatePfS_Pi,@function
_Z21__device_stub__mutatePfS_Pi:        # @_Z21__device_stub__mutatePfS_Pi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6mutatePfS_Pi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z21__device_stub__mutatePfS_Pi, .Lfunc_end3-_Z21__device_stub__mutatePfS_Pi
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__shuffleGenePfS_S_Pi # -- Begin function _Z26__device_stub__shuffleGenePfS_S_Pi
	.type	_Z26__device_stub__shuffleGenePfS_S_Pi,@function
_Z26__device_stub__shuffleGenePfS_S_Pi: # @_Z26__device_stub__shuffleGenePfS_S_Pi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11shuffleGenePfS_S_Pi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z26__device_stub__shuffleGenePfS_S_Pi, .Lfunc_end4-_Z26__device_stub__shuffleGenePfS_S_Pi
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14computeFitnessPfS_S_Pi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19rearrangePopulationPfS_Pi, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9crossOverPfS_Pi, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6mutatePfS_Pi, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11shuffleGenePfS_S_Pi, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z14computeFitnessPfS_S_Pi,@object # @_Z14computeFitnessPfS_S_Pi
	.section	.rodata,"a",@progbits
	.globl	_Z14computeFitnessPfS_S_Pi
	.p2align	3, 0x0
_Z14computeFitnessPfS_S_Pi:
	.quad	_Z29__device_stub__computeFitnessPfS_S_Pi
	.size	_Z14computeFitnessPfS_S_Pi, 8

	.type	_Z19rearrangePopulationPfS_Pi,@object # @_Z19rearrangePopulationPfS_Pi
	.globl	_Z19rearrangePopulationPfS_Pi
	.p2align	3, 0x0
_Z19rearrangePopulationPfS_Pi:
	.quad	_Z34__device_stub__rearrangePopulationPfS_Pi
	.size	_Z19rearrangePopulationPfS_Pi, 8

	.type	_Z9crossOverPfS_Pi,@object      # @_Z9crossOverPfS_Pi
	.globl	_Z9crossOverPfS_Pi
	.p2align	3, 0x0
_Z9crossOverPfS_Pi:
	.quad	_Z24__device_stub__crossOverPfS_Pi
	.size	_Z9crossOverPfS_Pi, 8

	.type	_Z6mutatePfS_Pi,@object         # @_Z6mutatePfS_Pi
	.globl	_Z6mutatePfS_Pi
	.p2align	3, 0x0
_Z6mutatePfS_Pi:
	.quad	_Z21__device_stub__mutatePfS_Pi
	.size	_Z6mutatePfS_Pi, 8

	.type	_Z11shuffleGenePfS_S_Pi,@object # @_Z11shuffleGenePfS_S_Pi
	.globl	_Z11shuffleGenePfS_S_Pi
	.p2align	3, 0x0
_Z11shuffleGenePfS_S_Pi:
	.quad	_Z26__device_stub__shuffleGenePfS_S_Pi
	.size	_Z11shuffleGenePfS_S_Pi, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z14computeFitnessPfS_S_Pi"
	.size	.L__unnamed_1, 27

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z19rearrangePopulationPfS_Pi"
	.size	.L__unnamed_2, 30

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z9crossOverPfS_Pi"
	.size	.L__unnamed_3, 19

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z6mutatePfS_Pi"
	.size	.L__unnamed_4, 16

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z11shuffleGenePfS_S_Pi"
	.size	.L__unnamed_5, 24

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub__computeFitnessPfS_S_Pi
	.addrsig_sym _Z34__device_stub__rearrangePopulationPfS_Pi
	.addrsig_sym _Z24__device_stub__crossOverPfS_Pi
	.addrsig_sym _Z21__device_stub__mutatePfS_Pi
	.addrsig_sym _Z26__device_stub__shuffleGenePfS_S_Pi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z14computeFitnessPfS_S_Pi
	.addrsig_sym _Z19rearrangePopulationPfS_Pi
	.addrsig_sym _Z9crossOverPfS_Pi
	.addrsig_sym _Z6mutatePfS_Pi
	.addrsig_sym _Z11shuffleGenePfS_S_Pi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z14computeFitnessPfS_S_Pi ; -- Begin function _Z14computeFitnessPfS_S_Pi
	.globl	_Z14computeFitnessPfS_S_Pi
	.p2align	8
	.type	_Z14computeFitnessPfS_S_Pi,@function
_Z14computeFitnessPfS_S_Pi:             ; @_Z14computeFitnessPfS_S_Pi
; %bb.0:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s0, s[0:1], 0x2c
	s_waitcnt lgkmcnt(0)
	s_load_b32 s1, s[10:11], 0x4
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s15, s0, v[0:1]
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_ge_i32_e64 s1, v4
	s_cbranch_execz .LBB0_5
; %bb.1:
	v_mul_lo_u32 v0, v4, 6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v1, vcc_lo
	s_clause 0x1
	global_load_b128 v[0:3], v[5:6], off
	global_load_b64 v[5:6], v[5:6], off offset:16
	s_load_b32 s3, s[10:11], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s3, 1
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v8, v3, v1 :: v_dual_sub_f32 v7, v5, v0
	v_sub_f32_e32 v9, v2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v10, v6, v1 :: v_dual_mul_f32 v7, v8, v7
	v_fma_f32 v7, v9, v10, -v7
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0, v7
	v_cndmask_b32_e64 v7, v7, -v7, vcc_lo
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph.i
	v_dual_sub_f32 v10, v5, v2 :: v_dual_sub_f32 v11, v6, v3
	v_dual_sub_f32 v12, v0, v5 :: v_dual_sub_f32 v13, v1, v6
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	s_add_u32 s0, s4, -4
	s_addc_u32 s1, s5, -1
	s_add_i32 s3, s3, -1
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_dual_mul_f32 v14, 0.5, v7 :: v_dual_sub_f32 v15, s0, v0
	v_dual_sub_f32 v16, s1, v1 :: v_dual_sub_f32 v17, s0, v2
	v_dual_sub_f32 v18, s1, v3 :: v_dual_sub_f32 v19, s0, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v20, s1, v6 :: v_dual_mul_f32 v15, v8, v15
	v_mul_f32_e32 v17, v11, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v19, v13, v19
	v_fma_f32 v15, v9, v16, -v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v16, v10, v18, -v17
	v_fma_f32 v17, v12, v20, -v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_f32_e32 vcc_lo, 0, v15
	v_cmp_lt_f32_e64 s0, 0, v16
	v_cmp_gt_f32_e64 s2, 0, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_f32_e64 s1, 0, v17
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 vcc_lo, s1, s0
	v_cmp_gt_f32_e64 s0, 0, v17
	v_cndmask_b32_e32 v7, v7, v14, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_f32_e32 v14, 0.5, v7
	s_and_b32 s1, s2, vcc_lo
	s_and_b32 vcc_lo, s0, s1
	s_add_u32 s4, s4, 8
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e32 v7, v7, v14, vcc_lo
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s3, 0
	s_cbranch_scc1 .LBB0_3
.LBB0_4:                                ; %_Z7fitnessffffffPfi.exit
	v_cmp_lt_f32_e32 vcc_lo, 1.0, v0
	v_cmp_gt_f32_e64 s0, -1.0, v0
	v_cmp_lt_f32_e64 s1, 1.0, v1
	v_cmp_gt_f32_e64 s2, -1.0, v1
	v_cmp_lt_f32_e64 s3, 1.0, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	s_or_b32 s4, vcc_lo, s0
	v_cmp_gt_f32_e32 vcc_lo, -1.0, v2
	s_or_b32 s2, s1, s2
	v_cmp_lt_f32_e64 s0, 1.0, v3
	v_cmp_gt_f32_e64 s1, -1.0, v3
	s_or_b32 s2, s4, s2
	s_or_b32 s3, s3, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, 1.0, v5
	s_or_b32 s2, s3, s2
	s_or_b32 s1, s0, s1
	v_cmp_gt_f32_e64 s0, -1.0, v5
	v_ashrrev_i32_e32 v5, 31, v4
	s_or_b32 s3, s1, s2
	v_cmp_lt_f32_e64 s1, 1.0, v6
	v_cmp_gt_f32_e64 s2, -1.0, v6
	s_or_b32 s0, vcc_lo, s0
	v_lshlrev_b64 v[0:1], 2, v[4:5]
	s_or_b32 s0, s0, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, s1, s2
	s_or_b32 s0, s1, s0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_cndmask_b32_e64 v2, v7, 0, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_5:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14computeFitnessPfS_S_Pi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z14computeFitnessPfS_S_Pi, .Lfunc_end0-_Z14computeFitnessPfS_S_Pi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 624
; NumSgprs: 18
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z19rearrangePopulationPfS_Pi ; -- Begin function _Z19rearrangePopulationPfS_Pi
	.globl	_Z19rearrangePopulationPfS_Pi
	.p2align	8
	.type	_Z19rearrangePopulationPfS_Pi,@function
_Z19rearrangePopulationPfS_Pi:          ; @_Z19rearrangePopulationPfS_Pi
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b32 s5, s[0:1], 0x24
	s_waitcnt lgkmcnt(0)
	s_load_b32 s4, s[2:3], 0x4
	s_and_b32 s2, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s2, s4, 31
	s_add_i32 s2, s4, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_ashr_i32 s2, s2, 1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e32 vcc_lo, s2, v4
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB1_4
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_xad_u32 v0, v4, -1, s4
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s2, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s2, v5
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v6, vcc_lo
	s_clause 0x1
	global_load_b32 v5, v[0:1], off
	global_load_b32 v6, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v5, v6
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_4
; %bb.2:                                ; %.preheader
	v_mul_lo_u32 v4, v4, 6
	s_mul_i32 s4, s4, 6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v4
	v_sub_nc_u32_e32 v6, s4, v4
	v_lshlrev_b64 v[7:8], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s0, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v8, vcc_lo
	v_mov_b32_e32 v7, -6
.LBB1_3:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v6, v7
	v_add_co_u32 v7, s2, v7, 1
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_u32 v8, vcc_lo, s0, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
	global_load_b32 v10, v[4:5], off
	global_load_b32 v11, v[8:9], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[4:5], v11, off
	global_store_b32 v[8:9], v10, off
	s_clause 0x1
	global_load_b32 v8, v[2:3], off
	global_load_b32 v9, v[0:1], off
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_waitcnt vmcnt(1)
	global_store_b32 v[0:1], v8, off
	s_waitcnt vmcnt(0)
	global_store_b32 v[2:3], v9, off
	s_cbranch_vccnz .LBB1_3
.LBB1_4:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19rearrangePopulationPfS_Pi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z19rearrangePopulationPfS_Pi, .Lfunc_end1-_Z19rearrangePopulationPfS_Pi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 420
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2align	2                               ; -- Begin function _Z6randomffPf
	.type	_Z6randomffPf,@function
_Z6randomffPf:                          ; @_Z6randomffPf
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	flat_load_b64 v[2:3], v[2:3]
	v_cvt_f64_f32_e32 v[4:5], v1
	s_mov_b32 s0, 0x857f3062
	s_mov_b32 s1, 0x40538ecc
	v_cvt_f64_f32_e32 v[0:1], v0
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[4:5], v[4:5], s[0:1]
	s_mov_b32 s0, 0x9bfc756
	s_mov_b32 s1, 0x4029f664
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_f64 v[0:1], v[0:1], s[0:1]
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cvt_f64_f32_e32 v[6:7], v3
	v_cvt_f64_f32_e32 v[2:3], v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[4:5], v[4:5], v[6:7]
	v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v0, v[0:1]
	v_and_b32_e32 v1, 0x7fffffff, v0
	v_cmpx_ngt_f32_e64 0x48000000, |v0|
	s_xor_b32 s2, exec_lo, s1
	s_cbranch_execz .LBB2_2
; %bb.1:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v4, 0
	v_and_or_b32 v12, v1, s0, 0x800000
	v_lshrrev_b32_e32 v9, 23, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, 0xfe5163ab, v12, 0
	v_add_nc_u32_e32 v10, 0xffffff88, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v10
	v_mad_u64_u32 v[5:6], null, 0x3c439041, v12, v[3:4]
	v_cndmask_b32_e64 v11, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v3, v6
	v_add_nc_u32_e32 v11, v11, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[6:7], null, 0xdb629599, v12, v[3:4]
	v_cmp_lt_u32_e64 s0, 31, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v13, 0, 0xffffffe0, s0
	v_dual_mov_b32 v3, v7 :: v_dual_cndmask_b32 v2, v6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v13, v13, v11
	v_mad_u64_u32 v[7:8], null, 0xf534ddc0, v12, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v13
	v_mov_b32_e32 v3, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v7, v5, vcc_lo
	v_mad_u64_u32 v[8:9], null, 0xfc2757d1, v12, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v2, v5, v2, s0
	v_mov_b32_e32 v3, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, 0x4e441529, v12, v[3:4]
	v_mov_b32_e32 v3, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, 0xa2f9836e, v12, v[3:4]
	v_cndmask_b32_e64 v3, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v4, v9, v7 :: v_dual_add_nc_u32 v3, v3, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v10, v10, v8 :: v_dual_cndmask_b32 v9, v11, v9
	v_cndmask_b32_e32 v8, v8, v6, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v7, v10, v4, s0
	v_cndmask_b32_e64 v9, v9, v10, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v4, v4, v8, s0
	v_sub_nc_u32_e32 v10, 32, v3
	v_cndmask_b32_e64 v8, v8, v5, s0
	v_cndmask_b32_e64 v9, v9, v7, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v7, v7, v4, s1
	v_cndmask_b32_e64 v4, v4, v8, s1
	v_cndmask_b32_e64 v2, v8, v2, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v11, v9, v7, v10
	v_alignbit_b32 v6, v7, v4, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v3, v11, v9, vcc_lo
	v_alignbit_b32 v9, v4, v2, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v5, v6, v7, vcc_lo
	v_bfe_u32 v6, v3, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, v9, v4, vcc_lo
	v_alignbit_b32 v7, v3, v5, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v8, 0, v6
	v_alignbit_b32 v5, v5, v4, 30
	v_alignbit_b32 v2, v4, v2, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v7, v7, v8
	v_xor_b32_e32 v4, v5, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v2, v2, v8
	v_clz_i32_u32_e32 v9, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v9, 32, v9
	v_sub_nc_u32_e32 v5, 31, v9
	v_lshlrev_b32_e32 v11, 23, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v7, v7, v4, v5
	v_alignbit_b32 v2, v4, v2, v5
	v_lshrrev_b32_e32 v5, 29, v3
	v_alignbit_b32 v4, v7, v2, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v5, 31, v5
	v_lshrrev_b32_e32 v7, 9, v7
	v_clz_i32_u32_e32 v8, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v10, 0.5, v5
	v_min_u32_e32 v8, 32, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, v10, v11
	v_sub_nc_u32_e32 v12, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v2, v4, v2, v12
	v_or_b32_e32 v4, v7, v10
	v_add_lshl_u32 v7, v8, v9, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v2, 9, v2
	v_mul_f32_e32 v8, 0x3fc90fda, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v2, v7
	v_fma_f32 v7, 0x3fc90fda, v4, -v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, 0x33000000, v2
	v_fmamk_f32 v4, v4, 0x33a22168, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v2, v2, v5
	v_fmac_f32_e32 v4, 0x3fc90fda, v2
	v_lshrrev_b32_e32 v3, 30, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v2, v8, v4 :: v_dual_add_nc_u32 v3, v6, v3
.LBB2_2:                                ; %Flow
	s_and_not1_saveexec_b32 s0, s2
; %bb.3:
	v_mul_f32_e64 v2, 0x3f22f983, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v3, v2
	v_fma_f32 v2, 0xbfc90fda, v3, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v2, v3, 0xb3a22168, v2
	v_fmamk_f32 v2, v3, 0xa7c234c4, v2
	v_cvt_i32_f32_e32 v3, v3
; %bb.4:                                ; %_ZL4sinff.exit
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v4, v2, v2 :: v_dual_and_b32 v7, 1, v3
	s_mov_b32 s0, 0xb94c1982
	s_mov_b32 s1, 0x37d75334
	v_xor_b32_e32 v1, v1, v0
	v_fmaak_f32 v5, s0, v4, 0x3c0881c4
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
	v_lshlrev_b32_e32 v3, 30, v3
	s_delay_alu instid0(VALU_DEP_3)
	v_fmaak_f32 v5, v4, v5, 0xbe2aaa9d
	v_fmaak_f32 v6, s1, v4, 0xbab64f3b
	s_mov_b32 s0, 0x7332c7d3
	s_mov_b32 s1, 0x40e55dd1
	v_and_b32_e32 v3, 0x80000000, v3
	v_mul_f32_e32 v5, v4, v5
	v_fmaak_f32 v6, v4, v6, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v2, v2, v5
	v_fmaak_f32 v6, v4, v6, 0xbf000004
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, v4, v6, 1.0
	v_cndmask_b32_e32 v2, v4, v2, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor3_b32 v1, v1, v3, v2
	v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[0:1], v0
	v_mul_f64 v[0:1], v[0:1], s[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v0, v[0:1]
	v_floor_f32_e32 v1, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_f32_e32 v0, v0, v1
	s_setpc_b64 s[30:31]
.Lfunc_end2:
	.size	_Z6randomffPf, .Lfunc_end2-_Z6randomffPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 1108
; NumSgprs: 34
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
	.text
	.protected	_Z9crossOverPfS_Pi      ; -- Begin function _Z9crossOverPfS_Pi
	.globl	_Z9crossOverPfS_Pi
	.p2align	8
	.type	_Z9crossOverPfS_Pi,@function
_Z9crossOverPfS_Pi:                     ; @_Z9crossOverPfS_Pi
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b32 s4, s[0:1], 0x24
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_load_b32 s2, s[2:3], 0x4
	s_and_b32 s3, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
	v_lshlrev_b32_e32 v24, 1, v1
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, s3
	s_ashr_i32 s3, s2, 1
	s_mov_b32 s2, exec_lo
	v_cmpx_ge_i32_e64 s3, v24
	s_cbranch_execz .LBB3_3
; %bb.1:
	v_cvt_f64_i32_e32 v[2:3], s3
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mul_lo_u32 v25, v1, 12
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, _Z6randomffPf@rel32@lo+4
	s_addc_u32 s9, s9, _Z6randomffPf@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v26, 31, v25
	v_mul_f64 v[2:3], 0x3ff80000, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f64_e32 v0, v[2:3]
	v_lshlrev_b64 v[2:3], 2, v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v24, v0
	v_mul_lo_u32 v0, v0, 6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v22, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v23, vcc_lo, s5, v3, vcc_lo
	v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
	s_clause 0x1
	global_load_b64 v[18:19], v[0:1], off
	global_load_b64 v[20:21], v[22:23], off offset:24
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v0, v18 :: v_dual_mov_b32 v1, v21
	s_swappc_b64 s[30:31], s[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v14, v0 :: v_dual_mov_b32 v3, s7
	v_dual_mov_b32 v0, v19 :: v_dual_mov_b32 v1, v20
	v_mov_b32_e32 v2, s6
	s_swappc_b64 s[30:31], s[8:9]
	v_dual_mov_b32 v15, v0 :: v_dual_mov_b32 v2, s6
	v_dual_mov_b32 v0, v20 :: v_dual_mov_b32 v1, v19
	v_mov_b32_e32 v3, s7
	s_swappc_b64 s[30:31], s[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v16, v0 :: v_dual_mov_b32 v1, v21
	v_dual_mov_b32 v0, v19 :: v_dual_mov_b32 v3, s7
	v_mov_b32_e32 v2, s6
	s_swappc_b64 s[30:31], s[8:9]
	v_dual_mov_b32 v17, v0 :: v_dual_mov_b32 v0, v18
	v_dual_mov_b32 v1, v20 :: v_dual_mov_b32 v2, s6
	v_mov_b32_e32 v3, s7
	s_swappc_b64 s[30:31], s[8:9]
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mov_b32 v18, v0 :: v_dual_mov_b32 v1, v19
	v_dual_mov_b32 v0, v21 :: v_dual_mov_b32 v3, s7
	v_mov_b32_e32 v2, s6
	s_swappc_b64 s[30:31], s[8:9]
	v_ashrrev_i32_e32 v1, 1, v24
	v_add_nc_u32_e32 v3, 6, v25
	s_mov_b64 s[0:1], 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s3, v1
	v_mul_lo_u32 v1, v1, 6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
.LBB3_2:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v4, s0, v3
	s_cmp_eq_u32 s0, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 2
	global_load_b32 v8, v[4:5], off
	global_load_b32 v6, v[22:23], off
	v_cndmask_b32_e32 v4, v14, v15, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v4, v16, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 4
	v_cndmask_b32_e32 v4, v4, v17, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 5
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v4, v18, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s0, 6
	v_cndmask_b32_e32 v9, v4, v0, vcc_lo
	v_add_co_u32 v22, vcc_lo, v22, 4
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[4:5], v9
	v_add_f64 v[4:5], -v[4:5], 1.0
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v8, v9, v8
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[6:7], v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[8:9], v8
	v_fma_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_f64_e32 v4, v[4:5]
	global_store_b32 v[1:2], v4, off
	v_add_co_u32 v1, vcc_lo, v1, 4
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	s_cbranch_scc1 .LBB3_2
.LBB3_3:                                ; %.loopexit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9crossOverPfS_Pi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 27
		.amdhsa_next_free_sgpr 33
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z9crossOverPfS_Pi, .Lfunc_end3-_Z9crossOverPfS_Pi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 700
; NumSgprs: 35
; NumVgprs: 27
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 35
; NumVGPRsForWavesPerEU: 27
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z6mutatePfS_Pi         ; -- Begin function _Z6mutatePfS_Pi
	.globl	_Z6mutatePfS_Pi
	.p2align	8
	.type	_Z6mutatePfS_Pi,@function
_Z6mutatePfS_Pi:                        ; @_Z6mutatePfS_Pi
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b32 s4, s[0:1], 0x24
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_load_b32 s2, s[2:3], 0x4
	s_and_b32 s3, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[16:17], null, s15, s3, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s3, s3, 30
	s_add_i32 s3, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_ashr_i32 s3, s3, 2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmpx_ge_i32_e64 s3, v16
	s_cbranch_execz .LBB4_2
; %bb.1:
	s_lshr_b32 s4, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s2, s2, s4
	s_load_b128 s[4:7], s[0:1], 0x0
	s_ashr_i32 s2, s2, 1
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, _Z6randomffPf@rel32@lo+4
	s_addc_u32 s9, s9, _Z6randomffPf@rel32@hi+12
	v_add3_u32 v0, s2, s3, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v0, 6
	v_ashrrev_i32_e32 v1, 31, v0
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v3, s7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v17, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v18, vcc_lo, s5, v1, vcc_lo
	global_load_b64 v[14:15], v[17:18], off
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v1, v14
	v_mov_b32_e32 v0, v14
	s_swappc_b64 s[30:31], s[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[0:1], v0
	v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
	v_add_f64 v[0:1], v[0:1], -0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], 1.0
	v_cvt_f32_f64_e32 v19, v[0:1]
	v_dual_mov_b32 v0, v15 :: v_dual_mov_b32 v1, v14
	s_swappc_b64 s[30:31], s[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[0:1], v0
	v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
	v_add_f64 v[0:1], v[0:1], -0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], 1.0
	v_cvt_f32_f64_e32 v20, v[0:1]
	v_dual_mov_b32 v0, v14 :: v_dual_mov_b32 v1, v15
	s_swappc_b64 s[30:31], s[8:9]
	v_mul_lo_u32 v1, v16, 6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[7:8], v0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v5, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v2, vcc_lo
	s_clause 0x1
	global_load_b128 v[1:4], v[5:6], off
	global_load_b64 v[5:6], v[5:6], off offset:16
	v_add_f64 v[7:8], v[7:8], -0.5
	v_add_f64 v[7:8], v[7:8], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_cvt_f32_f64_e32 v7, v[7:8]
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v0, v1, v19
	v_dual_mul_f32 v1, v2, v19 :: v_dual_mul_f32 v2, v3, v20
	s_waitcnt vmcnt(0)
	v_dual_mul_f32 v3, v4, v20 :: v_dual_mul_f32 v4, v5, v7
	v_mul_f32_e32 v5, v6, v7
	s_clause 0x1
	global_store_b128 v[17:18], v[0:3], off
	global_store_b64 v[17:18], v[4:5], off offset:16
.LBB4_2:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6mutatePfS_Pi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 33
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z6mutatePfS_Pi, .Lfunc_end4-_Z6mutatePfS_Pi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 484
; NumSgprs: 35
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 35
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11shuffleGenePfS_S_Pi ; -- Begin function _Z11shuffleGenePfS_S_Pi
	.globl	_Z11shuffleGenePfS_S_Pi
	.p2align	8
	.type	_Z11shuffleGenePfS_S_Pi,@function
_Z11shuffleGenePfS_S_Pi:                ; @_Z11shuffleGenePfS_S_Pi
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x18
	s_load_b32 s4, s[0:1], 0x2c
	s_waitcnt lgkmcnt(0)
	s_load_b32 s2, s[2:3], 0x4
	s_and_b32 s3, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 31
	s_add_i32 s2, s2, s3
	s_mov_b32 s3, exec_lo
	s_ashr_i32 s2, s2, 1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmpx_ge_i32_e64 s2, v1
	s_cbranch_execz .LBB5_3
; %bb.1:
	v_cvt_f64_i32_e32 v[2:3], s2
	s_mov_b32 s4, 0x33333333
	s_mov_b32 s5, 0x40153333
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[2:3]
	v_div_scale_f64 v[10:11], vcc_lo, v[2:3], s[4:5], v[2:3]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_div_fixup_f64 v[2:3], v[4:5], s[4:5], v[2:3]
	s_add_i32 s4, s2, s3
	s_xor_b32 s3, s4, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_sub_i32 s4, 0, s3
	v_cvt_i32_f64_e32 v0, v[2:3]
	v_cvt_f32_u32_e32 v2, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, s4, v2
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mov_b64 s[0:1], 0
	v_mul_hi_u32 v3, v2, v3
	v_add_nc_u32_e32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v2, v3
	v_ashrrev_i32_e32 v4, 31, v0
	v_mul_lo_u32 v3, v1, 6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v4
	v_xor_b32_e32 v0, v0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v0, v2
	v_mul_lo_u32 v2, v2, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v2
	v_subrev_nc_u32_e32 v2, s3, v0
	v_cmp_le_u32_e32 vcc_lo, s3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	v_subrev_nc_u32_e32 v2, s3, v0
	v_cmp_le_u32_e32 vcc_lo, s3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	v_ashrrev_i32_e32 v2, 31, v1
	v_xor_b32_e32 v0, v0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v0, v0, v4
	v_ashrrev_i32_e32 v4, 31, v3
	v_add_nc_u32_e32 v5, s2, v0
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[9:10], 2, v[3:4]
	v_mul_lo_u32 v7, v5, 6
	v_ashrrev_i32_e32 v6, 31, v5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	v_lshlrev_b64 v[2:3], 2, v[5:6]
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_lshlrev_b64 v[4:5], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, s4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v10, vcc_lo
.LBB5_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, v4, s0
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v10, vcc_lo, v6, s0
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v7, vcc_lo
	s_add_u32 s0, s0, 4
	s_clause 0x1
	global_load_b32 v12, v[8:9], off
	global_load_b32 v13, v[10:11], off
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s0, 24
	s_waitcnt vmcnt(1)
	global_store_b32 v[10:11], v12, off
	s_waitcnt vmcnt(0)
	global_store_b32 v[8:9], v13, off
	s_clause 0x1
	global_load_b32 v8, v[2:3], off
	global_load_b32 v9, v[0:1], off
	s_waitcnt vmcnt(1)
	global_store_b32 v[0:1], v8, off
	s_waitcnt vmcnt(0)
	global_store_b32 v[2:3], v9, off
	s_cbranch_scc1 .LBB5_2
.LBB5_3:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11shuffleGenePfS_S_Pi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z11shuffleGenePfS_S_Pi, .Lfunc_end5-_Z11shuffleGenePfS_S_Pi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 688
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14computeFitnessPfS_S_Pi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14computeFitnessPfS_S_Pi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     21
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19rearrangePopulationPfS_Pi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19rearrangePopulationPfS_Pi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9crossOverPfS_Pi
    .private_segment_fixed_size: 0
    .sgpr_count:     35
    .sgpr_spill_count: 0
    .symbol:         _Z9crossOverPfS_Pi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     27
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6mutatePfS_Pi
    .private_segment_fixed_size: 0
    .sgpr_count:     35
    .sgpr_spill_count: 0
    .symbol:         _Z6mutatePfS_Pi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     21
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11shuffleGenePfS_S_Pi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11shuffleGenePfS_S_Pi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
