#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <assert.h>
#include <cuda.h>

#define u32 unsigned int
#define u64 unsigned long
#define uchar unsigned char
#define BLOCK_SIZE 64

#define CREATE_RAND_ARR(arr, size, min, max) \
do {                                         \
    time_t t;                                \
    srand((unsigned)time(&t));               \
    for (u32 i = 0; i < size; i++)           \
        arr[i] = rand() % max + min;         \
} while (0)                                  \

#define PRINT_ARR(arr, size)       \
do {                               \
    for (u32 i = 0; i < size; i++) \
        printf("%u, ", arr[i]);    \
    printf("\n");                  \
} while (0)                        \

/**
 * @ref https://stackoverflow.com/questions/5447570/cuda-atomic-operations-on-unsigned-chars
 */
__device__
uchar atomicUChatAdd(uchar* address, const uchar val)
{
    u64 long_address_modulo = (u64) address & 3;
    u32* base_address = (u32*) ((char*) address - long_address_modulo);
    u32 long_val = (u32) val << (8 * long_address_modulo);
    u32 long_old = atomicAdd(base_address, long_val);

    if (long_address_modulo == 3) {
        // the first 8 bits of long_val represent the char value,
        // hence the first 8 bits of long_old represent its previous value.
        return (char) (long_old >> 24);
    } 
    else {
        // bits that represent the char value within long_val
        unsigned int mask = 0x000000ff << (8 * long_address_modulo);
        unsigned int masked_old = long_old & mask;
        // isolate the bits that represent the char value within long_old, add the long_val to that,
        // then re-isolate by excluding bits that represent the char value
        unsigned int overflow = (masked_old + long_val) & ~mask;
        if (overflow) {
            atomicSub(base_address, overflow);
        }
        return (char) (masked_old >> 8 * long_address_modulo);
    }
}

__global__
void global_hist_kernel(const uchar* __restrict__ arr, 
                        const u32 arr_size, 
                        uchar* hist, 
                        const u32 hist_bins)
{
    u32 id_x = blockIdx.x * blockDim.x + threadIdx.x;
    if (id_x < arr_size) {
        if (arr[id_x] < hist_bins) {
            atomicUChatAdd(&hist[arr[id_x]], 1);
        }
    }
}

__global__
void shared_hist_kernel(const uchar* __restrict__ arr, 
                        const u32 arr_size, 
                        uchar* hist, 
                        const u32 hist_bins)
{
    extern __shared__ uchar shared_hist[];
    u32 id_x = blockIdx.x * blockDim.x + threadIdx.x;
    if (id_x < hist_bins) {
        shared_hist[id_x] = 0;
    }
    __syncthreads();
    if (id_x < arr_size) {
        if (arr[id_x] < hist_bins) {
            atomicUChatAdd(&shared_hist[arr[id_x]], 1);
        }
    }
    __syncthreads();
    for (u32 i = threadIdx.x; i < hist_bins; i += blockDim.x) {
        atomicUChatAdd(&hist[i], shared_hist[i]);
    }
}

void gpuGlobalHist(uchar* h_arr, const u32 arr_size, uchar* h_hist, const u32 hist_bins)
{
    uchar* d_arr;
    cudaMalloc((void**)&d_arr, arr_size * sizeof(uchar));
    cudaMemcpy(d_arr, h_arr, arr_size * sizeof(uchar), cudaMemcpyHostToDevice);

    uchar* d_hist;
    cudaMalloc((void**)&d_hist, hist_bins * sizeof(uchar));

    dim3 blocks = BLOCK_SIZE;
    dim3 grids = (arr_size + BLOCK_SIZE - 1) / BLOCK_SIZE;

    global_hist_kernel <<< grids, blocks >>> (d_arr, arr_size, d_hist, hist_bins);
    if (cudaSuccess != cudaGetLastError()) {
        printf("global_hist_kernel fault!\n");
    }

    cudaMemcpy(h_hist, d_hist, hist_bins * sizeof(uchar), cudaMemcpyDeviceToHost);
    cudaFree(d_arr);
    cudaFree(d_hist);
}

void gpuSharedHist(uchar* h_arr, const u32 arr_size, uchar* h_hist, const u32 hist_bins)
{
    uchar* d_arr;
    cudaMalloc((void**)&d_arr, arr_size * sizeof(uchar));
    cudaMemcpy(d_arr, h_arr, arr_size * sizeof(uchar), cudaMemcpyHostToDevice);

    uchar* d_hist;
    cudaMalloc((void**)&d_hist, hist_bins * sizeof(uchar));

    dim3 blocks = BLOCK_SIZE;
    dim3 grids = (arr_size + BLOCK_SIZE - 1) / BLOCK_SIZE;

    u32 shared_mem_size = hist_bins * sizeof(uchar);

    shared_hist_kernel <<< grids, blocks, shared_mem_size >>> (d_arr, arr_size, d_hist, hist_bins);
    if (cudaSuccess != cudaGetLastError()) {
        printf("shared_clac_hist_kernel fault!\n");
    }

    cudaMemcpy(h_hist, d_hist, hist_bins * sizeof(uchar), cudaMemcpyDeviceToHost);
    cudaFree(d_arr);
    cudaFree(d_hist);
}

void cpuHist(uchar* arr, const u32 arr_size, uchar* hist, const u32 hist_bins)
{
    for (u32 i = 0; i < arr_size; i++) {
        if (arr[i] < hist_bins) {
            hist[arr[i]]++;
        }
    }
}

int main()
{
    const u32 arr_size = 1000;
    const u32 hist_bins = 8;

    uchar* arr = (uchar*)malloc(arr_size * sizeof(uchar));
    CREATE_RAND_ARR(arr, arr_size, 0, 8);

    uchar* cpu_hist = (uchar*)malloc(hist_bins * sizeof(uchar));
    cpuHist(arr, arr_size, cpu_hist, hist_bins);
    printf("CPU hist:\n");
    PRINT_ARR(cpu_hist, hist_bins);

    uchar* gpu_global_hist = (uchar*)malloc(hist_bins * sizeof(uchar));
    gpuGlobalHist(arr, arr_size, gpu_global_hist, hist_bins);
    printf("GPU hist - use global memory:\n");
    PRINT_ARR(gpu_global_hist, hist_bins);

    uchar* gpu_shared_hist = (uchar*)malloc(hist_bins * sizeof(uchar));
    gpuSharedHist(arr, arr_size, gpu_shared_hist, hist_bins);
    printf("GPU hist - use shared memory:\n");
    PRINT_ARR(gpu_shared_hist, hist_bins);

    free(arr);
    free(cpu_hist);
    free(gpu_global_hist);
    free(gpu_shared_hist);
    
    return 0;
}
	.file	"tmpxft_002c45e4_00000000-6_main.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2034:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z14atomicUChatAddPhh
	.type	_Z14atomicUChatAddPhh, @function
_Z14atomicUChatAddPhh:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z14atomicUChatAddPhh, .-_Z14atomicUChatAddPhh
	.globl	_Z7cpuHistPhjS_j
	.type	_Z7cpuHistPhjS_j, @function
_Z7cpuHistPhjS_j:
.LFB2030:
	.cfi_startproc
	endbr64
	xorl	%r8d, %r8d
.L5:
	cmpl	%esi, %r8d
	jnb	.L9
	movzbl	(%rdi,%r8), %r9d
	cmpl	%ecx, %r9d
	jnb	.L6
	incb	(%rdx,%r9)
.L6:
	incq	%r8
	jmp	.L5
.L9:
	ret
	.cfi_endproc
.LFE2030:
	.size	_Z7cpuHistPhjS_j, .-_Z7cpuHistPhjS_j
	.globl	_Z43__device_stub__Z18global_hist_kernelPKhjPhjPKhjPhj
	.type	_Z43__device_stub__Z18global_hist_kernelPKhjPhjPKhjPhj, @function
_Z43__device_stub__Z18global_hist_kernelPKhjPhjPKhjPhj:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movl	%esi, 12(%rsp)
	leaq	52(%rsp), %rsi
	movq	%rdx, (%rsp)
	leaq	24(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	32(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	40(%rsp), %rdi
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movq	%rsp, %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	32(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z18global_hist_kernelPKhjPhj(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 160
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L10:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z43__device_stub__Z18global_hist_kernelPKhjPhjPKhjPhj, .-_Z43__device_stub__Z18global_hist_kernelPKhjPhjPKhjPhj
	.globl	_Z18global_hist_kernelPKhjPhj
	.type	_Z18global_hist_kernelPKhjPhj, @function
_Z18global_hist_kernelPKhjPhj:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z18global_hist_kernelPKhjPhjPKhjPhj
	.cfi_endproc
.LFE2057:
	.size	_Z18global_hist_kernelPKhjPhj, .-_Z18global_hist_kernelPKhjPhj
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"global_hist_kernel fault!\n"
	.text
	.globl	_Z13gpuGlobalHistPhjS_j
	.type	_Z13gpuGlobalHistPhjS_j, @function
_Z13gpuGlobalHistPhjS_j:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	%esi, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%r14, %rsi
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rdx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$48, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movq	%r14, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	movl	%ebp, %r13d
	call	cudaMemcpy@PLT
	leaq	8(%rsp), %rdi
	movq	%r13, %rsi
	call	cudaMalloc@PLT
	leal	63(%r14), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	shrl	$6, %eax
	movl	$67108865, %edx
	movl	$1, %ecx
	movl	%eax, 28(%rsp)
	salq	$6, %rdx
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	28(%rsp), %rdi
	movl	36(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	movq	8(%rsp), %rdx
	movq	(%rsp), %rdi
	movl	%ebp, %ecx
	movl	%r14d, %esi
	call	_Z43__device_stub__Z18global_hist_kernelPKhjPhjPKhjPhj
.L16:
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L17
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L17:
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	%r13, %rdx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$48, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z13gpuGlobalHistPhjS_j, .-_Z13gpuGlobalHistPhjS_j
	.globl	_Z43__device_stub__Z18shared_hist_kernelPKhjPhjPKhjPhj
	.type	_Z43__device_stub__Z18shared_hist_kernelPKhjPhjPKhjPhj, @function
_Z43__device_stub__Z18shared_hist_kernelPKhjPhjPKhjPhj:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movl	%esi, 12(%rsp)
	leaq	52(%rsp), %rsi
	movq	%rdx, (%rsp)
	leaq	24(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	32(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	40(%rsp), %rdi
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movq	%rsp, %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	32(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z18shared_hist_kernelPKhjPhj(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 160
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L23:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z43__device_stub__Z18shared_hist_kernelPKhjPhjPKhjPhj, .-_Z43__device_stub__Z18shared_hist_kernelPKhjPhjPKhjPhj
	.globl	_Z18shared_hist_kernelPKhjPhj
	.type	_Z18shared_hist_kernelPKhjPhj, @function
_Z18shared_hist_kernelPKhjPhj:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z18shared_hist_kernelPKhjPhjPKhjPhj
	.cfi_endproc
.LFE2059:
	.size	_Z18shared_hist_kernelPKhjPhj, .-_Z18shared_hist_kernelPKhjPhj
	.section	.rodata.str1.1
.LC1:
	.string	"shared_clac_hist_kernel fault!\n"
	.text
	.globl	_Z13gpuSharedHistPhjS_j
	.type	_Z13gpuSharedHistPhjS_j, @function
_Z13gpuSharedHistPhjS_j:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	%esi, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%r14, %rsi
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rdx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$48, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movq	%r14, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	movl	%ebp, %r13d
	call	cudaMemcpy@PLT
	leaq	8(%rsp), %rdi
	movq	%r13, %rsi
	call	cudaMalloc@PLT
	leal	63(%r14), %eax
	xorl	%r9d, %r9d
	movq	%r13, %r8
	shrl	$6, %eax
	movl	$67108865, %edx
	movl	$1, %ecx
	movl	%eax, 28(%rsp)
	salq	$6, %rdx
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	28(%rsp), %rdi
	movl	36(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	movq	8(%rsp), %rdx
	movq	(%rsp), %rdi
	movl	%ebp, %ecx
	movl	%r14d, %esi
	call	_Z43__device_stub__Z18shared_hist_kernelPKhjPhjPKhjPhj
.L29:
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L30
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L30:
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	%r13, %rdx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$48, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z13gpuSharedHistPhjS_j, .-_Z13gpuSharedHistPhjS_j
	.section	.rodata.str1.1
.LC2:
	.string	"CPU hist:\n"
.LC3:
	.string	"%u, "
.LC4:
	.string	"\n"
.LC5:
	.string	"GPU hist - use global memory:\n"
.LC6:
	.string	"GPU hist - use shared memory:\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$1000, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	$8, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movq	%rsp, %rdi
	movq	%rax, %rbx
	call	time@PLT
	movl	%eax, %edi
	call	srand@PLT
.L37:
	call	rand@PLT
	cltd
	idivl	%r12d
	movb	%dl, (%rbx,%rbp)
	incq	%rbp
	cmpq	$1000, %rbp
	jne	.L37
	movl	$8, %edi
	xorl	%ebp, %ebp
	leaq	.LC3(%rip), %r15
	call	malloc@PLT
	movl	$8, %ecx
	movl	$1000, %esi
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movq	%rax, %r13
	xorl	%eax, %eax
	call	_Z7cpuHistPhjS_j
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
.L38:
	movzbl	0(%r13,%rbp), %edx
	movq	%r15, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbp
	call	__printf_chk@PLT
	cmpq	$8, %rbp
	jne	.L38
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%ebp, %ebp
	call	__printf_chk@PLT
	movl	$8, %edi
	call	malloc@PLT
	movl	$8, %ecx
	movl	$1000, %esi
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movq	%rax, %r12
	call	_Z13gpuGlobalHistPhjS_j
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L39:
	movzbl	(%r12,%rbp), %edx
	movq	%r15, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbp
	call	__printf_chk@PLT
	cmpq	$8, %rbp
	jne	.L39
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%r14d, %r14d
	call	__printf_chk@PLT
	movl	$8, %edi
	call	malloc@PLT
	movl	$8, %ecx
	movl	$1000, %esi
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movq	%rax, %rbp
	call	_Z13gpuSharedHistPhjS_j
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L40:
	movzbl	0(%rbp,%r14), %edx
	movq	%r15, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%r14
	call	__printf_chk@PLT
	cmpq	$8, %r14
	jne	.L40
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	8(%rsp), %rax
	subq	%fs:40, %rax
	je	.L41
	call	__stack_chk_fail@PLT
.L41:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2031:
	.size	main, .-main
	.section	.rodata.str1.1
.LC7:
	.string	"_Z18shared_hist_kernelPKhjPhj"
.LC8:
	.string	"_Z18global_hist_kernelPKhjPhj"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z18shared_hist_kernelPKhjPhj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z18global_hist_kernelPKhjPhj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2061:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <assert.h>
#include <hip/hip_runtime.h>

#define u32 unsigned int
#define u64 unsigned long
#define uchar unsigned char
#define BLOCK_SIZE 64

#define CREATE_RAND_ARR(arr, size, min, max) \
do {                                         \
    time_t t;                                \
    srand((unsigned)time(&t));               \
    for (u32 i = 0; i < size; i++)           \
        arr[i] = rand() % max + min;         \
} while (0)                                  \

#define PRINT_ARR(arr, size)       \
do {                               \
    for (u32 i = 0; i < size; i++) \
        printf("%u, ", arr[i]);    \
    printf("\n");                  \
} while (0)                        \

/**
 * @ref https://stackoverflow.com/questions/5447570/cuda-atomic-operations-on-unsigned-chars
 */
__device__
uchar atomicUChatAdd(uchar* address, const uchar val)
{
    u64 long_address_modulo = (u64) address & 3;
    u32* base_address = (u32*) ((char*) address - long_address_modulo);
    u32 long_val = (u32) val << (8 * long_address_modulo);
    u32 long_old = atomicAdd(base_address, long_val);

    if (long_address_modulo == 3) {
        // the first 8 bits of long_val represent the char value,
        // hence the first 8 bits of long_old represent its previous value.
        return (char) (long_old >> 24);
    } 
    else {
        // bits that represent the char value within long_val
        unsigned int mask = 0x000000ff << (8 * long_address_modulo);
        unsigned int masked_old = long_old & mask;
        // isolate the bits that represent the char value within long_old, add the long_val to that,
        // then re-isolate by excluding bits that represent the char value
        unsigned int overflow = (masked_old + long_val) & ~mask;
        if (overflow) {
            atomicSub(base_address, overflow);
        }
        return (char) (masked_old >> 8 * long_address_modulo);
    }
}

__global__
void global_hist_kernel(const uchar* __restrict__ arr, 
                        const u32 arr_size, 
                        uchar* hist, 
                        const u32 hist_bins)
{
    u32 id_x = blockIdx.x * blockDim.x + threadIdx.x;
    if (id_x < arr_size) {
        if (arr[id_x] < hist_bins) {
            atomicUChatAdd(&hist[arr[id_x]], 1);
        }
    }
}

__global__
void shared_hist_kernel(const uchar* __restrict__ arr, 
                        const u32 arr_size, 
                        uchar* hist, 
                        const u32 hist_bins)
{
    extern __shared__ uchar shared_hist[];
    u32 id_x = blockIdx.x * blockDim.x + threadIdx.x;
    if (id_x < hist_bins) {
        shared_hist[id_x] = 0;
    }
    __syncthreads();
    if (id_x < arr_size) {
        if (arr[id_x] < hist_bins) {
            atomicUChatAdd(&shared_hist[arr[id_x]], 1);
        }
    }
    __syncthreads();
    for (u32 i = threadIdx.x; i < hist_bins; i += blockDim.x) {
        atomicUChatAdd(&hist[i], shared_hist[i]);
    }
}

void gpuGlobalHist(uchar* h_arr, const u32 arr_size, uchar* h_hist, const u32 hist_bins)
{
    uchar* d_arr;
    hipMalloc((void**)&d_arr, arr_size * sizeof(uchar));
    hipMemcpy(d_arr, h_arr, arr_size * sizeof(uchar), hipMemcpyHostToDevice);

    uchar* d_hist;
    hipMalloc((void**)&d_hist, hist_bins * sizeof(uchar));

    dim3 blocks = BLOCK_SIZE;
    dim3 grids = (arr_size + BLOCK_SIZE - 1) / BLOCK_SIZE;

    global_hist_kernel <<< grids, blocks >>> (d_arr, arr_size, d_hist, hist_bins);
    if (hipSuccess != hipGetLastError()) {
        printf("global_hist_kernel fault!\n");
    }

    hipMemcpy(h_hist, d_hist, hist_bins * sizeof(uchar), hipMemcpyDeviceToHost);
    hipFree(d_arr);
    hipFree(d_hist);
}

void gpuSharedHist(uchar* h_arr, const u32 arr_size, uchar* h_hist, const u32 hist_bins)
{
    uchar* d_arr;
    hipMalloc((void**)&d_arr, arr_size * sizeof(uchar));
    hipMemcpy(d_arr, h_arr, arr_size * sizeof(uchar), hipMemcpyHostToDevice);

    uchar* d_hist;
    hipMalloc((void**)&d_hist, hist_bins * sizeof(uchar));

    dim3 blocks = BLOCK_SIZE;
    dim3 grids = (arr_size + BLOCK_SIZE - 1) / BLOCK_SIZE;

    u32 shared_mem_size = hist_bins * sizeof(uchar);

    shared_hist_kernel <<< grids, blocks, shared_mem_size >>> (d_arr, arr_size, d_hist, hist_bins);
    if (hipSuccess != hipGetLastError()) {
        printf("shared_clac_hist_kernel fault!\n");
    }

    hipMemcpy(h_hist, d_hist, hist_bins * sizeof(uchar), hipMemcpyDeviceToHost);
    hipFree(d_arr);
    hipFree(d_hist);
}

void cpuHist(uchar* arr, const u32 arr_size, uchar* hist, const u32 hist_bins)
{
    for (u32 i = 0; i < arr_size; i++) {
        if (arr[i] < hist_bins) {
            hist[arr[i]]++;
        }
    }
}

int main()
{
    const u32 arr_size = 1000;
    const u32 hist_bins = 8;

    uchar* arr = (uchar*)malloc(arr_size * sizeof(uchar));
    CREATE_RAND_ARR(arr, arr_size, 0, 8);

    uchar* cpu_hist = (uchar*)malloc(hist_bins * sizeof(uchar));
    cpuHist(arr, arr_size, cpu_hist, hist_bins);
    printf("CPU hist:\n");
    PRINT_ARR(cpu_hist, hist_bins);

    uchar* gpu_global_hist = (uchar*)malloc(hist_bins * sizeof(uchar));
    gpuGlobalHist(arr, arr_size, gpu_global_hist, hist_bins);
    printf("GPU hist - use global memory:\n");
    PRINT_ARR(gpu_global_hist, hist_bins);

    uchar* gpu_shared_hist = (uchar*)malloc(hist_bins * sizeof(uchar));
    gpuSharedHist(arr, arr_size, gpu_shared_hist, hist_bins);
    printf("GPU hist - use shared memory:\n");
    PRINT_ARR(gpu_shared_hist, hist_bins);

    free(arr);
    free(cpu_hist);
    free(gpu_global_hist);
    free(gpu_shared_hist);
    
    return 0;
}
	.text
	.file	"main.hip"
	.globl	_Z33__device_stub__global_hist_kernelPKhjPhj # -- Begin function _Z33__device_stub__global_hist_kernelPKhjPhj
	.type	_Z33__device_stub__global_hist_kernelPKhjPhj,@function
_Z33__device_stub__global_hist_kernelPKhjPhj: # @_Z33__device_stub__global_hist_kernelPKhjPhj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18global_hist_kernelPKhjPhj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__global_hist_kernelPKhjPhj, .Lfunc_end0-_Z33__device_stub__global_hist_kernelPKhjPhj
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__shared_hist_kernelPKhjPhj # -- Begin function _Z33__device_stub__shared_hist_kernelPKhjPhj
	.type	_Z33__device_stub__shared_hist_kernelPKhjPhj,@function
_Z33__device_stub__shared_hist_kernelPKhjPhj: # @_Z33__device_stub__shared_hist_kernelPKhjPhj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18shared_hist_kernelPKhjPhj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z33__device_stub__shared_hist_kernelPKhjPhj, .Lfunc_end1-_Z33__device_stub__shared_hist_kernelPKhjPhj
	.cfi_endproc
                                        # -- End function
	.globl	_Z13gpuGlobalHistPhjS_j         # -- Begin function _Z13gpuGlobalHistPhjS_j
	.type	_Z13gpuGlobalHistPhjS_j,@function
_Z13gpuGlobalHistPhjS_j:                # @_Z13gpuGlobalHistPhjS_j
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %ebp
	movq	%rdx, %rbx
	movl	%esi, %r15d
	movq	%rdi, %r14
	movl	%esi, %r12d
	leaq	16(%rsp), %r13
	movq	%r13, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	(%r13), %rdi
	movq	%r14, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%ebp, %r14d
	leaq	8(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	leal	63(%r15), %edi
	shrl	$6, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$64, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rdx
	movl	%r15d, %esi
	movl	%ebp, %ecx
	callq	_Z33__device_stub__global_hist_kernelPKhjPhj
.LBB2_2:
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB2_4
# %bb.3:
	movl	$.Lstr, %edi
	callq	puts@PLT
.LBB2_4:
	movq	8(%rsp), %rsi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z13gpuGlobalHistPhjS_j, .Lfunc_end2-_Z13gpuGlobalHistPhjS_j
	.cfi_endproc
                                        # -- End function
	.globl	_Z13gpuSharedHistPhjS_j         # -- Begin function _Z13gpuSharedHistPhjS_j
	.type	_Z13gpuSharedHistPhjS_j,@function
_Z13gpuSharedHistPhjS_j:                # @_Z13gpuSharedHistPhjS_j
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %ebp
	movq	%rdx, %rbx
	movl	%esi, %r15d
	movq	%rdi, %r14
	movl	%esi, %r12d
	leaq	16(%rsp), %r13
	movq	%r13, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	(%r13), %rdi
	movq	%r14, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%ebp, %r14d
	leaq	8(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	leal	63(%r15), %edi
	shrl	$6, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$64, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	movq	%r14, %r8
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_2
# %bb.1:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rdx
	movl	%r15d, %esi
	movl	%ebp, %ecx
	callq	_Z33__device_stub__shared_hist_kernelPKhjPhj
.LBB3_2:
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB3_4
# %bb.3:
	movl	$.Lstr.1, %edi
	callq	puts@PLT
.LBB3_4:
	movq	8(%rsp), %rsi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z13gpuSharedHistPhjS_j, .Lfunc_end3-_Z13gpuSharedHistPhjS_j
	.cfi_endproc
                                        # -- End function
	.globl	_Z7cpuHistPhjS_j                # -- Begin function _Z7cpuHistPhjS_j
	.type	_Z7cpuHistPhjS_j,@function
_Z7cpuHistPhjS_j:                       # @_Z7cpuHistPhjS_j
	.cfi_startproc
# %bb.0:
	testl	%esi, %esi
	je	.LBB4_5
# %bb.1:                                # %.lr.ph.preheader
	movl	%esi, %eax
	xorl	%esi, %esi
.LBB4_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movzbl	(%rdi,%rsi), %r8d
	cmpl	%ecx, %r8d
	jae	.LBB4_4
# %bb.3:                                #   in Loop: Header=BB4_2 Depth=1
	incb	(%rdx,%r8)
.LBB4_4:                                #   in Loop: Header=BB4_2 Depth=1
	incq	%rsi
	cmpq	%rsi, %rax
	jne	.LBB4_2
.LBB4_5:                                # %._crit_edge
	retq
.Lfunc_end4:
	.size	_Z7cpuHistPhjS_j, .Lfunc_end4-_Z7cpuHistPhjS_j
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$16, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$1000, %edi                     # imm = 0x3E8
	callq	malloc
	movq	%rax, %rbx
	leaq	8(%rsp), %rdi
	callq	time
	movl	%eax, %edi
	callq	srand
	xorl	%r14d, %r14d
.LBB5_1:                                # =>This Inner Loop Header: Depth=1
	callq	rand
                                        # kill: def $eax killed $eax def $rax
	leal	7(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	andl	$248, %ecx
	subl	%ecx, %eax
	movb	%al, (%rbx,%r14)
	incq	%r14
	cmpq	$1000, %r14                     # imm = 0x3E8
	jne	.LBB5_1
# %bb.2:
	movl	$8, %edi
	callq	malloc
	movq	%rax, %r14
	xorl	%eax, %eax
.LBB5_3:                                # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	movzbl	(%rbx,%rax), %ecx
	cmpq	$7, %rcx
	ja	.LBB5_5
# %bb.4:                                #   in Loop: Header=BB5_3 Depth=1
	incb	(%r14,%rcx)
.LBB5_5:                                #   in Loop: Header=BB5_3 Depth=1
	incq	%rax
	cmpq	$1000, %rax                     # imm = 0x3E8
	jne	.LBB5_3
# %bb.6:                                # %_Z7cpuHistPhjS_j.exit
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	xorl	%r15d, %r15d
.LBB5_7:                                # =>This Inner Loop Header: Depth=1
	movzbl	(%r14,%r15), %esi
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r15
	cmpq	$8, %r15
	jne	.LBB5_7
# %bb.8:
	movl	$10, %edi
	callq	putchar@PLT
	movl	$8, %edi
	callq	malloc
	movq	%rax, %r15
	movq	%rbx, %rdi
	movl	$1000, %esi                     # imm = 0x3E8
	movq	%rax, %rdx
	movl	$8, %ecx
	callq	_Z13gpuGlobalHistPhjS_j
	movl	$.Lstr.3, %edi
	callq	puts@PLT
	xorl	%r12d, %r12d
.LBB5_9:                                # =>This Inner Loop Header: Depth=1
	movzbl	(%r15,%r12), %esi
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r12
	cmpq	$8, %r12
	jne	.LBB5_9
# %bb.10:
	movl	$10, %edi
	callq	putchar@PLT
	movl	$8, %edi
	callq	malloc
	movq	%rax, %r12
	movq	%rbx, %rdi
	movl	$1000, %esi                     # imm = 0x3E8
	movq	%rax, %rdx
	movl	$8, %ecx
	callq	_Z13gpuSharedHistPhjS_j
	movl	$.Lstr.4, %edi
	callq	puts@PLT
	xorl	%r13d, %r13d
.LBB5_11:                               # =>This Inner Loop Header: Depth=1
	movzbl	(%r12,%r13), %esi
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r13
	cmpq	$8, %r13
	jne	.LBB5_11
# %bb.12:
	movl	$10, %edi
	callq	putchar@PLT
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	%r12, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$16, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18global_hist_kernelPKhjPhj, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18shared_hist_kernelPKhjPhj, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18global_hist_kernelPKhjPhj,@object # @_Z18global_hist_kernelPKhjPhj
	.section	.rodata,"a",@progbits
	.globl	_Z18global_hist_kernelPKhjPhj
	.p2align	3, 0x0
_Z18global_hist_kernelPKhjPhj:
	.quad	_Z33__device_stub__global_hist_kernelPKhjPhj
	.size	_Z18global_hist_kernelPKhjPhj, 8

	.type	_Z18shared_hist_kernelPKhjPhj,@object # @_Z18shared_hist_kernelPKhjPhj
	.globl	_Z18shared_hist_kernelPKhjPhj
	.p2align	3, 0x0
_Z18shared_hist_kernelPKhjPhj:
	.quad	_Z33__device_stub__shared_hist_kernelPKhjPhj
	.size	_Z18shared_hist_kernelPKhjPhj, 8

	.type	.L.str.3,@object                # @.str.3
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.3:
	.asciz	"%u, "
	.size	.L.str.3, 5

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z18global_hist_kernelPKhjPhj"
	.size	.L__unnamed_1, 30

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z18shared_hist_kernelPKhjPhj"
	.size	.L__unnamed_2, 30

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"global_hist_kernel fault!"
	.size	.Lstr, 26

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"shared_clac_hist_kernel fault!"
	.size	.Lstr.1, 31

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"CPU hist:"
	.size	.Lstr.2, 10

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"GPU hist - use global memory:"
	.size	.Lstr.3, 30

	.type	.Lstr.4,@object                 # @str.4
.Lstr.4:
	.asciz	"GPU hist - use shared memory:"
	.size	.Lstr.4, 30

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__global_hist_kernelPKhjPhj
	.addrsig_sym _Z33__device_stub__shared_hist_kernelPKhjPhj
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18global_hist_kernelPKhjPhj
	.addrsig_sym _Z18shared_hist_kernelPKhjPhj
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18global_hist_kernelPKhjPhj ; -- Begin function _Z18global_hist_kernelPKhjPhj
	.globl	_Z18global_hist_kernelPKhjPhj
	.p2align	8
	.type	_Z18global_hist_kernelPKhjPhj,@function
_Z18global_hist_kernelPKhjPhj:          ; @_Z18global_hist_kernelPKhjPhj
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b32 s3, s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s3, v1
	s_cbranch_execz .LBB0_5
; %bb.1:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b32 s4, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	global_load_u8 v0, v1, s[2:3]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 0xff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s4, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_5
; %bb.2:
	s_load_b64 s[0:1], s[0:1], 0x10
	v_mov_b32_e32 v6, 0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, s0, s0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v1, null, s1, 0, s0
	v_and_b32_e32 v5, 3, v0
	v_and_b32_e32 v0, -4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v2, 3, v5
	v_cmp_ne_u64_e32 vcc_lo, 3, v[5:6]
	v_lshlrev_b32_e64 v3, v2, 1
	global_atomic_add_u32 v4, v[0:1], v3, off glc
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_5
; %bb.3:
	v_lshlrev_b32_e64 v2, v2, 0xff
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v4, v2
	v_not_b32_e32 v2, v2
	v_add_nc_u32_e32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, v3, v2
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_5
; %bb.4:
	v_sub_nc_u32_e32 v2, 0, v2
	global_atomic_add_u32 v[0:1], v2, off
.LBB0_5:                                ; %_Z14atomicUChatAddPhh.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18global_hist_kernelPKhjPhj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18global_hist_kernelPKhjPhj, .Lfunc_end0-_Z18global_hist_kernelPKhjPhj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 276
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z18shared_hist_kernelPKhjPhj ; -- Begin function _Z18shared_hist_kernelPKhjPhj
	.globl	_Z18shared_hist_kernelPKhjPhj
	.p2align	8
	.type	_Z18shared_hist_kernelPKhjPhj,@function
_Z18shared_hist_kernelPKhjPhj:          ; @_Z18shared_hist_kernelPKhjPhj
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x2c
	s_load_b32 s2, s[0:1], 0x18
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
	v_cmpx_gt_u32_e64 s2, v1
	s_cbranch_execz .LBB1_2
; %bb.1:
	v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, 0, v1
	ds_store_b8 v2, v3
.LBB1_2:
	s_or_b32 exec_lo, exec_lo, s4
	s_load_b32 s4, s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_gt_u32_e32 vcc_lo, s4, v1
	s_and_saveexec_b32 s4, vcc_lo
	s_cbranch_execz .LBB1_7
; %bb.3:
	s_load_b64 s[6:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	global_load_u8 v1, v1, s[6:7]
	s_waitcnt vmcnt(0)
	v_cmp_gt_u32_e32 vcc_lo, s2, v1
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_7
; %bb.4:
	v_add_nc_u32_e32 v3, 0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v1, 0, v3, vcc_lo
	v_and_b32_e32 v1, 3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v4, 3, v1
	v_sub_nc_u32_e32 v2, v3, v1
	v_lshlrev_b32_e64 v5, v4, 1
	ds_add_rtn_u32 v6, v2, v5
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u64_e32 vcc_lo, 3, v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_7
; %bb.5:
	v_lshlrev_b32_e64 v2, v4, 0xff
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v6, v2
	v_not_b32_e32 v2, v2
	v_add_nc_u32_e32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, v4, v2
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_7
; %bb.6:
	v_sub_nc_u32_e32 v1, 0, v1
	v_sub_nc_u32_e32 v2, 0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v3, v1
	ds_add_u32 v1, v2
.LBB1_7:                                ; %_Z14atomicUChatAddPhh.exit
	s_or_b32 exec_lo, exec_lo, s4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_u32_e64 s2, v0
	s_cbranch_execz .LBB1_13
; %bb.8:                                ; %.lr.ph.preheader
	s_load_b64 s[0:1], s[0:1], 0x10
	v_mov_b32_e32 v2, 0
	s_mov_b32 s4, 0
.LBB1_9:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v1, 0, v0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, s5, s0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v4, null, s1, 0, s5
	ds_load_u8 v6, v1
	v_and_b32_e32 v1, 3, v3
	v_and_b32_e32 v3, -4, v3
	s_mov_b32 s5, exec_lo
	v_lshlrev_b32_e32 v5, 3, v1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v6, v5, v6
	global_atomic_add_u32 v7, v[3:4], v6, off glc
	v_cmpx_ne_u64_e32 3, v[1:2]
	s_cbranch_execz .LBB1_12
; %bb.10:                               ;   in Loop: Header=BB1_9 Depth=1
	v_lshlrev_b32_e64 v1, v5, 0xff
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_b32_e32 v5, v7, v1
	v_not_b32_e32 v1, v1
	v_add_nc_u32_e32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v1, v5, v1
	v_cmp_ne_u32_e32 vcc_lo, 0, v1
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_12
; %bb.11:                               ;   in Loop: Header=BB1_9 Depth=1
	v_sub_nc_u32_e32 v1, 0, v1
	global_atomic_add_u32 v[3:4], v1, off
.LBB1_12:                               ; %_Z14atomicUChatAddPhh.exit22
                                        ;   in Loop: Header=BB1_9 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v0, s3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s2, v0
	s_or_b32 s4, vcc_lo, s4
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_9
.LBB1_13:                               ; %Flow29
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18shared_hist_kernelPKhjPhj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z18shared_hist_kernelPKhjPhj, .Lfunc_end1-_Z18shared_hist_kernelPKhjPhj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 532
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym shared_hist
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .actual_access:  read_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18global_hist_kernelPKhjPhj
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18global_hist_kernelPKhjPhj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .actual_access:  read_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         152
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18shared_hist_kernelPKhjPhj
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18shared_hist_kernelPKhjPhj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
