// Stolen from Seb

/*#include <cstdint>*/
#include <stdint.h>

#define WARP_SIZE 32

// macro function
#define min(a,b) (a > b ? b : a);

// -------------------------------------------------------------------
// helper functions
// -------------------------------------------------------------------

// Get largest memory address that is aligned to a warp worth of floats
// and smaller than x.
__forceinline__ __device__ uintptr_t getBlockBeginning(void const * x)
{
  return (uintptr_t)(x) & (~((uintptr_t)(WARP_SIZE*sizeof(float)) - 1)) ;
}

__forceinline__ __device__ void blockReduce2(volatile float * mdata,
                                             volatile float * sdata,
                                             unsigned int tid,
                                             unsigned int blockSize,
                                             unsigned int maxDataSize)
{
  __syncthreads();
  if (blockSize >= 1024 && maxDataSize + WARP_SIZE >=512) { if (tid < 512) { sdata[tid] += sdata[tid + 512]; mdata[tid] += mdata[tid + 512]; } __syncthreads(); }
  if (blockSize >= 512  && maxDataSize + WARP_SIZE >=256) { if (tid < 256) { sdata[tid] += sdata[tid + 256]; mdata[tid] += mdata[tid + 256]; } __syncthreads(); }
  if (blockSize >= 256  && maxDataSize + WARP_SIZE >=128) { if (tid < 128) { sdata[tid] += sdata[tid + 128]; mdata[tid] += mdata[tid + 128]; } __syncthreads(); }
  if (blockSize >= 128  && maxDataSize + WARP_SIZE >=64)  { if (tid <  64) { sdata[tid] += sdata[tid + 64];  mdata[tid] += mdata[tid + 64];  } __syncthreads(); }
  if (tid < 32) {
    if (blockSize >=  64) { sdata[tid] += sdata[tid + 32]; mdata[tid] += mdata[tid + 32]; }
    if (blockSize >=  32) { sdata[tid] += sdata[tid + 16]; mdata[tid] += mdata[tid + 16]; }
    if (blockSize >=  16) { sdata[tid] += sdata[tid +  8]; mdata[tid] += mdata[tid +  8]; }
    if (blockSize >=   8) { sdata[tid] += sdata[tid +  4]; mdata[tid] += mdata[tid +  4]; }
    if (blockSize >=   4) { sdata[tid] += sdata[tid +  2]; mdata[tid] += mdata[tid +  2]; }
    if (blockSize >=   2) { sdata[tid] += sdata[tid +  1]; mdata[tid] += mdata[tid +  1]; }
  }
}



// This kernel accumulates means and variances for the data.
// Each block of thread sums over one or more data planes, resulting
// in an array accumulator[] of dimension numBlocksPerChannel x 2*numChannels.
//
// If each thread block scans all the images, then numBlocksPerChannel = 1.
// However, for efficiency different thread blocks do different
// subset of images, resulting in numBlocksPerChannel partial results to be summed
// later by a second kernel.
//
// The first part accumulator[:,0:numChannels-1] stores the data for the mean
// and the second part accumulator[:,numChannels,2*numChannels-1] the data
// for the sigmas.
//
// This function uses the sliding-window summing technique described
// above. It requires
//
//    2*sizeof(float)*blockSize
//
// bytes of shared scratch memory to hold to hold partial sums for
// means and sigmas.
__global__ void accumulate_moments_partial(float * accumulator,
                                           float const * data,
                                           int planeArea,
                                           int numPlanes,
                                           int numChannels,
                                           int numBlocksPerChannel)
{
  int tid = threadIdx.x ;
  int plane = blockIdx.x ;
  int blockSize = blockDim.x ;
  int planeStride = gridDim.x ;
  int channel = blockIdx.x % numChannels ;

  extern __shared__ float s [] ;
  /*SharedMemory<float> smem ;*/
  /*float* s = smem.getPointer() ;*/
  float* mdata = s ;
  float* sdata = mdata + blockSize ;

  mdata[tid] = 0 ;
  sdata[tid] = 0 ;

  while (plane < numPlanes) {
    float const * planeBegin = data + plane * planeArea ;
    float const * planeEnd = planeBegin + planeArea ;
    float const * block = (float const*) getBlockBeginning(planeBegin) + tid ;
    while (block < planeEnd) {
      if (block >= planeBegin) {
        float x = *block ;
        mdata[tid] += x ;
        sdata[tid] += x * x ;
      }
      block += blockSize ;
    }
    plane += planeStride ;
  }

  blockReduce2(sdata, mdata, tid, blockSize, planeArea) ;

  if (tid == 0) {
    int chunk = blockIdx.x / numChannels ;
    int i = chunk + channel * numBlocksPerChannel ;
    accumulator[i] = mdata[0];
    accumulator[i + gridDim.x] = sdata[0];
  }
}


	.file	"tmpxft_00396bcd_00000000-6_accumulate_moments_partial.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2012:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2012:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z53__device_stub__Z26accumulate_moments_partialPfPKfiiiiPfPKfiiii
	.type	_Z53__device_stub__Z26accumulate_moments_partialPfPKfiiiiPfPKfiiii, @function
_Z53__device_stub__Z26accumulate_moments_partialPfPKfiiiiPfPKfiiii:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z26accumulate_moments_partialPfPKfiiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 192
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z53__device_stub__Z26accumulate_moments_partialPfPKfiiiiPfPKfiiii, .-_Z53__device_stub__Z26accumulate_moments_partialPfPKfiiiiPfPKfiiii
	.globl	_Z26accumulate_moments_partialPfPKfiiii
	.type	_Z26accumulate_moments_partialPfPKfiiii, @function
_Z26accumulate_moments_partialPfPKfiiii:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z26accumulate_moments_partialPfPKfiiiiPfPKfiiii
	.cfi_endproc
.LFE2035:
	.size	_Z26accumulate_moments_partialPfPKfiiii, .-_Z26accumulate_moments_partialPfPKfiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z26accumulate_moments_partialPfPKfiiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2037:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z26accumulate_moments_partialPfPKfiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2037:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// Stolen from Seb

/*#include <cstdint>*/

#include <hip/hip_runtime.h>
#include <stdint.h>

#define WARP_SIZE 32

// macro function
#define min(a,b) (a > b ? b : a);

// -------------------------------------------------------------------
// helper functions
// -------------------------------------------------------------------

// Get largest memory address that is aligned to a warp worth of floats
// and smaller than x.
__forceinline__ __device__ uintptr_t getBlockBeginning(void const * x)
{
  return (uintptr_t)(x) & (~((uintptr_t)(WARP_SIZE*sizeof(float)) - 1)) ;
}

__forceinline__ __device__ void blockReduce2(volatile float * mdata,
                                             volatile float * sdata,
                                             unsigned int tid,
                                             unsigned int blockSize,
                                             unsigned int maxDataSize)
{
  __syncthreads();
  if (blockSize >= 1024 && maxDataSize + WARP_SIZE >=512) { if (tid < 512) { sdata[tid] += sdata[tid + 512]; mdata[tid] += mdata[tid + 512]; } __syncthreads(); }
  if (blockSize >= 512  && maxDataSize + WARP_SIZE >=256) { if (tid < 256) { sdata[tid] += sdata[tid + 256]; mdata[tid] += mdata[tid + 256]; } __syncthreads(); }
  if (blockSize >= 256  && maxDataSize + WARP_SIZE >=128) { if (tid < 128) { sdata[tid] += sdata[tid + 128]; mdata[tid] += mdata[tid + 128]; } __syncthreads(); }
  if (blockSize >= 128  && maxDataSize + WARP_SIZE >=64)  { if (tid <  64) { sdata[tid] += sdata[tid + 64];  mdata[tid] += mdata[tid + 64];  } __syncthreads(); }
  if (tid < 32) {
    if (blockSize >=  64) { sdata[tid] += sdata[tid + 32]; mdata[tid] += mdata[tid + 32]; }
    if (blockSize >=  32) { sdata[tid] += sdata[tid + 16]; mdata[tid] += mdata[tid + 16]; }
    if (blockSize >=  16) { sdata[tid] += sdata[tid +  8]; mdata[tid] += mdata[tid +  8]; }
    if (blockSize >=   8) { sdata[tid] += sdata[tid +  4]; mdata[tid] += mdata[tid +  4]; }
    if (blockSize >=   4) { sdata[tid] += sdata[tid +  2]; mdata[tid] += mdata[tid +  2]; }
    if (blockSize >=   2) { sdata[tid] += sdata[tid +  1]; mdata[tid] += mdata[tid +  1]; }
  }
}



// This kernel accumulates means and variances for the data.
// Each block of thread sums over one or more data planes, resulting
// in an array accumulator[] of dimension numBlocksPerChannel x 2*numChannels.
//
// If each thread block scans all the images, then numBlocksPerChannel = 1.
// However, for efficiency different thread blocks do different
// subset of images, resulting in numBlocksPerChannel partial results to be summed
// later by a second kernel.
//
// The first part accumulator[:,0:numChannels-1] stores the data for the mean
// and the second part accumulator[:,numChannels,2*numChannels-1] the data
// for the sigmas.
//
// This function uses the sliding-window summing technique described
// above. It requires
//
//    2*sizeof(float)*blockSize
//
// bytes of shared scratch memory to hold to hold partial sums for
// means and sigmas.
__global__ void accumulate_moments_partial(float * accumulator,
                                           float const * data,
                                           int planeArea,
                                           int numPlanes,
                                           int numChannels,
                                           int numBlocksPerChannel)
{
  int tid = threadIdx.x ;
  int plane = blockIdx.x ;
  int blockSize = blockDim.x ;
  int planeStride = gridDim.x ;
  int channel = blockIdx.x % numChannels ;

  extern __shared__ float s [] ;
  /*SharedMemory<float> smem ;*/
  /*float* s = smem.getPointer() ;*/
  float* mdata = s ;
  float* sdata = mdata + blockSize ;

  mdata[tid] = 0 ;
  sdata[tid] = 0 ;

  while (plane < numPlanes) {
    float const * planeBegin = data + plane * planeArea ;
    float const * planeEnd = planeBegin + planeArea ;
    float const * block = (float const*) getBlockBeginning(planeBegin) + tid ;
    while (block < planeEnd) {
      if (block >= planeBegin) {
        float x = *block ;
        mdata[tid] += x ;
        sdata[tid] += x * x ;
      }
      block += blockSize ;
    }
    plane += planeStride ;
  }

  blockReduce2(sdata, mdata, tid, blockSize, planeArea) ;

  if (tid == 0) {
    int chunk = blockIdx.x / numChannels ;
    int i = chunk + channel * numBlocksPerChannel ;
    accumulator[i] = mdata[0];
    accumulator[i + gridDim.x] = sdata[0];
  }
}


	.text
	.file	"accumulate_moments_partial.hip"
	.globl	_Z41__device_stub__accumulate_moments_partialPfPKfiiii # -- Begin function _Z41__device_stub__accumulate_moments_partialPfPKfiiii
	.type	_Z41__device_stub__accumulate_moments_partialPfPKfiiii,@function
_Z41__device_stub__accumulate_moments_partialPfPKfiiii: # @_Z41__device_stub__accumulate_moments_partialPfPKfiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26accumulate_moments_partialPfPKfiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z41__device_stub__accumulate_moments_partialPfPKfiiii, .Lfunc_end0-_Z41__device_stub__accumulate_moments_partialPfPKfiiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26accumulate_moments_partialPfPKfiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z26accumulate_moments_partialPfPKfiiii,@object # @_Z26accumulate_moments_partialPfPKfiiii
	.section	.rodata,"a",@progbits
	.globl	_Z26accumulate_moments_partialPfPKfiiii
	.p2align	3, 0x0
_Z26accumulate_moments_partialPfPKfiiii:
	.quad	_Z41__device_stub__accumulate_moments_partialPfPKfiiii
	.size	_Z26accumulate_moments_partialPfPKfiiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z26accumulate_moments_partialPfPKfiiii"
	.size	.L__unnamed_1, 40

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z41__device_stub__accumulate_moments_partialPfPKfiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z26accumulate_moments_partialPfPKfiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z26accumulate_moments_partialPfPKfiiii ; -- Begin function _Z26accumulate_moments_partialPfPKfiiii
	.globl	_Z26accumulate_moments_partialPfPKfiiii
	.p2align	8
	.type	_Z26accumulate_moments_partialPfPKfiiii,@function
_Z26accumulate_moments_partialPfPKfiiii: ; @_Z26accumulate_moments_partialPfPKfiiii
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s14, s[0:1], 0x20
	v_lshlrev_b32_e32 v5, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v4, 0, v5
	s_waitcnt lgkmcnt(0)
	s_and_b32 s17, s2, 0xffff
	s_lshl_b32 s18, s17, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s16, s18, 0
	s_cmp_ge_i32 s15, s9
	v_add_nc_u32_e32 v3, s16, v5
	ds_store_b32 v4, v1
	ds_store_b32 v3, v1
	s_cbranch_scc1 .LBB0_8
; %bb.1:                                ; %.lr.ph53
	s_ashr_i32 s1, s8, 31
	s_mov_b32 s0, s8
	s_mov_b32 s19, s15
	s_lshl_b64 s[0:1], s[0:1], 2
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
	s_mul_i32 s2, s19, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s3, s2, 31
	s_lshl_b64 s[2:3], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_add_u32 s2, s6, s2
	s_addc_u32 s3, s7, s3
	s_add_u32 s12, s2, s0
	s_addc_u32 s13, s3, s1
	s_and_b32 s20, s2, 0xffffff80
	v_add_co_u32 v1, s20, s20, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, null, s3, 0, s20
	s_mov_b32 s20, exec_lo
	v_cmpx_gt_u64_e64 s[12:13], v[1:2]
	s_cbranch_execz .LBB0_7
; %bb.3:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s21, 0
.LBB0_4:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_mov_b32 s22, exec_lo
	v_cmpx_le_u64_e64 s[2:3], v[1:2]
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=2
	flat_load_b32 v6, v[1:2]
	ds_load_b32 v7, v4
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v7, v6, v7
	ds_store_b32 v4, v7
	ds_load_b32 v7, v3
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v7, v6, v6
	ds_store_b32 v3, v7
.LBB0_6:                                ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	v_add_co_u32 v1, vcc_lo, v1, s18
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u64_e32 vcc_lo, s[12:13], v[1:2]
	s_or_b32 s21, vcc_lo, s21
	s_and_not1_b32 exec_lo, exec_lo, s21
	s_cbranch_execnz .LBB0_4
.LBB0_7:                                ; %Flow78
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
	s_add_i32 s19, s19, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s19, s9
	s_cbranch_scc1 .LBB0_2
.LBB0_8:                                ; %._crit_edge54
	s_cmpk_lt_u32 s17, 0x400
	s_waitcnt lgkmcnt(0)
	s_cselect_b32 s0, -1, 0
	s_add_i32 s1, s8, 0xfffffe20
	s_barrier
	s_cmp_gt_u32 s1, 0xfffffdff
	buffer_gl0_inv
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s1, s0
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_12
; %bb.9:
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e32 0x200, v0
	s_cbranch_execz .LBB0_11
; %bb.10:
	v_lshl_or_b32 v7, v0, 2, 0x800
	v_cmp_ne_u32_e64 s0, -1, v4
	s_mov_b64 s[2:3], src_shared_base
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, 0, v7
	v_cndmask_b32_e64 v2, 0, s3, s0
	v_add_nc_u32_e32 v7, s16, v7
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	v_cndmask_b32_e32 v5, 0, v1, vcc_lo
	v_cndmask_b32_e64 v6, 0, s3, vcc_lo
	v_cndmask_b32_e64 v1, 0, v4, s0
	v_cmp_ne_u32_e32 vcc_lo, -1, v7
	v_cmp_ne_u32_e64 s0, -1, v3
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v8, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cndmask_b32_e64 v6, 0, s3, s0
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v9, v5, v8
	v_cndmask_b32_e64 v8, 0, s3, vcc_lo
	v_cndmask_b32_e64 v5, 0, v3, s0
	flat_store_b32 v[1:2], v9 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[7:8] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v2, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	flat_store_b32 v[5:6], v1 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_11:
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB0_12:
	s_cmpk_lt_u32 s17, 0x200
	s_cselect_b32 s0, -1, 0
	s_add_i32 s1, s8, 0xffffff20
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_gt_u32 s1, 0xfffffeff
	s_cselect_b32 s1, -1, 0
	s_or_b32 s0, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_16
; %bb.13:
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e32 0x100, v0
	s_cbranch_execz .LBB0_15
; %bb.14:
	v_lshl_or_b32 v7, v0, 2, 0x400
	v_cmp_ne_u32_e64 s0, -1, v4
	s_mov_b64 s[2:3], src_shared_base
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, 0, v7
	v_cndmask_b32_e64 v2, 0, s3, s0
	v_add_nc_u32_e32 v7, s16, v7
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	v_cndmask_b32_e32 v5, 0, v1, vcc_lo
	v_cndmask_b32_e64 v6, 0, s3, vcc_lo
	v_cndmask_b32_e64 v1, 0, v4, s0
	v_cmp_ne_u32_e32 vcc_lo, -1, v7
	v_cmp_ne_u32_e64 s0, -1, v3
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v8, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cndmask_b32_e64 v6, 0, s3, s0
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v9, v5, v8
	v_cndmask_b32_e64 v8, 0, s3, vcc_lo
	v_cndmask_b32_e64 v5, 0, v3, s0
	flat_store_b32 v[1:2], v9 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[7:8] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v2, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	flat_store_b32 v[5:6], v1 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_15:
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB0_16:
	s_cmpk_lt_u32 s17, 0x100
	s_cselect_b32 s0, -1, 0
	s_add_i32 s1, s8, 0xffffffa0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_gt_u32 s1, 0xffffff7f
	s_cselect_b32 s1, -1, 0
	s_or_b32 s0, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_20
; %bb.17:
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB0_19
; %bb.18:
	v_lshl_or_b32 v7, v0, 2, 0x200
	v_cmp_ne_u32_e64 s0, -1, v4
	s_mov_b64 s[2:3], src_shared_base
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, 0, v7
	v_cndmask_b32_e64 v2, 0, s3, s0
	v_add_nc_u32_e32 v7, s16, v7
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	v_cndmask_b32_e32 v5, 0, v1, vcc_lo
	v_cndmask_b32_e64 v6, 0, s3, vcc_lo
	v_cndmask_b32_e64 v1, 0, v4, s0
	v_cmp_ne_u32_e32 vcc_lo, -1, v7
	v_cmp_ne_u32_e64 s0, -1, v3
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v8, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cndmask_b32_e64 v6, 0, s3, s0
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v9, v5, v8
	v_cndmask_b32_e64 v8, 0, s3, vcc_lo
	v_cndmask_b32_e64 v5, 0, v3, s0
	flat_store_b32 v[1:2], v9 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[7:8] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v2, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	flat_store_b32 v[5:6], v1 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_19:
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB0_20:
	s_cmpk_lt_u32 s17, 0x80
	s_cselect_b32 s0, -1, 0
	s_sub_i32 s1, s8, 32
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_gt_u32 s1, 0xffffffbf
	s_cselect_b32 s1, -1, 0
	s_or_b32 s0, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_24
; %bb.21:
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB0_23
; %bb.22:
	v_lshl_or_b32 v7, v0, 2, 0x100
	v_cmp_ne_u32_e64 s0, -1, v4
	s_mov_b64 s[2:3], src_shared_base
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, 0, v7
	v_cndmask_b32_e64 v2, 0, s3, s0
	v_add_nc_u32_e32 v7, s16, v7
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	v_cndmask_b32_e32 v5, 0, v1, vcc_lo
	v_cndmask_b32_e64 v6, 0, s3, vcc_lo
	v_cndmask_b32_e64 v1, 0, v4, s0
	v_cmp_ne_u32_e32 vcc_lo, -1, v7
	v_cmp_ne_u32_e64 s0, -1, v3
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v8, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cndmask_b32_e64 v6, 0, s3, s0
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v9, v5, v8
	v_cndmask_b32_e64 v8, 0, s3, vcc_lo
	v_cndmask_b32_e64 v5, 0, v3, s0
	flat_store_b32 v[1:2], v9 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[7:8] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v2, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	flat_store_b32 v[5:6], v1 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_23:
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB0_24:
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB0_37
; %bb.25:
	v_cmp_ne_u32_e64 s0, -1, v4
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	s_cmp_lt_u32 s17, 64
	s_cbranch_scc1 .LBB0_27
; %bb.26:
	v_lshl_or_b32 v7, v0, 2, 0x80
	s_mov_b64 s[6:7], src_shared_base
	v_cndmask_b32_e64 v1, 0, v4, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, 0, v7
	v_add_nc_u32_e32 v7, s16, v7
	v_cmp_ne_u32_e64 s1, -1, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v5, 0, v2, s1
	v_cndmask_b32_e64 v6, 0, s7, s1
	v_cndmask_b32_e64 v2, 0, s7, s0
	v_cmp_ne_u32_e64 s0, -1, v7
	flat_load_b32 v6, v[5:6] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v8, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e32 v5, 0, v3, vcc_lo
	v_cndmask_b32_e64 v7, 0, v7, s0
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v9, v6, v8
	v_cndmask_b32_e64 v8, 0, s7, s0
	v_cndmask_b32_e64 v6, 0, s7, vcc_lo
	flat_store_b32 v[1:2], v9 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[7:8] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v2, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	flat_store_b32 v[5:6], v1 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_27:
	s_cmp_lt_u32 s17, 32
	s_cbranch_scc1 .LBB0_29
; %bb.28:
	v_add_nc_u32_e32 v1, 64, v4
	s_mov_b64 s[0:1], src_shared_base
	v_cmp_ne_u32_e64 s0, -1, v4
	v_add_nc_u32_e32 v7, 64, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	v_cndmask_b32_e64 v2, 0, s1, s0
	v_cndmask_b32_e32 v5, 0, v1, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	v_cndmask_b32_e64 v1, 0, v4, s0
	v_cmp_ne_u32_e32 vcc_lo, -1, v7
	v_cmp_ne_u32_e64 s0, -1, v3
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v8, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, s0
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v9, v5, v8
	v_cndmask_b32_e64 v8, 0, s1, vcc_lo
	v_cndmask_b32_e64 v5, 0, v3, s0
	flat_store_b32 v[1:2], v9 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[7:8] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v2, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	flat_store_b32 v[5:6], v1 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_29:
	s_cmp_lt_u32 s17, 16
	s_cbranch_scc1 .LBB0_31
; %bb.30:
	v_add_nc_u32_e32 v1, 32, v4
	s_mov_b64 s[0:1], src_shared_base
	v_cmp_ne_u32_e64 s0, -1, v4
	v_add_nc_u32_e32 v7, 32, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	v_cndmask_b32_e64 v2, 0, s1, s0
	v_cndmask_b32_e32 v5, 0, v1, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	v_cndmask_b32_e64 v1, 0, v4, s0
	v_cmp_ne_u32_e32 vcc_lo, -1, v7
	v_cmp_ne_u32_e64 s0, -1, v3
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v8, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, s0
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v9, v5, v8
	v_cndmask_b32_e64 v8, 0, s1, vcc_lo
	v_cndmask_b32_e64 v5, 0, v3, s0
	flat_store_b32 v[1:2], v9 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[7:8] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v2, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	flat_store_b32 v[5:6], v1 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_31:
	s_cmp_lt_u32 s17, 8
	s_cbranch_scc1 .LBB0_33
; %bb.32:
	v_add_nc_u32_e32 v1, 16, v4
	s_mov_b64 s[0:1], src_shared_base
	v_cmp_ne_u32_e64 s0, -1, v4
	v_add_nc_u32_e32 v7, 16, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	v_cndmask_b32_e64 v2, 0, s1, s0
	v_cndmask_b32_e32 v5, 0, v1, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	v_cndmask_b32_e64 v1, 0, v4, s0
	v_cmp_ne_u32_e32 vcc_lo, -1, v7
	v_cmp_ne_u32_e64 s0, -1, v3
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v8, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, s0
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v9, v5, v8
	v_cndmask_b32_e64 v8, 0, s1, vcc_lo
	v_cndmask_b32_e64 v5, 0, v3, s0
	flat_store_b32 v[1:2], v9 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[7:8] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v2, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	flat_store_b32 v[5:6], v1 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_33:
	s_cmp_lt_u32 s17, 4
	s_cbranch_scc1 .LBB0_35
; %bb.34:
	v_add_nc_u32_e32 v1, 8, v4
	s_mov_b64 s[0:1], src_shared_base
	v_cmp_ne_u32_e64 s0, -1, v4
	v_add_nc_u32_e32 v7, 8, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	v_cndmask_b32_e64 v2, 0, s1, s0
	v_cndmask_b32_e32 v5, 0, v1, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	v_cndmask_b32_e64 v1, 0, v4, s0
	v_cmp_ne_u32_e32 vcc_lo, -1, v7
	v_cmp_ne_u32_e64 s0, -1, v3
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v8, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, s0
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v9, v5, v8
	v_cndmask_b32_e64 v8, 0, s1, vcc_lo
	v_cndmask_b32_e64 v5, 0, v3, s0
	flat_store_b32 v[1:2], v9 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[7:8] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v2, v[5:6] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	flat_store_b32 v[5:6], v1 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_35:
	s_cmp_lt_u32 s17, 2
	s_cbranch_scc1 .LBB0_37
; %bb.36:
	v_add_nc_u32_e32 v1, 4, v4
	s_mov_b64 s[0:1], src_shared_base
	v_cmp_ne_u32_e64 s0, -1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	v_cndmask_b32_e64 v2, 0, s1, s0
	v_cndmask_b32_e32 v5, 0, v1, vcc_lo
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	v_cndmask_b32_e64 v1, 0, v4, s0
	v_cmp_ne_u32_e64 s0, -1, v3
	flat_load_b32 v6, v[5:6] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v7, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, 4, v3
	v_cndmask_b32_e64 v4, 0, s1, s0
	v_cndmask_b32_e64 v3, 0, v3, s0
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v7, v6, v7
	v_cndmask_b32_e64 v6, 0, s1, vcc_lo
	flat_store_b32 v[1:2], v7 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[5:6] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v2, v[3:4] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	flat_store_b32 v[3:4], v1 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_37:                               ; %Flow72
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_39
; %bb.38:
	v_cvt_f32_u32_e32 v0, s10
	s_sub_i32 s1, 0, s10
	v_mov_b32_e32 v1, s16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_readfirstlane_b32 s0, v0
	v_mov_b32_e32 v0, 0
	ds_load_b32 v2, v0
	ds_load_b32 v1, v1
	s_mul_i32 s1, s1, s0
	s_mul_hi_u32 s1, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s1
	s_mul_hi_u32 s0, s15, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s0, s10
	s_add_i32 s2, s0, 1
	s_sub_i32 s1, s15, s1
	s_sub_i32 s3, s1, s10
	s_cmp_ge_u32 s1, s10
	s_cselect_b32 s0, s2, s0
	s_cselect_b32 s1, s3, s1
	s_add_i32 s2, s0, 1
	s_cmp_ge_u32 s1, s10
	s_cselect_b32 s0, s2, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s0, s10
	s_sub_i32 s1, s15, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s1, s11
	s_add_i32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s1, s0, 31
	s_lshl_b64 s[2:3], s[0:1], 2
	s_mov_b32 s1, 0
	s_add_u32 s2, s4, s2
	s_addc_u32 s3, s5, s3
	s_add_i32 s0, s0, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[0:1], 2
	s_add_u32 s0, s4, s0
	s_addc_u32 s1, s5, s1
	s_waitcnt lgkmcnt(1)
	global_store_b32 v0, v2, s[2:3]
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB0_39:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26accumulate_moments_partialPfPKfiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 23
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z26accumulate_moments_partialPfPKfiiii, .Lfunc_end0-_Z26accumulate_moments_partialPfPKfiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2876
; NumSgprs: 25
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 25
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym s
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         152
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z26accumulate_moments_partialPfPKfiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     25
    .sgpr_spill_count: 0
    .symbol:         _Z26accumulate_moments_partialPfPKfiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
