/*******************************************************************************
* PROGRAM: canny_edge_detector
* FILE: non_maximal_supp.cu 
* PURPOSE: Apply non maximal suppression.
* NAME: Vuong Pham-Duy
*       Faculty of Computer Science and Technology
*       Ho Chi Minh University of Technology, Viet Nam
*       vuongpd95@gmail.com
* DATE: 11/10/2016
*******************************************************************************/
#include "cuda_runtime.h"
#include "device_launch_parameters.h"

#define _USE_MATH_DEFINES
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>

#define NOEDGE 255
#define POSSIBLE_EDGE 128
#define EDGE 0
#define VERBOSE 1

__global__ void non_max_supp_kernel(int rows, int cols, int blockSize,
	short int *d_magnitude, short int *d_delta_x, short int *d_delta_y, unsigned char *d_nms);

#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
void gpuAssert(cudaError_t code, const char *file, int line, bool abort = true);
/*******************************************************************************
* PROCEDURE: non_maximal_supp
* PURPOSE: perform non-maximal suppression
* NAME: Vuong Pham-duy
* DATE: 10/11/2016
*******************************************************************************/
void non_maximal_supp(int rows, int cols, int blockSize, int gridSize,
	short int **d_magnitude, short int **d_delta_x, short int **d_delta_y, unsigned char **d_nms)
{
	/****************************************************************************
	* Perform non-maximal suppression.
	****************************************************************************/
	if (VERBOSE) printf("Doing the non-maximal suppression.\n");
	gpuErrchk(cudaMemset((*d_nms), 0, rows * cols * sizeof(unsigned char)));
	non_max_supp_kernel<<<gridSize, blockSize>>>(rows, cols, blockSize, (*d_magnitude), (*d_delta_x), (*d_delta_y), (*d_nms));
}
/*******************************************************************************
* PROCEDURE: non_max_supp_kernel
* PURPOSE: This routine applies non-maximal suppression to the magnitude of
* every pixel of the gradient image
* NAME: Vuong Pham-duy
* DATE: 10/11/2016
*******************************************************************************/
__global__ void non_max_supp_kernel(int rows, int cols, int blockSize,
	short int *d_magnitude, short int *d_delta_x, short int *d_delta_y, unsigned char *d_nms)
{
	/* This thread process the number img_idx element of image */
	int img_idx = blockIdx.x * blockSize + threadIdx.x;
	if (img_idx >= (rows * cols)) return;
	int r = img_idx / cols;		 /* row position of the pixel, range [0, rows - 1] */
	int c = img_idx - r * cols;  /* col position of the pixel, range [0, cols - 1] */
	if ((r != rows - 1) && (r != 0) && (c != 0) && (c != cols - 1))
	{
		short m00;
		m00 = d_magnitude[img_idx];
		if (m00 == 0) d_nms[img_idx] = (unsigned char)NOEDGE;
		else
		{
			short gx, gy, z1, z2;
			float mag1, mag2, xperp, yperp;
			gx = d_delta_x[img_idx];
			gy = d_delta_y[img_idx];
			xperp = -gx / ((float)m00);
			yperp = gy / ((float)m00);
			if (gx >= 0){
				if (gy >= 0){
					if (gx >= gy)
					{
						/* 111 */
						/* Left point */
						z1 = d_magnitude[img_idx - 1]; 
						z2 = d_magnitude[img_idx - cols - 1];

						mag1 = (m00 - z1)*xperp + (z2 - z1)*yperp;

						/* Right point */
						z1 = d_magnitude[img_idx + 1];
						z2 = d_magnitude[img_idx + cols + 1];

						mag2 = (m00 - z1)*xperp + (z2 - z1)*yperp;
					}
					else
					{
						/* 110 */
						/* Left point */
						z1 = d_magnitude[img_idx - cols];
						z2 = d_magnitude[img_idx - cols - 1];

						mag1 = (z1 - z2)*xperp + (z1 - m00)*yperp;

						/* Right point */
						z1 = d_magnitude[img_idx + cols];
						z2 = d_magnitude[img_idx + cols + 1];

						mag2 = (z1 - z2)*xperp + (z1 - m00)*yperp;
					}
				}
				else
				{
					if (gx >= -gy)
					{
						/* 101 */
						/* Left point */
						z1 = d_magnitude[img_idx - 1];
						z2 = d_magnitude[img_idx + cols - 1];

						mag1 = (m00 - z1)*xperp + (z1 - z2)*yperp;

						/* Right point */
						z1 = d_magnitude[img_idx + 1];
						z2 = d_magnitude[img_idx - cols + 1];

						mag2 = (m00 - z1)*xperp + (z1 - z2)*yperp;
					}
					else
					{
						/* 100 */
						/* Left point */
						z1 = d_magnitude[img_idx + cols];
						z2 = d_magnitude[img_idx + cols - 1];

						mag1 = (z1 - z2)*xperp + (m00 - z1)*yperp;

						/* Right point */
						z1 = d_magnitude[img_idx - cols];
						z2 = d_magnitude[img_idx - cols + 1];

						mag2 = (z1 - z2)*xperp + (m00 - z1)*yperp;
					}
				}
			}
			else
			{
				if (gy >= 0)
				{
					if (-gx >= gy)
					{
						/* 011 */
						/* Left point */
						z1 = d_magnitude[img_idx + 1];
						z2 = d_magnitude[img_idx - cols + 1];

						mag1 = (z1 - m00)*xperp + (z2 - z1)*yperp;

						/* Right point */
						z1 = d_magnitude[img_idx - 1];
						z2 = d_magnitude[img_idx + cols - 1];

						mag2 = (z1 - m00)*xperp + (z2 - z1)*yperp;
					}
					else
					{
						/* 010 */
						/* Left point */
						z1 = d_magnitude[img_idx - cols];
						z2 = d_magnitude[img_idx - cols + 1];

						mag1 = (z2 - z1)*xperp + (z1 - m00)*yperp;

						/* Right point */
						z1 = d_magnitude[img_idx + cols];
						z2 = d_magnitude[img_idx + cols - 1];

						mag2 = (z2 - z1)*xperp + (z1 - m00)*yperp;
					}
				}
				else
				{
					if (-gx > -gy)
					{
						/* 001 */
						/* Left point */
						z1 = d_magnitude[img_idx + 1];
						z2 = d_magnitude[img_idx + cols + 1];

						mag1 = (z1 - m00)*xperp + (z1 - z2)*yperp;

						/* Right point */
						z1 = d_magnitude[img_idx - 1];
						z2 = d_magnitude[img_idx - cols - 1];

						mag2 = (z1 - m00)*xperp + (z1 - z2)*yperp;
					}
					else
					{
						/* 000 */
						/* Left point */
						z1 = d_magnitude[img_idx + cols];
						z2 = d_magnitude[img_idx + cols + 1];

						mag1 = (z2 - z1)*xperp + (m00 - z1)*yperp;

						/* Right point */
						z1 = d_magnitude[img_idx - cols];
						z2 = d_magnitude[img_idx - cols - 1];

						mag2 = (z2 - z1)*xperp + (m00 - z1)*yperp;
					}
				}
			}

			/* Now determine if the current point is a maximum point */

			if ((mag1 > 0.0) || (mag2 > 0.0))
			{
				d_nms[img_idx] = (unsigned char)NOEDGE;
			}
			else
			{
				if (mag2 == 0.0)
					d_nms[img_idx] = (unsigned char)NOEDGE;
				else
					d_nms[img_idx] = (unsigned char)POSSIBLE_EDGE;
			}
		}
	}
}

	.file	"tmpxft_0032bf32_00000000-6_cuda_non_maximal_supp.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z48__device_stub__Z19non_max_supp_kerneliiiPsS_S_PhiiiPsS_S_Ph
	.type	_Z48__device_stub__Z19non_max_supp_kerneliiiPsS_S_PhiiiPsS_S_Ph, @function
_Z48__device_stub__Z19non_max_supp_kerneliiiPsS_S_PhiiiPsS_S_Ph:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movl	%edi, 44(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 36(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z19non_max_supp_kerneliiiPsS_S_Ph(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z48__device_stub__Z19non_max_supp_kerneliiiPsS_S_PhiiiPsS_S_Ph, .-_Z48__device_stub__Z19non_max_supp_kerneliiiPsS_S_PhiiiPsS_S_Ph
	.globl	_Z19non_max_supp_kerneliiiPsS_S_Ph
	.type	_Z19non_max_supp_kerneliiiPsS_S_Ph, @function
_Z19non_max_supp_kerneliiiPsS_S_Ph:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z19non_max_supp_kerneliiiPsS_S_PhiiiPsS_S_Ph
	.cfi_endproc
.LFE2053:
	.size	_Z19non_max_supp_kerneliiiPsS_S_Ph, .-_Z19non_max_supp_kerneliiiPsS_S_Ph
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Doing the non-maximal suppression.\n"
.LC1:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/vuongpd95/cuda-canny/master/cuda_non_maximal_supp.cu"
	.text
	.globl	_Z16non_maximal_suppiiiiPPsS0_S0_PPh
	.type	_Z16non_maximal_suppiiiiPPsS0_S0_PPh, @function
_Z16non_maximal_suppiiiiPPsS0_S0_PPh:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%eax, %eax
	movl	%ecx, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r9, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r8, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%edx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%esi, %ebp
	leaq	.LC0(%rip), %rsi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	112(%rsp), %r11
	movq	120(%rsp), %rbx
	movl	%edi, 4(%rsp)
	movl	$2, %edi
	movq	%r11, 8(%rsp)
	call	__printf_chk@PLT
	movl	4(%rsp), %edx
	movq	(%rbx), %rdi
	xorl	%esi, %esi
	imull	%ebp, %edx
	movslq	%edx, %rdx
	call	cudaMemset@PLT
	movl	$1, %ecx
	movl	$43, %edx
	leaq	.LC1(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib@PLT
	movl	%r12d, 36(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movl	%r15d, 24(%rsp)
	movq	%rax, 40(%rsp)
	movl	44(%rsp), %ecx
	movq	%rax, 28(%rsp)
	movq	36(%rsp), %rdx
	movq	24(%rsp), %rdi
	movl	32(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	movq	8(%rsp), %r11
	testl	%eax, %eax
	jne	.L8
	movq	(%rbx), %rax
	movl	4(%rsp), %edi
	movl	%r12d, %edx
	movl	%ebp, %esi
	movq	%rax, 112(%rsp)
	movq	(%r14), %r8
	movq	0(%r13), %rcx
	movq	(%r11), %r9
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z48__device_stub__Z19non_max_supp_kerneliiiPsS_S_PhiiiPsS_S_Ph
.L8:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z16non_maximal_suppiiiiPPsS0_S0_PPh, .-_Z16non_maximal_suppiiiiPPsS0_S0_PPh
	.section	.rodata.str1.1
.LC2:
	.string	"_Z19non_max_supp_kerneliiiPsS_S_Ph"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z19non_max_supp_kerneliiiPsS_S_Ph(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*******************************************************************************
* PROGRAM: canny_edge_detector
* FILE: non_maximal_supp.cu 
* PURPOSE: Apply non maximal suppression.
* NAME: Vuong Pham-Duy
*       Faculty of Computer Science and Technology
*       Ho Chi Minh University of Technology, Viet Nam
*       vuongpd95@gmail.com
* DATE: 11/10/2016
*******************************************************************************/
#include "hip/hip_runtime.h"


#define _USE_MATH_DEFINES
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>

#define NOEDGE 255
#define POSSIBLE_EDGE 128
#define EDGE 0
#define VERBOSE 1

__global__ void non_max_supp_kernel(int rows, int cols, int blockSize,
	short int *d_magnitude, short int *d_delta_x, short int *d_delta_y, unsigned char *d_nms);

#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
void gpuAssert(hipError_t code, const char *file, int line, bool abort = true);
/*******************************************************************************
* PROCEDURE: non_maximal_supp
* PURPOSE: perform non-maximal suppression
* NAME: Vuong Pham-duy
* DATE: 10/11/2016
*******************************************************************************/
void non_maximal_supp(int rows, int cols, int blockSize, int gridSize,
	short int **d_magnitude, short int **d_delta_x, short int **d_delta_y, unsigned char **d_nms)
{
	/****************************************************************************
	* Perform non-maximal suppression.
	****************************************************************************/
	if (VERBOSE) printf("Doing the non-maximal suppression.\n");
	gpuErrchk(hipMemset((*d_nms), 0, rows * cols * sizeof(unsigned char)));
	non_max_supp_kernel<<<gridSize, blockSize>>>(rows, cols, blockSize, (*d_magnitude), (*d_delta_x), (*d_delta_y), (*d_nms));
}
/*******************************************************************************
* PROCEDURE: non_max_supp_kernel
* PURPOSE: This routine applies non-maximal suppression to the magnitude of
* every pixel of the gradient image
* NAME: Vuong Pham-duy
* DATE: 10/11/2016
*******************************************************************************/
__global__ void non_max_supp_kernel(int rows, int cols, int blockSize,
	short int *d_magnitude, short int *d_delta_x, short int *d_delta_y, unsigned char *d_nms)
{
	/* This thread process the number img_idx element of image */
	int img_idx = blockIdx.x * blockSize + threadIdx.x;
	if (img_idx >= (rows * cols)) return;
	int r = img_idx / cols;		 /* row position of the pixel, range [0, rows - 1] */
	int c = img_idx - r * cols;  /* col position of the pixel, range [0, cols - 1] */
	if ((r != rows - 1) && (r != 0) && (c != 0) && (c != cols - 1))
	{
		short m00;
		m00 = d_magnitude[img_idx];
		if (m00 == 0) d_nms[img_idx] = (unsigned char)NOEDGE;
		else
		{
			short gx, gy, z1, z2;
			float mag1, mag2, xperp, yperp;
			gx = d_delta_x[img_idx];
			gy = d_delta_y[img_idx];
			xperp = -gx / ((float)m00);
			yperp = gy / ((float)m00);
			if (gx >= 0){
				if (gy >= 0){
					if (gx >= gy)
					{
						/* 111 */
						/* Left point */
						z1 = d_magnitude[img_idx - 1]; 
						z2 = d_magnitude[img_idx - cols - 1];

						mag1 = (m00 - z1)*xperp + (z2 - z1)*yperp;

						/* Right point */
						z1 = d_magnitude[img_idx + 1];
						z2 = d_magnitude[img_idx + cols + 1];

						mag2 = (m00 - z1)*xperp + (z2 - z1)*yperp;
					}
					else
					{
						/* 110 */
						/* Left point */
						z1 = d_magnitude[img_idx - cols];
						z2 = d_magnitude[img_idx - cols - 1];

						mag1 = (z1 - z2)*xperp + (z1 - m00)*yperp;

						/* Right point */
						z1 = d_magnitude[img_idx + cols];
						z2 = d_magnitude[img_idx + cols + 1];

						mag2 = (z1 - z2)*xperp + (z1 - m00)*yperp;
					}
				}
				else
				{
					if (gx >= -gy)
					{
						/* 101 */
						/* Left point */
						z1 = d_magnitude[img_idx - 1];
						z2 = d_magnitude[img_idx + cols - 1];

						mag1 = (m00 - z1)*xperp + (z1 - z2)*yperp;

						/* Right point */
						z1 = d_magnitude[img_idx + 1];
						z2 = d_magnitude[img_idx - cols + 1];

						mag2 = (m00 - z1)*xperp + (z1 - z2)*yperp;
					}
					else
					{
						/* 100 */
						/* Left point */
						z1 = d_magnitude[img_idx + cols];
						z2 = d_magnitude[img_idx + cols - 1];

						mag1 = (z1 - z2)*xperp + (m00 - z1)*yperp;

						/* Right point */
						z1 = d_magnitude[img_idx - cols];
						z2 = d_magnitude[img_idx - cols + 1];

						mag2 = (z1 - z2)*xperp + (m00 - z1)*yperp;
					}
				}
			}
			else
			{
				if (gy >= 0)
				{
					if (-gx >= gy)
					{
						/* 011 */
						/* Left point */
						z1 = d_magnitude[img_idx + 1];
						z2 = d_magnitude[img_idx - cols + 1];

						mag1 = (z1 - m00)*xperp + (z2 - z1)*yperp;

						/* Right point */
						z1 = d_magnitude[img_idx - 1];
						z2 = d_magnitude[img_idx + cols - 1];

						mag2 = (z1 - m00)*xperp + (z2 - z1)*yperp;
					}
					else
					{
						/* 010 */
						/* Left point */
						z1 = d_magnitude[img_idx - cols];
						z2 = d_magnitude[img_idx - cols + 1];

						mag1 = (z2 - z1)*xperp + (z1 - m00)*yperp;

						/* Right point */
						z1 = d_magnitude[img_idx + cols];
						z2 = d_magnitude[img_idx + cols - 1];

						mag2 = (z2 - z1)*xperp + (z1 - m00)*yperp;
					}
				}
				else
				{
					if (-gx > -gy)
					{
						/* 001 */
						/* Left point */
						z1 = d_magnitude[img_idx + 1];
						z2 = d_magnitude[img_idx + cols + 1];

						mag1 = (z1 - m00)*xperp + (z1 - z2)*yperp;

						/* Right point */
						z1 = d_magnitude[img_idx - 1];
						z2 = d_magnitude[img_idx - cols - 1];

						mag2 = (z1 - m00)*xperp + (z1 - z2)*yperp;
					}
					else
					{
						/* 000 */
						/* Left point */
						z1 = d_magnitude[img_idx + cols];
						z2 = d_magnitude[img_idx + cols + 1];

						mag1 = (z2 - z1)*xperp + (m00 - z1)*yperp;

						/* Right point */
						z1 = d_magnitude[img_idx - cols];
						z2 = d_magnitude[img_idx - cols - 1];

						mag2 = (z2 - z1)*xperp + (m00 - z1)*yperp;
					}
				}
			}

			/* Now determine if the current point is a maximum point */

			if ((mag1 > 0.0) || (mag2 > 0.0))
			{
				d_nms[img_idx] = (unsigned char)NOEDGE;
			}
			else
			{
				if (mag2 == 0.0)
					d_nms[img_idx] = (unsigned char)NOEDGE;
				else
					d_nms[img_idx] = (unsigned char)POSSIBLE_EDGE;
			}
		}
	}
}

	.text
	.file	"cuda_non_maximal_supp.hip"
	.globl	_Z16non_maximal_suppiiiiPPsS0_S0_PPh # -- Begin function _Z16non_maximal_suppiiiiPPsS0_S0_PPh
	.type	_Z16non_maximal_suppiiiiPPsS0_S0_PPh,@function
_Z16non_maximal_suppiiiiPPsS0_S0_PPh:   # @_Z16non_maximal_suppiiiiPPsS0_S0_PPh
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 16(%rsp)                   # 8-byte Spill
	movq	%r8, %r12
	movl	%ecx, %r13d
	movl	%edx, %ebx
	movl	%esi, %ebp
	movl	%edi, %r14d
	movq	88(%rsp), %r15
	movl	$.Lstr, %edi
	callq	puts@PLT
	movq	(%r15), %rdi
	movl	%ebp, %eax
	imull	%r14d, %eax
	movslq	%eax, %rdx
	xorl	%esi, %esi
	callq	hipMemset
	movl	$.L.str.1, %esi
	movl	%eax, %edi
	movl	$43, %edx
	movl	$1, %ecx
	callq	_Z9gpuAssert10hipError_tPKcib
	movl	%r13d, %edi
	btsq	$32, %rdi
	movl	%ebx, %edx
	btsq	$32, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_2
# %bb.1:
	movq	80(%rsp), %rax
	movq	(%r12), %rcx
	movq	16(%rsp), %rdx                  # 8-byte Reload
	movq	(%rdx), %r8
	movq	(%rax), %r9
	movq	88(%rsp), %rax
	movq	(%rax), %rax
	movq	%rax, (%rsp)
	movl	%r14d, %edi
	movl	%ebp, %esi
	movl	%ebx, %edx
	callq	_Z34__device_stub__non_max_supp_kerneliiiPsS_S_Ph
.LBB0_2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z16non_maximal_suppiiiiPPsS0_S0_PPh, .Lfunc_end0-_Z16non_maximal_suppiiiiPPsS0_S0_PPh
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__non_max_supp_kerneliiiPsS_S_Ph # -- Begin function _Z34__device_stub__non_max_supp_kerneliiiPsS_S_Ph
	.type	_Z34__device_stub__non_max_supp_kerneliiiPsS_S_Ph,@function
_Z34__device_stub__non_max_supp_kerneliiiPsS_S_Ph: # @_Z34__device_stub__non_max_supp_kerneliiiPsS_S_Ph
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	56(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19non_max_supp_kerneliiiPsS_S_Ph, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z34__device_stub__non_max_supp_kerneliiiPsS_S_Ph, .Lfunc_end1-_Z34__device_stub__non_max_supp_kerneliiiPsS_S_Ph
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19non_max_supp_kerneliiiPsS_S_Ph, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/vuongpd95/cuda-canny/master/cuda_non_maximal_supp.hip"
	.size	.L.str.1, 116

	.type	_Z19non_max_supp_kerneliiiPsS_S_Ph,@object # @_Z19non_max_supp_kerneliiiPsS_S_Ph
	.section	.rodata,"a",@progbits
	.globl	_Z19non_max_supp_kerneliiiPsS_S_Ph
	.p2align	3, 0x0
_Z19non_max_supp_kerneliiiPsS_S_Ph:
	.quad	_Z34__device_stub__non_max_supp_kerneliiiPsS_S_Ph
	.size	_Z19non_max_supp_kerneliiiPsS_S_Ph, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z19non_max_supp_kerneliiiPsS_S_Ph"
	.size	.L__unnamed_1, 35

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Doing the non-maximal suppression."
	.size	.Lstr, 35

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z34__device_stub__non_max_supp_kerneliiiPsS_S_Ph
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z19non_max_supp_kerneliiiPsS_S_Ph
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z19non_max_supp_kerneliiiPsS_S_Ph ; -- Begin function _Z19non_max_supp_kerneliiiPsS_S_Ph
	.globl	_Z19non_max_supp_kerneliiiPsS_S_Ph
	.p2align	8
	.type	_Z19non_max_supp_kerneliiiPsS_S_Ph,@function
_Z19non_max_supp_kerneliiiPsS_S_Ph:     ; @_Z19non_max_supp_kerneliiiPsS_S_Ph
; %bb.0:
	s_load_b128 s[16:19], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[1:2], null, s15, s18, v[0:1]
	s_mul_i32 s2, s17, s16
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_43
; %bb.1:
	s_ashr_i32 s13, s17, 31
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s2, s17, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s2, s2, s13
	v_add_nc_u32_e32 v4, v1, v2
	v_cvt_f32_u32_e32 v0, s2
	s_sub_i32 s3, 0, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v4, v2
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v3, s3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v0, v3
	v_add_nc_u32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v4, v0
	v_mul_lo_u32 v3, v0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v0
	v_subrev_nc_u32_e32 v5, s2, v3
	v_cmp_le_u32_e32 vcc_lo, s2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
	v_xor_b32_e32 v5, s13, v2
	v_cmp_le_u32_e32 vcc_lo, s2, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, 1, v0
	s_add_i32 s2, s16, -1
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v5
	v_sub_nc_u32_e32 v3, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v3, s17
	v_cmp_ne_u32_e32 vcc_lo, s2, v3
	v_cmp_ne_u32_e64 s2, 0, v3
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ne_u32_e64 s3, v1, v0
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_43
; %bb.2:
	v_sub_nc_u32_e32 v0, v1, v0
	s_add_i32 s2, s17, -1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ne_u32_e32 vcc_lo, s2, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_43
; %bb.3:
	s_load_b256 s[4:11], s[0:1], 0x10
	v_lshlrev_b64 v[5:6], 1, v[1:2]
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v6, vcc_lo
	global_load_u16 v0, v[3:4], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u16_e32 0, v0
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB0_41
; %bb.4:
	v_add_co_u32 v7, vcc_lo, s6, v5
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v6, vcc_lo
	v_add_co_u32 v5, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	global_load_i16 v11, v[7:8], off
	s_mov_b32 s2, exec_lo
	global_load_i16 v10, v[5:6], off
	v_bfe_i32 v6, v0, 0, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v5, v6
	s_waitcnt vmcnt(1)
	v_sub_nc_u32_e32 v12, 0, v11
	s_waitcnt vmcnt(0)
	v_cvt_f32_i32_e32 v7, v10
	v_cvt_f32_i32_e32 v0, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v9, null, v5, v5, v7
	v_div_scale_f32 v8, null, v5, v5, v0
	v_div_scale_f32 v17, vcc_lo, v0, v5, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v14, v9
	v_rcp_f32_e32 v13, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v16, -v9, v14, 1.0
	v_fma_f32 v15, -v8, v13, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v14, v16, v14 :: v_dual_fmac_f32 v13, v15, v13
	v_div_scale_f32 v15, s0, v7, v5, v7
	v_mul_f32_e32 v16, v17, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v18, v15, v14
	v_fma_f32 v19, -v8, v16, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v20, -v9, v18, v15
	v_fmac_f32_e32 v16, v19, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v18, v20, v14
	v_fma_f32 v8, -v8, v16, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v9, -v9, v18, v15
	v_div_fmas_f32 v8, v8, v13, v16
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v9, v9, v14, v18
	v_cmp_gt_i32_e32 vcc_lo, 0, v10
	v_div_fixup_f32 v0, v8, v5, v0
                                        ; implicit-def: $vgpr8
	s_delay_alu instid0(VALU_DEP_3)
	v_div_fixup_f32 v5, v9, v5, v7
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr9
	v_cmpx_gt_i32_e32 0, v11
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_18
; %bb.5:
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr9
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB0_11
; %bb.6:
	s_mov_b32 s6, exec_lo
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr9
	v_cmpx_le_u16_e64 v10, v11
	s_xor_b32 s6, exec_lo, s6
	s_cbranch_execz .LBB0_8
; %bb.7:
	v_subrev_nc_u32_e32 v7, s17, v1
	s_mov_b32 s12, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[8:9], s[12:13], 1
	v_add_co_u32 v3, s0, v3, s8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v8, 31, v7
	v_add_co_ci_u32_e64 v4, s0, s9, v4, s0
	v_lshlrev_b64 v[7:8], 1, v[7:8]
	global_load_b32 v9, v[3:4], off
	v_add_co_u32 v3, s0, s4, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v4, s0, s5, v8, s0
	global_load_b32 v3, v[3:4], off offset:-2
	s_waitcnt vmcnt(1)
	v_ashrrev_i32_e32 v4, 16, v9
	v_bfe_i32 v7, v9, 0, 16
	v_sub_nc_u32_e32 v4, v4, v7
	v_sub_nc_u32_e32 v7, v6, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v4, v4
	s_waitcnt vmcnt(0)
	v_bfe_i32 v8, v3, 0, 16
	v_ashrrev_i32_e32 v3, 16, v3
	v_sub_nc_u32_e32 v8, v8, v3
	v_sub_nc_u32_e32 v3, v6, v3
	v_cvt_f32_i32_e32 v6, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cvt_f32_i32_e32 v3, v3
	v_mul_f32_e32 v7, v0, v4
	v_cvt_f32_i32_e32 v4, v8
	v_mul_f32_e32 v8, v5, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v7, v5, v6
	v_mul_f32_e32 v9, v0, v4
                                        ; implicit-def: $vgpr3_vgpr4
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr0
.LBB0_8:                                ; %Flow274
	s_and_not1_saveexec_b32 s6, s6
	s_cbranch_execz .LBB0_10
; %bb.9:
	v_xad_u32 v7, s17, -1, v1
	s_mov_b32 s12, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[8:9], s[12:13], 1
	v_add_co_u32 v9, s0, v3, s8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v8, 31, v7
	v_add_co_ci_u32_e64 v10, s0, s9, v4, s0
	v_lshlrev_b64 v[7:8], 1, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v7, s0, s4, v7
	v_add_co_ci_u32_e64 v8, s0, s5, v8, s0
	s_clause 0x3
	global_load_i16 v11, v[3:4], off offset:2
	global_load_i16 v9, v[9:10], off offset:2
	global_load_i16 v7, v[7:8], off
	global_load_i16 v3, v[3:4], off offset:-2
	s_waitcnt vmcnt(3)
	v_sub_nc_u32_e32 v8, v11, v6
	s_waitcnt vmcnt(2)
	v_sub_nc_u32_e32 v4, v11, v9
	s_waitcnt vmcnt(0)
	v_sub_nc_u32_e32 v6, v3, v6
	v_sub_nc_u32_e32 v3, v3, v7
	v_cvt_f32_i32_e32 v8, v8
	v_cvt_f32_i32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v3, v3
	v_mul_f32_e32 v7, v5, v4
	v_cvt_f32_i32_e32 v4, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v9, v5, v3
	v_fmac_f32_e32 v7, v0, v8
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v8, v0, v4
.LBB0_10:                               ; %Flow275
	s_or_b32 exec_lo, exec_lo, s6
                                        ; implicit-def: $vgpr3_vgpr4
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr5
.LBB0_11:                               ; %Flow278
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB0_17
; %bb.12:
	s_mov_b32 s6, exec_lo
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr9
	v_cmpx_ge_i32_e64 v12, v10
	s_xor_b32 s6, exec_lo, s6
	s_cbranch_execz .LBB0_14
; %bb.13:
	v_subrev_nc_u32_e32 v7, s17, v1
	s_mov_b32 s12, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[8:9], s[12:13], 1
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 1, v[7:8]
	v_add_co_u32 v7, s0, s4, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v8, s0, s5, v8, s0
	v_add_co_u32 v9, s0, v3, s8
	v_add_co_ci_u32_e64 v10, s0, s9, v4, s0
	s_clause 0x3
	global_load_i16 v11, v[3:4], off offset:2
	global_load_i16 v7, v[7:8], off offset:2
	global_load_i16 v8, v[9:10], off offset:-2
	global_load_i16 v3, v[3:4], off offset:-2
	s_waitcnt vmcnt(2)
	v_sub_nc_u32_e32 v4, v7, v11
	v_sub_nc_u32_e32 v7, v11, v6
	s_waitcnt vmcnt(0)
	v_sub_nc_u32_e32 v6, v3, v6
	v_sub_nc_u32_e32 v3, v8, v3
	v_cvt_f32_i32_e32 v4, v4
	v_cvt_f32_i32_e32 v9, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_f32_i32_e32 v6, v6
	v_cvt_f32_i32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v7, v5, v4 :: v_dual_mul_f32 v8, v0, v6
                                        ; implicit-def: $vgpr6
	v_fmac_f32_e32 v7, v0, v9
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v9, v5, v3
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr3
.LBB0_14:                               ; %Flow276
	s_and_not1_saveexec_b32 s6, s6
	s_cbranch_execz .LBB0_16
; %bb.15:
	v_subrev_nc_u32_e32 v7, s17, v1
	s_mov_b32 s12, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[8:9], s[12:13], 1
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 1, v[7:8]
	v_add_co_u32 v7, s0, s4, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v8, s0, s5, v8, s0
	v_add_co_u32 v3, s0, v3, s8
	v_add_co_ci_u32_e64 v4, s0, s9, v4, s0
	s_clause 0x1
	global_load_b32 v7, v[7:8], off
	global_load_b32 v3, v[3:4], off offset:-2
	s_waitcnt vmcnt(1)
	v_ashrrev_i32_e32 v4, 16, v7
	v_bfe_i32 v7, v7, 0, 16
	s_waitcnt vmcnt(0)
	v_bfe_i32 v8, v3, 0, 16
	v_ashrrev_i32_e32 v3, 16, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v4, v4, v7
	v_sub_nc_u32_e32 v7, v7, v6
	v_sub_nc_u32_e32 v8, v8, v3
	v_sub_nc_u32_e32 v3, v3, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_f32_i32_e32 v4, v4
	v_cvt_f32_i32_e32 v6, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_f32_i32_e32 v8, v8
	v_cvt_f32_i32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v7, v0, v4
	v_dual_mul_f32 v9, v0, v8 :: v_dual_mul_f32 v8, v5, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_fmac_f32_e32 v7, v5, v6
.LBB0_16:                               ; %Flow277
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_17:                               ; %Flow279
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
                                        ; implicit-def: $vgpr3_vgpr4
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr5
.LBB0_18:                               ; %Flow286
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_32
; %bb.19:
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr9
	s_and_saveexec_b32 s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_25
; %bb.20:
	v_sub_nc_u32_e32 v7, 0, v10
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e32 vcc_lo, v11, v7
                                        ; implicit-def: $vgpr7
	s_and_saveexec_b32 s3, vcc_lo
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_22
; %bb.21:
	v_subrev_nc_u32_e32 v7, s17, v1
	s_mov_b32 s12, s17
	global_load_i16 v11, v[3:4], off offset:-2
	s_lshl_b64 s[6:7], s[12:13], 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v3, s6
	v_ashrrev_i32_e32 v8, 31, v7
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v4, vcc_lo
	v_lshlrev_b64 v[7:8], 1, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	s_clause 0x2
	global_load_i16 v9, v[9:10], off offset:-2
	global_load_i16 v7, v[7:8], off offset:2
	global_load_i16 v3, v[3:4], off offset:2
	s_waitcnt vmcnt(3)
	v_sub_nc_u32_e32 v8, v6, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_i32_e32 v8, v8
	s_waitcnt vmcnt(2)
	v_sub_nc_u32_e32 v4, v11, v9
	s_waitcnt vmcnt(0)
	v_sub_nc_u32_e32 v6, v6, v3
	v_sub_nc_u32_e32 v3, v3, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v4, v4
	v_cvt_f32_i32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v7, v5, v4
	v_cvt_f32_i32_e32 v4, v6
                                        ; implicit-def: $vgpr6
	v_mul_f32_e32 v9, v5, v3
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v7, v0, v8
	v_mul_f32_e32 v8, v0, v4
                                        ; implicit-def: $vgpr0
.LBB0_22:                               ; %Flow280
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB0_24
; %bb.23:
	v_subrev_nc_u32_e32 v7, s17, v1
	s_mov_b32 s12, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[6:7], s[12:13], 1
	v_add_co_u32 v3, vcc_lo, v3, s6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v8, 31, v7
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	v_lshlrev_b64 v[7:8], 1, v[7:8]
	global_load_b32 v9, v[3:4], off offset:-2
	v_add_co_u32 v3, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v8, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(1)
	v_ashrrev_i32_e32 v4, 16, v9
	v_bfe_i32 v7, v9, 0, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v7, v4, v7
	v_sub_nc_u32_e32 v4, v6, v4
	v_cvt_f32_i32_e32 v7, v7
	s_waitcnt vmcnt(0)
	v_bfe_i32 v8, v3, 0, 16
	v_ashrrev_i32_e32 v3, 16, v3
	v_cvt_f32_i32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v6, v6, v8
	v_sub_nc_u32_e32 v3, v8, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cvt_f32_i32_e32 v6, v6
	v_mul_f32_e32 v7, v0, v7
	v_cvt_f32_i32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v8, v5, v6
	v_fmac_f32_e32 v7, v5, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v9, v0, v3
.LBB0_24:                               ; %Flow281
	s_or_b32 exec_lo, exec_lo, s3
                                        ; implicit-def: $vgpr3_vgpr4
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr5
.LBB0_25:                               ; %Flow284
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB0_31
; %bb.26:
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr9
	v_cmpx_ge_u16_e64 v11, v10
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_28
; %bb.27:
	v_xad_u32 v7, s17, -1, v1
	s_mov_b32 s12, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[6:7], s[12:13], 1
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 1, v[7:8]
	v_add_co_u32 v7, vcc_lo, s4, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	v_add_co_u32 v9, vcc_lo, v3, s6
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v4, vcc_lo
	s_clause 0x3
	global_load_i16 v11, v[3:4], off offset:-2
	global_load_i16 v7, v[7:8], off
	global_load_i16 v8, v[9:10], off offset:2
	global_load_i16 v3, v[3:4], off offset:2
	s_waitcnt vmcnt(2)
	v_sub_nc_u32_e32 v4, v7, v11
	v_sub_nc_u32_e32 v7, v6, v11
	s_waitcnt vmcnt(0)
	v_sub_nc_u32_e32 v6, v6, v3
	v_sub_nc_u32_e32 v3, v8, v3
	v_cvt_f32_i32_e32 v4, v4
	v_cvt_f32_i32_e32 v9, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_f32_i32_e32 v6, v6
	v_cvt_f32_i32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v7, v5, v4 :: v_dual_mul_f32 v8, v0, v6
                                        ; implicit-def: $vgpr6
	v_fmac_f32_e32 v7, v0, v9
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v9, v5, v3
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr3
.LBB0_28:                               ; %Flow282
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB0_30
; %bb.29:
	v_subrev_nc_u32_e32 v7, s17, v1
	s_mov_b32 s12, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[6:7], s[12:13], 1
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 1, v[7:8]
	v_add_co_u32 v7, vcc_lo, s4, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	v_add_co_u32 v3, vcc_lo, v3, s6
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	s_clause 0x1
	global_load_b32 v7, v[7:8], off offset:-2
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(1)
	v_ashrrev_i32_e32 v4, 16, v7
	v_bfe_i32 v7, v7, 0, 16
	s_waitcnt vmcnt(0)
	v_bfe_i32 v8, v3, 0, 16
	v_ashrrev_i32_e32 v3, 16, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v7, v4, v7
	v_sub_nc_u32_e32 v4, v4, v6
	v_sub_nc_u32_e32 v3, v8, v3
	v_sub_nc_u32_e32 v6, v8, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_f32_i32_e32 v7, v7
	v_cvt_f32_i32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_f32_i32_e32 v3, v3
	v_cvt_f32_i32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v7, v0, v7
	v_dual_mul_f32 v9, v0, v3 :: v_dual_mul_f32 v8, v5, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_fmac_f32_e32 v7, v5, v4
.LBB0_30:                               ; %Flow283
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_31:                               ; %Flow285
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_32:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_add_f32 v0, v8, v9 :: v_dual_max_f32 v3, v7, v7
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_f32_e32 v3, v3, v0
	v_cmpx_nlt_f32_e32 0, v3
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB0_38
; %bb.33:
	v_cmp_neq_f32_e32 vcc_lo, 0, v0
	v_add_co_u32 v0, s0, s10, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v1, s0, s11, v2, s0
	s_and_saveexec_b32 s0, vcc_lo
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_35
; %bb.34:
	v_mov_b32_e32 v2, 0x80
	global_store_b8 v[0:1], v2, off
                                        ; implicit-def: $vgpr0_vgpr1
.LBB0_35:                               ; %Flow
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_37
; %bb.36:
	v_mov_b32_e32 v2, 0xff
	global_store_b8 v[0:1], v2, off
.LBB0_37:                               ; %Flow271
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr1_vgpr2
.LBB0_38:                               ; %Flow272
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_40
; %bb.39:
	v_add_co_u32 v0, vcc_lo, s10, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v2, vcc_lo
	v_mov_b32_e32 v2, 0xff
	global_store_b8 v[0:1], v2, off
.LBB0_40:                               ; %Flow273
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr1_vgpr2
.LBB0_41:                               ; %Flow287
	s_and_not1_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_43
; %bb.42:
	v_add_co_u32 v0, vcc_lo, s10, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v2, vcc_lo
	v_mov_b32_e32 v2, 0xff
	global_store_b8 v[0:1], v2, off
.LBB0_43:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19non_max_supp_kerneliiiPsS_S_Ph
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 48
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z19non_max_supp_kerneliiiPsS_S_Ph, .Lfunc_end0-_Z19non_max_supp_kerneliiiPsS_S_Ph
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2460
; NumSgprs: 22
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 48
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19non_max_supp_kerneliiiPsS_S_Ph
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z19non_max_supp_kerneliiiPsS_S_Ph.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     21
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
