/***************************************************************************//**
 * \file LHS1.cu
 * \author Christopher Minar (minarc@oregonstate.edu)
 * \brief kernels to generate the left hand side for the intermediate velocity solve
 */

#include "LHS1.h"

namespace kernels
{
/*
 * calculates the boundary terms for the left hand side matrix for the velocity solve
 * param row array storing the row indices for the sparse LHS matrix
 * param col array storing the column indices for the sparse LHS matrix
 * param val array storing the values for the sparse LHS matrix
 * param dx distance between nodes in the x direction (measured between node sides, where u velocites are stored)
 * param dy distance between nodes in the y direction (measured between node top/bot, where v velocites are stored)
 * param dt change in time
 * param nu viscosity
 * param nx number of cells in x direction
 * param ny number of cells in y direction
 */
__global__
void LHS_BC_X(int *row, int *col, double *val, double *dx, double *dy, double dt, double nu, int nx, int ny)
{
	if (threadIdx.x + blockDim.x * blockIdx.x >= (nx-1)*ny)
		return;
	int i 	= threadIdx.x + blockDim.x * blockIdx.x,
		I	= i % (nx-1),
		J	= i / (nx-1);
	if (I != 0 && I != nx-2 && J != 0 && J != ny-1)
		return;

	double temp = 1;
	int numE = 0;
	if (J == 0)
	{
		numE = I*4;
		if (I != 0)
			numE -= 1;
	}
	else if (J == ny-1)
	{
		numE = (nx-1)*4 - 2 + (J-1)*(5*(nx-1)  - 2) + I*4;
		if (I != 0)
			numE-=1;
	}
	else
	{
		if (I == 0)
			numE = (nx-1)*4 - 2 + (J-1)*(5*(nx-1)  - 2) + I*5;
		else
			numE = (nx-1)*4 - 2 + (J-1)*(5*(nx-1)  - 2) + I*5 - 1;
	}

	//EAST
	if(I != nx-2)//check if on east boundary
	{
		row[numE] = i;
		col[numE] = i+1;
		val[numE] = -0.5*dt*nu*(1/(dx[I+1]*(dx[I+1]+dx[I])*0.5));
		temp += 0.5*dt*nu*(1/(dx[I+1]*(dx[I+1]+dx[I])*0.5));
		numE++;
	}
	else
	{
		temp += 0.5*dt*nu*(1/(dx[I+1]*(dx[I+1]+dx[I])*0.5));
	}

	//WEST
	if(I != 0)//check if on west boundary
	{
		row[numE] = i;
		col[numE] = i-1;
		val[numE] = -0.5*dt*nu*(1/(dx[I]*(dx[I+1]+dx[I])*0.5));
		temp += 0.5*dt*nu*(1/(dx[I]*(dx[I+1]+dx[I])*0.5));
		numE++;
	}
	else
	{
		temp += 0.5*dt*nu*(1/(dx[I]*(dx[I+1]+dx[I])*0.5));
	}

	//NORTH
	if(J != ny-1)//check if on north boundary
	{
		row[numE] = i;
		col[numE] = i+(nx-1);
		val[numE] = -0.5*dt*nu*(1/(dy[J]*(dy[J+1]+dy[J])*0.5));
		temp += 0.5*dt*nu*(1/(dy[J]*(dy[J+1]+dy[J])*0.5));
		numE++;
	}
	else
	{
		temp += 0.5*dt*nu*(1/(dy[J]*(dy[J]+dy[J])*0.5));
	}

	//SOUTH
	if(J != 0)//check if on south boundary
	{
		row[numE] = i;
		col[numE] = i-(nx-1);
		val[numE] = -0.5*dt*nu*(1/(dy[J]*(dy[J-1]+dy[J])*0.5));
		temp += 0.5*dt*nu*(1/(dy[J]*(dy[J-1]+dy[J])*0.5));
		numE++;
	}
	else
	{
		temp += 0.5*dt*nu*(1/(dy[J]*(dy[J]+dy[J])*0.5));
	}

	//CENTER
	row[numE] = i;
	col[numE] = i;
	val[numE] = temp;
	numE++;
}

/*
 * calculates the boundary terms for the left hand side matrix for the velocity solve
 * param row array storing the row indices for the sparse LHS matrix
 * param col array storing the column indices for the sparse LHS matrix
 * param val array storing the values for the sparse LHS matrix
 * param dx distance between nodes in the x direction (measured between node sides, where u velocites are stored)
 * param dy distance between nodes in the y direction (measured between node top/bot, where v velocites are stored)
 * param dt change in time
 * param nu viscosity
 * param nx number of cells in x direction
 * param ny number of cells in y direction
 */
__global__
void LHS_BC_Y(int *row, int *col, double *val, double *dx, double *dy, double dt, double nu, int nx, int ny)
{
	if (threadIdx.x + blockDim.x * blockIdx.x >= nx*(ny-1))
		return;
	int ip 	= threadIdx.x + blockDim.x * blockIdx.x,
		I	= ip % nx,
		J	= ip / nx,
		i = ip + (nx-1)*ny;
	if (I != 0 && I != nx-1 && J != 0 && J != ny-2)
		return;

	int numE = (nx-1)*ny*5 - 2*ny-2*(nx-1);
	if (J == 0)
	{
		numE += I*4;
		if (I != 0)
			numE -= 1;
	}
	else if (J == ny-2)
	{
		numE += nx*4 - 2 + (J-1)*(5*nx - 2) + I*4;
		if (I != 0)
			numE-=1;
	}
	else
	{
		if (I == 0)
			numE += nx*4 - 2 + (J-1)*(5*nx - 2) + I*5;
		else
			numE += nx*4 - 2 + (J-1)*(5*nx - 2) + I*5 - 1;
	}
	double temp = 1;

	//EAST
	if(I != nx-1)//check if on east boundary
	{
		row[numE] = i;
		col[numE] = i+1;
		val[numE] = -0.5*dt*nu*(1/(dx[I]*(dx[I]+dx[I+1])*0.5));
		temp += 0.5*dt*nu*(1/(dx[I]*(dx[I]+dx[I+1])*0.5));
		numE++;
	}
	else
	{
		temp += 0.5*dt*nu*(1/(dx[I]*(dx[I]+dx[I])*0.5));
	}

	//WEST
	if(I != 0)//check if  on west boundary
	{
		row[numE] = i;
		col[numE] = i-1;
		val[numE] = -0.5*dt*nu*(1/(dx[I]*(dx[I]+dx[I-1])*0.5));
		temp += 0.5*dt*nu*(1/(dx[I]*(dx[I]+dx[I-1])*0.5));
		numE++;
	}
	else
	{
		temp += 0.5*dt*nu*(1/(dx[I]*(dx[I]+dx[I])*0.5));
	}

	//NORTH
	if(J != ny-2)//check if on north boundary
	{
		row[numE] = i;
		col[numE] = i + nx;
		val[numE] = -0.5*dt*nu*(1/(dy[J+1]*(dy[J]+dy[J+1])*0.5));
		temp += 0.5*dt*nu*(1/(dy[J+1]*(dy[J]+dy[J+1])*0.5));
		numE++;
	}
	else
	{
		temp += 0.5*dt*nu*(1/(dy[J+1]*(dy[J]+dy[J+1])*0.5));
	}

	//SOUTH
	if(J != 0)//check if on south boundary
	{
		row[numE] = i;
		col[numE] = i-nx;
		val[numE] = -0.5*dt*nu*(1/(dy[J]*(dy[J]+dy[J+1])*0.5));
		temp += 0.5*dt*nu*(1/(dy[J]*(dy[J]+dy[J+1])*0.5));
		numE++;
	}
	else
	{
		temp += 0.5*dt*nu*(1/(dy[J]*(dy[J]+dy[J+1])*0.5));
	}

	//CENTER
	row[numE] = i;
	col[numE] = i;
	val[numE] = temp;
	numE++;
}

/*
 * calculates the middle terms for the left hand side matrix for the velocity solve
 * param row array storing the row indices for the sparse LHS matrix
 * param col array storing the column indices for the sparse LHS matrix
 * param val array storing the values for the sparse LHS matrix
 * param dx distance between nodes in the x direction (measured between node sides, where u velocites are stored)
 * param dy distance between nodes in the y direction (measured between node top/bot, where v velocites are stored)
 * param dt change in time
 * param nu viscosity
 * param nx number of cells in x direction
 * param ny number of cells in y direction
 */
__global__
void LHS_mid_X_nobody(int *row, int *col, double *val, double *dx, double *dy, double dt, double nu, int nx, int ny)
{
	if (threadIdx.x + blockDim.x * blockIdx.x >= (nx-1)*ny)
		return;
	int i 	= threadIdx.x + blockDim.x * blockIdx.x,
		I	= i % (nx-1),
		J	= i / (nx-1);
	if (I == 0 || I == nx-2 || J == 0 || J == ny-1)
		return;

	//			top row - corner    mid           sides    current row
	int numE = (nx-1)*4 - 2      + (J-1)*(5*(nx-1)  - 2) + I*5 - 1;

	double temp = 1;
	//EAST
	row[numE] = i;
	col[numE] = i+1;
	val[numE] = -0.5*dt*nu*(1/(dx[I+1]*(dx[I+1]+dx[I])*0.5));
	temp += 0.5*dt*nu*(1/(dx[I+1]*(dx[I+1]+dx[I])*0.5));
	numE++;

	//WEST
	row[numE] = i;
	col[numE] = i-1;
	val[numE] = -0.5*dt*nu*(1/(dx[I]*(dx[I+1]+dx[I])*0.5));
	temp += 0.5*dt*nu*(1/(dx[I]*(dx[I+1]+dx[I])*0.5));
	numE++;

	//NORTH
	row[numE] = i;
	col[numE] = i+(nx-1);
	val[numE] = -0.5*dt*nu*(1/(dy[J]*(dy[J+1]+dy[J])*0.5));
	temp += 0.5*dt*nu*(1/(dy[J]*(dy[J+1]+dy[J])*0.5));
	numE++;

	//SOUTH
	row[numE] = i;
	col[numE] = i-(nx-1);
	val[numE] = -0.5*dt*nu*(1/(dy[J]*(dy[J-1]+dy[J])*0.5));
	temp += 0.5*dt*nu*(1/(dy[J]*(dy[J-1]+dy[J])*0.5));
	numE++;

	//CENTER
	row[numE] = i;
	col[numE] = i;
	val[numE] = temp;
	numE++;
}

/*
 * calculates the middle terms for the left hand side matrix for the velocity solve
 * param row array storing the row indices for the sparse LHS matrix
 * param col array storing the column indices for the sparse LHS matrix
 * param val array storing the values for the sparse LHS matrix
 * param dx distance between nodes in the x direction (measured between node sides, where u velocites are stored)
 * param dy distance between nodes in the y direction (measured between node top/bot, where v velocites are stored)
 * param dt change in time
 * param nu viscosity
 * param nx number of cells in x direction
 * param ny number of cells in y direction
 */
__global__
void LHS_mid_Y_nobody(int *row, int *col, double *val, double *dx, double *dy, double dt, double nu, int nx, int ny)
{
	if (threadIdx.x + blockDim.x * blockIdx.x >= nx*(ny-1))
		return;
	int ip 	= threadIdx.x + blockDim.x * blockIdx.x,
		I	= ip % nx,
		J	= ip / nx,
		i = ip + (nx-1)*ny;
	if (I == 0 || I == nx-1 || J == 0 || J == ny-2)
		return;

	//         (              numU       )     (row1)    (rows2-before me)  (current row)
	int numE = (nx-1)*ny*5 - 2*ny-2*(nx-1)  +  nx*4-2  + (J-1)*(nx*5 - 2) + I*5 - 1;
	double temp = 1;

	//EAST
	row[numE] = i;
	col[numE] = i+1;
	val[numE] = -0.5*dt*nu*(1/(dx[I]*(dx[I]+dx[I+1])*0.5));
	temp += 0.5*dt*nu*(1/(dx[I]*(dx[I]+dx[I+1])*0.5));
	numE++;

	//WEST
	row[numE] = i;
	col[numE] = i-1;
	val[numE] = -0.5*dt*nu*(1/(dx[I]*(dx[I]+dx[I-1])*0.5));
	temp += 0.5*dt*nu*(1/(dx[I]*(dx[I]+dx[I-1])*0.5));
	numE++;

	//NORTH
	row[numE] = i;
	col[numE] = i + nx;
	val[numE] = -0.5*dt*nu*(1/(dy[J+1]*(dy[J]+dy[J+1])*0.5));
	temp += 0.5*dt*nu*(1/(dy[J+1]*(dy[J]+dy[J+1])*0.5));
	numE++;

	//SOUTH
	row[numE] = i;
	col[numE] = i-nx;
	val[numE] = -0.5*dt*nu*(1/(dy[J]*(dy[J]+dy[J+1])*0.5));
	temp += 0.5*dt*nu*(1/(dy[J]*(dy[J]+dy[J+1])*0.5));
	numE++;

	//CENTER
	row[numE] = i;
	col[numE] = i;
	val[numE] = temp;
	numE++;
}
}

	.file	"tmpxft_003ade65_00000000-6_LHS1.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z52__device_stub__ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddiiPiS_PdS0_S0_ddii
	.type	_Z52__device_stub__ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddiiPiS_PdS0_S0_ddii, @function
_Z52__device_stub__ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddiiPiS_PdS0_S0_ddii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movl	%r9d, 4(%rsp)
	movsd	%xmm0, 16(%rsp)
	movsd	%xmm1, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	72(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 240
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L2:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z52__device_stub__ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddiiPiS_PdS0_S0_ddii, .-_Z52__device_stub__ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddiiPiS_PdS0_S0_ddii
	.globl	_ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii
	.type	_ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii, @function
_ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddiiPiS_PdS0_S0_ddii
	.cfi_endproc
.LFE2033:
	.size	_ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii, .-_ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii
	.globl	_Z52__device_stub__ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddiiPiS_PdS0_S0_ddii
	.type	_Z52__device_stub__ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddiiPiS_PdS0_S0_ddii, @function
_Z52__device_stub__ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddiiPiS_PdS0_S0_ddii:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movl	%r9d, 4(%rsp)
	movsd	%xmm0, 16(%rsp)
	movsd	%xmm1, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	72(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 240
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L8:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z52__device_stub__ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddiiPiS_PdS0_S0_ddii, .-_Z52__device_stub__ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddiiPiS_PdS0_S0_ddii
	.globl	_ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii
	.type	_ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii, @function
_ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddiiPiS_PdS0_S0_ddii
	.cfi_endproc
.LFE2035:
	.size	_ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii, .-_ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii
	.globl	_Z61__device_stub__ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddiiPiS_PdS0_S0_ddii
	.type	_Z61__device_stub__ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddiiPiS_PdS0_S0_ddii, @function
_Z61__device_stub__ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddiiPiS_PdS0_S0_ddii:
.LFB2036:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movl	%r9d, 4(%rsp)
	movsd	%xmm0, 16(%rsp)
	movsd	%xmm1, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	72(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 240
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L13:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	_Z61__device_stub__ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddiiPiS_PdS0_S0_ddii, .-_Z61__device_stub__ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddiiPiS_PdS0_S0_ddii
	.globl	_ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii
	.type	_ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii, @function
_ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii:
.LFB2037:
	.cfi_startproc
	endbr64
	jmp	_Z61__device_stub__ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddiiPiS_PdS0_S0_ddii
	.cfi_endproc
.LFE2037:
	.size	_ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii, .-_ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii
	.globl	_Z61__device_stub__ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddiiPiS_PdS0_S0_ddii
	.type	_Z61__device_stub__ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddiiPiS_PdS0_S0_ddii, @function
_Z61__device_stub__ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddiiPiS_PdS0_S0_ddii:
.LFB2038:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movl	%r9d, 4(%rsp)
	movsd	%xmm0, 16(%rsp)
	movsd	%xmm1, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	72(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 240
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L18:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2038:
	.size	_Z61__device_stub__ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddiiPiS_PdS0_S0_ddii, .-_Z61__device_stub__ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddiiPiS_PdS0_S0_ddii
	.globl	_ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii
	.type	_ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii, @function
_ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii:
.LFB2039:
	.cfi_startproc
	endbr64
	jmp	_Z61__device_stub__ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddiiPiS_PdS0_S0_ddii
	.cfi_endproc
.LFE2039:
	.size	_ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii, .-_ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii"
.LC1:
	.string	"_ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii"
.LC2:
	.string	"_ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii"
.LC3:
	.string	"_ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2041:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2041:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/***************************************************************************//**
 * \file LHS1.cu
 * \author Christopher Minar (minarc@oregonstate.edu)
 * \brief kernels to generate the left hand side for the intermediate velocity solve
 */


#include <hip/hip_runtime.h>
#include "LHS1.h"

namespace kernels
{
/*
 * calculates the boundary terms for the left hand side matrix for the velocity solve
 * param row array storing the row indices for the sparse LHS matrix
 * param col array storing the column indices for the sparse LHS matrix
 * param val array storing the values for the sparse LHS matrix
 * param dx distance between nodes in the x direction (measured between node sides, where u velocites are stored)
 * param dy distance between nodes in the y direction (measured between node top/bot, where v velocites are stored)
 * param dt change in time
 * param nu viscosity
 * param nx number of cells in x direction
 * param ny number of cells in y direction
 */
__global__
void LHS_BC_X(int *row, int *col, double *val, double *dx, double *dy, double dt, double nu, int nx, int ny)
{
	if (threadIdx.x + blockDim.x * blockIdx.x >= (nx-1)*ny)
		return;
	int i 	= threadIdx.x + blockDim.x * blockIdx.x,
		I	= i % (nx-1),
		J	= i / (nx-1);
	if (I != 0 && I != nx-2 && J != 0 && J != ny-1)
		return;

	double temp = 1;
	int numE = 0;
	if (J == 0)
	{
		numE = I*4;
		if (I != 0)
			numE -= 1;
	}
	else if (J == ny-1)
	{
		numE = (nx-1)*4 - 2 + (J-1)*(5*(nx-1)  - 2) + I*4;
		if (I != 0)
			numE-=1;
	}
	else
	{
		if (I == 0)
			numE = (nx-1)*4 - 2 + (J-1)*(5*(nx-1)  - 2) + I*5;
		else
			numE = (nx-1)*4 - 2 + (J-1)*(5*(nx-1)  - 2) + I*5 - 1;
	}

	//EAST
	if(I != nx-2)//check if on east boundary
	{
		row[numE] = i;
		col[numE] = i+1;
		val[numE] = -0.5*dt*nu*(1/(dx[I+1]*(dx[I+1]+dx[I])*0.5));
		temp += 0.5*dt*nu*(1/(dx[I+1]*(dx[I+1]+dx[I])*0.5));
		numE++;
	}
	else
	{
		temp += 0.5*dt*nu*(1/(dx[I+1]*(dx[I+1]+dx[I])*0.5));
	}

	//WEST
	if(I != 0)//check if on west boundary
	{
		row[numE] = i;
		col[numE] = i-1;
		val[numE] = -0.5*dt*nu*(1/(dx[I]*(dx[I+1]+dx[I])*0.5));
		temp += 0.5*dt*nu*(1/(dx[I]*(dx[I+1]+dx[I])*0.5));
		numE++;
	}
	else
	{
		temp += 0.5*dt*nu*(1/(dx[I]*(dx[I+1]+dx[I])*0.5));
	}

	//NORTH
	if(J != ny-1)//check if on north boundary
	{
		row[numE] = i;
		col[numE] = i+(nx-1);
		val[numE] = -0.5*dt*nu*(1/(dy[J]*(dy[J+1]+dy[J])*0.5));
		temp += 0.5*dt*nu*(1/(dy[J]*(dy[J+1]+dy[J])*0.5));
		numE++;
	}
	else
	{
		temp += 0.5*dt*nu*(1/(dy[J]*(dy[J]+dy[J])*0.5));
	}

	//SOUTH
	if(J != 0)//check if on south boundary
	{
		row[numE] = i;
		col[numE] = i-(nx-1);
		val[numE] = -0.5*dt*nu*(1/(dy[J]*(dy[J-1]+dy[J])*0.5));
		temp += 0.5*dt*nu*(1/(dy[J]*(dy[J-1]+dy[J])*0.5));
		numE++;
	}
	else
	{
		temp += 0.5*dt*nu*(1/(dy[J]*(dy[J]+dy[J])*0.5));
	}

	//CENTER
	row[numE] = i;
	col[numE] = i;
	val[numE] = temp;
	numE++;
}

/*
 * calculates the boundary terms for the left hand side matrix for the velocity solve
 * param row array storing the row indices for the sparse LHS matrix
 * param col array storing the column indices for the sparse LHS matrix
 * param val array storing the values for the sparse LHS matrix
 * param dx distance between nodes in the x direction (measured between node sides, where u velocites are stored)
 * param dy distance between nodes in the y direction (measured between node top/bot, where v velocites are stored)
 * param dt change in time
 * param nu viscosity
 * param nx number of cells in x direction
 * param ny number of cells in y direction
 */
__global__
void LHS_BC_Y(int *row, int *col, double *val, double *dx, double *dy, double dt, double nu, int nx, int ny)
{
	if (threadIdx.x + blockDim.x * blockIdx.x >= nx*(ny-1))
		return;
	int ip 	= threadIdx.x + blockDim.x * blockIdx.x,
		I	= ip % nx,
		J	= ip / nx,
		i = ip + (nx-1)*ny;
	if (I != 0 && I != nx-1 && J != 0 && J != ny-2)
		return;

	int numE = (nx-1)*ny*5 - 2*ny-2*(nx-1);
	if (J == 0)
	{
		numE += I*4;
		if (I != 0)
			numE -= 1;
	}
	else if (J == ny-2)
	{
		numE += nx*4 - 2 + (J-1)*(5*nx - 2) + I*4;
		if (I != 0)
			numE-=1;
	}
	else
	{
		if (I == 0)
			numE += nx*4 - 2 + (J-1)*(5*nx - 2) + I*5;
		else
			numE += nx*4 - 2 + (J-1)*(5*nx - 2) + I*5 - 1;
	}
	double temp = 1;

	//EAST
	if(I != nx-1)//check if on east boundary
	{
		row[numE] = i;
		col[numE] = i+1;
		val[numE] = -0.5*dt*nu*(1/(dx[I]*(dx[I]+dx[I+1])*0.5));
		temp += 0.5*dt*nu*(1/(dx[I]*(dx[I]+dx[I+1])*0.5));
		numE++;
	}
	else
	{
		temp += 0.5*dt*nu*(1/(dx[I]*(dx[I]+dx[I])*0.5));
	}

	//WEST
	if(I != 0)//check if  on west boundary
	{
		row[numE] = i;
		col[numE] = i-1;
		val[numE] = -0.5*dt*nu*(1/(dx[I]*(dx[I]+dx[I-1])*0.5));
		temp += 0.5*dt*nu*(1/(dx[I]*(dx[I]+dx[I-1])*0.5));
		numE++;
	}
	else
	{
		temp += 0.5*dt*nu*(1/(dx[I]*(dx[I]+dx[I])*0.5));
	}

	//NORTH
	if(J != ny-2)//check if on north boundary
	{
		row[numE] = i;
		col[numE] = i + nx;
		val[numE] = -0.5*dt*nu*(1/(dy[J+1]*(dy[J]+dy[J+1])*0.5));
		temp += 0.5*dt*nu*(1/(dy[J+1]*(dy[J]+dy[J+1])*0.5));
		numE++;
	}
	else
	{
		temp += 0.5*dt*nu*(1/(dy[J+1]*(dy[J]+dy[J+1])*0.5));
	}

	//SOUTH
	if(J != 0)//check if on south boundary
	{
		row[numE] = i;
		col[numE] = i-nx;
		val[numE] = -0.5*dt*nu*(1/(dy[J]*(dy[J]+dy[J+1])*0.5));
		temp += 0.5*dt*nu*(1/(dy[J]*(dy[J]+dy[J+1])*0.5));
		numE++;
	}
	else
	{
		temp += 0.5*dt*nu*(1/(dy[J]*(dy[J]+dy[J+1])*0.5));
	}

	//CENTER
	row[numE] = i;
	col[numE] = i;
	val[numE] = temp;
	numE++;
}

/*
 * calculates the middle terms for the left hand side matrix for the velocity solve
 * param row array storing the row indices for the sparse LHS matrix
 * param col array storing the column indices for the sparse LHS matrix
 * param val array storing the values for the sparse LHS matrix
 * param dx distance between nodes in the x direction (measured between node sides, where u velocites are stored)
 * param dy distance between nodes in the y direction (measured between node top/bot, where v velocites are stored)
 * param dt change in time
 * param nu viscosity
 * param nx number of cells in x direction
 * param ny number of cells in y direction
 */
__global__
void LHS_mid_X_nobody(int *row, int *col, double *val, double *dx, double *dy, double dt, double nu, int nx, int ny)
{
	if (threadIdx.x + blockDim.x * blockIdx.x >= (nx-1)*ny)
		return;
	int i 	= threadIdx.x + blockDim.x * blockIdx.x,
		I	= i % (nx-1),
		J	= i / (nx-1);
	if (I == 0 || I == nx-2 || J == 0 || J == ny-1)
		return;

	//			top row - corner    mid           sides    current row
	int numE = (nx-1)*4 - 2      + (J-1)*(5*(nx-1)  - 2) + I*5 - 1;

	double temp = 1;
	//EAST
	row[numE] = i;
	col[numE] = i+1;
	val[numE] = -0.5*dt*nu*(1/(dx[I+1]*(dx[I+1]+dx[I])*0.5));
	temp += 0.5*dt*nu*(1/(dx[I+1]*(dx[I+1]+dx[I])*0.5));
	numE++;

	//WEST
	row[numE] = i;
	col[numE] = i-1;
	val[numE] = -0.5*dt*nu*(1/(dx[I]*(dx[I+1]+dx[I])*0.5));
	temp += 0.5*dt*nu*(1/(dx[I]*(dx[I+1]+dx[I])*0.5));
	numE++;

	//NORTH
	row[numE] = i;
	col[numE] = i+(nx-1);
	val[numE] = -0.5*dt*nu*(1/(dy[J]*(dy[J+1]+dy[J])*0.5));
	temp += 0.5*dt*nu*(1/(dy[J]*(dy[J+1]+dy[J])*0.5));
	numE++;

	//SOUTH
	row[numE] = i;
	col[numE] = i-(nx-1);
	val[numE] = -0.5*dt*nu*(1/(dy[J]*(dy[J-1]+dy[J])*0.5));
	temp += 0.5*dt*nu*(1/(dy[J]*(dy[J-1]+dy[J])*0.5));
	numE++;

	//CENTER
	row[numE] = i;
	col[numE] = i;
	val[numE] = temp;
	numE++;
}

/*
 * calculates the middle terms for the left hand side matrix for the velocity solve
 * param row array storing the row indices for the sparse LHS matrix
 * param col array storing the column indices for the sparse LHS matrix
 * param val array storing the values for the sparse LHS matrix
 * param dx distance between nodes in the x direction (measured between node sides, where u velocites are stored)
 * param dy distance between nodes in the y direction (measured between node top/bot, where v velocites are stored)
 * param dt change in time
 * param nu viscosity
 * param nx number of cells in x direction
 * param ny number of cells in y direction
 */
__global__
void LHS_mid_Y_nobody(int *row, int *col, double *val, double *dx, double *dy, double dt, double nu, int nx, int ny)
{
	if (threadIdx.x + blockDim.x * blockIdx.x >= nx*(ny-1))
		return;
	int ip 	= threadIdx.x + blockDim.x * blockIdx.x,
		I	= ip % nx,
		J	= ip / nx,
		i = ip + (nx-1)*ny;
	if (I == 0 || I == nx-1 || J == 0 || J == ny-2)
		return;

	//         (              numU       )     (row1)    (rows2-before me)  (current row)
	int numE = (nx-1)*ny*5 - 2*ny-2*(nx-1)  +  nx*4-2  + (J-1)*(nx*5 - 2) + I*5 - 1;
	double temp = 1;

	//EAST
	row[numE] = i;
	col[numE] = i+1;
	val[numE] = -0.5*dt*nu*(1/(dx[I]*(dx[I]+dx[I+1])*0.5));
	temp += 0.5*dt*nu*(1/(dx[I]*(dx[I]+dx[I+1])*0.5));
	numE++;

	//WEST
	row[numE] = i;
	col[numE] = i-1;
	val[numE] = -0.5*dt*nu*(1/(dx[I]*(dx[I]+dx[I-1])*0.5));
	temp += 0.5*dt*nu*(1/(dx[I]*(dx[I]+dx[I-1])*0.5));
	numE++;

	//NORTH
	row[numE] = i;
	col[numE] = i + nx;
	val[numE] = -0.5*dt*nu*(1/(dy[J+1]*(dy[J]+dy[J+1])*0.5));
	temp += 0.5*dt*nu*(1/(dy[J+1]*(dy[J]+dy[J+1])*0.5));
	numE++;

	//SOUTH
	row[numE] = i;
	col[numE] = i-nx;
	val[numE] = -0.5*dt*nu*(1/(dy[J]*(dy[J]+dy[J+1])*0.5));
	temp += 0.5*dt*nu*(1/(dy[J]*(dy[J]+dy[J+1])*0.5));
	numE++;

	//CENTER
	row[numE] = i;
	col[numE] = i;
	val[numE] = temp;
	numE++;
}
}

	.text
	.file	"LHS1.hip"
	.globl	_ZN7kernels23__device_stub__LHS_BC_XEPiS0_PdS1_S1_ddii # -- Begin function _ZN7kernels23__device_stub__LHS_BC_XEPiS0_PdS1_S1_ddii
	.type	_ZN7kernels23__device_stub__LHS_BC_XEPiS0_PdS1_S1_ddii,@function
_ZN7kernels23__device_stub__LHS_BC_XEPiS0_PdS1_S1_ddii: # @_ZN7kernels23__device_stub__LHS_BC_XEPiS0_PdS1_S1_ddii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movsd	%xmm0, (%r8)
	leaq	24(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	4(%rsp), %r11
	movl	%r9d, (%r11)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r10, 48(%rbx)
	movq	%r11, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_ZN7kernels23__device_stub__LHS_BC_XEPiS0_PdS1_S1_ddii, .Lfunc_end0-_ZN7kernels23__device_stub__LHS_BC_XEPiS0_PdS1_S1_ddii
	.cfi_endproc
                                        # -- End function
	.globl	_ZN7kernels23__device_stub__LHS_BC_YEPiS0_PdS1_S1_ddii # -- Begin function _ZN7kernels23__device_stub__LHS_BC_YEPiS0_PdS1_S1_ddii
	.type	_ZN7kernels23__device_stub__LHS_BC_YEPiS0_PdS1_S1_ddii,@function
_ZN7kernels23__device_stub__LHS_BC_YEPiS0_PdS1_S1_ddii: # @_ZN7kernels23__device_stub__LHS_BC_YEPiS0_PdS1_S1_ddii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movsd	%xmm0, (%r8)
	leaq	24(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	4(%rsp), %r11
	movl	%r9d, (%r11)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r10, 48(%rbx)
	movq	%r11, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_ZN7kernels23__device_stub__LHS_BC_YEPiS0_PdS1_S1_ddii, .Lfunc_end1-_ZN7kernels23__device_stub__LHS_BC_YEPiS0_PdS1_S1_ddii
	.cfi_endproc
                                        # -- End function
	.globl	_ZN7kernels31__device_stub__LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii # -- Begin function _ZN7kernels31__device_stub__LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii
	.type	_ZN7kernels31__device_stub__LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii,@function
_ZN7kernels31__device_stub__LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii: # @_ZN7kernels31__device_stub__LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movsd	%xmm0, (%r8)
	leaq	24(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	4(%rsp), %r11
	movl	%r9d, (%r11)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r10, 48(%rbx)
	movq	%r11, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_ZN7kernels31__device_stub__LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii, .Lfunc_end2-_ZN7kernels31__device_stub__LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii
	.cfi_endproc
                                        # -- End function
	.globl	_ZN7kernels31__device_stub__LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii # -- Begin function _ZN7kernels31__device_stub__LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii
	.type	_ZN7kernels31__device_stub__LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii,@function
_ZN7kernels31__device_stub__LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii: # @_ZN7kernels31__device_stub__LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movsd	%xmm0, (%r8)
	leaq	24(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	4(%rsp), %r11
	movl	%r9d, (%r11)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r10, 48(%rbx)
	movq	%r11, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_ZN7kernels31__device_stub__LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii, .Lfunc_end3-_ZN7kernels31__device_stub__LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii,@object # @_ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii
	.section	.rodata,"a",@progbits
	.globl	_ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii
	.p2align	3, 0x0
_ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii:
	.quad	_ZN7kernels23__device_stub__LHS_BC_XEPiS0_PdS1_S1_ddii
	.size	_ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii, 8

	.type	_ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii,@object # @_ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii
	.globl	_ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii
	.p2align	3, 0x0
_ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii:
	.quad	_ZN7kernels23__device_stub__LHS_BC_YEPiS0_PdS1_S1_ddii
	.size	_ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii, 8

	.type	_ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii,@object # @_ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii
	.globl	_ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii
	.p2align	3, 0x0
_ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii:
	.quad	_ZN7kernels31__device_stub__LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii
	.size	_ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii, 8

	.type	_ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii,@object # @_ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii
	.globl	_ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii
	.p2align	3, 0x0
_ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii:
	.quad	_ZN7kernels31__device_stub__LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii
	.size	_ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii"
	.size	.L__unnamed_1, 39

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii"
	.size	.L__unnamed_2, 39

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii"
	.size	.L__unnamed_3, 48

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii"
	.size	.L__unnamed_4, 48

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _ZN7kernels23__device_stub__LHS_BC_XEPiS0_PdS1_S1_ddii
	.addrsig_sym _ZN7kernels23__device_stub__LHS_BC_YEPiS0_PdS1_S1_ddii
	.addrsig_sym _ZN7kernels31__device_stub__LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii
	.addrsig_sym _ZN7kernels31__device_stub__LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii
	.addrsig_sym _ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii
	.addrsig_sym _ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii
	.addrsig_sym _ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii ; -- Begin function _ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii
	.globl	_ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii
	.p2align	8
	.type	_ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii,@function
_ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii: ; @_ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b64 s[20:21], s[0:1], 0x38
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_add_i32 s22, s20, -1
	v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
	s_mul_i32 s2, s22, s21
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s2, v4
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_33
; %bb.1:
	s_ashr_i32 s2, s22, 31
	v_ashrrev_i32_e32 v2, 31, v4
	s_add_i32 s3, s22, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s3, s3, s2
	v_cvt_f32_u32_e32 v0, s3
	s_sub_i32 s4, 0, s3
	v_add_nc_u32_e32 v3, v4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	v_xor_b32_e32 v3, v3, v2
	v_xor_b32_e32 v2, s2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v1, s4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v1, v0, v1
	v_add_nc_u32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v3, v0
	v_mul_lo_u32 v1, v0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v1, v3, v1
	v_add_nc_u32_e32 v3, 1, v0
	v_subrev_nc_u32_e32 v5, s3, v1
	v_cmp_le_u32_e32 vcc_lo, s3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v0, v0, v3 :: v_dual_cndmask_b32 v1, v1, v5
	v_add_nc_u32_e32 v3, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s3, v1
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v2
	v_sub_nc_u32_e32 v7, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v7, s22
	v_sub_nc_u32_e32 v15, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s5, 0, v15
	v_cmp_ne_u32_e64 s3, 0, v15
	s_mov_b32 s2, s5
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s6, s3
; %bb.2:
	s_add_i32 s2, s20, -2
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
	v_cmp_eq_u32_e64 s2, s2, v15
	s_add_i32 s4, s21, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s4, s4, v7
	s_or_b32 s2, s2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s2, s4
	s_and_not1_b32 s4, s5, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s4, s2
; %bb.3:                                ; %Flow259
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_33
; %bb.4:
	v_cmp_ne_u32_e64 s2, 0, v7
                                        ; implicit-def: $vgpr5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s2
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB0_14
; %bb.5:
	s_add_i32 s6, s21, -1
                                        ; implicit-def: $vgpr5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_ne_u32_e32 vcc_lo, s6, v7
	s_lshl_b32 s6, s22, 2
	s_and_saveexec_b32 s7, vcc_lo
	s_xor_b32 s7, exec_lo, s7
	s_cbranch_execz .LBB0_11
; %bb.6:
                                        ; implicit-def: $vgpr5
	s_and_saveexec_b32 s8, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s8, exec_lo, s8
; %bb.7:
	v_add_nc_u32_e32 v0, -1, v7
	s_mul_i32 s9, s22, 5
	v_lshl_add_u32 v1, v15, 2, v15
	s_add_i32 s9, s9, -2
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v0, v0, s9
	s_add_i32 s9, s6, -3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add3_u32 v5, s9, v1, v0
; %bb.8:                                ; %Flow253
	s_and_not1_saveexec_b32 s8, s8
; %bb.9:
	v_add_nc_u32_e32 v0, -1, v7
	s_add_i32 s10, s6, -2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s9, s10, s22
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[5:6], null, v0, s9, s[10:11]
; %bb.10:                               ; %Flow254
	s_or_b32 exec_lo, exec_lo, s8
.LBB0_11:                               ; %Flow256
	s_and_not1_saveexec_b32 s7, s7
; %bb.12:
	v_add_nc_u32_e32 v0, -1, v7
	s_add_i32 s6, s6, -2
	v_lshl_add_u32 v1, v15, 2, -1
	s_add_i32 s8, s6, s22
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v0, v0, s8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v1, v1, 0, s5
	v_add3_u32 v5, s6, v0, v1
; %bb.13:                               ; %Flow257
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_14:                               ; %Flow258
	s_and_not1_saveexec_b32 s4, s4
; %bb.15:
	v_lshl_add_u32 v0, v15, 2, -1
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v5, v0, 0, s5
; %bb.16:
	s_or_b32 exec_lo, exec_lo, s4
	s_clause 0x1
	s_load_b256 s[12:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_add_i32 s0, s20, -2
	v_ashrrev_i32_e32 v16, 31, v15
	v_cmp_ne_u32_e32 vcc_lo, s0, v15
                                        ; implicit-def: $vgpr13_vgpr14
                                        ; implicit-def: $vgpr0_vgpr1
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[11:12], s[14:15], -0.5
	v_mul_f64 v[9:10], s[14:15], 0.5
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_18
; %bb.17:
	v_lshlrev_b64 v[0:1], 3, v[15:16]
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v13, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v14, vcc_lo, s11, v1, vcc_lo
	global_load_b128 v[0:3], v[13:14], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[2:3], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[2:3], v[0:1]
	v_mul_f64 v[0:1], v[0:1], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0
	v_div_scale_f64 v[21:22], vcc_lo, 1.0, v[0:1], 1.0
	v_rcp_f64_e32 v[17:18], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[19:20], -v[2:3], v[17:18], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	v_fma_f64 v[19:20], -v[2:3], v[17:18], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	v_mul_f64 v[19:20], v[21:22], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], -v[2:3], v[19:20], v[21:22]
	v_div_fmas_f64 v[2:3], v[2:3], v[17:18], v[19:20]
	v_mul_f64 v[17:18], v[11:12], s[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0
	v_lshlrev_b64 v[2:3], 3, v[5:6]
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	v_mul_f64 v[0:1], v[17:18], v[0:1]
	global_store_b64 v[2:3], v[0:1], off
	global_load_b128 v[0:3], v[13:14], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[13:14], v[2:3], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[13:14], v[2:3], v[13:14]
	v_mul_f64 v[13:14], v[13:14], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[17:18], null, v[13:14], v[13:14], 1.0
	v_rcp_f64_e32 v[19:20], v[17:18]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	v_div_scale_f64 v[21:22], vcc_lo, 1.0, v[13:14], 1.0
	v_mul_f64 v[23:24], v[21:22], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], -v[17:18], v[23:24], v[21:22]
	v_div_fmas_f64 v[17:18], v[17:18], v[19:20], v[23:24]
	v_mul_f64 v[19:20], v[9:10], s[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_div_fixup_f64 v[13:14], v[17:18], v[13:14], 1.0
	v_lshlrev_b64 v[17:18], 2, v[5:6]
	v_add_nc_u32_e32 v5, 1, v5
	v_add_nc_u32_e32 v6, 1, v4
	v_mul_f64 v[13:14], v[19:20], v[13:14]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v19, vcc_lo, s4, v17
	v_add_co_ci_u32_e32 v20, vcc_lo, s5, v18, vcc_lo
	v_add_co_u32 v17, vcc_lo, s6, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, s7, v18, vcc_lo
	global_store_b32 v[19:20], v4, off
	global_store_b32 v[17:18], v6, off
.LBB0_18:                               ; %Flow252
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_20
; %bb.19:
	v_lshlrev_b64 v[0:1], 3, v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	global_load_b128 v[0:3], v[0:1], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[13:14], v[2:3], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[13:14], v[2:3], v[13:14]
	v_mul_f64 v[13:14], v[13:14], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[17:18], null, v[13:14], v[13:14], 1.0
	v_rcp_f64_e32 v[19:20], v[17:18]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	v_div_scale_f64 v[21:22], vcc_lo, 1.0, v[13:14], 1.0
	v_mul_f64 v[23:24], v[21:22], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], -v[17:18], v[23:24], v[21:22]
	v_div_fmas_f64 v[17:18], v[17:18], v[19:20], v[23:24]
	v_mul_f64 v[19:20], v[9:10], s[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[13:14], v[17:18], v[13:14], 1.0
	v_mul_f64 v[13:14], v[19:20], v[13:14]
.LBB0_20:
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr17_vgpr18
	s_and_saveexec_b32 s0, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_22
; %bb.21:
	v_add_f64 v[2:3], v[0:1], v[2:3]
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[15:16], 3, v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[0:1], v[2:3]
	v_mul_f64 v[0:1], v[0:1], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0
	v_div_scale_f64 v[21:22], vcc_lo, 1.0, v[0:1], 1.0
	v_rcp_f64_e32 v[17:18], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[19:20], -v[2:3], v[17:18], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	v_fma_f64 v[19:20], -v[2:3], v[17:18], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	v_mul_f64 v[19:20], v[21:22], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], -v[2:3], v[19:20], v[21:22]
	v_div_fmas_f64 v[2:3], v[2:3], v[17:18], v[19:20]
	v_mul_f64 v[17:18], v[11:12], s[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0
	v_lshlrev_b64 v[2:3], 3, v[5:6]
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	v_add_co_u32 v15, vcc_lo, s10, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, s11, v16, vcc_lo
	v_mul_f64 v[0:1], v[17:18], v[0:1]
	global_store_b64 v[2:3], v[0:1], off
	global_load_b128 v[0:3], v[15:16], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[0:1], v[2:3]
	v_mul_f64 v[0:1], v[0:1], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0
	v_rcp_f64_e32 v[15:16], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[17:18], -v[2:3], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	v_fma_f64 v[17:18], -v[2:3], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	v_div_scale_f64 v[17:18], vcc_lo, 1.0, v[0:1], 1.0
	v_mul_f64 v[19:20], v[17:18], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], -v[2:3], v[19:20], v[17:18]
	v_div_fmas_f64 v[2:3], v[2:3], v[15:16], v[19:20]
	v_mul_f64 v[15:16], v[9:10], s[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0
	v_mul_f64 v[17:18], v[15:16], v[0:1]
	v_lshlrev_b64 v[0:1], 2, v[5:6]
	v_add_nc_u32_e32 v5, 1, v5
	v_add_nc_u32_e32 v6, -1, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[2:3], v4, off
	global_store_b32 v[0:1], v6, off
.LBB0_22:                               ; %Flow251
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_24
; %bb.23:
	v_mov_b32_e32 v0, 0
	global_load_b128 v[0:3], v0, s[10:11]
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[0:1], v[2:3]
	v_mul_f64 v[0:1], v[0:1], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0
	v_rcp_f64_e32 v[15:16], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[17:18], -v[2:3], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	v_fma_f64 v[17:18], -v[2:3], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	v_div_scale_f64 v[17:18], vcc_lo, 1.0, v[0:1], 1.0
	v_mul_f64 v[19:20], v[17:18], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], -v[2:3], v[19:20], v[17:18]
	v_div_fmas_f64 v[2:3], v[2:3], v[15:16], v[19:20]
	v_mul_f64 v[15:16], v[9:10], s[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0
	v_mul_f64 v[17:18], v[15:16], v[0:1]
.LBB0_24:
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s0, s21, -1
	v_ashrrev_i32_e32 v8, 31, v7
	v_cmp_ne_u32_e32 vcc_lo, s0, v7
                                        ; implicit-def: $vgpr2_vgpr3
                                        ; implicit-def: $vgpr0_vgpr1
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_26
; %bb.25:
	v_lshlrev_b64 v[0:1], 3, v[7:8]
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v15, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v16, vcc_lo, s13, v1, vcc_lo
	global_load_b128 v[0:3], v[15:16], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[0:1], v[2:3]
	v_mul_f64 v[0:1], v[0:1], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0
	v_div_scale_f64 v[23:24], vcc_lo, 1.0, v[0:1], 1.0
	v_rcp_f64_e32 v[19:20], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[21:22], -v[2:3], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	v_fma_f64 v[21:22], -v[2:3], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	v_mul_f64 v[21:22], v[23:24], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], -v[2:3], v[21:22], v[23:24]
	v_div_fmas_f64 v[2:3], v[2:3], v[19:20], v[21:22]
	v_mul_f64 v[19:20], v[11:12], s[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0
	v_lshlrev_b64 v[2:3], 3, v[5:6]
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	v_mul_f64 v[0:1], v[19:20], v[0:1]
	global_store_b64 v[2:3], v[0:1], off
	global_load_b128 v[0:3], v[15:16], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[2:3], v[0:1], v[2:3]
	v_mul_f64 v[2:3], v[2:3], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[15:16], null, v[2:3], v[2:3], 1.0
	v_rcp_f64_e32 v[19:20], v[15:16]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[21:22], -v[15:16], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	v_fma_f64 v[21:22], -v[15:16], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	v_div_scale_f64 v[21:22], vcc_lo, 1.0, v[2:3], 1.0
	v_mul_f64 v[23:24], v[21:22], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], -v[15:16], v[23:24], v[21:22]
	v_div_fmas_f64 v[15:16], v[15:16], v[19:20], v[23:24]
	v_mul_f64 v[19:20], v[9:10], s[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_div_fixup_f64 v[2:3], v[15:16], v[2:3], 1.0
	v_lshlrev_b64 v[15:16], 2, v[5:6]
	v_add_nc_u32_e32 v5, 1, v5
	v_add_nc_u32_e32 v6, s22, v4
	v_mul_f64 v[2:3], v[19:20], v[2:3]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v19, vcc_lo, s4, v15
	v_add_co_ci_u32_e32 v20, vcc_lo, s5, v16, vcc_lo
	v_add_co_u32 v15, vcc_lo, s6, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, s7, v16, vcc_lo
	global_store_b32 v[19:20], v4, off
	global_store_b32 v[15:16], v6, off
.LBB0_26:                               ; %Flow250
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_28
; %bb.27:
	v_lshlrev_b64 v[0:1], 3, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[0:1], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[2:3], v[0:1], v[2:3]
	v_mul_f64 v[2:3], v[2:3], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[15:16], null, v[2:3], v[2:3], 1.0
	v_rcp_f64_e32 v[19:20], v[15:16]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[21:22], -v[15:16], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	v_fma_f64 v[21:22], -v[15:16], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	v_div_scale_f64 v[21:22], vcc_lo, 1.0, v[2:3], 1.0
	v_mul_f64 v[23:24], v[21:22], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], -v[15:16], v[23:24], v[21:22]
	v_div_fmas_f64 v[15:16], v[15:16], v[19:20], v[23:24]
	v_mul_f64 v[19:20], v[9:10], s[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[2:3], v[15:16], v[2:3], 1.0
	v_mul_f64 v[2:3], v[19:20], v[2:3]
.LBB0_28:
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr15_vgpr16
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_30
; %bb.29:
	v_lshlrev_b64 v[6:7], 3, v[7:8]
	v_mul_f64 v[11:12], v[11:12], s[16:17]
	v_mul_f64 v[9:10], v[9:10], s[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v15, vcc_lo, s12, v6
	v_add_co_ci_u32_e32 v16, vcc_lo, s13, v7, vcc_lo
	global_load_b64 v[6:7], v[15:16], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_f64 v[6:7], v[0:1], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[0:1], v[6:7]
	v_mul_f64 v[0:1], v[0:1], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[6:7], null, v[0:1], v[0:1], 1.0
	v_div_scale_f64 v[23:24], vcc_lo, 1.0, v[0:1], 1.0
	v_rcp_f64_e32 v[19:20], v[6:7]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[21:22], -v[6:7], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	v_fma_f64 v[21:22], -v[6:7], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	v_mul_f64 v[21:22], v[23:24], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], -v[6:7], v[21:22], v[23:24]
	v_div_fmas_f64 v[6:7], v[6:7], v[19:20], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[6:7], v[0:1], 1.0
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[7:8], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s8, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
	v_mul_f64 v[0:1], v[11:12], v[0:1]
	global_store_b64 v[7:8], v[0:1], off
	global_load_b128 v[19:22], v[15:16], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[21:22], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[21:22], v[0:1]
	v_mul_f64 v[0:1], v[0:1], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[7:8], null, v[0:1], v[0:1], 1.0
	v_rcp_f64_e32 v[11:12], v[7:8]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[15:16], -v[7:8], v[11:12], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[11:12], v[15:16], v[11:12]
	v_fma_f64 v[15:16], -v[7:8], v[11:12], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[11:12], v[15:16], v[11:12]
	v_div_scale_f64 v[15:16], vcc_lo, 1.0, v[0:1], 1.0
	v_mul_f64 v[19:20], v[15:16], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], -v[7:8], v[19:20], v[15:16]
	v_div_fmas_f64 v[7:8], v[7:8], v[11:12], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[0:1], v[7:8], v[0:1], 1.0
	v_subrev_nc_u32_e32 v8, s22, v4
	v_mul_f64 v[15:16], v[9:10], v[0:1]
	v_lshlrev_b64 v[0:1], 2, v[5:6]
	v_add_nc_u32_e32 v5, 1, v5
                                        ; implicit-def: $vgpr9_vgpr10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[6:7], v4, off
	global_store_b32 v[0:1], v8, off
.LBB0_30:                               ; %Flow
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_32
; %bb.31:
	v_mov_b32_e32 v0, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[9:10], s[16:17]
	global_load_b64 v[0:1], v0, s[12:13]
	s_waitcnt vmcnt(0)
	v_add_f64 v[6:7], v[0:1], v[0:1]
	v_mul_f64 v[0:1], v[0:1], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[0:1], 0.5
	v_div_scale_f64 v[6:7], null, v[0:1], v[0:1], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[11:12], v[6:7]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[15:16], -v[6:7], v[11:12], 1.0
	v_fma_f64 v[11:12], v[11:12], v[15:16], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], -v[6:7], v[11:12], 1.0
	v_fma_f64 v[11:12], v[11:12], v[15:16], v[11:12]
	v_div_scale_f64 v[15:16], vcc_lo, 1.0, v[0:1], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[19:20], v[15:16], v[11:12]
	v_fma_f64 v[6:7], -v[6:7], v[19:20], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[6:7], v[6:7], v[11:12], v[19:20]
	v_div_fixup_f64 v[0:1], v[6:7], v[0:1], 1.0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[15:16], v[8:9], v[0:1]
.LBB0_32:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[0:1], v[13:14], 1.0
	v_ashrrev_i32_e32 v6, 31, v5
	v_add_f64 v[0:1], v[0:1], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[0:1], v[0:1], v[2:3]
	v_lshlrev_b64 v[2:3], 2, v[5:6]
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v5, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	v_add_f64 v[0:1], v[0:1], v[15:16]
	global_store_b32 v[7:8], v4, off
	global_store_b32 v[2:3], v4, off
	global_store_b64 v[5:6], v[0:1], off
.LBB0_33:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 25
		.amdhsa_next_free_sgpr 23
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii, .Lfunc_end0-_ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3400
; NumSgprs: 25
; NumVgprs: 25
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 25
; NumVGPRsForWavesPerEU: 25
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii ; -- Begin function _ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii
	.globl	_ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii
	.p2align	8
	.type	_ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii,@function
_ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii: ; @_ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b64 s[20:21], s[0:1], 0x38
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_add_i32 s2, s21, -1
	s_mul_i32 s2, s2, s20
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB1_33
; %bb.1:
	s_ashr_i32 s2, s20, 31
	v_ashrrev_i32_e32 v3, 31, v1
	s_add_i32 s3, s20, s2
	s_add_i32 s23, s20, -1
	s_xor_b32 s3, s3, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v1, v3
	v_cvt_f32_u32_e32 v0, s3
	s_sub_i32 s4, 0, s3
	v_xor_b32_e32 v4, v4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	v_xor_b32_e32 v3, s2, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, s4, v0
	v_mul_hi_u32 v2, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v2
	v_mul_hi_u32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v0, s3
	v_sub_nc_u32_e32 v2, v4, v2
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v5, s3, v2
	v_cmp_le_u32_e32 vcc_lo, s3, v2
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, v2, v5, vcc_lo
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s3, v2
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v3
	v_sub_nc_u32_e32 v6, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v6, s20
	v_sub_nc_u32_e32 v16, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s22, 0, v16
	v_cmp_ne_u32_e32 vcc_lo, 0, v16
	s_mov_b32 s2, s22
	s_and_saveexec_b32 s5, vcc_lo
; %bb.2:
	v_cmp_eq_u32_e64 s2, s23, v16
	v_cmp_eq_u32_e64 s3, 0, v6
	s_add_i32 s4, s21, -2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s4, s4, v6
	s_or_b32 s2, s2, s3
	s_and_not1_b32 s3, s22, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s2, s4
	s_and_b32 s2, s2, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s3, s2
; %bb.3:                                ; %Flow269
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB1_33
; %bb.4:
	s_mul_i32 s24, s23, s21
	s_add_i32 s3, s23, s21
	v_cmp_ne_u32_e64 s2, 0, v6
	s_mul_i32 s4, s24, 5
	s_lshl_b32 s3, s3, 1
                                        ; implicit-def: $vgpr4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_sub_i32 s4, s4, s3
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s5, exec_lo, s3
	s_cbranch_execz .LBB1_14
; %bb.5:
	s_add_i32 s3, s21, -2
                                        ; implicit-def: $vgpr4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ne_u32_e64 s3, s3, v6
	s_and_saveexec_b32 s6, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s6
	s_cbranch_execz .LBB1_11
; %bb.6:
	s_lshl_b32 s6, s20, 2
                                        ; implicit-def: $vgpr4
	s_and_saveexec_b32 s7, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s7, exec_lo, s7
; %bb.7:
	v_add_nc_u32_e32 v0, -1, v6
	s_add_i32 s8, s6, -2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s9, s8, s20
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v0, v0, s9
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v4, s8, s4, v0
; %bb.8:                                ; %Flow263
	s_and_not1_saveexec_b32 s7, s7
; %bb.9:
	v_add_nc_u32_e32 v0, -1, v6
	s_mul_i32 s8, s20, 5
	v_lshl_add_u32 v2, v16, 2, v16
	s_add_i32 s8, s8, -2
	s_add_i32 s6, s6, s4
	v_mul_lo_u32 v0, v0, s8
	s_add_i32 s6, s6, -3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add3_u32 v4, s6, v2, v0
; %bb.10:                               ; %Flow264
	s_or_b32 exec_lo, exec_lo, s7
.LBB1_11:                               ; %Flow266
	s_and_not1_saveexec_b32 s3, s3
; %bb.12:
	v_cndmask_b32_e64 v0, 0, 1, vcc_lo
	v_add_nc_u32_e32 v2, -1, v6
	s_mul_i32 s6, s20, 5
	v_add_nc_u32_e32 v3, s20, v16
	s_add_i32 s6, s6, -2
	v_sub_nc_u32_e32 v0, s4, v0
	v_mul_lo_u32 v2, v2, s6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v0, v3, 2, v0
	v_add3_u32 v4, v0, v2, -2
; %bb.13:                               ; %Flow267
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_14:                               ; %Flow268
	s_and_not1_saveexec_b32 s3, s5
; %bb.15:
	v_lshlrev_b32_e32 v0, 2, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, s4, -1, v0
	v_cndmask_b32_e32 v4, s4, v0, vcc_lo
; %bb.16:
	s_or_b32 exec_lo, exec_lo, s3
	s_clause 0x1
	s_load_b256 s[12:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	v_add_nc_u32_e32 v20, s24, v1
	v_ashrrev_i32_e32 v17, 31, v16
	s_mov_b32 s0, exec_lo
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $vgpr0_vgpr1
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[10:11], s[14:15], -0.5
	v_mul_f64 v[8:9], s[14:15], 0.5
	v_cmpx_ne_u32_e64 s23, v16
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB1_18
; %bb.17:
	v_lshlrev_b64 v[0:1], 3, v[16:17]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v12, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v13, vcc_lo, s11, v1, vcc_lo
	global_load_b128 v[0:3], v[12:13], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[0:1], v[2:3]
	v_mul_f64 v[0:1], v[0:1], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0
	v_div_scale_f64 v[21:22], vcc_lo, 1.0, v[0:1], 1.0
	v_rcp_f64_e32 v[14:15], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[2:3], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
	v_fma_f64 v[18:19], -v[2:3], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
	v_mul_f64 v[18:19], v[21:22], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], -v[2:3], v[18:19], v[21:22]
	v_div_fmas_f64 v[2:3], v[2:3], v[14:15], v[18:19]
	v_mul_f64 v[14:15], v[10:11], s[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0
	v_lshlrev_b64 v[2:3], 3, v[4:5]
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	v_mul_f64 v[0:1], v[14:15], v[0:1]
	global_store_b64 v[2:3], v[0:1], off
	global_load_b128 v[0:3], v[12:13], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[2:3], v[0:1], v[2:3]
	v_mul_f64 v[2:3], v[2:3], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[12:13], null, v[2:3], v[2:3], 1.0
	v_rcp_f64_e32 v[14:15], v[12:13]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
	v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
	v_div_scale_f64 v[18:19], vcc_lo, 1.0, v[2:3], 1.0
	v_mul_f64 v[21:22], v[18:19], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], -v[12:13], v[21:22], v[18:19]
	v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[21:22]
	v_mul_f64 v[14:15], v[8:9], s[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[2:3], v[12:13], v[2:3], 1.0
	v_mul_f64 v[12:13], v[14:15], v[2:3]
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	v_add_nc_u32_e32 v4, 1, v4
	v_add_nc_u32_e32 v5, 1, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v14, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v15, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	global_store_b32 v[14:15], v20, off
	global_store_b32 v[2:3], v5, off
.LBB1_18:                               ; %Flow262
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB1_20
; %bb.19:
	v_lshlrev_b64 v[0:1], 3, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[0:1], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[2:3], v[0:1], v[2:3]
	v_mul_f64 v[2:3], v[2:3], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[12:13], null, v[2:3], v[2:3], 1.0
	v_rcp_f64_e32 v[14:15], v[12:13]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
	v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
	v_div_scale_f64 v[18:19], vcc_lo, 1.0, v[2:3], 1.0
	v_mul_f64 v[21:22], v[18:19], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], -v[12:13], v[21:22], v[18:19]
	v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[21:22]
	v_mul_f64 v[14:15], v[8:9], s[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[2:3], v[12:13], v[2:3], 1.0
	v_mul_f64 v[12:13], v[14:15], v[2:3]
.LBB1_20:
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr14_vgpr15
	s_and_saveexec_b32 s0, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB1_22
; %bb.21:
	v_mov_b32_e32 v0, 0
	global_load_b64 v[0:1], v0, s[10:11]
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[0:1], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[0:1], v[2:3]
	v_mul_f64 v[0:1], v[0:1], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0
	v_rcp_f64_e32 v[14:15], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[2:3], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	v_fma_f64 v[16:17], -v[2:3], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	v_div_scale_f64 v[16:17], vcc_lo, 1.0, v[0:1], 1.0
	v_mul_f64 v[18:19], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], -v[2:3], v[18:19], v[16:17]
                                        ; implicit-def: $vgpr16
	v_div_fmas_f64 v[2:3], v[2:3], v[14:15], v[18:19]
	v_mul_f64 v[14:15], v[8:9], s[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0
	v_mul_f64 v[14:15], v[14:15], v[0:1]
                                        ; implicit-def: $vgpr0_vgpr1
.LBB1_22:                               ; %Flow261
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB1_24
; %bb.23:
	v_lshlrev_b64 v[2:3], 3, v[16:17]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	global_load_b64 v[14:15], v[2:3], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_f64 v[14:15], v[0:1], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[0:1], v[14:15]
	v_mul_f64 v[0:1], v[0:1], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[14:15], null, v[0:1], v[0:1], 1.0
	v_div_scale_f64 v[21:22], vcc_lo, 1.0, v[0:1], 1.0
	v_rcp_f64_e32 v[16:17], v[14:15]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[14:15], v[16:17], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
	v_fma_f64 v[18:19], -v[14:15], v[16:17], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
	v_mul_f64 v[18:19], v[21:22], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], -v[14:15], v[18:19], v[21:22]
	v_div_fmas_f64 v[14:15], v[14:15], v[16:17], v[18:19]
	v_mul_f64 v[16:17], v[10:11], s[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[14:15], v[0:1], 1.0
	v_lshlrev_b64 v[14:15], 3, v[4:5]
	v_add_co_u32 v14, vcc_lo, s8, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v15, vcc_lo, s9, v15, vcc_lo
	v_mul_f64 v[0:1], v[16:17], v[0:1]
	global_store_b64 v[14:15], v[0:1], off
	global_load_b128 v[0:3], v[2:3], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[2:3], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[2:3], v[0:1]
	v_mul_f64 v[0:1], v[0:1], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0
	v_rcp_f64_e32 v[14:15], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[2:3], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	v_fma_f64 v[16:17], -v[2:3], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	v_div_scale_f64 v[16:17], vcc_lo, 1.0, v[0:1], 1.0
	v_mul_f64 v[18:19], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], -v[2:3], v[18:19], v[16:17]
	v_div_fmas_f64 v[2:3], v[2:3], v[14:15], v[18:19]
	v_mul_f64 v[14:15], v[8:9], s[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0
	v_mul_f64 v[14:15], v[14:15], v[0:1]
	v_lshlrev_b64 v[0:1], 2, v[4:5]
	v_add_nc_u32_e32 v4, 1, v4
	v_add_nc_u32_e32 v5, -1, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[2:3], v20, off
	global_store_b32 v[0:1], v5, off
.LBB1_24:
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s0, s21, -2
	v_ashrrev_i32_e32 v7, 31, v6
	v_cmp_ne_u32_e32 vcc_lo, s0, v6
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $vgpr0_vgpr1
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB1_26
; %bb.25:
	v_lshlrev_b64 v[0:1], 3, v[6:7]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v16, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v17, vcc_lo, s13, v1, vcc_lo
	global_load_b128 v[0:3], v[16:17], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[2:3], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[2:3], v[0:1]
	v_mul_f64 v[0:1], v[0:1], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0
	v_div_scale_f64 v[23:24], vcc_lo, 1.0, v[0:1], 1.0
	v_rcp_f64_e32 v[18:19], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[21:22], -v[2:3], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[18:19], v[21:22], v[18:19]
	v_fma_f64 v[21:22], -v[2:3], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[18:19], v[21:22], v[18:19]
	v_mul_f64 v[21:22], v[23:24], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], -v[2:3], v[21:22], v[23:24]
	v_div_fmas_f64 v[2:3], v[2:3], v[18:19], v[21:22]
	v_mul_f64 v[18:19], v[10:11], s[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0
	v_lshlrev_b64 v[2:3], 3, v[4:5]
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	v_mul_f64 v[0:1], v[18:19], v[0:1]
	global_store_b64 v[2:3], v[0:1], off
	global_load_b128 v[0:3], v[16:17], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[16:17], v[2:3], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[16:17], v[2:3], v[16:17]
	v_mul_f64 v[16:17], v[16:17], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[18:19], null, v[16:17], v[16:17], 1.0
	v_rcp_f64_e32 v[21:22], v[18:19]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[23:24], -v[18:19], v[21:22], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], v[21:22], v[23:24], v[21:22]
	v_fma_f64 v[23:24], -v[18:19], v[21:22], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], v[21:22], v[23:24], v[21:22]
	v_div_scale_f64 v[23:24], vcc_lo, 1.0, v[16:17], 1.0
	v_mul_f64 v[25:26], v[23:24], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], -v[18:19], v[25:26], v[23:24]
	v_div_fmas_f64 v[18:19], v[18:19], v[21:22], v[25:26]
	v_mul_f64 v[21:22], v[8:9], s[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_div_fixup_f64 v[16:17], v[18:19], v[16:17], 1.0
	v_lshlrev_b64 v[18:19], 2, v[4:5]
	v_add_nc_u32_e32 v4, 1, v4
	v_add_nc_u32_e32 v5, s20, v20
	v_mul_f64 v[16:17], v[21:22], v[16:17]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v21, vcc_lo, s4, v18
	v_add_co_ci_u32_e32 v22, vcc_lo, s5, v19, vcc_lo
	v_add_co_u32 v18, vcc_lo, s6, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, s7, v19, vcc_lo
	global_store_b32 v[21:22], v20, off
	global_store_b32 v[18:19], v5, off
.LBB1_26:                               ; %Flow260
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB1_28
; %bb.27:
	v_lshlrev_b64 v[0:1], 3, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
	global_load_b128 v[0:3], v[0:1], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[16:17], v[2:3], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[16:17], v[2:3], v[16:17]
	v_mul_f64 v[16:17], v[16:17], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[18:19], null, v[16:17], v[16:17], 1.0
	v_rcp_f64_e32 v[21:22], v[18:19]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[23:24], -v[18:19], v[21:22], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], v[21:22], v[23:24], v[21:22]
	v_fma_f64 v[23:24], -v[18:19], v[21:22], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], v[21:22], v[23:24], v[21:22]
	v_div_scale_f64 v[23:24], vcc_lo, 1.0, v[16:17], 1.0
	v_mul_f64 v[25:26], v[23:24], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], -v[18:19], v[25:26], v[23:24]
	v_div_fmas_f64 v[18:19], v[18:19], v[21:22], v[25:26]
	v_mul_f64 v[21:22], v[8:9], s[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[16:17], v[18:19], v[16:17], 1.0
	v_mul_f64 v[16:17], v[21:22], v[16:17]
.LBB1_28:
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr18_vgpr19
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB1_30
; %bb.29:
	v_add_f64 v[2:3], v[0:1], v[2:3]
	v_mul_f64 v[10:11], v[10:11], s[16:17]
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[0:1], v[2:3]
	v_mul_f64 v[0:1], v[0:1], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0
	v_div_scale_f64 v[23:24], vcc_lo, 1.0, v[0:1], 1.0
	v_rcp_f64_e32 v[18:19], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[21:22], -v[2:3], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[18:19], v[21:22], v[18:19]
	v_fma_f64 v[21:22], -v[2:3], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[18:19], v[21:22], v[18:19]
	v_mul_f64 v[21:22], v[23:24], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], -v[2:3], v[21:22], v[23:24]
	v_div_fmas_f64 v[2:3], v[2:3], v[18:19], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0
	v_lshlrev_b64 v[2:3], 3, v[4:5]
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s12, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s13, v7, vcc_lo
	v_mul_f64 v[0:1], v[10:11], v[0:1]
	global_store_b64 v[2:3], v[0:1], off
	global_load_b128 v[0:3], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[0:1], v[2:3]
	v_mul_f64 v[0:1], v[0:1], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0
	v_rcp_f64_e32 v[6:7], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
	v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
	v_div_scale_f64 v[10:11], vcc_lo, 1.0, v[0:1], 1.0
	v_mul_f64 v[18:19], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], -v[2:3], v[18:19], v[10:11]
	v_div_fmas_f64 v[2:3], v[2:3], v[6:7], v[18:19]
	v_mul_f64 v[6:7], v[8:9], s[16:17]
                                        ; implicit-def: $vgpr8_vgpr9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0
	v_mul_f64 v[18:19], v[6:7], v[0:1]
	v_lshlrev_b64 v[0:1], 2, v[4:5]
	v_add_nc_u32_e32 v4, 1, v4
	v_subrev_nc_u32_e32 v5, s20, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[2:3], v20, off
	global_store_b32 v[0:1], v5, off
.LBB1_30:                               ; %Flow
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB1_32
; %bb.31:
	v_mov_b32_e32 v0, 0
	global_load_b128 v[0:3], v0, s[12:13]
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[0:1], v[2:3]
	v_mul_f64 v[0:1], v[0:1], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0
	v_rcp_f64_e32 v[5:6], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[10:11], -v[2:3], v[5:6], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], v[10:11], v[5:6]
	v_fma_f64 v[10:11], -v[2:3], v[5:6], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], v[10:11], v[5:6]
	v_div_scale_f64 v[10:11], vcc_lo, 1.0, v[0:1], 1.0
	v_mul_f64 v[18:19], v[10:11], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], -v[2:3], v[18:19], v[10:11]
	v_div_fmas_f64 v[2:3], v[2:3], v[5:6], v[18:19]
	v_mul_f64 v[5:6], v[8:9], s[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0
	v_mul_f64 v[18:19], v[5:6], v[0:1]
.LBB1_32:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[12:13], 1.0
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v4, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	v_add_f64 v[0:1], v[0:1], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], v[16:17]
	v_add_f64 v[0:1], v[0:1], v[18:19]
	global_store_b32 v[6:7], v20, off
	global_store_b32 v[2:3], v20, off
	global_store_b64 v[4:5], v[0:1], off
.LBB1_33:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 27
		.amdhsa_next_free_sgpr 25
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii, .Lfunc_end1-_ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3444
; NumSgprs: 27
; NumVgprs: 27
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 27
; NumVGPRsForWavesPerEU: 27
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii ; -- Begin function _ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii
	.globl	_ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii
	.p2align	8
	.type	_ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii,@function
_ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii: ; @_ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x4c
	s_load_b64 s[2:3], s[0:1], 0x38
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_add_i32 s20, s2, -1
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_mul_i32 s4, s20, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s4, v1
	s_and_saveexec_b32 s4, vcc_lo
	s_cbranch_execz .LBB2_4
; %bb.1:
	s_ashr_i32 s4, s20, 31
	v_ashrrev_i32_e32 v3, 31, v1
	s_add_i32 s5, s20, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s5, s5, s4
	v_add_nc_u32_e32 v4, v1, v3
	v_cvt_f32_u32_e32 v0, s5
	s_sub_i32 s6, 0, s5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v4, v3
	v_rcp_iflag_f32_e32 v0, v0
	v_xor_b32_e32 v3, s4, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v2, s6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v0, v2
	v_add_nc_u32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v4, v0
	v_mul_lo_u32 v2, v0, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v4, v2
	v_add_nc_u32_e32 v4, 1, v0
	v_subrev_nc_u32_e32 v5, s5, v2
	v_cmp_le_u32_e32 vcc_lo, s5, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_cndmask_b32_e32 v2, v2, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, 1, v0
	v_cmp_le_u32_e32 vcc_lo, s5, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_xor_b32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v0, v3
	v_mul_lo_u32 v0, v2, s20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v1, v0
	v_cmp_ne_u32_e32 vcc_lo, 0, v3
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_4
; %bb.2:
	s_add_i32 s2, s2, -2
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	v_cmp_ne_u32_e64 s2, s2, v3
	s_add_i32 s3, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e64 s3, s3, v2
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB2_4
; %bb.3:
	s_load_b256 s[12:19], s[0:1], 0x0
	v_ashrrev_i32_e32 v4, 31, v3
	s_load_b256 s[4:11], s[0:1], 0x20
	s_lshl_b32 s0, s20, 2
	v_add_nc_u32_e32 v0, -1, v2
	s_add_i32 s0, s0, -2
	v_lshlrev_b64 v[4:5], 3, v[3:4]
	s_add_i32 s1, s0, s20
	v_lshl_add_u32 v3, v3, 2, v3
	v_mul_lo_u32 v0, v0, s1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, vcc_lo, s18, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, s19, v5, vcc_lo
	global_load_b128 v[4:7], v[8:9], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[6:7], v[4:5]
	v_mul_f64 v[4:5], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[4:5], v[4:5], 0.5
	v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], 1.0
	v_div_scale_f64 v[14:15], vcc_lo, 1.0, v[4:5], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[10:11], v[6:7]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[12:13], -v[6:7], v[10:11], 1.0
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], -v[6:7], v[10:11], 1.0
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[12:13], v[14:15], v[10:11]
	v_fma_f64 v[6:7], -v[6:7], v[12:13], v[14:15]
	v_mul_f64 v[14:15], s[6:7], -0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[12:13]
	v_mul_f64 v[10:11], v[14:15], s[8:9]
	v_add3_u32 v12, s0, v3, v0
	v_add_nc_u32_e32 v0, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v13, 31, v12
	v_div_fixup_f64 v[4:5], v[6:7], v[4:5], 1.0
	v_lshlrev_b64 v[6:7], 3, v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, s16, v6
	v_add_co_ci_u32_e32 v15, vcc_lo, s17, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_mul_f64 v[4:5], v[10:11], v[4:5]
	global_store_b64 v[14:15], v[4:5], off offset:-8
	global_load_b128 v[3:6], v[8:9], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[16:17], v[5:6], v[3:4]
	v_mul_f64 v[5:6], v[5:6], v[16:17]
	v_mul_f64 v[3:4], v[3:4], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[16:17], v[5:6], 0.5
	v_mul_f64 v[3:4], v[3:4], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[5:6], null, v[16:17], v[16:17], 1.0
	v_div_scale_f64 v[18:19], null, v[3:4], v[3:4], 1.0
	v_div_scale_f64 v[28:29], vcc_lo, 1.0, v[16:17], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[20:21], v[5:6]
	v_rcp_f64_e32 v[22:23], v[18:19]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[24:25], -v[5:6], v[20:21], 1.0
	v_fma_f64 v[26:27], -v[18:19], v[22:23], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[20:21], v[24:25], v[20:21]
	v_fma_f64 v[22:23], v[22:23], v[26:27], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[24:25], -v[5:6], v[20:21], 1.0
	v_fma_f64 v[26:27], -v[18:19], v[22:23], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[20:21], v[20:21], v[24:25], v[20:21]
	v_div_scale_f64 v[24:25], s0, 1.0, v[3:4], 1.0
	v_fma_f64 v[22:23], v[22:23], v[26:27], v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[26:27], v[28:29], v[20:21]
	v_mul_f64 v[30:31], v[24:25], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[5:6], -v[5:6], v[26:27], v[28:29]
	v_fma_f64 v[18:19], -v[18:19], v[30:31], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[20:21], v[5:6], v[20:21], v[26:27]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[5:6], v[18:19], v[22:23], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[16:17], v[20:21], v[16:17], 1.0
	v_div_fixup_f64 v[3:4], v[5:6], v[3:4], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f64 v[4:5], v[10:11], v[3:4]
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v18, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v3, vcc_lo
	global_store_b64 v[14:15], v[4:5], off
	global_load_b128 v[2:5], v[8:9], off
	global_load_b128 v[6:9], v[18:19], off
	s_waitcnt vmcnt(1)
	v_add_f64 v[4:5], v[2:3], v[4:5]
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[2:3], v[2:3], v[4:5]
	v_mul_f64 v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[6:7], v[2:3], 0.5
	v_mul_f64 v[2:3], v[4:5], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, v[6:7], v[6:7], 1.0
	v_div_scale_f64 v[8:9], null, v[2:3], v[2:3], 1.0
	v_div_scale_f64 v[30:31], vcc_lo, 1.0, v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[22:23], v[4:5]
	v_rcp_f64_e32 v[24:25], v[8:9]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[26:27], -v[4:5], v[22:23], 1.0
	v_fma_f64 v[28:29], -v[8:9], v[24:25], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[22:23], v[22:23], v[26:27], v[22:23]
	v_fma_f64 v[24:25], v[24:25], v[28:29], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[26:27], -v[4:5], v[22:23], 1.0
	v_fma_f64 v[28:29], -v[8:9], v[24:25], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[22:23], v[22:23], v[26:27], v[22:23]
	v_div_scale_f64 v[26:27], s0, 1.0, v[2:3], 1.0
	v_fma_f64 v[24:25], v[24:25], v[28:29], v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[28:29], v[30:31], v[22:23]
	v_mul_f64 v[32:33], v[26:27], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[4:5], -v[4:5], v[28:29], v[30:31]
	v_fma_f64 v[8:9], -v[8:9], v[32:33], v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[22:23], v[4:5], v[22:23], v[28:29]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[4:5], v[8:9], v[24:25], v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[6:7], v[22:23], v[6:7], 1.0
	v_div_fixup_f64 v[2:3], v[4:5], v[2:3], 1.0
	v_lshlrev_b64 v[4:5], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s12, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v5, vcc_lo
	v_add_co_u32 v12, vcc_lo, s14, v4
	v_add_co_ci_u32_e32 v13, vcc_lo, s15, v5, vcc_lo
	v_add_nc_u32_e32 v4, -1, v1
	v_add_nc_u32_e32 v5, s20, v1
	v_mul_f64 v[2:3], v[10:11], v[2:3]
	global_store_b32 v[8:9], v1, off offset:-4
	global_store_b32 v[12:13], v0, off offset:-4
	global_store_b32 v[8:9], v1, off
	global_store_b32 v[12:13], v4, off
	global_store_b32 v[8:9], v1, off offset:4
	global_store_b32 v[12:13], v5, off offset:4
	global_store_b64 v[14:15], v[2:3], off offset:8
	s_clause 0x1
	global_load_b64 v[24:25], v[18:19], off offset:8
	global_load_b128 v[2:5], v[18:19], off offset:-8
	v_subrev_nc_u32_e32 v0, s20, v1
	s_waitcnt vmcnt(0)
	v_add_f64 v[24:25], v[4:5], v[24:25]
	v_add_f64 v[2:3], v[4:5], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[24:25], v[4:5], v[24:25]
	v_mul_f64 v[2:3], v[4:5], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[24:25], v[24:25], 0.5
	v_mul_f64 v[2:3], v[2:3], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, v[24:25], v[24:25], 1.0
	v_div_scale_f64 v[26:27], null, v[2:3], v[2:3], 1.0
	v_div_scale_f64 v[36:37], vcc_lo, 1.0, v[24:25], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[28:29], v[4:5]
	v_rcp_f64_e32 v[30:31], v[26:27]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[32:33], -v[4:5], v[28:29], 1.0
	v_fma_f64 v[34:35], -v[26:27], v[30:31], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[28:29], v[28:29], v[32:33], v[28:29]
	v_fma_f64 v[30:31], v[30:31], v[34:35], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[32:33], -v[4:5], v[28:29], 1.0
	v_fma_f64 v[34:35], -v[26:27], v[30:31], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[28:29], v[28:29], v[32:33], v[28:29]
	v_div_scale_f64 v[32:33], s0, 1.0, v[2:3], 1.0
	v_fma_f64 v[30:31], v[30:31], v[34:35], v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[34:35], v[36:37], v[28:29]
	v_mul_f64 v[38:39], v[32:33], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[4:5], -v[4:5], v[34:35], v[36:37]
	v_fma_f64 v[26:27], -v[26:27], v[38:39], v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[28:29], v[4:5], v[28:29], v[34:35]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[4:5], v[26:27], v[30:31], v[38:39]
	v_mul_f64 v[26:27], s[6:7], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[2:3], v[4:5], v[2:3], 1.0
	v_mul_f64 v[26:27], v[26:27], s[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[2:3], v[10:11], v[2:3]
	v_fma_f64 v[16:17], v[26:27], v[16:17], 1.0
	global_store_b64 v[14:15], v[2:3], off offset:16
	global_load_b128 v[2:5], v[18:19], off offset:-8
	v_fma_f64 v[6:7], v[26:27], v[6:7], v[16:17]
	v_div_fixup_f64 v[16:17], v[28:29], v[24:25], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[26:27], v[16:17], v[6:7]
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[4:5], v[2:3]
	v_mul_f64 v[2:3], v[4:5], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[2:3], v[2:3], 0.5
	v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[10:11], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[4:5], v[10:11], 1.0
	v_fma_f64 v[10:11], v[10:11], v[18:19], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], -v[4:5], v[10:11], 1.0
	v_fma_f64 v[10:11], v[10:11], v[18:19], v[10:11]
	v_div_scale_f64 v[18:19], vcc_lo, 1.0, v[2:3], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[20:21], v[18:19], v[10:11]
	v_fma_f64 v[4:5], -v[4:5], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[4:5], v[4:5], v[10:11], v[20:21]
	v_div_fixup_f64 v[2:3], v[4:5], v[2:3], 1.0
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[2:3], v[26:27], v[2:3], v[6:7]
	global_store_b32 v[8:9], v1, off offset:8
	global_store_b32 v[12:13], v0, off offset:8
	global_store_b32 v[8:9], v1, off offset:12
	global_store_b32 v[12:13], v1, off offset:12
	global_store_b64 v[14:15], v[2:3], off offset:24
.LBB2_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 40
		.amdhsa_next_free_sgpr 21
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii, .Lfunc_end2-_ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1912
; NumSgprs: 23
; NumVgprs: 40
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 40
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii ; -- Begin function _ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii
	.globl	_ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii
	.p2align	8
	.type	_ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii,@function
_ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii: ; @_ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b64 s[20:21], s[0:1], 0x38
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_add_i32 s2, s21, -1
	s_mul_i32 s2, s2, s20
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB3_4
; %bb.1:
	s_ashr_i32 s2, s20, 31
	v_ashrrev_i32_e32 v3, 31, v1
	s_add_i32 s3, s20, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s3, s3, s2
	v_add_nc_u32_e32 v4, v1, v3
	v_cvt_f32_u32_e32 v0, s3
	s_sub_i32 s4, 0, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v4, v3
	v_rcp_iflag_f32_e32 v0, v0
	v_xor_b32_e32 v3, s2, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v2, s4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v0, v2
	v_add_nc_u32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v4, v0
	v_mul_lo_u32 v2, v0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v4, v2
	v_add_nc_u32_e32 v4, 1, v0
	v_subrev_nc_u32_e32 v5, s3, v2
	v_cmp_le_u32_e32 vcc_lo, s3, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_cndmask_b32_e32 v2, v2, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, 1, v0
	v_cmp_le_u32_e32 vcc_lo, s3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_xor_b32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v3
	v_mul_lo_u32 v2, v0, s20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v1, v2
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_4
; %bb.2:
	s_add_i32 s22, s20, -1
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
	v_cmp_ne_u32_e64 s2, s22, v2
	s_add_i32 s3, s21, -2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e64 s3, s3, v0
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB3_4
; %bb.3:
	s_load_b256 s[12:19], s[0:1], 0x0
	v_ashrrev_i32_e32 v3, 31, v2
	s_load_b256 s[4:11], s[0:1], 0x20
	s_mul_i32 s0, s20, 5
	s_mul_i32 s1, s22, s21
	s_add_i32 s0, s0, -2
	v_lshlrev_b64 v[3:4], 3, v[2:3]
	s_add_i32 s22, s22, s21
	v_add_nc_u32_e32 v39, s1, v1
	s_lshl_b32 s2, s22, 1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v1, 1, v39
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v7, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, s19, v4, vcc_lo
	global_load_b128 v[3:6], v[7:8], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[5:6], v[3:4], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[3:4], v[3:4], v[5:6]
	v_mul_f64 v[3:4], v[3:4], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[5:6], null, v[3:4], v[3:4], 1.0
	v_div_scale_f64 v[13:14], vcc_lo, 1.0, v[3:4], 1.0
	v_rcp_f64_e32 v[9:10], v[5:6]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[11:12], -v[5:6], v[9:10], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	v_fma_f64 v[11:12], -v[5:6], v[9:10], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	v_mul_f64 v[11:12], v[13:14], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[5:6], -v[5:6], v[11:12], v[13:14]
	v_mul_f64 v[13:14], s[6:7], -0.5
	v_div_fmas_f64 v[5:6], v[5:6], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[9:10], v[13:14], s[8:9]
	v_div_fixup_f64 v[3:4], v[5:6], v[3:4], 1.0
	v_add_nc_u32_e32 v5, -1, v0
	v_add_nc_u32_e32 v6, s1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v5, v5, s0
	s_sub_i32 s0, s0, s20
	s_sub_i32 s0, s0, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f64 v[2:3], v[9:10], v[3:4]
	v_lshl_add_u32 v4, v6, 2, v6
	v_add3_u32 v4, s0, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[11:12], 2, v[4:5]
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v13, vcc_lo, s12, v11
	v_add_co_ci_u32_e32 v14, vcc_lo, s13, v12, vcc_lo
	v_add_co_u32 v11, vcc_lo, s14, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s15, v12, vcc_lo
	v_add_co_u32 v15, vcc_lo, s16, v4
	v_add_co_ci_u32_e32 v16, vcc_lo, s17, v5, vcc_lo
	global_store_b32 v[13:14], v39, off offset:-4
	global_store_b32 v[11:12], v1, off offset:-4
	global_store_b64 v[15:16], v[2:3], off offset:-8
	s_clause 0x1
	global_load_b64 v[5:6], v[7:8], off offset:8
	global_load_b128 v[1:4], v[7:8], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_f64 v[5:6], v[3:4], v[5:6]
	v_add_f64 v[1:2], v[3:4], v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[5:6], v[3:4], v[5:6]
	v_mul_f64 v[1:2], v[3:4], v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[17:18], v[5:6], 0.5
	v_mul_f64 v[1:2], v[1:2], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[3:4], null, v[17:18], v[17:18], 1.0
	v_div_scale_f64 v[5:6], null, v[1:2], v[1:2], 1.0
	v_div_scale_f64 v[27:28], vcc_lo, 1.0, v[17:18], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[19:20], v[3:4]
	v_rcp_f64_e32 v[21:22], v[5:6]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[23:24], -v[3:4], v[19:20], 1.0
	v_fma_f64 v[25:26], -v[5:6], v[21:22], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], v[19:20], v[23:24], v[19:20]
	v_fma_f64 v[21:22], v[21:22], v[25:26], v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[23:24], -v[3:4], v[19:20], 1.0
	v_fma_f64 v[25:26], -v[5:6], v[21:22], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[19:20], v[19:20], v[23:24], v[19:20]
	v_div_scale_f64 v[23:24], s0, 1.0, v[1:2], 1.0
	v_fma_f64 v[21:22], v[21:22], v[25:26], v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[25:26], v[27:28], v[19:20]
	v_mul_f64 v[29:30], v[23:24], v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[3:4], -v[3:4], v[25:26], v[27:28]
	v_fma_f64 v[5:6], -v[5:6], v[29:30], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[19:20], v[3:4], v[19:20], v[25:26]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[3:4], v[5:6], v[21:22], v[29:30]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[17:18], v[19:20], v[17:18], 1.0
	v_div_fixup_f64 v[1:2], v[3:4], v[1:2], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f64 v[2:3], v[9:10], v[1:2]
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v21, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v22, vcc_lo, s5, v1, vcc_lo
	global_store_b64 v[15:16], v[2:3], off
	global_load_b128 v[0:3], v[7:8], off offset:-8
	global_load_b128 v[4:7], v[21:22], off
	global_store_b32 v[13:14], v39, off
	s_waitcnt vmcnt(1)
	v_add_f64 v[0:1], v[2:3], v[0:1]
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[0:1], v[2:3], v[0:1]
	v_mul_f64 v[2:3], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[4:5], v[0:1], 0.5
	v_mul_f64 v[0:1], v[2:3], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[2:3], null, v[4:5], v[4:5], 1.0
	v_div_scale_f64 v[6:7], null, v[0:1], v[0:1], 1.0
	v_div_scale_f64 v[31:32], vcc_lo, 1.0, v[4:5], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[23:24], v[2:3]
	v_rcp_f64_e32 v[25:26], v[6:7]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[27:28], -v[2:3], v[23:24], 1.0
	v_fma_f64 v[29:30], -v[6:7], v[25:26], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[23:24], v[23:24], v[27:28], v[23:24]
	v_fma_f64 v[25:26], v[25:26], v[29:30], v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[27:28], -v[2:3], v[23:24], 1.0
	v_fma_f64 v[29:30], -v[6:7], v[25:26], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[23:24], v[23:24], v[27:28], v[23:24]
	v_div_scale_f64 v[27:28], s0, 1.0, v[0:1], 1.0
	v_fma_f64 v[25:26], v[25:26], v[29:30], v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[29:30], v[31:32], v[23:24]
	v_mul_f64 v[33:34], v[27:28], v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[2:3], -v[2:3], v[29:30], v[31:32]
	v_fma_f64 v[6:7], -v[6:7], v[33:34], v[27:28]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[23:24], v[2:3], v[23:24], v[29:30]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[2:3], v[6:7], v[25:26], v[33:34]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[4:5], v[23:24], v[4:5], 1.0
	v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[9:10], v[0:1]
	global_store_b64 v[15:16], v[0:1], off offset:8
	global_load_b128 v[0:3], v[21:22], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[6:7], v[2:3], v[0:1]
	v_mul_f64 v[2:3], v[2:3], v[6:7]
	v_mul_f64 v[0:1], v[0:1], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[6:7], v[2:3], 0.5
	v_mul_f64 v[0:1], v[0:1], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[2:3], null, v[6:7], v[6:7], 1.0
	v_div_scale_f64 v[25:26], null, v[0:1], v[0:1], 1.0
	v_div_scale_f64 v[35:36], vcc_lo, 1.0, v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[27:28], v[2:3]
	v_rcp_f64_e32 v[29:30], v[25:26]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[31:32], -v[2:3], v[27:28], 1.0
	v_fma_f64 v[33:34], -v[25:26], v[29:30], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[27:28], v[27:28], v[31:32], v[27:28]
	v_fma_f64 v[29:30], v[29:30], v[33:34], v[29:30]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[31:32], -v[2:3], v[27:28], 1.0
	v_fma_f64 v[33:34], -v[25:26], v[29:30], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[27:28], v[27:28], v[31:32], v[27:28]
	v_div_scale_f64 v[31:32], s0, 1.0, v[0:1], 1.0
	v_fma_f64 v[29:30], v[29:30], v[33:34], v[29:30]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[33:34], v[35:36], v[27:28]
	v_mul_f64 v[37:38], v[31:32], v[29:30]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[2:3], -v[2:3], v[33:34], v[35:36]
	v_fma_f64 v[25:26], -v[25:26], v[37:38], v[31:32]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[27:28], v[2:3], v[27:28], v[33:34]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[2:3], v[25:26], v[29:30], v[37:38]
	v_mul_f64 v[25:26], s[6:7], 0.5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f64 v[6:7], v[27:28], v[6:7], 1.0
	v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[25:26], v[25:26], s[8:9]
	v_mul_f64 v[0:1], v[9:10], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[25:26], v[17:18], 1.0
	global_store_b64 v[15:16], v[0:1], off offset:16
	global_load_b128 v[0:3], v[21:22], off
	v_fma_f64 v[4:5], v[25:26], v[4:5], v[17:18]
	v_fma_f64 v[4:5], v[25:26], v[6:7], v[4:5]
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[0:1], v[2:3]
	v_mul_f64 v[0:1], v[0:1], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0
	v_rcp_f64_e32 v[8:9], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[21:22], -v[2:3], v[8:9], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[8:9], v[21:22], v[8:9]
	v_fma_f64 v[21:22], -v[2:3], v[8:9], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[8:9], v[21:22], v[8:9]
	v_div_scale_f64 v[21:22], vcc_lo, 1.0, v[0:1], 1.0
	v_mul_f64 v[19:20], v[21:22], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], -v[2:3], v[19:20], v[21:22]
	v_div_fmas_f64 v[2:3], v[2:3], v[8:9], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0
	v_add_nc_u32_e32 v2, -1, v39
	v_add_nc_u32_e32 v3, s20, v39
	v_fma_f64 v[0:1], v[25:26], v[0:1], v[4:5]
	v_subrev_nc_u32_e32 v4, s20, v39
	global_store_b32 v[11:12], v2, off
	global_store_b32 v[13:14], v39, off offset:4
	global_store_b32 v[11:12], v3, off offset:4
	global_store_b32 v[13:14], v39, off offset:8
	global_store_b32 v[11:12], v4, off offset:8
	global_store_b32 v[13:14], v39, off offset:12
	global_store_b32 v[11:12], v39, off offset:12
	global_store_b64 v[15:16], v[0:1], off offset:24
.LBB3_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 40
		.amdhsa_next_free_sgpr 23
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii, .Lfunc_end3-_ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1948
; NumSgprs: 25
; NumVgprs: 40
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 25
; NumVGPRsForWavesPerEU: 40
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii
    .private_segment_fixed_size: 0
    .sgpr_count:     25
    .sgpr_spill_count: 0
    .symbol:         _ZN7kernels8LHS_BC_XEPiS0_PdS1_S1_ddii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     25
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii
    .private_segment_fixed_size: 0
    .sgpr_count:     27
    .sgpr_spill_count: 0
    .symbol:         _ZN7kernels8LHS_BC_YEPiS0_PdS1_S1_ddii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     27
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii
    .private_segment_fixed_size: 0
    .sgpr_count:     23
    .sgpr_spill_count: 0
    .symbol:         _ZN7kernels16LHS_mid_X_nobodyEPiS0_PdS1_S1_ddii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     40
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii
    .private_segment_fixed_size: 0
    .sgpr_count:     25
    .sgpr_spill_count: 0
    .symbol:         _ZN7kernels16LHS_mid_Y_nobodyEPiS0_PdS1_S1_ddii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     40
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
