#include <stdio.h>
 /*
  * This file is an attempt at producing what the generated target code 
  * should look like for the multiplyMatrixMatrix routine.
  */

/* Prototype matrix representation. */
struct dag_array_t{
  size_t rows;
  size_t cols; 
  int* matrix;
};

 /* 
   DAG Primitive. Here, we leverage the NVIDIA developer examples 
   to obtain a high-bandwith operation. They make use of shared memory
   to avoid strided global memory accesses, and instead perform the
   strided access in the shared block, which is roughly a ~3x improvement.

   TILE_DIM = 32
   BLOCK_ROWS = 8

   https://devblogs.nvidia.com/efficient-matrix-transpose-cuda-cc/
*/
const int tp_TILE_DIM = 32;
const int tp_BLOCK_ROWS = 8;

__global__ void transposeCoalesced(int *result, const int *in)
{
  const int TILE_DIM = tp_TILE_DIM;
  const int BLOCK_ROWS = tp_BLOCK_ROWS;

  __shared__ int tile[TILE_DIM][TILE_DIM];

  int x = blockIdx.x * TILE_DIM + threadIdx.x;
  int y = blockIdx.y * TILE_DIM + threadIdx.y;
  int width = gridDim.x * TILE_DIM;

  for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
     tile[threadIdx.y+j][threadIdx.x] = in[(y+j)*width + x];

  __syncthreads();

  x = blockIdx.y * TILE_DIM + threadIdx.x;  // transpose block offset
  y = blockIdx.x * TILE_DIM + threadIdx.y;

  for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
     result[(y+j)*width + x] = tile[threadIdx.x][threadIdx.y + j];
}


__global__ void multiplyMatrixVector(int* result, int* matrix, int* vector, int cols)
{
  __shared__ int reduce_array[256]; // Within a block

  int vector_slice_offset = blockIdx.x * cols + threadIdx.x; 
  int matrix_slice_offset = blockIdx.y * cols + threadIdx.x;
  reduce_array[threadIdx.x] = matrix[matrix_slice_offset] * vector[vector_slice_offset];

  __syncthreads();

  // Sequential reduce.
  if (threadIdx.x == 0){
    int accumulator = 0;
    for (int i = 0; i < blockDim.x; i++)
    {
      accumulator += reduce_array[i];
    }
    result[blockIdx.x * cols + blockIdx.y] = accumulator;
  }  
}

// We use single-dimensional lists.
void matrixMultiply(dag_array_t* result, dag_array_t* m1, dag_array_t* m2){

    // Precompute size information
    size_t size_m1 = m1->rows * m1->cols;
    size_t size_m2 = m2->rows * m2->cols;
    size_t size_result = m1->rows * m2->cols;

    // Copy onto device
    int* d_m1;  
    cudaMalloc(&d_m1,size_m1);
    cudaMemcpy(d_m1,m1->matrix,size_m1,cudaMemcpyHostToDevice);

    int* d_m2;  
    cudaMalloc(&d_m2,size_m2);
    cudaMemcpy(d_m2,m2->matrix,size_m2,cudaMemcpyHostToDevice);

    int* d_col; // We know that transpose will return same # of elem.
    cudaMalloc(&d_col,size_m2);

    int* d_result; // Allocate our result.
    cudaMalloc(&d_result,size_result);
    // A cruical optimization involves removing extraneous cudaMemcpy and cudaMallocs.

    dim3 dimGrid(m2->rows/tp_TILE_DIM, m2->cols/tp_TILE_DIM, 1);
    dim3 dimBlock(tp_TILE_DIM, tp_BLOCK_ROWS, 1);
    transposeCoalesced<<<dimGrid,dimBlock>>>(d_col,d_m2);

    const int threadsPerBlock = 256;
    dim3 dimBlock2(threadsPerBlock,1,1); // 256 threads per row
    dim3 dimGrid2((m1->rows + threadsPerBlock - 1) / threadsPerBlock,
                 (m2->rows + threadsPerBlock - 1) / threadsPerBlock,1);
    multiplyMatrixVector<<<dimGrid2,dimBlock2>>>(d_result,d_m1,d_col,m1->cols);

    cudaMemcpy(result->matrix,d_result,size_result,cudaMemcpyDeviceToHost);
    result->rows = m1->rows;
    result->cols = m2->cols;

    cudaFree(d_m1);
    cudaFree(d_m2);
    cudaFree(d_result);
    cudaFree(d_col);
}

int main(){
  int* a = (int*) malloc(100*sizeof(int));
  int* b = (int*) malloc(100*sizeof(int));

  dag_array_t A;
  A.rows = 10;
  A.cols = 10;
  A.matrix = a;

  dag_array_t B;
  B.rows = 10;
  B.cols = 10;
  B.matrix = b;

  dag_array_t C;
  C.rows = 10;
  C.cols = 10;
  C.matrix = (int*) malloc(100*sizeof(int));

  for (int i = 0; i < 10; i++)
  {
    for (int j = 0; j < 10; j++)
    {
      a[i*10+j] = 1;
      b[i*10+j] = 2;
    }
  }

  matrixMultiply(&C,&A,&B);

  for (int i = 0; i < 10; i++)
  {
    for (int j = 0; j < 10; j++)
    {
      printf(" %d ",C.matrix[i*10+j]);
    }
  }
}
	.file	"tmpxft_00245516_00000000-6_multiply.hand_written.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z41__device_stub__Z18transposeCoalescedPiPKiPiPKi
	.type	_Z41__device_stub__Z18transposeCoalescedPiPKiPiPKi, @function
_Z41__device_stub__Z18transposeCoalescedPiPKiPiPKi:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z18transposeCoalescedPiPKi(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z41__device_stub__Z18transposeCoalescedPiPKiPiPKi, .-_Z41__device_stub__Z18transposeCoalescedPiPKiPiPKi
	.globl	_Z18transposeCoalescedPiPKi
	.type	_Z18transposeCoalescedPiPKi, @function
_Z18transposeCoalescedPiPKi:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z18transposeCoalescedPiPKiPiPKi
	.cfi_endproc
.LFE2054:
	.size	_Z18transposeCoalescedPiPKi, .-_Z18transposeCoalescedPiPKi
	.globl	_Z45__device_stub__Z20multiplyMatrixVectorPiS_S_iPiS_S_i
	.type	_Z45__device_stub__Z20multiplyMatrixVectorPiS_S_iPiS_S_i, @function
_Z45__device_stub__Z20multiplyMatrixVectorPiS_S_iPiS_S_i:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z20multiplyMatrixVectorPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z45__device_stub__Z20multiplyMatrixVectorPiS_S_iPiS_S_i, .-_Z45__device_stub__Z20multiplyMatrixVectorPiS_S_iPiS_S_i
	.globl	_Z20multiplyMatrixVectorPiS_S_i
	.type	_Z20multiplyMatrixVectorPiS_S_i, @function
_Z20multiplyMatrixVectorPiS_S_i:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z20multiplyMatrixVectorPiS_S_iPiS_S_i
	.cfi_endproc
.LFE2056:
	.size	_Z20multiplyMatrixVectorPiS_S_i, .-_Z20multiplyMatrixVectorPiS_S_i
	.globl	_Z14matrixMultiplyP11dag_array_tS0_S0_
	.type	_Z14matrixMultiplyP11dag_array_tS0_S0_, @function
_Z14matrixMultiplyP11dag_array_tS0_S0_:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rdx, %rbx
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	(%rsi), %r13
	movq	8(%rsi), %r15
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	movq	(%rdx), %r14
	movq	8(%rdx), %rax
	leaq	8(%rsp), %rdi
	imulq	%r13, %r15
	imulq	%rax, %r14
	imulq	%rax, %r13
	movq	%r15, %rsi
	call	cudaMalloc@PLT
	movq	16(%rbp), %rsi
	movq	8(%rsp), %rdi
	movq	%r15, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leaq	16(%rsp), %rdi
	movq	%r14, %rsi
	call	cudaMalloc@PLT
	movq	16(%rbx), %rsi
	movq	16(%rsp), %rdi
	movq	%r14, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leaq	24(%rsp), %rdi
	movq	%r14, %rsi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movq	%r13, %rsi
	call	cudaMalloc@PLT
	movq	8(%rbx), %rax
	movq	(%rbx), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	shrq	$5, %rdx
	shrq	$5, %rax
	movl	%edx, 40(%rsp)
	movl	$1073741825, %edx
	movl	%eax, 44(%rsp)
	movq	40(%rsp), %rdi
	salq	$5, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	movq	16(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z41__device_stub__Z18transposeCoalescedPiPKiPiPKi
.L14:
	movq	0(%rbp), %rcx
	movq	(%rbx), %rax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %esi
	addq	$255, %rax
	leaq	255(%rcx), %rdx
	movl	$1, %ecx
	shrq	$8, %rdx
	shrq	$8, %rax
	movl	%edx, 76(%rsp)
	movl	$16777217, %edx
	movl	%eax, 80(%rsp)
	movq	76(%rsp), %rdi
	salq	$8, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	movl	8(%rbp), %ecx
	movq	24(%rsp), %rdx
	movq	8(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_Z45__device_stub__Z20multiplyMatrixVectorPiS_S_iPiS_S_i
.L15:
	movq	32(%rsp), %rsi
	movq	16(%r12), %rdi
	movl	$2, %ecx
	movq	%r13, %rdx
	call	cudaMemcpy@PLT
	movq	0(%rbp), %rax
	movq	8(%rsp), %rdi
	movq	%rax, (%r12)
	movq	8(%rbx), %rax
	movq	%rax, 8(%r12)
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z14matrixMultiplyP11dag_array_tS0_S0_, .-_Z14matrixMultiplyP11dag_array_tS0_S0_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	" %d "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$400, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$80, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$400, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movl	$400, %edi
	movq	%rbx, 16(%rsp)
	movq	$10, (%rsp)
	movq	%rax, %rbp
	movq	$10, 8(%rsp)
	movq	$10, 24(%rsp)
	movq	$10, 32(%rsp)
	movq	%rax, 40(%rsp)
	movq	$10, 48(%rsp)
	movq	$10, 56(%rsp)
	call	malloc@PLT
	xorl	%ecx, %ecx
	movq	%rax, 64(%rsp)
.L19:
	movq	%rcx, %rdx
	movl	$10, %eax
.L20:
	movl	$1, (%rbx,%rdx)
	movl	$2, 0(%rbp,%rdx)
	addq	$4, %rdx
	decl	%eax
	jne	.L20
	addq	$40, %rcx
	cmpq	$400, %rcx
	jne	.L19
	leaq	24(%rsp), %rdx
	movq	%rsp, %rsi
	leaq	48(%rsp), %rdi
	xorl	%ebp, %ebp
	call	_Z14matrixMultiplyP11dag_array_tS0_S0_
	leaq	.LC0(%rip), %r12
.L22:
	xorl	%ebx, %ebx
.L23:
	leaq	0(,%rbx,4), %rax
	addq	64(%rsp), %rax
	movq	%r12, %rsi
	movl	$2, %edi
	movl	(%rax,%rbp), %edx
	incq	%rbx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	cmpq	$10, %rbx
	jne	.L23
	addq	$40, %rbp
	cmpq	$400, %rbp
	jne	.L22
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$80, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC1:
	.string	"_Z20multiplyMatrixVectorPiS_S_i"
.LC2:
	.string	"_Z18transposeCoalescedPiPKi"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z20multiplyMatrixVectorPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z18transposeCoalescedPiPKi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2058:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
 /*
  * This file is an attempt at producing what the generated target code 
  * should look like for the multiplyMatrixMatrix routine.
  */

/* Prototype matrix representation. */
struct dag_array_t{
  size_t rows;
  size_t cols; 
  int* matrix;
};

 /* 
   DAG Primitive. Here, we leverage the NVIDIA developer examples 
   to obtain a high-bandwith operation. They make use of shared memory
   to avoid strided global memory accesses, and instead perform the
   strided access in the shared block, which is roughly a ~3x improvement.

   TILE_DIM = 32
   BLOCK_ROWS = 8

   https://devblogs.nvidia.com/efficient-matrix-transpose-cuda-cc/
*/
const int tp_TILE_DIM = 32;
const int tp_BLOCK_ROWS = 8;

__global__ void transposeCoalesced(int *result, const int *in)
{
  const int TILE_DIM = tp_TILE_DIM;
  const int BLOCK_ROWS = tp_BLOCK_ROWS;

  __shared__ int tile[TILE_DIM][TILE_DIM];

  int x = blockIdx.x * TILE_DIM + threadIdx.x;
  int y = blockIdx.y * TILE_DIM + threadIdx.y;
  int width = gridDim.x * TILE_DIM;

  for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
     tile[threadIdx.y+j][threadIdx.x] = in[(y+j)*width + x];

  __syncthreads();

  x = blockIdx.y * TILE_DIM + threadIdx.x;  // transpose block offset
  y = blockIdx.x * TILE_DIM + threadIdx.y;

  for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
     result[(y+j)*width + x] = tile[threadIdx.x][threadIdx.y + j];
}


__global__ void multiplyMatrixVector(int* result, int* matrix, int* vector, int cols)
{
  __shared__ int reduce_array[256]; // Within a block

  int vector_slice_offset = blockIdx.x * cols + threadIdx.x; 
  int matrix_slice_offset = blockIdx.y * cols + threadIdx.x;
  reduce_array[threadIdx.x] = matrix[matrix_slice_offset] * vector[vector_slice_offset];

  __syncthreads();

  // Sequential reduce.
  if (threadIdx.x == 0){
    int accumulator = 0;
    for (int i = 0; i < blockDim.x; i++)
    {
      accumulator += reduce_array[i];
    }
    result[blockIdx.x * cols + blockIdx.y] = accumulator;
  }  
}

// We use single-dimensional lists.
void matrixMultiply(dag_array_t* result, dag_array_t* m1, dag_array_t* m2){

    // Precompute size information
    size_t size_m1 = m1->rows * m1->cols;
    size_t size_m2 = m2->rows * m2->cols;
    size_t size_result = m1->rows * m2->cols;

    // Copy onto device
    int* d_m1;  
    hipMalloc(&d_m1,size_m1);
    hipMemcpy(d_m1,m1->matrix,size_m1,hipMemcpyHostToDevice);

    int* d_m2;  
    hipMalloc(&d_m2,size_m2);
    hipMemcpy(d_m2,m2->matrix,size_m2,hipMemcpyHostToDevice);

    int* d_col; // We know that transpose will return same # of elem.
    hipMalloc(&d_col,size_m2);

    int* d_result; // Allocate our result.
    hipMalloc(&d_result,size_result);
    // A cruical optimization involves removing extraneous cudaMemcpy and cudaMallocs.

    dim3 dimGrid(m2->rows/tp_TILE_DIM, m2->cols/tp_TILE_DIM, 1);
    dim3 dimBlock(tp_TILE_DIM, tp_BLOCK_ROWS, 1);
    transposeCoalesced<<<dimGrid,dimBlock>>>(d_col,d_m2);

    const int threadsPerBlock = 256;
    dim3 dimBlock2(threadsPerBlock,1,1); // 256 threads per row
    dim3 dimGrid2((m1->rows + threadsPerBlock - 1) / threadsPerBlock,
                 (m2->rows + threadsPerBlock - 1) / threadsPerBlock,1);
    multiplyMatrixVector<<<dimGrid2,dimBlock2>>>(d_result,d_m1,d_col,m1->cols);

    hipMemcpy(result->matrix,d_result,size_result,hipMemcpyDeviceToHost);
    result->rows = m1->rows;
    result->cols = m2->cols;

    hipFree(d_m1);
    hipFree(d_m2);
    hipFree(d_result);
    hipFree(d_col);
}

int main(){
  int* a = (int*) malloc(100*sizeof(int));
  int* b = (int*) malloc(100*sizeof(int));

  dag_array_t A;
  A.rows = 10;
  A.cols = 10;
  A.matrix = a;

  dag_array_t B;
  B.rows = 10;
  B.cols = 10;
  B.matrix = b;

  dag_array_t C;
  C.rows = 10;
  C.cols = 10;
  C.matrix = (int*) malloc(100*sizeof(int));

  for (int i = 0; i < 10; i++)
  {
    for (int j = 0; j < 10; j++)
    {
      a[i*10+j] = 1;
      b[i*10+j] = 2;
    }
  }

  matrixMultiply(&C,&A,&B);

  for (int i = 0; i < 10; i++)
  {
    for (int j = 0; j < 10; j++)
    {
      printf(" %d ",C.matrix[i*10+j]);
    }
  }
}
	.text
	.file	"multiply.hand_written.hip"
	.globl	_Z33__device_stub__transposeCoalescedPiPKi # -- Begin function _Z33__device_stub__transposeCoalescedPiPKi
	.type	_Z33__device_stub__transposeCoalescedPiPKi,@function
_Z33__device_stub__transposeCoalescedPiPKi: # @_Z33__device_stub__transposeCoalescedPiPKi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18transposeCoalescedPiPKi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__transposeCoalescedPiPKi, .Lfunc_end0-_Z33__device_stub__transposeCoalescedPiPKi
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__multiplyMatrixVectorPiS_S_i # -- Begin function _Z35__device_stub__multiplyMatrixVectorPiS_S_i
	.type	_Z35__device_stub__multiplyMatrixVectorPiS_S_i,@function
_Z35__device_stub__multiplyMatrixVectorPiS_S_i: # @_Z35__device_stub__multiplyMatrixVectorPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20multiplyMatrixVectorPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z35__device_stub__multiplyMatrixVectorPiS_S_i, .Lfunc_end1-_Z35__device_stub__multiplyMatrixVectorPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z14matrixMultiplyP11dag_array_tS0_S0_ # -- Begin function _Z14matrixMultiplyP11dag_array_tS0_S0_
	.type	_Z14matrixMultiplyP11dag_array_tS0_S0_,@function
_Z14matrixMultiplyP11dag_array_tS0_S0_: # @_Z14matrixMultiplyP11dag_array_tS0_S0_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdx, %rbx
	movq	%rsi, %r15
	movq	%rdi, 32(%rsp)                  # 8-byte Spill
	movq	(%rsi), %rax
	movq	8(%rsi), %rbp
	imulq	%rax, %rbp
	movq	8(%rdx), %r12
	movq	(%rdx), %r13
	imulq	%r12, %r13
	imulq	%rax, %r12
	leaq	24(%rsp), %r14
	movq	%r14, %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movq	(%r14), %rdi
	movq	16(%r15), %rsi
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %r14
	movq	%r14, %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	movq	(%r14), %rdi
	movq	16(%rbx), %rsi
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	movq	%rsp, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	(%rbx), %rax
	movq	8(%rbx), %rdi
	shrq	$5, %rax
	movl	%eax, %eax
	andq	$-32, %rdi
	shlq	$27, %rdi
	orq	%rax, %rdi
	movabsq	$34359738400, %rdx              # imm = 0x800000020
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	movq	8(%rsp), %rdi
	movq	16(%rsp), %rsi
	callq	_Z33__device_stub__transposeCoalescedPiPKi
.LBB2_2:
	movl	$255, %eax
	addq	(%r15), %rax
	shrq	$8, %rax
	movq	(%rbx), %rdi
	movl	%eax, %eax
	shlq	$24, %rdi
	movl	$4278190080, %edx               # imm = 0xFF000000
	addq	%rdx, %rdi
	movabsq	$-4294967296, %rcx              # imm = 0xFFFFFFFF00000000
	andq	%rcx, %rdi
	orq	%rax, %rdi
	addq	$16777472, %rdx                 # imm = 0x1000100
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_4
# %bb.3:
	movq	(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	8(%r15), %ecx
	callq	_Z35__device_stub__multiplyMatrixVectorPiS_S_i
.LBB2_4:
	movq	32(%rsp), %r14                  # 8-byte Reload
	movq	16(%r14), %rdi
	movq	(%rsp), %rsi
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	(%r15), %rax
	movq	%rax, (%r14)
	movq	8(%rbx), %rax
	movq	%rax, 8(%r14)
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z14matrixMultiplyP11dag_array_tS0_S0_, .Lfunc_end2-_Z14matrixMultiplyP11dag_array_tS0_S0_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$80, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$400, %edi                      # imm = 0x190
	callq	malloc
	movq	%rax, %rbx
	movl	$400, %edi                      # imm = 0x190
	callq	malloc
	movq	%rax, %r14
	movl	$10, %eax
	movq	%rax, 56(%rsp)
	movq	%rax, 64(%rsp)
	movq	%rbx, 72(%rsp)
	movq	%rax, 32(%rsp)
	movq	%rax, 40(%rsp)
	movq	%r14, 48(%rsp)
	movq	%rax, 8(%rsp)
	movq	%rax, 16(%rsp)
	movl	$400, %edi                      # imm = 0x190
	callq	malloc
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
.LBB3_1:                                # %.preheader21
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_2 Depth 2
	xorl	%ecx, %ecx
.LBB3_2:                                #   Parent Loop BB3_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$1, (%rbx,%rcx,4)
	movl	$2, (%r14,%rcx,4)
	incq	%rcx
	cmpq	$10, %rcx
	jne	.LBB3_2
# %bb.3:                                #   in Loop: Header=BB3_1 Depth=1
	incq	%rax
	addq	$40, %r14
	addq	$40, %rbx
	cmpq	$10, %rax
	jne	.LBB3_1
# %bb.4:
	leaq	8(%rsp), %rbx
	leaq	56(%rsp), %rsi
	leaq	32(%rsp), %rdx
	movq	%rbx, %rdi
	callq	_Z14matrixMultiplyP11dag_array_tS0_S0_
	movq	16(%rbx), %rbx
	xorl	%r14d, %r14d
.LBB3_5:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_6 Depth 2
	xorl	%r15d, %r15d
.LBB3_6:                                #   Parent Loop BB3_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%rbx,%r15,4), %esi
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r15
	cmpq	$10, %r15
	jne	.LBB3_6
# %bb.7:                                #   in Loop: Header=BB3_5 Depth=1
	incq	%r14
	addq	$40, %rbx
	cmpq	$10, %r14
	jne	.LBB3_5
# %bb.8:
	xorl	%eax, %eax
	addq	$80, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18transposeCoalescedPiPKi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20multiplyMatrixVectorPiS_S_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18transposeCoalescedPiPKi,@object # @_Z18transposeCoalescedPiPKi
	.section	.rodata,"a",@progbits
	.globl	_Z18transposeCoalescedPiPKi
	.p2align	3, 0x0
_Z18transposeCoalescedPiPKi:
	.quad	_Z33__device_stub__transposeCoalescedPiPKi
	.size	_Z18transposeCoalescedPiPKi, 8

	.type	_Z20multiplyMatrixVectorPiS_S_i,@object # @_Z20multiplyMatrixVectorPiS_S_i
	.globl	_Z20multiplyMatrixVectorPiS_S_i
	.p2align	3, 0x0
_Z20multiplyMatrixVectorPiS_S_i:
	.quad	_Z35__device_stub__multiplyMatrixVectorPiS_S_i
	.size	_Z20multiplyMatrixVectorPiS_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	" %d "
	.size	.L.str, 5

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z18transposeCoalescedPiPKi"
	.size	.L__unnamed_1, 28

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z20multiplyMatrixVectorPiS_S_i"
	.size	.L__unnamed_2, 32

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__transposeCoalescedPiPKi
	.addrsig_sym _Z35__device_stub__multiplyMatrixVectorPiS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18transposeCoalescedPiPKi
	.addrsig_sym _Z20multiplyMatrixVectorPiS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18transposeCoalescedPiPKi ; -- Begin function _Z18transposeCoalescedPiPKi
	.globl	_Z18transposeCoalescedPiPKi
	.p2align	8
	.type	_Z18transposeCoalescedPiPKi,@function
_Z18transposeCoalescedPiPKi:            ; @_Z18transposeCoalescedPiPKi
; %bb.0:
	s_load_b32 s5, s[0:1], 0x10
	v_bfe_u32 v2, v0, 10, 10
	s_lshl_b32 s6, s15, 5
	s_load_b128 s[0:3], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	s_lshl_b32 s7, s14, 5
	v_add_nc_u32_e32 v1, s6, v2
	s_mov_b32 s8, -8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v0, 2, v3
	v_lshl_add_u32 v4, v2, 7, v0
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v1, s5, v1
	s_lshl_b32 s4, s5, 8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v1, 5, v1
	v_add3_u32 v0, v3, v1, s7
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_i32 s8, s8, 8
	s_cmp_gt_u32 s8, 23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[0:1]
	v_add_nc_u32_e32 v0, s4, v0
	v_add_co_u32 v5, vcc_lo, s2, v5
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
	global_load_b32 v1, v[5:6], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v1
	v_add_nc_u32_e32 v4, 0x400, v4
	s_cbranch_scc0 .LBB0_1
; %bb.2:
	v_add_nc_u32_e32 v0, s7, v2
	v_lshlrev_b32_e32 v1, 2, v2
	s_mov_b32 s2, -8
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mul_lo_u32 v0, s5, v0
	v_lshl_add_u32 v2, v3, 7, v1
	buffer_gl0_inv
	v_lshlrev_b32_e32 v0, 5, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v0, v3, v0, s6
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v5, v2
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_nc_u32_e32 v2, 32, v2
	s_add_i32 s2, s2, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_gt_u32 s2, 23
	v_lshlrev_b64 v[3:4], 2, v[0:1]
	v_add_nc_u32_e32 v0, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[3:4], v5, off
	s_cbranch_scc0 .LBB0_3
; %bb.4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18transposeCoalescedPiPKi
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18transposeCoalescedPiPKi, .Lfunc_end0-_Z18transposeCoalescedPiPKi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 320
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z20multiplyMatrixVectorPiS_S_i ; -- Begin function _Z20multiplyMatrixVectorPiS_S_i
	.globl	_Z20multiplyMatrixVectorPiS_S_i
	.p2align	8
	.type	_Z20multiplyMatrixVectorPiS_S_i,@function
_Z20multiplyMatrixVectorPiS_S_i:        ; @_Z20multiplyMatrixVectorPiS_S_i
; %bb.0:
	s_clause 0x2
	s_load_b32 s3, s[0:1], 0x18
	s_load_b64 s[8:9], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s14, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s2, v0
	v_mad_u64_u32 v[3:4], null, s15, s3, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s8, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	v_add_co_u32 v3, vcc_lo, s6, v3
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	global_load_b32 v1, v[1:2], off
	global_load_b32 v2, v[3:4], off
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v1, v1, v2
	v_lshlrev_b32_e32 v2, 2, v0
	ds_store_b32 v2, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_5
; %bb.1:                                ; %.preheader
	s_load_b32 s0, s[0:1], 0x2c
	v_mov_b32_e32 v0, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 0
	s_cbranch_scc1 .LBB1_4
; %bb.2:                                ; %.lr.ph.preheader
	v_mov_b32_e32 v0, 0
	s_mov_b32 s1, 0
.LBB1_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s1
	s_add_i32 s0, s0, -1
	s_add_i32 s1, s1, 4
	s_cmp_eq_u32 s0, 0
	ds_load_b32 v1, v1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v0, v1, v0
	s_cbranch_scc0 .LBB1_3
.LBB1_4:                                ; %Flow29
	s_add_i32 s0, s2, s15
	s_mov_b32 s1, 0
	v_mov_b32_e32 v1, 0
	s_lshl_b64 s[0:1], s[0:1], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s4, s0
	s_addc_u32 s1, s5, s1
	global_store_b32 v1, v0, s[0:1]
.LBB1_5:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20multiplyMatrixVectorPiS_S_i
		.amdhsa_group_segment_fixed_size 1024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z20multiplyMatrixVectorPiS_S_i, .Lfunc_end1-_Z20multiplyMatrixVectorPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 316
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18transposeCoalescedPiPKi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18transposeCoalescedPiPKi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1024
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20multiplyMatrixVectorPiS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z20multiplyMatrixVectorPiS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
