#include <stdio.h>
#include <math.h>
#include <time.h>
#include <cuda.h>
//Code written by Alan Fleming

//CONSTANTS
#define MATRIXSIZE 2048
#define BLOCKSIZE 1024

void cpuHistogram(int* input, int* histogram, int size) {
	for(int i = 0; i < size; i++) {
		histogram[input[i]]++;
	}
}

__global__ void histogram(int* input, int* histogram, int size) {
	//get starting index for thread
	int i = threadIdx.x + blockIdx.x * blockDim.x;
	//calculate stride
	int stride = blockDim.x * gridDim.x;
	//preform histogram calculation
	while( i < size) {
		atomicAdd( &(histogram[input[i]]), 1);
		i += stride;
	}
}	

//currently does not work for block sizes smaller than 256
__global__ void sharedHistogram(int* input, int* histogram, int size) {
	//initialize shared memory for the block
	__shared__ int privateHistogram[256];

	if(threadIdx.x < 256) privateHistogram[threadIdx.x] = 0;
	__syncthreads();

	//get starting index for thread
	int i = threadIdx.x + blockIdx.x * blockDim.x;
	//calculate stride
	int stride = blockDim.x * gridDim.x;
	//preform histogram calculation
	while( i < size) {
		atomicAdd( &(privateHistogram[input[i]]), 1);
		i += stride;
	}

	//ensure all threads have finished their additions
	__syncthreads();

	//add private histogram to public histogram
	if(threadIdx.x < 256) {
		atomicAdd( &(histogram[threadIdx.x]), privateHistogram[threadIdx.x]);
	}
}


int main() {
	int *input = (int *)malloc(sizeof(int) * MATRIXSIZE); //allocate space for array
	int *cpuResult = (int *)malloc(sizeof(int) * 256); //allocate space for cpu output array
	int *basicGPUResult = (int *)malloc(sizeof(int) * 256); //allocate space for gpu output array using global memory
	int *sharedGPUResult = (int *)malloc(sizeof(int) * 256); //allocate space for gpu output array using shared memory

	//intialize the input array
	int init = 1325;
	for(int i=0; i < MATRIXSIZE; i++){
		init= 3125 * init % 65537;
		input[i]= init % 256;
	}
	//clear the output arrays to ensure proper adding
	for(int i = 0; i < 256; i++) {
		cpuResult[i] = 0;
		basicGPUResult[i] = 0;
		sharedGPUResult[i] = 0;
	}

	//Test CPU
	//Get start time
	clock_t t1 = clock();
	//Calculate reduction
	
	cpuHistogram(input, cpuResult, MATRIXSIZE);
	
	//Get stop time
	clock_t t2 = clock();
	//Calculate runtime
	float cpuTime= (float(t2-t1)/CLOCKS_PER_SEC*1000);

	//Allocate memory on GPU compution. dev_b is used to store the results of the first pass of reduction
	int *dev_input, *dev_basicGPUResult, *dev_sharedGPUResult;
	cudaMalloc((void **)(&dev_input), MATRIXSIZE *sizeof(int));
	cudaMalloc((void **)(&dev_basicGPUResult), 256 *sizeof(int));
	cudaMalloc((void **)(&dev_sharedGPUResult), 256 *sizeof(int));

	//copy memory to gpu
	cudaMemcpy(dev_input, input, MATRIXSIZE * sizeof(int), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_basicGPUResult, basicGPUResult, 256 * sizeof(int), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_sharedGPUResult, sharedGPUResult, 256 * sizeof(int), cudaMemcpyHostToDevice);

	//calculate dimentions for gpu
	dim3 dimBlock(BLOCKSIZE);
	dim3 dimGrid(ceil(double(MATRIXSIZE)/dimBlock.x));

	//~~WITHOUT SHARED MEMORY~~
	//Set up cuda events for recording runtime
	cudaEvent_t start,stop;
	float basicGPUTime; 
	cudaEventCreate(&start);
	cudaEventCreate(&stop);
	cudaEventRecord(start,0);
					
	//calculate histogram without shared memory
	histogram<<<dimGrid, dimBlock>>>(dev_input, dev_basicGPUResult, MATRIXSIZE);
						
	//calculate runtime 
	cudaEventRecord(stop,0);
	cudaEventSynchronize(stop);
	cudaEventElapsedTime(&basicGPUTime,start,stop);

	//destroy cuda events
	cudaEventDestroy(start);
	cudaEventDestroy(stop);

	//copy sum from gpu
	cudaMemcpy(basicGPUResult, dev_basicGPUResult, 256 * sizeof(int), cudaMemcpyDeviceToHost);

	//print speedup
	printf("--WITHOUT SHARED MEMORY--\nCPU Runtime: %f\nGpu Runtime: %f\nSpeedup: %f\n", (double)cpuTime, (double)basicGPUTime, double(cpuTime / basicGPUTime));

	//verify results
	bool valid = true;
	for(int i = 0; i < 256; i++) {	
		if(cpuResult[i] != basicGPUResult[i]) {
			valid = false;
			break;
		}
	}
	if(valid) {
		printf("TEST PASSED\n");
	} else {
		printf("TEST FAILED\n");
	}

	//~~WITH SHARED MEMORY~~
	//Set up cuda events for recording runtime
	float sharedGPUTime; 
	cudaEventCreate(&start);
	cudaEventCreate(&stop);
	cudaEventRecord(start,0);
					
	//calculate histogram with shared memory
	histogram<<<dimGrid, dimBlock>>>(dev_input, dev_sharedGPUResult, MATRIXSIZE);
						
	//calculate runtime 
	cudaEventRecord(stop,0);
	cudaEventSynchronize(stop);
	cudaEventElapsedTime(&sharedGPUTime,start,stop);

	//destroy cuda events
	cudaEventDestroy(start);
	cudaEventDestroy(stop);

	//copy sum from gpu
	cudaMemcpy(sharedGPUResult, dev_sharedGPUResult, 256 * sizeof(int), cudaMemcpyDeviceToHost);

	//print speedup
	printf("--WITH SHARED MEMORY--\nCPU Runtime: %f\nGpu Runtime: %f\nSpeedup: %f\n", (double)cpuTime, (double)sharedGPUTime, double(cpuTime / sharedGPUTime));

	//verify results
	valid = true;
	for(int i = 0; i < 256; i++) {	
		if(cpuResult[i] != sharedGPUResult[i]) {
			valid = false;
			break;
		}
	}
	if(valid) {
		printf("TEST PASSED\n");
	} else {
		printf("TEST FAILED\n");
	}
	

	//free up memory before returning
	free(input);
	free(cpuResult);
	free(basicGPUResult);
	free(sharedGPUResult);
	cudaFree(dev_input);
	cudaFree(dev_basicGPUResult);
	cudaFree(dev_sharedGPUResult);

	return 0;
}

	.file	"tmpxft_00226174_00000000-6_flemingHistogram.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z12cpuHistogramPiS_i
	.type	_Z12cpuHistogramPiS_i, @function
_Z12cpuHistogramPiS_i:
.LFB2027:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
.L3:
	cmpl	%eax, %edx
	jle	.L6
	movslq	(%rdi,%rax,4), %rcx
	incq	%rax
	incl	(%rsi,%rcx,4)
	jmp	.L3
.L6:
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z12cpuHistogramPiS_i, .-_Z12cpuHistogramPiS_i
	.globl	_Z31__device_stub__Z9histogramPiS_iPiS_i
	.type	_Z31__device_stub__Z9histogramPiS_iPiS_i, @function
_Z31__device_stub__Z9histogramPiS_iPiS_i:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L7
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z9histogramPiS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L7:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z31__device_stub__Z9histogramPiS_iPiS_i, .-_Z31__device_stub__Z9histogramPiS_iPiS_i
	.globl	_Z9histogramPiS_i
	.type	_Z9histogramPiS_i, @function
_Z9histogramPiS_i:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z9histogramPiS_iPiS_i
	.cfi_endproc
.LFE2054:
	.size	_Z9histogramPiS_i, .-_Z9histogramPiS_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"--WITHOUT SHARED MEMORY--\nCPU Runtime: %f\nGpu Runtime: %f\nSpeedup: %f\n"
.LC3:
	.string	"--WITH SHARED MEMORY--\nCPU Runtime: %f\nGpu Runtime: %f\nSpeedup: %f\n"
.LC4:
	.string	"TEST PASSED\n"
.LC5:
	.string	"TEST FAILED\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$8192, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$1024, %edi
	movq	%rax, %r13
	call	malloc@PLT
	movl	$1024, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movl	$1024, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	xorl	%ecx, %ecx
	movl	$1325, %esi
	movl	$65537, %r8d
	movq	%rax, %r12
	movl	$256, %edi
.L13:
	imull	$3125, %esi, %eax
	cltd
	idivl	%r8d
	movl	%edx, %eax
	movl	%edx, %esi
	cltd
	idivl	%edi
	movl	%edx, 0(%r13,%rcx,4)
	incq	%rcx
	cmpq	$2048, %rcx
	jne	.L13
	xorl	%eax, %eax
	movl	$256, %ecx
	leaq	56(%rsp), %r15
	movq	%rbx, %rdi
	rep stosl
	movl	$256, %ecx
	movq	%rbp, %rdi
	rep stosl
	movl	$256, %ecx
	movq	%r12, %rdi
	rep stosl
	call	clock@PLT
	movl	$2048, %edx
	movq	%rbx, %rsi
	movq	%r13, %rdi
	movq	%rax, %r14
	call	_Z12cpuHistogramPiS_i
	call	clock@PLT
	leaq	24(%rsp), %rdi
	movl	$8192, %esi
	subq	%r14, %rax
	leaq	48(%rsp), %r14
	cvtsi2ssq	%rax, %xmm0
	divss	.LC0(%rip), %xmm0
	mulss	.LC1(%rip), %xmm0
	movss	%xmm0, 4(%rsp)
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$1024, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$1024, %esi
	call	cudaMalloc@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$8192, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$1024, %edx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$1024, %edx
	call	cudaMemcpy@PLT
	movl	$2147483649, %eax
	movq	%r14, %rdi
	movl	$1, 84(%rsp)
	addq	%rax, %rax
	movq	%rax, 76(%rsp)
	call	cudaEventCreate@PLT
	movq	%r15, %rdi
	call	cudaEventCreate@PLT
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	76(%rsp), %rdi
	movl	84(%rsp), %esi
	salq	$10, %rdx
	movl	$1, %ecx
	movq	%rdx, 64(%rsp)
	movl	$1, 72(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdi
	movl	$2048, %edx
	call	_Z31__device_stub__Z9histogramPiS_iPiS_i
.L14:
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	56(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	leaq	16(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	48(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	56(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	32(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	movl	$1024, %edx
	call	cudaMemcpy@PLT
	movss	16(%rsp), %xmm1
	movb	$3, %al
	movss	4(%rsp), %xmm2
	cvtss2sd	4(%rsp), %xmm3
	leaq	.LC2(%rip), %rsi
	movaps	%xmm3, %xmm0
	movl	$2, %edi
	divss	%xmm1, %xmm2
	movsd	%xmm3, 8(%rsp)
	cvtss2sd	%xmm1, %xmm1
	cvtss2sd	%xmm2, %xmm2
	call	__printf_chk@PLT
	xorl	%eax, %eax
.L16:
	movl	0(%rbp,%rax), %edx
	cmpl	%edx, (%rbx,%rax)
	jne	.L15
	addq	$4, %rax
	cmpq	$1024, %rax
	jne	.L16
	leaq	.LC4(%rip), %rsi
	jmp	.L32
.L15:
	leaq	.LC5(%rip), %rsi
.L32:
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%r14, %rdi
	call	cudaEventCreate@PLT
	movq	%r15, %rdi
	call	cudaEventCreate@PLT
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	72(%rsp), %ecx
	movl	84(%rsp), %esi
	xorl	%r9d, %r9d
	movq	64(%rsp), %rdx
	movq	76(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	movq	40(%rsp), %rsi
	movq	24(%rsp), %rdi
	movl	$2048, %edx
	call	_Z31__device_stub__Z9histogramPiS_iPiS_i
.L18:
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	56(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	leaq	20(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	48(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	56(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movq	%r12, %rdi
	movl	$1024, %edx
	call	cudaMemcpy@PLT
	movss	20(%rsp), %xmm1
	movb	$3, %al
	movss	4(%rsp), %xmm2
	movsd	8(%rsp), %xmm0
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	divss	%xmm1, %xmm2
	cvtss2sd	%xmm1, %xmm1
	cvtss2sd	%xmm2, %xmm2
	call	__printf_chk@PLT
	xorl	%eax, %eax
.L20:
	movl	(%r12,%rax), %ecx
	cmpl	%ecx, (%rbx,%rax)
	jne	.L19
	addq	$4, %rax
	cmpq	$1024, %rax
	jne	.L20
	leaq	.LC4(%rip), %rsi
	jmp	.L33
.L19:
	leaq	.LC5(%rip), %rsi
.L33:
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.text
	.globl	_Z38__device_stub__Z15sharedHistogramPiS_iPiS_i
	.type	_Z38__device_stub__Z15sharedHistogramPiS_iPiS_i, @function
_Z38__device_stub__Z15sharedHistogramPiS_iPiS_i:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z15sharedHistogramPiS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L34:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z38__device_stub__Z15sharedHistogramPiS_iPiS_i, .-_Z38__device_stub__Z15sharedHistogramPiS_iPiS_i
	.globl	_Z15sharedHistogramPiS_i
	.type	_Z15sharedHistogramPiS_i, @function
_Z15sharedHistogramPiS_i:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z15sharedHistogramPiS_iPiS_i
	.cfi_endproc
.LFE2056:
	.size	_Z15sharedHistogramPiS_i, .-_Z15sharedHistogramPiS_i
	.section	.rodata.str1.1
.LC6:
	.string	"_Z15sharedHistogramPiS_i"
.LC7:
	.string	"_Z9histogramPiS_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z15sharedHistogramPiS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9histogramPiS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2058:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1232348160
	.align 4
.LC1:
	.long	1148846080
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <math.h>
#include <time.h>
#include <hip/hip_runtime.h>
//Code written by Alan Fleming

//CONSTANTS
#define MATRIXSIZE 2048
#define BLOCKSIZE 1024

void cpuHistogram(int* input, int* histogram, int size) {
	for(int i = 0; i < size; i++) {
		histogram[input[i]]++;
	}
}

__global__ void histogram(int* input, int* histogram, int size) {
	//get starting index for thread
	int i = threadIdx.x + blockIdx.x * blockDim.x;
	//calculate stride
	int stride = blockDim.x * gridDim.x;
	//preform histogram calculation
	while( i < size) {
		atomicAdd( &(histogram[input[i]]), 1);
		i += stride;
	}
}	

//currently does not work for block sizes smaller than 256
__global__ void sharedHistogram(int* input, int* histogram, int size) {
	//initialize shared memory for the block
	__shared__ int privateHistogram[256];

	if(threadIdx.x < 256) privateHistogram[threadIdx.x] = 0;
	__syncthreads();

	//get starting index for thread
	int i = threadIdx.x + blockIdx.x * blockDim.x;
	//calculate stride
	int stride = blockDim.x * gridDim.x;
	//preform histogram calculation
	while( i < size) {
		atomicAdd( &(privateHistogram[input[i]]), 1);
		i += stride;
	}

	//ensure all threads have finished their additions
	__syncthreads();

	//add private histogram to public histogram
	if(threadIdx.x < 256) {
		atomicAdd( &(histogram[threadIdx.x]), privateHistogram[threadIdx.x]);
	}
}


int main() {
	int *input = (int *)malloc(sizeof(int) * MATRIXSIZE); //allocate space for array
	int *cpuResult = (int *)malloc(sizeof(int) * 256); //allocate space for cpu output array
	int *basicGPUResult = (int *)malloc(sizeof(int) * 256); //allocate space for gpu output array using global memory
	int *sharedGPUResult = (int *)malloc(sizeof(int) * 256); //allocate space for gpu output array using shared memory

	//intialize the input array
	int init = 1325;
	for(int i=0; i < MATRIXSIZE; i++){
		init= 3125 * init % 65537;
		input[i]= init % 256;
	}
	//clear the output arrays to ensure proper adding
	for(int i = 0; i < 256; i++) {
		cpuResult[i] = 0;
		basicGPUResult[i] = 0;
		sharedGPUResult[i] = 0;
	}

	//Test CPU
	//Get start time
	clock_t t1 = clock();
	//Calculate reduction
	
	cpuHistogram(input, cpuResult, MATRIXSIZE);
	
	//Get stop time
	clock_t t2 = clock();
	//Calculate runtime
	float cpuTime= (float(t2-t1)/CLOCKS_PER_SEC*1000);

	//Allocate memory on GPU compution. dev_b is used to store the results of the first pass of reduction
	int *dev_input, *dev_basicGPUResult, *dev_sharedGPUResult;
	hipMalloc((void **)(&dev_input), MATRIXSIZE *sizeof(int));
	hipMalloc((void **)(&dev_basicGPUResult), 256 *sizeof(int));
	hipMalloc((void **)(&dev_sharedGPUResult), 256 *sizeof(int));

	//copy memory to gpu
	hipMemcpy(dev_input, input, MATRIXSIZE * sizeof(int), hipMemcpyHostToDevice);
	hipMemcpy(dev_basicGPUResult, basicGPUResult, 256 * sizeof(int), hipMemcpyHostToDevice);
	hipMemcpy(dev_sharedGPUResult, sharedGPUResult, 256 * sizeof(int), hipMemcpyHostToDevice);

	//calculate dimentions for gpu
	dim3 dimBlock(BLOCKSIZE);
	dim3 dimGrid(ceil(double(MATRIXSIZE)/dimBlock.x));

	//~~WITHOUT SHARED MEMORY~~
	//Set up cuda events for recording runtime
	hipEvent_t start,stop;
	float basicGPUTime; 
	hipEventCreate(&start);
	hipEventCreate(&stop);
	hipEventRecord(start,0);
					
	//calculate histogram without shared memory
	histogram<<<dimGrid, dimBlock>>>(dev_input, dev_basicGPUResult, MATRIXSIZE);
						
	//calculate runtime 
	hipEventRecord(stop,0);
	hipEventSynchronize(stop);
	hipEventElapsedTime(&basicGPUTime,start,stop);

	//destroy cuda events
	hipEventDestroy(start);
	hipEventDestroy(stop);

	//copy sum from gpu
	hipMemcpy(basicGPUResult, dev_basicGPUResult, 256 * sizeof(int), hipMemcpyDeviceToHost);

	//print speedup
	printf("--WITHOUT SHARED MEMORY--\nCPU Runtime: %f\nGpu Runtime: %f\nSpeedup: %f\n", (double)cpuTime, (double)basicGPUTime, double(cpuTime / basicGPUTime));

	//verify results
	bool valid = true;
	for(int i = 0; i < 256; i++) {	
		if(cpuResult[i] != basicGPUResult[i]) {
			valid = false;
			break;
		}
	}
	if(valid) {
		printf("TEST PASSED\n");
	} else {
		printf("TEST FAILED\n");
	}

	//~~WITH SHARED MEMORY~~
	//Set up cuda events for recording runtime
	float sharedGPUTime; 
	hipEventCreate(&start);
	hipEventCreate(&stop);
	hipEventRecord(start,0);
					
	//calculate histogram with shared memory
	histogram<<<dimGrid, dimBlock>>>(dev_input, dev_sharedGPUResult, MATRIXSIZE);
						
	//calculate runtime 
	hipEventRecord(stop,0);
	hipEventSynchronize(stop);
	hipEventElapsedTime(&sharedGPUTime,start,stop);

	//destroy cuda events
	hipEventDestroy(start);
	hipEventDestroy(stop);

	//copy sum from gpu
	hipMemcpy(sharedGPUResult, dev_sharedGPUResult, 256 * sizeof(int), hipMemcpyDeviceToHost);

	//print speedup
	printf("--WITH SHARED MEMORY--\nCPU Runtime: %f\nGpu Runtime: %f\nSpeedup: %f\n", (double)cpuTime, (double)sharedGPUTime, double(cpuTime / sharedGPUTime));

	//verify results
	valid = true;
	for(int i = 0; i < 256; i++) {	
		if(cpuResult[i] != sharedGPUResult[i]) {
			valid = false;
			break;
		}
	}
	if(valid) {
		printf("TEST PASSED\n");
	} else {
		printf("TEST FAILED\n");
	}
	

	//free up memory before returning
	free(input);
	free(cpuResult);
	free(basicGPUResult);
	free(sharedGPUResult);
	hipFree(dev_input);
	hipFree(dev_basicGPUResult);
	hipFree(dev_sharedGPUResult);

	return 0;
}

	.text
	.file	"flemingHistogram.hip"
	.globl	_Z12cpuHistogramPiS_i           # -- Begin function _Z12cpuHistogramPiS_i
	.type	_Z12cpuHistogramPiS_i,@function
_Z12cpuHistogramPiS_i:                  # @_Z12cpuHistogramPiS_i
	.cfi_startproc
# %bb.0:
	testl	%edx, %edx
	jle	.LBB0_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%edx, %eax
	xorl	%ecx, %ecx
.LBB0_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movslq	(%rdi,%rcx,4), %rdx
	incl	(%rsi,%rdx,4)
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB0_2
.LBB0_3:                                # %._crit_edge
	retq
.Lfunc_end0:
	.size	_Z12cpuHistogramPiS_i, .Lfunc_end0-_Z12cpuHistogramPiS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__histogramPiS_i # -- Begin function _Z24__device_stub__histogramPiS_i
	.type	_Z24__device_stub__histogramPiS_i,@function
_Z24__device_stub__histogramPiS_i:      # @_Z24__device_stub__histogramPiS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9histogramPiS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z24__device_stub__histogramPiS_i, .Lfunc_end1-_Z24__device_stub__histogramPiS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__sharedHistogramPiS_i # -- Begin function _Z30__device_stub__sharedHistogramPiS_i
	.type	_Z30__device_stub__sharedHistogramPiS_i,@function
_Z30__device_stub__sharedHistogramPiS_i: # @_Z30__device_stub__sharedHistogramPiS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15sharedHistogramPiS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z30__device_stub__sharedHistogramPiS_i, .Lfunc_end2-_Z30__device_stub__sharedHistogramPiS_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI3_0:
	.long	0x49742400                      # float 1.0E+6
.LCPI3_1:
	.long	0x447a0000                      # float 1000
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$8192, %edi                     # imm = 0x2000
	callq	malloc
	movq	%rax, %rbx
	movl	$1024, %edi                     # imm = 0x400
	callq	malloc
	movq	%rax, %r14
	movl	$1024, %edi                     # imm = 0x400
	callq	malloc
	movq	%rax, %r15
	movl	$1024, %edi                     # imm = 0x400
	callq	malloc
	movq	%rax, %r12
	movl	$1325, %eax                     # imm = 0x52D
	xorl	%ecx, %ecx
	movl	$4294901761, %edx               # imm = 0xFFFF0001
.LBB3_1:                                # =>This Inner Loop Header: Depth=1
	imull	$3125, %eax, %eax               # imm = 0xC35
	movq	%rax, %rsi
	imulq	%rdx, %rsi
	shrq	$48, %rsi
	movl	%esi, %edi
	shll	$16, %edi
	orl	%esi, %edi
	subl	%edi, %eax
	movzbl	%al, %esi
	movl	%esi, (%rbx,%rcx,4)
	incq	%rcx
	cmpq	$2048, %rcx                     # imm = 0x800
	jne	.LBB3_1
# %bb.2:                                # %.preheader.preheader
	xorl	%r13d, %r13d
	movl	$1024, %edx                     # imm = 0x400
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movl	$1024, %edx                     # imm = 0x400
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movl	$1024, %edx                     # imm = 0x400
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	callq	clock
	movq	%rax, %rbp
.LBB3_3:                                # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	movslq	(%rbx,%r13,4), %rax
	incl	(%r14,%rax,4)
	incq	%r13
	cmpq	$2048, %r13                     # imm = 0x800
	jne	.LBB3_3
# %bb.4:                                # %_Z12cpuHistogramPiS_i.exit
	callq	clock
	subq	%rbp, %rax
	cvtsi2ss	%rax, %xmm0
	divss	.LCPI3_0(%rip), %xmm0
	mulss	.LCPI3_1(%rip), %xmm0
	movss	%xmm0, 20(%rsp)                 # 4-byte Spill
	leaq	40(%rsp), %rbp
	movl	$8192, %esi                     # imm = 0x2000
	movq	%rbp, %rdi
	callq	hipMalloc
	leaq	32(%rsp), %r13
	movl	$1024, %esi                     # imm = 0x400
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$1024, %esi                     # imm = 0x400
	callq	hipMalloc
	movq	(%rbp), %rdi
	movl	$8192, %edx                     # imm = 0x2000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$1024, %edx                     # imm = 0x400
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movl	$1024, %edx                     # imm = 0x400
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %r13
	movq	%r13, %rdi
	callq	hipEventCreate
	movq	%rsp, %rdi
	callq	hipEventCreate
	movq	(%r13), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$4294967298, %rdi               # imm = 0x100000002
	leaq	1022(%rdi), %rdx
	movl	$1, %esi
	movq	%rdx, 48(%rsp)                  # 8-byte Spill
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_6
# %bb.5:
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movl	$2048, %edx                     # imm = 0x800
	callq	_Z24__device_stub__histogramPiS_i
.LBB3_6:
	movq	(%rsp), %rdi
	xorl	%ebp, %ebp
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	leaq	68(%rsp), %r13
	movq	%r13, %rdi
	callq	hipEventElapsedTime
	movq	8(%rsp), %rdi
	callq	hipEventDestroy
	movq	(%rsp), %rdi
	callq	hipEventDestroy
	movq	32(%rsp), %rsi
	movl	$1024, %edx                     # imm = 0x400
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movss	20(%rsp), %xmm2                 # 4-byte Reload
                                        # xmm2 = mem[0],zero,zero,zero
	cvtss2sd	%xmm2, %xmm0
	movss	(%r13), %xmm3                   # xmm3 = mem[0],zero,zero,zero
	cvtss2sd	%xmm3, %xmm1
	divss	%xmm3, %xmm2
	cvtss2sd	%xmm2, %xmm2
	movl	$.L.str, %edi
	movsd	%xmm0, 56(%rsp)                 # 8-byte Spill
	movb	$3, %al
	callq	printf
.LBB3_7:                                # =>This Inner Loop Header: Depth=1
	movl	(%r14,%rbp,4), %eax
	cmpl	(%r15,%rbp,4), %eax
	jne	.LBB3_10
# %bb.8:                                #   in Loop: Header=BB3_7 Depth=1
	incq	%rbp
	cmpq	$256, %rbp                      # imm = 0x100
	jne	.LBB3_7
# %bb.9:
	movl	$.Lstr.3, %edi
	jmp	.LBB3_11
.LBB3_10:
	movl	$.Lstr.2, %edi
.LBB3_11:                               # %.critedge
	callq	puts@PLT
	leaq	8(%rsp), %r13
	movq	%r13, %rdi
	callq	hipEventCreate
	movq	%rsp, %rdi
	callq	hipEventCreate
	movq	(%r13), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$4294967298, %rdi               # imm = 0x100000002
	movl	$1, %esi
	movq	48(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_13
# %bb.12:
	movq	40(%rsp), %rdi
	movq	24(%rsp), %rsi
	movl	$2048, %edx                     # imm = 0x800
	callq	_Z24__device_stub__histogramPiS_i
.LBB3_13:
	movq	(%rsp), %rdi
	xorl	%ebp, %ebp
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	leaq	64(%rsp), %r13
	movq	%r13, %rdi
	callq	hipEventElapsedTime
	movq	8(%rsp), %rdi
	callq	hipEventDestroy
	movq	(%rsp), %rdi
	callq	hipEventDestroy
	movq	24(%rsp), %rsi
	movl	$1024, %edx                     # imm = 0x400
	movq	%r12, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movss	(%r13), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	xorps	%xmm1, %xmm1
	cvtss2sd	%xmm0, %xmm1
	movss	20(%rsp), %xmm2                 # 4-byte Reload
                                        # xmm2 = mem[0],zero,zero,zero
	divss	%xmm0, %xmm2
	cvtss2sd	%xmm2, %xmm2
	movl	$.L.str.3, %edi
	movsd	56(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	movb	$3, %al
	callq	printf
.LBB3_14:                               # =>This Inner Loop Header: Depth=1
	movl	(%r14,%rbp,4), %eax
	cmpl	(%r12,%rbp,4), %eax
	jne	.LBB3_17
# %bb.15:                               #   in Loop: Header=BB3_14 Depth=1
	incq	%rbp
	cmpq	$256, %rbp                      # imm = 0x100
	jne	.LBB3_14
# %bb.16:
	movl	$.Lstr.3, %edi
	jmp	.LBB3_18
.LBB3_17:
	movl	$.Lstr.2, %edi
.LBB3_18:                               # %.critedge71
	callq	puts@PLT
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	%r12, %rdi
	callq	free
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9histogramPiS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15sharedHistogramPiS_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9histogramPiS_i,@object       # @_Z9histogramPiS_i
	.section	.rodata,"a",@progbits
	.globl	_Z9histogramPiS_i
	.p2align	3, 0x0
_Z9histogramPiS_i:
	.quad	_Z24__device_stub__histogramPiS_i
	.size	_Z9histogramPiS_i, 8

	.type	_Z15sharedHistogramPiS_i,@object # @_Z15sharedHistogramPiS_i
	.globl	_Z15sharedHistogramPiS_i
	.p2align	3, 0x0
_Z15sharedHistogramPiS_i:
	.quad	_Z30__device_stub__sharedHistogramPiS_i
	.size	_Z15sharedHistogramPiS_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"--WITHOUT SHARED MEMORY--\nCPU Runtime: %f\nGpu Runtime: %f\nSpeedup: %f\n"
	.size	.L.str, 71

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"--WITH SHARED MEMORY--\nCPU Runtime: %f\nGpu Runtime: %f\nSpeedup: %f\n"
	.size	.L.str.3, 68

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9histogramPiS_i"
	.size	.L__unnamed_1, 18

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z15sharedHistogramPiS_i"
	.size	.L__unnamed_2, 25

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr.2,@object                 # @str.2
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr.2:
	.asciz	"TEST FAILED"
	.size	.Lstr.2, 12

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"TEST PASSED"
	.size	.Lstr.3, 12

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__histogramPiS_i
	.addrsig_sym _Z30__device_stub__sharedHistogramPiS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9histogramPiS_i
	.addrsig_sym _Z15sharedHistogramPiS_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9histogramPiS_i       ; -- Begin function _Z9histogramPiS_i
	.globl	_Z9histogramPiS_i
	.p2align	8
	.type	_Z9histogramPiS_i,@function
_Z9histogramPiS_i:                      ; @_Z9histogramPiS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b32 s8, s[0:1], 0x10
	s_add_u32 s2, s0, 24
	s_addc_u32 s3, s1, 0
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_cmpx_gt_i32_e64 s8, v1
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s5, s[2:3], 0x0
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v0, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s5, s4
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_ashr_i32 s5, s4, 31
	s_mov_b32 s1, 0
	s_lshl_b64 s[6:7], s[4:5], 2
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v4, v[2:3], off
	v_add_nc_u32_e32 v1, s4, v1
	v_add_co_u32 v2, s0, v2, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, s7, v3, s0
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	v_cmp_le_i32_e32 vcc_lo, s8, v1
	global_atomic_add_u32 v[4:5], v0, off
	s_or_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_2
.LBB0_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9histogramPiS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9histogramPiS_i, .Lfunc_end0-_Z9histogramPiS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 244
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z15sharedHistogramPiS_i ; -- Begin function _Z15sharedHistogramPiS_i
	.globl	_Z15sharedHistogramPiS_i
	.p2align	8
	.type	_Z15sharedHistogramPiS_i,@function
_Z15sharedHistogramPiS_i:               ; @_Z15sharedHistogramPiS_i
; %bb.0:
	v_cmp_gt_u32_e32 vcc_lo, 0x100, v0
	v_lshlrev_b32_e32 v4, 2, v0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB1_2
; %bb.1:
	v_mov_b32_e32 v1, 0
	ds_store_b32 v4, v1
.LBB1_2:
	s_or_b32 exec_lo, exec_lo, s2
	s_clause 0x2
	s_load_b32 s9, s[0:1], 0x24
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_add_u32 s2, s0, 24
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 s1, s9, 0xffff
	s_mov_b32 s9, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s1, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s8, v1
	s_cbranch_execz .LBB1_5
; %bb.3:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[2:3], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v0, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s0, s1
	v_add_co_u32 v2, s0, s4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
	s_ashr_i32 s3, s2, 31
	s_lshl_b64 s[4:5], s[2:3], 2
	s_mov_b32 s3, 0
.LBB1_4:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v5, v[2:3], off
	v_add_nc_u32_e32 v1, s2, v1
	v_add_co_u32 v2, s1, v2, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v3, s1, s5, v3, s1
	v_cmp_le_i32_e64 s0, s8, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_or_b32 s3, s0, s3
	s_waitcnt vmcnt(0)
	v_lshlrev_b32_e32 v5, 2, v5
	ds_add_u32 v5, v0
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_4
.LBB1_5:                                ; %Flow17
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB1_7
; %bb.6:
	ds_load_b32 v0, v4
	s_waitcnt lgkmcnt(0)
	global_atomic_add_u32 v4, v0, s[6:7]
.LBB1_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15sharedHistogramPiS_i
		.amdhsa_group_segment_fixed_size 1024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z15sharedHistogramPiS_i, .Lfunc_end1-_Z15sharedHistogramPiS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 324
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9histogramPiS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9histogramPiS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1024
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15sharedHistogramPiS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15sharedHistogramPiS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
