////////////////////////////////////////////////////////////////////////////////
//
// FILE:        one_dim_convolution.cu
// DESCRIPTION: implements one-dimensional convolution in 3 ways
// AUTHOR:      Dan Fabian
// DATE:        3/15/2020

#include <cuda.h>
#include <cuda_runtime.h>
#include <iostream>
#include <stdio.h>

using std::cout; using std::endl; using std::cin;

// constant size params
const int SIZE = 15000, MASK_SIZE = 1001, BLOCK_SIZE = 1024;

// gpu prototypes
__global__ void naive_conv(float *input, float *kernel, float *output, 
                           int maskSize, int size); // naive implementation
__global__ void const_mem_conv(float *input, float *output, 
                               int maskSize, int size); // uses constant memory
__global__ void shared_mem_conv(float *input, float *output, 
                                int maskSize, int size); // uses shared and constant mem

// device constant used in const_mem_conv and shared_mem_conv
__constant__ float kernel_c[MASK_SIZE];

////////////////////////////////////////////////////////////////////////////////
//
// MAIN
int main()
{
    // create arrays
    float *input_d, input[SIZE], *kernel_d, kernel[MASK_SIZE], *output_d, output[SIZE];

    // init kernel
    for (int i = 0; i < MASK_SIZE; ++i)
        if (i == MASK_SIZE / 2)
            kernel[i] = 1;
        else
            kernel[i] = 0;

    // init input array
    for (int i = 0; i < SIZE; ++i)
        input[i] = 1;

    // memory sizes to allocate
    int inOutMem = SIZE * sizeof(float), kernelMem = MASK_SIZE * sizeof(float);

    // determine which version will be ran before allocating mem
    cout << "Which version ('n': naive, 'c': constant mem, 's': shared mem): ";
    char c; cin >> c;

    // allocate memory on device
    cudaMalloc((void**)&input_d, inOutMem);
    if (c == 'n')
        cudaMalloc((void**)&kernel_d, kernelMem);
    cudaMalloc((void**)&output_d, inOutMem);

    // copy frequency and sorted arrays to device
    cudaMemcpy(input_d, input, inOutMem, cudaMemcpyHostToDevice);
    if (c == 'n')
        cudaMemcpy(kernel_d, kernel, kernelMem, cudaMemcpyHostToDevice);

    // copy kernel to constant memory
    if (c != 'n')
        cudaMemcpyToSymbol(kernel_c, kernel, kernelMem);

    // call gpu func
    int gridSize = ceil(float(SIZE) / float(BLOCK_SIZE));

    if (c == 'n')
        naive_conv<<<gridSize, BLOCK_SIZE>>>(input_d, kernel_d, output_d, MASK_SIZE, SIZE);
    else if (c == 'c')
        const_mem_conv<<<gridSize, BLOCK_SIZE>>>(input_d, output_d, MASK_SIZE, SIZE);
    else if (c == 's')
        shared_mem_conv<<<gridSize, BLOCK_SIZE>>>(input_d, output_d, MASK_SIZE, SIZE);

    // copy device memory back to host
    cudaMemcpy(output, output_d, inOutMem, cudaMemcpyDeviceToHost);

    // free memory
    cudaFree(input_d); cudaFree(kernel_d); cudaFree(output_d);

    // print result
    for (int i = 0; i < SIZE; ++i)
        cout << output[i] << ' ';
    cout << endl;

    cudaDeviceSynchronize();
}

////////////////////////////////////////////////////////////////////////////////
//
// KERNEL functions
////////////////////////////////////////
// naive implementation
__global__ void naive_conv(float *input, float *kernel, float *output, 
                           int maskSize, int size)
{
    int idx = blockDim.x * blockIdx.x + threadIdx.x, 
        start = idx - (maskSize / 2);

    float val = 0;
    for (int i = 0; i < maskSize; ++i)
        if (0 <= start + i && start + i < size)
            val += input[start + i] * kernel[i];

    // copy to global mem
    if (idx < size)
        output[idx] = val;
}

////////////////////////////////////////
// faster implementation that uses constant memory
__global__ void const_mem_conv(float *input, float *output, 
                               int maskSize, int size)
{
    int idx = blockDim.x * blockIdx.x + threadIdx.x, 
        start = idx - (maskSize / 2);

    float val = 0;
    for (int i = 0; i < maskSize; ++i)
        if (0 <= start + i && start + i < size)
            val += input[start + i] * kernel_c[i];

    // copy to global mem
    if (idx < size)
        output[idx] = val;
}

////////////////////////////////////////
// implementation using shared and constant memory
__global__ void shared_mem_conv(float *input, float *output, 
                                int maskSize, int size)
{
    int idx = blockDim.x * blockIdx.x + threadIdx.x,
        lowerBound = blockDim.x * blockIdx.x,
        upperBound = blockDim.x * (blockIdx.x + 1),
        start = idx - (maskSize / 2);

    // shared mem
    __shared__ float tile_s[BLOCK_SIZE];

    // load elem
    if (idx < size)
        tile_s[threadIdx.x] = input[idx];
    __syncthreads();

    float val = 0;
    bool bound;
    for (int i = 0, elem = start; i < maskSize; ++i, ++elem)
    {
        // check if its within array
        bound = 0 <= elem && elem < size;

        // if its within bounds, use shared mem
        if (lowerBound <= elem && elem < upperBound && bound)
            val += tile_s[elem - lowerBound] * kernel_c[i];       
        // resort to global mem if needed
        else if (bound)
            val += input[elem] * kernel_c[i];
    }

    // copy to global mem
    if (idx < size)
        output[idx] = val;
}
	.file	"tmpxft_002af497_00000000-6_one_dim_convolution.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z36__device_stub__Z10naive_convPfS_S_iiPfS_S_ii
	.type	_Z36__device_stub__Z10naive_convPfS_S_iiPfS_S_ii, @function
_Z36__device_stub__Z10naive_convPfS_S_iiPfS_S_ii:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10naive_convPfS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z36__device_stub__Z10naive_convPfS_S_iiPfS_S_ii, .-_Z36__device_stub__Z10naive_convPfS_S_iiPfS_S_ii
	.globl	_Z10naive_convPfS_S_ii
	.type	_Z10naive_convPfS_S_ii, @function
_Z10naive_convPfS_S_ii:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z10naive_convPfS_S_iiPfS_S_ii
	.cfi_endproc
.LFE3661:
	.size	_Z10naive_convPfS_S_ii, .-_Z10naive_convPfS_S_ii
	.globl	_Z38__device_stub__Z14const_mem_convPfS_iiPfS_ii
	.type	_Z38__device_stub__Z14const_mem_convPfS_iiPfS_ii, @function
_Z38__device_stub__Z14const_mem_convPfS_iiPfS_ii:
.LFB3662:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z14const_mem_convPfS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3662:
	.size	_Z38__device_stub__Z14const_mem_convPfS_iiPfS_ii, .-_Z38__device_stub__Z14const_mem_convPfS_iiPfS_ii
	.globl	_Z14const_mem_convPfS_ii
	.type	_Z14const_mem_convPfS_ii, @function
_Z14const_mem_convPfS_ii:
.LFB3663:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z14const_mem_convPfS_iiPfS_ii
	.cfi_endproc
.LFE3663:
	.size	_Z14const_mem_convPfS_ii, .-_Z14const_mem_convPfS_ii
	.globl	_Z39__device_stub__Z15shared_mem_convPfS_iiPfS_ii
	.type	_Z39__device_stub__Z15shared_mem_convPfS_iiPfS_ii, @function
_Z39__device_stub__Z15shared_mem_convPfS_iiPfS_ii:
.LFB3664:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z15shared_mem_convPfS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3664:
	.size	_Z39__device_stub__Z15shared_mem_convPfS_iiPfS_ii, .-_Z39__device_stub__Z15shared_mem_convPfS_iiPfS_ii
	.globl	_Z15shared_mem_convPfS_ii
	.type	_Z15shared_mem_convPfS_ii, @function
_Z15shared_mem_convPfS_ii:
.LFB3665:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z15shared_mem_convPfS_iiPfS_ii
	.cfi_endproc
.LFE3665:
	.size	_Z15shared_mem_convPfS_ii, .-_Z15shared_mem_convPfS_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"Which version ('n': naive, 'c': constant mem, 's': shared mem): "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	leaq	-122880(%rsp), %r11
	.cfi_def_cfa 11, 122920
.LPSRL0:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL0
	.cfi_def_cfa_register 7
	subq	$1208, %rsp
	.cfi_def_cfa_offset 124128
	movss	.LC0(%rip), %xmm0
	movq	%fs:40, %rax
	movq	%rax, 124072(%rsp)
	xorl	%eax, %eax
	leaq	68(%rsp), %rbx
.L22:
	cmpq	$500, %rax
	jne	.L19
	movss	%xmm0, 2068(%rsp)
	movl	$501, %eax
.L19:
	movl	$0x00000000, (%rbx,%rax,4)
	incq	%rax
	cmpq	$1001, %rax
	jne	.L22
	movss	.LC0(%rip), %xmm0
	xorl	%eax, %eax
	leaq	4072(%rsp), %r12
.L21:
	movss	%xmm0, (%r12,%rax,4)
	incq	%rax
	cmpq	$15000, %rax
	jne	.L21
	leaq	_ZSt4cout(%rip), %rbp
	movl	$64, %edx
	leaq	.LC2(%rip), %rsi
	movq	%rbp, %rdi
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	leaq	15(%rsp), %rsi
	leaq	_ZSt3cin(%rip), %rdi
	call	_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_RS3_@PLT
	leaq	16(%rsp), %rdi
	movl	$60000, %esi
	call	cudaMalloc@PLT
	cmpb	$110, 15(%rsp)
	jne	.L23
	leaq	24(%rsp), %rdi
	movl	$4004, %esi
	call	cudaMalloc@PLT
.L23:
	leaq	32(%rsp), %rdi
	movl	$60000, %esi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$60000, %edx
	call	cudaMemcpy@PLT
	cmpb	$110, 15(%rsp)
	je	.L24
.L26:
	movl	$1, %r8d
	xorl	%ecx, %ecx
	movl	$4004, %edx
	movq	%rbx, %rsi
	leaq	_ZL8kernel_c(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	jmp	.L25
.L24:
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$4004, %edx
	movq	%rbx, %rsi
	call	cudaMemcpy@PLT
	cmpb	$110, 15(%rsp)
	jne	.L26
.L25:
	movb	15(%rsp), %al
	cmpb	$110, %al
	jne	.L27
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	salq	$10, %rdx
	movl	$1, %esi
	movabsq	$4294967311, %rdi
	movl	$1, 64(%rsp)
	movq	%rdx, 56(%rsp)
	movq	%rdi, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	movl	$1001, %ecx
	movl	$15000, %r8d
	movq	16(%rsp), %rdi
	call	_Z36__device_stub__Z10naive_convPfS_S_iiPfS_S_ii
	jmp	.L29
.L27:
	cmpb	$99, %al
	jne	.L30
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	salq	$10, %rdx
	movl	$1, %esi
	movabsq	$4294967311, %rdi
	movl	$1, 64(%rsp)
	movq	%rdx, 56(%rsp)
	movq	%rdi, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	movq	32(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	$15000, %ecx
	movl	$1001, %edx
	call	_Z38__device_stub__Z14const_mem_convPfS_iiPfS_ii
	jmp	.L29
.L30:
	cmpb	$115, %al
	jne	.L29
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	salq	$10, %rdx
	movl	$1, %esi
	movabsq	$4294967311, %rdi
	movl	$1, 64(%rsp)
	movq	%rdx, 56(%rsp)
	movq	%rdi, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	movq	32(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	$15000, %ecx
	movl	$1001, %edx
	call	_Z39__device_stub__Z15shared_mem_convPfS_iiPfS_ii
.L29:
	movq	32(%rsp), %rsi
	leaq	64072(%rsp), %r12
	movl	$2, %ecx
	xorl	%ebx, %ebx
	movl	$60000, %edx
	movq	%r12, %rdi
	leaq	56(%rsp), %r13
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
.L35:
	movq	%rbp, %rdi
	cvtss2sd	(%r12,%rbx,4), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movb	$32, 56(%rsp)
	movq	%rax, %rdi
	movq	(%rax), %rax
	movq	-24(%rax), %rax
	cmpq	$0, 16(%rdi,%rax)
	je	.L33
	movl	$1, %edx
	movq	%r13, %rsi
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	jmp	.L34
.L33:
	movl	$32, %esi
	call	_ZNSo3putEc@PLT
.L34:
	incq	%rbx
	cmpq	$15000, %rbx
	jne	.L35
	movq	%rbp, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	call	cudaDeviceSynchronize@PLT
	movq	124072(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	addq	$124088, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z15shared_mem_convPfS_ii"
.LC4:
	.string	"_Z14const_mem_convPfS_ii"
.LC5:
	.string	"_Z10naive_convPfS_S_ii"
.LC6:
	.string	"kernel_c"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3667:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z15shared_mem_convPfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z14const_mem_convPfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10naive_convPfS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movl	$4004, %r9d
	leaq	_ZL8kernel_c(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3667:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL8kernel_c
	.comm	_ZL8kernel_c,4004,32
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1065353216
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

////////////////////////////////////////////////////////////////////////////////
//
// FILE:        one_dim_convolution.cu
// DESCRIPTION: implements one-dimensional convolution in 3 ways
// AUTHOR:      Dan Fabian
// DATE:        3/15/2020

#include <hip/hip_runtime.h>

#include <iostream>
#include <stdio.h>

using std::cout; using std::endl; using std::cin;

// constant size params
const int SIZE = 15000, MASK_SIZE = 1001, BLOCK_SIZE = 1024;

// gpu prototypes
__global__ void naive_conv(float *input, float *kernel, float *output, 
                           int maskSize, int size); // naive implementation
__global__ void const_mem_conv(float *input, float *output, 
                               int maskSize, int size); // uses constant memory
__global__ void shared_mem_conv(float *input, float *output, 
                                int maskSize, int size); // uses shared and constant mem

// device constant used in const_mem_conv and shared_mem_conv
__constant__ float kernel_c[MASK_SIZE];

////////////////////////////////////////////////////////////////////////////////
//
// MAIN
int main()
{
    // create arrays
    float *input_d, input[SIZE], *kernel_d, kernel[MASK_SIZE], *output_d, output[SIZE];

    // init kernel
    for (int i = 0; i < MASK_SIZE; ++i)
        if (i == MASK_SIZE / 2)
            kernel[i] = 1;
        else
            kernel[i] = 0;

    // init input array
    for (int i = 0; i < SIZE; ++i)
        input[i] = 1;

    // memory sizes to allocate
    int inOutMem = SIZE * sizeof(float), kernelMem = MASK_SIZE * sizeof(float);

    // determine which version will be ran before allocating mem
    cout << "Which version ('n': naive, 'c': constant mem, 's': shared mem): ";
    char c; cin >> c;

    // allocate memory on device
    hipMalloc((void**)&input_d, inOutMem);
    if (c == 'n')
        hipMalloc((void**)&kernel_d, kernelMem);
    hipMalloc((void**)&output_d, inOutMem);

    // copy frequency and sorted arrays to device
    hipMemcpy(input_d, input, inOutMem, hipMemcpyHostToDevice);
    if (c == 'n')
        hipMemcpy(kernel_d, kernel, kernelMem, hipMemcpyHostToDevice);

    // copy kernel to constant memory
    if (c != 'n')
        hipMemcpyToSymbol(HIP_SYMBOL(kernel_c), kernel, kernelMem);

    // call gpu func
    int gridSize = ceil(float(SIZE) / float(BLOCK_SIZE));

    if (c == 'n')
        naive_conv<<<gridSize, BLOCK_SIZE>>>(input_d, kernel_d, output_d, MASK_SIZE, SIZE);
    else if (c == 'c')
        const_mem_conv<<<gridSize, BLOCK_SIZE>>>(input_d, output_d, MASK_SIZE, SIZE);
    else if (c == 's')
        shared_mem_conv<<<gridSize, BLOCK_SIZE>>>(input_d, output_d, MASK_SIZE, SIZE);

    // copy device memory back to host
    hipMemcpy(output, output_d, inOutMem, hipMemcpyDeviceToHost);

    // free memory
    hipFree(input_d); hipFree(kernel_d); hipFree(output_d);

    // print result
    for (int i = 0; i < SIZE; ++i)
        cout << output[i] << ' ';
    cout << endl;

    hipDeviceSynchronize();
}

////////////////////////////////////////////////////////////////////////////////
//
// KERNEL functions
////////////////////////////////////////
// naive implementation
__global__ void naive_conv(float *input, float *kernel, float *output, 
                           int maskSize, int size)
{
    int idx = blockDim.x * blockIdx.x + threadIdx.x, 
        start = idx - (maskSize / 2);

    float val = 0;
    for (int i = 0; i < maskSize; ++i)
        if (0 <= start + i && start + i < size)
            val += input[start + i] * kernel[i];

    // copy to global mem
    if (idx < size)
        output[idx] = val;
}

////////////////////////////////////////
// faster implementation that uses constant memory
__global__ void const_mem_conv(float *input, float *output, 
                               int maskSize, int size)
{
    int idx = blockDim.x * blockIdx.x + threadIdx.x, 
        start = idx - (maskSize / 2);

    float val = 0;
    for (int i = 0; i < maskSize; ++i)
        if (0 <= start + i && start + i < size)
            val += input[start + i] * kernel_c[i];

    // copy to global mem
    if (idx < size)
        output[idx] = val;
}

////////////////////////////////////////
// implementation using shared and constant memory
__global__ void shared_mem_conv(float *input, float *output, 
                                int maskSize, int size)
{
    int idx = blockDim.x * blockIdx.x + threadIdx.x,
        lowerBound = blockDim.x * blockIdx.x,
        upperBound = blockDim.x * (blockIdx.x + 1),
        start = idx - (maskSize / 2);

    // shared mem
    __shared__ float tile_s[BLOCK_SIZE];

    // load elem
    if (idx < size)
        tile_s[threadIdx.x] = input[idx];
    __syncthreads();

    float val = 0;
    bool bound;
    for (int i = 0, elem = start; i < maskSize; ++i, ++elem)
    {
        // check if its within array
        bound = 0 <= elem && elem < size;

        // if its within bounds, use shared mem
        if (lowerBound <= elem && elem < upperBound && bound)
            val += tile_s[elem - lowerBound] * kernel_c[i];       
        // resort to global mem if needed
        else if (bound)
            val += input[elem] * kernel_c[i];
    }

    // copy to global mem
    if (idx < size)
        output[idx] = val;
}
	.text
	.file	"one_dim_convolution.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$124056, %rsp                   # imm = 0x1E498
	.cfi_def_cfa_offset 124080
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	xorl	%eax, %eax
.LBB0_1:                                # =>This Inner Loop Header: Depth=1
	cmpq	$500, %rax                      # imm = 0x1F4
	jne	.LBB0_3
# %bb.2:                                #   in Loop: Header=BB0_1 Depth=1
	movl	$1065353216, 2032(%rsp)         # imm = 0x3F800000
	jmp	.LBB0_4
.LBB0_3:                                #   in Loop: Header=BB0_1 Depth=1
	movl	$0, 32(%rsp,%rax,4)
.LBB0_4:                                #   in Loop: Header=BB0_1 Depth=1
	incq	%rax
	cmpq	$1001, %rax                     # imm = 0x3E9
	jne	.LBB0_1
# %bb.5:                                # %.preheader.preheader
	xorl	%eax, %eax
.LBB0_6:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movl	$1065353216, 64048(%rsp,%rax,4) # imm = 0x3F800000
	incq	%rax
	cmpq	$15000, %rax                    # imm = 0x3A98
	jne	.LBB0_6
# %bb.7:
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$64, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	leaq	6(%rsp), %rbx
	movl	$_ZSt3cin, %edi
	movq	%rbx, %rsi
	callq	_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_RS3_
	leaq	16(%rsp), %rdi
	movl	$60000, %esi                    # imm = 0xEA60
	callq	hipMalloc
	cmpb	$110, (%rbx)
	jne	.LBB0_9
# %bb.8:
	leaq	24(%rsp), %rdi
	movl	$4004, %esi                     # imm = 0xFA4
	callq	hipMalloc
.LBB0_9:
	leaq	8(%rsp), %rdi
	movl	$60000, %esi                    # imm = 0xEA60
	callq	hipMalloc
	movq	16(%rsp), %rdi
	leaq	64048(%rsp), %rsi
	movl	$60000, %edx                    # imm = 0xEA60
	movl	$1, %ecx
	callq	hipMemcpy
	cmpb	$110, 6(%rsp)
	jne	.LBB0_11
# %bb.10:
	movq	24(%rsp), %rdi
	leaq	32(%rsp), %rsi
	movl	$4004, %edx                     # imm = 0xFA4
	movl	$1, %ecx
	callq	hipMemcpy
	cmpb	$110, 6(%rsp)
	je	.LBB0_14
.LBB0_11:                               # %.thread
	leaq	32(%rsp), %rsi
	movl	$kernel_c, %edi
	movl	$4004, %edx                     # imm = 0xFA4
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	movzbl	6(%rsp), %eax
	cmpl	$99, %eax
	je	.LBB0_16
# %bb.12:                               # %.thread
	cmpl	$115, %eax
	je	.LBB0_18
# %bb.13:                               # %.thread
	cmpl	$110, %eax
	jne	.LBB0_20
.LBB0_14:                               # %.thread55
	movabsq	$4294967311, %rdi               # imm = 0x10000000F
	leaq	1009(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_20
# %bb.15:
	movq	16(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	$1001, %ecx                     # imm = 0x3E9
	movl	$15000, %r8d                    # imm = 0x3A98
	callq	_Z25__device_stub__naive_convPfS_S_ii
	jmp	.LBB0_20
.LBB0_18:
	movabsq	$4294967311, %rdi               # imm = 0x10000000F
	leaq	1009(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_20
# %bb.19:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	$1001, %edx                     # imm = 0x3E9
	movl	$15000, %ecx                    # imm = 0x3A98
	callq	_Z30__device_stub__shared_mem_convPfS_ii
	jmp	.LBB0_20
.LBB0_16:
	movabsq	$4294967311, %rdi               # imm = 0x10000000F
	leaq	1009(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_20
# %bb.17:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	$1001, %edx                     # imm = 0x3E9
	movl	$15000, %ecx                    # imm = 0x3A98
	callq	_Z29__device_stub__const_mem_convPfS_ii
.LBB0_20:
	movq	8(%rsp), %rsi
	leaq	4048(%rsp), %rdi
	movl	$60000, %edx                    # imm = 0xEA60
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	xorl	%r14d, %r14d
	leaq	7(%rsp), %rbx
.LBB0_21:                               # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	4048(%rsp,%r14,4), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movb	$32, 7(%rsp)
	movq	(%rax), %rcx
	movq	-24(%rcx), %rcx
	cmpq	$0, 16(%rax,%rcx)
	je	.LBB0_23
# %bb.22:                               #   in Loop: Header=BB0_21 Depth=1
	movl	$1, %edx
	movq	%rax, %rdi
	movq	%rbx, %rsi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB0_24
.LBB0_23:                               #   in Loop: Header=BB0_21 Depth=1
	movq	%rax, %rdi
	movl	$32, %esi
	callq	_ZNSo3putEc
.LBB0_24:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
                                        #   in Loop: Header=BB0_21 Depth=1
	incq	%r14
	cmpq	$15000, %r14                    # imm = 0x3A98
	jne	.LBB0_21
# %bb.25:
	movq	_ZSt4cout(%rip), %rax
	movl	$_ZSt4cout, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	callq	hipDeviceSynchronize
	xorl	%eax, %eax
	addq	$124056, %rsp                   # imm = 0x1E498
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	main, .Lfunc_end0-main
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__naive_convPfS_S_ii # -- Begin function _Z25__device_stub__naive_convPfS_S_ii
	.type	_Z25__device_stub__naive_convPfS_S_ii,@function
_Z25__device_stub__naive_convPfS_S_ii:  # @_Z25__device_stub__naive_convPfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10naive_convPfS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z25__device_stub__naive_convPfS_S_ii, .Lfunc_end1-_Z25__device_stub__naive_convPfS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__const_mem_convPfS_ii # -- Begin function _Z29__device_stub__const_mem_convPfS_ii
	.type	_Z29__device_stub__const_mem_convPfS_ii,@function
_Z29__device_stub__const_mem_convPfS_ii: # @_Z29__device_stub__const_mem_convPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14const_mem_convPfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z29__device_stub__const_mem_convPfS_ii, .Lfunc_end2-_Z29__device_stub__const_mem_convPfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__shared_mem_convPfS_ii # -- Begin function _Z30__device_stub__shared_mem_convPfS_ii
	.type	_Z30__device_stub__shared_mem_convPfS_ii,@function
_Z30__device_stub__shared_mem_convPfS_ii: # @_Z30__device_stub__shared_mem_convPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15shared_mem_convPfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z30__device_stub__shared_mem_convPfS_ii, .Lfunc_end3-_Z30__device_stub__shared_mem_convPfS_ii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10naive_convPfS_S_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14const_mem_convPfS_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15shared_mem_convPfS_ii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$kernel_c, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movl	$4004, %r9d                     # imm = 0xFA4
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	kernel_c,@object                # @kernel_c
	.local	kernel_c
	.comm	kernel_c,4004,16
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Which version ('n': naive, 'c': constant mem, 's': shared mem): "
	.size	.L.str, 65

	.type	_Z10naive_convPfS_S_ii,@object  # @_Z10naive_convPfS_S_ii
	.section	.rodata,"a",@progbits
	.globl	_Z10naive_convPfS_S_ii
	.p2align	3, 0x0
_Z10naive_convPfS_S_ii:
	.quad	_Z25__device_stub__naive_convPfS_S_ii
	.size	_Z10naive_convPfS_S_ii, 8

	.type	_Z14const_mem_convPfS_ii,@object # @_Z14const_mem_convPfS_ii
	.globl	_Z14const_mem_convPfS_ii
	.p2align	3, 0x0
_Z14const_mem_convPfS_ii:
	.quad	_Z29__device_stub__const_mem_convPfS_ii
	.size	_Z14const_mem_convPfS_ii, 8

	.type	_Z15shared_mem_convPfS_ii,@object # @_Z15shared_mem_convPfS_ii
	.globl	_Z15shared_mem_convPfS_ii
	.p2align	3, 0x0
_Z15shared_mem_convPfS_ii:
	.quad	_Z30__device_stub__shared_mem_convPfS_ii
	.size	_Z15shared_mem_convPfS_ii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z10naive_convPfS_S_ii"
	.size	.L__unnamed_1, 23

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z14const_mem_convPfS_ii"
	.size	.L__unnamed_2, 25

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z15shared_mem_convPfS_ii"
	.size	.L__unnamed_3, 26

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"kernel_c"
	.size	.L__unnamed_4, 9

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__naive_convPfS_S_ii
	.addrsig_sym _Z29__device_stub__const_mem_convPfS_ii
	.addrsig_sym _Z30__device_stub__shared_mem_convPfS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym kernel_c
	.addrsig_sym _ZSt4cout
	.addrsig_sym _ZSt3cin
	.addrsig_sym _Z10naive_convPfS_S_ii
	.addrsig_sym _Z14const_mem_convPfS_ii
	.addrsig_sym _Z15shared_mem_convPfS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10naive_convPfS_S_ii  ; -- Begin function _Z10naive_convPfS_S_ii
	.globl	_Z10naive_convPfS_S_ii
	.p2align	8
	.type	_Z10naive_convPfS_S_ii,@function
_Z10naive_convPfS_S_ii:                 ; @_Z10naive_convPfS_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b256 s[4:11], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s2, 0xffff
	s_cmp_lt_i32 s10, 1
	v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
	s_cbranch_scc1 .LBB0_5
; %bb.1:                                ; %.lr.ph.preheader
	s_lshr_b32 s0, s10, 31
	v_mov_b32_e32 v3, 0
	s_add_i32 s0, s10, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s0, s0, 1
	v_mov_b32_e32 v0, v3
	s_delay_alu instid0(VALU_DEP_3)
	v_subrev_nc_u32_e32 v2, s0, v1
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, -1, v2
	v_cmp_gt_i32_e64 s0, s11, v2
	s_and_b32 s1, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_load_b32 s1, s[6:7], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v0, s1, v4
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s10, s10, -1
	v_add_nc_u32_e32 v2, 1, v2
	s_add_u32 s6, s6, 4
	s_addc_u32 s7, s7, 0
	s_cmp_eq_u32 s10, 0
	s_cbranch_scc0 .LBB0_2
	s_branch .LBB0_6
.LBB0_5:
	v_mov_b32_e32 v0, 0
.LBB0_6:                                ; %Flow45
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_gt_i32_e64 s11, v1
	s_cbranch_execz .LBB0_8
; %bb.7:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s8, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB0_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10naive_convPfS_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10naive_convPfS_S_ii, .Lfunc_end0-_Z10naive_convPfS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 268
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z14const_mem_convPfS_ii ; -- Begin function _Z14const_mem_convPfS_ii
	.globl	_Z14const_mem_convPfS_ii
	.p2align	8
	.type	_Z14const_mem_convPfS_ii,@function
_Z14const_mem_convPfS_ii:               ; @_Z14const_mem_convPfS_ii
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s8, 0xffff
	s_cmp_lt_i32 s2, 1
	v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
	s_cbranch_scc1 .LBB1_5
; %bb.1:                                ; %.lr.ph.preheader
	s_lshr_b32 s0, s2, 31
	v_mov_b32_e32 v3, 0
	s_add_i32 s0, s2, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_ashr_i32 s0, s0, 1
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, kernel_c@rel32@lo+4
	s_addc_u32 s9, s9, kernel_c@rel32@hi+12
	v_subrev_nc_u32_e32 v2, s0, v1
	v_mov_b32_e32 v0, v3
.LBB1_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, -1, v2
	v_cmp_gt_i32_e64 s0, s3, v2
	s_and_b32 s1, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB1_4
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_load_b32 s1, s[8:9], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v0, s1, v4
.LBB1_4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s2, s2, -1
	v_add_nc_u32_e32 v2, 1, v2
	s_add_u32 s8, s8, 4
	s_addc_u32 s9, s9, 0
	s_cmp_eq_u32 s2, 0
	s_cbranch_scc0 .LBB1_2
	s_branch .LBB1_6
.LBB1_5:
	v_mov_b32_e32 v0, 0
.LBB1_6:                                ; %Flow40
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB1_8
; %bb.7:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s6, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB1_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14const_mem_convPfS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z14const_mem_convPfS_ii, .Lfunc_end1-_Z14const_mem_convPfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 292
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z15shared_mem_convPfS_ii ; -- Begin function _Z15shared_mem_convPfS_ii
	.globl	_Z15shared_mem_convPfS_ii
	.p2align	8
	.type	_Z15shared_mem_convPfS_ii,@function
_Z15shared_mem_convPfS_ii:              ; @_Z15shared_mem_convPfS_ii
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[8:9], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s1, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s12, s15, s1
	v_add_nc_u32_e32 v1, s12, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s9, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB2_2
; %bb.1:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_co_u32 v2, s0, s4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
	global_load_b32 v2, v[2:3], off
	v_lshlrev_b32_e32 v3, 2, v0
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v2
.LBB2_2:
	s_or_b32 exec_lo, exec_lo, s2
	s_cmp_lt_i32 s8, 1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB2_13
; %bb.3:                                ; %.lr.ph.preheader
	s_lshr_b32 s0, s8, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s8, s0
	s_ashr_i32 s0, s0, 1
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, kernel_c@rel32@lo+4
	s_addc_u32 s11, s11, kernel_c@rel32@hi+12
	v_subrev_nc_u32_e32 v0, s0, v0
	v_mov_b32_e32 v3, 0
	v_subrev_nc_u32_e32 v2, s0, v1
	s_add_i32 s13, s12, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v4, 2, v0
	v_mov_b32_e32 v0, v3
.LBB2_4:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e64 s0, 0, v2
	v_cmp_le_i32_e64 s1, s9, v2
	v_cmp_gt_i32_e64 s2, s12, v2
	v_cmp_le_i32_e64 s3, s13, v2
                                        ; implicit-def: $vgpr5
	s_or_b32 s0, s0, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, s2, s3
	s_or_b32 s1, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_xor_b32 s2, s1, -1
	s_mov_b32 s1, 0
	s_and_saveexec_b32 s3, s2
	s_xor_b32 s2, exec_lo, s3
	s_cbranch_execz .LBB2_6
; %bb.5:                                ;   in Loop: Header=BB2_4 Depth=1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	ds_load_b32 v5, v4
	s_mov_b32 s1, exec_lo
.LBB2_6:                                ; %Flow
                                        ;   in Loop: Header=BB2_4 Depth=1
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB2_10
; %bb.7:                                ;   in Loop: Header=BB2_4 Depth=1
	s_xor_b32 s14, s0, -1
	s_mov_b32 s0, s1
                                        ; implicit-def: $vgpr5
	s_and_saveexec_b32 s3, s14
	s_cbranch_execz .LBB2_9
; %bb.8:                                ;   in Loop: Header=BB2_4 Depth=1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_lshlrev_b64 v[5:6], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s0, s4, v5
	v_add_co_ci_u32_e64 v6, s0, s5, v6, s0
	s_or_b32 s0, s1, exec_lo
	global_load_b32 v5, v[5:6], off
.LBB2_9:                                ; %Flow66
                                        ;   in Loop: Header=BB2_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s1, s1, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s1, s1, s0
.LBB2_10:                               ; %Flow65
                                        ;   in Loop: Header=BB2_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB2_12
; %bb.11:                               ; %.sink.split
                                        ;   in Loop: Header=BB2_4 Depth=1
	s_load_b32 s1, s[10:11], 0x0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v0, s1, v5
.LBB2_12:                               ;   in Loop: Header=BB2_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v2, 1, v2
	v_add_nc_u32_e32 v4, 4, v4
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_add_i32 s8, s8, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s8, 0
	s_cbranch_scc0 .LBB2_4
	s_branch .LBB2_14
.LBB2_13:
	v_mov_b32_e32 v0, 0
.LBB2_14:                               ; %Flow68
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB2_16
; %bb.15:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s6, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB2_16:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15shared_mem_convPfS_ii
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z15shared_mem_convPfS_ii, .Lfunc_end2-_Z15shared_mem_convPfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 532
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	kernel_c                ; @kernel_c
	.type	kernel_c,@object
	.section	.bss,"aw",@nobits
	.globl	kernel_c
	.p2align	4, 0x0
kernel_c:
	.zero	4004
	.size	kernel_c, 4004

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym kernel_c
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10naive_convPfS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10naive_convPfS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14const_mem_convPfS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14const_mem_convPfS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15shared_mem_convPfS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15shared_mem_convPfS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
