
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <cuda.h>

#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <ctype.h>

#define MAX_SAVES 1000
#define QTD_NUMBERS 3

#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
   if (code != cudaSuccess) 
   {
      fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
      if (abort) exit(code);
   }
}

__global__
void GenSeq(uint32_t *divs, uint8_t*arr, uint32_t arrSize, uint32_t* index, uint32_t MAXgTid){
    uint32_t ThrPerBlk = blockDim.x;
	uint32_t MYbid = blockIdx.x;
	uint32_t MYtid = threadIdx.x;
    uint32_t MYgtid = ThrPerBlk * MYbid + MYtid;
   
    uint8_t i;
    // uint32_t qtdNumbers = sizeof(divs) - 1;
    //uint8_t tempArr[qtd_numbers];
    uint32_t offset = MYgtid * QTD_NUMBERS;
    // printf("ThrPerBlk: %u, Mybid: %u, Mytid: %d, Mygtid: %u, offset: %u\n", ThrPerBlk, MYbid, MYtid, ThrPerBlk * MYbid + MYtid, offset);
    if(offset >= MAXgTid)
        return;
    
    uint8_t tempArr[QTD_NUMBERS];

    for(i = 0; i < QTD_NUMBERS; i++){
        tempArr[i] = (MYgtid %  divs[i]) / divs[i + 1];
    }

    uint32_t currIndex = atomicAdd(index, QTD_NUMBERS);
    if(currIndex > MAX_SAVES)
        return;

    printf("ThrPerBlk: %u, Mybid: %u, Mytid: %d, Mygtid: %u, offset: %u, currIndex: %u\n", ThrPerBlk, MYbid, MYtid, MYgtid, offset, currIndex);
    for(i = 0; i < QTD_NUMBERS; i++){
        arr[currIndex] = tempArr[i];
        currIndex++;
    }
}   

int main(){
	cudaError_t cudaStatus;
	cudaEvent_t time1, time2, time3;
	float totalTime, kernelExecutionTime, tfrGPUtoCPU;
    uint32_t ThrPerBlk = 32, NumBlocks = 0;

	int NumGPUs = 0; cudaGetDeviceCount(&NumGPUs);
	if (NumGPUs == 0){
		std::cout << "\nNo CUDA Device is available\n";
		exit(EXIT_FAILURE);
	}

    uint32_t i = 0;
    uint32_t possibilities = 1;
    uint8_t  numbers[] = {3,3,3};
    // uint8_t  qtd_numbers = sizeof(numbers);
    for(i = 0; i < QTD_NUMBERS; i++){
        possibilities *= numbers[i];
    }
    
    uint32_t  divs[QTD_NUMBERS + 1];
    divs[0] = possibilities;
    for(i = 0; i < QTD_NUMBERS; i++){
        divs[i + 1] = divs[i] / numbers[i];
    }
                for(i = 0; i < QTD_NUMBERS + 1; i++){ //DEBUG
                    std::cout << divs[i] << ", ";
                }
                std::cout << std::endl;

    // uint32_t arrSize = possibilities * QTD_NUMBERS * sizeof(uint8_t);
    uint32_t MAXgTid = possibilities * QTD_NUMBERS * sizeof(uint8_t);
    uint32_t arrSize = ((MAX_SAVES + QTD_NUMBERS -1) / QTD_NUMBERS) * QTD_NUMBERS;
                std::cout << "arrSize: " << arrSize << std::endl; //DEBUG
    uint8_t* sequencies = (uint8_t*)malloc(arrSize);

    uint32_t* GPUcont = nullptr;
    uint32_t* GPUdivs = nullptr;
    uint8_t* GPUsequencies = nullptr;    

    NumBlocks = (possibilities + ThrPerBlk - 1) / ThrPerBlk;
                std::cout << "NumBlocks: " << NumBlocks << ", ThrPerBlk: " << ThrPerBlk << std::endl; // debug
                // getchar();

    cudaEventCreate(&time1); 
    cudaEventCreate(&time2);
    cudaEventCreate(&time3);

	cudaEventRecord(time1, 0);
	gpuErrchk(cudaMalloc((void **)&GPUcont, sizeof(uint32_t)));
    gpuErrchk(cudaMemset(GPUcont, 0, sizeof(uint32_t)));

	gpuErrchk(cudaMalloc((void **)&GPUsequencies, arrSize));
    gpuErrchk(cudaMalloc((void **)&GPUdivs, (QTD_NUMBERS + 1) * sizeof(uint32_t)));
    gpuErrchk(cudaMemcpy(GPUdivs, divs, (QTD_NUMBERS + 1) * sizeof(uint32_t), cudaMemcpyHostToDevice));

	GenSeq <<< NumBlocks, ThrPerBlk >>> (GPUdivs, GPUsequencies, arrSize, GPUcont, MAXgTid);

	gpuErrchk(cudaDeviceSynchronize());
	cudaEventRecord(time2, 0);

	gpuErrchk(cudaMemcpy(sequencies, GPUsequencies, arrSize, cudaMemcpyDeviceToHost));
	cudaEventRecord(time3, 0);

	cudaEventSynchronize(time1); cudaEventSynchronize(time2);
	cudaEventSynchronize(time3);
	cudaEventElapsedTime(&totalTime, time1, time3);
	cudaEventElapsedTime(&kernelExecutionTime, time1, time2);
	cudaEventElapsedTime(&tfrGPUtoCPU, time2, time3);

	gpuErrchk(cudaDeviceSynchronize());
    
    for(i = 0; i < arrSize; i++){
        if(i % QTD_NUMBERS == 0)
            std::cout << std::endl;
        else
            std::cout << ", ";

        std::cout << int(sequencies[i]); 
    }

	printf("\n\n-------------------- ... ----------------------------\n");
	printf("Kernel Execution = %5.2f ms\n",   kernelExecutionTime);
    printf("GPU->CPU Transfer = %5.2f ms ... %4d MB ... %6.2f GB/s\n",  tfrGPUtoCPU, arrSize / 1024 / 1024, 
                                                                        (float)arrSize / (tfrGPUtoCPU * 1024.0 * 1024.0));
	printf("Total time elapsed = %5.2f ms\n", totalTime);
	printf("-------------------- ... ----------------------------\n");


    cudaFree(GPUdivs);
	cudaFree(GPUsequencies);
    cudaEventDestroy(time1); 
    cudaEventDestroy(time2);
	cudaEventDestroy(time3);

	cudaStatus = cudaDeviceReset();
	if (cudaStatus != cudaSuccess){
		std::cout << "cudaDeviceReset failed!";
		free(sequencies); exit(EXIT_FAILURE);
	}
	free(sequencies);

	return(EXIT_SUCCESS);
}
	.file	"tmpxft_0022ff2c_00000000-6_numbers.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3639:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
	.string	"GPUassert: %s %s %d\n"
	.section	.text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
	.weak	_Z9gpuAssert9cudaErrorPKcib
	.type	_Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB3635:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L8
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movl	%edx, 12(%rsp)
	movq	%rsi, (%rsp)
	call	cudaGetErrorString@PLT
	movl	12(%rsp), %r9d
	movq	(%rsp), %r8
	leaq	.LC0(%rip), %rdx
	movq	stderr(%rip), %rdi
	movq	%rax, %rcx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	testb	%bpl, %bpl
	je	.L2
	movl	%ebx, %edi
	call	exit@PLT
.L2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
.L8:
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
	.text
	.globl	_Z31__device_stub__Z6GenSeqPjPhjS_jPjPhjS_j
	.type	_Z31__device_stub__Z6GenSeqPjPhjS_jPjPhjS_j, @function
_Z31__device_stub__Z6GenSeqPjPhjS_jPjPhjS_j:
.LFB3661:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movq	%rsp, %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z6GenSeqPjPhjS_j(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L12:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3661:
	.size	_Z31__device_stub__Z6GenSeqPjPhjS_jPjPhjS_j, .-_Z31__device_stub__Z6GenSeqPjPhjS_jPjPhjS_j
	.globl	_Z6GenSeqPjPhjS_j
	.type	_Z6GenSeqPjPhjS_j, @function
_Z6GenSeqPjPhjS_j:
.LFB3662:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z6GenSeqPjPhjS_jPjPhjS_j
	.cfi_endproc
.LFE3662:
	.size	_Z6GenSeqPjPhjS_j, .-_Z6GenSeqPjPhjS_j
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"\nNo CUDA Device is available\n"
.LC2:
	.string	", "
.LC3:
	.string	"arrSize: "
.LC4:
	.string	"NumBlocks: "
.LC5:
	.string	", ThrPerBlk: "
.LC6:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/vinicius-r-silva/cuda_studies/master/number_sequencies/numbers.cu"
.LC7:
	.string	"\n\n-------------------- ... ----------------------------\n"
.LC8:
	.string	"Kernel Execution = %5.2f ms\n"
.LC11:
	.string	"GPU->CPU Transfer = %5.2f ms ... %4d MB ... %6.2f GB/s\n"
.LC12:
	.string	"Total time elapsed = %5.2f ms\n"
.LC13:
	.string	"-------------------- ... ----------------------------\n"
.LC14:
	.string	"cudaDeviceReset failed!"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	xorl	%edx, %edx
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	leaq	_ZSt4cout(%rip), %rbx
	subq	$120, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rdi
	movl	%edx, 12(%rsp)
	call	cudaGetDeviceCount@PLT
	cmpl	$0, 12(%rsp)
	jne	.L18
	leaq	.LC1(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	jmp	.L29
.L18:
	movabsq	$38654705691, %rax
	xorl	%ebp, %ebp
	leaq	.LC2(%rip), %r13
	movq	%rax, 88(%rsp)
	movabsq	$4294967299, %rax
	movq	%rax, 96(%rsp)
.L19:
	movl	88(%rsp,%rbp,4), %esi
	movq	%rbx, %rdi
	incq	%rbp
	call	_ZNSo9_M_insertImEERSoT_@PLT
	movq	%r13, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cmpq	$4, %rbp
	jne	.L19
	movq	%rbx, %rdi
	leaq	.LC6(%rip), %rbp
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$1002, %esi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertImEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movl	$1002, %edi
	call	malloc@PLT
	leaq	.LC4(%rip), %rsi
	movq	%rbx, %rdi
	movq	%rax, %r12
	xorl	%eax, %eax
	movq	%rax, 40(%rsp)
	movq	%rax, 48(%rsp)
	movq	%rax, 56(%rsp)
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$1, %esi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertImEERSoT_@PLT
	leaq	.LC5(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$32, %esi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertImEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	leaq	16(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	24(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	32(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	leaq	40(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$107, %edx
	movq	%rbp, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	movl	$4, %edx
	call	cudaMemset@PLT
	movl	$1, %ecx
	movl	$108, %edx
	movq	%rbp, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	leaq	56(%rsp), %rdi
	movl	$1002, %esi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$110, %edx
	movq	%rbp, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	leaq	48(%rsp), %rdi
	movl	$16, %esi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$111, %edx
	movq	%rbp, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	48(%rsp), %rdi
	movl	$1, %ecx
	movl	$16, %edx
	leaq	88(%rsp), %rsi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$112, %edx
	movq	%rbp, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movl	$134217729, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$5, %rdx
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rdx, 76(%rsp)
	movl	$1, 84(%rsp)
	movq	%rdi, 64(%rsp)
	movl	$1, 72(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	movq	40(%rsp), %rcx
	movq	56(%rsp), %rsi
	movl	$1002, %edx
	movl	$81, %r8d
	movq	48(%rsp), %rdi
	call	_Z31__device_stub__Z6GenSeqPjPhjS_jPjPhjS_j
.L20:
	call	cudaDeviceSynchronize@PLT
	movl	$1, %ecx
	movl	$116, %edx
	movq	%rbp, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	56(%rsp), %rsi
	movl	$2, %ecx
	movq	%r12, %rdi
	movl	$1002, %edx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$119, %edx
	movq	%rbp, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	16(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	24(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	32(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	32(%rsp), %rdx
	movq	16(%rsp), %rsi
	leaq	8(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	leaq	64(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	leaq	76(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	call	cudaDeviceSynchronize@PLT
	movq	%rbp, %rsi
	movl	$1, %ecx
	xorl	%ebp, %ebp
	movl	%eax, %edi
	movl	$128, %edx
	call	_Z9gpuAssert9cudaErrorPKcib
.L23:
	imull	$-1431655765, %ebp, %eax
	cmpl	$1431655765, %eax
	ja	.L21
	movq	%rbx, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	jmp	.L22
.L21:
	movq	%r13, %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L22:
	movzbl	(%r12,%rbp), %esi
	movq	%rbx, %rdi
	incq	%rbp
	call	_ZNSolsEi@PLT
	cmpq	$1002, %rbp
	jne	.L23
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	64(%rsp), %xmm0
	call	__printf_chk@PLT
	xorl	%edx, %edx
	movb	$2, %al
	movsd	.LC9(%rip), %xmm1
	cvtss2sd	76(%rsp), %xmm2
	movaps	%xmm2, %xmm0
	leaq	.LC11(%rip), %rsi
	movl	$2, %edi
	mulsd	%xmm1, %xmm0
	mulsd	%xmm1, %xmm0
	movsd	.LC10(%rip), %xmm1
	divsd	%xmm0, %xmm1
	movaps	%xmm2, %xmm0
	call	__printf_chk@PLT
	leaq	.LC12(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	8(%rsp), %xmm0
	call	__printf_chk@PLT
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC13(%rip), %rsi
	call	__printf_chk@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	24(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	32(%rsp), %rdi
	call	cudaEventDestroy@PLT
	call	cudaDeviceReset@PLT
	testl	%eax, %eax
	je	.L24
	movq	%rbx, %rdi
	leaq	.LC14(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%r12, %rdi
	call	free@PLT
.L29:
	movl	$1, %edi
	call	exit@PLT
.L24:
	movq	%r12, %rdi
	call	free@PLT
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$120, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	main, .-main
	.section	.rodata.str1.1
.LC15:
	.string	"_Z6GenSeqPjPhjS_j"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3664:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6GenSeqPjPhjS_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3664:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC9:
	.long	0
	.long	1083179008
	.align 8
.LC10:
	.long	0
	.long	1083133952
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>



#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <ctype.h>

#define MAX_SAVES 1000
#define QTD_NUMBERS 3

#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
   if (code != hipSuccess) 
   {
      fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
      if (abort) exit(code);
   }
}

__global__
void GenSeq(uint32_t *divs, uint8_t*arr, uint32_t arrSize, uint32_t* index, uint32_t MAXgTid){
    uint32_t ThrPerBlk = blockDim.x;
	uint32_t MYbid = blockIdx.x;
	uint32_t MYtid = threadIdx.x;
    uint32_t MYgtid = ThrPerBlk * MYbid + MYtid;
   
    uint8_t i;
    // uint32_t qtdNumbers = sizeof(divs) - 1;
    //uint8_t tempArr[qtd_numbers];
    uint32_t offset = MYgtid * QTD_NUMBERS;
    // printf("ThrPerBlk: %u, Mybid: %u, Mytid: %d, Mygtid: %u, offset: %u\n", ThrPerBlk, MYbid, MYtid, ThrPerBlk * MYbid + MYtid, offset);
    if(offset >= MAXgTid)
        return;
    
    uint8_t tempArr[QTD_NUMBERS];

    for(i = 0; i < QTD_NUMBERS; i++){
        tempArr[i] = (MYgtid %  divs[i]) / divs[i + 1];
    }

    uint32_t currIndex = atomicAdd(index, QTD_NUMBERS);
    if(currIndex > MAX_SAVES)
        return;

    printf("ThrPerBlk: %u, Mybid: %u, Mytid: %d, Mygtid: %u, offset: %u, currIndex: %u\n", ThrPerBlk, MYbid, MYtid, MYgtid, offset, currIndex);
    for(i = 0; i < QTD_NUMBERS; i++){
        arr[currIndex] = tempArr[i];
        currIndex++;
    }
}   

int main(){
	hipError_t cudaStatus;
	hipEvent_t time1, time2, time3;
	float totalTime, kernelExecutionTime, tfrGPUtoCPU;
    uint32_t ThrPerBlk = 32, NumBlocks = 0;

	int NumGPUs = 0; hipGetDeviceCount(&NumGPUs);
	if (NumGPUs == 0){
		std::cout << "\nNo CUDA Device is available\n";
		exit(EXIT_FAILURE);
	}

    uint32_t i = 0;
    uint32_t possibilities = 1;
    uint8_t  numbers[] = {3,3,3};
    // uint8_t  qtd_numbers = sizeof(numbers);
    for(i = 0; i < QTD_NUMBERS; i++){
        possibilities *= numbers[i];
    }
    
    uint32_t  divs[QTD_NUMBERS + 1];
    divs[0] = possibilities;
    for(i = 0; i < QTD_NUMBERS; i++){
        divs[i + 1] = divs[i] / numbers[i];
    }
                for(i = 0; i < QTD_NUMBERS + 1; i++){ //DEBUG
                    std::cout << divs[i] << ", ";
                }
                std::cout << std::endl;

    // uint32_t arrSize = possibilities * QTD_NUMBERS * sizeof(uint8_t);
    uint32_t MAXgTid = possibilities * QTD_NUMBERS * sizeof(uint8_t);
    uint32_t arrSize = ((MAX_SAVES + QTD_NUMBERS -1) / QTD_NUMBERS) * QTD_NUMBERS;
                std::cout << "arrSize: " << arrSize << std::endl; //DEBUG
    uint8_t* sequencies = (uint8_t*)malloc(arrSize);

    uint32_t* GPUcont = nullptr;
    uint32_t* GPUdivs = nullptr;
    uint8_t* GPUsequencies = nullptr;    

    NumBlocks = (possibilities + ThrPerBlk - 1) / ThrPerBlk;
                std::cout << "NumBlocks: " << NumBlocks << ", ThrPerBlk: " << ThrPerBlk << std::endl; // debug
                // getchar();

    hipEventCreate(&time1); 
    hipEventCreate(&time2);
    hipEventCreate(&time3);

	hipEventRecord(time1, 0);
	gpuErrchk(hipMalloc((void **)&GPUcont, sizeof(uint32_t)));
    gpuErrchk(hipMemset(GPUcont, 0, sizeof(uint32_t)));

	gpuErrchk(hipMalloc((void **)&GPUsequencies, arrSize));
    gpuErrchk(hipMalloc((void **)&GPUdivs, (QTD_NUMBERS + 1) * sizeof(uint32_t)));
    gpuErrchk(hipMemcpy(GPUdivs, divs, (QTD_NUMBERS + 1) * sizeof(uint32_t), hipMemcpyHostToDevice));

	GenSeq <<< NumBlocks, ThrPerBlk >>> (GPUdivs, GPUsequencies, arrSize, GPUcont, MAXgTid);

	gpuErrchk(hipDeviceSynchronize());
	hipEventRecord(time2, 0);

	gpuErrchk(hipMemcpy(sequencies, GPUsequencies, arrSize, hipMemcpyDeviceToHost));
	hipEventRecord(time3, 0);

	hipEventSynchronize(time1); hipEventSynchronize(time2);
	hipEventSynchronize(time3);
	hipEventElapsedTime(&totalTime, time1, time3);
	hipEventElapsedTime(&kernelExecutionTime, time1, time2);
	hipEventElapsedTime(&tfrGPUtoCPU, time2, time3);

	gpuErrchk(hipDeviceSynchronize());
    
    for(i = 0; i < arrSize; i++){
        if(i % QTD_NUMBERS == 0)
            std::cout << std::endl;
        else
            std::cout << ", ";

        std::cout << int(sequencies[i]); 
    }

	printf("\n\n-------------------- ... ----------------------------\n");
	printf("Kernel Execution = %5.2f ms\n",   kernelExecutionTime);
    printf("GPU->CPU Transfer = %5.2f ms ... %4d MB ... %6.2f GB/s\n",  tfrGPUtoCPU, arrSize / 1024 / 1024, 
                                                                        (float)arrSize / (tfrGPUtoCPU * 1024.0 * 1024.0));
	printf("Total time elapsed = %5.2f ms\n", totalTime);
	printf("-------------------- ... ----------------------------\n");


    hipFree(GPUdivs);
	hipFree(GPUsequencies);
    hipEventDestroy(time1); 
    hipEventDestroy(time2);
	hipEventDestroy(time3);

	cudaStatus = hipDeviceReset();
	if (cudaStatus != hipSuccess){
		std::cout << "hipDeviceReset failed!";
		free(sequencies); exit(EXIT_FAILURE);
	}
	free(sequencies);

	return(EXIT_SUCCESS);
}
	.text
	.file	"numbers.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z21__device_stub__GenSeqPjPhjS_j # -- Begin function _Z21__device_stub__GenSeqPjPhjS_j
	.type	_Z21__device_stub__GenSeqPjPhjS_j,@function
_Z21__device_stub__GenSeqPjPhjS_j:      # @_Z21__device_stub__GenSeqPjPhjS_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6GenSeqPjPhjS_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__GenSeqPjPhjS_j, .Lfunc_end0-_Z21__device_stub__GenSeqPjPhjS_j
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI1_0:
	.quad	0x4090000000000000              # double 1024
.LCPI1_1:
	.quad	0x408f500000000000              # double 1002
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	108(%rsp), %rbx
	movl	$0, (%rbx)
	movq	%rbx, %rdi
	callq	hipGetDeviceCount
	cmpl	$0, (%rbx)
	je	.LBB1_22
# %bb.1:
	movw	$771, 13(%rsp)                  # imm = 0x303
	movb	$3, 15(%rsp)
	movl	$27, 80(%rsp)
	movl	$27, %eax
	movl	$1, %ecx
.LBB1_2:                                # =>This Inner Loop Header: Depth=1
	movzbl	12(%rsp,%rcx), %esi
	xorl	%edx, %edx
	divl	%esi
	movl	%eax, 80(%rsp,%rcx,4)
	incq	%rcx
	cmpq	$4, %rcx
	jne	.LBB1_2
# %bb.3:                                # %.preheader.preheader
	xorl	%ebx, %ebx
.LBB1_4:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movl	80(%rsp,%rbx,4), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertImEERSoT_
	movl	$.L.str.1, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%rbx
	cmpq	$4, %rbx
	jne	.LBB1_4
# %bb.5:
	movq	_ZSt4cout(%rip), %rax
	movl	$_ZSt4cout, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$9, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$1002, %esi                     # imm = 0x3EA
	callq	_ZNSo9_M_insertImEERSoT_
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$1002, %edi                     # imm = 0x3EA
	callq	malloc
	movq	%rax, %rbx
	xorl	%eax, %eax
	leaq	72(%rsp), %r14
	movq	%rax, (%r14)
	movq	%rax, 40(%rsp)
	movq	%rax, 32(%rsp)
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$11, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$1, %esi
	callq	_ZNSo9_M_insertImEERSoT_
	movq	%rax, %r15
	movl	$.L.str.4, %esi
	movl	$13, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$32, %esi
	movq	%r15, %rdi
	callq	_ZNSo9_M_insertImEERSoT_
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	leaq	48(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventCreate
	leaq	24(%rsp), %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	movq	(%r15), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	$4, %esi
	movq	%r14, %rdi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_24
# %bb.6:                                # %_Z9gpuAssert10hipError_tPKcib.exit
	movq	72(%rsp), %rdi
	movl	$4, %edx
	xorl	%esi, %esi
	callq	hipMemset
	testl	%eax, %eax
	jne	.LBB1_25
# %bb.7:                                # %_Z9gpuAssert10hipError_tPKcib.exit44
	leaq	32(%rsp), %rdi
	movl	$1002, %esi                     # imm = 0x3EA
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_26
# %bb.8:                                # %_Z9gpuAssert10hipError_tPKcib.exit46
	leaq	40(%rsp), %rdi
	movl	$16, %esi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_27
# %bb.9:                                # %_Z9gpuAssert10hipError_tPKcib.exit48
	movq	40(%rsp), %rdi
	leaq	80(%rsp), %rsi
	movl	$16, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_28
# %bb.10:                               # %_Z9gpuAssert10hipError_tPKcib.exit50
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	31(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_12
# %bb.11:
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	72(%rsp), %rcx
	movl	$1002, %edx                     # imm = 0x3EA
	movl	$81, %r8d
	callq	_Z21__device_stub__GenSeqPjPhjS_j
.LBB1_12:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB1_29
# %bb.13:                               # %_Z9gpuAssert10hipError_tPKcib.exit52
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	32(%rsp), %rsi
	movl	$1002, %edx                     # imm = 0x3EA
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_30
# %bb.14:                               # %_Z9gpuAssert10hipError_tPKcib.exit54
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	48(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rdi
	callq	hipEventSynchronize
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	48(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	68(%rsp), %rdi
	callq	hipEventElapsedTime
	movq	48(%rsp), %rsi
	movq	24(%rsp), %rdx
	leaq	64(%rsp), %rdi
	callq	hipEventElapsedTime
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	60(%rsp), %rdi
	callq	hipEventElapsedTime
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB1_31
# %bb.15:                               # %_Z9gpuAssert10hipError_tPKcib.exit56.preheader.preheader
	xorl	%r14d, %r14d
	movl	$_ZSt4cout, %r15d
	xorl	%r12d, %r12d
.LBB1_16:                               # %_Z9gpuAssert10hipError_tPKcib.exit56.preheader
                                        # =>This Inner Loop Header: Depth=1
	movzwl	%r12w, %eax
	imull	$43691, %eax, %eax              # imm = 0xAAAB
	shrl	$17, %eax
	leal	(%rax,%rax,2), %eax
	addw	%r14w, %ax
	je	.LBB1_18
# %bb.17:                               #   in Loop: Header=BB1_16 Depth=1
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$2, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_19
.LBB1_18:                               #   in Loop: Header=BB1_16 Depth=1
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.LBB1_19:                               # %_Z9gpuAssert10hipError_tPKcib.exit56
                                        #   in Loop: Header=BB1_16 Depth=1
	movzbl	(%rbx,%r12), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	incq	%r12
	decl	%r14d
	cmpq	$1002, %r12                     # imm = 0x3EA
	jne	.LBB1_16
# %bb.20:
	movl	$.Lstr, %edi
	callq	puts@PLT
	cvtss2sd	64(%rsp), %xmm0
	movl	$.L.str.7, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	60(%rsp), %xmm0
	movsd	.LCPI1_0(%rip), %xmm1           # xmm1 = mem[0],zero
	movaps	%xmm0, %xmm2
	mulsd	%xmm1, %xmm2
	mulsd	%xmm1, %xmm2
	movsd	.LCPI1_1(%rip), %xmm1           # xmm1 = mem[0],zero
	divsd	%xmm2, %xmm1
	movl	$.L.str.8, %edi
	xorl	%esi, %esi
	movb	$2, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	68(%rsp), %xmm0
	movl	$.L.str.9, %edi
	movb	$1, %al
	callq	printf
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipEventDestroy
	movq	24(%rsp), %rdi
	callq	hipEventDestroy
	movq	16(%rsp), %rdi
	callq	hipEventDestroy
	callq	hipDeviceReset
	testl	%eax, %eax
	jne	.LBB1_33
# %bb.21:
	movq	%rbx, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$112, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_22:
	.cfi_def_cfa_offset 160
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	jmp	.LBB1_23
.LBB1_24:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.12, %esi
	movl	$.L.str.5, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$107, %r8d
	jmp	.LBB1_32
.LBB1_25:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.12, %esi
	movl	$.L.str.5, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$108, %r8d
	jmp	.LBB1_32
.LBB1_26:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.12, %esi
	movl	$.L.str.5, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$110, %r8d
	jmp	.LBB1_32
.LBB1_27:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.12, %esi
	movl	$.L.str.5, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$111, %r8d
	jmp	.LBB1_32
.LBB1_28:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.12, %esi
	movl	$.L.str.5, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$112, %r8d
	jmp	.LBB1_32
.LBB1_29:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.12, %esi
	movl	$.L.str.5, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$116, %r8d
	jmp	.LBB1_32
.LBB1_30:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.12, %esi
	movl	$.L.str.5, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$119, %r8d
	jmp	.LBB1_32
.LBB1_31:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.12, %esi
	movl	$.L.str.5, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$128, %r8d
.LBB1_32:
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebp, %edi
	callq	exit
.LBB1_33:
	movl	$_ZSt4cout, %edi
	movl	$.L.str.11, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rbx, %rdi
	callq	free
.LBB1_23:
	movl	$1, %edi
	callq	exit
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6GenSeqPjPhjS_j, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6GenSeqPjPhjS_j,@object       # @_Z6GenSeqPjPhjS_j
	.section	.rodata,"a",@progbits
	.globl	_Z6GenSeqPjPhjS_j
	.p2align	3, 0x0
_Z6GenSeqPjPhjS_j:
	.quad	_Z21__device_stub__GenSeqPjPhjS_j
	.size	_Z6GenSeqPjPhjS_j, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"\nNo CUDA Device is available\n"
	.size	.L.str, 30

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	", "
	.size	.L.str.1, 3

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"arrSize: "
	.size	.L.str.2, 10

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"NumBlocks: "
	.size	.L.str.3, 12

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	", ThrPerBlk: "
	.size	.L.str.4, 14

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/vinicius-r-silva/cuda_studies/master/number_sequencies/numbers.hip"
	.size	.L.str.5, 129

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Kernel Execution = %5.2f ms\n"
	.size	.L.str.7, 29

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"GPU->CPU Transfer = %5.2f ms ... %4d MB ... %6.2f GB/s\n"
	.size	.L.str.8, 56

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Total time elapsed = %5.2f ms\n"
	.size	.L.str.9, 31

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"hipDeviceReset failed!"
	.size	.L.str.11, 23

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"GPUassert: %s %s %d\n"
	.size	.L.str.12, 21

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6GenSeqPjPhjS_j"
	.size	.L__unnamed_1, 18

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"\n\n-------------------- ... ----------------------------"
	.size	.Lstr, 56

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"-------------------- ... ----------------------------"
	.size	.Lstr.1, 54

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__GenSeqPjPhjS_j
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6GenSeqPjPhjS_j
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6GenSeqPjPhjS_j       ; -- Begin function _Z6GenSeqPjPhjS_j
	.globl	_Z6GenSeqPjPhjS_j
	.p2align	8
	.type	_Z6GenSeqPjPhjS_j,@function
_Z6GenSeqPjPhjS_j:                      ; @_Z6GenSeqPjPhjS_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x34
	s_load_b32 s5, s[0:1], 0x20
	v_mov_b32_e32 v12, v0
	s_add_u32 s2, s0, 40
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s14, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[8:9], null, s15, s14, v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v5, v8, 1, v8
	v_cmpx_gt_u32_e64 s5, v5
	s_cbranch_execz .LBB0_312
; %bb.1:                                ; %.preheader87.preheader
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mov_b32_e32 v9, 0
	s_mov_b32 s8, 0
                                        ; implicit-def: $vgpr45
                                        ; implicit-def: $vgpr44
                                        ; implicit-def: $vgpr43
.LBB0_2:                                ; %.preheader87
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
	s_and_b32 s9, s8, 0xff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s10, s9, 2
	s_waitcnt lgkmcnt(0)
	s_load_b64 s[10:11], s[4:5], s10 offset:0x0
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v0, s10
	v_cvt_f32_u32_e32 v1, s11
	s_sub_i32 s12, 0, s10
	s_sub_i32 s13, 0, s11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v0, 0x4f7ffffe, v0 :: v_dual_mul_f32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v0, v0
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, s12, v0
	v_mul_lo_u32 v3, s13, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v0, v2
	v_add_nc_u32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v2, v1, v3
	v_and_b32_e32 v3, 0xff, v45
	v_mul_hi_u32 v0, v8, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v1, v2
	v_mul_lo_u32 v0, v0, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v8, v0
	v_subrev_nc_u32_e32 v2, s10, v0
	v_cmp_le_u32_e32 vcc_lo, s10, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	v_subrev_nc_u32_e32 v2, s10, v0
	v_cmp_le_u32_e32 vcc_lo, s10, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	v_mul_hi_u32 v1, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v1, s11
	v_add_nc_u32_e32 v4, 1, v1
	v_sub_nc_u32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v2, s11, v0
	v_cmp_le_u32_e32 vcc_lo, s11, v0
	v_dual_cndmask_b32 v1, v1, v4 :: v_dual_cndmask_b32 v0, v0, v2
	v_and_b32_e32 v4, 0xff, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v2, 1, v1
	v_cmp_le_u32_e32 vcc_lo, s11, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v1, v2, vcc_lo
	v_lshlrev_b16 v1, 8, v44
	v_lshlrev_b16 v2, 8, v0
	v_and_b32_e32 v0, 0xff, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v1, v3, v1
	v_or_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_and_b32_e32 v1, 0xffff, v1
	v_lshlrev_b32_e32 v2, 16, v4
	v_and_b32_e64 v4, 0xff, s8
	s_lshl_b32 s8, s9, 3
	v_and_b32_e32 v3, 0xffff, v0
	v_lshlrev_b32_e32 v0, 16, v0
	v_or_b32_e32 v1, v1, v2
	s_lshl_b32 s8, 0xff, s8
	v_add_nc_u16 v2, v4, 1
	v_cmp_gt_u16_e32 vcc_lo, 2, v4
	v_or_b32_e32 v0, v3, v0
	s_and_b32 vcc_lo, exec_lo, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_bfi_b32 v45, s8, v0, v1
	v_readfirstlane_b32 s8, v2
	v_lshrrev_b32_e32 v43, 16, v45
	v_lshrrev_b32_e32 v44, 8, v45
	s_cbranch_vccnz .LBB0_2
; %bb.3:
	s_mov_b32 s5, exec_lo
	s_mov_b32 s4, exec_lo
	v_mbcnt_lo_u32_b32 v0, s5, 0
                                        ; implicit-def: $vgpr1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_5
; %bb.4:
	s_load_b64 s[0:1], s[0:1], 0x18
	s_bcnt1_i32_b32 s5, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s5, s5, 3
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s5
	s_waitcnt lgkmcnt(0)
	global_atomic_add_u32 v1, v1, v2, s[0:1] glc
.LBB0_5:
	s_or_b32 exec_lo, exec_lo, s4
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v2, v0, 3, s0
	v_cmp_gt_u32_e32 vcc_lo, 0x3e9, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_312
; %bb.6:
	s_load_b64 s[2:3], s[2:3], 0x50
	v_mbcnt_lo_u32_b32 v41, -1, 0
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v17, v41
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v17
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_12
; %bb.7:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[15:16], v3, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v3, s[2:3] offset:40
	global_load_b64 v[6:7], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v0, v0, v15
	v_and_b32_e32 v1, v1, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v0, 24
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	global_load_b64 v[13:14], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[15:16]
	s_cbranch_execz .LBB0_11
; %bb.8:                                ; %.preheader3.i.i.i.preheader
	s_mov_b32 s5, 0
.LBB0_9:                                ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v3, s[2:3] offset:40
	global_load_b64 v[10:11], v3, s[2:3]
	v_dual_mov_b32 v16, v1 :: v_dual_mov_b32 v15, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v6, v15
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v4, 24, v[10:11]
	v_and_b32_e32 v4, v7, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v4, 24, v[1:2]
	v_mov_b32_e32 v1, v6
	global_load_b64 v[13:14], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[15:16]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_9
; %bb.10:                               ; %Flow613
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_11:                               ; %Flow615
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_12:                               ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v18, 0
	v_readfirstlane_b32 s4, v0
	v_readfirstlane_b32 s5, v1
	s_mov_b32 s12, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[3:4], v18, s[2:3] offset:40
	global_load_b128 v[13:16], v18, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v3
	v_readfirstlane_b32 s9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[4:5], s[8:9]
	s_mul_i32 s1, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB0_14
; %bb.13:
	v_dual_mov_b32 v19, s12 :: v_dual_mov_b32 v20, v18
	s_add_i32 s12, s10, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v13, s11
	v_add_co_ci_u32_e32 v1, vcc_lo, s12, v14, vcc_lo
	v_dual_mov_b32 v21, 2 :: v_dual_mov_b32 v22, 1
	global_store_b128 v[0:1], v[19:22], off offset:8
.LBB0_14:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[0:1], 6, v[17:18]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v15, s8
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v16, vcc_lo
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v3, v0
	s_mov_b32 s19, s16
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	v_add_co_ci_u32_e32 v1, vcc_lo, v4, v1, vcc_lo
	v_dual_mov_b32 v17, 33 :: v_dual_mov_b32 v20, v18
	v_dual_mov_b32 v19, v18 :: v_dual_mov_b32 v24, s19
	v_dual_mov_b32 v23, s18 :: v_dual_mov_b32 v22, s17
	v_mov_b32_e32 v21, s16
	s_clause 0x3
	global_store_b128 v[0:1], v[17:20], off
	global_store_b128 v[0:1], v[21:24], off offset:16
	global_store_b128 v[0:1], v[21:24], off offset:32
	global_store_b128 v[0:1], v[21:24], off offset:48
	s_and_saveexec_b32 s8, s0
	s_cbranch_execz .LBB0_22
; %bb.15:
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v18, s5
	s_mov_b32 s9, exec_lo
	s_clause 0x1
	global_load_b64 v[19:20], v6, s[2:3] offset:32 glc
	global_load_b64 v[3:4], v6, s[2:3] offset:40
	v_mov_b32_e32 v17, s4
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s4, v3
	v_and_b32_e32 v4, s5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v7, v3, 24
	v_mul_lo_u32 v4, v4, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v7, v4
	v_add_co_u32 v3, vcc_lo, v13, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v14, v4, vcc_lo
	global_store_b64 v[3:4], v[19:20], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[17:18], v6, v[17:20], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[17:18], v[19:20]
	s_cbranch_execz .LBB0_18
; %bb.16:                               ; %.preheader1.i.i.i.preheader
	s_mov_b32 s12, 0
.LBB0_17:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v15, s4 :: v_dual_mov_b32 v16, s5
	s_sleep 1
	global_store_b64 v[3:4], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v6, v[15:18], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[17:18]
	v_dual_mov_b32 v18, v11 :: v_dual_mov_b32 v17, v10
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_17
.LBB0_18:                               ; %Flow611
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v7, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v6, s12, 0
	global_load_b64 v[3:4], v7, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB0_20
; %bb.19:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[6:7], off offset:8
.LBB0_20:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[6:7], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	s_cbranch_vccnz .LBB0_22
; %bb.21:
	global_load_b32 v3, v[3:4], off offset:24
	v_mov_b32_e32 v4, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[6:7], v[3:4], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_22:                               ; %Flow612
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s1
	v_add_co_u32 v3, vcc_lo, v13, s11
	v_add_co_ci_u32_e32 v4, vcc_lo, s10, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_23:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_25
; %bb.24:                               ;   in Loop: Header=BB0_23 Depth=1
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_25:                               ;   in Loop: Header=BB0_23 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v6
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_27
; %bb.26:                               ;   in Loop: Header=BB0_23 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_28
.LBB0_27:                               ;   in Loop: Header=BB0_23 Depth=1
	s_mov_b32 s1, -1
.LBB0_28:                               ; %Flow606
                                        ;   in Loop: Header=BB0_23 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_23
; %bb.29:
	global_load_b64 v[13:14], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_33
; %bb.30:
	v_mov_b32_e32 v3, 0
	s_clause 0x2
	global_load_b64 v[0:1], v3, s[2:3] offset:40
	global_load_b64 v[6:7], v3, s[2:3] offset:24 glc
	global_load_b64 v[10:11], v3, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v4, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v1, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v18, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v15, vcc_lo, v4, s4
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[15:16]
	v_dual_cndmask_b32 v16, v16, v17 :: v_dual_cndmask_b32 v15, v15, v4
	v_mov_b32_e32 v17, v6
	v_and_b32_e32 v1, v16, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v15, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v11, v1, vcc_lo
	global_store_b64 v[0:1], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[17:18], v3, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[17:18], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_33
; %bb.31:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s0, 0
.LBB0_32:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v3, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[17:18]
	v_dual_mov_b32 v18, v7 :: v_dual_mov_b32 v17, v6
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_32
.LBB0_33:                               ; %__ockl_printf_begin.exit
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, .str@rel32@lo+4
	s_addc_u32 s5, s5, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[4:5], 0
	s_cbranch_scc0 .LBB0_119
; %bb.34:
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v42, 2, v13
	v_dual_mov_b32 v16, v14 :: v_dual_and_b32 v15, -3, v13
	v_dual_mov_b32 v19, 2 :: v_dual_mov_b32 v20, 1
	s_mov_b64 s[8:9], 0x4c
.LBB0_35:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_38 Depth 2
                                        ;     Child Loop BB0_45 Depth 2
                                        ;     Child Loop BB0_53 Depth 2
                                        ;     Child Loop BB0_61 Depth 2
                                        ;     Child Loop BB0_69 Depth 2
                                        ;     Child Loop BB0_77 Depth 2
                                        ;     Child Loop BB0_85 Depth 2
                                        ;     Child Loop BB0_93 Depth 2
                                        ;     Child Loop BB0_101 Depth 2
                                        ;     Child Loop BB0_107 Depth 2
                                        ;     Child Loop BB0_116 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[8:9], 56
                                        ; implicit-def: $vgpr23_vgpr24
                                        ; implicit-def: $sgpr19
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s10, s8, 56
	s_cselect_b32 s11, s9, 0
	s_cmp_gt_u32 s10, 7
	s_mov_b32 s0, -1
	s_cbranch_scc1 .LBB0_40
; %bb.36:                               ;   in Loop: Header=BB0_35 Depth=1
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_cmp_eq_u32 s10, 0
	s_cbranch_scc1 .LBB0_39
; %bb.37:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_lshl_b64 s[0:1], s[10:11], 3
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], s[4:5]
.LBB0_38:                               ; %.preheader31.i
                                        ;   Parent Loop BB0_35 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v0, v1, s[16:17]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s12, v[0:1]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s0, s12
	v_or_b32_e32 v23, v3, v23
	v_or_b32_e32 v24, v4, v24
	s_cbranch_scc1 .LBB0_38
.LBB0_39:                               ; %Flow582
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s0, 0
	s_mov_b32 s19, 0
.LBB0_40:                               ; %Flow584
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[4:5]
	s_cbranch_vccnz .LBB0_42
; %bb.41:                               ;   in Loop: Header=BB0_35 Depth=1
	global_load_b64 v[23:24], v1, s[4:5]
	s_add_i32 s19, s10, -8
	s_add_u32 s0, s4, 8
	s_addc_u32 s1, s5, 0
.LBB0_42:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_cmp_gt_u32 s19, 7
	s_cbranch_scc1 .LBB0_47
; %bb.43:                               ;   in Loop: Header=BB0_35 Depth=1
	v_mov_b32_e32 v25, 0
	v_mov_b32_e32 v26, 0
	s_cmp_eq_u32 s19, 0
	s_cbranch_scc1 .LBB0_46
; %bb.44:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], 0
.LBB0_45:                               ; %.preheader29.i
                                        ;   Parent Loop BB0_35 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s0, s16
	s_addc_u32 s21, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v0, v1, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s12, v[0:1]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s19, s16
	v_or_b32_e32 v25, v3, v25
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v26, v4, v26
	s_cbranch_scc1 .LBB0_45
.LBB0_46:                               ; %Flow577
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s18, 0
	s_branch .LBB0_48
.LBB0_47:                               ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $vgpr25_vgpr26
                                        ; implicit-def: $sgpr18
.LBB0_48:                               ; %Flow579
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_50
; %bb.49:                               ;   in Loop: Header=BB0_35 Depth=1
	global_load_b64 v[25:26], v1, s[0:1]
	s_add_i32 s18, s19, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_50:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_cmp_gt_u32 s18, 7
	s_cbranch_scc1 .LBB0_55
; %bb.51:                               ;   in Loop: Header=BB0_35 Depth=1
	v_mov_b32_e32 v27, 0
	v_mov_b32_e32 v28, 0
	s_cmp_eq_u32 s18, 0
	s_cbranch_scc1 .LBB0_54
; %bb.52:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], 0
.LBB0_53:                               ; %.preheader27.i
                                        ;   Parent Loop BB0_35 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s0, s16
	s_addc_u32 s21, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v0, v1, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s12, v[0:1]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s18, s16
	v_or_b32_e32 v27, v3, v27
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v28, v4, v28
	s_cbranch_scc1 .LBB0_53
.LBB0_54:                               ; %Flow572
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s19, 0
	s_branch .LBB0_56
.LBB0_55:                               ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $sgpr19
.LBB0_56:                               ; %Flow574
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_58
; %bb.57:                               ;   in Loop: Header=BB0_35 Depth=1
	global_load_b64 v[27:28], v1, s[0:1]
	s_add_i32 s19, s18, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_58:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_cmp_gt_u32 s19, 7
	s_cbranch_scc1 .LBB0_63
; %bb.59:                               ;   in Loop: Header=BB0_35 Depth=1
	v_mov_b32_e32 v29, 0
	v_mov_b32_e32 v30, 0
	s_cmp_eq_u32 s19, 0
	s_cbranch_scc1 .LBB0_62
; %bb.60:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], 0
.LBB0_61:                               ; %.preheader25.i
                                        ;   Parent Loop BB0_35 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s0, s16
	s_addc_u32 s21, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v0, v1, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s12, v[0:1]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s19, s16
	v_or_b32_e32 v29, v3, v29
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v30, v4, v30
	s_cbranch_scc1 .LBB0_61
.LBB0_62:                               ; %Flow567
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s18, 0
	s_branch .LBB0_64
.LBB0_63:                               ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $vgpr29_vgpr30
                                        ; implicit-def: $sgpr18
.LBB0_64:                               ; %Flow569
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_66
; %bb.65:                               ;   in Loop: Header=BB0_35 Depth=1
	global_load_b64 v[29:30], v1, s[0:1]
	s_add_i32 s18, s19, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_66:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_cmp_gt_u32 s18, 7
	s_cbranch_scc1 .LBB0_71
; %bb.67:                               ;   in Loop: Header=BB0_35 Depth=1
	v_mov_b32_e32 v31, 0
	v_mov_b32_e32 v32, 0
	s_cmp_eq_u32 s18, 0
	s_cbranch_scc1 .LBB0_70
; %bb.68:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], 0
.LBB0_69:                               ; %.preheader23.i
                                        ;   Parent Loop BB0_35 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s0, s16
	s_addc_u32 s21, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v0, v1, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s12, v[0:1]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s18, s16
	v_or_b32_e32 v31, v3, v31
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v32, v4, v32
	s_cbranch_scc1 .LBB0_69
.LBB0_70:                               ; %Flow562
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s19, 0
	s_branch .LBB0_72
.LBB0_71:                               ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $sgpr19
.LBB0_72:                               ; %Flow564
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_74
; %bb.73:                               ;   in Loop: Header=BB0_35 Depth=1
	global_load_b64 v[31:32], v1, s[0:1]
	s_add_i32 s19, s18, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_74:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_cmp_gt_u32 s19, 7
	s_cbranch_scc1 .LBB0_79
; %bb.75:                               ;   in Loop: Header=BB0_35 Depth=1
	v_mov_b32_e32 v33, 0
	v_mov_b32_e32 v34, 0
	s_cmp_eq_u32 s19, 0
	s_cbranch_scc1 .LBB0_78
; %bb.76:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], 0
.LBB0_77:                               ; %.preheader21.i
                                        ;   Parent Loop BB0_35 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s0, s16
	s_addc_u32 s21, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v0, v1, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s12, v[0:1]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s19, s16
	v_or_b32_e32 v33, v3, v33
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v34, v4, v34
	s_cbranch_scc1 .LBB0_77
.LBB0_78:                               ; %Flow557
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s18, 0
	s_branch .LBB0_80
.LBB0_79:                               ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $vgpr33_vgpr34
                                        ; implicit-def: $sgpr18
.LBB0_80:                               ; %Flow559
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_82
; %bb.81:                               ;   in Loop: Header=BB0_35 Depth=1
	global_load_b64 v[33:34], v1, s[0:1]
	s_add_i32 s18, s19, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_82:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_cmp_gt_u32 s18, 7
	s_cbranch_scc1 .LBB0_87
; %bb.83:                               ;   in Loop: Header=BB0_35 Depth=1
	v_mov_b32_e32 v35, 0
	v_mov_b32_e32 v36, 0
	s_cmp_eq_u32 s18, 0
	s_cbranch_scc1 .LBB0_86
; %bb.84:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], s[0:1]
.LBB0_85:                               ; %.preheader.i
                                        ;   Parent Loop BB0_35 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v0, v1, s[16:17]
	s_add_i32 s18, s18, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s12, v[0:1]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s18, 0
	v_or_b32_e32 v35, v3, v35
	v_or_b32_e32 v36, v4, v36
	s_cbranch_scc1 .LBB0_85
.LBB0_86:                               ; %Flow552
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s12, 0
	s_branch .LBB0_88
.LBB0_87:                               ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s12, -1
.LBB0_88:                               ; %Flow554
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_90
; %bb.89:                               ;   in Loop: Header=BB0_35 Depth=1
	global_load_b64 v[35:36], v1, s[0:1]
.LBB0_90:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB0_35 Depth=1
	v_dual_mov_b32 v0, v41 :: v_dual_mov_b32 v3, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v0
	v_mov_b32_e32 v4, 0
	v_cmp_eq_u32_e64 s0, s0, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_96
; %bb.91:                               ;   in Loop: Header=BB0_35 Depth=1
	global_load_b64 v[39:40], v1, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v1, s[2:3] offset:40
	global_load_b64 v[6:7], v1, s[2:3]
	s_mov_b32 s12, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v40
	v_and_b32_e32 v3, v3, v39
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v10, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v10, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v6, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v7, v4, vcc_lo
	global_load_b64 v[37:38], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v1, v[37:40], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[39:40]
	s_cbranch_execz .LBB0_95
; %bb.92:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s13, 0
.LBB0_93:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB0_35 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v1, s[2:3] offset:40
	global_load_b64 v[10:11], v1, s[2:3]
	v_dual_mov_b32 v40, v4 :: v_dual_mov_b32 v39, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v6, v39
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v6, 24, v[10:11]
	v_and_b32_e32 v10, v7, v40
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v10, 24, v[4:5]
	v_mov_b32_e32 v4, v6
	global_load_b64 v[37:38], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v1, v[37:40], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[39:40]
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_93
; %bb.94:                               ; %Flow547
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_95:                               ; %Flow549
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s12
.LBB0_96:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[6:7], v1, s[2:3] offset:40
	global_load_b128 v[37:40], v1, s[2:3]
	v_readfirstlane_b32 s12, v3
	v_readfirstlane_b32 s13, v4
	s_mov_b32 s20, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s16, v6
	v_readfirstlane_b32 s17, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[12:13], s[16:17]
	s_mul_i32 s1, s17, 24
	s_mul_hi_u32 s18, s16, 24
	s_mul_i32 s19, s16, 24
	s_and_saveexec_b32 s21, s0
	s_cbranch_execz .LBB0_98
; %bb.97:                               ;   in Loop: Header=BB0_35 Depth=1
	v_dual_mov_b32 v17, s20 :: v_dual_mov_b32 v18, v1
	s_add_i32 s20, s18, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v37, s19
	v_add_co_ci_u32_e32 v4, vcc_lo, s20, v38, vcc_lo
	global_store_b128 v[3:4], v[17:20], off offset:8
.LBB0_98:                               ;   in Loop: Header=BB0_35 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	v_cmp_gt_u64_e64 vcc_lo, s[8:9], 56
	v_or_b32_e32 v3, 0, v16
	v_or_b32_e32 v4, v15, v42
	s_lshl_b64 s[16:17], s[16:17], 12
	s_lshl_b32 s20, s10, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s20, s20, 28
	v_cndmask_b32_e32 v22, v3, v16, vcc_lo
	v_cndmask_b32_e32 v6, v4, v15, vcc_lo
	v_lshlrev_b64 v[3:4], 6, v[0:1]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v39, s16
	v_add_co_ci_u32_e32 v7, vcc_lo, s17, v40, vcc_lo
	s_and_b32 s20, s20, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v0, v3
	v_and_or_b32 v21, 0xffffff1f, v6, s20
	v_add_co_ci_u32_e32 v4, vcc_lo, v7, v4, vcc_lo
	s_clause 0x3
	global_store_b128 v[3:4], v[21:24], off
	global_store_b128 v[3:4], v[25:28], off offset:16
	global_store_b128 v[3:4], v[29:32], off offset:32
	global_store_b128 v[3:4], v[33:36], off offset:48
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB0_106
; %bb.99:                               ;   in Loop: Header=BB0_35 Depth=1
	s_clause 0x1
	global_load_b64 v[23:24], v1, s[2:3] offset:32 glc
	global_load_b64 v[6:7], v1, s[2:3] offset:40
	v_dual_mov_b32 v21, s12 :: v_dual_mov_b32 v22, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s20, v6
	v_readfirstlane_b32 s21, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[20:21], s[20:21], s[12:13]
	s_mul_i32 s17, s21, 24
	s_mul_hi_u32 s21, s20, 24
	s_mul_i32 s20, s20, 24
	s_add_i32 s21, s21, s17
	v_add_co_u32 v6, vcc_lo, v37, s20
	v_add_co_ci_u32_e32 v7, vcc_lo, s21, v38, vcc_lo
	s_mov_b32 s17, exec_lo
	global_store_b64 v[6:7], v[23:24], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[17:18], v1, v[21:24], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[17:18], v[23:24]
	s_cbranch_execz .LBB0_102
; %bb.100:                              ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s20, 0
.LBB0_101:                              ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB0_35 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v15, s12 :: v_dual_mov_b32 v16, s13
	s_sleep 1
	global_store_b64 v[6:7], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v1, v[15:18], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[17:18]
	v_dual_mov_b32 v18, v11 :: v_dual_mov_b32 v17, v10
	s_or_b32 s20, vcc_lo, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s20
	s_cbranch_execnz .LBB0_101
.LBB0_102:                              ; %Flow545
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	global_load_b64 v[6:7], v1, s[2:3] offset:16
	s_mov_b32 s20, exec_lo
	s_mov_b32 s17, exec_lo
	v_mbcnt_lo_u32_b32 v0, s20, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_104
; %bb.103:                              ;   in Loop: Header=BB0_35 Depth=1
	s_bcnt1_i32_b32 s20, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v0, s20
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[6:7], v[0:1], off offset:8
.LBB0_104:                              ;   in Loop: Header=BB0_35 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	s_waitcnt vmcnt(0)
	global_load_b64 v[10:11], v[6:7], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
	s_cbranch_vccnz .LBB0_106
; %bb.105:                              ;   in Loop: Header=BB0_35 Depth=1
	global_load_b32 v0, v[6:7], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s17, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[10:11], v[0:1], off
	s_and_b32 m0, s17, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_106:                              ; %Flow546
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_add_i32 s18, s18, s1
	v_add_co_u32 v0, vcc_lo, v37, s19
	v_add_co_ci_u32_e32 v7, vcc_lo, s18, v38, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
.LBB0_107:                              ;   Parent Loop BB0_35 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v0, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_109
; %bb.108:                              ;   in Loop: Header=BB0_107 Depth=2
	global_load_b32 v0, v[6:7], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v0, 1, v0
.LBB0_109:                              ;   in Loop: Header=BB0_107 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v0
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_111
; %bb.110:                              ;   in Loop: Header=BB0_107 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_112
.LBB0_111:                              ;   in Loop: Header=BB0_107 Depth=2
	s_mov_b32 s1, -1
.LBB0_112:                              ; %Flow540
                                        ;   in Loop: Header=BB0_107 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_107
; %bb.113:                              ;   in Loop: Header=BB0_35 Depth=1
	global_load_b128 v[15:18], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_117
; %bb.114:                              ;   in Loop: Header=BB0_35 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v1, s[2:3] offset:40
	global_load_b64 v[6:7], v1, s[2:3] offset:24 glc
	global_load_b64 v[10:11], v1, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v0, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v4, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v24, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v17, vcc_lo, v0, s12
	v_add_co_ci_u32_e32 v18, vcc_lo, s13, v21, vcc_lo
	v_mov_b32_e32 v23, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[17:18]
	v_dual_cndmask_b32 v22, v18, v21 :: v_dual_cndmask_b32 v21, v17, v0
	v_and_b32_e32 v0, v22, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v21, v3
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v0, v4, v0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v10, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, v11, v0, vcc_lo
	global_store_b64 v[3:4], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[23:24], v1, v[21:24], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[23:24], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_117
; %bb.115:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s0, 0
.LBB0_116:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB0_35 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[23:24], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v1, v[21:24], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[23:24]
	v_dual_mov_b32 v24, v7 :: v_dual_mov_b32 v23, v6
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_116
.LBB0_117:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s8, s8, s10
	s_subb_u32 s9, s9, s11
	s_add_u32 s4, s4, s10
	s_addc_u32 s5, s5, s11
	s_cmp_lg_u64 s[8:9], 0
	s_cbranch_scc1 .LBB0_35
; %bb.118:                              ; %Flow585
	s_mov_b32 s0, 0
	s_branch .LBB0_120
.LBB0_119:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr15_vgpr16
.LBB0_120:                              ; %Flow600
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_149
; %bb.121:
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v15, v41 :: v_dual_mov_b32 v0, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v15
	v_mov_b32_e32 v1, 0
	v_cmp_eq_u32_e64 s0, s0, v15
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_127
; %bb.122:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[18:19], v3, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v3, s[2:3] offset:40
	global_load_b64 v[6:7], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v0, v0, v18
	v_and_b32_e32 v1, v1, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v0, 24
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	global_load_b64 v[16:17], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[16:19], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[18:19]
	s_cbranch_execz .LBB0_126
; %bb.123:                              ; %.preheader3.i.i.i39.preheader
	s_mov_b32 s5, 0
.LBB0_124:                              ; %.preheader3.i.i.i39
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v3, s[2:3] offset:40
	global_load_b64 v[10:11], v3, s[2:3]
	v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v6, v18
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v4, 24, v[10:11]
	v_and_b32_e32 v4, v7, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v4, 24, v[1:2]
	v_mov_b32_e32 v1, v6
	global_load_b64 v[16:17], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[16:19], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[18:19]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_124
; %bb.125:                              ; %Flow597
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_126:                              ; %Flow599
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_127:                              ; %.loopexit4.i.i.i34
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v16, 0
	v_readfirstlane_b32 s4, v0
	v_readfirstlane_b32 s5, v1
	s_mov_b32 s12, exec_lo
	s_clause 0x1
	global_load_b64 v[3:4], v16, s[2:3] offset:40
	global_load_b128 v[17:20], v16, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v3
	v_readfirstlane_b32 s9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[4:5], s[8:9]
	s_mul_i32 s1, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB0_129
; %bb.128:
	v_dual_mov_b32 v21, s12 :: v_dual_mov_b32 v22, v16
	s_add_i32 s12, s10, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v17, s11
	v_add_co_ci_u32_e32 v1, vcc_lo, s12, v18, vcc_lo
	v_dual_mov_b32 v23, 2 :: v_dual_mov_b32 v24, 1
	global_store_b128 v[0:1], v[21:24], off offset:8
.LBB0_129:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[0:1], 6, v[15:16]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v19, s8
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v20, vcc_lo
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v3, v0
	s_mov_b32 s19, s16
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	v_and_or_b32 v13, 0xffffff1f, v13, 32
	v_add_co_ci_u32_e32 v1, vcc_lo, v4, v1, vcc_lo
	v_dual_mov_b32 v15, v16 :: v_dual_mov_b32 v22, s19
	v_dual_mov_b32 v21, s18 :: v_dual_mov_b32 v20, s17
	v_mov_b32_e32 v19, s16
	s_clause 0x3
	global_store_b128 v[0:1], v[13:16], off
	global_store_b128 v[0:1], v[19:22], off offset:16
	global_store_b128 v[0:1], v[19:22], off offset:32
	global_store_b128 v[0:1], v[19:22], off offset:48
	s_and_saveexec_b32 s8, s0
	s_cbranch_execz .LBB0_137
; %bb.130:
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v19, s4
	v_mov_b32_e32 v20, s5
	s_clause 0x1
	global_load_b64 v[21:22], v6, s[2:3] offset:32 glc
	global_load_b64 v[3:4], v6, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v3
	v_readfirstlane_b32 s13, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[4:5]
	s_mul_i32 s9, s13, 24
	s_mul_hi_u32 s13, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s13, s13, s9
	v_add_co_u32 v3, vcc_lo, v17, s12
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v18, vcc_lo
	s_mov_b32 s9, exec_lo
	global_store_b64 v[3:4], v[21:22], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v6, v[19:22], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[15:16], v[21:22]
	s_cbranch_execz .LBB0_133
; %bb.131:                              ; %.preheader1.i.i.i37.preheader
	s_mov_b32 s12, 0
.LBB0_132:                              ; %.preheader1.i.i.i37
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v13, s4 :: v_dual_mov_b32 v14, s5
	s_sleep 1
	global_store_b64 v[3:4], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v6, v[13:16], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[15:16]
	v_dual_mov_b32 v16, v11 :: v_dual_mov_b32 v15, v10
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_132
.LBB0_133:                              ; %Flow595
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v7, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v6, s12, 0
	global_load_b64 v[3:4], v7, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB0_135
; %bb.134:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[6:7], off offset:8
.LBB0_135:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[6:7], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	s_cbranch_vccnz .LBB0_137
; %bb.136:
	global_load_b32 v3, v[3:4], off offset:24
	v_mov_b32_e32 v4, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[6:7], v[3:4], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_137:                              ; %Flow596
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s1
	v_add_co_u32 v3, vcc_lo, v17, s11
	v_add_co_ci_u32_e32 v4, vcc_lo, s10, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_138:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_140
; %bb.139:                              ;   in Loop: Header=BB0_138 Depth=1
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_140:                              ;   in Loop: Header=BB0_138 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v6
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_142
; %bb.141:                              ;   in Loop: Header=BB0_138 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_143
.LBB0_142:                              ;   in Loop: Header=BB0_138 Depth=1
	s_mov_b32 s1, -1
.LBB0_143:                              ; %Flow590
                                        ;   in Loop: Header=BB0_138 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_138
; %bb.144:
	global_load_b128 v[15:18], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_148
; %bb.145:
	v_mov_b32_e32 v3, 0
	s_clause 0x2
	global_load_b64 v[0:1], v3, s[2:3] offset:40
	global_load_b64 v[6:7], v3, s[2:3] offset:24 glc
	global_load_b64 v[10:11], v3, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v4, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v1, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v20, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v13, vcc_lo, v4, s4
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v17, vcc_lo
	v_mov_b32_e32 v19, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	v_dual_cndmask_b32 v18, v14, v17 :: v_dual_cndmask_b32 v17, v13, v4
	v_and_b32_e32 v1, v18, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v17, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v11, v1, vcc_lo
	global_store_b64 v[0:1], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[19:20], v3, v[17:20], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[19:20], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_148
; %bb.146:                              ; %.preheader.i.i.i36.preheader
	s_mov_b32 s0, 0
.LBB0_147:                              ; %.preheader.i.i.i36
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[19:20], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v3, v[17:20], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[19:20]
	v_dual_mov_b32 v20, v7 :: v_dual_mov_b32 v19, v6
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_147
.LBB0_148:                              ; %__ockl_hostcall_preview.exit.i
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_149:                              ; %__ockl_printf_append_string_n.exit
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v17, v41 :: v_dual_mov_b32 v0, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v17
	v_mov_b32_e32 v1, 0
	v_cmp_eq_u32_e64 s0, s0, v17
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_155
; %bb.150:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[20:21], v3, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v3, s[2:3] offset:40
	global_load_b64 v[6:7], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v0, v0, v20
	v_and_b32_e32 v1, v1, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v0, 24
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	global_load_b64 v[18:19], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[18:21], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[20:21]
	s_cbranch_execz .LBB0_154
; %bb.151:                              ; %.preheader3.i.i.i46.preheader
	s_mov_b32 s5, 0
.LBB0_152:                              ; %.preheader3.i.i.i46
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v3, s[2:3] offset:40
	global_load_b64 v[10:11], v3, s[2:3]
	v_dual_mov_b32 v21, v1 :: v_dual_mov_b32 v20, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v6, v20
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v4, 24, v[10:11]
	v_and_b32_e32 v4, v7, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v4, 24, v[1:2]
	v_mov_b32_e32 v1, v6
	global_load_b64 v[18:19], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[18:21], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[20:21]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_152
; %bb.153:                              ; %Flow533
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_154:                              ; %Flow535
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_155:                              ; %.loopexit4.i.i.i40
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v18, 0
	v_readfirstlane_b32 s4, v0
	v_readfirstlane_b32 s5, v1
	s_mov_b32 s12, exec_lo
	s_clause 0x1
	global_load_b64 v[3:4], v18, s[2:3] offset:40
	global_load_b128 v[19:22], v18, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v3
	v_readfirstlane_b32 s9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[4:5], s[8:9]
	s_mul_i32 s1, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB0_157
; %bb.156:
	v_dual_mov_b32 v23, s12 :: v_dual_mov_b32 v24, v18
	s_add_i32 s12, s10, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v19, s11
	v_add_co_ci_u32_e32 v1, vcc_lo, s12, v20, vcc_lo
	v_dual_mov_b32 v25, 2 :: v_dual_mov_b32 v26, 1
	global_store_b128 v[0:1], v[23:26], off offset:8
.LBB0_157:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[0:1], 6, v[17:18]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v21, s8
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v22, vcc_lo
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v3, v0
	s_mov_b32 s19, s16
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	v_and_or_b32 v15, 0xffffff1f, v15, 32
	v_add_co_ci_u32_e32 v1, vcc_lo, v4, v1, vcc_lo
	v_dual_mov_b32 v17, s14 :: v_dual_mov_b32 v24, s19
	v_dual_mov_b32 v23, s18 :: v_dual_mov_b32 v22, s17
	v_mov_b32_e32 v21, s16
	s_clause 0x3
	global_store_b128 v[0:1], v[15:18], off
	global_store_b128 v[0:1], v[21:24], off offset:16
	global_store_b128 v[0:1], v[21:24], off offset:32
	global_store_b128 v[0:1], v[21:24], off offset:48
	s_and_saveexec_b32 s8, s0
	s_cbranch_execz .LBB0_165
; %bb.158:
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v15, s4
	v_mov_b32_e32 v16, s5
	s_clause 0x1
	global_load_b64 v[17:18], v6, s[2:3] offset:32 glc
	global_load_b64 v[3:4], v6, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v3
	v_readfirstlane_b32 s13, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[4:5]
	s_mul_i32 s9, s13, 24
	s_mul_hi_u32 s13, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s13, s13, s9
	v_add_co_u32 v3, vcc_lo, v19, s12
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v20, vcc_lo
	s_mov_b32 s9, exec_lo
	global_store_b64 v[3:4], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v6, v[15:18], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[15:16], v[17:18]
	s_cbranch_execz .LBB0_161
; %bb.159:                              ; %.preheader1.i.i.i44.preheader
	s_mov_b32 s12, 0
.LBB0_160:                              ; %.preheader1.i.i.i44
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v13, s4 :: v_dual_mov_b32 v14, s5
	s_sleep 1
	global_store_b64 v[3:4], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v6, v[13:16], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[15:16]
	v_dual_mov_b32 v16, v11 :: v_dual_mov_b32 v15, v10
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_160
.LBB0_161:                              ; %Flow531
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v7, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v6, s12, 0
	global_load_b64 v[3:4], v7, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB0_163
; %bb.162:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[6:7], off offset:8
.LBB0_163:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[6:7], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	s_cbranch_vccnz .LBB0_165
; %bb.164:
	global_load_b32 v3, v[3:4], off offset:24
	v_mov_b32_e32 v4, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[6:7], v[3:4], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_165:                              ; %Flow532
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s1
	v_add_co_u32 v3, vcc_lo, v19, s11
	v_add_co_ci_u32_e32 v4, vcc_lo, s10, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_166:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_168
; %bb.167:                              ;   in Loop: Header=BB0_166 Depth=1
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_168:                              ;   in Loop: Header=BB0_166 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v6
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_170
; %bb.169:                              ;   in Loop: Header=BB0_166 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_171
.LBB0_170:                              ;   in Loop: Header=BB0_166 Depth=1
	s_mov_b32 s1, -1
.LBB0_171:                              ; %Flow526
                                        ;   in Loop: Header=BB0_166 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_166
; %bb.172:
	global_load_b64 v[13:14], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_176
; %bb.173:
	v_mov_b32_e32 v3, 0
	s_clause 0x2
	global_load_b64 v[0:1], v3, s[2:3] offset:40
	global_load_b64 v[6:7], v3, s[2:3] offset:24 glc
	global_load_b64 v[10:11], v3, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v4, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v1, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v18, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v15, vcc_lo, v4, s4
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[15:16]
	v_dual_cndmask_b32 v16, v16, v17 :: v_dual_cndmask_b32 v15, v15, v4
	v_mov_b32_e32 v17, v6
	v_and_b32_e32 v1, v16, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v15, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v11, v1, vcc_lo
	global_store_b64 v[0:1], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[17:18], v3, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[17:18], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_176
; %bb.174:                              ; %.preheader.i.i.i43.preheader
	s_mov_b32 s0, 0
.LBB0_175:                              ; %.preheader.i.i.i43
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v3, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[17:18]
	v_dual_mov_b32 v18, v7 :: v_dual_mov_b32 v17, v6
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_175
.LBB0_176:                              ; %__ockl_printf_append_args.exit
	s_or_b32 exec_lo, exec_lo, s1
	v_dual_mov_b32 v15, v41 :: v_dual_mov_b32 v0, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v15
	v_mov_b32_e32 v1, 0
	v_cmp_eq_u32_e64 s0, s0, v15
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_182
; %bb.177:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[18:19], v3, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v3, s[2:3] offset:40
	global_load_b64 v[6:7], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v0, v0, v18
	v_and_b32_e32 v1, v1, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v0, 24
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	global_load_b64 v[16:17], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[16:19], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[18:19]
	s_cbranch_execz .LBB0_181
; %bb.178:                              ; %.preheader3.i.i.i53.preheader
	s_mov_b32 s5, 0
.LBB0_179:                              ; %.preheader3.i.i.i53
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v3, s[2:3] offset:40
	global_load_b64 v[10:11], v3, s[2:3]
	v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v6, v18
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v4, 24, v[10:11]
	v_and_b32_e32 v4, v7, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v4, 24, v[1:2]
	v_mov_b32_e32 v1, v6
	global_load_b64 v[16:17], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[16:19], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[18:19]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_179
; %bb.180:                              ; %Flow519
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_181:                              ; %Flow521
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_182:                              ; %.loopexit4.i.i.i47
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v16, 0
	v_readfirstlane_b32 s4, v0
	v_readfirstlane_b32 s5, v1
	s_mov_b32 s12, exec_lo
	s_clause 0x1
	global_load_b64 v[3:4], v16, s[2:3] offset:40
	global_load_b128 v[17:20], v16, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v3
	v_readfirstlane_b32 s9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[4:5], s[8:9]
	s_mul_i32 s1, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB0_184
; %bb.183:
	v_dual_mov_b32 v21, s12 :: v_dual_mov_b32 v22, v16
	s_add_i32 s12, s10, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v17, s11
	v_add_co_ci_u32_e32 v1, vcc_lo, s12, v18, vcc_lo
	v_dual_mov_b32 v23, 2 :: v_dual_mov_b32 v24, 1
	global_store_b128 v[0:1], v[21:24], off offset:8
.LBB0_184:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[0:1], 6, v[15:16]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v19, s8
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v20, vcc_lo
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v3, v0
	s_mov_b32 s19, s16
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	v_and_or_b32 v13, 0xffffff1f, v13, 32
	v_add_co_ci_u32_e32 v1, vcc_lo, v4, v1, vcc_lo
	v_dual_mov_b32 v15, s15 :: v_dual_mov_b32 v22, s19
	v_dual_mov_b32 v21, s18 :: v_dual_mov_b32 v20, s17
	v_mov_b32_e32 v19, s16
	s_clause 0x3
	global_store_b128 v[0:1], v[13:16], off
	global_store_b128 v[0:1], v[19:22], off offset:16
	global_store_b128 v[0:1], v[19:22], off offset:32
	global_store_b128 v[0:1], v[19:22], off offset:48
	s_and_saveexec_b32 s8, s0
	s_cbranch_execz .LBB0_192
; %bb.185:
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v19, s4
	v_mov_b32_e32 v20, s5
	s_clause 0x1
	global_load_b64 v[21:22], v6, s[2:3] offset:32 glc
	global_load_b64 v[3:4], v6, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v3
	v_readfirstlane_b32 s13, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[4:5]
	s_mul_i32 s9, s13, 24
	s_mul_hi_u32 s13, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s13, s13, s9
	v_add_co_u32 v3, vcc_lo, v17, s12
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v18, vcc_lo
	s_mov_b32 s9, exec_lo
	global_store_b64 v[3:4], v[21:22], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v6, v[19:22], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[15:16], v[21:22]
	s_cbranch_execz .LBB0_188
; %bb.186:                              ; %.preheader1.i.i.i51.preheader
	s_mov_b32 s12, 0
.LBB0_187:                              ; %.preheader1.i.i.i51
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v13, s4 :: v_dual_mov_b32 v14, s5
	s_sleep 1
	global_store_b64 v[3:4], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v6, v[13:16], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[15:16]
	v_dual_mov_b32 v16, v11 :: v_dual_mov_b32 v15, v10
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_187
.LBB0_188:                              ; %Flow517
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v7, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v6, s12, 0
	global_load_b64 v[3:4], v7, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB0_190
; %bb.189:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[6:7], off offset:8
.LBB0_190:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[6:7], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	s_cbranch_vccnz .LBB0_192
; %bb.191:
	global_load_b32 v3, v[3:4], off offset:24
	v_mov_b32_e32 v4, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[6:7], v[3:4], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_192:                              ; %Flow518
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s1
	v_add_co_u32 v3, vcc_lo, v17, s11
	v_add_co_ci_u32_e32 v4, vcc_lo, s10, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_193:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_195
; %bb.194:                              ;   in Loop: Header=BB0_193 Depth=1
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_195:                              ;   in Loop: Header=BB0_193 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v6
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_197
; %bb.196:                              ;   in Loop: Header=BB0_193 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_198
.LBB0_197:                              ;   in Loop: Header=BB0_193 Depth=1
	s_mov_b32 s1, -1
.LBB0_198:                              ; %Flow512
                                        ;   in Loop: Header=BB0_193 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_193
; %bb.199:
	global_load_b64 v[10:11], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_203
; %bb.200:
	v_mov_b32_e32 v3, 0
	s_clause 0x2
	global_load_b64 v[0:1], v3, s[2:3] offset:40
	global_load_b64 v[6:7], v3, s[2:3] offset:24 glc
	global_load_b64 v[15:16], v3, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v4, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v4, s4
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	v_dual_cndmask_b32 v14, v14, v17 :: v_dual_cndmask_b32 v13, v13, v4
	v_and_b32_e32 v1, v14, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v13, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v15, v0
	v_mov_b32_e32 v15, v6
	v_add_co_ci_u32_e32 v1, vcc_lo, v16, v1, vcc_lo
	v_mov_b32_e32 v16, v7
	global_store_b64 v[0:1], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v3, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[15:16], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_203
; %bb.201:                              ; %.preheader.i.i.i50.preheader
	s_mov_b32 s0, 0
.LBB0_202:                              ; %.preheader.i.i.i50
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v3, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[15:16]
	v_dual_mov_b32 v16, v7 :: v_dual_mov_b32 v15, v6
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_202
.LBB0_203:                              ; %__ockl_printf_append_args.exit54
	s_or_b32 exec_lo, exec_lo, s1
	v_dual_mov_b32 v3, v41 :: v_dual_mov_b32 v0, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v3
	v_mov_b32_e32 v1, 0
	v_cmp_eq_u32_e64 s0, s0, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_209
; %bb.204:
	v_mov_b32_e32 v4, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[15:16], v4, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v4, s[2:3] offset:40
	global_load_b64 v[6:7], v4, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v16
	v_and_b32_e32 v0, v0, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v13, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v13, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	global_load_b64 v[13:14], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v4, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[15:16]
	s_cbranch_execz .LBB0_208
; %bb.205:                              ; %.preheader3.i.i.i61.preheader
	s_mov_b32 s5, 0
.LBB0_206:                              ; %.preheader3.i.i.i61
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v4, s[2:3] offset:40
	global_load_b64 v[13:14], v4, s[2:3]
	v_dual_mov_b32 v16, v1 :: v_dual_mov_b32 v15, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v6, v15
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v6, 24, v[13:14]
	v_and_b32_e32 v13, v7, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v13, 24, v[1:2]
	v_mov_b32_e32 v1, v6
	global_load_b64 v[13:14], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v4, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[15:16]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_206
; %bb.207:                              ; %Flow505
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_208:                              ; %Flow507
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_209:                              ; %.loopexit4.i.i.i55
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v4, 0
	v_readfirstlane_b32 s4, v0
	v_readfirstlane_b32 s5, v1
	s_mov_b32 s12, exec_lo
	s_clause 0x1
	global_load_b64 v[6:7], v4, s[2:3] offset:40
	global_load_b128 v[14:17], v4, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v6
	v_readfirstlane_b32 s9, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[4:5], s[8:9]
	s_mul_i32 s1, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB0_211
; %bb.210:
	v_dual_mov_b32 v18, s12 :: v_dual_mov_b32 v19, v4
	s_add_i32 s12, s10, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v14, s11
	v_add_co_ci_u32_e32 v1, vcc_lo, s12, v15, vcc_lo
	v_dual_mov_b32 v20, 2 :: v_dual_mov_b32 v21, 1
	global_store_b128 v[0:1], v[18:21], off offset:8
.LBB0_211:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[0:1], 6, v[3:4]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v16, s8
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v17, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v3, v0
	s_mov_b32 s15, s12
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	v_and_or_b32 v10, 0xffffff1f, v10, 32
	v_add_co_ci_u32_e32 v1, vcc_lo, v6, v1, vcc_lo
	v_mov_b32_e32 v13, v4
	v_dual_mov_b32 v19, s15 :: v_dual_mov_b32 v16, s12
	v_dual_mov_b32 v18, s14 :: v_dual_mov_b32 v17, s13
	s_clause 0x3
	global_store_b128 v[0:1], v[10:13], off
	global_store_b128 v[0:1], v[16:19], off offset:16
	global_store_b128 v[0:1], v[16:19], off offset:32
	global_store_b128 v[0:1], v[16:19], off offset:48
	s_and_saveexec_b32 s8, s0
	s_cbranch_execz .LBB0_219
; %bb.212:
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v17, s5
	v_mov_b32_e32 v16, s4
	s_clause 0x1
	global_load_b64 v[18:19], v6, s[2:3] offset:32 glc
	global_load_b64 v[3:4], v6, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v3
	v_readfirstlane_b32 s13, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[4:5]
	s_mul_i32 s9, s13, 24
	s_mul_hi_u32 s13, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s13, s13, s9
	v_add_co_u32 v3, vcc_lo, v14, s12
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v15, vcc_lo
	s_mov_b32 s9, exec_lo
	global_store_b64 v[3:4], v[18:19], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v6, v[16:19], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[12:13], v[18:19]
	s_cbranch_execz .LBB0_215
; %bb.213:                              ; %.preheader1.i.i.i59.preheader
	s_mov_b32 s12, 0
.LBB0_214:                              ; %.preheader1.i.i.i59
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v10, s4 :: v_dual_mov_b32 v11, s5
	s_sleep 1
	global_store_b64 v[3:4], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v6, v[10:13], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[12:13]
	v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_214
.LBB0_215:                              ; %Flow503
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v7, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v6, s12, 0
	global_load_b64 v[3:4], v7, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB0_217
; %bb.216:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[6:7], off offset:8
.LBB0_217:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[6:7], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	s_cbranch_vccnz .LBB0_219
; %bb.218:
	global_load_b32 v3, v[3:4], off offset:24
	v_mov_b32_e32 v4, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[6:7], v[3:4], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_219:                              ; %Flow504
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s1
	v_add_co_u32 v3, vcc_lo, v14, s11
	v_add_co_ci_u32_e32 v4, vcc_lo, s10, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_220:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_222
; %bb.221:                              ;   in Loop: Header=BB0_220 Depth=1
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_222:                              ;   in Loop: Header=BB0_220 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v6
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_224
; %bb.223:                              ;   in Loop: Header=BB0_220 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_225
.LBB0_224:                              ;   in Loop: Header=BB0_220 Depth=1
	s_mov_b32 s1, -1
.LBB0_225:                              ; %Flow498
                                        ;   in Loop: Header=BB0_220 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_220
; %bb.226:
	global_load_b64 v[6:7], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_230
; %bb.227:
	v_mov_b32_e32 v3, 0
	s_clause 0x2
	global_load_b64 v[0:1], v3, s[2:3] offset:40
	global_load_b64 v[14:15], v3, s[2:3] offset:24 glc
	global_load_b64 v[12:13], v3, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v4, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v4, s4
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
	v_cndmask_b32_e32 v10, v10, v4, vcc_lo
	v_cndmask_b32_e32 v11, v11, v16, vcc_lo
	v_and_b32_e32 v0, v10, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v12, v0
	v_dual_mov_b32 v12, v14 :: v_dual_and_b32 v1, v11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, v13, v1, vcc_lo
	v_mov_b32_e32 v13, v15
	global_store_b64 v[0:1], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v3, v[10:13], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[12:13], v[14:15]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_230
; %bb.228:                              ; %.preheader.i.i.i58.preheader
	s_mov_b32 s0, 0
.LBB0_229:                              ; %.preheader.i.i.i58
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v3, v[10:13], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[14:15], v[12:13]
	v_dual_mov_b32 v12, v14 :: v_dual_mov_b32 v13, v15
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_229
.LBB0_230:                              ; %__ockl_printf_append_args.exit62
	s_or_b32 exec_lo, exec_lo, s1
	v_dual_mov_b32 v0, v41 :: v_dual_mov_b32 v3, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v0
	v_mov_b32_e32 v4, 0
	v_cmp_eq_u32_e64 s0, s0, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_236
; %bb.231:
	v_mov_b32_e32 v1, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[12:13], v1, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v1, s[2:3] offset:40
	global_load_b64 v[10:11], v1, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v13
	v_and_b32_e32 v3, v3, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v14, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v14, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v10, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v11, v4, vcc_lo
	global_load_b64 v[10:11], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v1, v[10:13], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[12:13]
	s_cbranch_execz .LBB0_235
; %bb.232:                              ; %.preheader3.i.i.i69.preheader
	s_mov_b32 s5, 0
.LBB0_233:                              ; %.preheader3.i.i.i69
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[10:11], v1, s[2:3] offset:40
	global_load_b64 v[14:15], v1, s[2:3]
	v_dual_mov_b32 v13, v4 :: v_dual_mov_b32 v12, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v10, v10, v12
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v10, 24, v[14:15]
	v_and_b32_e32 v14, v11, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, v14, 24, v[4:5]
	v_mov_b32_e32 v4, v10
	global_load_b64 v[10:11], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v1, v[10:13], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[12:13]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_233
; %bb.234:                              ; %Flow491
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_235:                              ; %Flow493
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_236:                              ; %.loopexit4.i.i.i63
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v1, 0
	v_readfirstlane_b32 s4, v3
	v_readfirstlane_b32 s5, v4
	s_mov_b32 s12, exec_lo
	s_clause 0x1
	global_load_b64 v[14:15], v1, s[2:3] offset:40
	global_load_b128 v[10:13], v1, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v14
	v_readfirstlane_b32 s9, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[4:5], s[8:9]
	s_mul_i32 s1, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB0_238
; %bb.237:
	v_dual_mov_b32 v14, s12 :: v_dual_mov_b32 v15, v1
	s_add_i32 s12, s10, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v10, s11
	v_add_co_ci_u32_e32 v4, vcc_lo, s12, v11, vcc_lo
	v_dual_mov_b32 v16, 2 :: v_dual_mov_b32 v17, 1
	global_store_b128 v[3:4], v[14:17], off offset:8
.LBB0_238:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[0:1], 6, v[0:1]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v12, s8
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v13, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v3, v0
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v6, 0xffffff1f, v6, 32
	v_add_co_ci_u32_e32 v1, vcc_lo, v4, v1, vcc_lo
	v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13
	v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15
	s_clause 0x3
	global_store_b128 v[0:1], v[6:9], off
	global_store_b128 v[0:1], v[12:15], off offset:16
	global_store_b128 v[0:1], v[12:15], off offset:32
	global_store_b128 v[0:1], v[12:15], off offset:48
	s_and_saveexec_b32 s8, s0
	s_cbranch_execz .LBB0_246
; %bb.239:
	v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v13, s4
	v_mov_b32_e32 v14, s5
	s_clause 0x1
	global_load_b64 v[15:16], v12, s[2:3] offset:32 glc
	global_load_b64 v[3:4], v12, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v3
	v_readfirstlane_b32 s13, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[4:5]
	s_mul_i32 s9, s13, 24
	s_mul_hi_u32 s13, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s13, s13, s9
	v_add_co_u32 v3, vcc_lo, v10, s12
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v11, vcc_lo
	s_mov_b32 s9, exec_lo
	global_store_b64 v[3:4], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v12, v[13:16], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[8:9], v[15:16]
	s_cbranch_execz .LBB0_242
; %bb.240:                              ; %.preheader1.i.i.i67.preheader
	s_mov_b32 s12, 0
.LBB0_241:                              ; %.preheader1.i.i.i67
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
	s_sleep 1
	global_store_b64 v[3:4], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v12, v[6:9], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
	v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_241
.LBB0_242:                              ; %Flow489
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v7, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v6, s12, 0
	global_load_b64 v[3:4], v7, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB0_244
; %bb.243:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[6:7], off offset:8
.LBB0_244:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[6:7], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	s_cbranch_vccnz .LBB0_246
; %bb.245:
	global_load_b32 v3, v[3:4], off offset:24
	v_mov_b32_e32 v4, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[6:7], v[3:4], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_246:                              ; %Flow490
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s1
	v_add_co_u32 v3, vcc_lo, v10, s11
	v_add_co_ci_u32_e32 v4, vcc_lo, s10, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_247:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_249
; %bb.248:                              ;   in Loop: Header=BB0_247 Depth=1
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_249:                              ;   in Loop: Header=BB0_247 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v6
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_251
; %bb.250:                              ;   in Loop: Header=BB0_247 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_252
.LBB0_251:                              ;   in Loop: Header=BB0_247 Depth=1
	s_mov_b32 s1, -1
.LBB0_252:                              ; %Flow484
                                        ;   in Loop: Header=BB0_247 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_247
; %bb.253:
	global_load_b64 v[3:4], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_257
; %bb.254:
	v_mov_b32_e32 v10, 0
	s_clause 0x2
	global_load_b64 v[0:1], v10, s[2:3] offset:40
	global_load_b64 v[11:12], v10, s[2:3] offset:24 glc
	global_load_b64 v[8:9], v10, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v13, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v13, s4
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	v_dual_cndmask_b32 v7, v7, v14 :: v_dual_cndmask_b32 v6, v6, v13
	v_and_b32_e32 v1, v7, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v6, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v13, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v13, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v8, v0
	v_mov_b32_e32 v8, v11
	v_add_co_ci_u32_e32 v1, vcc_lo, v9, v1, vcc_lo
	v_mov_b32_e32 v9, v12
	global_store_b64 v[0:1], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v10, v[6:9], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[8:9], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_257
; %bb.255:                              ; %.preheader.i.i.i66.preheader
	s_mov_b32 s0, 0
.LBB0_256:                              ; %.preheader.i.i.i66
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v10, v[6:9], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[8:9]
	v_dual_mov_b32 v8, v11 :: v_dual_mov_b32 v9, v12
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_256
.LBB0_257:                              ; %__ockl_printf_append_args.exit70
	s_or_b32 exec_lo, exec_lo, s1
	v_dual_mov_b32 v11, v41 :: v_dual_mov_b32 v0, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v11
	v_mov_b32_e32 v1, 0
	v_cmp_eq_u32_e64 s0, s0, v11
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_263
; %bb.258:
	v_mov_b32_e32 v6, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[9:10], v6, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v10
	v_and_b32_e32 v0, v0, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v12, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v12, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v7, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v8, v1, vcc_lo
	global_load_b64 v[7:8], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[7:10], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[9:10]
	s_cbranch_execz .LBB0_262
; %bb.259:                              ; %.preheader3.i.i.i77.preheader
	s_mov_b32 s5, 0
.LBB0_260:                              ; %.preheader3.i.i.i77
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b64 v[12:13], v6, s[2:3]
	v_dual_mov_b32 v10, v1 :: v_dual_mov_b32 v9, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v9
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v7, 24, v[12:13]
	v_and_b32_e32 v12, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v12, 24, v[1:2]
	v_mov_b32_e32 v1, v7
	global_load_b64 v[7:8], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[7:10], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[9:10]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_260
; %bb.261:                              ; %Flow477
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_262:                              ; %Flow479
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_263:                              ; %.loopexit4.i.i.i71
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v12, 0
	v_readfirstlane_b32 s4, v0
	v_readfirstlane_b32 s5, v1
	s_mov_b32 s12, exec_lo
	s_clause 0x1
	global_load_b64 v[13:14], v12, s[2:3] offset:40
	global_load_b128 v[7:10], v12, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v13
	v_readfirstlane_b32 s9, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[4:5], s[8:9]
	s_mul_i32 s1, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB0_265
; %bb.264:
	v_dual_mov_b32 v13, s12 :: v_dual_mov_b32 v14, v12
	s_add_i32 s12, s10, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v7, s11
	v_add_co_ci_u32_e32 v1, vcc_lo, s12, v8, vcc_lo
	v_dual_mov_b32 v15, 2 :: v_dual_mov_b32 v16, 1
	global_store_b128 v[0:1], v[13:16], off offset:8
.LBB0_265:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[0:1], 6, v[11:12]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v9, s8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v10, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v6, v0
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v3, 0xffffff1f, v3, 32
	v_add_co_ci_u32_e32 v1, vcc_lo, v9, v1, vcc_lo
	v_dual_mov_b32 v6, v12 :: v_dual_mov_b32 v9, s12
	v_dual_mov_b32 v10, s13 :: v_dual_mov_b32 v11, s14
	v_mov_b32_e32 v12, s15
	s_clause 0x3
	global_store_b128 v[0:1], v[3:6], off
	global_store_b128 v[0:1], v[9:12], off offset:16
	global_store_b128 v[0:1], v[9:12], off offset:32
	global_store_b128 v[0:1], v[9:12], off offset:48
	s_and_saveexec_b32 s8, s0
	s_cbranch_execz .LBB0_273
; %bb.266:
	v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v12, s4
	v_mov_b32_e32 v13, s5
	s_clause 0x1
	global_load_b64 v[14:15], v11, s[2:3] offset:32 glc
	global_load_b64 v[3:4], v11, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v3
	v_readfirstlane_b32 s13, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[4:5]
	s_mul_i32 s9, s13, 24
	s_mul_hi_u32 s13, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s13, s13, s9
	v_add_co_u32 v9, vcc_lo, v7, s12
	v_add_co_ci_u32_e32 v10, vcc_lo, s13, v8, vcc_lo
	s_mov_b32 s9, exec_lo
	global_store_b64 v[9:10], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v11, v[12:15], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[5:6], v[14:15]
	s_cbranch_execz .LBB0_269
; %bb.267:                              ; %.preheader1.i.i.i75.preheader
	s_mov_b32 s12, 0
.LBB0_268:                              ; %.preheader1.i.i.i75
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5
	s_sleep 1
	global_store_b64 v[9:10], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v11, v[3:6], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_268
.LBB0_269:                              ; %Flow475
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v6, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v5, s12, 0
	global_load_b64 v[3:4], v6, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_271
; %bb.270:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[5:6], off offset:8
.LBB0_271:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[5:6], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
	s_cbranch_vccnz .LBB0_273
; %bb.272:
	global_load_b32 v3, v[3:4], off offset:24
	v_mov_b32_e32 v4, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v3
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[5:6], v[3:4], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_273:                              ; %Flow476
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s1
	v_add_co_u32 v3, vcc_lo, v7, s11
	v_add_co_ci_u32_e32 v4, vcc_lo, s10, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_274:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v5, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_276
; %bb.275:                              ;   in Loop: Header=BB0_274 Depth=1
	global_load_b32 v5, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v5, 1, v5
.LBB0_276:                              ;   in Loop: Header=BB0_274 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v5
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_278
; %bb.277:                              ;   in Loop: Header=BB0_274 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_279
.LBB0_278:                              ;   in Loop: Header=BB0_274 Depth=1
	s_mov_b32 s1, -1
.LBB0_279:                              ; %Flow470
                                        ;   in Loop: Header=BB0_274 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_274
; %bb.280:
	global_load_b64 v[0:1], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_284
; %bb.281:
	v_mov_b32_e32 v9, 0
	s_clause 0x2
	global_load_b64 v[5:6], v9, s[2:3] offset:40
	global_load_b64 v[10:11], v9, s[2:3] offset:24 glc
	global_load_b64 v[7:8], v9, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v12, vcc_lo, v5, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v12, s4
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
	v_dual_cndmask_b32 v4, v4, v13 :: v_dual_cndmask_b32 v3, v3, v12
	v_and_b32_e32 v6, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v5, v3, v5
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v12, v5, 24
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v6, v12, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v7, v5
	v_mov_b32_e32 v5, v10
	v_add_co_ci_u32_e32 v8, vcc_lo, v8, v6, vcc_lo
	v_mov_b32_e32 v6, v11
	global_store_b64 v[7:8], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v9, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[5:6], v[10:11]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_284
; %bb.282:                              ; %.preheader.i.i.i74.preheader
	s_mov_b32 s0, 0
.LBB0_283:                              ; %.preheader.i.i.i74
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[7:8], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v9, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[5:6]
	v_dual_mov_b32 v5, v10 :: v_dual_mov_b32 v6, v11
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_283
.LBB0_284:                              ; %__ockl_printf_append_args.exit78
	s_or_b32 exec_lo, exec_lo, s1
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v41
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v41
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_290
; %bb.285:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[6:7], v3, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[8:9], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v5, v5, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v10, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[6:7]
	s_cbranch_execz .LBB0_289
; %bb.286:                              ; %.preheader3.i.i.i85.preheader
	s_mov_b32 s5, 0
.LBB0_287:                              ; %.preheader3.i.i.i85
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[10:11], v3, s[2:3]
	v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v4, 24, v[10:11]
	v_mov_b32_e32 v4, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v5, 24, v[4:5]
	global_load_b64 v[4:5], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[6:7]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_287
; %bb.288:                              ; %Flow463
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_289:                              ; %Flow465
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_290:                              ; %.loopexit4.i.i.i79
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v42, 0
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_mov_b32 s12, exec_lo
	s_clause 0x1
	global_load_b64 v[10:11], v42, s[2:3] offset:40
	global_load_b128 v[4:7], v42, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v10
	v_readfirstlane_b32 s9, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[4:5], s[8:9]
	s_mul_i32 s1, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB0_292
; %bb.291:
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, v42
	s_add_i32 s12, s10, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v12, vcc_lo, v4, s11
	v_add_co_ci_u32_e32 v13, vcc_lo, s12, v5, vcc_lo
	v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1
	global_store_b128 v[12:13], v[8:11], off offset:8
.LBB0_292:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[8:9], 6, v[41:42]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v6, s8
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v7, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v3, v8
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v0, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v11, vcc_lo, v6, v9, vcc_lo
	v_dual_mov_b32 v3, v42 :: v_dual_mov_b32 v6, s12
	v_dual_mov_b32 v7, s13 :: v_dual_mov_b32 v8, s14
	v_mov_b32_e32 v9, s15
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s8, s0
	s_cbranch_execz .LBB0_300
; %bb.293:
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v8, s4
	v_mov_b32_e32 v9, s5
	s_clause 0x1
	global_load_b64 v[10:11], v3, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v3, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v0
	v_readfirstlane_b32 s13, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[4:5]
	s_mul_i32 s9, s13, 24
	s_mul_hi_u32 s13, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s13, s13, s9
	v_add_co_u32 v0, vcc_lo, v4, s12
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v5, vcc_lo
	s_mov_b32 s9, exec_lo
	global_store_b64 v[0:1], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v3, v[8:11], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[8:9], v[10:11]
	s_cbranch_execz .LBB0_296
; %bb.294:                              ; %.preheader1.i.i.i83.preheader
	s_mov_b32 s12, 0
.LBB0_295:                              ; %.preheader1.i.i.i83
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
	s_sleep 1
	global_store_b64 v[0:1], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v3, v[6:9], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
	v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_295
.LBB0_296:                              ; %Flow461
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v7, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v3, s12, 0
	global_load_b64 v[0:1], v7, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB0_298
; %bb.297:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[6:7], off offset:8
.LBB0_298:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[6:7], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	s_cbranch_vccnz .LBB0_300
; %bb.299:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[6:7], v[0:1], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_300:                              ; %Flow462
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s1
	v_add_co_u32 v0, vcc_lo, v4, s11
	v_add_co_ci_u32_e32 v1, vcc_lo, s10, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_301:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v3, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_303
; %bb.302:                              ;   in Loop: Header=BB0_301 Depth=1
	global_load_b32 v3, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v3, 1, v3
.LBB0_303:                              ;   in Loop: Header=BB0_301 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v3
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_305
; %bb.304:                              ;   in Loop: Header=BB0_301 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_306
.LBB0_305:                              ;   in Loop: Header=BB0_301 Depth=1
	s_mov_b32 s1, -1
.LBB0_306:                              ; %Flow456
                                        ;   in Loop: Header=BB0_301 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_301
; %bb.307:
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_311
; %bb.308:
	v_mov_b32_e32 v7, 0
	s_clause 0x2
	global_load_b64 v[0:1], v7, s[2:3] offset:40
	global_load_b64 v[8:9], v7, s[2:3] offset:24 glc
	global_load_b64 v[5:6], v7, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v10, s4
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
	v_dual_cndmask_b32 v4, v4, v11 :: v_dual_cndmask_b32 v3, v3, v10
	v_and_b32_e32 v1, v4, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v3, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v10, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v5, v0
	v_mov_b32_e32 v5, v8
	v_add_co_ci_u32_e32 v1, vcc_lo, v6, v1, vcc_lo
	v_mov_b32_e32 v6, v9
	global_store_b64 v[0:1], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v7, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[5:6], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_311
; %bb.309:                              ; %.preheader.i.i.i82.preheader
	s_mov_b32 s0, 0
.LBB0_310:                              ; %.preheader.i.i.i82
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v7, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[5:6]
	v_dual_mov_b32 v5, v8 :: v_dual_mov_b32 v6, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_310
.LBB0_311:                              ; %__ockl_printf_append_args.exit86
	s_or_b32 exec_lo, exec_lo, s1
	v_and_b32_e32 v3, 0xff, v45
	v_lshlrev_b16 v4, 8, v44
	v_add_co_u32 v0, s0, s6, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v1, null, s7, 0, s0
	v_or_b32_e32 v2, v3, v4
	s_clause 0x1
	global_store_b8 v[0:1], v43, off offset:2
	global_store_b16 v[0:1], v2, off
.LBB0_312:                              ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6GenSeqPjPhjS_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 46
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6GenSeqPjPhjS_j, .Lfunc_end0-_Z6GenSeqPjPhjS_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 14148
; NumSgprs: 24
; NumVgprs: 46
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 46
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"ThrPerBlk: %u, Mybid: %u, Mytid: %d, Mygtid: %u, offset: %u, currIndex: %u\n"
	.size	.str, 76

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         120
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6GenSeqPjPhjS_j
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z6GenSeqPjPhjS_j.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     46
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
