#include "includes.h"
__global__ void PD_INPLACE_GPU_KERNEL(float *d_input, float *d_temp, unsigned char *d_output_taps, float *d_MSD, int maxTaps, int nTimesamples)
{
extern __shared__ float s_input[]; //dynamically allocated memory for now

int f, i, gpos_y, gpos_x, spos, itemp;
float res_SNR[PD_NWINDOWS], SNR, temp_FIR_value, FIR_value, ftemp;
int res_Taps[PD_NWINDOWS];
float signal_mean, signal_sd, modifier;
signal_mean = d_MSD[0];
signal_sd = d_MSD[2];
modifier = d_MSD[1];

//----------------------------------------------
//----> Reading data
gpos_y = blockIdx.y * nTimesamples;
gpos_x = blockIdx.x * PD_NTHREADS * PD_NWINDOWS + threadIdx.x;
spos = threadIdx.x;
for (f = 0; f < PD_NWINDOWS; f++)
{
if (gpos_x < nTimesamples)
{
s_input[spos] = d_input[gpos_y + gpos_x];
}
spos = spos + blockDim.x;
gpos_x = gpos_x + blockDim.x;
}

//----> Loading shared data
itemp = PD_NTHREADS * PD_NWINDOWS + maxTaps - 1;
gpos_y = blockIdx.y * ( maxTaps - 1 ) * gridDim.x;
gpos_x = blockIdx.x * ( maxTaps - 1 ) + threadIdx.x;
while (spos < itemp)
{ // && gpos_x<((maxTaps-1)*gridDim.x)
s_input[spos] = d_temp[gpos_y + gpos_x];
spos = spos + blockDim.x;
gpos_x = gpos_x + blockDim.x;
}

__syncthreads();

//----> SNR for nTaps=1
spos = PD_NWINDOWS * threadIdx.x;
for (i = 0; i < PD_NWINDOWS; i++)
{
res_SNR[i] = ( s_input[spos + i] - signal_mean ) / signal_sd;
res_Taps[i] = 1;
}

//----------------------------------------------
//----> FIR calculation loop
FIR_value = s_input[spos];
for (f = 1; f < maxTaps; f++)
{
//nTaps=f+1;!
ftemp = signal_sd + f * modifier;
spos = PD_NWINDOWS * threadIdx.x;

// 0th element from NWINDOW
i = 0;
FIR_value += s_input[spos + f];

SNR = ( FIR_value - ( f + 1 ) * signal_mean ) / ( ftemp );
if (SNR > res_SNR[i])
{
res_SNR[i] = SNR;
res_Taps[i] = f + 1;
}

temp_FIR_value = FIR_value;
for (i = 1; i < PD_NWINDOWS; i++)
{
temp_FIR_value = temp_FIR_value - s_input[spos + i - 1] + s_input[spos + f + i];

SNR = ( temp_FIR_value - ( f + 1 ) * signal_mean ) / ( ftemp );
if (SNR > res_SNR[i])
{
res_SNR[i] = SNR;
res_Taps[i] = f + 1;
}
}
}

//----------------------------------------------
//---- Writing data
gpos_y = blockIdx.y * nTimesamples;
gpos_x = blockIdx.x * PD_NTHREADS * PD_NWINDOWS + PD_NWINDOWS * threadIdx.x;
for (i = 0; i < PD_NWINDOWS; i++)
{
if (( gpos_x + i ) < ( nTimesamples ))
{
d_input[gpos_y + gpos_x + i] = res_SNR[i];
d_output_taps[gpos_y + gpos_x + i] = res_Taps[i];
}
}
}
	.file	"tmpxft_00387935_00000000-6_PD_INPLACE_GPU_KERNEL.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z49__device_stub__Z21PD_INPLACE_GPU_KERNELPfS_PhS_iiPfS_PhS_ii
	.type	_Z49__device_stub__Z21PD_INPLACE_GPU_KERNELPfS_PhS_iiPfS_PhS_ii, @function
_Z49__device_stub__Z21PD_INPLACE_GPU_KERNELPfS_PhS_iiPfS_PhS_ii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z49__device_stub__Z21PD_INPLACE_GPU_KERNELPfS_PhS_iiPfS_PhS_ii, .-_Z49__device_stub__Z21PD_INPLACE_GPU_KERNELPfS_PhS_iiPfS_PhS_ii
	.globl	_Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii
	.type	_Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii, @function
_Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z21PD_INPLACE_GPU_KERNELPfS_PhS_iiPfS_PhS_ii
	.cfi_endproc
.LFE2033:
	.size	_Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii, .-_Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void PD_INPLACE_GPU_KERNEL(float *d_input, float *d_temp, unsigned char *d_output_taps, float *d_MSD, int maxTaps, int nTimesamples)
{
extern __shared__ float s_input[]; //dynamically allocated memory for now

int f, i, gpos_y, gpos_x, spos, itemp;
float res_SNR[PD_NWINDOWS], SNR, temp_FIR_value, FIR_value, ftemp;
int res_Taps[PD_NWINDOWS];
float signal_mean, signal_sd, modifier;
signal_mean = d_MSD[0];
signal_sd = d_MSD[2];
modifier = d_MSD[1];

//----------------------------------------------
//----> Reading data
gpos_y = blockIdx.y * nTimesamples;
gpos_x = blockIdx.x * PD_NTHREADS * PD_NWINDOWS + threadIdx.x;
spos = threadIdx.x;
for (f = 0; f < PD_NWINDOWS; f++)
{
if (gpos_x < nTimesamples)
{
s_input[spos] = d_input[gpos_y + gpos_x];
}
spos = spos + blockDim.x;
gpos_x = gpos_x + blockDim.x;
}

//----> Loading shared data
itemp = PD_NTHREADS * PD_NWINDOWS + maxTaps - 1;
gpos_y = blockIdx.y * ( maxTaps - 1 ) * gridDim.x;
gpos_x = blockIdx.x * ( maxTaps - 1 ) + threadIdx.x;
while (spos < itemp)
{ // && gpos_x<((maxTaps-1)*gridDim.x)
s_input[spos] = d_temp[gpos_y + gpos_x];
spos = spos + blockDim.x;
gpos_x = gpos_x + blockDim.x;
}

__syncthreads();

//----> SNR for nTaps=1
spos = PD_NWINDOWS * threadIdx.x;
for (i = 0; i < PD_NWINDOWS; i++)
{
res_SNR[i] = ( s_input[spos + i] - signal_mean ) / signal_sd;
res_Taps[i] = 1;
}

//----------------------------------------------
//----> FIR calculation loop
FIR_value = s_input[spos];
for (f = 1; f < maxTaps; f++)
{
//nTaps=f+1;!
ftemp = signal_sd + f * modifier;
spos = PD_NWINDOWS * threadIdx.x;

// 0th element from NWINDOW
i = 0;
FIR_value += s_input[spos + f];

SNR = ( FIR_value - ( f + 1 ) * signal_mean ) / ( ftemp );
if (SNR > res_SNR[i])
{
res_SNR[i] = SNR;
res_Taps[i] = f + 1;
}

temp_FIR_value = FIR_value;
for (i = 1; i < PD_NWINDOWS; i++)
{
temp_FIR_value = temp_FIR_value - s_input[spos + i - 1] + s_input[spos + f + i];

SNR = ( temp_FIR_value - ( f + 1 ) * signal_mean ) / ( ftemp );
if (SNR > res_SNR[i])
{
res_SNR[i] = SNR;
res_Taps[i] = f + 1;
}
}
}

//----------------------------------------------
//---- Writing data
gpos_y = blockIdx.y * nTimesamples;
gpos_x = blockIdx.x * PD_NTHREADS * PD_NWINDOWS + PD_NWINDOWS * threadIdx.x;
for (i = 0; i < PD_NWINDOWS; i++)
{
if (( gpos_x + i ) < ( nTimesamples ))
{
d_input[gpos_y + gpos_x + i] = res_SNR[i];
d_output_taps[gpos_y + gpos_x + i] = res_Taps[i];
}
}
}
	.text
	.file	"PD_INPLACE_GPU_KERNEL.hip"
	.globl	_Z36__device_stub__PD_INPLACE_GPU_KERNELPfS_PhS_ii # -- Begin function _Z36__device_stub__PD_INPLACE_GPU_KERNELPfS_PhS_ii
	.type	_Z36__device_stub__PD_INPLACE_GPU_KERNELPfS_PhS_ii,@function
_Z36__device_stub__PD_INPLACE_GPU_KERNELPfS_PhS_ii: # @_Z36__device_stub__PD_INPLACE_GPU_KERNELPfS_PhS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z36__device_stub__PD_INPLACE_GPU_KERNELPfS_PhS_ii, .Lfunc_end0-_Z36__device_stub__PD_INPLACE_GPU_KERNELPfS_PhS_ii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii,@object # @_Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii
	.p2align	3, 0x0
_Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii:
	.quad	_Z36__device_stub__PD_INPLACE_GPU_KERNELPfS_PhS_ii
	.size	_Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii"
	.size	.L__unnamed_1, 36

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z36__device_stub__PD_INPLACE_GPU_KERNELPfS_PhS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii ; -- Begin function _Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii
	.globl	_Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii
	.p2align	8
	.type	_Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii,@function
_Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii:    ; @_Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii
; %bb.0:
	s_clause 0x2
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x20
	s_load_b32 s17, s[0:1], 0x34
	v_lshl_add_u32 v1, v0, 2, 0
	v_mov_b32_e32 v3, v0
	s_mov_b32 s20, -1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	s_load_b64 s[12:13], s[10:11], 0x0
	s_load_b32 s16, s[10:11], 0x8
	s_lshl_b32 s11, s14, 10
	s_add_u32 s0, s0, 40
	s_mul_i32 s10, s15, s3
	s_addc_u32 s1, s1, 0
	s_and_b32 s17, s17, 0xffff
	s_add_i32 s18, s11, s10
	s_lshl_b32 s19, s17, 2
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v2, s11, v3
	s_mov_b32 s21, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s3, v2
	s_cbranch_execz .LBB0_3
; %bb.2:                                ;   in Loop: Header=BB0_1 Depth=1
	v_add_nc_u32_e32 v4, s18, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v2, v[4:5], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v2
.LBB0_3:                                ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	v_add_nc_u32_e32 v3, s17, v3
	v_add_nc_u32_e32 v1, s19, v1
	s_xor_b32 s20, s20, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s20
	s_mov_b32 s20, 0
	s_cbranch_vccnz .LBB0_1
; %bb.4:
	s_add_i32 s18, s2, 0x3ff
	s_mov_b32 s19, exec_lo
	v_cmpx_gt_i32_e64 s18, v3
	s_cbranch_execz .LBB0_7
; %bb.5:                                ; %.lr.ph
	s_load_b32 s0, s[0:1], 0x0
	s_mov_b32 s1, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s15, s15, s0
	s_add_i32 s0, s2, -1
	s_add_i32 s14, s14, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s14, s0, v[0:1]
	v_add_nc_u32_e32 v2, s17, v3
	s_mov_b32 s0, 0
.LBB0_6:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, s1, v1
	v_add_nc_u32_e32 v6, s1, v3
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s6, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	v_add_nc_u32_e32 v5, s1, v2
	s_add_i32 s1, s1, s17
	v_cmp_le_i32_e32 vcc_lo, s18, v5
	v_lshl_add_u32 v5, v6, 2, 0
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v4
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_6
.LBB0_7:                                ; %Flow189
	s_or_b32 exec_lo, exec_lo, s19
	v_lshlrev_b32_e32 v5, 1, v0
	s_mov_b32 s7, 0
	s_mov_b32 s6, -1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $sgpr0
                                        ; implicit-def: $vgpr0_vgpr1
.LBB0_8:                                ; =>This Inner Loop Header: Depth=1
	v_or_b32_e32 v2, s7, v5
	s_cmp_eq_u32 s7, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, v2, 2, 0
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_subrev_f32_e32 v2, s12, v2
	v_div_scale_f32 v3, null, s16, s16, v2
	v_div_scale_f32 v8, vcc_lo, v2, s16, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v6, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v7, -v3, v6, 1.0
	v_fmac_f32_e32 v6, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, v8, v6
	v_fma_f32 v9, -v3, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v9, v6
	v_fma_f32 v3, -v3, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_div_fmas_f32 v3, v3, v6, v7
	s_cselect_b32 vcc_lo, -1, 0
	s_and_b32 s14, vcc_lo, exec_lo
	s_cselect_b32 s1, 1, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v2, v3, s16, v2
	s_cmp_eq_u32 s7, 0
	s_mov_b32 s7, 1
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e32 v4, v4, v2, vcc_lo
	s_and_b32 s14, vcc_lo, exec_lo
	s_cselect_b32 s0, 1, s0
	s_and_b32 vcc_lo, exec_lo, s6
	s_mov_b32 s6, 0
	s_cbranch_vccnz .LBB0_8
; %bb.9:
	s_cmp_lt_i32 s2, 2
	s_cbranch_scc1 .LBB0_12
; %bb.10:                               ; %.lr.ph130.preheader
	v_lshl_add_u32 v2, v5, 2, 0
	v_lshlrev_b32_e32 v0, 3, v0
	s_mov_b32 s6, 1
	ds_load_b32 v6, v2
	v_mov_b32_e32 v3, s1
	v_add3_u32 v0, v0, 0, 4
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v7, v6
.LBB0_11:                               ; %.lr.ph130
                                        ; =>This Inner Loop Header: Depth=1
	ds_load_2addr_b32 v[8:9], v0 offset1:1
	v_cvt_f32_i32_e32 v10, s6
	s_add_i32 s6, s6, 1
	v_add_nc_u32_e32 v0, 4, v0
	v_cvt_f32_i32_e32 v11, s6
	s_cmp_lg_u32 s2, s6
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v7, v7, v8
	v_fma_f32 v8, s13, v10, s16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v10, -s12, v11, v7
	v_sub_f32_e32 v12, v7, v6
	v_div_scale_f32 v13, null, v8, v8, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v9, v12, v9
	v_div_scale_f32 v16, vcc_lo, v10, v8, v10
	v_rcp_f32_e32 v12, v13
	s_waitcnt_depctr 0xfff
	v_fma_f32 v14, -v13, v12, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v14, v12
	v_fma_f32 v9, -s12, v11, v9
	v_div_scale_f32 v11, null, v8, v8, v9
	v_div_scale_f32 v18, s0, v9, v8, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v15, v11
	s_waitcnt_depctr 0xfff
	v_fma_f32 v17, -v11, v15, 1.0
	v_dual_fmac_f32 v15, v17, v15 :: v_dual_mul_f32 v14, v16, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v17, v18, v15
	v_fma_f32 v19, -v13, v14, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, v19, v12
	v_fma_f32 v13, -v13, v14, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v16, -v11, v17, v18
	v_fmac_f32_e32 v17, v16, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v12, v13, v12, v14
	s_mov_b32 vcc_lo, s0
	v_fma_f32 v11, -v11, v17, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v10, v12, v8, v10
	v_div_fmas_f32 v11, v11, v15, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f32_e64 s1, v10, v4
	v_div_fixup_f32 v8, v11, v8, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, v1, v1, s1
	v_cndmask_b32_e64 v2, v2, s6, s1
	v_cndmask_b32_e64 v4, v4, v10, s1
	v_cmp_gt_f32_e32 vcc_lo, v8, v1
	v_cndmask_b32_e64 v3, v3, s6, vcc_lo
	v_cndmask_b32_e32 v1, v1, v8, vcc_lo
	s_cbranch_scc1 .LBB0_11
	s_branch .LBB0_13
.LBB0_12:
	v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
.LBB0_13:                               ; %._crit_edge131
	v_add_nc_u32_e32 v0, s11, v5
	s_mov_b32 s2, 0
	s_mov_b32 s0, -1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v5, s10, v0
.LBB0_14:                               ; =>This Inner Loop Header: Depth=1
	v_or_b32_e32 v6, s2, v0
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s3, v6
	s_cbranch_execz .LBB0_16
; %bb.15:                               ;   in Loop: Header=BB0_14 Depth=1
	s_cmp_eq_u32 s2, 1
	s_cselect_b32 vcc_lo, -1, 0
	v_dual_cndmask_b32 v11, v2, v3 :: v_dual_add_nc_u32 v6, s2, v5
	v_cndmask_b32_e32 v10, v4, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[8:9], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
	v_add_co_u32 v6, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
	global_store_b32 v[8:9], v10, off
	global_store_b8 v[6:7], v11, off
.LBB0_16:                               ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_xor_b32 s0, s0, -1
	s_mov_b32 s2, 1
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b32 s0, 0
	s_cbranch_vccnz .LBB0_14
; %bb.17:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii, .Lfunc_end0-_Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1144
; NumSgprs: 24
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         160
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z21PD_INPLACE_GPU_KERNELPfS_PhS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
