#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cmath>
#include <cstdio>

#define N 300
#define NSTREAM 4

__global__ void kernel_1()
{
	double sum = 0.0;

	for (int i = 0; i < N; i++)
	{
		sum = sum + tan(0.1) * tan(0.1);
	}
}

__global__ void kernel_2()
{
	double sum = 0.0;

	for (int i = 0; i < N; i++)
	{
		sum = sum + tan(0.1) * tan(0.1);
	}
}

__global__ void kernel_3()
{
	double sum = 0.0;

	for (int i = 0; i < N; i++)
	{
		sum = sum + tan(0.1) * tan(0.1);
	}
}

__global__ void kernel_4()
{
	double sum = 0.0;

	for (int i = 0; i < N; i++)
	{
		sum = sum + tan(0.1) * tan(0.1);
	}
}

int main(int argc, char **argv)
{
	int n_streams = NSTREAM;
	int isize = 1;
	int iblock = 1;

	float elapsed_time;

	int dev = 0;
	cudaDeviceProp deviceProp;
	cudaGetDeviceProperties(&deviceProp, dev);
	printf("> Using Device %d: %s with num_streams=%d\n", dev, deviceProp.name,n_streams);
	cudaSetDevice(dev);

	// check if device support hyper-q
	if (deviceProp.major < 3 || (deviceProp.major == 3 && deviceProp.minor < 5))
	{
		if (deviceProp.concurrentKernels == 0)
		{
			printf("> GPU does not support concurrent kernel execution (SM 3.5 or higher required)\n");
			printf("> CUDA kernel runs will be serialized\n");
		}
		else
		{
			printf("> GPU does not support HyperQ\n");
			printf("> CUDA kernel runs will have limited concurrency\n");
		}
	}

	printf("> Compute Capability %d.%d hardware with %d multi-processors\n", deviceProp.major, deviceProp.minor, deviceProp.multiProcessorCount);

	// Allocate and initialize an array of stream handles
	cudaStream_t *streams = (cudaStream_t *)malloc(n_streams * sizeof(cudaStream_t));
	cudaEvent_t *events = (cudaEvent_t *)malloc(n_streams * sizeof(cudaEvent_t));

	for (int i = 0; i < n_streams; i++)
	{
		cudaStreamCreate(&(streams[i]));
	}
	for(int i = 0; i< n_streams; ++i)
	{
		cudaEventCreateWithFlags(&events[i], cudaEventDisableTiming);
	}

	// set up execution configuration
	dim3 block(iblock);
	dim3 grid(isize / iblock);
	printf("> grid %d block %d\n", grid.x, block.x);

	// creat events
	cudaEvent_t start, stop;
	cudaEventCreate(&start);
	cudaEventCreate(&stop);

	// record start event
	cudaEventRecord(start, 0);

	// dispatch job with depth first ordering
	for (int i = 0; i < n_streams; i++)
	{
		kernel_1 <<<grid, block, 0, streams[i] >>>();
		kernel_2 <<<grid, block, 0, streams[i] >>>();
		kernel_3 <<<grid, block, 0, streams[i] >>>();
		kernel_4 <<<grid, block, 0, streams[i] >>>();

		cudaEventRecord(events[i], streams[i]);
		cudaStreamWaitEvent(streams[i], events[i], 0);
	}

	// record stop event
	cudaEventRecord(stop, 0);
	cudaEventSynchronize(stop);

	// calculate elapsed time
	cudaEventElapsedTime(&elapsed_time, start, stop);
	printf("Measured time for parallel execution = %.3fs\n", elapsed_time / 1000.0f);

	// release all stream
	for (int i = 0; i < n_streams; i++)
	{
		cudaStreamDestroy(streams[i]);
	}

	free(streams);
	free(events);

	// destroy events
	cudaEventDestroy(start);
	cudaEventDestroy(stop);

	// reset device
	cudaDeviceReset();
	system("Pause");
	return 0;
}

	.file	"tmpxft_00343ab0_00000000-6_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z26__device_stub__Z8kernel_1vv
	.type	_Z26__device_stub__Z8kernel_1vv, @function
_Z26__device_stub__Z8kernel_1vv:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$4294967297, %rax
	leaq	8(%rsp), %rcx
	movq	%rsp, %rdx
	leaq	28(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1, 24(%rsp)
	movl	$1, 36(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 28(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	8(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z8kernel_1v(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 112
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L2:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z26__device_stub__Z8kernel_1vv, .-_Z26__device_stub__Z8kernel_1vv
	.globl	_Z8kernel_1v
	.type	_Z8kernel_1v, @function
_Z8kernel_1v:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z26__device_stub__Z8kernel_1vv
	.cfi_endproc
.LFE2053:
	.size	_Z8kernel_1v, .-_Z8kernel_1v
	.globl	_Z26__device_stub__Z8kernel_2vv
	.type	_Z26__device_stub__Z8kernel_2vv, @function
_Z26__device_stub__Z8kernel_2vv:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$4294967297, %rax
	leaq	8(%rsp), %rcx
	movq	%rsp, %rdx
	leaq	28(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1, 24(%rsp)
	movl	$1, 36(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 28(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	8(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z8kernel_2v(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 112
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L8:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z26__device_stub__Z8kernel_2vv, .-_Z26__device_stub__Z8kernel_2vv
	.globl	_Z8kernel_2v
	.type	_Z8kernel_2v, @function
_Z8kernel_2v:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z26__device_stub__Z8kernel_2vv
	.cfi_endproc
.LFE2055:
	.size	_Z8kernel_2v, .-_Z8kernel_2v
	.globl	_Z26__device_stub__Z8kernel_3vv
	.type	_Z26__device_stub__Z8kernel_3vv, @function
_Z26__device_stub__Z8kernel_3vv:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$4294967297, %rax
	leaq	8(%rsp), %rcx
	movq	%rsp, %rdx
	leaq	28(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1, 24(%rsp)
	movl	$1, 36(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 28(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	8(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z8kernel_3v(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 112
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L13:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z26__device_stub__Z8kernel_3vv, .-_Z26__device_stub__Z8kernel_3vv
	.globl	_Z8kernel_3v
	.type	_Z8kernel_3v, @function
_Z8kernel_3v:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z26__device_stub__Z8kernel_3vv
	.cfi_endproc
.LFE2057:
	.size	_Z8kernel_3v, .-_Z8kernel_3v
	.globl	_Z26__device_stub__Z8kernel_4vv
	.type	_Z26__device_stub__Z8kernel_4vv, @function
_Z26__device_stub__Z8kernel_4vv:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$4294967297, %rax
	leaq	8(%rsp), %rcx
	movq	%rsp, %rdx
	leaq	28(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1, 24(%rsp)
	movl	$1, 36(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 28(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	8(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z8kernel_4v(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 112
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L18:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z26__device_stub__Z8kernel_4vv, .-_Z26__device_stub__Z8kernel_4vv
	.globl	_Z8kernel_4v
	.type	_Z8kernel_4v, @function
_Z8kernel_4v:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z26__device_stub__Z8kernel_4vv
	.cfi_endproc
.LFE2059:
	.size	_Z8kernel_4v, .-_Z8kernel_4v
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"> Using Device %d: %s with num_streams=%d\n"
.LC1:
	.string	"> GPU does not support concurrent kernel execution (SM 3.5 or higher required)\n"
.LC2:
	.string	"> CUDA kernel runs will be serialized\n"
.LC3:
	.string	"> GPU does not support HyperQ\n"
.LC4:
	.string	"> CUDA kernel runs will have limited concurrency\n"
.LC5:
	.string	"> Compute Capability %d.%d hardware with %d multi-processors\n"
.LC6:
	.string	"> grid %d block %d\n"
.LC8:
	.string	"Measured time for parallel execution = %.3fs\n"
.LC9:
	.string	"Pause"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	xorl	%esi, %esi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$1096, %rsp
	.cfi_def_cfa_offset 1136
	movq	%fs:40, %rax
	movq	%rax, 1080(%rsp)
	xorl	%eax, %eax
	leaq	48(%rsp), %rbx
	movq	%rbx, %rdi
	call	cudaGetDeviceProperties_v2@PLT
	movl	$4, %r8d
	movq	%rbx, %rcx
	xorl	%edx, %edx
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%edi, %edi
	call	cudaSetDevice@PLT
	movl	408(%rsp), %eax
	cmpl	$2, %eax
	jle	.L24
	cmpl	$3, %eax
	jne	.L25
	cmpl	$4, 412(%rsp)
	jg	.L25
.L24:
	cmpl	$0, 624(%rsp)
	jne	.L26
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC2(%rip), %rsi
	jmp	.L39
.L26:
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC4(%rip), %rsi
.L39:
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L25:
	movl	436(%rsp), %r8d
	movl	412(%rsp), %ecx
	xorl	%eax, %eax
	leaq	.LC5(%rip), %rsi
	movl	408(%rsp), %edx
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	$32, %edi
	call	malloc@PLT
	movl	$32, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, %r12
	call	cudaStreamCreate@PLT
	leaq	8(%rbx), %rdi
	movq	%r12, %rbp
	leaq	32(%r12), %r13
	call	cudaStreamCreate@PLT
	leaq	16(%rbx), %rdi
	call	cudaStreamCreate@PLT
	leaq	24(%rbx), %rdi
	call	cudaStreamCreate@PLT
.L27:
	movq	%rbp, %rdi
	movl	$2, %esi
	addq	$8, %rbp
	call	cudaEventCreateWithFlags@PLT
	cmpq	%rbp, %r13
	jne	.L27
	movl	$1, %ecx
	movl	$1, %edx
	xorl	%eax, %eax
	xorl	%ebp, %ebp
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	movl	$1, 28(%rsp)
	movl	$1, 32(%rsp)
	movl	$1, 40(%rsp)
	movl	$1, 44(%rsp)
	call	__printf_chk@PLT
	leaq	8(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	16(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
.L32:
	movl	$1, 36(%rsp)
	movl	32(%rsp), %ecx
	xorl	%r8d, %r8d
	movq	(%rbx,%rbp), %r9
	movl	44(%rsp), %esi
	movl	$1, 24(%rsp)
	movq	36(%rsp), %rdi
	movq	24(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	call	_Z26__device_stub__Z8kernel_1vv
.L28:
	movl	32(%rsp), %ecx
	movq	(%rbx,%rbp), %r9
	xorl	%r8d, %r8d
	movq	24(%rsp), %rdx
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	call	_Z26__device_stub__Z8kernel_2vv
.L29:
	movl	32(%rsp), %ecx
	movq	(%rbx,%rbp), %r9
	xorl	%r8d, %r8d
	movq	24(%rsp), %rdx
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	call	_Z26__device_stub__Z8kernel_3vv
.L30:
	movl	32(%rsp), %ecx
	movq	(%rbx,%rbp), %r9
	xorl	%r8d, %r8d
	movq	24(%rsp), %rdx
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L31
	call	_Z26__device_stub__Z8kernel_4vv
.L31:
	movq	(%rbx,%rbp), %rsi
	movq	(%r12,%rbp), %rdi
	call	cudaEventRecord@PLT
	movq	(%r12,%rbp), %rsi
	movq	(%rbx,%rbp), %rdi
	xorl	%edx, %edx
	addq	$8, %rbp
	call	cudaStreamWaitEvent@PLT
	cmpq	$32, %rbp
	jne	.L32
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	xorl	%ebp, %ebp
	call	cudaEventRecord@PLT
	movq	16(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	leaq	4(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	movss	4(%rsp), %xmm0
	divss	.LC7(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
.L33:
	movq	(%rbx,%rbp,8), %rdi
	incq	%rbp
	call	cudaStreamDestroy@PLT
	cmpq	$4, %rbp
	jne	.L33
	movq	%rbx, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	16(%rsp), %rdi
	call	cudaEventDestroy@PLT
	call	cudaDeviceReset@PLT
	leaq	.LC9(%rip), %rdi
	call	system@PLT
	movq	1080(%rsp), %rax
	subq	%fs:40, %rax
	je	.L34
	call	__stack_chk_fail@PLT
.L34:
	addq	$1096, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z8kernel_4v"
.LC11:
	.string	"_Z8kernel_3v"
.LC12:
	.string	"_Z8kernel_2v"
.LC13:
	.string	"_Z8kernel_1v"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z8kernel_4v(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8kernel_3v(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8kernel_2v(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8kernel_1v(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2061:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC7:
	.long	1148846080
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include "hip/hip_runtime.h"

#include <cmath>
#include <cstdio>

#define N 300
#define NSTREAM 4

__global__ void kernel_1()
{
	double sum = 0.0;

	for (int i = 0; i < N; i++)
	{
		sum = sum + tan(0.1) * tan(0.1);
	}
}

__global__ void kernel_2()
{
	double sum = 0.0;

	for (int i = 0; i < N; i++)
	{
		sum = sum + tan(0.1) * tan(0.1);
	}
}

__global__ void kernel_3()
{
	double sum = 0.0;

	for (int i = 0; i < N; i++)
	{
		sum = sum + tan(0.1) * tan(0.1);
	}
}

__global__ void kernel_4()
{
	double sum = 0.0;

	for (int i = 0; i < N; i++)
	{
		sum = sum + tan(0.1) * tan(0.1);
	}
}

int main(int argc, char **argv)
{
	int n_streams = NSTREAM;
	int isize = 1;
	int iblock = 1;

	float elapsed_time;

	int dev = 0;
	hipDeviceProp_t deviceProp;
	hipGetDeviceProperties(&deviceProp, dev);
	printf("> Using Device %d: %s with num_streams=%d\n", dev, deviceProp.name,n_streams);
	hipSetDevice(dev);

	// check if device support hyper-q
	if (deviceProp.major < 3 || (deviceProp.major == 3 && deviceProp.minor < 5))
	{
		if (deviceProp.concurrentKernels == 0)
		{
			printf("> GPU does not support concurrent kernel execution (SM 3.5 or higher required)\n");
			printf("> CUDA kernel runs will be serialized\n");
		}
		else
		{
			printf("> GPU does not support HyperQ\n");
			printf("> CUDA kernel runs will have limited concurrency\n");
		}
	}

	printf("> Compute Capability %d.%d hardware with %d multi-processors\n", deviceProp.major, deviceProp.minor, deviceProp.multiProcessorCount);

	// Allocate and initialize an array of stream handles
	hipStream_t *streams = (hipStream_t *)malloc(n_streams * sizeof(hipStream_t));
	hipEvent_t *events = (hipEvent_t *)malloc(n_streams * sizeof(hipEvent_t));

	for (int i = 0; i < n_streams; i++)
	{
		hipStreamCreate(&(streams[i]));
	}
	for(int i = 0; i< n_streams; ++i)
	{
		hipEventCreateWithFlags(&events[i], hipEventDisableTiming);
	}

	// set up execution configuration
	dim3 block(iblock);
	dim3 grid(isize / iblock);
	printf("> grid %d block %d\n", grid.x, block.x);

	// creat events
	hipEvent_t start, stop;
	hipEventCreate(&start);
	hipEventCreate(&stop);

	// record start event
	hipEventRecord(start, 0);

	// dispatch job with depth first ordering
	for (int i = 0; i < n_streams; i++)
	{
		kernel_1 <<<grid, block, 0, streams[i] >>>();
		kernel_2 <<<grid, block, 0, streams[i] >>>();
		kernel_3 <<<grid, block, 0, streams[i] >>>();
		kernel_4 <<<grid, block, 0, streams[i] >>>();

		hipEventRecord(events[i], streams[i]);
		hipStreamWaitEvent(streams[i], events[i], 0);
	}

	// record stop event
	hipEventRecord(stop, 0);
	hipEventSynchronize(stop);

	// calculate elapsed time
	hipEventElapsedTime(&elapsed_time, start, stop);
	printf("Measured time for parallel execution = %.3fs\n", elapsed_time / 1000.0f);

	// release all stream
	for (int i = 0; i < n_streams; i++)
	{
		hipStreamDestroy(streams[i]);
	}

	free(streams);
	free(events);

	// destroy events
	hipEventDestroy(start);
	hipEventDestroy(stop);

	// reset device
	hipDeviceReset();
	system("Pause");
	return 0;
}

	.text
	.file	"kernel.hip"
	.globl	_Z23__device_stub__kernel_1v    # -- Begin function _Z23__device_stub__kernel_1v
	.type	_Z23__device_stub__kernel_1v,@function
_Z23__device_stub__kernel_1v:           # @_Z23__device_stub__kernel_1v
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rbx
	leaq	24(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movq	%r12, %rcx
	callq	__hipPopCallConfiguration
	movq	(%rbx), %rsi
	movl	8(%rbx), %edx
	movq	(%r14), %rcx
	movl	8(%r14), %r8d
	movq	%rsp, %r9
	movl	$_Z8kernel_1v, %edi
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	pushq	(%r15)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$72, %rsp
	.cfi_adjust_cfa_offset -72
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z23__device_stub__kernel_1v, .Lfunc_end0-_Z23__device_stub__kernel_1v
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__kernel_2v    # -- Begin function _Z23__device_stub__kernel_2v
	.type	_Z23__device_stub__kernel_2v,@function
_Z23__device_stub__kernel_2v:           # @_Z23__device_stub__kernel_2v
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rbx
	leaq	24(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movq	%r12, %rcx
	callq	__hipPopCallConfiguration
	movq	(%rbx), %rsi
	movl	8(%rbx), %edx
	movq	(%r14), %rcx
	movl	8(%r14), %r8d
	movq	%rsp, %r9
	movl	$_Z8kernel_2v, %edi
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	pushq	(%r15)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$72, %rsp
	.cfi_adjust_cfa_offset -72
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z23__device_stub__kernel_2v, .Lfunc_end1-_Z23__device_stub__kernel_2v
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__kernel_3v    # -- Begin function _Z23__device_stub__kernel_3v
	.type	_Z23__device_stub__kernel_3v,@function
_Z23__device_stub__kernel_3v:           # @_Z23__device_stub__kernel_3v
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rbx
	leaq	24(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movq	%r12, %rcx
	callq	__hipPopCallConfiguration
	movq	(%rbx), %rsi
	movl	8(%rbx), %edx
	movq	(%r14), %rcx
	movl	8(%r14), %r8d
	movq	%rsp, %r9
	movl	$_Z8kernel_3v, %edi
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	pushq	(%r15)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$72, %rsp
	.cfi_adjust_cfa_offset -72
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z23__device_stub__kernel_3v, .Lfunc_end2-_Z23__device_stub__kernel_3v
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__kernel_4v    # -- Begin function _Z23__device_stub__kernel_4v
	.type	_Z23__device_stub__kernel_4v,@function
_Z23__device_stub__kernel_4v:           # @_Z23__device_stub__kernel_4v
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rbx
	leaq	24(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movq	%r12, %rcx
	callq	__hipPopCallConfiguration
	movq	(%rbx), %rsi
	movl	8(%rbx), %edx
	movq	(%r14), %rcx
	movl	8(%r14), %r8d
	movq	%rsp, %r9
	movl	$_Z8kernel_4v, %edi
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	pushq	(%r15)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$72, %rsp
	.cfi_adjust_cfa_offset -72
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z23__device_stub__kernel_4v, .Lfunc_end3-_Z23__device_stub__kernel_4v
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI4_0:
	.long	0x447a0000                      # float 1000
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$1504, %rsp                     # imm = 0x5E0
	.cfi_def_cfa_offset 1552
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	32(%rsp), %rbx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	hipGetDevicePropertiesR0600
	movl	$.L.str, %edi
	xorl	%esi, %esi
	movq	%rbx, %rdx
	movl	$4, %ecx
	xorl	%eax, %eax
	callq	printf
	xorl	%edi, %edi
	callq	hipSetDevice
	cmpl	$3, 360(%rbx)
	jl	.LBB4_3
# %bb.1:
	jne	.LBB4_4
# %bb.2:
	cmpl	$4, 396(%rsp)
	jg	.LBB4_4
.LBB4_3:                                # %.sink.split
	cmpl	$0, 608(%rsp)
	movl	$.Lstr.2, %eax
	movl	$.Lstr, %edi
	cmoveq	%rax, %rdi
	movl	$.Lstr.3, %eax
	movl	$.Lstr.1, %ebx
	cmoveq	%rax, %rbx
	callq	puts@PLT
	movq	%rbx, %rdi
	callq	puts@PLT
.LBB4_4:
	movl	392(%rsp), %esi
	movl	396(%rsp), %edx
	movl	420(%rsp), %ecx
	xorl	%r15d, %r15d
	movl	$.L.str.5, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$32, %edi
	callq	malloc
	movq	%rax, %rbx
	movl	$32, %edi
	callq	malloc
	movq	%rax, %r14
.LBB4_5:                                # =>This Inner Loop Header: Depth=1
	leaq	(%rbx,%r15), %rdi
	callq	hipStreamCreate
	addq	$8, %r15
	cmpq	$32, %r15
	jne	.LBB4_5
# %bb.6:                                # %.preheader.preheader
	xorl	%r15d, %r15d
.LBB4_7:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	leaq	(%r14,%r15), %rdi
	movl	$2, %esi
	callq	hipEventCreateWithFlags
	addq	$8, %r15
	cmpq	$32, %r15
	jne	.LBB4_7
# %bb.8:
	movabsq	$4294967297, %r15               # imm = 0x100000001
	xorl	%r13d, %r13d
	movl	$.L.str.6, %edi
	movl	$1, %esi
	movl	$1, %edx
	xorl	%eax, %eax
	callq	printf
	leaq	16(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movq	(%r12), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
.LBB4_9:                                # =>This Inner Loop Header: Depth=1
	movq	(%rbx,%r13,8), %r9
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_11
# %bb.10:                               #   in Loop: Header=BB4_9 Depth=1
	callq	_Z23__device_stub__kernel_1v
.LBB4_11:                               #   in Loop: Header=BB4_9 Depth=1
	movq	(%rbx,%r13,8), %r9
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_13
# %bb.12:                               #   in Loop: Header=BB4_9 Depth=1
	callq	_Z23__device_stub__kernel_2v
.LBB4_13:                               #   in Loop: Header=BB4_9 Depth=1
	movq	(%rbx,%r13,8), %r9
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_15
# %bb.14:                               #   in Loop: Header=BB4_9 Depth=1
	callq	_Z23__device_stub__kernel_3v
.LBB4_15:                               #   in Loop: Header=BB4_9 Depth=1
	movq	(%rbx,%r13,8), %r9
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_17
# %bb.16:                               #   in Loop: Header=BB4_9 Depth=1
	callq	_Z23__device_stub__kernel_4v
.LBB4_17:                               #   in Loop: Header=BB4_9 Depth=1
	movq	(%r14,%r13,8), %rdi
	movq	(%rbx,%r13,8), %rsi
	callq	hipEventRecord
	movq	(%rbx,%r13,8), %rdi
	movq	(%r14,%r13,8), %rsi
	xorl	%edx, %edx
	callq	hipStreamWaitEvent
	incq	%r13
	cmpq	$4, %r13
	jne	.LBB4_9
# %bb.18:
	movq	8(%rsp), %rdi
	xorl	%r12d, %r12d
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	28(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventElapsedTime
	movss	(%r15), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	divss	.LCPI4_0(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.7, %edi
	movb	$1, %al
	callq	printf
.LBB4_19:                               # =>This Inner Loop Header: Depth=1
	movq	(%rbx,%r12,8), %rdi
	callq	hipStreamDestroy
	incq	%r12
	cmpq	$4, %r12
	jne	.LBB4_19
# %bb.20:
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	16(%rsp), %rdi
	callq	hipEventDestroy
	movq	8(%rsp), %rdi
	callq	hipEventDestroy
	callq	hipDeviceReset
	movl	$.L.str.8, %edi
	callq	system
	xorl	%eax, %eax
	addq	$1504, %rsp                     # imm = 0x5E0
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8kernel_1v, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8kernel_2v, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8kernel_3v, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8kernel_4v, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z8kernel_1v,@object            # @_Z8kernel_1v
	.section	.rodata,"a",@progbits
	.globl	_Z8kernel_1v
	.p2align	3, 0x0
_Z8kernel_1v:
	.quad	_Z23__device_stub__kernel_1v
	.size	_Z8kernel_1v, 8

	.type	_Z8kernel_2v,@object            # @_Z8kernel_2v
	.globl	_Z8kernel_2v
	.p2align	3, 0x0
_Z8kernel_2v:
	.quad	_Z23__device_stub__kernel_2v
	.size	_Z8kernel_2v, 8

	.type	_Z8kernel_3v,@object            # @_Z8kernel_3v
	.globl	_Z8kernel_3v
	.p2align	3, 0x0
_Z8kernel_3v:
	.quad	_Z23__device_stub__kernel_3v
	.size	_Z8kernel_3v, 8

	.type	_Z8kernel_4v,@object            # @_Z8kernel_4v
	.globl	_Z8kernel_4v
	.p2align	3, 0x0
_Z8kernel_4v:
	.quad	_Z23__device_stub__kernel_4v
	.size	_Z8kernel_4v, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"> Using Device %d: %s with num_streams=%d\n"
	.size	.L.str, 43

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"> Compute Capability %d.%d hardware with %d multi-processors\n"
	.size	.L.str.5, 62

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"> grid %d block %d\n"
	.size	.L.str.6, 20

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Measured time for parallel execution = %.3fs\n"
	.size	.L.str.7, 46

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"Pause"
	.size	.L.str.8, 6

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z8kernel_1v"
	.size	.L__unnamed_1, 13

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z8kernel_2v"
	.size	.L__unnamed_2, 13

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z8kernel_3v"
	.size	.L__unnamed_3, 13

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z8kernel_4v"
	.size	.L__unnamed_4, 13

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"> GPU does not support HyperQ"
	.size	.Lstr, 30

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"> CUDA kernel runs will have limited concurrency"
	.size	.Lstr.1, 49

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"> GPU does not support concurrent kernel execution (SM 3.5 or higher required)"
	.size	.Lstr.2, 79

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"> CUDA kernel runs will be serialized"
	.size	.Lstr.3, 38

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__kernel_1v
	.addrsig_sym _Z23__device_stub__kernel_2v
	.addrsig_sym _Z23__device_stub__kernel_3v
	.addrsig_sym _Z23__device_stub__kernel_4v
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8kernel_1v
	.addrsig_sym _Z8kernel_2v
	.addrsig_sym _Z8kernel_3v
	.addrsig_sym _Z8kernel_4v
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8kernel_1v            ; -- Begin function _Z8kernel_1v
	.globl	_Z8kernel_1v
	.p2align	8
	.type	_Z8kernel_1v,@function
_Z8kernel_1v:                           ; @_Z8kernel_1v
; %bb.0:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8kernel_1v
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 0
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 0
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 1
		.amdhsa_next_free_sgpr 1
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8kernel_1v, .Lfunc_end0-_Z8kernel_1v
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4
; NumSgprs: 0
; NumVgprs: 0
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 1
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8kernel_2v            ; -- Begin function _Z8kernel_2v
	.globl	_Z8kernel_2v
	.p2align	8
	.type	_Z8kernel_2v,@function
_Z8kernel_2v:                           ; @_Z8kernel_2v
; %bb.0:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8kernel_2v
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 0
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 0
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 1
		.amdhsa_next_free_sgpr 1
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z8kernel_2v, .Lfunc_end1-_Z8kernel_2v
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4
; NumSgprs: 0
; NumVgprs: 0
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 1
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8kernel_3v            ; -- Begin function _Z8kernel_3v
	.globl	_Z8kernel_3v
	.p2align	8
	.type	_Z8kernel_3v,@function
_Z8kernel_3v:                           ; @_Z8kernel_3v
; %bb.0:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8kernel_3v
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 0
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 0
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 1
		.amdhsa_next_free_sgpr 1
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z8kernel_3v, .Lfunc_end2-_Z8kernel_3v
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4
; NumSgprs: 0
; NumVgprs: 0
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 1
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8kernel_4v            ; -- Begin function _Z8kernel_4v
	.globl	_Z8kernel_4v
	.p2align	8
	.type	_Z8kernel_4v,@function
_Z8kernel_4v:                           ; @_Z8kernel_4v
; %bb.0:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8kernel_4v
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 0
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 0
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 1
		.amdhsa_next_free_sgpr 1
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z8kernel_4v, .Lfunc_end3-_Z8kernel_4v
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4
; NumSgprs: 0
; NumVgprs: 0
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 1
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:           []
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 4
    .kernarg_segment_size: 0
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8kernel_1v
    .private_segment_fixed_size: 0
    .sgpr_count:     0
    .sgpr_spill_count: 0
    .symbol:         _Z8kernel_1v.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     0
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:           []
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 4
    .kernarg_segment_size: 0
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8kernel_2v
    .private_segment_fixed_size: 0
    .sgpr_count:     0
    .sgpr_spill_count: 0
    .symbol:         _Z8kernel_2v.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     0
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:           []
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 4
    .kernarg_segment_size: 0
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8kernel_3v
    .private_segment_fixed_size: 0
    .sgpr_count:     0
    .sgpr_spill_count: 0
    .symbol:         _Z8kernel_3v.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     0
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:           []
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 4
    .kernarg_segment_size: 0
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8kernel_4v
    .private_segment_fixed_size: 0
    .sgpr_count:     0
    .sgpr_spill_count: 0
    .symbol:         _Z8kernel_4v.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     0
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
