#include<stdio.h>
#include<sys/time.h>
/*
#define BLOCKSIZEX 64
#define BLOCKSIZEY 16
#define BLOCKSIZE BLOCKSIZEX * BLOCKSIZEY
#define GRIDSIZEX 8
#define GRIDSIZEY 16
#define GRIDSIZE GRIDSIZEX * GRIDSIZEY
#define THREAD_NUM BLOCKSIZE * GRIDSIZE

#define MIMAX	256
#define MJMAX	GRIDSIZEY * (BLOCKSIZEY - 2) + 2
#define MKMAX	GRIDSIZEX * (BLOCKSIZEX - 2) + 2

#define NN 750
*/

#define BLOCKSIZEX 6
#define BLOCKSIZEY 4
#define BLOCKSIZE BLOCKSIZEX * BLOCKSIZEY
#define GRIDSIZEX 3
#define GRIDSIZEY 6
#define GRIDSIZE GRIDSIZEX * GRIDSIZEY
#define THREAD_NUM BLOCKSIZE * GRIDSIZE

#define MIMAX	6
#define MJMAX	GRIDSIZEY * (BLOCKSIZEY - 2) + 2
#define MKMAX	GRIDSIZEX * (BLOCKSIZEX - 2) + 2

#define NN 3

/*static float p[MIMAX][MJMAX][MKMAX];
static float a[MIMAX][MJMAX][MKMAX][4];
static float b[MIMAX][MJMAX][MKMAX][3];
static float c[MIMAX][MJMAX][MKMAX][3];
static float bnd[MIMAX][MJMAX][MKMAX];
static float work1[MIMAX][MJMAX][MKMAX];
static float work2[MIMAX][MJMAX][MKMAX];*/

static int imax, jmax, kmax, mimax, mjmax, mkmax;
static float omega;

double second(){
	struct timeval tm;
	double t;

	static int base_sec = 0, base_usec = 0;

	gettimeofday(&tm, NULL);

	if(base_sec == 0 && base_usec == 0){
		base_sec = tm.tv_sec;
		base_usec = tm.tv_usec;
		t = 0.0;
	}
	else{
		t = (double)(tm.tv_sec-base_sec) + ((double)(tm.tv_usec-base_usec))/1.0e6;
	}

	return t;
}


__global__ void jacobi(float *a0, float *a1, float *a2, float *a3, float *b0, float *b1, float *b2, float *c0, float *c1, float *c2, float *p, float *wrk1, float *wrk2, float *bnd, int nn, int imax, int jmax, int kmax, float omega, float *gosa){
	int i, j, k, i2, j2, k2, n, xy, c, csb;
	i = 1;
	float s0, ss, temp;
	//const int size = (imax-1)/(imax-1);
	k = threadIdx.x + (blockDim.x-2) * blockIdx.x + 1;
	j = threadIdx.y + (blockDim.y-2) * blockIdx.y + 1;
	i2 = i-1;
	k2 = threadIdx.x + blockDim.x * blockIdx.x;
	j2 = threadIdx.y + blockDim.y * blockIdx.y;
	const int tid = (k-1) + (j-1) * (kmax-2);
	xy = kmax * jmax;
	//__shared__ float sb[BLOCKSIZE];
	//__shared__ float sb2[BLOCKSIZE];
	extern __shared__ float sb[];
	float *sb_t = sb;
	float *sb_m = sb + blockDim.x * blockDim.y;
	float *sb_b = sb + 2 * blockDim.x * blockDim.y;
	extern __shared__ float sb2[];
	float *sb2_t = sb2;
	float *sb2_m = sb2 + blockDim.x * blockDim.y;
	float *sb2_b = sb2 + 2 * blockDim.x * blockDim.y;
	csb = threadIdx.x + threadIdx.y * blockDim.x;
	for(n=0;n<nn;++n){
		temp=0.0;

		s0 = a0[i*jmax*kmax+j*kmax+k] * p[(i+1)*jmax*kmax+j*kmax+k]
		+ a1[i*jmax*kmax+j*kmax+k] * p[i*jmax*kmax+(j+1)*kmax+k]
		+ a2[i*jmax*kmax+j*kmax+k] * p[i*jmax*kmax+j*kmax+(k+1)]
		+ b0[i*jmax*kmax+j*kmax+k]
			*(p[(i+1)*jmax*kmax+(j+1)*kmax+k]
			- p[(i+1)*jmax*kmax+(j-1)*kmax+k]
			- p[(i-1)*jmax*kmax+(j+1)*kmax+k]
			+ p[(i-1)*jmax*kmax+(j-1)*kmax+k] )
		+ b1[i*jmax*kmax+j*kmax+k]
			*(p[i*jmax*kmax+(j+1)*kmax+(k+1)]
			- p[i*jmax*kmax+(j-1)*kmax+(k+1)]
			- p[i*jmax*kmax+(j-1)*kmax+(k-1)]
			+ p[i*jmax*kmax+(j+1)*kmax+(k-1)])
		+ b2[i*jmax*kmax+j*kmax+k]
			*(p[(i+1)*jmax*kmax+j*kmax+(k+1)]
			- p[(i-1)*jmax*kmax+j*kmax+(k+1)]
			- p[(i+1)*jmax*kmax+j*kmax+(k-1)]
			+ p[(i-1)*jmax*kmax+j*kmax+(k-1)] )
		+ c0[i*jmax*kmax+j*kmax+k] * p[(i-1)*jmax*kmax+j*kmax+k]
		+ c1[i*jmax*kmax+j*kmax+k] * p[i*jmax*kmax+(j-1)*kmax+k]
		+ c2[i*jmax*kmax+j*kmax+k] * p[i*jmax*kmax+j*kmax+(k-1)]
		+ wrk1[i*jmax*kmax+j*kmax+k];

		ss = (s0 * a3[i*jmax*kmax+j*kmax+k] - p[i*jmax*kmax+j*kmax+k]) * bnd[i*jmax*kmax+j*kmax+k];

		temp = temp + ss*ss;

		wrk2[i*jmax*kmax+j*kmax+k] = p[i*jmax*kmax+j*kmax+k] + omega * ss;

		for(i=2 ; i<imax-1 ; ++i){
			i2 = i-1;
			printf("%f\n", sb_m[csb]);
			sb_m[csb] = p[i*jmax*kmax+j*kmax+k];
			if(0 < threadIdx.x && k < kmax-1 && 0 < j && j < jmax-1){
				s0 = a0[i*jmax*kmax+j*kmax+k] * p[(i+1)*jmax*kmax+j*kmax+k]
				+ a1[i*jmax*kmax+j*kmax+k] * p[i*jmax*kmax+(j+1)*kmax+k]
				+ a2[i*jmax*kmax+j*kmax+k] * p[i*jmax*kmax+j*kmax+(k+1)]
				+ b0[i*jmax*kmax+j*kmax+k]
					*(p[(i+1)*jmax*kmax+(j+1)*kmax+k]
					- p[(i+1)*jmax*kmax+(j-1)*kmax+k]
					- p[(i-1)*jmax*kmax+(j+1)*kmax+k]
					+ p[(i-1)*jmax*kmax+(j-1)*kmax+k] )
				+ b1[i*jmax*kmax+j*kmax+k]
					*(p[i*jmax*kmax+(j+1)*kmax+(k+1)]
					- p[i*jmax*kmax+(j-1)*kmax+(k+1)]
					- p[i*jmax*kmax+(j-1)*kmax+(k-1)]
					+ p[i*jmax*kmax+(j+1)*kmax+(k-1)])
				+ b2[i*jmax*kmax+j*kmax+k]
					*(p[(i+1)*jmax*kmax+j*kmax+(k+1)]
					- p[(i-1)*jmax*kmax+j*kmax+(k+1)]
					- p[(i+1)*jmax*kmax+j*kmax+(k-1)]
					+ p[(i-1)*jmax*kmax+j*kmax+(k-1)] )
				+ c0[i*jmax*kmax+j*kmax+k] * p[(i-1)*jmax*kmax+j*kmax+k]
				+ c1[i*jmax*kmax+j*kmax+k] * p[i*jmax*kmax+(j-1)*kmax+k]
				+ c2[i*jmax*kmax+j*kmax+k] * p[i*jmax*kmax+j*kmax+(k-1)]
				+ wrk1[i*jmax*kmax+j*kmax+k];

				ss = (s0 * a3[i*jmax*kmax+j*kmax+k] - p[i*jmax*kmax+j*kmax+k]) * bnd[i*jmax*kmax+j*kmax+k];

				temp = temp + ss*ss;

				wrk2[i*jmax*kmax+j*kmax+k] = p[i*jmax*kmax+j*kmax+k] + omega * ss;
			}
			sb2_m[csb] = wrk2[i*jmax*kmax+j*kmax+k];
			printf("%f\n", sb2_m[csb]);
			__syncthreads();
			if(0 < threadIdx.x && threadIdx.x < blockDim.x-1 && 0 < threadIdx.y && threadIdx.y < blockDim.y-1){
				s0 = a0[i2*jmax*kmax+j*kmax+k] * wrk2[(i2+1)*jmax*kmax+j*kmax+k]
				+ a1[i2*jmax*kmax+j*kmax+k] * wrk2[i2*jmax*kmax+(j+1)*kmax+k]
				+ a2[i2*jmax*kmax+j*kmax+k] * wrk2[i2*jmax*kmax+j*kmax+(k+1)]
				+ b0[i2*jmax*kmax+j*kmax+k]
					*(wrk2[(i2+1)*jmax*kmax+(j+1)*kmax+k]
					- wrk2[(i2+1)*jmax*kmax+(j-1)*kmax+k]
					- wrk2[(i2-1)*jmax*kmax+(j+1)*kmax+k]
					+ wrk2[(i2-1)*jmax*kmax+(j-1)*kmax+k] )
				+ b1[i2*jmax*kmax+j*kmax+k]
					*(wrk2[i2*jmax*kmax+(j+1)*kmax+(k+1)]
					- wrk2[i2*jmax*kmax+(j-1)*kmax+(k+1)]
					- wrk2[i2*jmax*kmax+(j-1)*kmax+(k-1)]
					+ wrk2[i2*jmax*kmax+(j+1)*kmax+(k-1)])
				+ b2[i2*jmax*kmax+j*kmax+k]
					*(wrk2[(i2+1)*jmax*kmax+j*kmax+(k+1)]
					- wrk2[(i2-1)*jmax*kmax+j*kmax+(k+1)]
					- wrk2[(i2+1)*jmax*kmax+j*kmax+(k-1)]
					+ wrk2[(i2-1)*jmax*kmax+j*kmax+(k-1)] )
				+ c0[i2*jmax*kmax+j*kmax+k] * wrk2[(i2-1)*jmax*kmax+j*kmax+k]
				+ c1[i2*jmax*kmax+j*kmax+k] * wrk2[i2*jmax*kmax+(j-1)*kmax+k]
				+ c2[i2*jmax*kmax+j*kmax+k] * wrk2[i2*jmax*kmax+j*kmax+(k-1)]
				+ wrk1[i2*jmax*kmax+j*kmax+k];

				ss = ( s0 * a3[i2*jmax*kmax+j*kmax+k] - wrk2[i2*jmax*kmax+j*kmax+k] ) * bnd[i2*jmax*kmax+j*kmax+k];

				temp = temp + ss*ss;

				p[i2*jmax*kmax+j*kmax+k] = wrk2[i2*jmax*kmax+j*kmax+k] + omega * ss;
				c += xy;
			}
		}
		i2 = imax-1;
		if(0 < threadIdx.x && threadIdx.x < blockDim.x-1 && 0 < threadIdx.y && threadIdx.y < blockDim.y-1){
			s0 = a0[i2*jmax*kmax+j*kmax+k] * wrk2[(i2+1)*jmax*kmax+j*kmax+k]
			+ a1[i2*jmax*kmax+j*kmax+k] * wrk2[i2*jmax*kmax+(j+1)*kmax+k]
			+ a2[i2*jmax*kmax+j*kmax+k] * wrk2[i2*jmax*kmax+j*kmax+(k+1)]
			+ b0[i2*jmax*kmax+j*kmax+k]
				*(wrk2[(i2+1)*jmax*kmax+(j+1)*kmax+k]
				- wrk2[(i2+1)*jmax*kmax+(j-1)*kmax+k]
				- wrk2[(i2-1)*jmax*kmax+(j+1)*kmax+k]
				+ wrk2[(i2-1)*jmax*kmax+(j-1)*kmax+k] )
			+ b1[i2*jmax*kmax+j*kmax+k]
				*(wrk2[i2*jmax*kmax+(j+1)*kmax+(k+1)]
				- wrk2[i2*jmax*kmax+(j-1)*kmax+(k+1)]
				- wrk2[i2*jmax*kmax+(j-1)*kmax+(k-1)]
				+ wrk2[i2*jmax*kmax+(j+1)*kmax+(k-1)])
			+ b2[i2*jmax*kmax+j*kmax+k]
				*(wrk2[(i2+1)*jmax*kmax+j*kmax+(k+1)]
				- wrk2[(i2-1)*jmax*kmax+j*kmax+(k+1)]
				- wrk2[(i2+1)*jmax*kmax+j*kmax+(k-1)]
				+ wrk2[(i2-1)*jmax*kmax+j*kmax+(k-1)] )
			+ c0[i2*jmax*kmax+j*kmax+k] * wrk2[(i2-1)*jmax*kmax+j*kmax+k]
			+ c1[i2*jmax*kmax+j*kmax+k] * wrk2[i2*jmax*kmax+(j-1)*kmax+k]
			+ c2[i2*jmax*kmax+j*kmax+k] * wrk2[i2*jmax*kmax+j*kmax+(k-1)]
			+ wrk1[i2*jmax*kmax+j*kmax+k];

			ss = ( s0 * a3[i2*jmax*kmax+j*kmax+k] - wrk2[i2*jmax*kmax+j*kmax+k] ) * bnd[i2*jmax*kmax+j*kmax+k];

			temp = temp + ss*ss;

			p[i2*jmax*kmax+j*kmax+k] = wrk2[i2*jmax*kmax+j*kmax+k] + omega * ss;
		}
	} /* end n loop */
	__syncthreads();
	gosa[tid] = temp;
}

int main(){
	int i, j, k;
	float final_gosa;
	double cpu0, cpu1, nflop, xmflops2, score;

	float gosa[THREAD_NUM];

	/************************************/
	float *p;
	float *a0, *a1, *a2, *a3;
	float *b0, *b1, *b2;
	float *c0, *c1, *c2;

	float *bnd;
	float *wrk1, *wrk2;
	/************************************/
	mimax = MIMAX;
	mjmax = MJMAX;
	mkmax = MKMAX;
	imax = MIMAX-1;
	jmax = MJMAX-1;
	kmax = MKMAX-1;
	//int N_IJK = MIMAX*MJMAX*MKMAX;
	int N_IJK = mimax*mjmax*mkmax;
	int WORKSIZE = THREAD_NUM*mimax;
	/************************************/
	float *dev_p;
	float *dev_a0, *dev_a1, *dev_a2, *dev_a3;
	float *dev_b0, *dev_b1, *dev_b2;
	float *dev_c0, *dev_c1, *dev_c2;

	float *dev_bnd;
	float *dev_wrk1, *dev_wrk2;

	float *dev_gosa;
	/************************************/


	omega = 0.8;

	//initial_maxtrix();

	/******allocate mem on CPU***********/
	a0 = (float*)malloc(sizeof(float)*N_IJK);
	a1 = (float*)malloc(sizeof(float)*N_IJK);
	a2 = (float*)malloc(sizeof(float)*N_IJK);
	a3 = (float*)malloc(sizeof(float)*N_IJK);

	b0 = (float*)malloc(sizeof(float)*N_IJK);
	b1 = (float*)malloc(sizeof(float)*N_IJK);
	b2 = (float*)malloc(sizeof(float)*N_IJK);

	c0 = (float*)malloc(sizeof(float)*N_IJK);
	c1 = (float*)malloc(sizeof(float)*N_IJK);
	c2 = (float*)malloc(sizeof(float)*N_IJK);

	p = (float*)malloc(sizeof(float)*N_IJK);

	wrk1 = (float*)malloc(sizeof(float)*N_IJK);
	wrk2 = (float*)malloc(sizeof(float)*WORKSIZE);
	bnd = (float*)malloc(sizeof(float)*N_IJK);

	//gosa = (float*)malloc(sizeof(float));
	/************************************/

	/******allocate mem on GPU***********/
	cudaMalloc((void**)&dev_a0, N_IJK*sizeof(float));
	cudaMalloc((void**)&dev_a1, N_IJK*sizeof(float));
	cudaMalloc((void**)&dev_a2, N_IJK*sizeof(float));
	cudaMalloc((void**)&dev_a3, N_IJK*sizeof(float));

	cudaMalloc((void**)&dev_b0, N_IJK*sizeof(float));
	cudaMalloc((void**)&dev_b1, N_IJK*sizeof(float));
	cudaMalloc((void**)&dev_b2, N_IJK*sizeof(float));

	cudaMalloc((void**)&dev_c0, N_IJK*sizeof(float));
	cudaMalloc((void**)&dev_c1, N_IJK*sizeof(float));
	cudaMalloc((void**)&dev_c2, N_IJK*sizeof(float));

	cudaMalloc((void**)&dev_p, N_IJK*sizeof(float));

	cudaMalloc((void**)&dev_bnd, N_IJK*sizeof(float));
	cudaMalloc((void**)&dev_wrk1, N_IJK*sizeof(float));
	cudaMalloc((void**)&dev_wrk2, WORKSIZE*sizeof(float));

	cudaMalloc((void**)&dev_gosa, sizeof(float)*THREAD_NUM);
	/************************************/

	/*****Initialize*********************/
	//int i,j,k;
	/*
	for(i=0 ; i<mimax ; ++i)
		for(j=0 ; j<mjmax ; ++j)
			for(k=0 ; k<mkmax ; ++k){
				a0[i*mjmax*mkmax+j*mkmax+k]=0.0;
				a1[i*mjmax*mkmax+j*mkmax+k]=0.0;
				a2[i*mjmax*mkmax+j*mkmax+k]=0.0;
				a3[i*mjmax*mkmax+j*mkmax+k]=0.0;
				b0[i*mjmax*mkmax+j*mkmax+k]=0.0;
				b1[i*mjmax*mkmax+j*mkmax+k]=0.0;
				b2[i*mjmax*mkmax+j*mkmax+k]=0.0;
				c0[i*mjmax*mkmax+j*mkmax+k]=0.0;
				c1[i*mjmax*mkmax+j*mkmax+k]=0.0;
				c2[i*mjmax*mkmax+j*mkmax+k]=0.0;
				p[i*mjmax*mkmax+j*mkmax+k]=0.0;
				wrk1[i*mjmax*mkmax+j*mkmax+k]=0.0;
				bnd[i*mjmax*mkmax+j*mkmax+k]=0.0;
	      		}
	*/
	for(i=0 ; i<mimax ; ++i){
		for(j=0 ; j<mjmax ; ++j){
			for(k=0 ; k<mkmax ; ++k){
				a0[i*mjmax*mkmax+j*mkmax+k]=1.0;
				a1[i*mjmax*mkmax+j*mkmax+k]=1.0;
				a2[i*mjmax*mkmax+j*mkmax+k]=1.0;
				a3[i*mjmax*mkmax+j*mkmax+k]=1.0/6.0;
				b0[i*mjmax*mkmax+j*mkmax+k]=0.0;
				b1[i*mjmax*mkmax+j*mkmax+k]=0.0;
				b2[i*mjmax*mkmax+j*mkmax+k]=0.0;
				c0[i*mjmax*mkmax+j*mkmax+k]=1.0;
				c1[i*mjmax*mkmax+j*mkmax+k]=1.0;
				c2[i*mjmax*mkmax+j*mkmax+k]=1.0;
				p[i*mjmax*mkmax+j*mkmax+k]=(float)(i*i)/(float)(imax*imax);
				wrk1[i*mjmax*mkmax+j*mkmax+k]=0.0;
				bnd[i*mjmax*mkmax+j*mkmax+k]=1.0;
			}
		}
	}
	/************************************/

	/*****copy array to device mem*******/
	cudaMemcpy(dev_a0, a0, N_IJK*sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_a1, a1, N_IJK*sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_a2, a2, N_IJK*sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_a3, a3, N_IJK*sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_b0, b0, N_IJK*sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_b1, b1, N_IJK*sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_b2, b2, N_IJK*sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_c0, c0, N_IJK*sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_c1, c1, N_IJK*sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_c2, c2, N_IJK*sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_wrk1, wrk1, N_IJK*sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_wrk2, wrk2, WORKSIZE*sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_bnd, bnd, N_IJK*sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_p, p, N_IJK*sizeof(float), cudaMemcpyHostToDevice);

	//cudaMemcpy(dev_gosa, gosa, sizeof(float), cudaMemcpyHostToDevice);
	/************************************/

	printf("mimax = %d mjmax = %d mkmax = %d\n", MIMAX, MJMAX, MKMAX);
	printf("imax = %d jmax = %d kmax = %d\n", imax, jmax, kmax);

	cpu0 = second(); /**measuring**/

	dim3 block(BLOCKSIZEX, BLOCKSIZEY, 1);
	dim3 grid(GRIDSIZEX, GRIDSIZEY, 1);

	jacobi<<<grid, block, sizeof(float) * BLOCKSIZE * 6>>>(dev_a0, dev_a1, dev_a2, dev_a3, dev_b0, dev_b1, dev_b2, dev_c0, dev_c1, dev_c2, dev_p, dev_wrk1, dev_wrk2, dev_bnd, NN, mimax, mjmax, mkmax, omega, dev_gosa);

	cudaDeviceSynchronize();

	cpu1 = second();

	cudaMemcpy(&gosa, dev_gosa, sizeof(float)*THREAD_NUM, cudaMemcpyDeviceToHost);

	/******Free mem on the GPU**********/
	cudaFree(dev_a0);
	cudaFree(dev_a1);
	cudaFree(dev_a2);
	cudaFree(dev_a3);
	cudaFree(dev_b0);
	cudaFree(dev_b1);
	cudaFree(dev_b2);
	cudaFree(dev_c0);
	cudaFree(dev_c1);
	cudaFree(dev_c2);
	cudaFree(dev_p);
	cudaFree(dev_wrk1);
	cudaFree(dev_wrk2);
	cudaFree(dev_bnd);

	cudaFree(dev_gosa);
	/************************************/

	/********Final sum of gosa***********/
	for(int gosa_index=0; gosa_index<THREAD_NUM; gosa_index++){
		//printf("%f\n", gosa[gosa_index]);
		final_gosa += gosa[gosa_index];
		//printf("Gosa%d: %e \n", gosa_index, gosa[gosa_index]);
	}
	/************************************/

	nflop = (kmax-2)*(jmax-2)*(imax-2)*34;

	if(cpu1 != 0.0){
		xmflops2 = nflop/cpu1*1.0e-6*(float)NN;
	}

	score = xmflops2/32.27;

	printf("gpu: %f sec.\n", cpu1);
	printf("Loop executed for %d times\n", NN);
	printf("Gosa: %e \n", final_gosa);
	//printf("MFLOPS measured: %f\n", xmflops2);
	//printf("Score: %f\n", score);

	return(0);
}

	.file	"tmpxft_0033e651_00000000-6_himeno_temporal_blocking2.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z6secondv
	.type	_Z6secondv, @function
_Z6secondv:
.LFB2027:
	.cfi_startproc
	endbr64
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	xorl	%esi, %esi
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	gettimeofday@PLT
	movslq	_ZZ6secondvE8base_sec(%rip), %rdx
	movq	16(%rsp), %rcx
	movslq	_ZZ6secondvE9base_usec(%rip), %rsi
	movl	%edx, %eax
	orl	%esi, %eax
	movq	8(%rsp), %rax
	jne	.L3
	movl	%eax, _ZZ6secondvE8base_sec(%rip)
	xorps	%xmm0, %xmm0
	movl	%ecx, _ZZ6secondvE9base_usec(%rip)
	jmp	.L2
.L3:
	subq	%rdx, %rax
	subq	%rsi, %rcx
	cvtsi2sdq	%rax, %xmm1
	cvtsi2sdq	%rcx, %xmm0
	divsd	.LC1(%rip), %xmm0
	addsd	%xmm1, %xmm0
.L2:
	movq	24(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z6secondv, .-_Z6secondv
	.globl	_Z58__device_stub__Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_PfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_
	.type	_Z58__device_stub__Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_PfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_, @function
_Z58__device_stub__Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_PfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$376, %rsp
	.cfi_def_cfa_offset 384
	movq	384(%rsp), %rax
	movq	%rdi, 120(%rsp)
	leaq	152(%rsp), %rdi
	movq	%rsi, 112(%rsp)
	leaq	164(%rsp), %rsi
	movq	%rax, 72(%rsp)
	movq	392(%rsp), %rax
	movq	%rdx, 104(%rsp)
	leaq	136(%rsp), %rdx
	movq	%rax, 64(%rsp)
	movq	400(%rsp), %rax
	movq	%rcx, 96(%rsp)
	leaq	144(%rsp), %rcx
	movq	%rax, 56(%rsp)
	movq	408(%rsp), %rax
	movq	%r8, 88(%rsp)
	movq	%rax, 48(%rsp)
	movq	416(%rsp), %rax
	movq	%r9, 80(%rsp)
	movq	%rax, 40(%rsp)
	movq	424(%rsp), %rax
	movss	%xmm0, 12(%rsp)
	movq	%rax, 32(%rsp)
	movq	432(%rsp), %rax
	movq	%rax, 24(%rsp)
	movq	440(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	480(%rsp), %rax
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 360(%rsp)
	xorl	%eax, %eax
	leaq	120(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	448(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	456(%rsp), %rax
	movq	%rax, 320(%rsp)
	leaq	464(%rsp), %rax
	movq	%rax, 328(%rsp)
	leaq	472(%rsp), %rax
	movq	%rax, 336(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 344(%rsp)
	movq	%rsp, %rax
	movq	%rax, 352(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 152(%rsp)
	movl	$1, 160(%rsp)
	movq	%rax, 164(%rsp)
	movl	$1, 172(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	144(%rsp)
	.cfi_def_cfa_offset 392
	leaq	_Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_(%rip), %rdi
	pushq	144(%rsp)
	.cfi_def_cfa_offset 400
	movq	180(%rsp), %rcx
	movl	188(%rsp), %r8d
	movq	168(%rsp), %rsi
	movl	176(%rsp), %edx
	leaq	216(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 392
	popq	%rdx
	.cfi_def_cfa_offset 384
.L8:
	movq	360(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$376, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z58__device_stub__Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_PfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_, .-_Z58__device_stub__Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_PfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_
	.globl	_Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_
	.type	_Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_, @function
_Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z58__device_stub__Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_PfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_
	.cfi_endproc
.LFE2054:
	.size	_Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_, .-_Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC6:
	.string	"mimax = %d mjmax = %d mkmax = %d\n"
.LC7:
	.string	"imax = %d jmax = %d kmax = %d\n"
.LC8:
	.string	"gpu: %f sec.\n"
.LC9:
	.string	"Loop executed for %d times\n"
.LC10:
	.string	"Gosa: %e \n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$4704, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$1992, %rsp
	.cfi_def_cfa_offset 2048
	movq	%fs:40, %rax
	movq	%rax, 1976(%rsp)
	xorl	%eax, %eax
	movl	$6, _ZL5mimax(%rip)
	movl	$14, _ZL5mjmax(%rip)
	movl	$14, _ZL5mkmax(%rip)
	movl	$5, _ZL4imax(%rip)
	movl	$13, _ZL4jmax(%rip)
	movl	$13, _ZL4kmax(%rip)
	movl	$0x3f4ccccd, _ZL5omega(%rip)
	call	malloc@PLT
	movl	$4704, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$4704, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$4704, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movl	$4704, %edi
	movq	%rax, (%rsp)
	call	malloc@PLT
	movl	$4704, %edi
	movq	%rax, 8(%rsp)
	call	malloc@PLT
	movl	$4704, %edi
	movq	%rax, 16(%rsp)
	call	malloc@PLT
	movl	$4704, %edi
	movq	%rax, 24(%rsp)
	call	malloc@PLT
	movl	$4704, %edi
	movq	%rax, 32(%rsp)
	call	malloc@PLT
	movl	$4704, %edi
	movq	%rax, 40(%rsp)
	call	malloc@PLT
	movl	$4704, %edi
	movq	%rax, 48(%rsp)
	call	malloc@PLT
	movl	$4704, %edi
	movq	%rax, %r14
	call	malloc@PLT
	movl	$10368, %edi
	movq	%rax, 56(%rsp)
	call	malloc@PLT
	movl	$4704, %edi
	movq	%rax, 88(%rsp)
	call	malloc@PLT
	leaq	112(%rsp), %rdi
	movl	$4704, %esi
	movq	%rax, 64(%rsp)
	call	cudaMalloc@PLT
	leaq	120(%rsp), %rdi
	movl	$4704, %esi
	call	cudaMalloc@PLT
	leaq	128(%rsp), %rdi
	movl	$4704, %esi
	call	cudaMalloc@PLT
	leaq	136(%rsp), %rdi
	movl	$4704, %esi
	call	cudaMalloc@PLT
	leaq	144(%rsp), %rdi
	movl	$4704, %esi
	call	cudaMalloc@PLT
	leaq	152(%rsp), %rdi
	movl	$4704, %esi
	call	cudaMalloc@PLT
	leaq	160(%rsp), %rdi
	movl	$4704, %esi
	call	cudaMalloc@PLT
	leaq	168(%rsp), %rdi
	movl	$4704, %esi
	call	cudaMalloc@PLT
	leaq	176(%rsp), %rdi
	movl	$4704, %esi
	call	cudaMalloc@PLT
	leaq	184(%rsp), %rdi
	movl	$4704, %esi
	call	cudaMalloc@PLT
	leaq	104(%rsp), %rdi
	movl	$4704, %esi
	call	cudaMalloc@PLT
	leaq	192(%rsp), %rdi
	movl	$4704, %esi
	call	cudaMalloc@PLT
	leaq	200(%rsp), %rdi
	movl	$4704, %esi
	call	cudaMalloc@PLT
	leaq	208(%rsp), %rdi
	movl	$10368, %esi
	call	cudaMalloc@PLT
	leaq	216(%rsp), %rdi
	movl	$1728, %esi
	call	cudaMalloc@PLT
	movl	_ZL4imax(%rip), %ecx
	movl	_ZL5mimax(%rip), %eax
	movl	_ZL5mjmax(%rip), %r11d
	movl	_ZL5mkmax(%rip), %r9d
	imull	%ecx, %ecx
	movl	%eax, 84(%rsp)
	movss	.LC3(%rip), %xmm0
	movl	%r11d, %r15d
	movss	.LC4(%rip), %xmm2
	imull	%r9d, %r15d
	xorl	%r8d, %r8d
	xorl	%edx, %edx
	movl	%ecx, 80(%rsp)
.L14:
	cmpl	%edx, 84(%rsp)
	jle	.L18
	movl	%edx, %r13d
	movl	%r8d, %edi
	xorl	%esi, %esi
	imull	%edx, %r13d
.L19:
	cmpl	%esi, %r11d
	jle	.L16
	movslq	%edi, %rax
	xorl	%r10d, %r10d
	salq	$2, %rax
.L17:
	cmpl	%r10d, %r9d
	jle	.L25
	cvtsi2ssl	%r13d, %xmm1
	movq	(%rsp), %rcx
	movss	%xmm0, (%rbx,%rax)
	incl	%r10d
	cvtsi2ssl	80(%rsp), %xmm3
	movss	%xmm0, (%r12,%rax)
	movss	%xmm2, (%rcx,%rax)
	movq	8(%rsp), %rcx
	movss	%xmm0, 0(%rbp,%rax)
	movl	$0x00000000, (%rcx,%rax)
	movq	16(%rsp), %rcx
	divss	%xmm3, %xmm1
	movl	$0x00000000, (%rcx,%rax)
	movq	24(%rsp), %rcx
	movl	$0x00000000, (%rcx,%rax)
	movq	32(%rsp), %rcx
	movss	%xmm0, (%rcx,%rax)
	movq	40(%rsp), %rcx
	movss	%xmm0, (%rcx,%rax)
	movq	48(%rsp), %rcx
	movss	%xmm0, (%rcx,%rax)
	movq	56(%rsp), %rcx
	movl	$0x00000000, (%rcx,%rax)
	movq	64(%rsp), %rcx
	movss	%xmm0, (%rcx,%rax)
	movss	%xmm1, (%r14,%rax)
	addq	$4, %rax
	jmp	.L17
.L25:
	incl	%esi
	addl	%r9d, %edi
	jmp	.L19
.L16:
	incl	%edx
	addl	%r15d, %r8d
	jmp	.L14
.L18:
	movq	112(%rsp), %rdi
	movl	$1, %ecx
	movl	$4704, %edx
	movq	%r12, %rsi
	call	cudaMemcpy@PLT
	movq	120(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$4704, %edx
	call	cudaMemcpy@PLT
	movq	128(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$4704, %edx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	movl	$1, %ecx
	movq	136(%rsp), %rdi
	movl	$4704, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rsi
	movl	$1, %ecx
	movq	144(%rsp), %rdi
	movl	$4704, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	movq	152(%rsp), %rdi
	movl	$4704, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rsi
	movl	$1, %ecx
	movq	160(%rsp), %rdi
	movl	$4704, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rsi
	movl	$1, %ecx
	movq	168(%rsp), %rdi
	movl	$4704, %edx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rsi
	movl	$1, %ecx
	movq	176(%rsp), %rdi
	movl	$4704, %edx
	call	cudaMemcpy@PLT
	movq	48(%rsp), %rsi
	movl	$1, %ecx
	movq	184(%rsp), %rdi
	movl	$4704, %edx
	call	cudaMemcpy@PLT
	movq	56(%rsp), %rsi
	movl	$1, %ecx
	movq	200(%rsp), %rdi
	movl	$4704, %edx
	call	cudaMemcpy@PLT
	movq	88(%rsp), %rsi
	movl	$1, %ecx
	movq	208(%rsp), %rdi
	movl	$10368, %edx
	call	cudaMemcpy@PLT
	movq	64(%rsp), %rsi
	movl	$1, %ecx
	movq	192(%rsp), %rdi
	movl	$4704, %edx
	call	cudaMemcpy@PLT
	movq	104(%rsp), %rdi
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	$4704, %edx
	call	cudaMemcpy@PLT
	movl	$14, %r8d
	xorl	%eax, %eax
	movl	$14, %ecx
	movl	$6, %edx
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	_ZL4kmax(%rip), %r8d
	xorl	%eax, %eax
	movl	_ZL4jmax(%rip), %ecx
	movl	_ZL4imax(%rip), %edx
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	call	_Z6secondv
	xorl	%r9d, %r9d
	movl	$576, %r8d
	movabsq	$17179869190, %rdx
	movabsq	$25769803779, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 224(%rsp)
	movl	$1, 232(%rsp)
	movq	%rdi, 236(%rsp)
	movl	$1, 244(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	pushq	%rax
	.cfi_def_cfa_offset 2056
	movl	_ZL5mkmax(%rip), %eax
	pushq	224(%rsp)
	.cfi_def_cfa_offset 2064
	pushq	%rax
	.cfi_def_cfa_offset 2072
	movl	_ZL5mjmax(%rip), %eax
	pushq	%rax
	.cfi_def_cfa_offset 2080
	movl	_ZL5mimax(%rip), %eax
	pushq	%rax
	.cfi_def_cfa_offset 2088
	pushq	$3
	.cfi_def_cfa_offset 2096
	pushq	240(%rsp)
	.cfi_def_cfa_offset 2104
	pushq	264(%rsp)
	.cfi_def_cfa_offset 2112
	pushq	264(%rsp)
	.cfi_def_cfa_offset 2120
	pushq	176(%rsp)
	.cfi_def_cfa_offset 2128
	pushq	264(%rsp)
	.cfi_def_cfa_offset 2136
	pushq	264(%rsp)
	.cfi_def_cfa_offset 2144
	movss	_ZL5omega(%rip), %xmm0
	pushq	264(%rsp)
	.cfi_def_cfa_offset 2152
	pushq	264(%rsp)
	.cfi_def_cfa_offset 2160
	movq	264(%rsp), %r9
	movq	256(%rsp), %r8
	movq	248(%rsp), %rcx
	movq	240(%rsp), %rdx
	movq	232(%rsp), %rsi
	movq	224(%rsp), %rdi
	call	_Z58__device_stub__Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_PfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_
	addq	$112, %rsp
	.cfi_def_cfa_offset 2048
.L20:
	call	cudaDeviceSynchronize@PLT
	leaq	248(%rsp), %rbx
	call	_Z6secondv
	movq	216(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$1728, %edx
	movsd	%xmm0, (%rsp)
	call	cudaMemcpy@PLT
	movq	112(%rsp), %rdi
	call	cudaFree@PLT
	movq	120(%rsp), %rdi
	call	cudaFree@PLT
	movq	128(%rsp), %rdi
	call	cudaFree@PLT
	movq	136(%rsp), %rdi
	call	cudaFree@PLT
	movq	144(%rsp), %rdi
	call	cudaFree@PLT
	movq	152(%rsp), %rdi
	call	cudaFree@PLT
	movq	160(%rsp), %rdi
	call	cudaFree@PLT
	movq	168(%rsp), %rdi
	call	cudaFree@PLT
	movq	176(%rsp), %rdi
	call	cudaFree@PLT
	movq	184(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rdi
	call	cudaFree@PLT
	movq	200(%rsp), %rdi
	call	cudaFree@PLT
	movq	208(%rsp), %rdi
	call	cudaFree@PLT
	movq	192(%rsp), %rdi
	call	cudaFree@PLT
	movq	216(%rsp), %rdi
	call	cudaFree@PLT
	movsd	(%rsp), %xmm0
	xorl	%eax, %eax
.L21:
	movss	76(%rsp), %xmm4
	addss	(%rbx,%rax,4), %xmm4
	incq	%rax
	movss	%xmm4, 76(%rsp)
	cmpq	$432, %rax
	jne	.L21
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	call	__printf_chk@PLT
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	movl	$3, %edx
	call	__printf_chk@PLT
	leaq	.LC10(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	76(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	1976(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$1992, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC11:
	.string	"_Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZZ6secondvE9base_usec
	.comm	_ZZ6secondvE9base_usec,4,4
	.local	_ZZ6secondvE8base_sec
	.comm	_ZZ6secondvE8base_sec,4,4
	.local	_ZL5omega
	.comm	_ZL5omega,4,4
	.local	_ZL5mkmax
	.comm	_ZL5mkmax,4,4
	.local	_ZL5mjmax
	.comm	_ZL5mjmax,4,4
	.local	_ZL5mimax
	.comm	_ZL5mimax,4,4
	.local	_ZL4kmax
	.comm	_ZL4kmax,4,4
	.local	_ZL4jmax
	.comm	_ZL4jmax,4,4
	.local	_ZL4imax
	.comm	_ZL4imax,4,4
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC1:
	.long	0
	.long	1093567616
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC3:
	.long	1065353216
	.align 4
.LC4:
	.long	1042983595
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include<stdio.h>
#include<sys/time.h>
/*
#define BLOCKSIZEX 64
#define BLOCKSIZEY 16
#define BLOCKSIZE BLOCKSIZEX * BLOCKSIZEY
#define GRIDSIZEX 8
#define GRIDSIZEY 16
#define GRIDSIZE GRIDSIZEX * GRIDSIZEY
#define THREAD_NUM BLOCKSIZE * GRIDSIZE

#define MIMAX	256
#define MJMAX	GRIDSIZEY * (BLOCKSIZEY - 2) + 2
#define MKMAX	GRIDSIZEX * (BLOCKSIZEX - 2) + 2

#define NN 750
*/

#define BLOCKSIZEX 6
#define BLOCKSIZEY 4
#define BLOCKSIZE BLOCKSIZEX * BLOCKSIZEY
#define GRIDSIZEX 3
#define GRIDSIZEY 6
#define GRIDSIZE GRIDSIZEX * GRIDSIZEY
#define THREAD_NUM BLOCKSIZE * GRIDSIZE

#define MIMAX	6
#define MJMAX	GRIDSIZEY * (BLOCKSIZEY - 2) + 2
#define MKMAX	GRIDSIZEX * (BLOCKSIZEX - 2) + 2

#define NN 3

/*static float p[MIMAX][MJMAX][MKMAX];
static float a[MIMAX][MJMAX][MKMAX][4];
static float b[MIMAX][MJMAX][MKMAX][3];
static float c[MIMAX][MJMAX][MKMAX][3];
static float bnd[MIMAX][MJMAX][MKMAX];
static float work1[MIMAX][MJMAX][MKMAX];
static float work2[MIMAX][MJMAX][MKMAX];*/

static int imax, jmax, kmax, mimax, mjmax, mkmax;
static float omega;

double second(){
	struct timeval tm;
	double t;

	static int base_sec = 0, base_usec = 0;

	gettimeofday(&tm, NULL);

	if(base_sec == 0 && base_usec == 0){
		base_sec = tm.tv_sec;
		base_usec = tm.tv_usec;
		t = 0.0;
	}
	else{
		t = (double)(tm.tv_sec-base_sec) + ((double)(tm.tv_usec-base_usec))/1.0e6;
	}

	return t;
}


__global__ void jacobi(float *a0, float *a1, float *a2, float *a3, float *b0, float *b1, float *b2, float *c0, float *c1, float *c2, float *p, float *wrk1, float *wrk2, float *bnd, int nn, int imax, int jmax, int kmax, float omega, float *gosa){
	int i, j, k, i2, j2, k2, n, xy, c, csb;
	i = 1;
	float s0, ss, temp;
	//const int size = (imax-1)/(imax-1);
	k = threadIdx.x + (blockDim.x-2) * blockIdx.x + 1;
	j = threadIdx.y + (blockDim.y-2) * blockIdx.y + 1;
	i2 = i-1;
	k2 = threadIdx.x + blockDim.x * blockIdx.x;
	j2 = threadIdx.y + blockDim.y * blockIdx.y;
	const int tid = (k-1) + (j-1) * (kmax-2);
	xy = kmax * jmax;
	//__shared__ float sb[BLOCKSIZE];
	//__shared__ float sb2[BLOCKSIZE];
	extern __shared__ float sb[];
	float *sb_t = sb;
	float *sb_m = sb + blockDim.x * blockDim.y;
	float *sb_b = sb + 2 * blockDim.x * blockDim.y;
	extern __shared__ float sb2[];
	float *sb2_t = sb2;
	float *sb2_m = sb2 + blockDim.x * blockDim.y;
	float *sb2_b = sb2 + 2 * blockDim.x * blockDim.y;
	csb = threadIdx.x + threadIdx.y * blockDim.x;
	for(n=0;n<nn;++n){
		temp=0.0;

		s0 = a0[i*jmax*kmax+j*kmax+k] * p[(i+1)*jmax*kmax+j*kmax+k]
		+ a1[i*jmax*kmax+j*kmax+k] * p[i*jmax*kmax+(j+1)*kmax+k]
		+ a2[i*jmax*kmax+j*kmax+k] * p[i*jmax*kmax+j*kmax+(k+1)]
		+ b0[i*jmax*kmax+j*kmax+k]
			*(p[(i+1)*jmax*kmax+(j+1)*kmax+k]
			- p[(i+1)*jmax*kmax+(j-1)*kmax+k]
			- p[(i-1)*jmax*kmax+(j+1)*kmax+k]
			+ p[(i-1)*jmax*kmax+(j-1)*kmax+k] )
		+ b1[i*jmax*kmax+j*kmax+k]
			*(p[i*jmax*kmax+(j+1)*kmax+(k+1)]
			- p[i*jmax*kmax+(j-1)*kmax+(k+1)]
			- p[i*jmax*kmax+(j-1)*kmax+(k-1)]
			+ p[i*jmax*kmax+(j+1)*kmax+(k-1)])
		+ b2[i*jmax*kmax+j*kmax+k]
			*(p[(i+1)*jmax*kmax+j*kmax+(k+1)]
			- p[(i-1)*jmax*kmax+j*kmax+(k+1)]
			- p[(i+1)*jmax*kmax+j*kmax+(k-1)]
			+ p[(i-1)*jmax*kmax+j*kmax+(k-1)] )
		+ c0[i*jmax*kmax+j*kmax+k] * p[(i-1)*jmax*kmax+j*kmax+k]
		+ c1[i*jmax*kmax+j*kmax+k] * p[i*jmax*kmax+(j-1)*kmax+k]
		+ c2[i*jmax*kmax+j*kmax+k] * p[i*jmax*kmax+j*kmax+(k-1)]
		+ wrk1[i*jmax*kmax+j*kmax+k];

		ss = (s0 * a3[i*jmax*kmax+j*kmax+k] - p[i*jmax*kmax+j*kmax+k]) * bnd[i*jmax*kmax+j*kmax+k];

		temp = temp + ss*ss;

		wrk2[i*jmax*kmax+j*kmax+k] = p[i*jmax*kmax+j*kmax+k] + omega * ss;

		for(i=2 ; i<imax-1 ; ++i){
			i2 = i-1;
			printf("%f\n", sb_m[csb]);
			sb_m[csb] = p[i*jmax*kmax+j*kmax+k];
			if(0 < threadIdx.x && k < kmax-1 && 0 < j && j < jmax-1){
				s0 = a0[i*jmax*kmax+j*kmax+k] * p[(i+1)*jmax*kmax+j*kmax+k]
				+ a1[i*jmax*kmax+j*kmax+k] * p[i*jmax*kmax+(j+1)*kmax+k]
				+ a2[i*jmax*kmax+j*kmax+k] * p[i*jmax*kmax+j*kmax+(k+1)]
				+ b0[i*jmax*kmax+j*kmax+k]
					*(p[(i+1)*jmax*kmax+(j+1)*kmax+k]
					- p[(i+1)*jmax*kmax+(j-1)*kmax+k]
					- p[(i-1)*jmax*kmax+(j+1)*kmax+k]
					+ p[(i-1)*jmax*kmax+(j-1)*kmax+k] )
				+ b1[i*jmax*kmax+j*kmax+k]
					*(p[i*jmax*kmax+(j+1)*kmax+(k+1)]
					- p[i*jmax*kmax+(j-1)*kmax+(k+1)]
					- p[i*jmax*kmax+(j-1)*kmax+(k-1)]
					+ p[i*jmax*kmax+(j+1)*kmax+(k-1)])
				+ b2[i*jmax*kmax+j*kmax+k]
					*(p[(i+1)*jmax*kmax+j*kmax+(k+1)]
					- p[(i-1)*jmax*kmax+j*kmax+(k+1)]
					- p[(i+1)*jmax*kmax+j*kmax+(k-1)]
					+ p[(i-1)*jmax*kmax+j*kmax+(k-1)] )
				+ c0[i*jmax*kmax+j*kmax+k] * p[(i-1)*jmax*kmax+j*kmax+k]
				+ c1[i*jmax*kmax+j*kmax+k] * p[i*jmax*kmax+(j-1)*kmax+k]
				+ c2[i*jmax*kmax+j*kmax+k] * p[i*jmax*kmax+j*kmax+(k-1)]
				+ wrk1[i*jmax*kmax+j*kmax+k];

				ss = (s0 * a3[i*jmax*kmax+j*kmax+k] - p[i*jmax*kmax+j*kmax+k]) * bnd[i*jmax*kmax+j*kmax+k];

				temp = temp + ss*ss;

				wrk2[i*jmax*kmax+j*kmax+k] = p[i*jmax*kmax+j*kmax+k] + omega * ss;
			}
			sb2_m[csb] = wrk2[i*jmax*kmax+j*kmax+k];
			printf("%f\n", sb2_m[csb]);
			__syncthreads();
			if(0 < threadIdx.x && threadIdx.x < blockDim.x-1 && 0 < threadIdx.y && threadIdx.y < blockDim.y-1){
				s0 = a0[i2*jmax*kmax+j*kmax+k] * wrk2[(i2+1)*jmax*kmax+j*kmax+k]
				+ a1[i2*jmax*kmax+j*kmax+k] * wrk2[i2*jmax*kmax+(j+1)*kmax+k]
				+ a2[i2*jmax*kmax+j*kmax+k] * wrk2[i2*jmax*kmax+j*kmax+(k+1)]
				+ b0[i2*jmax*kmax+j*kmax+k]
					*(wrk2[(i2+1)*jmax*kmax+(j+1)*kmax+k]
					- wrk2[(i2+1)*jmax*kmax+(j-1)*kmax+k]
					- wrk2[(i2-1)*jmax*kmax+(j+1)*kmax+k]
					+ wrk2[(i2-1)*jmax*kmax+(j-1)*kmax+k] )
				+ b1[i2*jmax*kmax+j*kmax+k]
					*(wrk2[i2*jmax*kmax+(j+1)*kmax+(k+1)]
					- wrk2[i2*jmax*kmax+(j-1)*kmax+(k+1)]
					- wrk2[i2*jmax*kmax+(j-1)*kmax+(k-1)]
					+ wrk2[i2*jmax*kmax+(j+1)*kmax+(k-1)])
				+ b2[i2*jmax*kmax+j*kmax+k]
					*(wrk2[(i2+1)*jmax*kmax+j*kmax+(k+1)]
					- wrk2[(i2-1)*jmax*kmax+j*kmax+(k+1)]
					- wrk2[(i2+1)*jmax*kmax+j*kmax+(k-1)]
					+ wrk2[(i2-1)*jmax*kmax+j*kmax+(k-1)] )
				+ c0[i2*jmax*kmax+j*kmax+k] * wrk2[(i2-1)*jmax*kmax+j*kmax+k]
				+ c1[i2*jmax*kmax+j*kmax+k] * wrk2[i2*jmax*kmax+(j-1)*kmax+k]
				+ c2[i2*jmax*kmax+j*kmax+k] * wrk2[i2*jmax*kmax+j*kmax+(k-1)]
				+ wrk1[i2*jmax*kmax+j*kmax+k];

				ss = ( s0 * a3[i2*jmax*kmax+j*kmax+k] - wrk2[i2*jmax*kmax+j*kmax+k] ) * bnd[i2*jmax*kmax+j*kmax+k];

				temp = temp + ss*ss;

				p[i2*jmax*kmax+j*kmax+k] = wrk2[i2*jmax*kmax+j*kmax+k] + omega * ss;
				c += xy;
			}
		}
		i2 = imax-1;
		if(0 < threadIdx.x && threadIdx.x < blockDim.x-1 && 0 < threadIdx.y && threadIdx.y < blockDim.y-1){
			s0 = a0[i2*jmax*kmax+j*kmax+k] * wrk2[(i2+1)*jmax*kmax+j*kmax+k]
			+ a1[i2*jmax*kmax+j*kmax+k] * wrk2[i2*jmax*kmax+(j+1)*kmax+k]
			+ a2[i2*jmax*kmax+j*kmax+k] * wrk2[i2*jmax*kmax+j*kmax+(k+1)]
			+ b0[i2*jmax*kmax+j*kmax+k]
				*(wrk2[(i2+1)*jmax*kmax+(j+1)*kmax+k]
				- wrk2[(i2+1)*jmax*kmax+(j-1)*kmax+k]
				- wrk2[(i2-1)*jmax*kmax+(j+1)*kmax+k]
				+ wrk2[(i2-1)*jmax*kmax+(j-1)*kmax+k] )
			+ b1[i2*jmax*kmax+j*kmax+k]
				*(wrk2[i2*jmax*kmax+(j+1)*kmax+(k+1)]
				- wrk2[i2*jmax*kmax+(j-1)*kmax+(k+1)]
				- wrk2[i2*jmax*kmax+(j-1)*kmax+(k-1)]
				+ wrk2[i2*jmax*kmax+(j+1)*kmax+(k-1)])
			+ b2[i2*jmax*kmax+j*kmax+k]
				*(wrk2[(i2+1)*jmax*kmax+j*kmax+(k+1)]
				- wrk2[(i2-1)*jmax*kmax+j*kmax+(k+1)]
				- wrk2[(i2+1)*jmax*kmax+j*kmax+(k-1)]
				+ wrk2[(i2-1)*jmax*kmax+j*kmax+(k-1)] )
			+ c0[i2*jmax*kmax+j*kmax+k] * wrk2[(i2-1)*jmax*kmax+j*kmax+k]
			+ c1[i2*jmax*kmax+j*kmax+k] * wrk2[i2*jmax*kmax+(j-1)*kmax+k]
			+ c2[i2*jmax*kmax+j*kmax+k] * wrk2[i2*jmax*kmax+j*kmax+(k-1)]
			+ wrk1[i2*jmax*kmax+j*kmax+k];

			ss = ( s0 * a3[i2*jmax*kmax+j*kmax+k] - wrk2[i2*jmax*kmax+j*kmax+k] ) * bnd[i2*jmax*kmax+j*kmax+k];

			temp = temp + ss*ss;

			p[i2*jmax*kmax+j*kmax+k] = wrk2[i2*jmax*kmax+j*kmax+k] + omega * ss;
		}
	} /* end n loop */
	__syncthreads();
	gosa[tid] = temp;
}

int main(){
	int i, j, k;
	float final_gosa;
	double cpu0, cpu1, nflop, xmflops2, score;

	float gosa[THREAD_NUM];

	/************************************/
	float *p;
	float *a0, *a1, *a2, *a3;
	float *b0, *b1, *b2;
	float *c0, *c1, *c2;

	float *bnd;
	float *wrk1, *wrk2;
	/************************************/
	mimax = MIMAX;
	mjmax = MJMAX;
	mkmax = MKMAX;
	imax = MIMAX-1;
	jmax = MJMAX-1;
	kmax = MKMAX-1;
	//int N_IJK = MIMAX*MJMAX*MKMAX;
	int N_IJK = mimax*mjmax*mkmax;
	int WORKSIZE = THREAD_NUM*mimax;
	/************************************/
	float *dev_p;
	float *dev_a0, *dev_a1, *dev_a2, *dev_a3;
	float *dev_b0, *dev_b1, *dev_b2;
	float *dev_c0, *dev_c1, *dev_c2;

	float *dev_bnd;
	float *dev_wrk1, *dev_wrk2;

	float *dev_gosa;
	/************************************/


	omega = 0.8;

	//initial_maxtrix();

	/******allocate mem on CPU***********/
	a0 = (float*)malloc(sizeof(float)*N_IJK);
	a1 = (float*)malloc(sizeof(float)*N_IJK);
	a2 = (float*)malloc(sizeof(float)*N_IJK);
	a3 = (float*)malloc(sizeof(float)*N_IJK);

	b0 = (float*)malloc(sizeof(float)*N_IJK);
	b1 = (float*)malloc(sizeof(float)*N_IJK);
	b2 = (float*)malloc(sizeof(float)*N_IJK);

	c0 = (float*)malloc(sizeof(float)*N_IJK);
	c1 = (float*)malloc(sizeof(float)*N_IJK);
	c2 = (float*)malloc(sizeof(float)*N_IJK);

	p = (float*)malloc(sizeof(float)*N_IJK);

	wrk1 = (float*)malloc(sizeof(float)*N_IJK);
	wrk2 = (float*)malloc(sizeof(float)*WORKSIZE);
	bnd = (float*)malloc(sizeof(float)*N_IJK);

	//gosa = (float*)malloc(sizeof(float));
	/************************************/

	/******allocate mem on GPU***********/
	hipMalloc((void**)&dev_a0, N_IJK*sizeof(float));
	hipMalloc((void**)&dev_a1, N_IJK*sizeof(float));
	hipMalloc((void**)&dev_a2, N_IJK*sizeof(float));
	hipMalloc((void**)&dev_a3, N_IJK*sizeof(float));

	hipMalloc((void**)&dev_b0, N_IJK*sizeof(float));
	hipMalloc((void**)&dev_b1, N_IJK*sizeof(float));
	hipMalloc((void**)&dev_b2, N_IJK*sizeof(float));

	hipMalloc((void**)&dev_c0, N_IJK*sizeof(float));
	hipMalloc((void**)&dev_c1, N_IJK*sizeof(float));
	hipMalloc((void**)&dev_c2, N_IJK*sizeof(float));

	hipMalloc((void**)&dev_p, N_IJK*sizeof(float));

	hipMalloc((void**)&dev_bnd, N_IJK*sizeof(float));
	hipMalloc((void**)&dev_wrk1, N_IJK*sizeof(float));
	hipMalloc((void**)&dev_wrk2, WORKSIZE*sizeof(float));

	hipMalloc((void**)&dev_gosa, sizeof(float)*THREAD_NUM);
	/************************************/

	/*****Initialize*********************/
	//int i,j,k;
	/*
	for(i=0 ; i<mimax ; ++i)
		for(j=0 ; j<mjmax ; ++j)
			for(k=0 ; k<mkmax ; ++k){
				a0[i*mjmax*mkmax+j*mkmax+k]=0.0;
				a1[i*mjmax*mkmax+j*mkmax+k]=0.0;
				a2[i*mjmax*mkmax+j*mkmax+k]=0.0;
				a3[i*mjmax*mkmax+j*mkmax+k]=0.0;
				b0[i*mjmax*mkmax+j*mkmax+k]=0.0;
				b1[i*mjmax*mkmax+j*mkmax+k]=0.0;
				b2[i*mjmax*mkmax+j*mkmax+k]=0.0;
				c0[i*mjmax*mkmax+j*mkmax+k]=0.0;
				c1[i*mjmax*mkmax+j*mkmax+k]=0.0;
				c2[i*mjmax*mkmax+j*mkmax+k]=0.0;
				p[i*mjmax*mkmax+j*mkmax+k]=0.0;
				wrk1[i*mjmax*mkmax+j*mkmax+k]=0.0;
				bnd[i*mjmax*mkmax+j*mkmax+k]=0.0;
	      		}
	*/
	for(i=0 ; i<mimax ; ++i){
		for(j=0 ; j<mjmax ; ++j){
			for(k=0 ; k<mkmax ; ++k){
				a0[i*mjmax*mkmax+j*mkmax+k]=1.0;
				a1[i*mjmax*mkmax+j*mkmax+k]=1.0;
				a2[i*mjmax*mkmax+j*mkmax+k]=1.0;
				a3[i*mjmax*mkmax+j*mkmax+k]=1.0/6.0;
				b0[i*mjmax*mkmax+j*mkmax+k]=0.0;
				b1[i*mjmax*mkmax+j*mkmax+k]=0.0;
				b2[i*mjmax*mkmax+j*mkmax+k]=0.0;
				c0[i*mjmax*mkmax+j*mkmax+k]=1.0;
				c1[i*mjmax*mkmax+j*mkmax+k]=1.0;
				c2[i*mjmax*mkmax+j*mkmax+k]=1.0;
				p[i*mjmax*mkmax+j*mkmax+k]=(float)(i*i)/(float)(imax*imax);
				wrk1[i*mjmax*mkmax+j*mkmax+k]=0.0;
				bnd[i*mjmax*mkmax+j*mkmax+k]=1.0;
			}
		}
	}
	/************************************/

	/*****copy array to device mem*******/
	hipMemcpy(dev_a0, a0, N_IJK*sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_a1, a1, N_IJK*sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_a2, a2, N_IJK*sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_a3, a3, N_IJK*sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_b0, b0, N_IJK*sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_b1, b1, N_IJK*sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_b2, b2, N_IJK*sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_c0, c0, N_IJK*sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_c1, c1, N_IJK*sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_c2, c2, N_IJK*sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_wrk1, wrk1, N_IJK*sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_wrk2, wrk2, WORKSIZE*sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_bnd, bnd, N_IJK*sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_p, p, N_IJK*sizeof(float), hipMemcpyHostToDevice);

	//cudaMemcpy(dev_gosa, gosa, sizeof(float), cudaMemcpyHostToDevice);
	/************************************/

	printf("mimax = %d mjmax = %d mkmax = %d\n", MIMAX, MJMAX, MKMAX);
	printf("imax = %d jmax = %d kmax = %d\n", imax, jmax, kmax);

	cpu0 = second(); /**measuring**/

	dim3 block(BLOCKSIZEX, BLOCKSIZEY, 1);
	dim3 grid(GRIDSIZEX, GRIDSIZEY, 1);

	jacobi<<<grid, block, sizeof(float) * BLOCKSIZE * 6>>>(dev_a0, dev_a1, dev_a2, dev_a3, dev_b0, dev_b1, dev_b2, dev_c0, dev_c1, dev_c2, dev_p, dev_wrk1, dev_wrk2, dev_bnd, NN, mimax, mjmax, mkmax, omega, dev_gosa);

	hipDeviceSynchronize();

	cpu1 = second();

	hipMemcpy(&gosa, dev_gosa, sizeof(float)*THREAD_NUM, hipMemcpyDeviceToHost);

	/******Free mem on the GPU**********/
	hipFree(dev_a0);
	hipFree(dev_a1);
	hipFree(dev_a2);
	hipFree(dev_a3);
	hipFree(dev_b0);
	hipFree(dev_b1);
	hipFree(dev_b2);
	hipFree(dev_c0);
	hipFree(dev_c1);
	hipFree(dev_c2);
	hipFree(dev_p);
	hipFree(dev_wrk1);
	hipFree(dev_wrk2);
	hipFree(dev_bnd);

	hipFree(dev_gosa);
	/************************************/

	/********Final sum of gosa***********/
	for(int gosa_index=0; gosa_index<THREAD_NUM; gosa_index++){
		//printf("%f\n", gosa[gosa_index]);
		final_gosa += gosa[gosa_index];
		//printf("Gosa%d: %e \n", gosa_index, gosa[gosa_index]);
	}
	/************************************/

	nflop = (kmax-2)*(jmax-2)*(imax-2)*34;

	if(cpu1 != 0.0){
		xmflops2 = nflop/cpu1*1.0e-6*(float)NN;
	}

	score = xmflops2/32.27;

	printf("gpu: %f sec.\n", cpu1);
	printf("Loop executed for %d times\n", NN);
	printf("Gosa: %e \n", final_gosa);
	//printf("MFLOPS measured: %f\n", xmflops2);
	//printf("Score: %f\n", score);

	return(0);
}

	.text
	.file	"himeno_temporal_blocking2.hip"
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z6secondv
.LCPI0_0:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	_Z6secondv
	.type	_Z6secondv,@function
_Z6secondv:                             # @_Z6secondv
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -16
	movq	%rsp, %rbx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movslq	_ZZ6secondvE8base_sec(%rip), %rcx
	movslq	_ZZ6secondvE9base_usec(%rip), %rax
	movq	(%rbx), %rdx
	movl	%eax, %esi
	orl	%ecx, %esi
	jne	.LBB0_2
# %bb.1:
	movl	%edx, _ZZ6secondvE8base_sec(%rip)
	movl	8(%rsp), %eax
	movl	%eax, _ZZ6secondvE9base_usec(%rip)
	xorpd	%xmm0, %xmm0
	jmp	.LBB0_3
.LBB0_2:
	subq	%rcx, %rdx
	cvtsi2sd	%rdx, %xmm1
	movq	8(%rsp), %rcx
	subq	%rax, %rcx
	cvtsi2sd	%rcx, %xmm0
	divsd	.LCPI0_0(%rip), %xmm0
	addsd	%xmm1, %xmm0
.LBB0_3:
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z6secondv, .Lfunc_end0-_Z6secondv
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_ # -- Begin function _Z21__device_stub__jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_
	.type	_Z21__device_stub__jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_,@function
_Z21__device_stub__jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_: # @_Z21__device_stub__jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$272, %rsp                      # imm = 0x110
	.cfi_def_cfa_offset 320
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %r10
	movq	%rdi, (%r10)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	12(%rsp), %rax
	movss	%xmm0, (%rax)
	leaq	112(%rsp), %rbx
	movq	%r10, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	320(%rsp), %rcx
	movq	%rcx, 48(%rbx)
	leaq	328(%rsp), %rcx
	movq	%rcx, 56(%rbx)
	leaq	336(%rsp), %rcx
	movq	%rcx, 64(%rbx)
	leaq	344(%rsp), %rcx
	movq	%rcx, 72(%rbx)
	leaq	352(%rsp), %rcx
	movq	%rcx, 80(%rbx)
	leaq	360(%rsp), %rcx
	movq	%rcx, 88(%rbx)
	leaq	368(%rsp), %rcx
	movq	%rcx, 96(%rbx)
	leaq	376(%rsp), %rcx
	movq	%rcx, 104(%rbx)
	leaq	384(%rsp), %rcx
	movq	%rcx, 112(%rbx)
	leaq	392(%rsp), %rcx
	movq	%rcx, 120(%rbx)
	leaq	400(%rsp), %rcx
	movq	%rcx, 128(%rbx)
	leaq	408(%rsp), %rcx
	movq	%rcx, 136(%rbx)
	movq	%rax, 144(%rbx)
	leaq	416(%rsp), %rax
	movq	%rax, 152(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$288, %rsp                      # imm = 0x120
	.cfi_adjust_cfa_offset -288
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z21__device_stub__jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_, .Lfunc_end1-_Z21__device_stub__jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI2_0:
	.long	0x41c80000                      # float 25
.LCPI2_1:
	.long	0x3f4ccccd                      # float 0.800000011
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$2024, %rsp                     # imm = 0x7E8
	.cfi_def_cfa_offset 2080
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$4704, %edi                     # imm = 0x1260
	callq	malloc
	movq	%rax, 136(%rsp)                 # 8-byte Spill
	movl	$4704, %edi                     # imm = 0x1260
	callq	malloc
	movq	%rax, 144(%rsp)                 # 8-byte Spill
	movl	$4704, %edi                     # imm = 0x1260
	callq	malloc
	movq	%rax, 152(%rsp)                 # 8-byte Spill
	movl	$4704, %edi                     # imm = 0x1260
	callq	malloc
	movq	%rax, %rbp
	movl	$1, %edi
	movl	$4704, %esi                     # imm = 0x1260
	callq	calloc@PLT
	movq	%rax, 168(%rsp)                 # 8-byte Spill
	movl	$1, %edi
	movl	$4704, %esi                     # imm = 0x1260
	callq	calloc@PLT
	movq	%rax, 176(%rsp)                 # 8-byte Spill
	movl	$1, %edi
	movl	$4704, %esi                     # imm = 0x1260
	callq	calloc@PLT
	movq	%rax, 184(%rsp)                 # 8-byte Spill
	movl	$4704, %edi                     # imm = 0x1260
	callq	malloc
	movq	%rax, %r13
	movl	$4704, %edi                     # imm = 0x1260
	callq	malloc
	movq	%rax, %r12
	movl	$4704, %edi                     # imm = 0x1260
	callq	malloc
	movq	%rax, %r15
	movl	$4704, %edi                     # imm = 0x1260
	callq	malloc
	movq	%rax, %rbx
	movl	$1, %edi
	movl	$4704, %esi                     # imm = 0x1260
	callq	calloc@PLT
	movq	%rax, 208(%rsp)                 # 8-byte Spill
	movl	$10368, %edi                    # imm = 0x2880
	callq	malloc
	movq	%rax, 216(%rsp)                 # 8-byte Spill
	movl	$4704, %edi                     # imm = 0x1260
	callq	malloc
	movq	%rax, %r14
	leaq	120(%rsp), %rdi
	movl	$4704, %esi                     # imm = 0x1260
	callq	hipMalloc
	leaq	112(%rsp), %rdi
	movl	$4704, %esi                     # imm = 0x1260
	callq	hipMalloc
	leaq	104(%rsp), %rdi
	movl	$4704, %esi                     # imm = 0x1260
	callq	hipMalloc
	leaq	96(%rsp), %rdi
	movl	$4704, %esi                     # imm = 0x1260
	callq	hipMalloc
	leaq	88(%rsp), %rdi
	movl	$4704, %esi                     # imm = 0x1260
	callq	hipMalloc
	leaq	80(%rsp), %rdi
	movl	$4704, %esi                     # imm = 0x1260
	callq	hipMalloc
	leaq	72(%rsp), %rdi
	movl	$4704, %esi                     # imm = 0x1260
	callq	hipMalloc
	leaq	64(%rsp), %rdi
	movl	$4704, %esi                     # imm = 0x1260
	callq	hipMalloc
	leaq	56(%rsp), %rdi
	movl	$4704, %esi                     # imm = 0x1260
	callq	hipMalloc
	leaq	48(%rsp), %rdi
	movl	$4704, %esi                     # imm = 0x1260
	callq	hipMalloc
	leaq	128(%rsp), %rdi
	movl	$4704, %esi                     # imm = 0x1260
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movl	$4704, %esi                     # imm = 0x1260
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movl	$4704, %esi                     # imm = 0x1260
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$10368, %esi                    # imm = 0x2880
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$1728, %esi                     # imm = 0x6C0
	callq	hipMalloc
	xorl	%eax, %eax
	movss	.LCPI2_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movl	$1065353216, %ecx               # imm = 0x3F800000
	movq	%r14, 232(%rsp)                 # 8-byte Spill
	movq	%rbx, 240(%rsp)                 # 8-byte Spill
	movq	%rbx, %rdi
	movq	%r15, 224(%rsp)                 # 8-byte Spill
	movq	%r15, %r8
	movq	%r12, 200(%rsp)                 # 8-byte Spill
	movq	%r12, %r9
	movq	%r13, 192(%rsp)                 # 8-byte Spill
	movq	%r13, %r10
	movq	%rbp, 160(%rsp)                 # 8-byte Spill
	movq	%rbp, %r11
	movq	152(%rsp), %rbx                 # 8-byte Reload
	movq	144(%rsp), %rdx                 # 8-byte Reload
	movq	136(%rsp), %rbp                 # 8-byte Reload
.LBB2_1:                                # %.preheader140
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_2 Depth 2
                                        #       Child Loop BB2_3 Depth 3
	movl	%eax, %esi
	imull	%eax, %esi
	xorps	%xmm1, %xmm1
	cvtsi2ss	%esi, %xmm1
	divss	%xmm0, %xmm1
	movq	%r14, 8(%rsp)                   # 8-byte Spill
	movq	%r14, %rsi
	movq	%rdi, (%rsp)                    # 8-byte Spill
	movq	%r8, 280(%rsp)                  # 8-byte Spill
	movq	%r9, 272(%rsp)                  # 8-byte Spill
	movq	%r10, 264(%rsp)                 # 8-byte Spill
	movq	%r11, 256(%rsp)                 # 8-byte Spill
	movq	%rbx, 248(%rsp)                 # 8-byte Spill
	movq	%rdx, %r14
	movq	%rbp, %r15
	xorl	%r12d, %r12d
.LBB2_2:                                # %.preheader
                                        #   Parent Loop BB2_1 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB2_3 Depth 3
	xorl	%r13d, %r13d
.LBB2_3:                                #   Parent Loop BB2_1 Depth=1
                                        #     Parent Loop BB2_2 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movl	%ecx, (%r15,%r13)
	movl	%ecx, (%r14,%r13)
	movl	%ecx, (%rbx,%r13)
	movl	$1042983595, (%r11,%r13)        # imm = 0x3E2AAAAB
	movl	%ecx, (%r10,%r13)
	movl	%ecx, (%r9,%r13)
	movl	%ecx, (%r8,%r13)
	movss	%xmm1, (%rdi,%r13)
	movl	%ecx, (%rsi,%r13)
	addq	$4, %r13
	cmpq	$56, %r13
	jne	.LBB2_3
# %bb.4:                                #   in Loop: Header=BB2_2 Depth=2
	incq	%r12
	addq	$56, %r15
	addq	$56, %r14
	addq	$56, %rbx
	addq	$56, %r11
	addq	$56, %r10
	addq	$56, %r9
	addq	$56, %r8
	addq	$56, %rdi
	addq	$56, %rsi
	cmpq	$14, %r12
	jne	.LBB2_2
# %bb.5:                                #   in Loop: Header=BB2_1 Depth=1
	incq	%rax
	movl	$784, %esi                      # imm = 0x310
	addq	%rsi, %rbp
	addq	%rsi, %rdx
	movq	248(%rsp), %rbx                 # 8-byte Reload
	addq	%rsi, %rbx
	movq	256(%rsp), %r11                 # 8-byte Reload
	addq	%rsi, %r11
	movq	264(%rsp), %r10                 # 8-byte Reload
	addq	%rsi, %r10
	movq	272(%rsp), %r9                  # 8-byte Reload
	addq	%rsi, %r9
	movq	280(%rsp), %r8                  # 8-byte Reload
	addq	%rsi, %r8
	movq	(%rsp), %rdi                    # 8-byte Reload
	addq	%rsi, %rdi
	movq	8(%rsp), %r14                   # 8-byte Reload
	addq	%rsi, %r14
	cmpq	$6, %rax
	jne	.LBB2_1
# %bb.6:
	movq	120(%rsp), %rdi
	movl	$4704, %edx                     # imm = 0x1260
	movq	136(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	112(%rsp), %rdi
	movl	$4704, %edx                     # imm = 0x1260
	movq	144(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	104(%rsp), %rdi
	movl	$4704, %edx                     # imm = 0x1260
	movq	152(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	96(%rsp), %rdi
	movl	$4704, %edx                     # imm = 0x1260
	movq	160(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	88(%rsp), %rdi
	movl	$4704, %edx                     # imm = 0x1260
	movq	168(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	80(%rsp), %rdi
	movl	$4704, %edx                     # imm = 0x1260
	movq	176(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	72(%rsp), %rdi
	movl	$4704, %edx                     # imm = 0x1260
	movq	184(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	64(%rsp), %rdi
	movl	$4704, %edx                     # imm = 0x1260
	movq	192(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	56(%rsp), %rdi
	movl	$4704, %edx                     # imm = 0x1260
	movq	200(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	48(%rsp), %rdi
	movl	$4704, %edx                     # imm = 0x1260
	movq	224(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdi
	movl	$4704, %edx                     # imm = 0x1260
	movq	208(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	movl	$10368, %edx                    # imm = 0x2880
	movq	216(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rdi
	movl	$4704, %edx                     # imm = 0x1260
	movq	232(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	128(%rsp), %rdi
	movl	$4704, %edx                     # imm = 0x1260
	movq	240(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$14, %ebx
	movl	$.L.str, %edi
	movl	$6, %esi
	movl	$14, %edx
	movl	$14, %ecx
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.1, %edi
	movl	$5, %esi
	movl	$13, %edx
	movl	$13, %ecx
	xorl	%eax, %eax
	callq	printf
	callq	_Z6secondv
	movabsq	$25769803779, %rdi              # imm = 0x600000003
	movabsq	$17179869190, %rdx              # imm = 0x400000006
	movl	$576, %r8d                      # imm = 0x240
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_8
# %bb.7:
	movq	120(%rsp), %rdi
	movq	112(%rsp), %rsi
	movq	104(%rsp), %rdx
	movq	96(%rsp), %rcx
	movq	88(%rsp), %r8
	movq	80(%rsp), %r9
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movss	.LCPI2_1(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	pushq	24(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	$6
	.cfi_adjust_cfa_offset 8
	pushq	$3
	.cfi_adjust_cfa_offset 8
	pushq	88(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	80(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	96(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	200(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	128(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	144(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	176(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z21__device_stub__jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
.LBB2_8:
	callq	hipDeviceSynchronize
	callq	_Z6secondv
	movsd	%xmm0, 8(%rsp)                  # 8-byte Spill
	movq	16(%rsp), %rsi
	leaq	288(%rsp), %rdi
	movl	$1728, %edx                     # imm = 0x6C0
	movl	$2, %ecx
	callq	hipMemcpy
	movq	120(%rsp), %rdi
	callq	hipFree
	movq	112(%rsp), %rdi
	callq	hipFree
	movq	104(%rsp), %rdi
	callq	hipFree
	movq	96(%rsp), %rdi
	callq	hipFree
	movq	88(%rsp), %rdi
	callq	hipFree
	movq	80(%rsp), %rdi
	callq	hipFree
	movq	72(%rsp), %rdi
	callq	hipFree
	movq	64(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	128(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
                                        # implicit-def: $xmm0
.LBB2_9:                                # =>This Inner Loop Header: Depth=1
	addss	288(%rsp,%rax,4), %xmm0
	incq	%rax
	cmpq	$432, %rax                      # imm = 0x1B0
	jne	.LBB2_9
# %bb.10:
	movl	$.L.str.2, %edi
	movss	%xmm0, (%rsp)                   # 4-byte Spill
	movsd	8(%rsp), %xmm0                  # 8-byte Reload
                                        # xmm0 = mem[0],zero
	movb	$1, %al
	callq	printf
	movl	$.L.str.3, %edi
	movl	$3, %esi
	xorl	%eax, %eax
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rsp), %xmm0                   # 4-byte Folded Reload
	movl	$.L.str.4, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$2024, %rsp                     # imm = 0x7E8
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_ZZ6secondvE8base_sec,@object   # @_ZZ6secondvE8base_sec
	.local	_ZZ6secondvE8base_sec
	.comm	_ZZ6secondvE8base_sec,4,4
	.type	_ZZ6secondvE9base_usec,@object  # @_ZZ6secondvE9base_usec
	.local	_ZZ6secondvE9base_usec
	.comm	_ZZ6secondvE9base_usec,4,4
	.type	_Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_,@object # @_Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_
	.section	.rodata,"a",@progbits
	.globl	_Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_
	.p2align	3, 0x0
_Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_:
	.quad	_Z21__device_stub__jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_
	.size	_Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"mimax = %d mjmax = %d mkmax = %d\n"
	.size	.L.str, 34

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"imax = %d jmax = %d kmax = %d\n"
	.size	.L.str.1, 31

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"gpu: %f sec.\n"
	.size	.L.str.2, 14

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Loop executed for %d times\n"
	.size	.L.str.3, 28

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Gosa: %e \n"
	.size	.L.str.4, 11

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_"
	.size	.L__unnamed_1, 45

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.p2align	2                               ; -- Begin function __ockl_printf_append_string_n
	.type	__ockl_printf_append_string_n,@function
__ockl_printf_append_string_n:          ; @__ockl_printf_append_string_n
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	v_mov_b32_e32 v8, v0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[0:1], 0
	s_cbranch_scc0 .LBB0_87
; %bb.1:
	s_load_b64 s[2:3], s[8:9], 0x50
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	v_and_b32_e32 v0, -3, v8
	v_dual_mov_b32 v32, s1 :: v_dual_mov_b32 v11, 2
	v_dual_mov_b32 v31, s0 :: v_dual_mov_b32 v12, 1
	v_mov_b32_e32 v5, v1
	v_dual_mov_b32 v30, 0 :: v_dual_and_b32 v35, 2, v8
	v_mbcnt_lo_u32_b32 v36, -1, 0
	v_mov_b32_e32 v4, v0
	s_mov_b32 s11, 0
	s_mov_b32 s10, 0
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;     Child Loop BB0_13 Depth 2
                                        ;     Child Loop BB0_21 Depth 2
                                        ;     Child Loop BB0_29 Depth 2
                                        ;     Child Loop BB0_37 Depth 2
                                        ;     Child Loop BB0_45 Depth 2
                                        ;     Child Loop BB0_53 Depth 2
                                        ;     Child Loop BB0_61 Depth 2
                                        ;     Child Loop BB0_69 Depth 2
                                        ;     Child Loop BB0_75 Depth 2
                                        ;     Child Loop BB0_84 Depth 2
	v_cmp_gt_u64_e32 vcc_lo, 56, v[2:3]
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $sgpr4
	s_mov_b32 s0, exec_lo
	v_dual_cndmask_b32 v34, 0, v3 :: v_dual_cndmask_b32 v33, 56, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 8, v33
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB0_8
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	s_mov_b32 s6, exec_lo
	v_cmpx_ne_u32_e32 0, v33
	s_cbranch_execz .LBB0_7
; %bb.4:                                ; %.preheader31.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_lshlrev_b64 v[9:10], 3, v[33:34]
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v13, v31
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v14, v32
	s_mov_b64 s[4:5], 0
	s_mov_b32 s7, 0
.LBB0_5:                                ; %.preheader31
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v0, v[13:14], off
	v_mov_b32_e32 v16, s11
	v_add_co_u32 v13, vcc_lo, v13, 1
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v15, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[15:16], s4, v[15:16]
	s_add_u32 s4, s4, 8
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e64 s0, s4, v9
	v_or_b32_e32 v7, v16, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_or_b32_e32 v6, v15, v6
	s_or_b32 s7, s0, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_5
; %bb.6:                                ; %Flow172
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_7:                                ; %Flow174
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s4, 0
.LBB0_8:                                ; %Flow176
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v9, v31
	v_mov_b32_e32 v10, v32
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[6:7], v[31:32], off
	v_add_co_u32 v9, vcc_lo, v31, 8
	v_add_nc_u32_e32 v0, -8, v33
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v32, vcc_lo
.LBB0_10:                               ; %.loopexit32
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr13_vgpr14
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_16
; %bb.11:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v0
	s_cbranch_execz .LBB0_15
; %bb.12:                               ; %.preheader29.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s12, 0
	s_mov_b64 s[4:5], 0
.LBB0_13:                               ; %.preheader29
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v15, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v0
	global_load_u8 v15, v[15:16], off
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v16, s11 :: v_dual_and_b32 v15, 0xffff, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[15:16], s0, v[15:16]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s12, vcc_lo, s12
	v_or_b32_e32 v14, v16, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v13, v15, v13
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_13
; %bb.14:                               ; %Flow167
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
.LBB0_15:                               ; %Flow169
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr0
.LBB0_16:                               ; %Flow171
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v17, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[13:14], v[9:10], off
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_add_nc_u32_e32 v17, -8, v0
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
.LBB0_18:                               ; %.loopexit30
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v17
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_24
; %bb.19:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v17
	s_cbranch_execz .LBB0_23
; %bb.20:                               ; %.preheader27.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s12, 0
	s_mov_b64 s[4:5], 0
.LBB0_21:                               ; %.preheader27
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v18, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v17
	global_load_u8 v0, v[18:19], off
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v19, s11 :: v_dual_and_b32 v18, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[18:19], s0, v[18:19]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s12, vcc_lo, s12
	v_or_b32_e32 v16, v19, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v15, v18, v15
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_21
; %bb.22:                               ; %Flow162
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
.LBB0_23:                               ; %Flow164
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr17
.LBB0_24:                               ; %Flow166
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v0, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_26
; %bb.25:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[15:16], v[9:10], off
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_add_nc_u32_e32 v0, -8, v17
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
.LBB0_26:                               ; %.loopexit28
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr17_vgpr18
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_32
; %bb.27:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v0
	s_cbranch_execz .LBB0_31
; %bb.28:                               ; %.preheader25.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s12, 0
	s_mov_b64 s[4:5], 0
.LBB0_29:                               ; %.preheader25
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v19, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v20, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v0
	global_load_u8 v19, v[19:20], off
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v20, s11 :: v_dual_and_b32 v19, 0xffff, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[19:20], s0, v[19:20]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s12, vcc_lo, s12
	v_or_b32_e32 v18, v20, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v17, v19, v17
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_29
; %bb.30:                               ; %Flow157
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
.LBB0_31:                               ; %Flow159
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr0
.LBB0_32:                               ; %Flow161
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v21, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_34
; %bb.33:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[17:18], v[9:10], off
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_add_nc_u32_e32 v21, -8, v0
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
.LBB0_34:                               ; %.loopexit26
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v21
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_40
; %bb.35:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v21
	s_cbranch_execz .LBB0_39
; %bb.36:                               ; %.preheader23.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s12, 0
	s_mov_b64 s[4:5], 0
.LBB0_37:                               ; %.preheader23
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v22, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v23, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v21
	global_load_u8 v0, v[22:23], off
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v23, s11 :: v_dual_and_b32 v22, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[22:23], s0, v[22:23]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s12, vcc_lo, s12
	v_or_b32_e32 v20, v23, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v19, v22, v19
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_37
; %bb.38:                               ; %Flow152
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
.LBB0_39:                               ; %Flow154
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr21
.LBB0_40:                               ; %Flow156
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v0, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_42
; %bb.41:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[19:20], v[9:10], off
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_add_nc_u32_e32 v0, -8, v21
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
.LBB0_42:                               ; %.loopexit24
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr21_vgpr22
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_48
; %bb.43:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v0
	s_cbranch_execz .LBB0_47
; %bb.44:                               ; %.preheader21.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s12, 0
	s_mov_b64 s[4:5], 0
.LBB0_45:                               ; %.preheader21
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v23, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v24, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v0
	global_load_u8 v23, v[23:24], off
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v24, s11 :: v_dual_and_b32 v23, 0xffff, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[23:24], s0, v[23:24]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s12, vcc_lo, s12
	v_or_b32_e32 v22, v24, v22
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v21, v23, v21
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_45
; %bb.46:                               ; %Flow147
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
.LBB0_47:                               ; %Flow149
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr0
.LBB0_48:                               ; %Flow151
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v25, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_50
; %bb.49:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[21:22], v[9:10], off
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_add_nc_u32_e32 v25, -8, v0
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
.LBB0_50:                               ; %.loopexit22
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v25
	s_xor_b32 s4, exec_lo, s0
	s_cbranch_execz .LBB0_56
; %bb.51:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_mov_b32 s5, exec_lo
	v_cmpx_ne_u32_e32 0, v25
	s_cbranch_execz .LBB0_55
; %bb.52:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s6, 0
.LBB0_53:                               ; %.preheader
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v0, v[9:10], off
	v_mov_b32_e32 v27, s11
	v_add_nc_u32_e32 v25, -1, v25
	v_add_co_u32 v9, vcc_lo, v9, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v25
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v26, 0xffff, v0
	v_lshlrev_b64 v[26:27], s0, v[26:27]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v24, v27, v24
	v_or_b32_e32 v23, v26, v23
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_53
; %bb.54:                               ; %Flow142
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_55:                               ; %Flow144
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
                                        ; implicit-def: $vgpr9_vgpr10
.LBB0_56:                               ; %Flow146
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s0, s4
	s_cbranch_execz .LBB0_58
; %bb.57:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[23:24], v[9:10], off
.LBB0_58:                               ; %.loopexit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v29, v36
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v10, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v29
	v_cmp_eq_u32_e64 s0, s0, v29
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_64
; %bb.59:                               ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[27:28], v30, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[9:10], v30, s[2:3] offset:40
	global_load_b64 v[25:26], v30, s[2:3]
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v0, v10, v28
	v_and_b32_e32 v9, v9, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v0, v0, 24
	v_mul_hi_u32 v10, v9, 24
	v_mul_lo_u32 v9, v9, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, v10, v0
	s_waitcnt vmcnt(0)
	v_add_co_u32 v9, vcc_lo, v25, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, v26, v0, vcc_lo
	global_load_b64 v[25:26], v[9:10], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v30, v[25:28], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[9:10], v[27:28]
	s_cbranch_execz .LBB0_63
; %bb.60:                               ; %.preheader3.i.i19.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s5, 0
.LBB0_61:                               ; %.preheader3.i.i19
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[25:26], v30, s[2:3] offset:40
	global_load_b64 v[37:38], v30, s[2:3]
	v_dual_mov_b32 v28, v10 :: v_dual_mov_b32 v27, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v0, v25, v27
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[9:10], null, v0, 24, v[37:38]
	v_and_b32_e32 v37, v26, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v0, v10
	v_mad_u64_u32 v[25:26], null, v37, 24, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v10, v25
	global_load_b64 v[25:26], v[9:10], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v30, v[25:28], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[27:28]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_61
; %bb.62:                               ; %Flow139
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_63:                               ; %Flow141
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_64:                               ; %.loopexit4.i.i14
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[37:38], v30, s[2:3] offset:40
	global_load_b128 v[25:28], v30, s[2:3]
	v_readfirstlane_b32 s4, v9
	v_readfirstlane_b32 s5, v10
	s_mov_b32 s14, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v37
	v_readfirstlane_b32 s7, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s12, s6, 24
	s_mul_i32 s13, s6, 24
	s_and_saveexec_b32 s15, s0
	s_cbranch_execz .LBB0_66
; %bb.65:                               ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s16, s12, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v37, vcc_lo, v25, s13
	v_add_co_ci_u32_e32 v38, vcc_lo, s16, v26, vcc_lo
	v_dual_mov_b32 v9, s14 :: v_dual_mov_b32 v10, v30
	global_store_b128 v[37:38], v[9:12], off offset:8
.LBB0_66:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	v_cmp_lt_u64_e32 vcc_lo, 56, v[2:3]
	v_or_b32_e32 v0, 0, v5
	v_or_b32_e32 v9, v4, v35
	v_lshl_add_u32 v10, v33, 2, 28
	s_lshl_b64 s[6:7], s[6:7], 12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v5, v0, v5 :: v_dual_cndmask_b32 v0, v9, v4
	v_and_b32_e32 v4, 0x1e0, v10
	v_lshlrev_b64 v[9:10], 6, v[29:30]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v27, vcc_lo, v27, s6
	v_add_co_ci_u32_e32 v28, vcc_lo, s7, v28, vcc_lo
	v_and_or_b32 v4, 0xffffff1f, v0, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, v27, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, v28, v10, vcc_lo
	s_clause 0x3
	global_store_b128 v[9:10], v[4:7], off
	global_store_b128 v[9:10], v[13:16], off offset:16
	global_store_b128 v[9:10], v[17:20], off offset:32
	global_store_b128 v[9:10], v[21:24], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_74
; %bb.67:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x1
	global_load_b64 v[17:18], v30, s[2:3] offset:32 glc
	global_load_b64 v[4:5], v30, s[2:3] offset:40
	v_dual_mov_b32 v15, s4 :: v_dual_mov_b32 v16, s5
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v4
	v_readfirstlane_b32 s15, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[14:15], s[4:5]
	s_mul_i32 s7, s15, 24
	s_mul_hi_u32 s15, s14, 24
	s_mul_i32 s14, s14, 24
	s_add_i32 s15, s15, s7
	v_add_co_u32 v13, vcc_lo, v25, s14
	v_add_co_ci_u32_e32 v14, vcc_lo, s15, v26, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[13:14], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v30, v[15:18], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[6:7], v[17:18]
	s_cbranch_execz .LBB0_70
; %bb.68:                               ; %.preheader1.i.i17.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s14, 0
.LBB0_69:                               ; %.preheader1.i.i17
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
	s_sleep 1
	global_store_b64 v[13:14], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v30, v[4:7], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
	v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB0_69
.LBB0_70:                               ; %Flow137
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	global_load_b64 v[4:5], v30, s[2:3] offset:16
	s_mov_b32 s14, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v0, s14, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_72
; %bb.71:                               ;   in Loop: Header=BB0_2 Depth=1
	s_bcnt1_i32_b32 s14, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v29, s14
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[4:5], v[29:30], off offset:8
.LBB0_72:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[6:7], v[4:5], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	s_cbranch_vccnz .LBB0_74
; %bb.73:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v29, v[4:5], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v29
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[6:7], v[29:30], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_74:                               ; %Flow138
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s12, s12, s1
	v_add_co_u32 v0, vcc_lo, v25, s13
	v_add_co_ci_u32_e32 v5, vcc_lo, s12, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
.LBB0_75:                               ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v0, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_77
; %bb.76:                               ;   in Loop: Header=BB0_75 Depth=2
	global_load_b32 v0, v[4:5], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v0, 1, v0
.LBB0_77:                               ;   in Loop: Header=BB0_75 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v0
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_79
; %bb.78:                               ;   in Loop: Header=BB0_75 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_80
.LBB0_79:                               ;   in Loop: Header=BB0_75 Depth=2
	s_mov_b32 s1, -1
.LBB0_80:                               ; %Flow132
                                        ;   in Loop: Header=BB0_75 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_75
; %bb.81:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b128 v[4:7], v[9:10], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_85
; %bb.82:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x2
	global_load_b64 v[6:7], v30, s[2:3] offset:40
	global_load_b64 v[9:10], v30, s[2:3] offset:24 glc
	global_load_b64 v[15:16], v30, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v0, vcc_lo, v6, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v0, s4
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	v_dual_cndmask_b32 v14, v14, v17 :: v_dual_cndmask_b32 v13, v13, v0
	v_and_b32_e32 v0, v14, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v13, v6
	v_mul_hi_u32 v7, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, vcc_lo, v15, v6
	v_mov_b32_e32 v15, v9
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v0, v7, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, v16, v0, vcc_lo
	v_mov_b32_e32 v16, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v30, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[15:16], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_85
; %bb.83:                               ; %.preheader.i.i16.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
.LBB0_84:                               ; %.preheader.i.i16
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[6:7], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v30, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[15:16]
	v_dual_mov_b32 v16, v10 :: v_dual_mov_b32 v15, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_84
.LBB0_85:                               ; %__ockl_hostcall_preview.exit20
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_sub_co_u32 v2, vcc_lo, v2, v33
	v_sub_co_ci_u32_e32 v3, vcc_lo, v3, v34, vcc_lo
	v_add_co_u32 v31, s0, v31, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v32, s0, v32, v34, s0
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_2
; %bb.86:                               ; %Flow177
	s_or_b32 exec_lo, exec_lo, s10
	s_mov_b32 s0, 0
	s_branch .LBB0_88
.LBB0_87:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr4_vgpr5
.LBB0_88:                               ; %Flow192
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_117
; %bb.89:
	s_load_b64 s[2:3], s[8:9], 0x50
	v_mbcnt_lo_u32_b32 v2, -1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s0, v2
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v10, 0
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_95
; %bb.90:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[5:6], v0, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v0, s[2:3] offset:40
	global_load_b64 v[9:10], v0, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v7, v3, 24
	v_mul_lo_u32 v4, v4, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v7, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v9, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v10, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v0, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[9:10], v[5:6]
	s_cbranch_execz .LBB0_94
; %bb.91:                               ; %.preheader3.i.i.preheader
	s_mov_b32 s5, 0
.LBB0_92:                               ; %.preheader3.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[3:4], v0, s[2:3] offset:40
	global_load_b64 v[11:12], v0, s[2:3]
	v_dual_mov_b32 v5, v9 :: v_dual_mov_b32 v6, v10
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, v3, v5
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[9:10], null, v3, 24, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v3, v10 :: v_dual_and_b32 v4, v4, v6
	v_mad_u64_u32 v[10:11], null, v4, 24, v[3:4]
	global_load_b64 v[3:4], v[9:10], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v0, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[5:6]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_92
; %bb.93:                               ; %Flow189
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_94:                               ; %Flow191
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_95:                               ; %.loopexit4.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s4, v9
	v_readfirstlane_b32 s5, v10
	s_mov_b32 s10, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[11:12], v3, s[2:3] offset:40
	global_load_b128 v[4:7], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v11
	v_readfirstlane_b32 s7, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB0_97
; %bb.96:
	s_add_i32 s12, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v13, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v14, vcc_lo, s12, v5, vcc_lo
	v_dual_mov_b32 v9, s10 :: v_dual_mov_b32 v10, v3
	v_dual_mov_b32 v11, 2 :: v_dual_mov_b32 v12, 1
	global_store_b128 v[13:14], v[9:12], off offset:8
.LBB0_97:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[9:10], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v9
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v0, 0xffffff1f, v8, 32
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v10, vcc_lo
	v_mov_b32_e32 v2, v3
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v11, s15
	v_dual_mov_b32 v9, s13 :: v_dual_mov_b32 v10, s14
	s_clause 0x3
	global_store_b128 v[6:7], v[0:3], off
	global_store_b128 v[6:7], v[8:11], off offset:16
	global_store_b128 v[6:7], v[8:11], off offset:32
	global_store_b128 v[6:7], v[8:11], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_105
; %bb.98:
	v_mov_b32_e32 v10, 0
	s_mov_b32 s7, exec_lo
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v10, s[2:3] offset:40
	v_dual_mov_b32 v11, s4 :: v_dual_mov_b32 v12, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, s5, v1
	v_and_b32_e32 v0, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v2, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v2, v1
	v_add_co_u32 v8, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v5, v1, vcc_lo
	global_store_b64 v[8:9], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[13:14]
	s_cbranch_execz .LBB0_101
; %bb.99:                               ; %.preheader1.i.i.preheader
	s_mov_b32 s10, 0
.LBB0_100:                              ; %.preheader1.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[8:9], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_100
.LBB0_101:                              ; %Flow187
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s10, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_103
; %bb.102:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_103:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB0_105
; %bb.104:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_105:                              ; %Flow188
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_106:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_108
; %bb.107:                              ;   in Loop: Header=BB0_106 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_108:                              ;   in Loop: Header=BB0_106 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_110
; %bb.109:                              ;   in Loop: Header=BB0_106 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_111
.LBB0_110:                              ;   in Loop: Header=BB0_106 Depth=1
	s_mov_b32 s1, -1
.LBB0_111:                              ; %Flow182
                                        ;   in Loop: Header=BB0_106 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_106
; %bb.112:
	global_load_b128 v[4:7], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_116
; %bb.113:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[2:3], v8, s[2:3] offset:40
	global_load_b64 v[9:10], v8, s[2:3] offset:24 glc
	global_load_b64 v[6:7], v8, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v12 :: v_dual_cndmask_b32 v0, v0, v11
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v0, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v11, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v2
	v_mov_b32_e32 v2, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v3, vcc_lo
	v_mov_b32_e32 v3, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v8, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_116
; %bb.114:                              ; %.preheader.i.i.preheader
	s_mov_b32 s0, 0
.LBB0_115:                              ; %.preheader.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[2:3]
	v_dual_mov_b32 v2, v9 :: v_dual_mov_b32 v3, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_115
.LBB0_116:                              ; %__ockl_hostcall_preview.exit
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_117:                              ; %.loopexit33
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
	s_waitcnt lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end0:
	.size	__ockl_printf_append_string_n, .Lfunc_end0-__ockl_printf_append_string_n
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 4464
; NumSgprs: 34
; NumVgprs: 39
; ScratchSize: 0
; MemoryBound: 0
	.text
	.protected	_Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_ ; -- Begin function _Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_
	.globl	_Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_
	.p2align	8
	.type	_Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_,@function
_Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_: ; @_Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_
; %bb.0:
	s_mov_b64 s[18:19], s[0:1]
	s_load_b32 s0, s[0:1], 0x9c
	s_load_b128 s[52:55], s[18:19], 0x70
	s_add_u32 s34, s18, 0x90
	v_and_b32_e32 v1, 0x3ff, v0
	s_addc_u32 s35, s19, 0
	v_bfe_u32 v0, v0, 10, 10
	s_mov_b32 s4, 1
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s0, 0xffff
	s_lshr_b32 s5, s0, 16
	s_add_i32 s0, s3, -2
	s_add_i32 s1, s5, -2
	v_mad_u64_u32 v[47:48], null, s0, s14, v[1:2]
	v_mad_u64_u32 v[48:49], null, s1, s15, v[0:1]
	s_cmp_lt_i32 s52, 1
	s_cbranch_scc1 .LBB1_124
; %bb.1:                                ; %.lr.ph1093
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v45, 2 :: v_dual_add_nc_u32 v6, 1, v48
	s_add_i32 s62, s53, -1
	v_mul_u32_u24_e32 v2, s3, v0
	s_mul_i32 s6, s62, s54
	v_mul_lo_u32 v119, v6, s55
	s_mul_i32 s33, s55, s54
	s_mul_i32 s7, s6, s55
	s_mul_i32 s9, s33, s53
	v_add_nc_u32_e32 v120, 1, v47
	v_add_lshl_u32 v2, v2, v1, 2
	s_mul_i32 s0, s5, s3
	s_clause 0x3
	s_load_b512 s[36:51], s[18:19], 0x0
	s_load_b32 s17, s[18:19], 0x80
	s_load_b128 s[56:59], s[18:19], 0x60
	s_load_b256 s[20:27], s[18:19], 0x40
	v_add_nc_u32_e32 v10, s7, v119
	v_dual_mov_b32 v40, 33 :: v_dual_add_nc_u32 v11, s9, v119
	s_lshl_b32 s0, s0, 2
	v_dual_mov_b32 v42, 0 :: v_dual_add_nc_u32 v123, s55, v119
	v_add3_u32 v126, 0, s0, v2
	v_add_nc_u32_e32 v2, v10, v120
	s_cmp_gt_i32 s53, 3
	v_add_nc_u32_e32 v4, v11, v120
	s_cselect_b32 s63, -1, 0
	v_cmp_ne_u32_e32 vcc_lo, 0, v1
	v_cmp_ne_u32_e64 s2, 0, v0
	s_add_i32 s3, s3, -1
	v_ashrrev_i32_e32 v3, 31, v2
	v_cmp_gt_u32_e64 s3, s3, v1
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_nc_u32_e32 v12, s7, v123
	s_and_b32 s2, vcc_lo, s2
	s_add_i32 s5, s5, -1
	s_and_b32 s10, s2, s3
	v_cmp_gt_u32_e64 s3, s5, v0
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	v_add_nc_u32_e32 v4, v12, v120
	v_add_nc_u32_e32 v122, 2, v47
	s_and_b32 s53, s10, s3
	s_add_i32 s8, s54, -1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v49, s3, s36, v0
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_co_ci_u32_e64 v50, s3, s37, v1, s3
	v_add_co_u32 v51, s3, s56, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v52, s3, s57, v3, s3
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	v_add_co_u32 v53, s3, s38, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v54, s3, s39, v1, s3
	v_add_nc_u32_e32 v4, v10, v122
	v_add_co_u32 v55, s3, s56, v2
	v_mul_lo_u32 v121, v48, s55
	v_cmp_gt_i32_e64 s2, s8, v6
	v_add_nc_u32_e32 v6, s9, v120
	v_add_co_ci_u32_e64 v56, s3, s57, v3, s3
	v_add_co_u32 v57, s3, s40, v0
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_co_ci_u32_e64 v58, s3, s41, v1, s3
	s_sub_i32 s3, s6, s54
	v_add_nc_u32_e32 v2, v6, v123
	s_mul_i32 s5, s3, s55
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_nc_u32_e32 v6, v6, v121
	v_add_nc_u32_e32 v8, s5, v120
	v_ashrrev_i32_e32 v3, 31, v2
	v_add_nc_u32_e32 v13, s7, v121
	s_add_i32 s0, s55, -1
	v_add_co_u32 v59, s3, s56, v4
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_nc_u32_e32 v4, v8, v123
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_nc_u32_e32 v8, v8, v121
	v_add_co_ci_u32_e64 v60, s3, s57, v5, s3
	v_add_co_u32 v61, s3, s44, v0
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_co_ci_u32_e64 v62, s3, s45, v1, s3
	v_add_co_u32 v63, s3, s56, v2
	v_ashrrev_i32_e32 v9, 31, v8
	v_add_co_ci_u32_e64 v64, s3, s57, v3, s3
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	v_add_co_u32 v65, s3, s56, v6
	v_add_nc_u32_e32 v6, v12, v122
	v_lshlrev_b64 v[4:5], 2, v[8:9]
	v_add_co_ci_u32_e64 v66, s3, s57, v7, s3
	v_add_co_u32 v67, s3, s56, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_nc_u32_e32 v2, v13, v122
	v_add_co_ci_u32_e64 v68, s3, s57, v3, s3
	v_add_co_u32 v69, s3, s56, v4
	v_add_co_ci_u32_e64 v70, s3, s57, v5, s3
	v_lshlrev_b64 v[4:5], 2, v[6:7]
	v_ashrrev_i32_e32 v3, 31, v2
	v_add_nc_u32_e32 v6, v13, v47
	v_add_nc_u32_e32 v8, v12, v47
	v_add_co_u32 v71, s3, s46, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_co_ci_u32_e64 v72, s3, s47, v1, s3
	v_add_co_u32 v73, s3, s56, v4
	v_ashrrev_i32_e32 v9, 31, v8
	v_add_co_ci_u32_e64 v74, s3, s57, v5, s3
	v_lshlrev_b64 v[4:5], 2, v[6:7]
	v_add_co_u32 v75, s3, s56, v2
	v_add_nc_u32_e32 v6, v11, v122
	v_add_nc_u32_e32 v12, s5, v119
	v_add_co_ci_u32_e64 v76, s3, s57, v3, s3
	v_lshlrev_b64 v[2:3], 2, v[8:9]
	v_add_co_u32 v77, s3, s56, v4
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_nc_u32_e32 v4, v12, v122
	v_add_co_ci_u32_e64 v78, s3, s57, v5, s3
	v_add_co_u32 v79, s3, s56, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v80, s3, s57, v3, s3
	v_lshlrev_b64 v[2:3], 2, v[6:7]
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_nc_u32_e32 v6, v11, v47
	v_add_nc_u32_e32 v8, v12, v47
	v_add_co_u32 v81, s3, s48, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_co_ci_u32_e64 v82, s3, s49, v1, s3
	v_add_co_u32 v83, s3, s56, v2
	v_ashrrev_i32_e32 v9, 31, v8
	v_add_co_ci_u32_e64 v84, s3, s57, v3, s3
	v_lshlrev_b64 v[2:3], 2, v[6:7]
	v_add_co_u32 v85, s3, s56, v4
	v_add_nc_u32_e32 v6, v12, v120
	v_add_co_ci_u32_e64 v86, s3, s57, v5, s3
	v_lshlrev_b64 v[4:5], 2, v[8:9]
	v_add_co_u32 v87, s3, s56, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_co_ci_u32_e64 v88, s3, s57, v3, s3
	v_add_co_u32 v89, s3, s56, v4
	v_add_nc_u32_e32 v4, v13, v120
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[2:3], 2, v[6:7]
	v_add_co_ci_u32_e64 v90, s3, s57, v5, s3
	v_add_co_u32 v91, s3, s50, v0
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_co_ci_u32_e64 v92, s3, s51, v1, s3
	v_add_co_u32 v93, s3, s56, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v94, s3, s57, v3, s3
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	v_add_nc_u32_e32 v4, v10, v47
	v_add_co_u32 v95, s3, s20, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v96, s3, s21, v1, s3
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_co_u32 v97, s3, s56, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v98, s3, s57, v3, s3
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	v_add_co_u32 v99, s3, s22, v0
	v_cmp_gt_i32_e64 s0, s0, v120
	v_add_co_ci_u32_e64 v100, s3, s23, v1, s3
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v101, s3, s56, v2
	v_cmp_gt_u32_e64 s1, 0x7fffffff, v48
	v_add_co_ci_u32_e64 v102, s3, s57, v3, s3
	v_add_co_u32 v103, s3, s26, v0
	s_and_b32 s0, vcc_lo, s0
	v_add_co_ci_u32_e64 v104, s3, s27, v1, s3
	s_and_b32 s3, s0, s1
	v_add_co_u32 v105, vcc_lo, s42, v0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	s_and_b32 s54, s3, s2
	v_add_co_ci_u32_e32 v106, vcc_lo, s43, v1, vcc_lo
	s_cmp_lg_u64 s[0:1], 0
	v_add_co_u32 v107, vcc_lo, s56, v0
	s_cselect_b32 s0, -1, 0
	v_add_co_ci_u32_e32 v108, vcc_lo, s57, v1, vcc_lo
	v_add_co_u32 v109, vcc_lo, s58, v0
	v_cndmask_b32_e64 v2, 0, 1, s0
	v_add_co_ci_u32_e32 v110, vcc_lo, s59, v1, vcc_lo
	v_add_co_u32 v111, vcc_lo, s24, v0
	v_add_nc_u32_e32 v124, v121, v120
	v_dual_mov_b32 v46, 1 :: v_dual_add_nc_u32 v125, v123, v120
	v_add_co_ci_u32_e32 v112, vcc_lo, s25, v1, vcc_lo
	v_lshlrev_b32_e32 v39, 2, v2
	v_mbcnt_lo_u32_b32 v127, -1, 0
	s_mov_b32 s28, 0
	s_lshl_b32 s64, s33, 1
	s_mov_b32 s65, 0
.LBB1_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_4 Depth 2
                                        ;       Child Loop BB1_7 Depth 3
                                        ;       Child Loop BB1_15 Depth 3
                                        ;       Child Loop BB1_21 Depth 3
                                        ;       Child Loop BB1_30 Depth 3
                                        ;       Child Loop BB1_34 Depth 3
                                        ;       Child Loop BB1_42 Depth 3
                                        ;       Child Loop BB1_48 Depth 3
                                        ;       Child Loop BB1_57 Depth 3
                                        ;       Child Loop BB1_65 Depth 3
                                        ;       Child Loop BB1_73 Depth 3
                                        ;       Child Loop BB1_79 Depth 3
                                        ;       Child Loop BB1_88 Depth 3
                                        ;       Child Loop BB1_92 Depth 3
                                        ;       Child Loop BB1_100 Depth 3
                                        ;       Child Loop BB1_106 Depth 3
                                        ;       Child Loop BB1_115 Depth 3
	s_mul_i32 s0, s33, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v18, s0, v119
	s_add_i32 s1, s0, s33
	v_add_nc_u32_e32 v19, s0, v123
	v_add_nc_u32_e32 v20, s1, v119
	v_add_nc_u32_e32 v28, s0, v121
	v_add_nc_u32_e32 v0, v18, v120
	v_add_nc_u32_e32 v6, v18, v122
	v_add_nc_u32_e32 v2, v19, v120
	v_add_nc_u32_e32 v4, v20, v120
	v_add_nc_u32_e32 v16, v28, v47
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v17, 31, v16
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s36, v0
	v_add_co_ci_u32_e32 v8, vcc_lo, s37, v1, vcc_lo
	v_add_co_u32 v9, vcc_lo, s38, v0
	v_add_co_ci_u32_e32 v10, vcc_lo, s39, v1, vcc_lo
	global_load_b32 v21, v[7:8], off
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_co_u32 v4, vcc_lo, s24, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s25, v5, vcc_lo
	v_add_co_u32 v2, vcc_lo, s24, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_ci_u32_e32 v3, vcc_lo, s25, v3, vcc_lo
	v_add_co_u32 v11, vcc_lo, s40, v0
	v_add_co_ci_u32_e32 v12, vcc_lo, s41, v1, vcc_lo
	global_load_b32 v22, v[4:5], off
	global_load_b32 v23, v[9:10], off
	global_load_b32 v24, v[2:3], off
	global_load_b32 v25, v[11:12], off
	v_add_co_u32 v2, vcc_lo, s24, v6
	v_add_nc_u32_e32 v4, s1, v125
	v_add_nc_u32_e32 v6, s1, v124
	v_add_co_ci_u32_e32 v3, vcc_lo, s25, v7, vcc_lo
	s_sub_i32 s1, s1, s64
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v5, 31, v4
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_nc_u32_e32 v10, s1, v125
	v_add_co_u32 v8, vcc_lo, s44, v0
	global_load_b32 v26, v[2:3], off
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	v_lshlrev_b64 v[4:5], 2, v[6:7]
	v_add_nc_u32_e32 v6, s1, v124
	v_add_co_ci_u32_e32 v9, vcc_lo, s45, v1, vcc_lo
	v_ashrrev_i32_e32 v11, 31, v10
	v_add_co_u32 v2, vcc_lo, s24, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v7, 31, v6
	global_load_b32 v27, v[8:9], off
	v_lshlrev_b64 v[8:9], 2, v[10:11]
	v_add_co_ci_u32_e32 v3, vcc_lo, s25, v3, vcc_lo
	v_add_co_u32 v4, vcc_lo, s24, v4
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_nc_u32_e32 v10, v19, v122
	v_add_co_ci_u32_e32 v5, vcc_lo, s25, v5, vcc_lo
	v_add_co_u32 v8, vcc_lo, s24, v8
	v_add_nc_u32_e32 v12, v28, v122
	v_add_co_ci_u32_e32 v9, vcc_lo, s25, v9, vcc_lo
	v_add_co_u32 v6, vcc_lo, s24, v6
	v_ashrrev_i32_e32 v11, 31, v10
	v_add_co_ci_u32_e32 v7, vcc_lo, s25, v7, vcc_lo
	v_ashrrev_i32_e32 v13, 31, v12
	s_clause 0x3
	global_load_b32 v29, v[2:3], off
	global_load_b32 v30, v[4:5], off
	global_load_b32 v31, v[8:9], off
	global_load_b32 v32, v[6:7], off
	v_add_nc_u32_e32 v6, v19, v47
	v_lshlrev_b64 v[2:3], 2, v[10:11]
	v_add_co_u32 v14, vcc_lo, s46, v0
	v_lshlrev_b64 v[4:5], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_co_ci_u32_e32 v15, vcc_lo, s47, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s24, v2
	v_lshlrev_b64 v[8:9], 2, v[16:17]
	v_add_co_ci_u32_e32 v3, vcc_lo, s25, v3, vcc_lo
	v_add_nc_u32_e32 v19, s1, v119
	v_add_co_u32 v4, vcc_lo, s24, v4
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_nc_u32_e32 v10, v20, v122
	v_add_co_ci_u32_e32 v5, vcc_lo, s25, v5, vcc_lo
	v_add_co_u32 v8, vcc_lo, s24, v8
	v_add_nc_u32_e32 v12, v19, v122
	v_add_co_ci_u32_e32 v9, vcc_lo, s25, v9, vcc_lo
	v_add_co_u32 v6, vcc_lo, s24, v6
	v_ashrrev_i32_e32 v11, 31, v10
	v_add_nc_u32_e32 v16, v20, v47
	v_add_co_ci_u32_e32 v7, vcc_lo, s25, v7, vcc_lo
	v_ashrrev_i32_e32 v13, 31, v12
	global_load_b32 v33, v[14:15], off
	s_clause 0x3
	global_load_b32 v20, v[2:3], off
	global_load_b32 v34, v[4:5], off
	global_load_b32 v35, v[8:9], off
	global_load_b32 v36, v[6:7], off
	v_add_nc_u32_e32 v6, v19, v47
	v_lshlrev_b64 v[2:3], 2, v[10:11]
	v_ashrrev_i32_e32 v17, 31, v16
	v_add_co_u32 v14, vcc_lo, s48, v0
	v_lshlrev_b64 v[4:5], 2, v[12:13]
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_co_ci_u32_e32 v15, vcc_lo, s49, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s24, v2
	v_lshlrev_b64 v[8:9], 2, v[16:17]
	v_add_co_ci_u32_e32 v3, vcc_lo, s25, v3, vcc_lo
	v_add_co_u32 v4, vcc_lo, s24, v4
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_ci_u32_e32 v5, vcc_lo, s25, v5, vcc_lo
	v_add_nc_u32_e32 v10, v19, v120
	v_add_co_u32 v8, vcc_lo, s24, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s25, v9, vcc_lo
	v_add_co_u32 v6, vcc_lo, s24, v6
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v11, 31, v10
	global_load_b32 v37, v[14:15], off
	v_add_co_ci_u32_e32 v7, vcc_lo, s25, v7, vcc_lo
	v_add_nc_u32_e32 v14, v28, v120
	v_add_co_u32 v12, vcc_lo, s50, v0
	v_add_co_ci_u32_e32 v13, vcc_lo, s51, v1, vcc_lo
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_clause 0x3
	global_load_b32 v16, v[2:3], off
	global_load_b32 v17, v[4:5], off
	global_load_b32 v19, v[8:9], off
	global_load_b32 v28, v[6:7], off
	global_load_b32 v12, v[12:13], off
	v_ashrrev_i32_e32 v15, 31, v14
	v_add_nc_u32_e32 v6, v18, v47
	v_add_co_u32 v2, vcc_lo, s24, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[4:5], 2, v[14:15]
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_co_ci_u32_e32 v3, vcc_lo, s25, v11, vcc_lo
	v_add_co_u32 v8, vcc_lo, s20, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s21, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s24, v4
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_ci_u32_e32 v5, vcc_lo, s25, v5, vcc_lo
	v_add_co_u32 v10, vcc_lo, s22, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, s23, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, s24, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s25, v7, vcc_lo
	global_load_b32 v13, v[2:3], off
	global_load_b32 v8, v[8:9], off
	global_load_b32 v9, v[4:5], off
	global_load_b32 v10, v[10:11], off
	global_load_b32 v11, v[6:7], off
	v_add_co_u32 v2, vcc_lo, s26, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s27, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s42, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s43, v1, vcc_lo
	v_add_co_u32 v6, vcc_lo, s24, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s25, v1, vcc_lo
	global_load_b32 v14, v[2:3], off
	global_load_b32 v4, v[4:5], off
	global_load_b32 v5, v[6:7], off
	v_add_co_u32 v2, vcc_lo, s58, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s59, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s56, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s57, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_and_not1_b32 vcc_lo, exec_lo, s63
	s_waitcnt vmcnt(27)
	v_mul_f32_e32 v6, v23, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v21, v22
	s_waitcnt vmcnt(25)
	v_fmac_f32_e32 v6, v25, v26
	s_waitcnt vmcnt(22)
	v_sub_f32_e32 v3, v29, v30
	s_waitcnt vmcnt(21)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v3, v3, v31
	s_waitcnt vmcnt(20)
	v_add_f32_e32 v3, v3, v32
	s_waitcnt vmcnt(17)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v6, v27, v3 :: v_dual_sub_f32 v7, v20, v34
	s_waitcnt vmcnt(16)
	v_sub_f32_e32 v7, v7, v35
	s_waitcnt vmcnt(15)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v7, v36
	s_waitcnt vmcnt(12)
	v_dual_fmac_f32 v6, v33, v7 :: v_dual_sub_f32 v15, v16, v17
	s_waitcnt vmcnt(11)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v15, v15, v19
	s_waitcnt vmcnt(10)
	v_add_f32_e32 v3, v15, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v37, v3
	s_waitcnt vmcnt(8)
	v_fmac_f32_e32 v6, v12, v13
	s_waitcnt vmcnt(6)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v8, v9
	s_waitcnt vmcnt(4)
	v_fmac_f32_e32 v6, v10, v11
	s_waitcnt vmcnt(3)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v14, v6
	s_waitcnt vmcnt(1)
	v_fma_f32 v3, v4, v3, -v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v2, v3
	v_fmac_f32_e32 v5, s17, v2
	v_mul_f32_e32 v128, v2, v2
	global_store_b32 v[0:1], v5, off
	s_cbranch_vccnz .LBB1_120
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_load_b64 s[60:61], s[34:35], 0x50
	s_mov_b32 s66, 2
.LBB1_4:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_7 Depth 3
                                        ;       Child Loop BB1_15 Depth 3
                                        ;       Child Loop BB1_21 Depth 3
                                        ;       Child Loop BB1_30 Depth 3
                                        ;       Child Loop BB1_34 Depth 3
                                        ;       Child Loop BB1_42 Depth 3
                                        ;       Child Loop BB1_48 Depth 3
                                        ;       Child Loop BB1_57 Depth 3
                                        ;       Child Loop BB1_65 Depth 3
                                        ;       Child Loop BB1_73 Depth 3
                                        ;       Child Loop BB1_79 Depth 3
                                        ;       Child Loop BB1_88 Depth 3
                                        ;       Child Loop BB1_92 Depth 3
                                        ;       Child Loop BB1_100 Depth 3
                                        ;       Child Loop BB1_106 Depth 3
                                        ;       Child Loop BB1_115 Depth 3
	ds_load_b32 v113, v126
	v_dual_mov_b32 v41, v127 :: v_dual_mov_b32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v41
	v_mov_b32_e32 v5, 0
	v_cmp_eq_u32_e64 s0, s0, v41
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_10
; %bb.5:                                ;   in Loop: Header=BB1_4 Depth=2
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[2:3], v42, s[60:61] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v42, s[60:61] offset:40
	global_load_b64 v[4:5], v42, s[60:61]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v42, v[0:3], s[60:61] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[2:3]
	s_cbranch_execz .LBB1_9
; %bb.6:                                ; %.preheader3.i.i.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s3, 0
.LBB1_7:                                ; %.preheader3.i.i.i
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[0:1], v42, s[60:61] offset:40
	global_load_b64 v[6:7], v42, s[60:61]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v0, v2
	v_and_b32_e32 v1, v1, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v0, 24, v[6:7]
	v_mov_b32_e32 v0, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[0:1]
	global_load_b64 v[0:1], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v42, v[0:3], s[60:61] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_7
; %bb.8:                                ; %Flow1345
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_9:                                ; %Flow1347
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_10:                               ; %.loopexit4.i.i.i
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[6:7], v42, s[60:61] offset:40
	global_load_b128 v[0:3], v42, s[60:61]
	v_readfirstlane_b32 s2, v4
	v_readfirstlane_b32 s3, v5
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_12
; %bb.11:                               ;   in Loop: Header=BB1_4 Depth=2
	v_dual_mov_b32 v43, s8 :: v_dual_mov_b32 v44, v42
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v5, vcc_lo, s8, v1, vcc_lo
	global_store_b128 v[4:5], v[43:46], off offset:8
.LBB1_12:                               ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[4:5], 6, v[41:42]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s29, s28
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v4
	s_mov_b32 s30, s28
	s_mov_b32 s31, s28
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v5, vcc_lo
	v_dual_mov_b32 v41, v42 :: v_dual_mov_b32 v2, s28
	v_dual_mov_b32 v43, v42 :: v_dual_mov_b32 v4, s30
	v_mov_b32_e32 v3, s29
	v_mov_b32_e32 v5, s31
	s_clause 0x3
	global_store_b128 v[6:7], v[40:43], off
	global_store_b128 v[6:7], v[2:5], off offset:16
	global_store_b128 v[6:7], v[2:5], off offset:32
	global_store_b128 v[6:7], v[2:5], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_20
; %bb.13:                               ;   in Loop: Header=BB1_4 Depth=2
	s_clause 0x1
	global_load_b64 v[12:13], v42, s[60:61] offset:32 glc
	global_load_b64 v[2:3], v42, s[60:61] offset:40
	v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v2
	v_readfirstlane_b32 s9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v8, vcc_lo, v0, s8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v42, v[10:13], s[60:61] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB1_16
; %bb.14:                               ; %.preheader1.i.i.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s8, 0
.LBB1_15:                               ; %.preheader1.i.i.i
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v42, v[2:5], s[60:61] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_15
.LBB1_16:                               ; %Flow1343
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v42, s[60:61] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_18
; %bb.17:                               ;   in Loop: Header=BB1_4 Depth=2
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v41, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[41:42], off offset:8
.LBB1_18:                               ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_20
; %bb.19:                               ;   in Loop: Header=BB1_4 Depth=2
	global_load_b32 v41, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v41
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[41:42], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_20:                               ; %Flow1344
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_21:                               ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_23
; %bb.22:                               ;   in Loop: Header=BB1_21 Depth=3
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_23:                               ;   in Loop: Header=BB1_21 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_25
; %bb.24:                               ;   in Loop: Header=BB1_21 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_26
.LBB1_25:                               ;   in Loop: Header=BB1_21 Depth=3
	s_mov_b32 s1, -1
.LBB1_26:                               ; %Flow1338
                                        ;   in Loop: Header=BB1_21 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_21
; %bb.27:                               ;   in Loop: Header=BB1_4 Depth=2
	global_load_b64 v[0:1], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_31
; %bb.28:                               ;   in Loop: Header=BB1_4 Depth=2
	s_clause 0x2
	global_load_b64 v[4:5], v42, s[60:61] offset:40
	global_load_b64 v[8:9], v42, s[60:61] offset:24 glc
	global_load_b64 v[6:7], v42, s[60:61]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v10, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v2, v4
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v8
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v9
	global_store_b64 v[6:7], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v42, v[2:5], s[60:61] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_31
; %bb.29:                               ; %.preheader.i.i.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s0, 0
.LBB1_30:                               ; %.preheader.i.i.i
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v42, v[2:5], s[60:61] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
	v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_30
.LBB1_31:                               ; %__ockl_printf_begin.exit
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	v_dual_mov_b32 v2, v39 :: v_dual_mov_b32 v3, 0
	s_add_u32 s8, s18, 0x90
	s_addc_u32 s9, s19, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s1, s1, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_swappc_b64 s[30:31], s[0:1]
	v_dual_mov_b32 v41, v127 :: v_dual_mov_b32 v2, 0
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v41
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v41
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_37
; %bb.32:                               ;   in Loop: Header=BB1_4 Depth=2
	global_load_b64 v[4:5], v42, s[60:61] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[2:3], v42, s[60:61] offset:40
	global_load_b64 v[6:7], v42, s[60:61]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v8, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo
	global_load_b64 v[2:3], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v42, v[2:5], s[60:61] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[2:3], v[4:5]
	s_cbranch_execz .LBB1_36
; %bb.33:                               ; %.preheader3.i.i.i1045.preheader
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s3, 0
.LBB1_34:                               ; %.preheader3.i.i.i1045
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v42, s[60:61] offset:40
	global_load_b64 v[8:9], v42, s[60:61]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v6, v4
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[2:3], null, v6, 24, v[8:9]
	v_and_b32_e32 v8, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v8, 24, v[3:4]
	v_mov_b32_e32 v3, v6
	global_load_b64 v[2:3], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v42, v[2:5], s[60:61] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_34
; %bb.35:                               ; %Flow1331
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_36:                               ; %Flow1333
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_37:                               ; %.loopexit4.i.i.i1040
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v42, s[60:61] offset:40
	global_load_b128 v[4:7], v42, s[60:61]
	v_readfirstlane_b32 s2, v2
	v_readfirstlane_b32 s3, v3
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_39
; %bb.38:                               ;   in Loop: Header=BB1_4 Depth=2
	v_dual_mov_b32 v43, s8 :: v_dual_mov_b32 v44, v42
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v3, vcc_lo, s8, v5, vcc_lo
	global_store_b128 v[2:3], v[43:46], off offset:8
.LBB1_39:                               ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	v_cvt_f64_f32_e32 v[2:3], v113
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[8:9], 6, v[41:42]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v6, s4
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_mov_b32 s29, s28
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v6, v8
	s_mov_b32 s30, s28
	s_mov_b32 s31, s28
	v_and_or_b32 v0, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v11, vcc_lo, v7, v9, vcc_lo
	v_dual_mov_b32 v6, s28 :: v_dual_mov_b32 v7, s29
	v_dual_mov_b32 v8, s30 :: v_dual_mov_b32 v9, s31
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_47
; %bb.40:                               ;   in Loop: Header=BB1_4 Depth=2
	s_clause 0x1
	global_load_b64 v[10:11], v42, s[60:61] offset:32 glc
	global_load_b64 v[0:1], v42, s[60:61] offset:40
	v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v9, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v0
	v_readfirstlane_b32 s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v6, vcc_lo, v4, s8
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v5, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[6:7], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v42, v[8:11], s[60:61] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[10:11]
	s_cbranch_execz .LBB1_43
; %bb.41:                               ; %.preheader1.i.i.i1043.preheader
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s8, 0
.LBB1_42:                               ; %.preheader1.i.i.i1043
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v42, v[0:3], s[60:61] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_42
.LBB1_43:                               ; %Flow1329
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[0:1], v42, s[60:61] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v2, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_45
; %bb.44:                               ;   in Loop: Header=BB1_4 Depth=2
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v41, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[41:42], off offset:8
.LBB1_45:                               ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB1_47
; %bb.46:                               ;   in Loop: Header=BB1_4 Depth=2
	global_load_b32 v41, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v41
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[41:42], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_47:                               ; %Flow1330
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_48:                               ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_50
; %bb.49:                               ;   in Loop: Header=BB1_48 Depth=3
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_50:                               ;   in Loop: Header=BB1_48 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_52
; %bb.51:                               ;   in Loop: Header=BB1_48 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_53
.LBB1_52:                               ;   in Loop: Header=BB1_48 Depth=3
	s_mov_b32 s1, -1
.LBB1_53:                               ; %Flow1324
                                        ;   in Loop: Header=BB1_48 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_48
; %bb.54:                               ;   in Loop: Header=BB1_4 Depth=2
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_58
; %bb.55:                               ;   in Loop: Header=BB1_4 Depth=2
	s_clause 0x2
	global_load_b64 v[2:3], v42, s[60:61] offset:40
	global_load_b64 v[6:7], v42, s[60:61] offset:24 glc
	global_load_b64 v[4:5], v42, s[60:61]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v8, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v8, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v9 :: v_dual_cndmask_b32 v0, v0, v8
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, v0, v2
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v6
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v3, v8, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v7
	global_store_b64 v[4:5], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v42, v[0:3], s[60:61] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_58
; %bb.56:                               ; %.preheader.i.i.i1042.preheader
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s0, 0
.LBB1_57:                               ; %.preheader.i.i.i1042
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v42, v[0:3], s[60:61] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
	v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_57
.LBB1_58:                               ; %__ockl_printf_append_args.exit
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_mul_i32 s67, s33, s66
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, s67, v119
	v_add_nc_u32_e32 v0, v2, v120
	v_add_nc_u32_e32 v115, v2, v122
	v_add_nc_u32_e32 v113, v2, v47
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v116, 31, v115
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v114, 31, v113
	v_lshlrev_b64 v[117:118], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s24, v117
	v_add_co_ci_u32_e32 v1, vcc_lo, s25, v118, vcc_lo
	global_load_b32 v129, v[0:1], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v126, v129
	s_and_saveexec_b32 s0, s54
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB1_60
; %bb.59:                               ;   in Loop: Header=BB1_4 Depth=2
	s_add_i32 s1, s66, 1
	v_add_nc_u32_e32 v17, s67, v123
	s_mul_i32 s1, s33, s1
	v_add_co_u32 v4, vcc_lo, s36, v117
	v_add_nc_u32_e32 v16, s1, v119
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v2, v17, v120
	v_add_co_ci_u32_e32 v5, vcc_lo, s37, v118, vcc_lo
	v_add_co_u32 v6, vcc_lo, s38, v117
	v_add_nc_u32_e32 v0, v16, v120
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v3, 31, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s39, v118, vcc_lo
	global_load_b32 v18, v[4:5], off
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_lshlrev_b64 v[8:9], 2, v[115:116]
	v_add_nc_u32_e32 v25, s67, v121
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_nc_u32_e32 v14, v25, v47
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s24, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s25, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s24, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s25, v3, vcc_lo
	v_add_co_u32 v4, vcc_lo, s40, v117
	v_add_co_ci_u32_e32 v5, vcc_lo, s41, v118, vcc_lo
	global_load_b32 v19, v[0:1], off
	global_load_b32 v20, v[6:7], off
	global_load_b32 v21, v[2:3], off
	global_load_b32 v22, v[4:5], off
	v_add_nc_u32_e32 v2, s1, v125
	v_add_nc_u32_e32 v4, s1, v124
	v_add_co_u32 v0, vcc_lo, s24, v8
	v_add_co_ci_u32_e32 v1, vcc_lo, s25, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v3, 31, v2
	s_sub_i32 s1, s1, s64
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_nc_u32_e32 v8, s1, v125
	v_add_co_u32 v6, vcc_lo, s44, v117
	global_load_b32 v23, v[0:1], off
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	v_add_nc_u32_e32 v4, s1, v124
	v_add_co_ci_u32_e32 v7, vcc_lo, s45, v118, vcc_lo
	v_ashrrev_i32_e32 v9, 31, v8
	v_add_co_u32 v0, vcc_lo, s24, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v5, 31, v4
	global_load_b32 v24, v[6:7], off
	v_lshlrev_b64 v[6:7], 2, v[8:9]
	v_add_co_ci_u32_e32 v1, vcc_lo, s25, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s24, v2
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_ci_u32_e32 v3, vcc_lo, s25, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s24, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s25, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s24, v4
	v_add_nc_u32_e32 v8, v17, v122
	v_add_co_ci_u32_e32 v5, vcc_lo, s25, v5, vcc_lo
	v_add_co_u32 v12, vcc_lo, s46, v117
	v_add_nc_u32_e32 v10, v25, v122
	v_add_co_ci_u32_e32 v13, vcc_lo, s47, v118, vcc_lo
	v_ashrrev_i32_e32 v9, 31, v8
	s_clause 0x3
	global_load_b32 v26, v[0:1], off
	global_load_b32 v27, v[2:3], off
	global_load_b32 v28, v[6:7], off
	global_load_b32 v29, v[4:5], off
	v_ashrrev_i32_e32 v11, 31, v10
	global_load_b32 v30, v[12:13], off
	v_add_nc_u32_e32 v4, v17, v47
	v_lshlrev_b64 v[0:1], 2, v[8:9]
	v_ashrrev_i32_e32 v15, 31, v14
	v_lshlrev_b64 v[2:3], 2, v[10:11]
	v_add_nc_u32_e32 v17, s1, v119
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_nc_u32_e32 v8, v16, v122
	v_add_co_u32 v0, vcc_lo, s24, v0
	v_lshlrev_b64 v[6:7], 2, v[14:15]
	v_add_co_ci_u32_e32 v1, vcc_lo, s25, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s24, v2
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_ci_u32_e32 v3, vcc_lo, s25, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s24, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s25, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s24, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s25, v5, vcc_lo
	v_add_co_u32 v12, vcc_lo, s48, v117
	v_add_co_ci_u32_e32 v13, vcc_lo, s49, v118, vcc_lo
	v_add_nc_u32_e32 v14, v16, v47
	s_clause 0x3
	global_load_b32 v16, v[0:1], off
	global_load_b32 v31, v[2:3], off
	global_load_b32 v32, v[6:7], off
	global_load_b32 v33, v[4:5], off
	v_ashrrev_i32_e32 v9, 31, v8
	global_load_b32 v34, v[12:13], off
	v_add_nc_u32_e32 v10, v17, v122
	v_add_nc_u32_e32 v4, v17, v47
	v_ashrrev_i32_e32 v15, 31, v14
	v_lshlrev_b64 v[0:1], 2, v[8:9]
	v_add_nc_u32_e32 v8, v17, v120
	v_ashrrev_i32_e32 v11, 31, v10
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[6:7], 2, v[14:15]
	v_add_nc_u32_e32 v12, v25, v120
	v_add_co_u32 v0, vcc_lo, s24, v0
	v_lshlrev_b64 v[2:3], 2, v[10:11]
	v_add_co_ci_u32_e32 v1, vcc_lo, s25, v1, vcc_lo
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_ashrrev_i32_e32 v9, 31, v8
	v_ashrrev_i32_e32 v13, 31, v12
	v_add_co_u32 v2, vcc_lo, s24, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s25, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s24, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s25, v7, vcc_lo
	v_add_co_u32 v4, vcc_lo, s24, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s25, v5, vcc_lo
	v_add_co_u32 v10, vcc_lo, s50, v117
	v_add_co_ci_u32_e32 v11, vcc_lo, s51, v118, vcc_lo
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_clause 0x3
	global_load_b32 v14, v[0:1], off
	global_load_b32 v15, v[2:3], off
	global_load_b32 v17, v[6:7], off
	global_load_b32 v25, v[4:5], off
	global_load_b32 v10, v[10:11], off
	v_lshlrev_b64 v[2:3], 2, v[12:13]
	v_lshlrev_b64 v[6:7], 2, v[113:114]
	v_add_co_u32 v0, vcc_lo, s24, v8
	v_add_co_ci_u32_e32 v1, vcc_lo, s25, v9, vcc_lo
	v_add_co_u32 v4, vcc_lo, s20, v117
	v_add_co_ci_u32_e32 v5, vcc_lo, s21, v118, vcc_lo
	v_add_co_u32 v2, vcc_lo, s24, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s25, v3, vcc_lo
	v_add_co_u32 v8, vcc_lo, s22, v117
	v_add_co_ci_u32_e32 v9, vcc_lo, s23, v118, vcc_lo
	v_add_co_u32 v6, vcc_lo, s24, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s25, v7, vcc_lo
	global_load_b32 v11, v[0:1], off
	global_load_b32 v4, v[4:5], off
	global_load_b32 v5, v[2:3], off
	global_load_b32 v8, v[8:9], off
	global_load_b32 v6, v[6:7], off
	v_add_co_u32 v0, vcc_lo, s26, v117
	v_add_co_ci_u32_e32 v1, vcc_lo, s27, v118, vcc_lo
	v_add_co_u32 v2, vcc_lo, s42, v117
	v_add_co_ci_u32_e32 v3, vcc_lo, s43, v118, vcc_lo
	global_load_b32 v7, v[0:1], off
	global_load_b32 v2, v[2:3], off
	v_add_co_u32 v0, vcc_lo, s58, v117
	v_add_co_ci_u32_e32 v1, vcc_lo, s59, v118, vcc_lo
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(26)
	v_mul_f32_e32 v3, v20, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v18, v19
	s_waitcnt vmcnt(24)
	v_fmac_f32_e32 v3, v22, v23
	s_waitcnt vmcnt(21)
	v_sub_f32_e32 v1, v26, v27
	s_waitcnt vmcnt(20)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v1, v1, v28
	s_waitcnt vmcnt(19)
	v_add_f32_e32 v1, v1, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v24, v1
	s_waitcnt vmcnt(16)
	v_sub_f32_e32 v9, v16, v31
	s_waitcnt vmcnt(15)
	v_sub_f32_e32 v9, v9, v32
	s_waitcnt vmcnt(14)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v9, v33
	v_fmac_f32_e32 v3, v30, v9
	s_waitcnt vmcnt(11)
	v_sub_f32_e32 v12, v14, v15
	s_waitcnt vmcnt(10)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v12, v12, v17
	s_waitcnt vmcnt(9)
	v_add_f32_e32 v1, v12, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v34, v1
	s_waitcnt vmcnt(7)
	v_fmac_f32_e32 v3, v10, v11
	s_waitcnt vmcnt(5)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v4, v5
	s_waitcnt vmcnt(3)
	v_fmac_f32_e32 v3, v8, v6
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v7, v3
	s_waitcnt vmcnt(1)
	v_fma_f32 v1, v2, v1, -v129
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v2, v0, v1
	v_add_co_u32 v0, vcc_lo, s56, v117
	v_add_co_ci_u32_e32 v1, vcc_lo, s57, v118, vcc_lo
	v_fmac_f32_e32 v129, s17, v2
	v_fmac_f32_e32 v128, v2, v2
	global_store_b32 v[0:1], v129, off
.LBB1_60:                               ; %Flow1319
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB1_62
; %bb.61:                               ; %__ockl_printf_append_args.exit._crit_edge
                                        ;   in Loop: Header=BB1_4 Depth=2
	v_add_co_u32 v0, vcc_lo, s56, v117
	v_add_co_ci_u32_e32 v1, vcc_lo, s57, v118, vcc_lo
	global_load_b32 v129, v[0:1], off
.LBB1_62:                               ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mov_b32 v41, v127 :: v_dual_mov_b32 v4, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v126, v129
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v41
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v41
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_68
; %bb.63:                               ;   in Loop: Header=BB1_4 Depth=2
	global_load_b64 v[2:3], v42, s[60:61] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v42, s[60:61] offset:40
	global_load_b64 v[4:5], v42, s[60:61]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v42, v[0:3], s[60:61] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[2:3]
	s_cbranch_execz .LBB1_67
; %bb.64:                               ; %.preheader3.i.i.i1051.preheader
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s3, 0
.LBB1_65:                               ; %.preheader3.i.i.i1051
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[0:1], v42, s[60:61] offset:40
	global_load_b64 v[6:7], v42, s[60:61]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v0, v2
	v_and_b32_e32 v1, v1, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v0, 24, v[6:7]
	v_mov_b32_e32 v0, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[0:1]
	global_load_b64 v[0:1], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v42, v[0:3], s[60:61] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_65
; %bb.66:                               ; %Flow1316
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_67:                               ; %Flow1318
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_68:                               ; %.loopexit4.i.i.i1046
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[6:7], v42, s[60:61] offset:40
	global_load_b128 v[0:3], v42, s[60:61]
	v_readfirstlane_b32 s2, v4
	v_readfirstlane_b32 s3, v5
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_70
; %bb.69:                               ;   in Loop: Header=BB1_4 Depth=2
	v_dual_mov_b32 v43, s8 :: v_dual_mov_b32 v44, v42
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v5, vcc_lo, s8, v1, vcc_lo
	global_store_b128 v[4:5], v[43:46], off offset:8
.LBB1_70:                               ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[4:5], 6, v[41:42]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s29, s28
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v4
	s_mov_b32 s30, s28
	s_mov_b32 s31, s28
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v5, vcc_lo
	v_dual_mov_b32 v41, v42 :: v_dual_mov_b32 v2, s28
	v_dual_mov_b32 v43, v42 :: v_dual_mov_b32 v4, s30
	v_mov_b32_e32 v3, s29
	v_mov_b32_e32 v5, s31
	s_clause 0x3
	global_store_b128 v[6:7], v[40:43], off
	global_store_b128 v[6:7], v[2:5], off offset:16
	global_store_b128 v[6:7], v[2:5], off offset:32
	global_store_b128 v[6:7], v[2:5], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_78
; %bb.71:                               ;   in Loop: Header=BB1_4 Depth=2
	s_clause 0x1
	global_load_b64 v[12:13], v42, s[60:61] offset:32 glc
	global_load_b64 v[2:3], v42, s[60:61] offset:40
	v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v2
	v_readfirstlane_b32 s9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v8, vcc_lo, v0, s8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v42, v[10:13], s[60:61] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB1_74
; %bb.72:                               ; %.preheader1.i.i.i1049.preheader
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s8, 0
.LBB1_73:                               ; %.preheader1.i.i.i1049
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v42, v[2:5], s[60:61] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_73
.LBB1_74:                               ; %Flow1314
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v42, s[60:61] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_76
; %bb.75:                               ;   in Loop: Header=BB1_4 Depth=2
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v41, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[41:42], off offset:8
.LBB1_76:                               ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_78
; %bb.77:                               ;   in Loop: Header=BB1_4 Depth=2
	global_load_b32 v41, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v41
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[41:42], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_78:                               ; %Flow1315
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_79:                               ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_81
; %bb.80:                               ;   in Loop: Header=BB1_79 Depth=3
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_81:                               ;   in Loop: Header=BB1_79 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_83
; %bb.82:                               ;   in Loop: Header=BB1_79 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_84
.LBB1_83:                               ;   in Loop: Header=BB1_79 Depth=3
	s_mov_b32 s1, -1
.LBB1_84:                               ; %Flow1309
                                        ;   in Loop: Header=BB1_79 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_79
; %bb.85:                               ;   in Loop: Header=BB1_4 Depth=2
	global_load_b64 v[0:1], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_89
; %bb.86:                               ;   in Loop: Header=BB1_4 Depth=2
	s_clause 0x2
	global_load_b64 v[4:5], v42, s[60:61] offset:40
	global_load_b64 v[8:9], v42, s[60:61] offset:24 glc
	global_load_b64 v[6:7], v42, s[60:61]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v10, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v2, v4
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v8
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v9
	global_store_b64 v[6:7], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v42, v[2:5], s[60:61] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_89
; %bb.87:                               ; %.preheader.i.i.i1048.preheader
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s0, 0
.LBB1_88:                               ; %.preheader.i.i.i1048
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v42, v[2:5], s[60:61] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
	v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_88
.LBB1_89:                               ; %__ockl_printf_begin.exit1052
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	v_dual_mov_b32 v2, v39 :: v_dual_mov_b32 v3, 0
	s_add_u32 s8, s18, 0x90
	s_addc_u32 s9, s19, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s1, s1, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_swappc_b64 s[30:31], s[0:1]
	v_dual_mov_b32 v41, v127 :: v_dual_mov_b32 v2, 0
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v41
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v41
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_95
; %bb.90:                               ;   in Loop: Header=BB1_4 Depth=2
	global_load_b64 v[4:5], v42, s[60:61] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[2:3], v42, s[60:61] offset:40
	global_load_b64 v[6:7], v42, s[60:61]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v8, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo
	global_load_b64 v[2:3], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v42, v[2:5], s[60:61] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[2:3], v[4:5]
	s_cbranch_execz .LBB1_94
; %bb.91:                               ; %.preheader3.i.i.i1058.preheader
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s3, 0
.LBB1_92:                               ; %.preheader3.i.i.i1058
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v42, s[60:61] offset:40
	global_load_b64 v[8:9], v42, s[60:61]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v6, v4
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[2:3], null, v6, 24, v[8:9]
	v_and_b32_e32 v8, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v8, 24, v[3:4]
	v_mov_b32_e32 v3, v6
	global_load_b64 v[2:3], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v42, v[2:5], s[60:61] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_92
; %bb.93:                               ; %Flow1302
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_94:                               ; %Flow1304
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_95:                               ; %.loopexit4.i.i.i1053
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v42, s[60:61] offset:40
	global_load_b128 v[4:7], v42, s[60:61]
	v_readfirstlane_b32 s2, v2
	v_readfirstlane_b32 s3, v3
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_97
; %bb.96:                               ;   in Loop: Header=BB1_4 Depth=2
	v_dual_mov_b32 v43, s8 :: v_dual_mov_b32 v44, v42
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v3, vcc_lo, s8, v5, vcc_lo
	global_store_b128 v[2:3], v[43:46], off offset:8
.LBB1_97:                               ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	v_cvt_f64_f32_e32 v[2:3], v129
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[8:9], 6, v[41:42]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v6, s4
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_mov_b32 s29, s28
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v6, v8
	s_mov_b32 s30, s28
	s_mov_b32 s31, s28
	v_and_or_b32 v0, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v11, vcc_lo, v7, v9, vcc_lo
	v_dual_mov_b32 v6, s28 :: v_dual_mov_b32 v7, s29
	v_dual_mov_b32 v8, s30 :: v_dual_mov_b32 v9, s31
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_105
; %bb.98:                               ;   in Loop: Header=BB1_4 Depth=2
	s_clause 0x1
	global_load_b64 v[10:11], v42, s[60:61] offset:32 glc
	global_load_b64 v[0:1], v42, s[60:61] offset:40
	v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v9, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v0
	v_readfirstlane_b32 s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v6, vcc_lo, v4, s8
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v5, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[6:7], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v42, v[8:11], s[60:61] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[10:11]
	s_cbranch_execz .LBB1_101
; %bb.99:                               ; %.preheader1.i.i.i1056.preheader
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s8, 0
.LBB1_100:                              ; %.preheader1.i.i.i1056
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v42, v[0:3], s[60:61] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_100
.LBB1_101:                              ; %Flow1300
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[0:1], v42, s[60:61] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v2, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_103
; %bb.102:                              ;   in Loop: Header=BB1_4 Depth=2
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v41, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[41:42], off offset:8
.LBB1_103:                              ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB1_105
; %bb.104:                              ;   in Loop: Header=BB1_4 Depth=2
	global_load_b32 v41, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v41
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[41:42], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_105:                              ; %Flow1301
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_106:                              ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_108
; %bb.107:                              ;   in Loop: Header=BB1_106 Depth=3
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_108:                              ;   in Loop: Header=BB1_106 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_110
; %bb.109:                              ;   in Loop: Header=BB1_106 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_111
.LBB1_110:                              ;   in Loop: Header=BB1_106 Depth=3
	s_mov_b32 s1, -1
.LBB1_111:                              ; %Flow1295
                                        ;   in Loop: Header=BB1_106 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_106
; %bb.112:                              ;   in Loop: Header=BB1_4 Depth=2
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_116
; %bb.113:                              ;   in Loop: Header=BB1_4 Depth=2
	s_clause 0x2
	global_load_b64 v[2:3], v42, s[60:61] offset:40
	global_load_b64 v[6:7], v42, s[60:61] offset:24 glc
	global_load_b64 v[4:5], v42, s[60:61]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v8, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v8, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v9 :: v_dual_cndmask_b32 v0, v0, v8
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, v0, v2
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v6
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v3, v8, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v7
	global_store_b64 v[4:5], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v42, v[0:3], s[60:61] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_116
; %bb.114:                              ; %.preheader.i.i.i1055.preheader
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s0, 0
.LBB1_115:                              ; %.preheader.i.i.i1055
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v42, v[0:3], s[60:61] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
	v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_115
.LBB1_116:                              ; %__ockl_printf_append_args.exit1059
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, s53
	s_cbranch_execz .LBB1_118
; %bb.117:                              ;   in Loop: Header=BB1_4 Depth=2
	s_add_i32 s1, s66, -1
	v_add_co_u32 v6, vcc_lo, s56, v117
	s_mul_i32 s1, s33, s1
	v_add_co_ci_u32_e32 v7, vcc_lo, s57, v118, vcc_lo
	v_add_nc_u32_e32 v18, s1, v119
	s_sub_i32 s2, s1, s33
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, v18, v120
	v_add_nc_u32_e32 v4, v18, v122
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v8, vcc_lo, s36, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v9, vcc_lo, s37, v1, vcc_lo
	v_add_co_u32 v10, vcc_lo, s38, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, s39, v1, vcc_lo
	global_load_b32 v20, v[8:9], off
	v_add_nc_u32_e32 v19, s1, v123
	v_add_nc_u32_e32 v2, v19, v120
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s56, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s57, v3, vcc_lo
	v_add_co_u32 v8, vcc_lo, s40, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s41, v1, vcc_lo
	global_load_b32 v21, v[6:7], off
	global_load_b32 v22, v[10:11], off
	global_load_b32 v23, v[2:3], off
	global_load_b32 v24, v[8:9], off
	v_add_co_u32 v2, vcc_lo, s56, v4
	v_add_nc_u32_e32 v4, s67, v125
	v_add_nc_u32_e32 v6, s67, v124
	v_add_co_ci_u32_e32 v3, vcc_lo, s57, v5, vcc_lo
	v_add_nc_u32_e32 v10, s2, v125
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v5, 31, v4
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_co_u32 v8, vcc_lo, s44, v0
	global_load_b32 v25, v[2:3], off
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	v_lshlrev_b64 v[4:5], 2, v[6:7]
	v_add_nc_u32_e32 v6, s2, v124
	v_add_co_ci_u32_e32 v9, vcc_lo, s45, v1, vcc_lo
	v_ashrrev_i32_e32 v11, 31, v10
	v_add_co_u32 v2, vcc_lo, s56, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v7, 31, v6
	global_load_b32 v26, v[8:9], off
	v_lshlrev_b64 v[8:9], 2, v[10:11]
	v_add_co_ci_u32_e32 v3, vcc_lo, s57, v3, vcc_lo
	v_add_nc_u32_e32 v27, s1, v121
	v_add_co_u32 v4, vcc_lo, s56, v4
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_nc_u32_e32 v10, v19, v122
	v_add_co_ci_u32_e32 v5, vcc_lo, s57, v5, vcc_lo
	v_add_co_u32 v8, vcc_lo, s56, v8
	v_add_nc_u32_e32 v12, v27, v122
	v_add_co_ci_u32_e32 v9, vcc_lo, s57, v9, vcc_lo
	v_add_co_u32 v6, vcc_lo, s56, v6
	v_ashrrev_i32_e32 v11, 31, v10
	v_add_nc_u32_e32 v16, v27, v47
	v_add_co_ci_u32_e32 v7, vcc_lo, s57, v7, vcc_lo
	v_ashrrev_i32_e32 v13, 31, v12
	s_clause 0x3
	global_load_b32 v28, v[2:3], off
	global_load_b32 v29, v[4:5], off
	global_load_b32 v30, v[8:9], off
	global_load_b32 v31, v[6:7], off
	v_add_nc_u32_e32 v6, v19, v47
	v_lshlrev_b64 v[2:3], 2, v[10:11]
	v_ashrrev_i32_e32 v17, 31, v16
	v_add_co_u32 v14, vcc_lo, s46, v0
	v_lshlrev_b64 v[4:5], 2, v[12:13]
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_co_ci_u32_e32 v15, vcc_lo, s47, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s56, v2
	v_lshlrev_b64 v[8:9], 2, v[16:17]
	v_add_co_ci_u32_e32 v3, vcc_lo, s57, v3, vcc_lo
	v_add_co_u32 v4, vcc_lo, s56, v4
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_nc_u32_e32 v16, s2, v119
	v_add_co_ci_u32_e32 v5, vcc_lo, s57, v5, vcc_lo
	v_add_co_u32 v8, vcc_lo, s56, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s57, v9, vcc_lo
	v_add_co_u32 v6, vcc_lo, s56, v6
	v_add_nc_u32_e32 v10, v16, v122
	v_add_co_ci_u32_e32 v7, vcc_lo, s57, v7, vcc_lo
	v_add_co_u32 v12, vcc_lo, s48, v0
	v_add_co_ci_u32_e32 v13, vcc_lo, s49, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v11, 31, v10
	global_load_b32 v32, v[14:15], off
	s_clause 0x3
	global_load_b32 v17, v[2:3], off
	global_load_b32 v19, v[4:5], off
	global_load_b32 v33, v[8:9], off
	global_load_b32 v34, v[6:7], off
	global_load_b32 v35, v[12:13], off
	v_add_nc_u32_e32 v4, v16, v47
	v_lshlrev_b64 v[14:15], 2, v[115:116]
	v_lshlrev_b64 v[2:3], 2, v[10:11]
	v_lshlrev_b64 v[8:9], 2, v[113:114]
	v_add_nc_u32_e32 v10, v16, v120
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_co_u32 v6, vcc_lo, s56, v14
	v_add_co_ci_u32_e32 v7, vcc_lo, s57, v15, vcc_lo
	v_add_co_u32 v2, vcc_lo, s56, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_ci_u32_e32 v3, vcc_lo, s57, v3, vcc_lo
	v_add_co_u32 v8, vcc_lo, s56, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s57, v9, vcc_lo
	v_add_co_u32 v4, vcc_lo, s56, v4
	v_ashrrev_i32_e32 v11, 31, v10
	v_add_co_ci_u32_e32 v5, vcc_lo, s57, v5, vcc_lo
	v_add_nc_u32_e32 v14, v27, v120
	v_add_co_u32 v12, vcc_lo, s50, v0
	v_add_co_ci_u32_e32 v13, vcc_lo, s51, v1, vcc_lo
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_clause 0x3
	global_load_b32 v16, v[6:7], off
	global_load_b32 v27, v[2:3], off
	global_load_b32 v36, v[8:9], off
	global_load_b32 v37, v[4:5], off
	global_load_b32 v12, v[12:13], off
	v_ashrrev_i32_e32 v15, 31, v14
	v_add_nc_u32_e32 v6, v18, v47
	v_add_co_u32 v2, vcc_lo, s56, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[4:5], 2, v[14:15]
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_co_ci_u32_e32 v3, vcc_lo, s57, v11, vcc_lo
	v_add_co_u32 v8, vcc_lo, s20, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s21, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s56, v4
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_ci_u32_e32 v5, vcc_lo, s57, v5, vcc_lo
	v_add_co_u32 v10, vcc_lo, s22, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, s23, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, s56, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s57, v7, vcc_lo
	global_load_b32 v13, v[2:3], off
	global_load_b32 v8, v[8:9], off
	global_load_b32 v9, v[4:5], off
	global_load_b32 v10, v[10:11], off
	global_load_b32 v11, v[6:7], off
	v_add_co_u32 v2, vcc_lo, s26, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s27, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s42, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s43, v1, vcc_lo
	v_add_co_u32 v6, vcc_lo, s56, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s57, v1, vcc_lo
	global_load_b32 v14, v[2:3], off
	global_load_b32 v4, v[4:5], off
	global_load_b32 v5, v[6:7], off
	v_add_co_u32 v2, vcc_lo, s58, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s59, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s24, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s25, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(27)
	v_mul_f32_e32 v6, v22, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v20, v21
	s_waitcnt vmcnt(25)
	v_fmac_f32_e32 v6, v24, v25
	s_waitcnt vmcnt(22)
	v_sub_f32_e32 v3, v28, v29
	s_waitcnt vmcnt(21)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v3, v3, v30
	s_waitcnt vmcnt(20)
	v_add_f32_e32 v3, v3, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v26, v3
	s_waitcnt vmcnt(17)
	v_sub_f32_e32 v7, v17, v19
	s_waitcnt vmcnt(16)
	v_sub_f32_e32 v7, v7, v33
	s_waitcnt vmcnt(15)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v7, v34
	v_fmac_f32_e32 v6, v32, v7
	s_waitcnt vmcnt(12)
	v_sub_f32_e32 v15, v16, v27
	s_waitcnt vmcnt(11)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v15, v15, v36
	s_waitcnt vmcnt(10)
	v_add_f32_e32 v3, v15, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v35, v3
	s_waitcnt vmcnt(8)
	v_fmac_f32_e32 v6, v12, v13
	s_waitcnt vmcnt(6)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v8, v9
	s_waitcnt vmcnt(4)
	v_fmac_f32_e32 v6, v10, v11
	s_waitcnt vmcnt(3)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v14, v6
	s_waitcnt vmcnt(1)
	v_fma_f32 v3, v4, v3, -v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v2, v3
	v_fmac_f32_e32 v5, s17, v2
	v_fmac_f32_e32 v128, v2, v2
	global_store_b32 v[0:1], v5, off
.LBB1_118:                              ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s66, s66, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s66, s62
	s_cbranch_scc1 .LBB1_4
; %bb.119:                              ; %Flow1348
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b32 s4, s62
	s_branch .LBB1_121
.LBB1_120:                              ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b32 s4, 2
.LBB1_121:                              ; %._crit_edge
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_and_saveexec_b32 s0, s53
	s_cbranch_execz .LBB1_123
; %bb.122:                              ;   in Loop: Header=BB1_2 Depth=1
	global_load_b32 v0, v[53:54], off
	s_clause 0x2
	global_load_b32 v1, v[55:56], off
	global_load_b32 v2, v[63:64], off
	global_load_b32 v3, v[65:66], off
	global_load_b32 v4, v[49:50], off
	s_clause 0x3
	global_load_b32 v5, v[73:74], off
	global_load_b32 v6, v[75:76], off
	global_load_b32 v7, v[51:52], off
	global_load_b32 v8, v[67:68], off
	global_load_b32 v9, v[57:58], off
	s_clause 0x5
	global_load_b32 v10, v[59:60], off
	global_load_b32 v11, v[77:78], off
	global_load_b32 v12, v[69:70], off
	global_load_b32 v13, v[83:84], off
	global_load_b32 v14, v[85:86], off
	global_load_b32 v15, v[79:80], off
	global_load_b32 v16, v[61:62], off
	global_load_b32 v17, v[87:88], off
	global_load_b32 v18, v[71:72], off
	global_load_b32 v19, v[89:90], off
	global_load_b32 v20, v[81:82], off
	global_load_b32 v21, v[91:92], off
	global_load_b32 v22, v[93:94], off
	global_load_b32 v23, v[95:96], off
	global_load_b32 v24, v[97:98], off
	global_load_b32 v25, v[99:100], off
	global_load_b32 v26, v[101:102], off
	global_load_b32 v27, v[103:104], off
	global_load_b32 v28, v[105:106], off
	global_load_b32 v29, v[107:108], off
	global_load_b32 v30, v[109:110], off
	s_waitcnt vmcnt(27)
	v_dual_mul_f32 v0, v0, v1 :: v_dual_sub_f32 v1, v2, v3
	s_waitcnt vmcnt(22)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v0, v4, v7 :: v_dual_sub_f32 v1, v1, v8
	s_waitcnt vmcnt(20)
	v_fmac_f32_e32 v0, v9, v10
	s_waitcnt vmcnt(18)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v1, v12
	s_waitcnt vmcnt(14)
	v_dual_sub_f32 v3, v13, v14 :: v_dual_fmac_f32 v0, v16, v1
	s_waitcnt vmcnt(13)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v2, v5, v6 :: v_dual_sub_f32 v1, v3, v17
	v_sub_f32_e32 v2, v2, v11
	s_waitcnt vmcnt(11)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v1, v1, v19
	v_add_f32_e32 v2, v2, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, v18, v2
	s_waitcnt vmcnt(10)
	v_fmac_f32_e32 v0, v20, v1
	s_waitcnt vmcnt(8)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, v21, v22
	s_waitcnt vmcnt(6)
	v_fmac_f32_e32 v0, v23, v24
	s_waitcnt vmcnt(4)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, v25, v26
	s_waitcnt vmcnt(3)
	v_add_f32_e32 v0, v27, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v0, v28, v0, -v29
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v0, v30, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v29, s17, v0
	v_fmac_f32_e32 v128, v0, v0
	global_store_b32 v[111:112], v29, off
.LBB1_123:                              ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s65, s65, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s65, s52
	s_cbranch_scc1 .LBB1_2
	s_branch .LBB1_125
.LBB1_124:
                                        ; implicit-def: $vgpr128
.LBB1_125:                              ; %._crit_edge1094
	s_add_i32 s2, s55, -2
	s_load_b64 s[0:1], s[18:19], 0x88
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v48, s2, v[47:48]
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v128, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 400
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 130
		.amdhsa_next_free_sgpr 68
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_, .Lfunc_end1-_Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 11084
; NumSgprs: 70
; NumVgprs: 130
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 8
; VGPRBlocks: 16
; NumSGPRsForWavesPerEU: 70
; NumVGPRsForWavesPerEU: 130
; Occupancy: 10
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"%f\n"
	.size	.str, 4

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         88
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         96
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         104
        .size:           8
        .value_kind:     global_buffer
      - .offset:         112
        .size:           4
        .value_kind:     by_value
      - .offset:         116
        .size:           4
        .value_kind:     by_value
      - .offset:         120
        .size:           4
        .value_kind:     by_value
      - .offset:         124
        .size:           4
        .value_kind:     by_value
      - .offset:         128
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         136
        .size:           8
        .value_kind:     global_buffer
      - .offset:         144
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         148
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         152
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         156
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         158
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         160
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         162
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         164
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         166
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         184
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         192
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         200
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         208
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         224
        .size:           8
        .value_kind:     hidden_hostcall_buffer
      - .offset:         264
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 400
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_
    .private_segment_fixed_size: 0
    .sgpr_count:     70
    .sgpr_spill_count: 0
    .symbol:         _Z6jacobiPfS_S_S_S_S_S_S_S_S_S_S_S_S_iiiifS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     130
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
