#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <cuda.h>

#define ROWS 4096
#define COLS 4096

__global__ void histo(int* d_hist1, int* d_hist2, int* mat) {

	int id;
	id = blockIdx.x * blockDim.x + threadIdx.x;

	switch (d_hist1[id]) {
	case 0:
		atomicAdd(&mat[0], 1);
		break;
	case 1:
		atomicAdd(&mat[1], 1);
		break;
	case 2:
		atomicAdd(&mat[2], 1);
		break;
	case 3:
		atomicAdd(&mat[3], 1);
		break;
	case 4:
		atomicAdd(&mat[4], 1);
		break;
	case 5:
		atomicAdd(&mat[5], 1);
		break;
	case 6:
		atomicAdd(&mat[6], 1);
		break;
	case 7:
		atomicAdd(&mat[7], 1);
		break;
	case 8:
		atomicAdd(&mat[8], 1);
		break;
	case 9:
		atomicAdd(&mat[9], 1);
		break;

	}
	__syncthreads();
	switch (d_hist2[id]) {
	case 0:
		atomicAdd(&mat[0], 1);
		break;
	case 1:
		atomicAdd(&mat[1], 1);
		break;
	case 2:
		atomicAdd(&mat[2], 1);
		break;
	case 3:
		atomicAdd(&mat[3], 1);
		break;
	case 4:
		atomicAdd(&mat[4], 1);
		break;
	case 5:
		atomicAdd(&mat[5], 1);
		break;
	case 6:
		atomicAdd(&mat[6], 1);
		break;
	case 7:
		atomicAdd(&mat[7], 1);
		break;
	case 8:
		atomicAdd(&mat[8], 1);
		break;
	case 9:
		atomicAdd(&mat[9], 1);
		break;


	}

}

int main(int argc, char* argv[]) {

	//int histogram[ROWS][COLS];
	int x, y;
	int hist[ROWS * COLS], hist1[(ROWS * COLS) / 2], hist2[(ROWS * COLS) / 2];
	int *d_hist1, *d_hist2;
	int i = 0;
	int mat[10];
	int *d_mat;


	FILE *fp;
	fp = fopen("input.txt", "r");
	for (x = 0; x < ROWS; x++)
	{
		for ( y = 0; y < COLS; y++)
		{
			fscanf(fp, "%d", &hist[i]);
			// printf("%d\t",hist[i]);
			i++;
		}

	}
	fclose(fp);

	printf("\n");

	//int i = 0;
	/*for (x = 0; x < ROWS; x++) {
			for (y = 0; y < COLS; y++) {
					hist[i] = histogram[x][y];
			}
	}*/

	for (i = 0; i < (ROWS * COLS) / 2; i++) {
		hist1[i] = hist[i];
		//	printf("%d\t", hist[i]);
	}
	printf("\n");
	for (i = 0; i < (ROWS * COLS) / 2; i++) {
		hist2[i] = hist[((ROWS * COLS) / 2) + i];
		//	printf("%d\t", hist[i]);
	}

	for (i = 0; i < 10; i++) {
		mat[i] = 0;
	}

	cudaMalloc(&d_hist1, ROWS * COLS * sizeof(int) / 2);
	cudaMalloc(&d_hist2, ROWS * COLS * sizeof(int) / 2);
	cudaMalloc(&d_mat, 10 * sizeof(int));


	cudaMemcpy(d_hist1, hist1, (ROWS * COLS * sizeof(int)) / 2, cudaMemcpyHostToDevice);
	cudaMemcpy(d_hist2, hist2, (ROWS * COLS * sizeof(int)) / 2, cudaMemcpyHostToDevice);
	cudaMemcpy(d_mat, &mat, 10 * sizeof(int), cudaMemcpyHostToDevice);
	cudaMemset(d_mat, 0, sizeof(d_mat));


	//histo <<<16384,1024>>>(d_hist, d_mat, ROWS * COLS);
	histo <<< 8192, 1024>>>(d_hist1, d_hist2, d_mat);


	cudaThreadSynchronize();

	cudaMemcpy(mat, d_mat, 10 * sizeof(int), cudaMemcpyDeviceToHost);

	FILE *fout;
	fout = fopen("output.txt", "w");

	for (i = 0; i < 10; i++) {
		printf("\n%d => %d", i, mat[i]);
		fprintf(fout, "%d => %d\n", i, mat[i]);
	}

	fclose(fout);
	cudaFree(d_mat);
	cudaFree(d_hist1);
	cudaFree(d_hist2);
	return 0;

}

	.file	"tmpxft_00268c2a_00000000-6_histogram.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z28__device_stub__Z5histoPiS_S_PiS_S_
	.type	_Z28__device_stub__Z5histoPiS_S_PiS_S_, @function
_Z28__device_stub__Z5histoPiS_S_PiS_S_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z5histoPiS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z28__device_stub__Z5histoPiS_S_PiS_S_, .-_Z28__device_stub__Z5histoPiS_S_PiS_S_
	.globl	_Z5histoPiS_S_
	.type	_Z5histoPiS_S_, @function
_Z5histoPiS_S_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z5histoPiS_S_PiS_S_
	.cfi_endproc
.LFE2053:
	.size	_Z5histoPiS_S_, .-_Z5histoPiS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"r"
.LC1:
	.string	"input.txt"
.LC2:
	.string	"%d"
.LC3:
	.string	"\n"
.LC4:
	.string	"w"
.LC5:
	.string	"output.txt"
.LC6:
	.string	"\n%d => %d"
.LC7:
	.string	"%d => %d\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	leaq	-134217728(%rsp), %r11
	.cfi_def_cfa 11, 134217784
.LPSRL0:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL0
	.cfi_def_cfa_register 7
	subq	$120, %rsp
	.cfi_def_cfa_offset 134217904
	leaq	.LC1(%rip), %rdi
	leaq	.LC0(%rip), %rsi
	xorl	%ebp, %ebp
	leaq	.LC2(%rip), %r15
	movq	%fs:40, %rax
	movq	%rax, 134217832(%rsp)
	xorl	%eax, %eax
	leaq	67108968(%rsp), %r12
	call	fopen@PLT
	movq	%r12, %r13
	movq	%rax, %rdi
.L9:
	movq	%r12, %r14
	movl	$4096, %ebx
.L10:
	movq	%r14, %rdx
	xorl	%eax, %eax
	movq	%r15, %rsi
	movq	%rdi, 8(%rsp)
	call	__isoc23_fscanf@PLT
	addq	$4, %r14
	decl	%ebx
	movq	8(%rsp), %rdi
	jne	.L10
	addl	$4096, %ebp
	addq	$16384, %r12
	cmpl	$16777216, %ebp
	jne	.L9
	call	fclose@PLT
	leaq	.LC3(%rip), %rbp
	movl	$2, %edi
	xorl	%eax, %eax
	movq	%rbp, %rsi
	call	__printf_chk@PLT
	xorl	%eax, %eax
	leaq	104(%rsp), %rdi
	movq	%r13, %rsi
	movl	$8388608, %ecx
	rep movsl
	movq	%rbp, %rsi
	movl	$2, %edi
	leaq	64(%rsp), %rbp
	call	__printf_chk@PLT
	movl	%ebx, %eax
	movl	$8388608, %ecx
	leaq	33554536(%rsp), %rdi
	leaq	100663400(%rsp), %rsi
	rep movsl
	movl	$10, %ecx
	movq	%rbp, %rdi
	movl	$33554432, %esi
	rep stosl
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$33554432, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$40, %esi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	leaq	104(%rsp), %rsi
	movl	$1, %ecx
	movl	$33554432, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	leaq	33554536(%rsp), %rsi
	movl	$33554432, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$40, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	movl	$8, %edx
	call	cudaMemset@PLT
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$524289, %edi
	salq	$10, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$13, %rdi
	movq	%rdx, 52(%rsp)
	movl	$1, 60(%rsp)
	movq	%rdi, 40(%rsp)
	movl	$1, 48(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	call	_Z28__device_stub__Z5histoPiS_S_PiS_S_
.L12:
	call	cudaThreadSynchronize@PLT
	movq	32(%rsp), %rsi
	movq	%rbp, %rdi
	xorl	%ebx, %ebx
	movl	$2, %ecx
	movl	$40, %edx
	leaq	.LC6(%rip), %r14
	call	cudaMemcpy@PLT
	leaq	.LC4(%rip), %rsi
	leaq	.LC5(%rip), %rdi
	call	fopen@PLT
	movq	%rax, %r12
.L13:
	movl	0(%rbp,%rbx,4), %ecx
	movl	%ebx, %edx
	movq	%r14, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	0(%rbp,%rbx,4), %r8d
	movl	%ebx, %ecx
	movq	%r12, %rdi
	leaq	.LC7(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	incq	%rbx
	call	__fprintf_chk@PLT
	cmpq	$10, %rbx
	jne	.L13
	movq	%r12, %rdi
	call	fclose@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	134217832(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$134217848, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC8:
	.string	"_Z5histoPiS_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z5histoPiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <hip/hip_runtime.h>

#define ROWS 4096
#define COLS 4096

__global__ void histo(int* d_hist1, int* d_hist2, int* mat) {

	int id;
	id = blockIdx.x * blockDim.x + threadIdx.x;

	switch (d_hist1[id]) {
	case 0:
		atomicAdd(&mat[0], 1);
		break;
	case 1:
		atomicAdd(&mat[1], 1);
		break;
	case 2:
		atomicAdd(&mat[2], 1);
		break;
	case 3:
		atomicAdd(&mat[3], 1);
		break;
	case 4:
		atomicAdd(&mat[4], 1);
		break;
	case 5:
		atomicAdd(&mat[5], 1);
		break;
	case 6:
		atomicAdd(&mat[6], 1);
		break;
	case 7:
		atomicAdd(&mat[7], 1);
		break;
	case 8:
		atomicAdd(&mat[8], 1);
		break;
	case 9:
		atomicAdd(&mat[9], 1);
		break;

	}
	__syncthreads();
	switch (d_hist2[id]) {
	case 0:
		atomicAdd(&mat[0], 1);
		break;
	case 1:
		atomicAdd(&mat[1], 1);
		break;
	case 2:
		atomicAdd(&mat[2], 1);
		break;
	case 3:
		atomicAdd(&mat[3], 1);
		break;
	case 4:
		atomicAdd(&mat[4], 1);
		break;
	case 5:
		atomicAdd(&mat[5], 1);
		break;
	case 6:
		atomicAdd(&mat[6], 1);
		break;
	case 7:
		atomicAdd(&mat[7], 1);
		break;
	case 8:
		atomicAdd(&mat[8], 1);
		break;
	case 9:
		atomicAdd(&mat[9], 1);
		break;


	}

}

int main(int argc, char* argv[]) {

	//int histogram[ROWS][COLS];
	int x, y;
	int hist[ROWS * COLS], hist1[(ROWS * COLS) / 2], hist2[(ROWS * COLS) / 2];
	int *d_hist1, *d_hist2;
	int i = 0;
	int mat[10];
	int *d_mat;


	FILE *fp;
	fp = fopen("input.txt", "r");
	for (x = 0; x < ROWS; x++)
	{
		for ( y = 0; y < COLS; y++)
		{
			fscanf(fp, "%d", &hist[i]);
			// printf("%d\t",hist[i]);
			i++;
		}

	}
	fclose(fp);

	printf("\n");

	//int i = 0;
	/*for (x = 0; x < ROWS; x++) {
			for (y = 0; y < COLS; y++) {
					hist[i] = histogram[x][y];
			}
	}*/

	for (i = 0; i < (ROWS * COLS) / 2; i++) {
		hist1[i] = hist[i];
		//	printf("%d\t", hist[i]);
	}
	printf("\n");
	for (i = 0; i < (ROWS * COLS) / 2; i++) {
		hist2[i] = hist[((ROWS * COLS) / 2) + i];
		//	printf("%d\t", hist[i]);
	}

	for (i = 0; i < 10; i++) {
		mat[i] = 0;
	}

	hipMalloc(&d_hist1, ROWS * COLS * sizeof(int) / 2);
	hipMalloc(&d_hist2, ROWS * COLS * sizeof(int) / 2);
	hipMalloc(&d_mat, 10 * sizeof(int));


	hipMemcpy(d_hist1, hist1, (ROWS * COLS * sizeof(int)) / 2, hipMemcpyHostToDevice);
	hipMemcpy(d_hist2, hist2, (ROWS * COLS * sizeof(int)) / 2, hipMemcpyHostToDevice);
	hipMemcpy(d_mat, &mat, 10 * sizeof(int), hipMemcpyHostToDevice);
	hipMemset(d_mat, 0, sizeof(d_mat));


	//histo <<<16384,1024>>>(d_hist, d_mat, ROWS * COLS);
	histo <<< 8192, 1024>>>(d_hist1, d_hist2, d_mat);


	hipDeviceSynchronize();

	hipMemcpy(mat, d_mat, 10 * sizeof(int), hipMemcpyDeviceToHost);

	FILE *fout;
	fout = fopen("output.txt", "w");

	for (i = 0; i < 10; i++) {
		printf("\n%d => %d", i, mat[i]);
		fprintf(fout, "%d => %d\n", i, mat[i]);
	}

	fclose(fout);
	hipFree(d_mat);
	hipFree(d_hist1);
	hipFree(d_hist2);
	return 0;

}

	.text
	.file	"histogram.hip"
	.globl	_Z20__device_stub__histoPiS_S_  # -- Begin function _Z20__device_stub__histoPiS_S_
	.type	_Z20__device_stub__histoPiS_S_,@function
_Z20__device_stub__histoPiS_S_:         # @_Z20__device_stub__histoPiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5histoPiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z20__device_stub__histoPiS_S_, .Lfunc_end0-_Z20__device_stub__histoPiS_S_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$134217816, %rsp                # imm = 0x8000058
	.cfi_def_cfa_offset 134217872
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$.L.str, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	movq	%rax, %rbx
	leaq	80(%rsp), %r14
	xorl	%ebp, %ebp
.LBB1_1:                                # %.preheader34
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
	xorl	%r15d, %r15d
.LBB1_2:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leaq	(%r14,%r15), %rdx
	movl	$.L.str.2, %esi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	addq	$4, %r15
	cmpl	$16384, %r15d                   # imm = 0x4000
	jne	.LBB1_2
# %bb.3:                                #   in Loop: Header=BB1_1 Depth=1
	incl	%ebp
	addq	$16384, %r14                    # imm = 0x4000
	cmpl	$4096, %ebp                     # imm = 0x1000
	jne	.LBB1_1
# %bb.4:                                # %.preheader.preheader
	movq	%rbx, %rdi
	callq	fclose
	movl	$10, %edi
	callq	putchar@PLT
	leaq	100663376(%rsp), %rbx
	leaq	80(%rsp), %rsi
	movl	$33554432, %edx                 # imm = 0x2000000
	movq	%rbx, %rdi
	callq	memcpy@PLT
	movl	$10, %edi
	callq	putchar@PLT
	leaq	33554512(%rsp), %rsi
	leaq	67108944(%rsp), %r15
	movl	$33554432, %edx                 # imm = 0x2000000
	movq	%r15, %rdi
	callq	memcpy@PLT
	xorps	%xmm0, %xmm0
	leaq	32(%rsp), %r14
	movaps	%xmm0, (%r14)
	movaps	%xmm0, 16(%r14)
	movq	$0, 32(%r14)
	leaq	24(%rsp), %r13
	movl	$33554432, %esi                 # imm = 0x2000000
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	16(%rsp), %rbp
	movl	$33554432, %esi                 # imm = 0x2000000
	movq	%rbp, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %r12
	movl	$40, %esi
	movq	%r12, %rdi
	callq	hipMalloc
	movq	(%r13), %rdi
	movl	$33554432, %edx                 # imm = 0x2000000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movl	$33554432, %edx                 # imm = 0x2000000
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movl	$40, %edx
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movl	$8, %edx
	xorl	%esi, %esi
	callq	hipMemset
	movabsq	$4294968320, %rdx               # imm = 0x100000400
	leaq	7168(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.5:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	callq	_Z20__device_stub__histoPiS_S_
.LBB1_6:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movl	$40, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.4, %edi
	movl	$.L.str.5, %esi
	callq	fopen
	movq	%rax, %rbx
	xorl	%r14d, %r14d
.LBB1_7:                                # =>This Inner Loop Header: Depth=1
	movl	32(%rsp,%r14,4), %edx
	movl	$.L.str.6, %edi
	movl	%r14d, %esi
	xorl	%eax, %eax
	callq	printf
	movl	32(%rsp,%r14,4), %ecx
	movl	$.L.str.7, %esi
	movq	%rbx, %rdi
	movl	%r14d, %edx
	xorl	%eax, %eax
	callq	fprintf
	incq	%r14
	cmpq	$10, %r14
	jne	.LBB1_7
# %bb.8:
	movq	%rbx, %rdi
	callq	fclose
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$134217816, %rsp                # imm = 0x8000058
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5histoPiS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z5histoPiS_S_,@object          # @_Z5histoPiS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z5histoPiS_S_
	.p2align	3, 0x0
_Z5histoPiS_S_:
	.quad	_Z20__device_stub__histoPiS_S_
	.size	_Z5histoPiS_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"input.txt"
	.size	.L.str, 10

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"r"
	.size	.L.str.1, 2

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"%d"
	.size	.L.str.2, 3

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"output.txt"
	.size	.L.str.4, 11

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"w"
	.size	.L.str.5, 2

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"\n%d => %d"
	.size	.L.str.6, 10

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"%d => %d\n"
	.size	.L.str.7, 10

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z5histoPiS_S_"
	.size	.L__unnamed_1, 15

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__histoPiS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z5histoPiS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z5histoPiS_S_          ; -- Begin function _Z5histoPiS_S_
	.globl	_Z5histoPiS_S_
	.p2align	8
	.type	_Z5histoPiS_S_,@function
_Z5histoPiS_S_:                         ; @_Z5histoPiS_S_
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	s_mov_b32 s5, 0
	global_load_b32 v4, v[2:3], off
                                        ; implicit-def: $vgpr2_vgpr3
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e32 4, v4
	s_xor_b32 s4, exec_lo, s2
	s_cbranch_execz .LBB0_20
; %bb.1:                                ; %NodeBlock50
	s_mov_b32 s8, 0
                                        ; implicit-def: $vgpr2_vgpr3
	s_mov_b32 s2, exec_lo
	v_cmpx_lt_i32_e32 6, v4
	s_xor_b32 s5, exec_lo, s2
	s_cbranch_execz .LBB0_13
; %bb.2:                                ; %NodeBlock48
	s_mov_b32 s2, 0
                                        ; implicit-def: $vgpr2_vgpr3
	s_mov_b32 s3, exec_lo
	v_cmpx_lt_i32_e32 7, v4
	s_xor_b32 s8, exec_lo, s3
	s_cbranch_execz .LBB0_10
; %bb.3:                                ; %NodeBlock46
	s_mov_b32 s9, 0
	s_mov_b32 s10, exec_lo
                                        ; implicit-def: $sgpr2_sgpr3
	v_cmpx_lt_i32_e32 8, v4
	s_xor_b32 s10, exec_lo, s10
	s_cbranch_execz .LBB0_7
; %bb.4:                                ; %LeafBlock44
	s_mov_b32 s11, exec_lo
                                        ; implicit-def: $sgpr2_sgpr3
	v_cmpx_eq_u32_e32 9, v4
; %bb.5:
	s_add_u32 s2, s0, 36
	s_mov_b32 s9, exec_lo
	s_addc_u32 s3, s1, 0
; %bb.6:                                ; %Flow104
	s_or_b32 exec_lo, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s9, s9, exec_lo
.LBB0_7:                                ; %Flow103
	s_or_saveexec_b32 s10, s10
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_xor_b32 exec_lo, exec_lo, s10
; %bb.8:
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_or_b32 s9, s9, exec_lo
; %bb.9:                                ; %Flow105
	s_or_b32 exec_lo, exec_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s9, exec_lo
.LBB0_10:                               ; %Flow102
	s_and_not1_saveexec_b32 s3, s8
; %bb.11:
	s_add_u32 s8, s0, 28
	s_addc_u32 s9, s1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, s9
	s_or_b32 s2, s2, exec_lo
; %bb.12:                               ; %Flow106
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s8, s2, exec_lo
                                        ; implicit-def: $vgpr4
.LBB0_13:                               ; %Flow101
	s_and_not1_saveexec_b32 s5, s5
	s_cbranch_execz .LBB0_19
; %bb.14:                               ; %NodeBlock42
	s_mov_b32 s9, exec_lo
                                        ; implicit-def: $sgpr2_sgpr3
	v_cmpx_lt_i32_e32 5, v4
	s_xor_b32 s9, exec_lo, s9
; %bb.15:
	s_add_u32 s2, s0, 24
	s_addc_u32 s3, s1, 0
; %bb.16:                               ; %Flow94
	s_or_saveexec_b32 s9, s9
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_xor_b32 exec_lo, exec_lo, s9
; %bb.17:
	s_add_u32 s2, s0, 20
	s_addc_u32 s3, s1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; %bb.18:                               ; %Flow95
	s_or_b32 exec_lo, exec_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s8, s8, exec_lo
.LBB0_19:                               ; %Flow107
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s5, s8, exec_lo
                                        ; implicit-def: $vgpr4
.LBB0_20:                               ; %Flow100
	s_and_not1_saveexec_b32 s4, s4
	s_cbranch_execz .LBB0_38
; %bb.21:                               ; %NodeBlock40
	s_mov_b32 s8, s5
                                        ; implicit-def: $vgpr2_vgpr3
	s_mov_b32 s2, exec_lo
	v_cmpx_lt_i32_e32 1, v4
	s_xor_b32 s9, exec_lo, s2
	s_cbranch_execz .LBB0_31
; %bb.22:                               ; %NodeBlock38
                                        ; implicit-def: $vgpr2_vgpr3
	s_mov_b32 s2, exec_lo
	v_cmpx_lt_i32_e32 2, v4
	s_xor_b32 s8, exec_lo, s2
	s_cbranch_execz .LBB0_28
; %bb.23:                               ; %NodeBlock36
	s_mov_b32 s10, exec_lo
                                        ; implicit-def: $sgpr2_sgpr3
	v_cmpx_lt_i32_e32 3, v4
	s_xor_b32 s10, exec_lo, s10
; %bb.24:
	s_add_u32 s2, s0, 16
	s_addc_u32 s3, s1, 0
; %bb.25:                               ; %Flow96
	s_or_saveexec_b32 s10, s10
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_xor_b32 exec_lo, exec_lo, s10
; %bb.26:
	s_add_u32 s2, s0, 12
	s_addc_u32 s3, s1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; %bb.27:                               ; %Flow97
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_28:                               ; %Flow98
	s_and_not1_saveexec_b32 s2, s8
; %bb.29:
	s_add_u32 s10, s0, 8
	s_addc_u32 s11, s1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11
; %bb.30:                               ; %Flow99
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s8, s5, exec_lo
                                        ; implicit-def: $vgpr4
.LBB0_31:                               ; %Flow109
	s_and_not1_saveexec_b32 s9, s9
	s_cbranch_execz .LBB0_37
; %bb.32:                               ; %NodeBlock
	s_mov_b32 s10, s8
	s_mov_b32 s11, exec_lo
                                        ; implicit-def: $sgpr2_sgpr3
	v_cmpx_lt_i32_e32 0, v4
	s_xor_b32 s11, exec_lo, s11
; %bb.33:
	s_add_u32 s2, s0, 4
	s_addc_u32 s3, s1, 0
	s_or_b32 s10, s8, exec_lo
                                        ; implicit-def: $vgpr4
; %bb.34:                               ; %Flow111
	s_or_saveexec_b32 s11, s11
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_xor_b32 exec_lo, exec_lo, s11
; %bb.35:                               ; %LeafBlock
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
	s_and_not1_b32 s2, s10, exec_lo
	s_and_b32 s3, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s10, s2, s3
; %bb.36:                               ; %Flow112
	s_or_b32 exec_lo, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s8, exec_lo
	s_and_b32 s3, s10, exec_lo
	s_or_b32 s8, s2, s3
.LBB0_37:                               ; %Flow110
	s_or_b32 exec_lo, exec_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s5, exec_lo
	s_and_b32 s3, s8, exec_lo
	s_or_b32 s5, s2, s3
.LBB0_38:                               ; %Flow108
	s_or_b32 exec_lo, exec_lo, s4
	s_and_saveexec_b32 s2, s5
	s_cbranch_execz .LBB0_40
; %bb.39:                               ; %.sink.split
	v_mov_b32_e32 v4, 1
	global_atomic_add_u32 v[2:3], v4, off
.LBB0_40:
	s_or_b32 exec_lo, exec_lo, s2
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	global_load_b32 v2, v[0:1], off
	s_mov_b32 s5, 0
                                        ; implicit-def: $vgpr0_vgpr1
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e32 4, v2
	s_xor_b32 s4, exec_lo, s2
	s_cbranch_execz .LBB0_60
; %bb.41:                               ; %NodeBlock72
	s_mov_b32 s6, 0
                                        ; implicit-def: $vgpr0_vgpr1
	s_mov_b32 s2, exec_lo
	v_cmpx_lt_i32_e32 6, v2
	s_xor_b32 s5, exec_lo, s2
	s_cbranch_execz .LBB0_53
; %bb.42:                               ; %NodeBlock70
	s_mov_b32 s2, 0
                                        ; implicit-def: $vgpr0_vgpr1
	s_mov_b32 s3, exec_lo
	v_cmpx_lt_i32_e32 7, v2
	s_xor_b32 s6, exec_lo, s3
	s_cbranch_execz .LBB0_50
; %bb.43:                               ; %NodeBlock68
	s_mov_b32 s7, 0
	s_mov_b32 s8, exec_lo
                                        ; implicit-def: $sgpr2_sgpr3
	v_cmpx_lt_i32_e32 8, v2
	s_xor_b32 s8, exec_lo, s8
	s_cbranch_execz .LBB0_47
; %bb.44:                               ; %LeafBlock66
	s_mov_b32 s9, exec_lo
                                        ; implicit-def: $sgpr2_sgpr3
	v_cmpx_eq_u32_e32 9, v2
; %bb.45:
	s_add_u32 s2, s0, 36
	s_mov_b32 s7, exec_lo
	s_addc_u32 s3, s1, 0
; %bb.46:                               ; %Flow85
	s_or_b32 exec_lo, exec_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s7, s7, exec_lo
.LBB0_47:                               ; %Flow84
	s_or_saveexec_b32 s8, s8
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_xor_b32 exec_lo, exec_lo, s8
; %bb.48:
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_or_b32 s7, s7, exec_lo
; %bb.49:                               ; %Flow86
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s7, exec_lo
.LBB0_50:                               ; %Flow83
	s_and_not1_saveexec_b32 s3, s6
; %bb.51:
	s_add_u32 s6, s0, 28
	s_addc_u32 s7, s1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
	s_or_b32 s2, s2, exec_lo
; %bb.52:                               ; %Flow87
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s6, s2, exec_lo
                                        ; implicit-def: $vgpr2
.LBB0_53:                               ; %Flow82
	s_and_not1_saveexec_b32 s5, s5
	s_cbranch_execz .LBB0_59
; %bb.54:                               ; %NodeBlock64
	s_mov_b32 s7, exec_lo
                                        ; implicit-def: $sgpr2_sgpr3
	v_cmpx_lt_i32_e32 5, v2
	s_xor_b32 s7, exec_lo, s7
; %bb.55:
	s_add_u32 s2, s0, 24
	s_addc_u32 s3, s1, 0
; %bb.56:                               ; %Flow
	s_or_saveexec_b32 s7, s7
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_xor_b32 exec_lo, exec_lo, s7
; %bb.57:
	s_add_u32 s2, s0, 20
	s_addc_u32 s3, s1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; %bb.58:                               ; %Flow76
	s_or_b32 exec_lo, exec_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s6, s6, exec_lo
.LBB0_59:                               ; %Flow88
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s5, s6, exec_lo
                                        ; implicit-def: $vgpr2
.LBB0_60:                               ; %Flow81
	s_and_not1_saveexec_b32 s4, s4
	s_cbranch_execz .LBB0_78
; %bb.61:                               ; %NodeBlock62
	s_mov_b32 s6, s5
                                        ; implicit-def: $vgpr0_vgpr1
	s_mov_b32 s2, exec_lo
	v_cmpx_lt_i32_e32 1, v2
	s_xor_b32 s7, exec_lo, s2
	s_cbranch_execz .LBB0_71
; %bb.62:                               ; %NodeBlock60
                                        ; implicit-def: $vgpr0_vgpr1
	s_mov_b32 s2, exec_lo
	v_cmpx_lt_i32_e32 2, v2
	s_xor_b32 s6, exec_lo, s2
	s_cbranch_execz .LBB0_68
; %bb.63:                               ; %NodeBlock58
	s_mov_b32 s8, exec_lo
                                        ; implicit-def: $sgpr2_sgpr3
	v_cmpx_lt_i32_e32 3, v2
	s_xor_b32 s8, exec_lo, s8
; %bb.64:
	s_add_u32 s2, s0, 16
	s_addc_u32 s3, s1, 0
; %bb.65:                               ; %Flow77
	s_or_saveexec_b32 s8, s8
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_xor_b32 exec_lo, exec_lo, s8
; %bb.66:
	s_add_u32 s2, s0, 12
	s_addc_u32 s3, s1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; %bb.67:                               ; %Flow78
	s_or_b32 exec_lo, exec_lo, s8
.LBB0_68:                               ; %Flow79
	s_and_not1_saveexec_b32 s2, s6
; %bb.69:
	s_add_u32 s8, s0, 8
	s_addc_u32 s9, s1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
; %bb.70:                               ; %Flow80
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s6, s5, exec_lo
                                        ; implicit-def: $vgpr2
.LBB0_71:                               ; %Flow90
	s_and_not1_saveexec_b32 s7, s7
	s_cbranch_execz .LBB0_77
; %bb.72:                               ; %NodeBlock56
	s_mov_b32 s8, s6
	s_mov_b32 s9, exec_lo
                                        ; implicit-def: $sgpr2_sgpr3
	v_cmpx_lt_i32_e32 0, v2
	s_xor_b32 s9, exec_lo, s9
; %bb.73:
	s_add_u32 s2, s0, 4
	s_addc_u32 s3, s1, 0
	s_or_b32 s8, s6, exec_lo
                                        ; implicit-def: $vgpr2
; %bb.74:                               ; %Flow92
	s_or_saveexec_b32 s9, s9
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_xor_b32 exec_lo, exec_lo, s9
; %bb.75:                               ; %LeafBlock54
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
	s_and_not1_b32 s0, s8, exec_lo
	s_and_b32 s1, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s8, s0, s1
; %bb.76:                               ; %Flow93
	s_or_b32 exec_lo, exec_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s6, exec_lo
	s_and_b32 s1, s8, exec_lo
	s_or_b32 s6, s0, s1
.LBB0_77:                               ; %Flow91
	s_or_b32 exec_lo, exec_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s5, exec_lo
	s_and_b32 s1, s6, exec_lo
	s_or_b32 s5, s0, s1
.LBB0_78:                               ; %Flow89
	s_or_b32 exec_lo, exec_lo, s4
	s_and_saveexec_b32 s0, s5
	s_cbranch_execz .LBB0_80
; %bb.79:                               ; %.sink.split26
	v_mov_b32_e32 v2, 1
	global_atomic_add_u32 v[0:1], v2, off
.LBB0_80:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5histoPiS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z5histoPiS_S_, .Lfunc_end0-_Z5histoPiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1304
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5histoPiS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z5histoPiS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
