//#include "bits/stdc++.h"
//#include<iostream>
//#include<string>
#include<stdio.h>
#include<stdlib.h>

extern "C"

//typedef struct testStruct{
//    int x;
//}testStruct;

__global__ void gpu(float* input, float* output, int* startPoints, int* endPoints, float* distancePoints){
	int block = blockIdx.x;
	output[block*3] = startPoints[block];
	output[block*3+1] = startPoints[block]+1;
	output[block*3+2] = distancePoints[block];

    for(int i1=startPoints[block];i1<endPoints[block];++i1){
        for(int i2=i1+1; i2<endPoints[block];++i2){
            float x_distance = powf(((float)input[i1*2] - (float)input[i2*2]),(float)2);
            float y_distance = powf(((float)input[(i1*2)+1] - (float)input[(i2*2)+1]),(float)2);
            float distance = sqrt(x_distance+y_distance);
            if(distance < output[block*3+2]){
                output[block*3] = (float)i1;
                output[block*3+1] = (float)i2;
                output[block*3+2] = distance;
                }
            }
        }
    }


	.file	"tmpxft_00303b95_00000000-6_gpu_test.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2029:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z31__device_stub__Z3gpuPfS_PiS0_S_PfS_PiS0_S_
	.type	_Z31__device_stub__Z3gpuPfS_PiS0_S_PfS_PiS0_S_, @function
_Z31__device_stub__Z3gpuPfS_PiS0_S_PfS_PiS0_S_:
.LFB2051:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	gpu(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2051:
	.size	_Z31__device_stub__Z3gpuPfS_PiS0_S_PfS_PiS0_S_, .-_Z31__device_stub__Z3gpuPfS_PiS0_S_PfS_PiS0_S_
	.globl	gpu
	.type	gpu, @function
gpu:
.LFB2052:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z3gpuPfS_PiS0_S_PfS_PiS0_S_
	.cfi_endproc
.LFE2052:
	.size	gpu, .-gpu
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"gpu"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	gpu(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2054:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

//#include "bits/stdc++.h"
//#include<iostream>
//#include<string>

#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>

extern "C"

//typedef struct testStruct{
//    int x;
//}testStruct;

__global__ void gpu(float* input, float* output, int* startPoints, int* endPoints, float* distancePoints){
	int block = blockIdx.x;
	output[block*3] = startPoints[block];
	output[block*3+1] = startPoints[block]+1;
	output[block*3+2] = distancePoints[block];

    for(int i1=startPoints[block];i1<endPoints[block];++i1){
        for(int i2=i1+1; i2<endPoints[block];++i2){
            float x_distance = powf(((float)input[i1*2] - (float)input[i2*2]),(float)2);
            float y_distance = powf(((float)input[(i1*2)+1] - (float)input[(i2*2)+1]),(float)2);
            float distance = sqrt(x_distance+y_distance);
            if(distance < output[block*3+2]){
                output[block*3] = (float)i1;
                output[block*3+1] = (float)i2;
                output[block*3+2] = distance;
                }
            }
        }
    }


	.text
	.file	"gpu_test.hip"
	.globl	__device_stub__gpu              # -- Begin function __device_stub__gpu
	.type	__device_stub__gpu,@function
__device_stub__gpu:                     # @__device_stub__gpu
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$gpu, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__gpu, .Lfunc_end0-__device_stub__gpu
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$gpu, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	gpu,@object                     # @gpu
	.section	.rodata,"a",@progbits
	.globl	gpu
	.p2align	3, 0x0
gpu:
	.quad	__device_stub__gpu
	.size	gpu, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"gpu"
	.size	.L__unnamed_1, 4

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__gpu
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym gpu
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	gpu                     ; -- Begin function gpu
	.globl	gpu
	.p2align	8
	.type	gpu,@function
gpu:                                    ; @gpu
; %bb.0:
	s_mov_b32 s4, s15
	s_load_b256 s[8:15], s[0:1], 0x0
	s_ashr_i32 s5, s4, 31
	v_mov_b32_e32 v3, 0
	s_lshl_b64 s[16:17], s[4:5], 2
	s_mul_i32 s4, s4, 3
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s12, s16
	s_addc_u32 s3, s13, s17
	s_load_b32 s2, s[2:3], 0x0
	s_load_b64 s[0:1], s[0:1], 0x20
	s_ashr_i32 s5, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[4:5], 2
	s_add_u32 s6, s10, s4
	s_addc_u32 s7, s11, s5
	s_waitcnt lgkmcnt(0)
	s_add_i32 s3, s2, 1
	v_cvt_f32_i32_e32 v0, s2
	v_cvt_f32_i32_e32 v1, s3
	s_add_u32 s0, s0, s16
	s_addc_u32 s1, s1, s17
	global_store_b64 v3, v[0:1], s[6:7]
	global_load_b32 v0, v3, s[0:1]
	s_add_u32 s0, s14, s16
	s_addc_u32 s1, s15, s17
	s_load_b32 s5, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_i32 s2, s5
	s_waitcnt vmcnt(0)
	global_store_b32 v3, v0, s[6:7] offset:8
	s_cbranch_scc1 .LBB0_9
; %bb.1:                                ; %.lr.ph53.preheader
	s_lshl_b32 s0, s2, 1
	s_mov_b32 s15, 0x3e76c4e1
	s_add_i32 s14, s0, 2
.LBB0_2:                                ; %.lr.ph53
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
	s_add_i32 s16, s2, 1
	s_mov_b32 s0, -1
	s_cmp_ge_i32 s16, s5
	s_cbranch_scc1 .LBB0_8
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_lshl_b32 s0, s2, 1
	v_cvt_f32_i32_e32 v0, s2
	s_ashr_i32 s1, s0, 31
	s_mov_b32 s10, s14
	s_lshl_b64 s[0:1], s[0:1], 2
	s_mov_b32 s17, s16
	s_add_u32 s12, s8, s0
	s_addc_u32 s13, s9, s1
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_ashr_i32 s11, s10, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[10:11], 2
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	s_clause 0x2
	global_load_b64 v[1:2], v3, s[0:1]
	global_load_b64 v[4:5], v3, s[12:13]
	global_load_b32 v6, v3, s[6:7] offset:8
	s_waitcnt vmcnt(1)
	v_dual_sub_f32 v1, v4, v1 :: v_dual_sub_f32 v2, v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_frexp_mant_f32_e64 v4, |v1|
	v_frexp_mant_f32_e64 v5, |v2|
	v_frexp_exp_i32_f32_e32 v20, v2
	v_cmp_class_f32_e64 s11, v1, 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v4
	v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v5
	v_cndmask_b32_e64 v7, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v8, 0, 1, s0
	v_ldexp_f32 v4, v4, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v5, v5, v8
	v_dual_add_f32 v7, 1.0, v4 :: v_dual_add_f32 v8, 1.0, v5
	v_dual_add_f32 v11, -1.0, v4 :: v_dual_add_f32 v12, -1.0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v9, v7
	v_rcp_f32_e32 v10, v8
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v13, v11, v9 :: v_dual_mul_f32 v14, v12, v10
	v_add_f32_e32 v15, -1.0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v17, -1.0, v8 :: v_dual_mul_f32 v16, v7, v13
	v_mul_f32_e32 v18, v8, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v4, v4, v15 :: v_dual_sub_f32 v5, v5, v17
	v_fma_f32 v7, v13, v7, -v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, v14, v8, -v18
	v_dual_fmac_f32 v7, v13, v4 :: v_dual_fmac_f32 v8, v14, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v4, v16, v7 :: v_dual_add_f32 v5, v18, v8
	v_dual_sub_f32 v15, v11, v4 :: v_dual_sub_f32 v18, v5, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v16, v4, v16 :: v_dual_sub_f32 v11, v11, v15
	v_sub_f32_e32 v17, v12, v5
	v_dual_sub_f32 v7, v16, v7 :: v_dual_sub_f32 v8, v18, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v11, v4
	v_add_f32_e32 v4, v7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v15, v4
	v_mul_f32_e32 v4, v9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v12, v12, v17 :: v_dual_add_f32 v7, v13, v4
	v_sub_f32_e32 v5, v12, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v11, v7, v7
	v_add_f32_e32 v5, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v17, v5
	v_mul_f32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v14, v5
	v_dual_sub_f32 v9, v7, v13 :: v_dual_sub_f32 v10, v8, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v4, v4, v9 :: v_dual_sub_f32 v5, v5, v10
	v_mul_f32_e32 v9, v8, v8
	v_fma_f32 v10, v7, v7, -v11
	v_add_f32_e32 v14, v5, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v13, v8, v8, -v9
	v_fmac_f32_e32 v13, v8, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v14, v9, v13
	v_dual_add_f32 v12, v4, v4 :: v_dual_sub_f32 v9, v14, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v7, v12
	v_fmaak_f32 v16, s15, v14, 0x3e91f4c4
	v_fmaak_f32 v16, v14, v16, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v12, v11, v10 :: v_dual_sub_f32 v9, v13, v9
	v_fmaak_f32 v15, s15, v12, 0x3e91f4c4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v18, v14, v16 :: v_dual_sub_f32 v11, v12, v11
	v_fmaak_f32 v15, v12, v15, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v13, v14, v16, -v18
	v_sub_f32_e32 v10, v10, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v17, v12, v15
	v_fmac_f32_e32 v13, v9, v16
	v_dual_mul_f32 v16, v7, v12 :: v_dual_mul_f32 v21, v8, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v11, v12, v15, -v17
	v_add_f32_e32 v22, v18, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v23, v12, v7, -v16
	v_fma_f32 v25, v14, v8, -v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v11, v10, v15 :: v_dual_add_f32 v26, 0x3f2aaaaa, v22
	v_dual_sub_f32 v18, v22, v18 :: v_dual_fmac_f32 v23, v12, v4
	v_frexp_exp_i32_f32_e32 v15, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v19, v17, v11
	v_ldexp_f32 v4, v4, 1
	v_dual_sub_f32 v12, v13, v18 :: v_dual_sub_f32 v17, v19, v17
	v_dual_add_f32 v24, 0x3f2aaaaa, v19 :: v_dual_fmac_f32 v25, v14, v5
	v_ldexp_f32 v5, v5, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v11, v11, v17
	v_fmac_f32_e32 v25, v9, v8
	v_fmac_f32_e32 v23, v10, v7
	v_add_f32_e32 v13, 0xbf2aaaaa, v26
	v_add_f32_e32 v17, 0xbf2aaaaa, v24
	v_dual_add_f32 v11, 0x31739010, v11 :: v_dual_add_f32 v10, 0x31739010, v12
	v_ldexp_f32 v7, v7, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v12, v22, v13
	v_sub_f32_e32 v17, v19, v17
	v_subrev_co_ci_u32_e32 v13, vcc_lo, 0, v15, vcc_lo
	v_subrev_co_ci_u32_e64 v14, vcc_lo, 0, v20, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v9, v10, v12 :: v_dual_add_f32 v10, v16, v23
	v_add_f32_e32 v11, v11, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v13, v13
	v_ldexp_f32 v8, v8, 1
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v1
	v_sub_f32_e32 v16, v10, v16
	v_add_f32_e32 v12, v24, v11
	v_sub_f32_e32 v18, v24, v12
	v_mul_f32_e32 v19, v10, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v11, v11, v18
	v_fma_f32 v18, v10, v12, -v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v18, v10, v11 :: v_dual_add_f32 v17, v21, v25
	v_sub_f32_e32 v21, v17, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v10, v25, v21
	v_dual_add_f32 v15, v26, v9 :: v_dual_sub_f32 v16, v23, v16
	v_sub_f32_e32 v20, v26, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v18, v16, v12
	v_mul_f32_e32 v22, v17, v15
	v_add_f32_e32 v9, v9, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v20, v17, v15, -v22
	v_fmac_f32_e32 v20, v17, v9
	v_add_f32_e32 v12, v19, v18
	v_cvt_f32_i32_e32 v9, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v20, v10, v15 :: v_dual_mul_f32 v11, 0x3f317218, v13
	v_dual_add_f32 v16, v7, v12 :: v_dual_sub_f32 v17, v12, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v10, 0x3f317218, v9
	v_add_f32_e32 v14, v22, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v15, 0x3f317218, v13, -v11
	v_sub_f32_e32 v17, v18, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v19, v8, v14
	v_dual_sub_f32 v21, v14, v22 :: v_dual_sub_f32 v8, v19, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v8, v14, v8
	v_sub_f32_e32 v18, v20, v21
	v_fma_f32 v20, 0x3f317218, v9, -v10
	v_sub_f32_e32 v7, v16, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v4, v4, v17 :: v_dual_add_f32 v5, v5, v18
	v_dual_fmac_f32 v20, 0xb102e308, v9 :: v_dual_sub_f32 v7, v12, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, v5, v8
	v_add_f32_e32 v8, v10, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v4, v4, v7
	v_add_f32_e32 v12, v19, v5
	v_fmac_f32_e32 v15, 0xb102e308, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v9, v16, v4
	v_sub_f32_e32 v10, v8, v10
	v_dual_add_f32 v14, v8, v12 :: v_dual_add_f32 v7, v11, v15
	v_sub_f32_e32 v18, v12, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v10, v20, v10 :: v_dual_sub_f32 v17, v14, v8
	v_sub_f32_e32 v11, v7, v11
	v_add_f32_e32 v13, v7, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v19, v14, v17
	v_sub_f32_e32 v11, v15, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v15, v9, v16 :: v_dual_sub_f32 v8, v8, v19
	v_sub_f32_e32 v4, v4, v15
	v_sub_f32_e32 v12, v12, v17
	v_sub_f32_e32 v16, v13, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v8, v12, v8 :: v_dual_sub_f32 v5, v5, v18
	v_sub_f32_e32 v15, v13, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v7, v7, v15
	v_add_f32_e32 v15, v11, v4
	v_dual_sub_f32 v9, v9, v16 :: v_dual_add_f32 v16, v10, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v12, v16, v10
	v_dual_add_f32 v8, v16, v8 :: v_dual_add_f32 v7, v9, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v5, v5, v12
	v_add_f32_e32 v17, v14, v8
	v_sub_f32_e32 v9, v15, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v7, v15, v7
	v_sub_f32_e32 v15, v15, v9
	v_sub_f32_e32 v4, v4, v9
	v_dual_sub_f32 v9, v16, v12 :: v_dual_sub_f32 v12, v17, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v9, v10, v9 :: v_dual_sub_f32 v8, v8, v12
	v_add_f32_e32 v16, v13, v7
	v_dual_sub_f32 v11, v11, v15 :: v_dual_sub_f32 v10, v16, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v4, v4, v11 :: v_dual_sub_f32 v7, v7, v10
	v_dual_add_f32 v4, v4, v7 :: v_dual_add_f32 v5, v5, v9
	v_cndmask_b32_e64 v7, 2.0, 1.0, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v5, v5, v8 :: v_dual_mul_f32 v22, 0.5, v7
	v_add_f32_e32 v8, v16, v4
	v_cndmask_b32_e64 v10, 2.0, 1.0, vcc_lo
	v_trunc_f32_e32 v21, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v11, v8, v16
	v_mul_f32_e32 v12, v7, v8
	v_cmp_eq_f32_e64 s0, v21, v7
	v_trunc_f32_e32 v21, v22
	v_trunc_f32_e32 v24, v10
	v_sub_f32_e32 v4, v4, v11
	v_fma_f32 v8, v7, v8, -v12
	v_add_f32_e32 v9, v17, v5
	v_cmp_class_f32_e64 vcc_lo, v12, 0x204
	v_cmp_neq_f32_e64 s2, v21, v22
	v_cmp_eq_f32_e64 s1, v24, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v8, v7, v4 :: v_dual_sub_f32 v13, v9, v17
	v_mul_f32_e32 v14, v10, v9
	s_and_b32 s2, s0, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v4, v12, v8 :: v_dual_sub_f32 v5, v5, v13
	v_fma_f32 v9, v10, v9, -v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v11, v4, v12, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v14, 0x204
	v_dual_fmac_f32 v9, v10, v5 :: v_dual_sub_f32 v4, v4, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_neq_f32_e64 s3, 0x7f800000, |v11|
	v_dual_add_f32 v5, v14, v9 :: v_dual_sub_f32 v4, v8, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v13, v5, v14, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v11
	v_cndmask_b32_e64 v4, 0, v4, s3
	v_sub_f32_e32 v5, v5, v14
	v_cndmask_b32_e64 v15, 0, 0x37000000, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v17, v11, v15
	v_add_f32_e32 v4, v15, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v20, 0x3fb8aa3b, v17
	v_fma_f32 v25, 0x3fb8aa3b, v17, -v20
	v_rndne_f32_e32 v26, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v25, 0x32a5705f, v17 :: v_dual_sub_f32 v20, v20, v26
	v_cvt_i32_f32_e32 v8, v26
	v_add_f32_e32 v20, v20, v25
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v13
	v_cmp_neq_f32_e64 s3, 0x7f800000, |v13|
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v12, v20
	v_cndmask_b32_e64 v16, 0, 0x37000000, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0, v1
	v_sub_f32_e32 v18, v13, v16
	v_sub_f32_e32 v5, v9, v5
	v_cndmask_b32_e64 v19, 0x7f800000, 0, vcc_lo
	s_or_b32 vcc_lo, vcc_lo, s11
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v8, v12, v8
	v_mul_f32_e32 v23, 0x3fb8aa3b, v18
	v_cndmask_b32_e64 v5, 0, v5, s3
	v_cmp_ngt_f32_e64 s3, 0xc2ce8ed0, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v28, 0x3fb8aa3b, v18, -v23
	v_rndne_f32_e32 v29, v23
	v_cndmask_b32_e64 v8, 0, v8, s3
	v_cmp_ngt_f32_e64 s3, 0xc2ce8ed0, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v5, v16, v5 :: v_dual_fmac_f32 v28, 0x32a5705f, v18
	v_sub_f32_e32 v7, v23, v29
	v_cvt_i32_f32_e32 v9, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v7, v28
	v_exp_f32_e32 v7, v7
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v7, v7, v9
	v_cndmask_b32_e64 v9, 1.0, v1, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v7, 0, v7, s3
	v_cmp_nlt_f32_e64 s3, 0x42b17218, v17
	v_cndmask_b32_e64 v8, 0x7f800000, v8, s3
	v_cmp_nlt_f32_e64 s3, 0x42b17218, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v4, v8, v4, v8
	v_cmp_eq_f32_e64 s4, 0x7f800000, v8
	v_cndmask_b32_e64 v7, 0x7f800000, v7, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v4, v4, v8, s4
	v_cndmask_b32_e64 v8, 0, v1, s2
	v_fma_f32 v5, v7, v5, v7
	v_cmp_eq_f32_e64 s4, 0x7f800000, v7
	v_cmp_class_f32_e64 s2, v2, 0x204
	v_bfi_b32 v4, 0x7fffffff, v4, v9
	v_bfi_b32 v8, 0x7fffffff, v19, v8
	v_mul_f32_e32 v27, 0.5, v10
	v_cndmask_b32_e64 v5, v5, v7, s4
	v_cmp_eq_f32_e64 s4, 0, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_trunc_f32_e32 v10, v27
	v_cndmask_b32_e64 v7, 0x7f800000, 0, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_neq_f32_e64 s3, v10, v27
	s_and_b32 s3, s1, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v10, 1.0, v2, s3
	v_cndmask_b32_e64 v9, 0, v2, s3
	v_bfi_b32 v5, 0x7fffffff, v5, v10
	v_cndmask_b32_e64 v10, 0x7fc00000, v4, s0
	v_cmp_gt_f32_e64 s0, 0, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_bfi_b32 v7, 0x7fffffff, v7, v9
	v_cndmask_b32_e64 v11, 0x7fc00000, v5, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v4, v4, v10, s0
	v_cmp_gt_f32_e64 s0, 0, v2
	v_cndmask_b32_e32 v4, v4, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v5, v5, v11, s0
	s_or_b32 vcc_lo, s4, s2
	v_cndmask_b32_e32 v5, v5, v7, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v1, v1
	v_cndmask_b32_e32 v1, 0x7fc00000, v4, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v2, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, 0x7fc00000, v5, vcc_lo
	v_add_f32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v2, 0x4f800000, v1
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v1
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v2, v1
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v4, -1, v2
	v_add_nc_u32_e32 v5, 1, v2
	v_fma_f32 v7, -v4, v2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v8, -v5, v2, v1
	v_cmp_ge_f32_e64 s0, 0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v2, v2, v4, s0
	v_cmp_lt_f32_e64 s0, 0, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v2, v2, v5, s0
	v_mul_f32_e32 v4, 0x37800000, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, v2, v4, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v1, 0x260
	v_cndmask_b32_e32 v2, v2, v1, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_nlt_f32_e32 vcc_lo, v2, v6
	s_cbranch_vccnz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=2
	v_cvt_f32_i32_e32 v1, s17
	global_store_b96 v3, v[0:2], s[6:7]
.LBB0_6:                                ;   in Loop: Header=BB0_4 Depth=2
	s_add_i32 s17, s17, 1
	s_add_i32 s10, s10, 2
	s_cmp_ge_i32 s17, s5
	s_cbranch_scc0 .LBB0_4
; %bb.7:                                ; %.loopexit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s14, s14, 2
	s_mov_b32 s0, 0
.LBB0_8:                                ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_mov_b32 s2, s16
	s_cbranch_vccz .LBB0_2
.LBB0_9:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel gpu
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 30
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	gpu, .Lfunc_end0-gpu
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2568
; NumSgprs: 20
; NumVgprs: 30
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 30
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           gpu
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         gpu.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     30
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
