__device__ float magnitude(const float *r) {
  return pow((r[0] * r[0]) + (r[1] * r[1]) + (r[2] * r[2]), 0.5);
}

__device__ float magnitude_withId(const float *r) {
  const int i = blockIdx.x;
  return pow((r[3 * i] * r[3 * i]) + (r[3 * i + 1] * r[3 * i + 1]) +
                 (r[3 * i + 2] * r[3 * i + 2]),
             0.5);
}

__device__ float clamp(float x, float max_v, float min_v) {
  return max(min_v, min(max_v, x));
}

__device__ float WPoly6(const float mag, const float *h,
                        const float *WPoly6_const) {
  if (mag < *h && mag > 0) {
    float inner_val = ((*h * *h) - (mag * mag));
    return inner_val * inner_val * inner_val * *WPoly6_const;
  } else
    return 0;
}

__device__ void grad_WPoly6(float *grad, float *r, const float mag,
                            const float *h, const float *grad_WPoly6_const) {
  float inner_val = ((*h * *h) - (mag * mag));
  inner_val =
      inner_val * inner_val * *grad_WPoly6_const * (1 / (mag + 0.000001f));
  grad[0] = inner_val * r[0];
  grad[1] = inner_val * r[1];
  grad[2] = inner_val * r[2];
}

__device__ float lap_WPoly6(const float *h, const float mag,
                            const float *lap_WPoly6_const) {
  float inner_val = ((*h * *h) - (mag * mag));
  return *lap_WPoly6_const * inner_val * ((3 * *h * *h) - (7 * mag * mag));
}

__device__ float Wspiky(const float *h, const float mag,
                        const float *Wpiky_const) {
  if (mag < *h && mag > 0) {
    return *Wpiky_const * (*h - mag) * (*h - mag) * (*h - mag);
  } else {
    return 0;
  }
}

__device__ void grad_WSpiky(float *grad, const float mag, const float *r,
                            const float *h, const float *grad_Wspiky_const) {
  float inner_val =
      *grad_Wspiky_const * (*h - mag) * (*h - mag) * (1 / (mag + 0.0000001f));
  grad[0] = r[0] * inner_val;
  grad[1] = r[1] * inner_val;
  grad[2] = r[2] * inner_val;
}

__device__ float Wviscosity(const float *h, const float mag,
                            const float *Wviscosity_const) {
  float inner_val = ((-mag * mag * mag) / (2 * *h * *h * *h)) +
                    ((mag * mag) / (*h * *h)) + (*h / (2 * mag + 0.0000001f)) -
                    1;
  return inner_val * *Wviscosity_const;
}

__device__ float lap_Wviscosity(const float mag, const float *h,
                                const float *lap_Wviscosity_const) {
  return *lap_Wviscosity_const * (*h - mag);
}

__device__ void pressure_force(float *press_force, const float *mass,
                               const float mag, const float *r, const float *h,
                               const float *density_n, const int *neighbors,
                               const float *rest_density, const float *k,
                               const float *grad_Wspiky_const) {
  const int i = neighbors[blockIdx.x * blockDim.x + threadIdx.x];
  float grad[3];
  grad_WSpiky(grad, mag, r, h, grad_Wspiky_const);
  float const_val = *mass * *k *
                    (density_n[blockIdx.x] + density_n[i] - 2 * *rest_density) *
                    1 / (2 * density_n[i]);
  press_force[0] = const_val * grad[0];
  press_force[1] = const_val * grad[1];
  press_force[2] = const_val * grad[2];
}

__device__ void viscosity_force(float *visc_force, const float *eta,
                                const float *mass, const float mag,
                                const float *h, const float *density_n,
                                const float *vel_n, const int *neighbors,
                                const float *lap_Wviscosity_const) {

  const int i = neighbors[blockIdx.x * blockDim.x + threadIdx.x];
  float const_val = *eta * *mass * (1 / (density_n[i] + 0.0000001f)) *
                    lap_Wviscosity(mag, h, lap_Wviscosity_const);
  visc_force[0] = const_val * (vel_n[3 * i] - vel_n[3 * blockIdx.x]);
  visc_force[1] = const_val * (vel_n[3 * i + 1] - vel_n[3 * blockIdx.x + 1]);
  visc_force[2] = const_val * (vel_n[3 * i + 2] - vel_n[3 * blockIdx.x + 2]);
}

__device__ void color_field_grad(float *color_field_grad_val, const float *mass,
                                 const float *density_n, float *r_dash,
                                 const int *neighbors, const float *h,
                                 const float mag,
                                 const float *grad_WPoly6_const) {
  const int i = neighbors[blockIdx.x * blockDim.x + threadIdx.x];
  float inner_val = *mass * 1 / (density_n[i] + 0.0000001f);
  float grad_Wpoly[3];
  grad_WPoly6(grad_Wpoly, r_dash, mag, h, grad_WPoly6_const);
  color_field_grad_val[blockIdx.x * blockDim.x * 3 + 3 * threadIdx.x] =
      grad_Wpoly[0] * inner_val;
  color_field_grad_val[blockIdx.x * blockDim.x * 3 + 3 * threadIdx.x + 1] =
      grad_Wpoly[1] * inner_val;
  color_field_grad_val[blockIdx.x * blockDim.x * 3 + 3 * threadIdx.x + 2] =
      grad_Wpoly[2] * inner_val;
}

__device__ void color_field_lap(float *color_field_lap_val, const float *mass,
                                const float *density_n, const float *r,
                                const int *neighbors, const float *h,
                                const float mag,
                                const float *lap_WPoly6_const) {
  const int i = blockIdx.x * blockDim.x + threadIdx.x;
  color_field_lap_val[i] = *mass * 1 / (density_n[neighbors[i]] + 0.0000001f) *
                           lap_WPoly6(h, mag, lap_WPoly6_const);
}

__global__ void calc_density(float *density, const float *r1,
                             const int *neighbors, const float *mass,
                             const float *h, const float *WPoly6_const) {
  float r_dash[3];
  const int i = threadIdx.x;
  const int j = blockIdx.x;
  const int n = j * blockDim.x + i;
  r_dash[0] = r1[3 * j] - r1[3 * neighbors[n]];
  r_dash[1] = r1[3 * j + 1] - r1[3 * neighbors[n] + 1];
  r_dash[2] = r1[3 * j + 2] - r1[3 * neighbors[n] + 2];
  const float mag = magnitude(r_dash);
  density[n] = WPoly6(mag, h, WPoly6_const) * *mass;
}

__global__ void
calc_forces(float *force, float *color_field_lap_val,
            float *color_field_grad_val, const float *r1,
            const float *density_n, float *vel_n, int *neighbors,
            const float *h, const float *eta, const float *mass,
            const float *rest_density, const float *k,
            const float *grad_WPoly6_const, const float *lap_WPoly6_const,
            const float *Wspiky_const, const float *grad_Wspiky_const,
            const float *Wviscosity_const, const float *lap_Wviscosity_const) {

  const int i = threadIdx.x;
  const int j = blockIdx.x;
  const int n = j * blockDim.x + i;

  float r_dash[3], press_force[3], visc_force[3];
  r_dash[0] = r1[3 * j] - r1[3 * neighbors[n]];
  r_dash[1] = r1[3 * j + 1] - r1[3 * neighbors[n] + 1];
  r_dash[2] = r1[3 * j + 1] - r1[3 * neighbors[n] + 2];
  float mag = magnitude(r_dash);
  if (mag > 0.000001f && mag < *h) {
    pressure_force(press_force, mass, mag, r_dash, h, density_n, neighbors,
                   rest_density, k, grad_Wspiky_const);
    viscosity_force(visc_force, eta, mass, mag, h, density_n, vel_n, neighbors,
                    lap_Wviscosity_const);
    color_field_grad(color_field_grad_val, mass, density_n, r_dash, neighbors,
                     h, mag, grad_WPoly6_const);
    color_field_lap(color_field_lap_val, mass, density_n, r_dash, neighbors, h,
                    mag, lap_WPoly6_const);
    force[blockIdx.x * blockDim.x * 3 + 3 * i] =
        clamp(press_force[0] + visc_force[0], 200, -200);
    force[blockIdx.x * blockDim.x * 3 + 3 * i + 1] =
        clamp(press_force[1] + visc_force[1], 200, -200);
    force[blockIdx.x * blockDim.x * 3 + 3 * i + 2] =
        clamp(press_force[2] + visc_force[2], 200, -200);
  } else {
    force[blockIdx.x * blockDim.x * 3 + 3 * i] = 0;
    force[blockIdx.x * blockDim.x * 3 + 3 * i + 1] = 0;
    force[blockIdx.x * blockDim.x * 3 + 3 * i + 2] = 0;
    color_field_grad_val[blockIdx.x * blockDim.x * 3 + 3 * i] = 0;
    color_field_grad_val[blockIdx.x * blockDim.x * 3 + 3 * i + 1] = 0;
    color_field_grad_val[blockIdx.x * blockDim.x * 3 + 3 * i + 2] = 0;
    color_field_lap_val[blockIdx.x * blockDim.x + threadIdx.x] = 0;
  }
}

__global__ void update_pos(float *r, float *vel_p, float *force,
                           const float *threshold, const float *mass,
                           const float *time, const float *sigma,
                           const float *Width, const float *damping,
                           const float *eps, const float *color_field_lap_val,
                           const float *color_field_grad_val) {
  const int i = blockIdx.x;
  float gradient_length = magnitude_withId(color_field_grad_val);
  float force_surface[3] = {0, 0, 0};

  if (gradient_length >= *threshold) {
    float const_val = -1 * *sigma * color_field_lap_val[i] *
                      (1 / (gradient_length + 0.0000001f));
    force_surface[0] = const_val * color_field_grad_val[3 * i];
    force_surface[1] = const_val * color_field_grad_val[3 * i + 1];
    force_surface[2] = const_val * color_field_grad_val[3 * i + 2];
  }

  vel_p[3 * i] += clamp(
      (force[3 * i] + force_surface[0]) * (1 / (*mass)) * *time, 200, -200);
  vel_p[3 * i + 1] += clamp(
      (force[3 * i + 1] + force_surface[1]) * (1 / (*mass)) * *time, 200, -200);
  vel_p[3 * i + 2] += clamp(
      (((force[3 * i + 2] + force_surface[2]) * 1 / (*mass)) - 10 * 12000) *
          *time,
      200, -200);

  r[3 * i] += vel_p[3 * i] * *time;
  r[3 * i + 1] += vel_p[3 * i + 1] * *time;
  r[3 * i + 2] += vel_p[3 * i + 2] * *time;

  if (r[3 * i] < -*Width) {
    r[3 * i] = -*Width + *eps;
    vel_p[3 * i] = *damping * vel_p[3 * i];
  }
  if (r[3 * i + 1] < -*Width) {
    r[3 * i + 1] = -*Width + *eps;
    vel_p[3 * i + 1] = *damping * vel_p[3 * i + 1];
  }
  if (r[3 * i + 2] < -*Width) {
    r[3 * i + 2] = -*Width + *eps;
    vel_p[3 * i + 2] = *damping * vel_p[3 * i + 2];
  }
  if (r[3 * i] > *Width) {
    r[3 * i] = *Width - *eps;
    vel_p[3 * i] = *damping * vel_p[3 * i];
  }
  if (r[3 * i + 1] > *Width) {
    r[3 * i + 1] = *Width - *eps;
    vel_p[3 * i + 1] = *damping * vel_p[3 * i + 1];
  }
  if (r[3 * i + 2] > *Width) {
    r[3 * i + 2] = *Width * 10 - *eps;
    vel_p[3 * i + 2] = *damping * vel_p[3 * i + 2];
  }
}

	.file	"tmpxft_00235aaa_00000000-6_source.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2024:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2024:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z9magnitudePKf
	.type	_Z9magnitudePKf, @function
_Z9magnitudePKf:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z9magnitudePKf, .-_Z9magnitudePKf
	.globl	_Z16magnitude_withIdPKf
	.type	_Z16magnitude_withIdPKf, @function
_Z16magnitude_withIdPKf:
.LFB2170:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z9magnitudePKf
	.cfi_endproc
.LFE2170:
	.size	_Z16magnitude_withIdPKf, .-_Z16magnitude_withIdPKf
	.globl	_Z5clampfff
	.type	_Z5clampfff, @function
_Z5clampfff:
.LFB2010:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2010:
	.size	_Z5clampfff, .-_Z5clampfff
	.globl	_Z6WPoly6fPKfS0_
	.type	_Z6WPoly6fPKfS0_, @function
_Z6WPoly6fPKfS0_:
.LFB2011:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2011:
	.size	_Z6WPoly6fPKfS0_, .-_Z6WPoly6fPKfS0_
	.globl	_Z11grad_WPoly6PfS_fPKfS1_
	.type	_Z11grad_WPoly6PfS_fPKfS1_, @function
_Z11grad_WPoly6PfS_fPKfS1_:
.LFB2012:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2012:
	.size	_Z11grad_WPoly6PfS_fPKfS1_, .-_Z11grad_WPoly6PfS_fPKfS1_
	.globl	_Z10lap_WPoly6PKffS0_
	.type	_Z10lap_WPoly6PKffS0_, @function
_Z10lap_WPoly6PKffS0_:
.LFB2013:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2013:
	.size	_Z10lap_WPoly6PKffS0_, .-_Z10lap_WPoly6PKffS0_
	.globl	_Z6WspikyPKffS0_
	.type	_Z6WspikyPKffS0_, @function
_Z6WspikyPKffS0_:
.LFB2174:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2174:
	.size	_Z6WspikyPKffS0_, .-_Z6WspikyPKffS0_
	.globl	_Z11grad_WSpikyPffPKfS1_S1_
	.type	_Z11grad_WSpikyPffPKfS1_S1_, @function
_Z11grad_WSpikyPffPKfS1_S1_:
.LFB2015:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2015:
	.size	_Z11grad_WSpikyPffPKfS1_S1_, .-_Z11grad_WSpikyPffPKfS1_S1_
	.globl	_Z10WviscosityPKffS0_
	.type	_Z10WviscosityPKffS0_, @function
_Z10WviscosityPKffS0_:
.LFB2176:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2176:
	.size	_Z10WviscosityPKffS0_, .-_Z10WviscosityPKffS0_
	.globl	_Z14lap_WviscosityfPKfS0_
	.type	_Z14lap_WviscosityfPKfS0_, @function
_Z14lap_WviscosityfPKfS0_:
.LFB2172:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2172:
	.size	_Z14lap_WviscosityfPKfS0_, .-_Z14lap_WviscosityfPKfS0_
	.globl	_Z14pressure_forcePfPKffS1_S1_S1_PKiS1_S1_S1_
	.type	_Z14pressure_forcePfPKffS1_S1_S1_PKiS1_S1_S1_, @function
_Z14pressure_forcePfPKffS1_S1_S1_PKiS1_S1_S1_:
.LFB2018:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2018:
	.size	_Z14pressure_forcePfPKffS1_S1_S1_PKiS1_S1_S1_, .-_Z14pressure_forcePfPKffS1_S1_S1_PKiS1_S1_S1_
	.globl	_Z15viscosity_forcePfPKfS1_fS1_S1_S1_PKiS1_
	.type	_Z15viscosity_forcePfPKfS1_fS1_S1_S1_PKiS1_, @function
_Z15viscosity_forcePfPKfS1_fS1_S1_S1_PKiS1_:
.LFB2019:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2019:
	.size	_Z15viscosity_forcePfPKfS1_fS1_S1_S1_PKiS1_, .-_Z15viscosity_forcePfPKfS1_fS1_S1_S1_PKiS1_
	.globl	_Z16color_field_gradPfPKfS1_S_PKiS1_fS1_
	.type	_Z16color_field_gradPfPKfS1_S_PKiS1_fS1_, @function
_Z16color_field_gradPfPKfS1_S_PKiS1_fS1_:
.LFB2020:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2020:
	.size	_Z16color_field_gradPfPKfS1_S_PKiS1_fS1_, .-_Z16color_field_gradPfPKfS1_S_PKiS1_fS1_
	.globl	_Z15color_field_lapPfPKfS1_S1_PKiS1_fS1_
	.type	_Z15color_field_lapPfPKfS1_S1_PKiS1_fS1_, @function
_Z15color_field_lapPfPKfS1_S1_PKiS1_fS1_:
.LFB2178:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2178:
	.size	_Z15color_field_lapPfPKfS1_S1_PKiS1_fS1_, .-_Z15color_field_lapPfPKfS1_S1_PKiS1_fS1_
	.globl	_Z47__device_stub__Z12calc_densityPfPKfPKiS1_S1_S1_PfPKfPKiS1_S1_S1_
	.type	_Z47__device_stub__Z12calc_densityPfPKfPKiS1_S1_S1_PfPKfPKiS1_S1_S1_, @function
_Z47__device_stub__Z12calc_densityPfPKfPKiS1_S1_S1_PfPKfPKiS1_S1_S1_:
.LFB2046:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z12calc_densityPfPKfPKiS1_S1_S1_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L30:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L32
	call	__stack_chk_fail@PLT
.L32:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2046:
	.size	_Z47__device_stub__Z12calc_densityPfPKfPKiS1_S1_S1_PfPKfPKiS1_S1_S1_, .-_Z47__device_stub__Z12calc_densityPfPKfPKiS1_S1_S1_PfPKfPKiS1_S1_S1_
	.globl	_Z12calc_densityPfPKfPKiS1_S1_S1_
	.type	_Z12calc_densityPfPKfPKiS1_S1_S1_, @function
_Z12calc_densityPfPKfPKiS1_S1_S1_:
.LFB2047:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z12calc_densityPfPKfPKiS1_S1_S1_PfPKfPKiS1_S1_S1_
	.cfi_endproc
.LFE2047:
	.size	_Z12calc_densityPfPKfPKiS1_S1_S1_, .-_Z12calc_densityPfPKfPKiS1_S1_S1_
	.globl	_Z78__device_stub__Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_
	.type	_Z78__device_stub__Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_, @function
_Z78__device_stub__Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_:
.LFB2048:
	.cfi_startproc
	endbr64
	subq	$376, %rsp
	.cfi_def_cfa_offset 384
	movq	384(%rsp), %rax
	movq	%rdi, 136(%rsp)
	leaq	168(%rsp), %rdi
	movq	%rsi, 128(%rsp)
	leaq	180(%rsp), %rsi
	movq	%rax, 88(%rsp)
	movq	392(%rsp), %rax
	movq	%rdx, 120(%rsp)
	leaq	152(%rsp), %rdx
	movq	%rax, 80(%rsp)
	movq	400(%rsp), %rax
	movq	%rcx, 112(%rsp)
	leaq	160(%rsp), %rcx
	movq	%rax, 72(%rsp)
	movq	408(%rsp), %rax
	movq	%r8, 104(%rsp)
	movq	%rax, 64(%rsp)
	movq	416(%rsp), %rax
	movq	%r9, 96(%rsp)
	movq	%rax, 56(%rsp)
	movq	424(%rsp), %rax
	movq	%rax, 48(%rsp)
	movq	432(%rsp), %rax
	movq	%rax, 40(%rsp)
	movq	440(%rsp), %rax
	movq	%rax, 32(%rsp)
	movq	448(%rsp), %rax
	movq	%rax, 24(%rsp)
	movq	456(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	464(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	472(%rsp), %rax
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 360(%rsp)
	xorl	%eax, %eax
	leaq	136(%rsp), %rax
	movl	$1, 176(%rsp)
	movq	%rax, 216(%rsp)
	leaq	128(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	120(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 320(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 328(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 336(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 344(%rsp)
	movq	%rsp, %rax
	movq	%rax, 352(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 168(%rsp)
	movq	%rax, 180(%rsp)
	movl	$1, 188(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	pushq	160(%rsp)
	.cfi_def_cfa_offset 392
	leaq	_Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_(%rip), %rdi
	pushq	160(%rsp)
	.cfi_def_cfa_offset 400
	movq	196(%rsp), %rcx
	movl	204(%rsp), %r8d
	movq	184(%rsp), %rsi
	movl	192(%rsp), %edx
	leaq	232(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 392
	popq	%rdx
	.cfi_def_cfa_offset 384
.L36:
	movq	360(%rsp), %rax
	subq	%fs:40, %rax
	je	.L38
	call	__stack_chk_fail@PLT
.L38:
	addq	$376, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2048:
	.size	_Z78__device_stub__Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_, .-_Z78__device_stub__Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_
	.globl	_Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_
	.type	_Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_, @function
_Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_:
.LFB2049:
	.cfi_startproc
	endbr64
	jmp	_Z78__device_stub__Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_
	.cfi_endproc
.LFE2049:
	.size	_Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_, .-_Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_
	.globl	_Z61__device_stub__Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_PfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_
	.type	_Z61__device_stub__Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_PfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_, @function
_Z61__device_stub__Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_PfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_:
.LFB2050:
	.cfi_startproc
	endbr64
	subq	$280, %rsp
	.cfi_def_cfa_offset 288
	movq	288(%rsp), %rax
	movq	%rdi, 88(%rsp)
	leaq	120(%rsp), %rdi
	movq	%rsi, 80(%rsp)
	leaq	132(%rsp), %rsi
	movq	%rax, 40(%rsp)
	movq	296(%rsp), %rax
	movq	%rdx, 72(%rsp)
	leaq	104(%rsp), %rdx
	movq	%rax, 32(%rsp)
	movq	304(%rsp), %rax
	movq	%rcx, 64(%rsp)
	leaq	112(%rsp), %rcx
	movq	%rax, 24(%rsp)
	movq	312(%rsp), %rax
	movq	%r8, 56(%rsp)
	movq	%rax, 16(%rsp)
	movq	320(%rsp), %rax
	movq	%r9, 48(%rsp)
	movq	%rax, 8(%rsp)
	movq	328(%rsp), %rax
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 264(%rsp)
	xorl	%eax, %eax
	leaq	88(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 248(%rsp)
	movq	%rsp, %rax
	movq	%rax, 256(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 120(%rsp)
	movl	$1, 128(%rsp)
	movq	%rax, 132(%rsp)
	movl	$1, 140(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L41
	pushq	112(%rsp)
	.cfi_def_cfa_offset 296
	leaq	_Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_(%rip), %rdi
	pushq	112(%rsp)
	.cfi_def_cfa_offset 304
	movq	148(%rsp), %rcx
	movl	156(%rsp), %r8d
	movq	136(%rsp), %rsi
	movl	144(%rsp), %edx
	leaq	184(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 296
	popq	%rdx
	.cfi_def_cfa_offset 288
.L41:
	movq	264(%rsp), %rax
	subq	%fs:40, %rax
	je	.L43
	call	__stack_chk_fail@PLT
.L43:
	addq	$280, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2050:
	.size	_Z61__device_stub__Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_PfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_, .-_Z61__device_stub__Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_PfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_
	.globl	_Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_
	.type	_Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_, @function
_Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_:
.LFB2051:
	.cfi_startproc
	endbr64
	jmp	_Z61__device_stub__Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_PfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_
	.cfi_endproc
.LFE2051:
	.size	_Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_, .-_Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_"
.LC1:
	.string	"_Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_"
.LC2:
	.string	"_Z12calc_densityPfPKfPKiS1_S1_S1_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z12calc_densityPfPKfPKiS1_S1_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2053:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
__device__ float magnitude(const float *r) {
  return pow((r[0] * r[0]) + (r[1] * r[1]) + (r[2] * r[2]), 0.5);
}

__device__ float magnitude_withId(const float *r) {
  const int i = blockIdx.x;
  return pow((r[3 * i] * r[3 * i]) + (r[3 * i + 1] * r[3 * i + 1]) +
                 (r[3 * i + 2] * r[3 * i + 2]),
             0.5);
}

__device__ float clamp(float x, float max_v, float min_v) {
  return max(min_v, min(max_v, x));
}

__device__ float WPoly6(const float mag, const float *h,
                        const float *WPoly6_const) {
  if (mag < *h && mag > 0) {
    float inner_val = ((*h * *h) - (mag * mag));
    return inner_val * inner_val * inner_val * *WPoly6_const;
  } else
    return 0;
}

__device__ void grad_WPoly6(float *grad, float *r, const float mag,
                            const float *h, const float *grad_WPoly6_const) {
  float inner_val = ((*h * *h) - (mag * mag));
  inner_val =
      inner_val * inner_val * *grad_WPoly6_const * (1 / (mag + 0.000001f));
  grad[0] = inner_val * r[0];
  grad[1] = inner_val * r[1];
  grad[2] = inner_val * r[2];
}

__device__ float lap_WPoly6(const float *h, const float mag,
                            const float *lap_WPoly6_const) {
  float inner_val = ((*h * *h) - (mag * mag));
  return *lap_WPoly6_const * inner_val * ((3 * *h * *h) - (7 * mag * mag));
}

__device__ float Wspiky(const float *h, const float mag,
                        const float *Wpiky_const) {
  if (mag < *h && mag > 0) {
    return *Wpiky_const * (*h - mag) * (*h - mag) * (*h - mag);
  } else {
    return 0;
  }
}

__device__ void grad_WSpiky(float *grad, const float mag, const float *r,
                            const float *h, const float *grad_Wspiky_const) {
  float inner_val =
      *grad_Wspiky_const * (*h - mag) * (*h - mag) * (1 / (mag + 0.0000001f));
  grad[0] = r[0] * inner_val;
  grad[1] = r[1] * inner_val;
  grad[2] = r[2] * inner_val;
}

__device__ float Wviscosity(const float *h, const float mag,
                            const float *Wviscosity_const) {
  float inner_val = ((-mag * mag * mag) / (2 * *h * *h * *h)) +
                    ((mag * mag) / (*h * *h)) + (*h / (2 * mag + 0.0000001f)) -
                    1;
  return inner_val * *Wviscosity_const;
}

__device__ float lap_Wviscosity(const float mag, const float *h,
                                const float *lap_Wviscosity_const) {
  return *lap_Wviscosity_const * (*h - mag);
}

__device__ void pressure_force(float *press_force, const float *mass,
                               const float mag, const float *r, const float *h,
                               const float *density_n, const int *neighbors,
                               const float *rest_density, const float *k,
                               const float *grad_Wspiky_const) {
  const int i = neighbors[blockIdx.x * blockDim.x + threadIdx.x];
  float grad[3];
  grad_WSpiky(grad, mag, r, h, grad_Wspiky_const);
  float const_val = *mass * *k *
                    (density_n[blockIdx.x] + density_n[i] - 2 * *rest_density) *
                    1 / (2 * density_n[i]);
  press_force[0] = const_val * grad[0];
  press_force[1] = const_val * grad[1];
  press_force[2] = const_val * grad[2];
}

__device__ void viscosity_force(float *visc_force, const float *eta,
                                const float *mass, const float mag,
                                const float *h, const float *density_n,
                                const float *vel_n, const int *neighbors,
                                const float *lap_Wviscosity_const) {

  const int i = neighbors[blockIdx.x * blockDim.x + threadIdx.x];
  float const_val = *eta * *mass * (1 / (density_n[i] + 0.0000001f)) *
                    lap_Wviscosity(mag, h, lap_Wviscosity_const);
  visc_force[0] = const_val * (vel_n[3 * i] - vel_n[3 * blockIdx.x]);
  visc_force[1] = const_val * (vel_n[3 * i + 1] - vel_n[3 * blockIdx.x + 1]);
  visc_force[2] = const_val * (vel_n[3 * i + 2] - vel_n[3 * blockIdx.x + 2]);
}

__device__ void color_field_grad(float *color_field_grad_val, const float *mass,
                                 const float *density_n, float *r_dash,
                                 const int *neighbors, const float *h,
                                 const float mag,
                                 const float *grad_WPoly6_const) {
  const int i = neighbors[blockIdx.x * blockDim.x + threadIdx.x];
  float inner_val = *mass * 1 / (density_n[i] + 0.0000001f);
  float grad_Wpoly[3];
  grad_WPoly6(grad_Wpoly, r_dash, mag, h, grad_WPoly6_const);
  color_field_grad_val[blockIdx.x * blockDim.x * 3 + 3 * threadIdx.x] =
      grad_Wpoly[0] * inner_val;
  color_field_grad_val[blockIdx.x * blockDim.x * 3 + 3 * threadIdx.x + 1] =
      grad_Wpoly[1] * inner_val;
  color_field_grad_val[blockIdx.x * blockDim.x * 3 + 3 * threadIdx.x + 2] =
      grad_Wpoly[2] * inner_val;
}

__device__ void color_field_lap(float *color_field_lap_val, const float *mass,
                                const float *density_n, const float *r,
                                const int *neighbors, const float *h,
                                const float mag,
                                const float *lap_WPoly6_const) {
  const int i = blockIdx.x * blockDim.x + threadIdx.x;
  color_field_lap_val[i] = *mass * 1 / (density_n[neighbors[i]] + 0.0000001f) *
                           lap_WPoly6(h, mag, lap_WPoly6_const);
}

__global__ void calc_density(float *density, const float *r1,
                             const int *neighbors, const float *mass,
                             const float *h, const float *WPoly6_const) {
  float r_dash[3];
  const int i = threadIdx.x;
  const int j = blockIdx.x;
  const int n = j * blockDim.x + i;
  r_dash[0] = r1[3 * j] - r1[3 * neighbors[n]];
  r_dash[1] = r1[3 * j + 1] - r1[3 * neighbors[n] + 1];
  r_dash[2] = r1[3 * j + 2] - r1[3 * neighbors[n] + 2];
  const float mag = magnitude(r_dash);
  density[n] = WPoly6(mag, h, WPoly6_const) * *mass;
}

__global__ void
calc_forces(float *force, float *color_field_lap_val,
            float *color_field_grad_val, const float *r1,
            const float *density_n, float *vel_n, int *neighbors,
            const float *h, const float *eta, const float *mass,
            const float *rest_density, const float *k,
            const float *grad_WPoly6_const, const float *lap_WPoly6_const,
            const float *Wspiky_const, const float *grad_Wspiky_const,
            const float *Wviscosity_const, const float *lap_Wviscosity_const) {

  const int i = threadIdx.x;
  const int j = blockIdx.x;
  const int n = j * blockDim.x + i;

  float r_dash[3], press_force[3], visc_force[3];
  r_dash[0] = r1[3 * j] - r1[3 * neighbors[n]];
  r_dash[1] = r1[3 * j + 1] - r1[3 * neighbors[n] + 1];
  r_dash[2] = r1[3 * j + 1] - r1[3 * neighbors[n] + 2];
  float mag = magnitude(r_dash);
  if (mag > 0.000001f && mag < *h) {
    pressure_force(press_force, mass, mag, r_dash, h, density_n, neighbors,
                   rest_density, k, grad_Wspiky_const);
    viscosity_force(visc_force, eta, mass, mag, h, density_n, vel_n, neighbors,
                    lap_Wviscosity_const);
    color_field_grad(color_field_grad_val, mass, density_n, r_dash, neighbors,
                     h, mag, grad_WPoly6_const);
    color_field_lap(color_field_lap_val, mass, density_n, r_dash, neighbors, h,
                    mag, lap_WPoly6_const);
    force[blockIdx.x * blockDim.x * 3 + 3 * i] =
        clamp(press_force[0] + visc_force[0], 200, -200);
    force[blockIdx.x * blockDim.x * 3 + 3 * i + 1] =
        clamp(press_force[1] + visc_force[1], 200, -200);
    force[blockIdx.x * blockDim.x * 3 + 3 * i + 2] =
        clamp(press_force[2] + visc_force[2], 200, -200);
  } else {
    force[blockIdx.x * blockDim.x * 3 + 3 * i] = 0;
    force[blockIdx.x * blockDim.x * 3 + 3 * i + 1] = 0;
    force[blockIdx.x * blockDim.x * 3 + 3 * i + 2] = 0;
    color_field_grad_val[blockIdx.x * blockDim.x * 3 + 3 * i] = 0;
    color_field_grad_val[blockIdx.x * blockDim.x * 3 + 3 * i + 1] = 0;
    color_field_grad_val[blockIdx.x * blockDim.x * 3 + 3 * i + 2] = 0;
    color_field_lap_val[blockIdx.x * blockDim.x + threadIdx.x] = 0;
  }
}

__global__ void update_pos(float *r, float *vel_p, float *force,
                           const float *threshold, const float *mass,
                           const float *time, const float *sigma,
                           const float *Width, const float *damping,
                           const float *eps, const float *color_field_lap_val,
                           const float *color_field_grad_val) {
  const int i = blockIdx.x;
  float gradient_length = magnitude_withId(color_field_grad_val);
  float force_surface[3] = {0, 0, 0};

  if (gradient_length >= *threshold) {
    float const_val = -1 * *sigma * color_field_lap_val[i] *
                      (1 / (gradient_length + 0.0000001f));
    force_surface[0] = const_val * color_field_grad_val[3 * i];
    force_surface[1] = const_val * color_field_grad_val[3 * i + 1];
    force_surface[2] = const_val * color_field_grad_val[3 * i + 2];
  }

  vel_p[3 * i] += clamp(
      (force[3 * i] + force_surface[0]) * (1 / (*mass)) * *time, 200, -200);
  vel_p[3 * i + 1] += clamp(
      (force[3 * i + 1] + force_surface[1]) * (1 / (*mass)) * *time, 200, -200);
  vel_p[3 * i + 2] += clamp(
      (((force[3 * i + 2] + force_surface[2]) * 1 / (*mass)) - 10 * 12000) *
          *time,
      200, -200);

  r[3 * i] += vel_p[3 * i] * *time;
  r[3 * i + 1] += vel_p[3 * i + 1] * *time;
  r[3 * i + 2] += vel_p[3 * i + 2] * *time;

  if (r[3 * i] < -*Width) {
    r[3 * i] = -*Width + *eps;
    vel_p[3 * i] = *damping * vel_p[3 * i];
  }
  if (r[3 * i + 1] < -*Width) {
    r[3 * i + 1] = -*Width + *eps;
    vel_p[3 * i + 1] = *damping * vel_p[3 * i + 1];
  }
  if (r[3 * i + 2] < -*Width) {
    r[3 * i + 2] = -*Width + *eps;
    vel_p[3 * i + 2] = *damping * vel_p[3 * i + 2];
  }
  if (r[3 * i] > *Width) {
    r[3 * i] = *Width - *eps;
    vel_p[3 * i] = *damping * vel_p[3 * i];
  }
  if (r[3 * i + 1] > *Width) {
    r[3 * i + 1] = *Width - *eps;
    vel_p[3 * i + 1] = *damping * vel_p[3 * i + 1];
  }
  if (r[3 * i + 2] > *Width) {
    r[3 * i + 2] = *Width * 10 - *eps;
    vel_p[3 * i + 2] = *damping * vel_p[3 * i + 2];
  }
}

	.text
	.file	"source.hip"
	.globl	_Z27__device_stub__calc_densityPfPKfPKiS1_S1_S1_ # -- Begin function _Z27__device_stub__calc_densityPfPKfPKiS1_S1_S1_
	.type	_Z27__device_stub__calc_densityPfPKfPKiS1_S1_S1_,@function
_Z27__device_stub__calc_densityPfPKfPKiS1_S1_S1_: # @_Z27__device_stub__calc_densityPfPKfPKiS1_S1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12calc_densityPfPKfPKiS1_S1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__calc_densityPfPKfPKiS1_S1_S1_, .Lfunc_end0-_Z27__device_stub__calc_densityPfPKfPKiS1_S1_S1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_ # -- Begin function _Z26__device_stub__calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_
	.type	_Z26__device_stub__calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_,@function
_Z26__device_stub__calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_: # @_Z26__device_stub__calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$240, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	368(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	376(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$256, %rsp                      # imm = 0x100
	.cfi_adjust_cfa_offset -256
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z26__device_stub__calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_, .Lfunc_end1-_Z26__device_stub__calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_ # -- Begin function _Z25__device_stub__update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_
	.type	_Z25__device_stub__update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_,@function
_Z25__device_stub__update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_: # @_Z25__device_stub__update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z25__device_stub__update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_, .Lfunc_end2-_Z25__device_stub__update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12calc_densityPfPKfPKiS1_S1_S1_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12calc_densityPfPKfPKiS1_S1_S1_,@object # @_Z12calc_densityPfPKfPKiS1_S1_S1_
	.section	.rodata,"a",@progbits
	.globl	_Z12calc_densityPfPKfPKiS1_S1_S1_
	.p2align	3, 0x0
_Z12calc_densityPfPKfPKiS1_S1_S1_:
	.quad	_Z27__device_stub__calc_densityPfPKfPKiS1_S1_S1_
	.size	_Z12calc_densityPfPKfPKiS1_S1_S1_, 8

	.type	_Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_,@object # @_Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_
	.globl	_Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_
	.p2align	3, 0x0
_Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_:
	.quad	_Z26__device_stub__calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_
	.size	_Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_, 8

	.type	_Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_,@object # @_Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_
	.globl	_Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_
	.p2align	3, 0x0
_Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_:
	.quad	_Z25__device_stub__update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_
	.size	_Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z12calc_densityPfPKfPKiS1_S1_S1_"
	.size	.L__unnamed_1, 34

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_"
	.size	.L__unnamed_2, 65

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_"
	.size	.L__unnamed_3, 48

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__calc_densityPfPKfPKiS1_S1_S1_
	.addrsig_sym _Z26__device_stub__calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_
	.addrsig_sym _Z25__device_stub__update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12calc_densityPfPKfPKiS1_S1_S1_
	.addrsig_sym _Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_
	.addrsig_sym _Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12calc_densityPfPKfPKiS1_S1_S1_ ; -- Begin function _Z12calc_densityPfPKfPKiS1_S1_S1_
	.globl	_Z12calc_densityPfPKfPKiS1_S1_S1_
	.p2align	8
	.type	_Z12calc_densityPfPKfPKiS1_S1_S1_,@function
_Z12calc_densityPfPKfPKiS1_S1_S1_:      ; @_Z12calc_densityPfPKfPKiS1_S1_S1_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b256 s[16:23], s[0:1], 0x0
	s_mov_b32 s6, 0x4222de17
	s_mov_b32 s7, 0x3fbdee67
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mul_i32 s2, s15, 3
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[2:3], s[2:3], 2
	s_add_u32 s2, s18, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	s_addc_u32 s3, s19, s3
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s20, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s21, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_lshl_add_u32 v2, v2, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s18, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s19, v3, vcc_lo
	global_load_b96 v[3:5], v[2:3], off
	s_clause 0x1
	s_load_b64 s[4:5], s[2:3], 0x0
	s_load_b32 s2, s[2:3], 0x8
	s_mov_b32 s3, 0x3fe55555
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_sub_f32 v2, s5, v4 :: v_dual_sub_f32 v3, s4, v3
	s_mov_b32 s4, 0x968915a9
	s_mov_b32 s5, 0x3fba6564
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v4, v2, v2
	v_sub_f32_e32 v2, s2, v5
	s_mov_b32 s2, 0x55555555
	v_fmac_f32_e32 v4, v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v2, v2
	v_cvt_f64_f32_e32 v[5:6], v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_frexp_mant_f64_e64 v[2:3], |v[5:6]|
	v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[2:3]
	v_cndmask_b32_e64 v7, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[2:3], v[2:3], v7
	v_add_f64 v[7:8], v[2:3], 1.0
	v_add_f64 v[13:14], v[2:3], -1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[9:10], v[7:8]
	v_add_f64 v[15:16], v[7:8], -1.0
	v_add_f64 v[2:3], v[2:3], -v[15:16]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], v[11:12], v[9:10], v[9:10]
	v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], v[11:12], v[9:10], v[9:10]
	v_mul_f64 v[11:12], v[13:14], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[17:18], v[7:8], v[11:12]
	v_fma_f64 v[7:8], v[11:12], v[7:8], -v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], v[11:12], v[2:3], v[7:8]
	v_add_f64 v[7:8], v[17:18], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[13:14], -v[7:8]
	v_add_f64 v[17:18], v[7:8], -v[17:18]
	v_add_f64 v[13:14], v[13:14], -v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[2:3], v[17:18], -v[2:3]
	v_add_f64 v[7:8], v[13:14], -v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[7:8]
	v_add_f64 v[2:3], v[15:16], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[2:3], v[9:10], v[2:3]
	v_add_f64 v[7:8], v[11:12], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[7:8], -v[11:12]
	v_mul_f64 v[11:12], v[7:8], v[7:8]
	v_add_f64 v[2:3], v[2:3], -v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[9:10], v[7:8], v[7:8], -v[11:12]
	v_add_f64 v[13:14], v[2:3], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], v[7:8], v[13:14], v[9:10]
	v_add_f64 v[13:14], v[11:12], v[9:10]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[15:16], v[13:14], s[6:7], s[4:5]
	s_mov_b32 s4, 0x3abe935a
	s_mov_b32 s5, 0x3fbe25e4
	v_add_f64 v[11:12], v[13:14], -v[11:12]
	v_mul_f64 v[21:22], v[7:8], v[13:14]
	s_mov_b32 s6, 0x652b82fe
	s_mov_b32 s7, 0x3ff71547
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[4:5]
	s_mov_b32 s4, 0x47e6c9c2
	s_mov_b32 s5, 0x3fc110ef
	v_add_f64 v[9:10], v[9:10], -v[11:12]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[4:5]
	s_mov_b32 s4, 0xcfa74449
	s_mov_b32 s5, 0x3fc3b13b
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[4:5]
	s_mov_b32 s4, 0x71bf3c30
	s_mov_b32 s5, 0x3fc745d1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[4:5]
	s_mov_b32 s4, 0x1c7792ce
	s_mov_b32 s5, 0x3fcc71c7
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[4:5]
	s_mov_b32 s4, 0x924920da
	s_mov_b32 s5, 0x3fd24924
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[4:5]
	s_mov_b32 s4, 0x9999999c
	s_mov_b32 s5, 0x3fd99999
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[4:5]
	s_mov_b32 s5, 0x3c7abc9e
	s_mov_b32 s4, 0x3b39803f
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[17:18], v[13:14], v[15:16]
	v_fma_f64 v[11:12], v[13:14], v[15:16], -v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[9:10], v[15:16], v[11:12]
	v_add_f64 v[15:16], v[17:18], v[11:12]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[19:20], v[15:16], s[2:3]
	v_add_f64 v[17:18], v[15:16], -v[17:18]
	s_mov_b32 s3, 0xbfe55555
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add_f64 v[23:24], v[19:20], s[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[11:12], -v[17:18]
	v_fma_f64 v[17:18], v[13:14], v[7:8], -v[21:22]
	s_mov_b32 s2, 0xd5df274d
	s_mov_b32 s3, 0x3c8543b0
	v_add_f64 v[15:16], v[15:16], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[11:12], s[2:3]
	v_fma_f64 v[13:14], v[13:14], v[2:3], v[17:18]
	s_mov_b32 s3, 0x3fe62e42
	s_mov_b32 s2, 0xfefa39ef
	v_ldexp_f64 v[2:3], v[2:3], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[11:12], v[15:16]
	v_fma_f64 v[9:10], v[9:10], v[7:8], v[13:14]
	v_ldexp_f64 v[7:8], v[7:8], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[19:20], v[11:12]
	v_add_f64 v[15:16], v[21:22], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[19:20], -v[13:14]
	v_mul_f64 v[19:20], v[15:16], v[13:14]
	v_add_f64 v[21:22], v[15:16], -v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[11:12], v[17:18]
	v_fma_f64 v[17:18], v[15:16], v[13:14], -v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[9:10], -v[21:22]
	v_fma_f64 v[11:12], v[15:16], v[11:12], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[9:10], v[9:10], v[13:14], v[11:12]
	v_frexp_exp_i32_f64_e32 v13, v[5:6]
	v_add_f64 v[11:12], v[19:20], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v4
	v_cvt_f64_i32_e32 v[13:14], v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[7:8], v[11:12]
	v_add_f64 v[17:18], v[11:12], -v[19:20]
	v_mul_f64 v[19:20], v[13:14], s[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[15:16], -v[7:8]
	v_add_f64 v[9:10], v[9:10], -v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[17:18], v[13:14], s[2:3], -v[19:20]
	s_mov_b32 s3, 0xbfe62e42
	v_add_f64 v[7:8], v[11:12], -v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[2:3], v[2:3], v[9:10]
	v_fma_f64 v[9:10], v[13:14], s[4:5], v[17:18]
	s_mov_b32 s5, 0xbc7abc9e
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[2:3], v[2:3], v[7:8]
	v_add_f64 v[7:8], v[19:20], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[15:16], v[2:3]
	v_add_f64 v[19:20], v[7:8], -v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[7:8], v[11:12]
	v_add_f64 v[15:16], v[11:12], -v[15:16]
	v_add_f64 v[9:10], v[9:10], -v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[17:18], v[13:14], -v[7:8]
	v_add_f64 v[2:3], v[2:3], -v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[13:14], -v[17:18]
	v_add_f64 v[11:12], v[11:12], -v[17:18]
	v_add_f64 v[15:16], v[9:10], v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], -v[21:22]
	v_add_f64 v[7:8], v[11:12], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[15:16], -v[9:10]
	v_add_f64 v[7:8], v[15:16], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[15:16], -v[11:12]
	v_add_f64 v[2:3], v[2:3], -v[11:12]
	v_add_f64 v[17:18], v[13:14], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[9:10], -v[15:16]
	v_add_f64 v[11:12], v[17:18], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[2:3], v[2:3], v[9:10]
	v_add_f64 v[7:8], v[7:8], -v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[2:3], v[7:8]
	v_dual_mov_b32 v3, 0x3ff00000 :: v_dual_mov_b32 v2, 0
	v_cndmask_b32_e32 v3, 0x3fe00000, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[17:18], v[7:8]
	v_add_f64 v[11:12], v[9:10], -v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[13:14], v[2:3], v[9:10]
	v_add_f64 v[7:8], v[7:8], -v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[9:10], v[2:3], v[9:10], -v[13:14]
	v_cmp_class_f64_e64 vcc_lo, v[13:14], 0x204
	v_fma_f64 v[7:8], v[2:3], v[7:8], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[13:14], v[7:8]
	v_dual_cndmask_b32 v12, v10, v14 :: v_dual_cndmask_b32 v11, v9, v13
	v_add_f64 v[9:10], v[9:10], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[15:16], v[11:12], s[6:7]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[11:12]|
	v_add_f64 v[7:8], v[7:8], -v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rndne_f64_e32 v[15:16], v[15:16]
	v_dual_cndmask_b32 v8, 0, v8 :: v_dual_cndmask_b32 v7, 0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fma_f64 v[17:18], v[15:16], s[2:3], v[11:12]
	s_mov_b32 s2, 0xfca7ab0c
	s_mov_b32 s3, 0x3e928af3
	v_cvt_i32_f64_e32 v21, v[15:16]
	v_fma_f64 v[17:18], v[15:16], s[4:5], v[17:18]
	s_mov_b32 s4, 0x6a5dcb37
	s_mov_b32 s5, 0x3e5ade15
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[19:20], v[17:18], s[4:5], s[2:3]
	s_mov_b32 s2, 0x623fde64
	s_mov_b32 s3, 0x3ec71dee
	v_cmp_class_f64_e64 s5, v[5:6], 0x204
	v_cmp_eq_f32_e64 s4, 0, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[19:20], v[17:18], v[19:20], s[2:3]
	s_mov_b32 s2, 0x7c89e6b0
	s_mov_b32 s3, 0x3efa0199
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[19:20], v[17:18], v[19:20], s[2:3]
	s_mov_b32 s2, 0x14761f6e
	s_mov_b32 s3, 0x3f2a01a0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[19:20], v[17:18], v[19:20], s[2:3]
	s_mov_b32 s2, 0x1852b7b0
	s_mov_b32 s3, 0x3f56c16c
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[19:20], v[17:18], v[19:20], s[2:3]
	s_mov_b32 s2, 0x11122322
	s_mov_b32 s3, 0x3f811111
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[19:20], v[17:18], v[19:20], s[2:3]
	s_mov_b32 s2, 0x555502a1
	s_mov_b32 s3, 0x3fa55555
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[19:20], v[17:18], v[19:20], s[2:3]
	s_mov_b32 s2, 0x55555511
	s_mov_b32 s3, 0x3fc55555
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[19:20], v[17:18], v[19:20], s[2:3]
	s_mov_b32 s2, 11
	s_mov_b32 s3, 0x3fe00000
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[19:20], v[17:18], v[19:20], s[2:3]
	v_cmp_nlt_f64_e64 s2, 0x40900000, v[11:12]
	v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], v[17:18], v[19:20], 1.0
	s_and_b32 vcc_lo, s3, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[17:18], v[19:20], 1.0
	v_ldexp_f64 v[13:14], v[15:16], v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v13, 0, v13, vcc_lo
	v_mul_f64 v[15:16], v[2:3], 0.5
	v_trunc_f64_e32 v[9:10], v[2:3]
	v_cndmask_b32_e64 v14, 0x7ff00000, v14, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v14, 0, v14, s3
	v_fma_f64 v[7:8], v[13:14], v[7:8], v[13:14]
	v_cmp_class_f64_e64 s3, v[13:14], 0x204
	v_trunc_f64_e32 v[11:12], v[15:16]
	v_cmp_eq_f64_e32 vcc_lo, v[9:10], v[2:3]
	v_cndmask_b32_e64 v3, 0x7ff00000, 0, s4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v8, v8, v14, s3
	v_cndmask_b32_e64 v7, v7, v13, s3
	v_cmp_neq_f64_e64 s2, v[11:12], v[15:16]
	s_and_b32 vcc_lo, vcc_lo, s2
	s_load_b128 s[0:3], s[0:1], 0x20
	v_cndmask_b32_e32 v5, 0x3ff00000, v6, vcc_lo
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	s_or_b32 vcc_lo, s4, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v3, 0x7fffffff, v3, v6
	v_bfi_b32 v6, 0x7fffffff, v8, v5
	v_cndmask_b32_e64 v5, v7, 0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v6, v3, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v4, v4
	v_cvt_f32_f64_e32 v3, v[5:6]
	s_waitcnt lgkmcnt(0)
	s_load_b32 s1, s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, 0x7fc00000, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, s1, v3
	v_cmp_lt_f32_e64 s0, 0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s4, s0, vcc_lo
	s_and_saveexec_b32 s0, s4
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_mul_f32_e32 v2, v3, v3
	s_load_b32 s2, s[2:3], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, s1, s1, -v2
	v_mul_f32_e32 v3, v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v2, v3
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v2, s2, v2
.LBB0_2:                                ; %_Z6WPoly6fPKfS0_.exit
	s_or_b32 exec_lo, exec_lo, s0
	s_load_b32 s0, s[22:23], 0x0
	v_add_co_u32 v0, vcc_lo, s16, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v2, s0, v2
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12calc_densityPfPKfPKiS1_S1_S1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 25
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12calc_densityPfPKfPKiS1_S1_S1_, .Lfunc_end0-_Z12calc_densityPfPKfPKiS1_S1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2400
; NumSgprs: 26
; NumVgprs: 25
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 25
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_ ; -- Begin function _Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_
	.globl	_Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_
	.p2align	8
	.type	_Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_,@function
_Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_: ; @_Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_
; %bb.0:
	s_mov_b32 s34, s15
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x9c
	s_load_b512 s[8:23], s[0:1], 0x0
	s_mul_i32 s36, s34, 3
	s_mov_b32 s4, 0x968915a9
	s_ashr_i32 s37, s36, 31
	s_mov_b32 s6, 0x4222de17
	s_mov_b32 s5, 0x3fba6564
	s_mov_b32 s7, 0x3fbdee67
                                        ; implicit-def: $sgpr33
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s34, s2, v[0:1]
	s_lshl_b64 s[2:3], s[36:37], 2
	s_add_u32 s2, s14, s2
	s_addc_u32 s3, s15, s3
	s_load_b64 s[2:3], s[2:3], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s20, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, s21, v4, vcc_lo
	global_load_b32 v5, v[5:6], off
	s_waitcnt vmcnt(0)
	v_lshl_add_u32 v6, v5, 1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s14, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s15, v7, vcc_lo
	global_load_b96 v[6:8], v[6:7], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_sub_f32 v0, s3, v7 :: v_dual_sub_f32 v9, s3, v8
	v_sub_f32_e32 v10, s2, v6
	s_mov_b32 s3, 0x3fe55555
	s_mov_b32 s2, 0x55555555
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v0, v0
	v_fmac_f32_e32 v2, v10, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, v9, v9
	v_cvt_f64_f32_e32 v[6:7], v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_frexp_mant_f64_e64 v[11:12], |v[6:7]|
	v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[11:12]
	v_cndmask_b32_e64 v8, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[11:12], v[11:12], v8
	v_frexp_exp_i32_f64_e32 v8, v[6:7]
	v_add_f64 v[13:14], v[11:12], 1.0
	v_add_f64 v[19:20], v[11:12], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_subrev_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v2
	v_rcp_f64_e32 v[15:16], v[13:14]
	v_add_f64 v[21:22], v[13:14], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[11:12], -v[21:22]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
	v_fma_f64 v[15:16], v[17:18], v[15:16], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
	v_fma_f64 v[15:16], v[17:18], v[15:16], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[17:18], v[19:20], v[15:16]
	v_mul_f64 v[23:24], v[13:14], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[17:18], v[13:14], -v[23:24]
	v_fma_f64 v[11:12], v[17:18], v[11:12], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[23:24], v[11:12]
	v_add_f64 v[21:22], v[19:20], -v[13:14]
	v_add_f64 v[23:24], v[13:14], -v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[19:20], v[19:20], -v[21:22]
	v_add_f64 v[11:12], v[23:24], -v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[19:20], -v[13:14]
	v_add_f64 v[11:12], v[11:12], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[21:22], v[11:12]
	v_mul_f64 v[11:12], v[15:16], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[17:18], v[11:12]
	v_add_f64 v[15:16], v[13:14], -v[17:18]
	v_mul_f64 v[17:18], v[13:14], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[11:12], -v[15:16]
	v_fma_f64 v[15:16], v[13:14], v[13:14], -v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[19:20], v[11:12], v[11:12]
	v_fma_f64 v[15:16], v[13:14], v[19:20], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[19:20], v[17:18], v[15:16]
	v_fma_f64 v[21:22], v[19:20], s[6:7], s[4:5]
	s_mov_b32 s4, 0x3abe935a
	s_mov_b32 s5, 0x3fbe25e4
	v_add_f64 v[17:18], v[19:20], -v[17:18]
	v_mul_f64 v[27:28], v[13:14], v[19:20]
	s_mov_b32 s6, 0x652b82fe
	s_mov_b32 s7, 0x3ff71547
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[4:5]
	s_mov_b32 s4, 0x47e6c9c2
	s_mov_b32 s5, 0x3fc110ef
	v_add_f64 v[15:16], v[15:16], -v[17:18]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[4:5]
	s_mov_b32 s4, 0xcfa74449
	s_mov_b32 s5, 0x3fc3b13b
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[4:5]
	s_mov_b32 s4, 0x71bf3c30
	s_mov_b32 s5, 0x3fc745d1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[4:5]
	s_mov_b32 s4, 0x1c7792ce
	s_mov_b32 s5, 0x3fcc71c7
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[4:5]
	s_mov_b32 s4, 0x924920da
	s_mov_b32 s5, 0x3fd24924
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[4:5]
	s_mov_b32 s4, 0x9999999c
	s_mov_b32 s5, 0x3fd99999
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[4:5]
	s_mov_b32 s5, 0x3c7abc9e
	s_mov_b32 s4, 0x3b39803f
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[23:24], v[19:20], v[21:22]
	v_fma_f64 v[17:18], v[19:20], v[21:22], -v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[21:22], v[17:18]
	v_add_f64 v[21:22], v[23:24], v[17:18]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[25:26], v[21:22], s[2:3]
	v_add_f64 v[23:24], v[21:22], -v[23:24]
	s_mov_b32 s3, 0xbfe55555
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add_f64 v[29:30], v[25:26], s[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_f64 v[17:18], v[17:18], -v[23:24]
	v_fma_f64 v[23:24], v[19:20], v[13:14], -v[27:28]
	s_mov_b32 s2, 0xd5df274d
	s_mov_b32 s3, 0x3c8543b0
	v_add_f64 v[21:22], v[21:22], -v[29:30]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[17:18], v[17:18], s[2:3]
	v_fma_f64 v[19:20], v[19:20], v[11:12], v[23:24]
	s_mov_b32 s3, 0x3fe62e42
	s_mov_b32 s2, 0xfefa39ef
	v_ldexp_f64 v[11:12], v[11:12], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[17:18], v[17:18], v[21:22]
	v_fma_f64 v[15:16], v[15:16], v[13:14], v[19:20]
	v_ldexp_f64 v[13:14], v[13:14], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[19:20], v[25:26], v[17:18]
	v_add_f64 v[21:22], v[27:28], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[23:24], v[25:26], -v[19:20]
	v_mul_f64 v[25:26], v[21:22], v[19:20]
	v_add_f64 v[27:28], v[21:22], -v[27:28]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[17:18], v[17:18], v[23:24]
	v_fma_f64 v[23:24], v[21:22], v[19:20], -v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[15:16], -v[27:28]
	v_fma_f64 v[17:18], v[21:22], v[17:18], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[15:16], v[15:16], v[19:20], v[17:18]
	v_cvt_f64_i32_e32 v[19:20], v8
	v_mov_b32_e32 v8, 0x3ff00000
	v_add_f64 v[17:18], v[25:26], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[13:14], v[17:18]
	v_add_f64 v[23:24], v[17:18], -v[25:26]
	v_mul_f64 v[25:26], v[19:20], s[2:3]
	v_add_f64 v[13:14], v[21:22], -v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[15:16], -v[23:24]
	v_fma_f64 v[23:24], v[19:20], s[2:3], -v[25:26]
	s_mov_b32 s3, 0xbfe62e42
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[17:18], -v[13:14]
	v_add_f64 v[11:12], v[11:12], v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], v[19:20], s[4:5], v[23:24]
	s_mov_b32 s5, 0xbc7abc9e
	v_add_f64 v[11:12], v[11:12], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[25:26], v[15:16]
	v_add_f64 v[17:18], v[21:22], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[25:26], v[13:14], -v[25:26]
	v_add_f64 v[19:20], v[13:14], v[17:18]
	v_add_f64 v[21:22], v[17:18], -v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[15:16], -v[25:26]
	v_add_f64 v[23:24], v[19:20], -v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[11:12], -v[21:22]
	v_add_f64 v[27:28], v[19:20], -v[23:24]
	v_add_f64 v[17:18], v[17:18], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[15:16], v[11:12]
	v_add_f64 v[13:14], v[13:14], -v[27:28]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[17:18], v[13:14]
	v_add_f64 v[17:18], v[21:22], -v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[21:22], v[13:14]
	v_add_f64 v[21:22], v[21:22], -v[17:18]
	v_add_f64 v[11:12], v[11:12], -v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[23:24], v[19:20], v[13:14]
	v_add_f64 v[15:16], v[15:16], -v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[23:24], -v[19:20]
	v_add_f64 v[11:12], v[11:12], v[15:16]
	v_dual_mov_b32 v15, 0 :: v_dual_cndmask_b32 v16, 0x3fe00000, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[13:14], -v[17:18]
	v_add_f64 v[11:12], v[11:12], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[23:24], v[11:12]
	v_add_f64 v[17:18], v[13:14], -v[23:24]
	v_mul_f64 v[19:20], v[15:16], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[11:12], -v[17:18]
	v_fma_f64 v[13:14], v[15:16], v[13:14], -v[19:20]
	v_cmp_class_f64_e64 vcc_lo, v[19:20], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[15:16], v[11:12], v[13:14]
	v_add_f64 v[13:14], v[19:20], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v18, v14, v20 :: v_dual_cndmask_b32 v17, v13, v19
	v_add_f64 v[13:14], v[13:14], -v[19:20]
	v_mul_f64 v[21:22], v[17:18], s[6:7]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[17:18]|
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[11:12], v[11:12], -v[13:14]
	v_trunc_f64_e32 v[13:14], v[15:16]
	v_rndne_f64_e32 v[21:22], v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v12, 0, v12 :: v_dual_cndmask_b32 v11, 0, v11
	v_fma_f64 v[23:24], v[21:22], s[2:3], v[17:18]
	s_mov_b32 s2, 0xfca7ab0c
	s_mov_b32 s3, 0x3e928af3
	v_cvt_i32_f64_e32 v8, v[21:22]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[23:24], v[21:22], s[4:5], v[23:24]
	s_mov_b32 s4, 0x6a5dcb37
	s_mov_b32 s5, 0x3e5ade15
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[25:26], v[23:24], s[4:5], s[2:3]
	s_mov_b32 s2, 0x623fde64
	s_mov_b32 s3, 0x3ec71dee
	v_cmp_class_f64_e64 s5, v[6:7], 0x204
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[25:26], v[23:24], v[25:26], s[2:3]
	s_mov_b32 s2, 0x7c89e6b0
	s_mov_b32 s3, 0x3efa0199
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[25:26], v[23:24], v[25:26], s[2:3]
	s_mov_b32 s2, 0x14761f6e
	s_mov_b32 s3, 0x3f2a01a0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[25:26], v[23:24], v[25:26], s[2:3]
	s_mov_b32 s2, 0x1852b7b0
	s_mov_b32 s3, 0x3f56c16c
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[25:26], v[23:24], v[25:26], s[2:3]
	s_mov_b32 s2, 0x11122322
	s_mov_b32 s3, 0x3f811111
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[25:26], v[23:24], v[25:26], s[2:3]
	s_mov_b32 s2, 0x555502a1
	s_mov_b32 s3, 0x3fa55555
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[25:26], v[23:24], v[25:26], s[2:3]
	s_mov_b32 s2, 0x55555511
	s_mov_b32 s3, 0x3fc55555
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[25:26], v[23:24], v[25:26], s[2:3]
	s_mov_b32 s2, 11
	s_mov_b32 s3, 0x3fe00000
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[25:26], v[23:24], v[25:26], s[2:3]
	v_cmp_nlt_f64_e64 s2, 0x40900000, v[17:18]
	v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[25:26], v[23:24], v[25:26], 1.0
	s_and_b32 vcc_lo, s3, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], v[23:24], v[25:26], 1.0
	v_ldexp_f64 v[19:20], v[21:22], v8
	v_mul_f64 v[21:22], v[15:16], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v8, 0x7ff00000, v20, s2
	v_trunc_f64_e32 v[17:18], v[21:22]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v19, 0, v19, vcc_lo
	v_cmp_eq_f64_e32 vcc_lo, v[13:14], v[15:16]
	v_cmp_eq_f32_e64 s4, 0, v2
	v_cndmask_b32_e64 v20, 0, v8, s3
	v_cndmask_b32_e64 v6, 0x7ff00000, 0, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[11:12], v[19:20], v[11:12], v[19:20]
	v_cmp_class_f64_e64 s3, v[19:20], 0x204
	v_cmp_neq_f64_e64 s2, v[17:18], v[21:22]
	v_cndmask_b32_e64 v12, v12, v20, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v11, v11, v19, s3
	s_and_b32 vcc_lo, vcc_lo, s2
	s_mov_b32 s2, 0
	v_cndmask_b32_e32 v8, 0x3ff00000, v7, vcc_lo
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	s_or_b32 vcc_lo, s4, s5
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_bfi_b32 v8, 0x7fffffff, v12, v8
	v_bfi_b32 v7, 0x7fffffff, v6, v7
	v_cndmask_b32_e64 v6, v11, 0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v7, v8, v7, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v2, v2
	v_cvt_f32_f64_e32 v6, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v11, 0x7fc00000, v6, vcc_lo
	v_cmp_nlt_f32_e64 s3, 0x358637bd, v11
	v_cmpx_lt_f32_e32 0x358637bd, v11
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_load_b32 s33, s[22:23], 0x0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s3, exec_lo
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f32_e32 vcc_lo, s33, v11
	s_and_b32 s5, vcc_lo, exec_lo
	s_or_b32 s3, s3, s5
.LBB1_2:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s4
	v_lshl_add_u32 v7, v1, 1, v1
	s_and_saveexec_b32 s4, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s4
	s_cbranch_execz .LBB1_4
; %bb.3:
	v_mov_b32_e32 v8, 0
	v_add_nc_u32_e32 v12, 1, v7
	v_add_nc_u32_e32 v14, 2, v7
	s_and_not1_b32 s2, s2, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v15, v8
	v_mov_b32_e32 v13, v8
	v_lshlrev_b64 v[16:17], 2, v[7:8]
	v_mov_b32_e32 v2, v8
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_add_co_u32 v18, vcc_lo, s8, v16
	v_add_co_ci_u32_e32 v19, vcc_lo, s9, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v20, vcc_lo, s8, v12
	v_add_co_ci_u32_e32 v21, vcc_lo, s9, v13, vcc_lo
	v_add_co_u32 v22, vcc_lo, s8, v14
	v_add_co_ci_u32_e32 v23, vcc_lo, s9, v15, vcc_lo
	v_add_co_u32 v16, vcc_lo, s12, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s13, v17, vcc_lo
	s_clause 0x2
	global_store_b32 v[18:19], v8, off
	global_store_b32 v[20:21], v8, off
	global_store_b32 v[22:23], v8, off
	v_add_co_u32 v12, vcc_lo, s12, v12
	v_lshlrev_b64 v[18:19], 2, v[1:2]
	v_add_co_ci_u32_e32 v13, vcc_lo, s13, v13, vcc_lo
	v_add_co_u32 v14, vcc_lo, s12, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s13, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v18, vcc_lo, s10, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, s11, v19, vcc_lo
	s_clause 0x2
	global_store_b32 v[16:17], v8, off
	global_store_b32 v[12:13], v8, off
	global_store_b32 v[14:15], v8, off
	global_store_b32 v[18:19], v8, off
.LBB1_4:                                ; %Flow132
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_6
; %bb.5:
	v_dual_mov_b32 v2, 0 :: v_dual_mul_f32 v29, v11, v11
	s_load_b256 s[24:31], s[0:1], 0x40
	s_mov_b32 s35, 0
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[12:13], 2, v[1:2]
	s_lshl_b64 s[2:3], s[34:35], 2
	v_dual_mov_b32 v8, v2 :: v_dual_add_nc_u32 v1, 1, v7
	s_add_u32 s2, s16, s2
	s_addc_u32 s3, s17, s3
	v_add_co_u32 v12, vcc_lo, s20, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s21, v13, vcc_lo
	v_lshlrev_b64 v[15:16], 2, v[1:2]
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_mov_b32 s37, s35
	global_load_b32 v12, v[12:13], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[13:14], 2, v[12:13]
	v_add_co_u32 v13, vcc_lo, s16, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v14, vcc_lo, s17, v14, vcc_lo
	global_load_b32 v25, v[13:14], off
	s_waitcnt lgkmcnt(0)
	global_load_b32 v27, v2, s[26:27]
	s_load_b32 s40, s[2:3], 0x0
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x60
	s_load_b64 s[20:21], s[0:1], 0x78
	s_load_b64 s[14:15], s[0:1], 0x88
	v_fma_f32 v13, s33, s33, -v29
	v_add_f32_e32 v28, 0x33d6bf95, v11
	s_load_b32 s30, s[30:31], 0x0
	s_load_b32 s31, s[28:29], 0x0
	v_add_f32_e32 v26, 0x358637bd, v11
	v_add_nc_u32_e32 v1, 2, v7
	v_mul_f32_e32 v35, v13, v13
	v_div_scale_f32 v30, null, v28, v28, 1.0
	v_lshlrev_b64 v[13:14], 2, v[7:8]
	v_add_co_u32 v17, s1, s16, v5
	s_delay_alu instid0(VALU_DEP_3)
	v_rcp_f32_e32 v34, v30
	v_add_co_ci_u32_e64 v18, s1, s17, v6, s1
	v_div_scale_f32 v31, vcc_lo, 1.0, v28, 1.0
	s_lshl_b64 s[2:3], s[36:37], 2
	v_add_co_u32 v21, s1, s12, v13
	s_add_u32 s38, s18, s2
	s_addc_u32 s39, s19, s3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v30, v34, 1.0
	s_add_i32 s34, s36, 1
	v_add_co_ci_u32_e64 v22, s1, s13, v14, s1
	s_lshl_b64 s[2:3], s[34:35], 2
	v_add_co_u32 v23, s1, s12, v15
	s_add_u32 s28, s18, s2
	v_add_co_ci_u32_e64 v24, s1, s13, v16, s1
	s_addc_u32 s29, s19, s3
	s_waitcnt lgkmcnt(0)
	s_load_b32 s4, s[4:5], 0x0
	s_add_i32 s34, s36, 2
	v_fmac_f32_e32 v34, v6, v34
	s_lshl_b64 s[16:17], s[34:35], 2
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v8, 0x33d6bf95, v25
	v_lshlrev_b64 v[19:20], 2, v[1:2]
	v_add_f32_e32 v1, s40, v25
	v_div_scale_f32 v32, null, v26, v26, 1.0
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v5, s30, v27
	v_div_scale_f32 v33, s0, 1.0, v26, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v36, v32
	v_fmac_f32_e64 v1, s31, -2.0
	v_div_scale_f32 v42, s1, 1.0, v8, 1.0
	v_div_scale_f32 v43, s2, v27, v8, v27
	v_dual_mul_f32 v38, v5, v1 :: v_dual_mul_f32 v5, v31, v34
	v_div_scale_f32 v1, null, v8, v8, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v7, -v32, v36, 1.0
	v_add_f32_e32 v37, v25, v25
	v_div_scale_f32 v25, null, v8, v8, v27
	v_rcp_f32_e32 v6, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v36, v7, v36
	v_div_scale_f32 v39, null, v37, v37, v38
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v7, v25
	v_div_scale_f32 v47, s3, v38, v37, v38
	v_rcp_f32_e32 v40, v39
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f32 v44, -v1, v6, 1.0
	v_mul_f32_e32 v41, v33, v36
	s_waitcnt_depctr 0xfff
	v_fma_f32 v45, -v25, v7, 1.0
	v_fmac_f32_e32 v6, v44, v6
	v_fma_f32 v44, -v30, v5, v31
	v_fma_f32 v46, -v39, v40, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v7, v45, v7
	v_fma_f32 v45, -v32, v41, v33
	v_dual_fmac_f32 v5, v44, v34 :: v_dual_fmac_f32 v40, v46, v40
	v_mul_f32_e32 v46, v42, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v48, v43, v7
	v_fma_f32 v30, -v30, v5, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v49, v47, v40
	v_fma_f32 v44, -v1, v46, v42
	v_fmac_f32_e32 v41, v45, v36
	v_fma_f32 v45, -v25, v48, v43
	v_div_fmas_f32 v30, v30, v34, v5
	v_fma_f32 v50, -v39, v49, v47
	v_fmac_f32_e32 v46, v44, v6
	v_lshl_add_u32 v5, v12, 1, v12
	v_fmac_f32_e32 v48, v45, v7
	s_mov_b32 vcc_lo, s3
	v_fmac_f32_e32 v49, v50, v40
	v_fma_f32 v1, -v1, v46, v42
	v_fma_f32 v31, -v32, v41, v33
	v_fma_f32 v25, -v25, v48, v43
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, -v39, v49, v47
	v_div_fmas_f32 v32, v12, v40, v49
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f32 v12, v1, v6, v46
	s_mov_b32 vcc_lo, s2
	v_ashrrev_i32_e32 v6, 31, v5
	v_div_fmas_f32 v1, v25, v7, v48
	s_mov_b32 vcc_lo, s0
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v25, s4, v35
	v_div_fmas_f32 v7, v31, v36, v41
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_div_fixup_f32 v1, v1, v8, v27
	v_div_fixup_f32 v8, v12, v8, 1.0
	s_load_b32 s2, s[20:21], 0x0
	s_load_b32 s3, s[24:25], 0x0
	s_load_b32 s4, s[14:15], 0x0
	v_div_fixup_f32 v7, v7, v26, 1.0
	s_add_u32 s0, s18, s16
	v_add_co_u32 v5, vcc_lo, s18, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s19, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v7, v7, v25
	s_addc_u32 s1, s19, s17
	v_add_co_u32 v25, vcc_lo, s12, v19
	v_add_co_ci_u32_e32 v26, vcc_lo, s13, v20, vcc_lo
	v_mul_f32_e32 v31, v10, v7
	v_mul_f32_e32 v33, v0, v7
	v_mul_f32_e32 v7, v9, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v31, v1, v31
	v_mul_f32_e32 v33, v1, v33
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v1, v1, v7
	global_load_b96 v[5:7], v[5:6], off
	s_clause 0x2
	s_load_b32 s5, s[38:39], 0x0
	s_load_b32 s12, s[28:29], 0x0
	s_load_b32 s1, s[0:1], 0x0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_subrev_f32_e32 v6, s12, v6
	s_clause 0x2
	global_store_b32 v[21:22], v31, off
	global_store_b32 v[23:24], v33, off
	global_store_b32 v[25:26], v1, off
	global_load_b32 v1, v[17:18], off
	s_clause 0x2
	global_load_b32 v17, v2, s[26:27]
	global_load_b32 v18, v2, s[6:7]
	global_load_b32 v21, v2, s[22:23]
	v_sub_f32_e32 v22, s33, v11
	v_mul_f32_e32 v24, 0xc0e00000, v11
	s_waitcnt vmcnt(3)
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mul_f32 v24, v11, v24 :: v_dual_add_f32 v23, 0x33d6bf95, v1
	v_add_co_u32 v1, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v2, vcc_lo, s11, v4, vcc_lo
	v_add_co_u32 v3, vcc_lo, s8, v13
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v14, vcc_lo
	v_mul_f32_e32 v14, s3, v27
	s_waitcnt vmcnt(2)
	v_div_scale_f32 v26, null, v23, v23, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v8, v8, v14
	v_mul_f32_e32 v25, s2, v22
	v_rcp_f32_e32 v31, v26
	s_mov_b32 s2, 0x43480000
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v11, v22, v25
	v_div_fixup_f32 v25, v30, v28, 1.0
	v_mul_f32_e32 v13, v25, v11
	s_waitcnt_depctr 0xfff
	v_fma_f32 v11, -v26, v31, 1.0
	v_div_scale_f32 v25, vcc_lo, v17, v23, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v31, v11, v31
	v_add_co_u32 v11, s0, s8, v15
	v_add_co_ci_u32_e64 v12, s0, s9, v16, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v14, v25, v31 :: v_dual_mul_f32 v15, s4, v22
	v_mul_f32_e32 v8, v8, v15
	v_div_fixup_f32 v15, v32, v37, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v22, v8, v6
	v_mul_f32_e32 v0, v0, v13
	v_subrev_f32_e32 v5, s5, v5
	v_mul_f32_e32 v10, v10, v13
	v_fmac_f32_e32 v22, v0, v15
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v16, v8, v5
	v_mul_f32_e32 v9, v9, v13
	v_fma_f32 v13, -v26, v14, v25
	s_waitcnt vmcnt(0)
	v_fma_f32 v5, v21, v21, -v29
	v_fmac_f32_e32 v16, v10, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v14, v13, v31 :: v_dual_mul_f32 v13, 0x40400000, v21
	v_mul_f32_e32 v5, v18, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v6, -v26, v14, v25
	v_dual_fmac_f32 v24, v21, v13 :: v_dual_subrev_f32 v7, s1, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v6, v6, v31, v14
	v_dual_mul_f32 v0, v5, v24 :: v_dual_mul_f32 v7, v8, v7
	v_add_co_u32 v5, vcc_lo, s8, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fixup_f32 v8, v6, v23, v17
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v20, vcc_lo
	v_fmac_f32_e32 v7, v9, v15
	v_minmax_f32 v9, v22, s2, 0xc3480000
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v0, v8, v0
	v_minmax_f32 v8, v16, s2, 0xc3480000
	v_minmax_f32 v7, v7, s2, 0xc3480000
	global_store_b32 v[1:2], v0, off
	s_clause 0x2
	global_store_b32 v[3:4], v8, off
	global_store_b32 v[11:12], v9, off
	global_store_b32 v[5:6], v7, off
.LBB1_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 400
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 51
		.amdhsa_next_free_sgpr 41
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_, .Lfunc_end1-_Z11calc_forcesPfS_S_PKfS1_S_PiS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4020
; NumSgprs: 43
; NumVgprs: 51
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 43
; NumVGPRsForWavesPerEU: 51
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_ ; -- Begin function _Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_
	.globl	_Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_
	.p2align	8
	.type	_Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_,@function
_Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_: ; @_Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_
; %bb.0:
	s_load_b256 s[16:23], s[0:1], 0x40
	s_mul_i32 s2, s15, 3
	s_mov_b32 s4, 0x968915a9
	s_ashr_i32 s3, s2, 31
	s_mov_b32 s6, 0x4222de17
	s_lshl_b64 s[24:25], s[2:3], 2
	s_mov_b32 s5, 0x3fba6564
	s_mov_b32 s7, 0x3fbdee67
	s_mov_b32 s8, 0x652b82fe
	s_mov_b32 s9, 0x3ff71547
	s_mov_b32 s26, s15
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s22, s24
	s_addc_u32 s3, s23, s25
	s_clause 0x1
	s_load_b64 s[22:23], s[2:3], 0x0
	s_load_b32 s28, s[2:3], 0x8
	s_mov_b32 s3, 0x3fe55555
	s_mov_b32 s2, 0x55555555
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e64 v0, s23, s23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e64 v0, s22, s22
	v_fmac_f32_e64 v0, s28, s28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[1:2], v0
	v_frexp_mant_f64_e64 v[3:4], |v[1:2]|
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[3:4]
	v_cndmask_b32_e64 v5, 0, 1, vcc_lo
	v_ldexp_f64 v[3:4], v[3:4], v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[3:4], 1.0
	v_add_f64 v[11:12], v[3:4], -1.0
	v_rcp_f64_e32 v[7:8], v[5:6]
	v_add_f64 v[13:14], v[5:6], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[3:4], v[3:4], -v[13:14]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
	v_fma_f64 v[7:8], v[9:10], v[7:8], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
	v_fma_f64 v[7:8], v[9:10], v[7:8], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[9:10], v[11:12], v[7:8]
	v_mul_f64 v[15:16], v[5:6], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[9:10], v[5:6], -v[15:16]
	v_fma_f64 v[3:4], v[9:10], v[3:4], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[15:16], v[3:4]
	v_add_f64 v[13:14], v[11:12], -v[5:6]
	v_add_f64 v[15:16], v[5:6], -v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[11:12], -v[13:14]
	v_add_f64 v[3:4], v[15:16], -v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[11:12], -v[5:6]
	v_add_f64 v[3:4], v[3:4], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[3:4], v[13:14], v[3:4]
	v_mul_f64 v[3:4], v[7:8], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[9:10], v[3:4]
	v_add_f64 v[7:8], v[5:6], -v[9:10]
	v_mul_f64 v[9:10], v[5:6], v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[3:4], v[3:4], -v[7:8]
	v_fma_f64 v[7:8], v[5:6], v[5:6], -v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[3:4], v[3:4]
	v_fma_f64 v[7:8], v[5:6], v[11:12], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[9:10], v[7:8]
	v_fma_f64 v[13:14], v[11:12], s[6:7], s[4:5]
	s_mov_b32 s4, 0x3abe935a
	s_mov_b32 s5, 0x3fbe25e4
	v_add_f64 v[9:10], v[11:12], -v[9:10]
	v_mul_f64 v[19:20], v[5:6], v[11:12]
	s_mov_b32 s7, 0x3c7abc9e
	s_mov_b32 s6, 0x3b39803f
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[13:14], v[11:12], v[13:14], s[4:5]
	s_mov_b32 s4, 0x47e6c9c2
	s_mov_b32 s5, 0x3fc110ef
	v_add_f64 v[7:8], v[7:8], -v[9:10]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[13:14], v[11:12], v[13:14], s[4:5]
	s_mov_b32 s4, 0xcfa74449
	s_mov_b32 s5, 0x3fc3b13b
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[13:14], v[11:12], v[13:14], s[4:5]
	s_mov_b32 s4, 0x71bf3c30
	s_mov_b32 s5, 0x3fc745d1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[13:14], v[11:12], v[13:14], s[4:5]
	s_mov_b32 s4, 0x1c7792ce
	s_mov_b32 s5, 0x3fcc71c7
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[13:14], v[11:12], v[13:14], s[4:5]
	s_mov_b32 s4, 0x924920da
	s_mov_b32 s5, 0x3fd24924
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[13:14], v[11:12], v[13:14], s[4:5]
	s_mov_b32 s4, 0x9999999c
	s_mov_b32 s5, 0x3fd99999
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[13:14], v[11:12], v[13:14], s[4:5]
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[15:16], v[11:12], v[13:14]
	v_fma_f64 v[9:10], v[11:12], v[13:14], -v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], v[7:8], v[13:14], v[9:10]
	v_add_f64 v[13:14], v[15:16], v[9:10]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[17:18], v[13:14], s[2:3]
	v_add_f64 v[15:16], v[13:14], -v[15:16]
	s_mov_b32 s3, 0xbfe55555
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add_f64 v[21:22], v[17:18], s[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_f64 v[9:10], v[9:10], -v[15:16]
	v_fma_f64 v[15:16], v[11:12], v[5:6], -v[19:20]
	s_mov_b32 s2, 0xd5df274d
	s_mov_b32 s3, 0x3c8543b0
	v_add_f64 v[13:14], v[13:14], -v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[9:10], v[9:10], s[2:3]
	v_fma_f64 v[11:12], v[11:12], v[3:4], v[15:16]
	s_mov_b32 s3, 0x3fe62e42
	s_mov_b32 s2, 0xfefa39ef
	v_ldexp_f64 v[3:4], v[3:4], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[9:10], v[9:10], v[13:14]
	v_fma_f64 v[7:8], v[7:8], v[5:6], v[11:12]
	v_ldexp_f64 v[5:6], v[5:6], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[17:18], v[9:10]
	v_add_f64 v[13:14], v[19:20], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[17:18], -v[11:12]
	v_mul_f64 v[17:18], v[13:14], v[11:12]
	v_add_f64 v[19:20], v[13:14], -v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[9:10], v[9:10], v[15:16]
	v_fma_f64 v[15:16], v[13:14], v[11:12], -v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[7:8], -v[19:20]
	v_fma_f64 v[9:10], v[13:14], v[9:10], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[7:8], v[7:8], v[11:12], v[9:10]
	v_frexp_exp_i32_f64_e32 v11, v[1:2]
	v_add_f64 v[9:10], v[17:18], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v0
	v_cvt_f64_i32_e32 v[11:12], v11
	s_and_b32 s5, vcc_lo, exec_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[5:6], v[9:10]
	v_add_f64 v[15:16], v[9:10], -v[17:18]
	v_mul_f64 v[17:18], v[11:12], s[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[5:6], v[13:14], -v[5:6]
	v_add_f64 v[7:8], v[7:8], -v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[11:12], s[2:3], -v[17:18]
	s_mov_b32 s3, 0x3ff00000
	s_cselect_b32 s5, s3, 0x3fe00000
	s_mov_b32 s3, 0xbfe62e42
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[5:6], v[9:10], -v[5:6]
	v_add_f64 v[3:4], v[3:4], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[7:8], v[11:12], s[6:7], v[15:16]
	s_mov_b32 s7, 0xbc7abc9e
	v_add_f64 v[3:4], v[3:4], v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[17:18], v[7:8]
	v_add_f64 v[9:10], v[13:14], v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[5:6], -v[17:18]
	v_add_f64 v[11:12], v[5:6], v[9:10]
	v_add_f64 v[13:14], v[9:10], -v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[7:8], -v[17:18]
	v_add_f64 v[15:16], v[11:12], -v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[3:4], v[3:4], -v[13:14]
	v_add_f64 v[19:20], v[11:12], -v[15:16]
	v_add_f64 v[9:10], v[9:10], -v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[7:8], v[3:4]
	v_add_f64 v[5:6], v[5:6], -v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[5:6], v[9:10], v[5:6]
	v_add_f64 v[9:10], v[13:14], -v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[13:14], v[5:6]
	v_add_f64 v[13:14], v[13:14], -v[9:10]
	v_add_f64 v[3:4], v[3:4], -v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[11:12], v[5:6]
	v_add_f64 v[7:8], v[7:8], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[15:16], -v[11:12]
	v_add_f64 v[3:4], v[3:4], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[5:6], -v[9:10]
	v_add_f64 v[3:4], v[3:4], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[15:16], v[3:4]
	v_add_f64 v[7:8], v[5:6], -v[15:16]
	v_mul_f64 v[9:10], s[4:5], v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[3:4], v[3:4], -v[7:8]
	v_fma_f64 v[5:6], s[4:5], v[5:6], -v[9:10]
	v_cmp_class_f64_e64 vcc_lo, v[9:10], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[3:4], s[4:5], v[3:4], v[5:6]
	v_add_f64 v[5:6], v[9:10], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v8, v6, v10 :: v_dual_cndmask_b32 v7, v5, v9
	v_add_f64 v[5:6], v[5:6], -v[9:10]
	v_mul_f64 v[11:12], v[7:8], s[8:9]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[7:8]|
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[3:4], v[3:4], -v[5:6]
	v_trunc_f64_e32 v[5:6], s[4:5]
	v_rndne_f64_e32 v[11:12], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v4, 0, v4 :: v_dual_cndmask_b32 v3, 0, v3
	v_fma_f64 v[13:14], v[11:12], s[2:3], v[7:8]
	s_mov_b32 s2, 0xfca7ab0c
	s_mov_b32 s3, 0x3e928af3
	v_cvt_i32_f64_e32 v17, v[11:12]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[13:14], v[11:12], s[6:7], v[13:14]
	s_mov_b32 s6, 0x6a5dcb37
	s_mov_b32 s7, 0x3e5ade15
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], s[6:7], s[2:3]
	s_mov_b32 s2, 0x623fde64
	s_mov_b32 s3, 0x3ec71dee
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
	s_mov_b32 s2, 0x7c89e6b0
	s_mov_b32 s3, 0x3efa0199
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
	s_mov_b32 s2, 0x14761f6e
	s_mov_b32 s3, 0x3f2a01a0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
	s_mov_b32 s2, 0x1852b7b0
	s_mov_b32 s3, 0x3f56c16c
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
	s_mov_b32 s2, 0x11122322
	s_mov_b32 s3, 0x3f811111
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
	s_mov_b32 s2, 0x555502a1
	s_mov_b32 s3, 0x3fa55555
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
	s_mov_b32 s2, 0x55555511
	s_mov_b32 s3, 0x3fc55555
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
	s_mov_b32 s2, 11
	s_mov_b32 s3, 0x3fe00000
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
	v_cmp_nlt_f64_e64 s2, 0x40900000, v[7:8]
	v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], v[13:14], v[15:16], 1.0
	s_and_b32 vcc_lo, s3, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[13:14], v[15:16], 1.0
	v_ldexp_f64 v[9:10], v[11:12], v17
	v_mul_f64 v[11:12], s[4:5], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v10, 0x7ff00000, v10, s2
	v_trunc_f64_e32 v[7:8], v[11:12]
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e32 v9, 0, v9, vcc_lo
	v_cmp_eq_f64_e32 vcc_lo, s[4:5], v[5:6]
	v_cmp_class_f64_e64 s5, v[1:2], 0x204
	v_cndmask_b32_e64 v10, 0, v10, s3
	v_cmp_eq_f32_e64 s4, 0, v0
	v_cmp_neq_f64_e64 s2, v[7:8], v[11:12]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, vcc_lo, s2
	v_cndmask_b32_e32 v1, 0x3ff00000, v2, vcc_lo
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_fma_f64 v[3:4], v[9:10], v[3:4], v[9:10]
	v_cmp_class_f64_e64 s3, v[9:10], 0x204
	s_or_b32 vcc_lo, s4, s5
	s_and_b32 s2, s4, exec_lo
	s_cselect_b32 s2, 0, 0x7ff00000
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_bfi_b32 v2, 0x7fffffff, s2, v2
	v_cndmask_b32_e64 v4, v4, v10, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, v3, v9, s3
	s_load_b512 s[0:15], s[0:1], 0x0
	v_bfi_b32 v4, 0x7fffffff, v4, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v1, v3, 0, vcc_lo
	v_cndmask_b32_e32 v2, v4, v2, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v1, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_load_b32 s6, s[6:7], 0x0
	v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_nle_f32_e32 vcc_lo, s6, v0
	s_cbranch_vccnz .LBB2_2
; %bb.1:
	v_add_f32_e32 v0, 0x33d6bf95, v0
	s_ashr_i32 s27, s26, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[6:7], s[26:27], 2
	s_add_u32 s6, s20, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_scale_f32 v1, null, v0, v0, -1.0
	v_div_scale_f32 v4, vcc_lo, -1.0, v0, -1.0
	s_addc_u32 s7, s21, s7
	v_rcp_f32_e32 v2, v1
	s_load_b32 s12, s[12:13], 0x0
	s_load_b32 s6, s[6:7], 0x0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v3, -v1, v2, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, v3, v2
	v_mul_f32_e32 v3, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, -v1, v3, v4
	v_fmac_f32_e32 v3, v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v1, -v1, v3, v4
	v_div_fmas_f32 v1, v1, v2, v3
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e64 v2, s6, s12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v0, v1, v0, -1.0
	v_mul_f32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v2, s23, v0
	v_mul_f32_e32 v1, s22, v0
	v_mul_f32_e32 v0, s28, v0
	s_branch .LBB2_3
.LBB2_2:
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, 0
	v_mov_b32_e32 v0, 0
.LBB2_3:
	s_load_b32 s6, s[8:9], 0x0
	s_add_u32 s4, s4, s24
	s_addc_u32 s5, s5, s25
	s_load_b32 s12, s[10:11], 0x0
	s_load_b32 s7, s[4:5], 0x0
	s_add_u32 s2, s2, s24
	s_addc_u32 s3, s3, s25
	s_add_u32 s0, s0, s24
	s_addc_u32 s1, s1, s25
	s_load_b32 s13, s[2:3], 0x8
	s_waitcnt lgkmcnt(0)
	v_div_scale_f32 v3, null, s6, s6, 1.0
	v_div_scale_f32 v6, vcc_lo, 1.0, s6, 1.0
	v_add_f32_e32 v1, s7, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	v_fmac_f32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v6, v4
	v_fma_f32 v7, -v3, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v7, v4
	v_fma_f32 v3, -v3, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v3, v3, v4, v5
	v_div_fixup_f32 v3, v3, s6, 1.0
	s_load_b64 s[6:7], s[2:3], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, v1, v3
	v_mul_f32_e32 v1, s12, v1
	s_mov_b32 s12, 0x43480000
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_minmax_f32 v3, v1, s12, 0xc3480000
	v_mov_b32_e32 v1, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f32_e32 v5, s6, v3
	global_store_b32 v1, v5, s[2:3]
	s_clause 0x2
	global_load_b32 v3, v1, s[8:9]
	global_load_b32 v4, v1, s[4:5] offset:4
	global_load_b32 v6, v1, s[10:11]
	s_waitcnt vmcnt(2)
	v_div_scale_f32 v7, null, v3, v3, 1.0
	v_div_scale_f32 v10, vcc_lo, 1.0, v3, 1.0
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v8, v7
	s_waitcnt_depctr 0xfff
	v_fma_f32 v9, -v7, v8, 1.0
	v_fmac_f32_e32 v8, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v9, v10, v8
	v_fma_f32 v11, -v7, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v11, v8
	v_fma_f32 v7, -v7, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v7, v7, v8, v9
	v_div_fixup_f32 v3, v7, v3, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v2, v3
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v2, v6, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_minmax_f32 v2, v2, s12, 0xc3480000
	v_add_f32_e32 v2, s7, v2
	global_store_b32 v1, v2, s[2:3] offset:4
	s_clause 0x2
	global_load_b32 v2, v1, s[4:5] offset:8
	global_load_b32 v3, v1, s[8:9]
	global_load_b32 v4, v1, s[10:11]
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v0, v0, v2
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v2, null, v3, v3, v0
	v_div_scale_f32 v8, vcc_lo, v0, v3, v0
	v_rcp_f32_e32 v6, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v7, -v2, v6, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v7, v6
	v_mul_f32_e32 v7, v8, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, -v2, v7, v8
	v_fmac_f32_e32 v7, v9, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v2, v7, v8
	v_div_fmas_f32 v2, v2, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v0, v2, v3, v0
	v_add_f32_e32 v0, 0xc7ea6000, v0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, v4, v0
	v_minmax_f32 v0, v0, s12, 0xc3480000
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v0, s13, v0
	global_store_b32 v1, v0, s[2:3] offset:8
	s_clause 0x1
	global_load_b32 v0, v1, s[10:11]
	global_load_b96 v[2:4], v1, s[0:1]
	s_waitcnt vmcnt(0)
	v_fma_f32 v5, v5, v0, v2
	global_store_b32 v1, v5, s[0:1]
	s_clause 0x1
	global_load_b32 v0, v1, s[2:3] offset:4
	global_load_b32 v2, v1, s[10:11]
	s_waitcnt vmcnt(0)
	v_fma_f32 v2, v0, v2, v3
	global_store_b32 v1, v2, s[0:1] offset:4
	s_clause 0x1
	global_load_b32 v0, v1, s[2:3] offset:8
	global_load_b32 v3, v1, s[10:11]
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v4, v0, v3
	global_store_b32 v1, v4, s[0:1] offset:8
	global_load_b32 v0, v1, s[14:15]
	s_waitcnt vmcnt(0)
	v_cmp_nlt_f32_e64 s4, v5, -v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB2_5
; %bb.4:
	global_load_b32 v2, v1, s[18:19]
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v0, v2, v0
	global_store_b32 v1, v0, s[0:1]
	s_clause 0x1
	global_load_b32 v0, v1, s[16:17]
	global_load_b32 v2, v1, s[2:3]
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v0, v0, v2
	global_store_b32 v1, v0, s[2:3]
	s_clause 0x1
	global_load_b32 v0, v1, s[14:15]
	global_load_b32 v2, v1, s[0:1] offset:4
.LBB2_5:
	s_waitcnt vmcnt(1)
	v_xor_b32_e32 v1, 0x80000000, v0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_nlt_f32_e32 vcc_lo, v2, v1
	s_cbranch_vccnz .LBB2_7
; %bb.6:
	v_mov_b32_e32 v1, 0
	global_load_b32 v2, v1, s[18:19]
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v0, v2, v0
	global_store_b32 v1, v0, s[0:1] offset:4
	s_clause 0x1
	global_load_b32 v0, v1, s[16:17]
	global_load_b32 v2, v1, s[2:3] offset:4
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v0, v0, v2
	global_store_b32 v1, v0, s[2:3] offset:4
	global_load_b32 v0, v1, s[14:15]
	s_waitcnt vmcnt(0)
	v_xor_b32_e32 v1, 0x80000000, v0
.LBB2_7:
	v_mov_b32_e32 v2, 0
	global_load_b32 v3, v2, s[0:1] offset:8
	s_waitcnt vmcnt(0)
	v_cmp_nlt_f32_e32 vcc_lo, v3, v1
	s_cbranch_vccnz .LBB2_9
; %bb.8:
	global_load_b32 v1, v2, s[18:19]
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v0, v1, v0
	global_store_b32 v2, v0, s[0:1] offset:8
	s_clause 0x1
	global_load_b32 v0, v2, s[16:17]
	global_load_b32 v1, v2, s[2:3] offset:8
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v0, v0, v1
	global_store_b32 v2, v0, s[2:3] offset:8
	global_load_b32 v0, v2, s[14:15]
.LBB2_9:
	global_load_b32 v1, v2, s[0:1]
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f32_e32 vcc_lo, v1, v0
	s_cbranch_vccnz .LBB2_11
; %bb.10:
	v_mov_b32_e32 v1, 0
	global_load_b32 v2, v1, s[18:19]
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v0, v0, v2
	global_store_b32 v1, v0, s[0:1]
	s_clause 0x1
	global_load_b32 v0, v1, s[16:17]
	global_load_b32 v2, v1, s[2:3]
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v0, v0, v2
	global_store_b32 v1, v0, s[2:3]
	global_load_b32 v0, v1, s[14:15]
.LBB2_11:
	v_mov_b32_e32 v1, 0
	global_load_b32 v2, v1, s[0:1] offset:4
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f32_e32 vcc_lo, v2, v0
	s_cbranch_vccnz .LBB2_13
; %bb.12:
	global_load_b32 v2, v1, s[18:19]
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v0, v0, v2
	global_store_b32 v1, v0, s[0:1] offset:4
	s_clause 0x1
	global_load_b32 v0, v1, s[16:17]
	global_load_b32 v2, v1, s[2:3] offset:4
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v0, v0, v2
	global_store_b32 v1, v0, s[2:3] offset:4
	global_load_b32 v0, v1, s[14:15]
.LBB2_13:
	global_load_b32 v1, v1, s[0:1] offset:8
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f32_e32 vcc_lo, v1, v0
	s_cbranch_vccnz .LBB2_15
; %bb.14:
	v_mov_b32_e32 v1, 0
	global_load_b32 v2, v1, s[18:19]
	s_waitcnt vmcnt(0)
	v_fma_f32 v0, 0x41200000, v0, -v2
	global_store_b32 v1, v0, s[0:1] offset:8
	s_clause 0x1
	global_load_b32 v0, v1, s[16:17]
	global_load_b32 v2, v1, s[2:3] offset:8
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v0, v0, v2
	global_store_b32 v1, v0, s[2:3] offset:8
.LBB2_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 96
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 23
		.amdhsa_next_free_sgpr 29
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_, .Lfunc_end2-_Z10update_posPfS_S_PKfS1_S1_S1_S1_S1_S1_S1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3660
; NumSgprs: 31
; NumVgprs: 23
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 31
; NumVGPRsForWavesPerEU: 23
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
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...

	.end_amdgpu_metadata
