// Passing array of a Class and assigning elements at odd/even elements to another array.
// @alpha74

#include "cuda_runtime.h"
#include "device_launch_parameters.h"

#include <iostream>
#include "stdio.h"

using namespace std;

class Coord
{
	int x;
	int y;

	public:
		Coord() 
		{
			x = 0;
			y = 0;
		}
		void set(int a, int b)
		{
			x = a;
			y = b;
		}
		void print()
		{
			printf(" (%d,%d) ", x, y);
		}
};

__global__ void foo( int lim, Coord C[], Coord *oddi, Coord *eveni)
{
	int tid = blockIdx.x;

	if (tid < lim)
	{
		if (tid % 2 == 0)
		{
			eveni[tid / 2] = C[tid];
		}
		else
		{
			oddi[tid / 2] = C[tid];
		}
	}
}

int main()
{
	const int N = 20;

	// Declare an array of size N
	Coord C[N];
	Coord result_odd[ N/2], result_even[ N/2 ];

	// Initialize the elements
	for (int i = 0; i < N; i++)
	{
		if (i % 2 == 0)
		{
			C[i].set(2, 2);
		}
		else
			C[i].set(-1, -1);
	}

	// Declare and allocate device memory
	Coord *dev_C;
	Coord *dev_odd, *dev_even;

	cudaMalloc((void**)&dev_C, N * sizeof(Coord));
	cudaMalloc((void**)&dev_odd, N / 2 * sizeof(Coord));
	cudaMalloc((void**)&dev_even, N / 2 * sizeof(Coord));

	cudaMemcpy(dev_C, C, N * sizeof(Coord), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_odd, C, N/2 * sizeof(Coord), cudaMemcpyHostToDevice);	// Adding part of the array for comparison.
	cudaMemcpy(dev_even, C, N / 2 * sizeof(Coord), cudaMemcpyHostToDevice);	// Adding part of the array for comparison.

	foo <<<N, 1 >>> ( N, dev_C, dev_odd, dev_even );

	// Copying back the results
	cudaMemcpy(&result_even, dev_even, N/2 * sizeof(Coord), cudaMemcpyDeviceToHost);
	cudaMemcpy(&result_odd, dev_odd, N/2 * sizeof(Coord), cudaMemcpyDeviceToHost);

	cout << "\n At even pos: ";
	for (int i = 0 ; i < N / 2; i++)
	{
		result_even[i].print();
	}

	cout << "\n At odd pos: ";
	for (int i = 0; i < N / 2; i++)
	{
		result_odd[i].print();
	}

	cout << "\n ";

	// Freeing device memory

	cudaFree(dev_C);
	cudaFree(dev_odd);
	cudaFree(dev_even);

	return 0;
}

	.file	"tmpxft_00391898_00000000-6_extract_odd_even.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3643:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3643:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z34__device_stub__Z3fooiP5CoordS0_S0_iP5CoordS0_S0_
	.type	_Z34__device_stub__Z3fooiP5CoordS0_S0_iP5CoordS0_S0_, @function
_Z34__device_stub__Z3fooiP5CoordS0_S0_iP5CoordS0_S0_:
.LFB3665:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z3fooiP5CoordS0_S0_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3665:
	.size	_Z34__device_stub__Z3fooiP5CoordS0_S0_iP5CoordS0_S0_, .-_Z34__device_stub__Z3fooiP5CoordS0_S0_iP5CoordS0_S0_
	.globl	_Z3fooiP5CoordS0_S0_
	.type	_Z3fooiP5CoordS0_S0_, @function
_Z3fooiP5CoordS0_S0_:
.LFB3666:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z3fooiP5CoordS0_S0_iP5CoordS0_S0_
	.cfi_endproc
.LFE3666:
	.size	_Z3fooiP5CoordS0_S0_, .-_Z3fooiP5CoordS0_S0_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"\n At even pos: "
.LC1:
	.string	" (%d,%d) "
.LC2:
	.string	"\n At odd pos: "
.LC3:
	.string	"\n "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3640:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$392, %rsp
	.cfi_def_cfa_offset 448
	movq	%fs:40, %rax
	movq	%rax, 376(%rsp)
	xorl	%eax, %eax
	leaq	216(%rsp), %rax
	leaq	376(%rsp), %rdx
	movq	%rax, %rbp
.L9:
	xorl	%esi, %esi
	addq	$8, %rax
	movl	%esi, -8(%rax)
	movl	%esi, -4(%rax)
	cmpq	%rdx, %rax
	jne	.L9
	leaq	56(%rsp), %rbx
	leaq	136(%rsp), %r12
	movq	%rbx, %rax
.L10:
	xorl	%ecx, %ecx
	addq	$8, %rax
	movl	%ecx, -8(%rax)
	movl	%ecx, -4(%rax)
	cmpq	%r12, %rax
	jne	.L10
	movq	%r12, %r13
	movq	%r12, %rax
.L11:
	xorl	%edx, %edx
	addq	$8, %rax
	movl	%edx, -8(%rax)
	movl	%edx, -4(%rax)
	cmpq	%rbp, %rax
	jne	.L11
	xorl	%eax, %eax
.L13:
	movl	%eax, %edx
	andl	$1, %edx
	negl	%edx
	sbbl	%edx, %edx
	orl	$2, %edx
	movl	%edx, 0(%rbp,%rax,8)
	movl	%edx, 4(%rbp,%rax,8)
	incq	%rax
	cmpq	$20, %rax
	jne	.L13
	leaq	8(%rsp), %rdi
	movl	$160, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$80, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$80, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$160, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$80, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$80, %edx
	call	cudaMemcpy@PLT
	movl	$1073741829, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$2, %rdi
	movl	$1, %ecx
	movabsq	$4294967297, %rdx
	movl	$1, %esi
	movq	%rdx, 44(%rsp)
	movl	$1, 52(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	movq	24(%rsp), %rcx
	movq	16(%rsp), %rdx
	movl	$20, %edi
	movq	8(%rsp), %rsi
	call	_Z34__device_stub__Z3fooiP5CoordS0_S0_iP5CoordS0_S0_
.L14:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movl	$80, %edx
	movq	%r12, %rdi
	leaq	_ZSt4cout(%rip), %r14
	leaq	.LC1(%rip), %r15
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$80, %edx
	call	cudaMemcpy@PLT
	movl	$15, %edx
	leaq	.LC0(%rip), %rsi
	movq	%r14, %rdi
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L15:
	movl	4(%r13), %ecx
	movl	0(%r13), %edx
	movq	%r15, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	addq	$8, %r13
	call	__printf_chk@PLT
	cmpq	%rbp, %r13
	jne	.L15
	movl	$14, %edx
	leaq	.LC2(%rip), %rsi
	movq	%r14, %rdi
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L16:
	movl	4(%rbx), %ecx
	movl	(%rbx), %edx
	movq	%r15, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	addq	$8, %rbx
	call	__printf_chk@PLT
	cmpq	%r12, %rbx
	jne	.L16
	movl	$2, %edx
	leaq	.LC3(%rip), %rsi
	movq	%r14, %rdi
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	376(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$392, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3640:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z3fooiP5CoordS0_S0_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3668:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z3fooiP5CoordS0_S0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3668:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// Passing array of a Class and assigning elements at odd/even elements to another array.
// @alpha74

#include "hip/hip_runtime.h"


#include <iostream>
#include "stdio.h"

using namespace std;

class Coord
{
	int x;
	int y;

	public:
		Coord() 
		{
			x = 0;
			y = 0;
		}
		void set(int a, int b)
		{
			x = a;
			y = b;
		}
		void print()
		{
			printf(" (%d,%d) ", x, y);
		}
};

__global__ void foo( int lim, Coord C[], Coord *oddi, Coord *eveni)
{
	int tid = blockIdx.x;

	if (tid < lim)
	{
		if (tid % 2 == 0)
		{
			eveni[tid / 2] = C[tid];
		}
		else
		{
			oddi[tid / 2] = C[tid];
		}
	}
}

int main()
{
	const int N = 20;

	// Declare an array of size N
	Coord C[N];
	Coord result_odd[ N/2], result_even[ N/2 ];

	// Initialize the elements
	for (int i = 0; i < N; i++)
	{
		if (i % 2 == 0)
		{
			C[i].set(2, 2);
		}
		else
			C[i].set(-1, -1);
	}

	// Declare and allocate device memory
	Coord *dev_C;
	Coord *dev_odd, *dev_even;

	hipMalloc((void**)&dev_C, N * sizeof(Coord));
	hipMalloc((void**)&dev_odd, N / 2 * sizeof(Coord));
	hipMalloc((void**)&dev_even, N / 2 * sizeof(Coord));

	hipMemcpy(dev_C, C, N * sizeof(Coord), hipMemcpyHostToDevice);
	hipMemcpy(dev_odd, C, N/2 * sizeof(Coord), hipMemcpyHostToDevice);	// Adding part of the array for comparison.
	hipMemcpy(dev_even, C, N / 2 * sizeof(Coord), hipMemcpyHostToDevice);	// Adding part of the array for comparison.

	foo <<<N, 1 >>> ( N, dev_C, dev_odd, dev_even );

	// Copying back the results
	hipMemcpy(&result_even, dev_even, N/2 * sizeof(Coord), hipMemcpyDeviceToHost);
	hipMemcpy(&result_odd, dev_odd, N/2 * sizeof(Coord), hipMemcpyDeviceToHost);

	cout << "\n At even pos: ";
	for (int i = 0 ; i < N / 2; i++)
	{
		result_even[i].print();
	}

	cout << "\n At odd pos: ";
	for (int i = 0; i < N / 2; i++)
	{
		result_odd[i].print();
	}

	cout << "\n ";

	// Freeing device memory

	hipFree(dev_C);
	hipFree(dev_odd);
	hipFree(dev_even);

	return 0;
}

	.text
	.file	"extract_odd_even.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z18__device_stub__fooiP5CoordS0_S0_ # -- Begin function _Z18__device_stub__fooiP5CoordS0_S0_
	.type	_Z18__device_stub__fooiP5CoordS0_S0_,@function
_Z18__device_stub__fooiP5CoordS0_S0_:   # @_Z18__device_stub__fooiP5CoordS0_S0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3fooiP5CoordS0_S0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z18__device_stub__fooiP5CoordS0_S0_, .Lfunc_end0-_Z18__device_stub__fooiP5CoordS0_S0_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:                                # %.preheader.preheader
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$352, %rsp                      # imm = 0x160
	.cfi_def_cfa_offset 384
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	192(%rsp), %rdi
	xorl	%ebx, %ebx
	movl	$160, %edx
	xorl	%esi, %esi
	callq	memset@PLT
	xorps	%xmm0, %xmm0
	movaps	%xmm0, 176(%rsp)
	movaps	%xmm0, 160(%rsp)
	movaps	%xmm0, 144(%rsp)
	movaps	%xmm0, 128(%rsp)
	movaps	%xmm0, 112(%rsp)
	movaps	%xmm0, 96(%rsp)
	movaps	%xmm0, 80(%rsp)
	movaps	%xmm0, 64(%rsp)
	movaps	%xmm0, 48(%rsp)
	movaps	%xmm0, 32(%rsp)
.LBB1_1:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movl	%ebx, %eax
	andl	$1, %eax
	negl	%eax
	orl	$2, %eax
	movl	%eax, 192(%rsp,%rbx,8)
	movl	%eax, 196(%rsp,%rbx,8)
	incq	%rbx
	cmpq	$20, %rbx
	jne	.LBB1_1
# %bb.2:
	leaq	24(%rsp), %rbx
	movl	$160, %esi
	movq	%rbx, %rdi
	callq	hipMalloc
	leaq	16(%rsp), %r14
	movl	$80, %esi
	movq	%r14, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %r15
	movl	$80, %esi
	movq	%r15, %rdi
	callq	hipMalloc
	movq	(%rbx), %rdi
	leaq	192(%rsp), %rbx
	movl	$160, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r14), %rdi
	movl	$80, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r15), %rdi
	movl	$80, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967297, %rdx               # imm = 0x100000001
	leaq	19(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.3:
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rcx
	movl	$20, %edi
	callq	_Z18__device_stub__fooiP5CoordS0_S0_
.LBB1_4:
	movq	8(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movl	$80, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rsi
	leaq	112(%rsp), %rdi
	movl	$80, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$15, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorl	%ebx, %ebx
.LBB1_5:                                # =>This Inner Loop Header: Depth=1
	movl	32(%rsp,%rbx,8), %esi
	movl	36(%rsp,%rbx,8), %edx
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%rbx
	cmpq	$10, %rbx
	jne	.LBB1_5
# %bb.6:
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$14, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorl	%ebx, %ebx
.LBB1_7:                                # =>This Inner Loop Header: Depth=1
	movl	112(%rsp,%rbx,8), %esi
	movl	116(%rsp,%rbx,8), %edx
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%rbx
	cmpq	$10, %rbx
	jne	.LBB1_7
# %bb.8:
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$2, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$352, %rsp                      # imm = 0x160
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3fooiP5CoordS0_S0_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z3fooiP5CoordS0_S0_,@object    # @_Z3fooiP5CoordS0_S0_
	.section	.rodata,"a",@progbits
	.globl	_Z3fooiP5CoordS0_S0_
	.p2align	3, 0x0
_Z3fooiP5CoordS0_S0_:
	.quad	_Z18__device_stub__fooiP5CoordS0_S0_
	.size	_Z3fooiP5CoordS0_S0_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"\n At even pos: "
	.size	.L.str, 16

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"\n At odd pos: "
	.size	.L.str.1, 15

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"\n "
	.size	.L.str.2, 3

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	" (%d,%d) "
	.size	.L.str.3, 10

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z3fooiP5CoordS0_S0_"
	.size	.L__unnamed_1, 21

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z18__device_stub__fooiP5CoordS0_S0_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z3fooiP5CoordS0_S0_
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z3fooiP5CoordS0_S0_    ; -- Begin function _Z3fooiP5CoordS0_S0_
	.globl	_Z3fooiP5CoordS0_S0_
	.p2align	8
	.type	_Z3fooiP5CoordS0_S0_,@function
_Z3fooiP5CoordS0_S0_:                   ; @_Z3fooiP5CoordS0_S0_
; %bb.0:
	s_load_b32 s3, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_i32 s15, s3
	s_cbranch_scc1 .LBB0_7
; %bb.1:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b64 s[8:9], s[0:1], 0x18
	s_bitcmp1_b32 s15, 0
	s_mov_b32 s2, s15
	s_cselect_b32 s12, -1, 0
	s_ashr_i32 s3, s15, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[10:11], s[2:3], 3
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s4, s10
	s_addc_u32 s1, s5, s11
	s_and_b32 vcc_lo, exec_lo, s12
	s_load_b64 s[0:1], s[0:1], 0x0
	s_cbranch_vccz .LBB0_3
; %bb.2:
	s_lshr_b32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s2, s3
	s_ashr_i32 s4, s3, 1
	s_mov_b32 s3, 0
	s_branch .LBB0_4
.LBB0_3:
	s_mov_b32 s3, -1
                                        ; implicit-def: $sgpr6_sgpr7
                                        ; implicit-def: $sgpr4
.LBB0_4:                                ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_6
; %bb.5:
	s_ashr_i32 s4, s2, 1
	s_mov_b64 s[6:7], s[8:9]
.LBB0_6:                                ; %.sink.split
	s_ashr_i32 s5, s4, 31
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v0, s0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1
	s_lshl_b64 s[2:3], s[4:5], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s6, s2
	s_addc_u32 s1, s7, s3
	global_store_b64 v2, v[0:1], s[0:1]
.LBB0_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3fooiP5CoordS0_S0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z3fooiP5CoordS0_S0_, .Lfunc_end0-_Z3fooiP5CoordS0_S0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 196
; NumSgprs: 18
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z3fooiP5CoordS0_S0_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z3fooiP5CoordS0_S0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
