#include <iostream>
#include <math.h>
#include <vector>
#include <iomanip>
#include <sstream>
#include <string>
#include <fstream>
#include <thread>
#include <ctime>
#include <stdio.h>
__device__ static inline void setSeed(int64_t *seed)
{
    *seed = (*seed ^ 0x5deece66d) & ((1LL << 48) - 1);
}

__device__ static inline int next(int64_t *seed, const int bits)
{
    *seed = (*seed * 0x5deece66d + 0xb) & ((1LL << 48) - 1);
    return (int) (*seed >> (48 - bits));
}

__device__ static inline int nextInt(int64_t *seed, const int n)
{
    int bits, val;
    const int m = n - 1;

    if((m & n) == 0) return (int) ((n * (int64_t)next(seed, 31)) >> 31);

    do {
        bits = next(seed, 31);
        val = bits % n;
    }
    while (bits - val + m < 0);
    return val;
}
__device__ static inline void skip65(int64_t *seed){
    *seed = (*seed * 0xB4500F159B6D  + 0x5593A16ED14B ) & ((1LL << 48) - 1);
}
__device__ static inline void skip63(int64_t *seed){
    *seed = (*seed * 0x89A36E758065 + 0xD75D8F3C9E9 ) & ((1LL << 48) - 1);
}



#define BLOCK_SIZE (256)
#define WORK_SIZE_BITS 20
#define SEEDS_PER_CALL ((1ULL << (WORK_SIZE_BITS)) * (BLOCK_SIZE))

#define GPU_ASSERT(code) gpuAssert((code), __FILE__, __LINE__)
inline void gpuAssert(cudaError_t code, const char *file, int line) {
  if (code != cudaSuccess) {
    fprintf(stderr, "GPUassert: %s (code %d) %s %d\n", cudaGetErrorString(code), code, file, line);
    exit(code);
  }
}


enum Item{
    unset,
    saddle,
    bread,
    bucketEmpty,
    appleGold,
    record,
    wheat,
    gunpowder,
    silk,
    ingotIron,
    redstone
};
struct Pos
{
    int x, z;
};

struct ItemStack{
    Item id;
    int amount;
};
const __device__ ItemStack Chest1[27] = {
    {},
    {},
    {},
    {},
    {},
    {gunpowder, 1}, //5
    {}, //6
    {}, //7 
    {}, //8
    {}, //9
    {}, //10
    {}, //11
    {}, //12
    {}, //13
    {}, //14
    {}, //15
    {}, //16
    {}, //17
    {}, //18
    {}, //19
    {}, //20
    {silk, 1}, //21
    {gunpowder, 1}, //22
    {}, //23
    {}, //24
    {}, //25
    {saddle, 1}, //26
};
const __device__ ItemStack Chest2[27] = {
    {},
    {},
    {},
    {},
    {},
    {bucketEmpty, 1}, //5
    {}, //6
    {gunpowder, 1}, //7
    {saddle, 1}, //8
    {}, //9
    {}, //10
    {}, //11
    {}, //12
    {}, //13
    {wheat, 1}, //14
    {}, //15
    {}, //16
    {}, //17
    {gunpowder, 3}, //18
};
//__device__ ItemStack *Chest1;
//__device__ ItemStack *Chest2;
__device__ static void getItem(ItemStack* tempItem, int64_t* seed){

    int x = nextInt(seed, 11);
    if(x == 0){
        tempItem->id = saddle;
        tempItem->amount = 1;
    }
    if(x == 1){
        tempItem->id = ingotIron;
        tempItem->amount = nextInt(seed, 4) + 1;
    }
    if(x == 2){
        tempItem->id = bread;
        tempItem->amount = 1;
    }
    if(x == 3){
        tempItem->id = wheat;
        tempItem->amount = nextInt(seed, 4) + 1;
    }
    if(x == 4){
        tempItem->id = gunpowder;
        tempItem->amount = nextInt(seed, 4) + 1;
    }
    if(x == 5){
        tempItem->id = silk;
        tempItem->amount = nextInt(seed, 4) + 1;
    }
    if(x == 6){
        tempItem->id = bucketEmpty;
        tempItem->amount = 1;
    }
    if(x == 7 && nextInt(seed, 100) == 0){
        tempItem->id = appleGold;
    }
    if(x == 8 && nextInt(seed, 2) == 0){
        tempItem->id = redstone;
        tempItem->amount = nextInt(seed, 4) + 1;
    }
    if(x == 9 && nextInt(seed, 10) == 0){
        tempItem->id = record;
        tempItem->amount = 1;
        //We don't have one anyway so I'm unconcerned
    }
    if(x > 9){
        tempItem->id = unset;
        tempItem->amount = 1;
    }

}
/*__device__ static void getItem(ItemStack* tempItem, int64_t* seed){
    int x = nextInt(seed, 11);
    switch(x){
        case 0:
            tempItem->id = saddle;
            tempItem->amount = 1;
        case 1:
            tempItem->id = ingotIron;
            tempItem->amount = nextInt(seed, 4) + 1;
        case 2:
            tempItem->id = bread;
            tempItem->amount = 1;
        case 3:
            tempItem->id = wheat;
            tempItem->amount = nextInt(seed, 4) + 1;
        case 4:
            tempItem->id = gunpowder;
            tempItem->amount = nextInt(seed, 4) + 1;
        case 5:
            tempItem->id = silk;
            tempItem->amount = nextInt(seed, 4) + 1;
        case 6:
            tempItem->id = bucketEmpty;
            tempItem->amount = 1;
        case 7:
            if(nextInt(seed, 100) == 0){
                tempItem->id = appleGold;
                tempItem->amount = 1;
            }
        case 8:
            if(nextInt(seed, 2) == 0){
                tempItem->id = redstone;
                tempItem->amount = nextInt(seed, 4) + 1;
            }
        case 9:
            if(nextInt(seed, 10) == 0){
                tempItem->id = record;
                tempItem->amount = 1;
                //We don't have one anyway so I'm unconcerned
            }
        default:
            tempItem->id = unset;
            tempItem->amount = 1;
    }
}*/
__device__ static bool testSeed(int64_t seed){
    int64_t testSeed = seed;
    int64_t permutationSeed = testSeed;
    int chestCounter = 0;
    int itemCounter = 0;
    int firstChest = 0;
    ItemStack firstChestSim[27];
    ItemStack secondChestSim[27];
    for(int i = 0; i < 2; i++){
        for(int i2 = 0; i2 < 3; i2++){
            int curChest = 0;
            /*
                int xChest = (x + random.nextInt(xWiggle * 2 + 1)) - xWiggle;
                int yChest = ySpawner;
                int zChest = (z + random.nextInt(zWiggle * 2 + 1)) - zWiggle;
            */
            int xChest = (nextInt(&permutationSeed, 7));
            int zChest = (nextInt(&permutationSeed, 5));
            if(xChest == 6 && zChest == 2)
                curChest = 2;
            else if(xChest == 4 && zChest == 4)
                curChest = 1;
            if(curChest == firstChest){
                continue;
            }
            if((xChest == 6 && zChest == 2) || xChest == 4 && zChest == 4){
                for(int i3 = 0; i3 <= 8; i3++){
                    ItemStack it;
                    getItem(&it, &permutationSeed);
                    if(it.id != 0){
                        int itemIndex = nextInt(&permutationSeed, 26);
                        if(Chest1[itemIndex].id != 0 && curChest == 1){
                            if(firstChestSim[itemIndex].id == it.id && it.id > record){
                                firstChestSim[itemIndex].amount += it.amount;
                            }
                            else{
                                firstChestSim[itemIndex].id = it.id;
                                firstChestSim[itemIndex].amount = it.amount;
                            }
                        }  
                        if(Chest2[itemIndex].id != 0 && curChest == 2){
                            if(secondChestSim[itemIndex].id == it.id && it.id > record){
                                secondChestSim[itemIndex].amount += it.amount;
                            }
                            else{
                                secondChestSim[itemIndex].id = it.id;
                                secondChestSim[itemIndex].amount = it.amount;
                            }
                        }
                    }
                }
            }
            if(firstChest == 0){
                firstChest = curChest;
            }
        }
    }
    for(int i = 0; i < 27; i++){
        if((firstChestSim[i].id != Chest1[i].id || firstChestSim[i].amount != Chest1[i].amount) || (secondChestSim[i].id != Chest2[i].id || secondChestSim[i].amount != Chest2[i].amount)){
            return false;
        }

    }
    return true;
}
__global__ __launch_bounds__(BLOCK_SIZE,2) static void threadWork(int64_t offset, uint32_t* counter, int64_t* buffer){
    uint64_t seed = (blockIdx.x * blockDim.x + threadIdx.x) + offset;
    int64_t structureSeed = seed;
    int count = 0;
    setSeed(&structureSeed);
    nextInt(&structureSeed, 16);
    nextInt(&structureSeed, 128);
    nextInt(&structureSeed, 16);
    int xWiggle = nextInt(&structureSeed, 2) + 2;
    int zWiggle = nextInt(&structureSeed, 2) + 2;
    if(xWiggle == 3 && zWiggle == 2){
        skip63(&structureSeed);
        if(testSeed(structureSeed)){
            buffer[atomicAdd(counter, 1)] = seed;
        }
    }
}
__device__ int64_t stonks[] = {3033227586,
    11299383782,
    19174124756,
    26213759191,
    30882125013,
    31573082574};
__global__ __launch_bounds__(1,1) static void testFunc(){
    for(int64_t i = 0; i < 6; i++){
        int64_t structureSeed = stonks[i];
        skip63(&structureSeed);
        if(testSeed(structureSeed)){
            printf("THIS SEED IS STONKS: %lld\n", stonks[i]);
        }
        else{
            printf("THIS SEED IS NOT STONKS: %lld\n", stonks[i]);
        }
    }
}

/*__global__ __launch_bounds__(1,1) static void setupChestTables(){
    Chest1 = (ItemStack*) malloc(sizeof(ItemStack) * 27);
    Chest2 = (ItemStack*) malloc(sizeof(ItemStack) * 27);

    Chest1[5].id = gunpowder;
    Chest1[5].amount = 1;
    Chest1[21].id = silk;
    Chest1[21].amount = 1;
    Chest1[22].id = gunpowder;
    Chest1[22].amount = 1;
    Chest1[26].id = saddle;
    Chest1[26].amount = 1;

    Chest2[5].id = bucketEmpty;
    Chest2[5].amount = 1;
    Chest2[7].id = gunpowder;
    Chest2[7].amount = 2;
    Chest2[8].id = saddle;
    Chest2[8].amount = 1;
    Chest2[14].id = wheat;
    Chest2[14].amount = 1;
    Chest2[18].id = gunpowder;
    Chest2[18].amount = 3;
}*/
int64_t* buffer;
uint32_t* counter;

std::vector<int64_t> structureSeeds;
int64_t* structSeedsArr;
int main(int argc, char **argv ){
    int64_t startValue  = 0;
    int64_t total       = 281474976710656; 
    time_t start = time(NULL);
    FILE* fp = fopen("seananners-dloot.txt", "w+");
    double seconds_per_structure_seed = 0.0;
    int thread = 0;
    int curr = 0;

    uint64_t amount = total - startValue;
    int tmpCount = 0;
    GPU_ASSERT(cudaMallocManaged(&buffer, sizeof(int64_t) * SEEDS_PER_CALL));
    GPU_ASSERT(cudaPeekAtLastError());
    GPU_ASSERT(cudaMallocManaged(&counter, sizeof(uint32_t)));
    GPU_ASSERT(cudaPeekAtLastError());

    //setupChestTables<<<1,1>>>();
    //printf("Chest tables set up\n");

    //testFunc<<<1,1>>>();
    for(int i = 0; i < 27; i++){
        printf("%d, %d index: %d\n", Chest1[i].id, Chest1[i].amount, i);
    }
    for(int i = 0; i < 27; i++){
        printf("%d, %d index: %d\n", Chest2[i].id, Chest2[i].amount, i);
    }
    GPU_ASSERT(cudaPeekAtLastError());
    GPU_ASSERT(cudaDeviceSynchronize());
    cudaSetDevice(0);
    GPU_ASSERT(cudaPeekAtLastError());
    GPU_ASSERT(cudaDeviceSynchronize());
    uint64_t countOut = 0;
    uint64_t tempCount;
    for(int64_t offset = 0; offset < amount; offset += SEEDS_PER_CALL){
        int64_t value = startValue + offset;
        threadWork<<<1ULL<<WORK_SIZE_BITS,BLOCK_SIZE>>>(value, counter, buffer);
        GPU_ASSERT(cudaPeekAtLastError());
        GPU_ASSERT(cudaDeviceSynchronize());  
        for(int i = 0; i < *counter; i++){
            int64_t timeGuess = buffer[i];
            fprintf(fp, "%lld\n", timeGuess);
        }
        if(countOut >= 20000000000){
            time_t tempTime = time(NULL);
            uint64_t tempDiff = tempTime - start;
            double sps = (double)offset/(double)tempDiff;
            double percent = ((double)offset/(double)amount) * 100.0;
            printf("Seeds Per Second: %f\tProgress: %f\n", sps, percent);
            countOut = 0;
        }
        *counter = 0;
        countOut += SEEDS_PER_CALL;
    }
    time_t end = time(NULL);
    uint64_t diff = end - start;
    double seedsPerSec = (double)total/(double)diff;
    printf("Time taken: %lld\nSeeds per second: %15.9f", diff, seedsPerSec);
    fclose(fp);
    return 0;
}
	.file	"tmpxft_0038e031_00000000-6_seananners_dloot.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4599:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4599:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.text._ZNSt6vectorIlSaIlEED2Ev,"axG",@progbits,_ZNSt6vectorIlSaIlEED5Ev,comdat
	.align 2
	.weak	_ZNSt6vectorIlSaIlEED2Ev
	.type	_ZNSt6vectorIlSaIlEED2Ev, @function
_ZNSt6vectorIlSaIlEED2Ev:
.LFB5339:
	.cfi_startproc
	endbr64
	movq	(%rdi), %rax
	testq	%rax, %rax
	je	.L2
	movq	16(%rdi), %rsi
	movq	%rax, %rdi
	subq	%rax, %rsi
	jmp	_ZdlPvm@PLT
.L2:
	ret
	.cfi_endproc
.LFE5339:
	.size	_ZNSt6vectorIlSaIlEED2Ev, .-_ZNSt6vectorIlSaIlEED2Ev
	.weak	_ZNSt6vectorIlSaIlEED1Ev
	.set	_ZNSt6vectorIlSaIlEED1Ev,_ZNSt6vectorIlSaIlEED2Ev
	.text
	.type	_ZL33__device_stub__Z10threadWorklPjPllPjPl, @function
_ZL33__device_stub__Z10threadWorklPjPllPjPl:
.LFB4621:
	.cfi_startproc
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L5
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_ZL10threadWorklPjPl(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L5:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L7
	call	__stack_chk_fail@PLT
.L7:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4621:
	.size	_ZL33__device_stub__Z10threadWorklPjPllPjPl, .-_ZL33__device_stub__Z10threadWorklPjPllPjPl
	.type	_ZL10threadWorklPjPl, @function
_ZL10threadWorklPjPl:
.LFB4622:
	.cfi_startproc
	endbr64
	jmp	_ZL33__device_stub__Z10threadWorklPjPllPjPl
	.cfi_endproc
.LFE4622:
	.size	_ZL10threadWorklPjPl, .-_ZL10threadWorklPjPl
	.type	_ZL8testFuncv, @function
_ZL8testFuncv:
.LFB4624:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$4294967297, %rax
	leaq	8(%rsp), %rcx
	movq	%rsp, %rdx
	leaq	28(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1, 24(%rsp)
	movl	$1, 36(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 28(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	8(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_ZL8testFuncv(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 112
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L10:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4624:
	.size	_ZL8testFuncv, .-_ZL8testFuncv
	.section	.rodata._Z9gpuAssert9cudaErrorPKci.str1.1,"aMS",@progbits,1
.LC0:
	.string	"GPUassert: %s (code %d) %s %d\n"
	.section	.text._Z9gpuAssert9cudaErrorPKci,"axG",@progbits,_Z9gpuAssert9cudaErrorPKci,comdat
	.weak	_Z9gpuAssert9cudaErrorPKci
	.type	_Z9gpuAssert9cudaErrorPKci, @function
_Z9gpuAssert9cudaErrorPKci:
.LFB4583:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L14
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movq	%rsi, 8(%rsp)
	call	cudaGetErrorString@PLT
	movq	stderr(%rip), %rdi
	movl	%ebx, %r8d
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rcx
	pushq	%rax
	.cfi_def_cfa_offset 56
	movl	$2, %esi
	xorl	%eax, %eax
	pushq	%rbp
	.cfi_def_cfa_offset 64
	movq	24(%rsp), %r9
	call	__fprintf_chk@PLT
	movl	%ebx, %edi
	call	exit@PLT
.L14:
	.cfi_def_cfa_offset 8
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE4583:
	.size	_Z9gpuAssert9cudaErrorPKci, .-_Z9gpuAssert9cudaErrorPKci
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"w+"
.LC2:
	.string	"seananners-dloot.txt"
.LC3:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/BoySanic/seananners/master/seananners_dloot.cu"
.LC4:
	.string	"%d, %d index: %d\n"
.LC5:
	.string	"%lld\n"
.LC8:
	.string	"Seeds Per Second: %f\tProgress: %f\n"
.LC10:
	.string	"Time taken: %lld\nSeeds per second: %15.9f"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB4596:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%edi, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	leaq	4+_ZL6Chest1(%rip), %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	call	time@PLT
	leaq	.LC1(%rip), %rsi
	leaq	.LC2(%rip), %rdi
	movq	%rax, %rbp
	call	fopen@PLT
	movl	$1, %edx
	movl	$2147483648, %esi
	leaq	buffer(%rip), %rdi
	movq	%rax, 8(%rsp)
	call	cudaMallocManaged@PLT
	movl	$367, %edx
	leaq	.LC3(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKci
	call	cudaPeekAtLastError@PLT
	movl	$368, %edx
	leaq	.LC3(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKci
	movl	$1, %edx
	movl	$4, %esi
	leaq	counter(%rip), %rdi
	call	cudaMallocManaged@PLT
	movl	$369, %edx
	leaq	.LC3(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKci
	call	cudaPeekAtLastError@PLT
	movl	$370, %edx
	leaq	.LC3(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKci
.L20:
	leaq	_ZL6Chest1(%rip), %rax
	movl	(%r14,%r12,8), %ecx
	movl	%r12d, %r8d
	movl	$2, %edi
	movl	(%rax,%r12,8), %edx
	leaq	.LC4(%rip), %r13
	xorl	%eax, %eax
	incq	%r12
	movq	%r13, %rsi
	call	__printf_chk@PLT
	cmpq	$27, %r12
	jne	.L20
	xorl	%r12d, %r12d
	leaq	4+_ZL6Chest2(%rip), %r14
.L21:
	movl	(%r14,%r12,8), %ecx
	movl	%r12d, %r8d
	movq	%r13, %rsi
	movl	$2, %edi
	leaq	_ZL6Chest2(%rip), %rax
	movl	(%rax,%r12,8), %edx
	xorl	%eax, %eax
	incq	%r12
	call	__printf_chk@PLT
	cmpq	$27, %r12
	jne	.L21
	call	cudaPeekAtLastError@PLT
	xorl	%r12d, %r12d
	xorl	%r13d, %r13d
	movl	$382, %edx
	movl	%eax, %edi
	leaq	.LC3(%rip), %rsi
	movabsq	$4294967552, %r14
	call	_Z9gpuAssert9cudaErrorPKci
	call	cudaDeviceSynchronize@PLT
	movl	$383, %edx
	leaq	.LC3(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKci
	xorl	%edi, %edi
	call	cudaSetDevice@PLT
	call	cudaPeekAtLastError@PLT
	movl	$385, %edx
	leaq	.LC3(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKci
	call	cudaDeviceSynchronize@PLT
	movl	$386, %edx
	leaq	.LC3(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKci
.L28:
	movl	$4097, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r14, %rdx
	salq	$20, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%r14, 36(%rsp)
	movl	$1, 44(%rsp)
	movq	%rdi, 24(%rsp)
	movl	$1, 32(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	movq	buffer(%rip), %rdx
	movq	counter(%rip), %rsi
	movq	%r12, %rdi
	call	_ZL33__device_stub__Z10threadWorklPjPllPjPl
.L22:
	call	cudaPeekAtLastError@PLT
	movl	$392, %edx
	xorl	%ebx, %ebx
	leaq	.LC3(%rip), %rsi
	movl	%eax, %edi
	leaq	.LC5(%rip), %r15
	call	_Z9gpuAssert9cudaErrorPKci
	call	cudaDeviceSynchronize@PLT
	movl	$393, %edx
	leaq	.LC3(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKci
.L23:
	movq	counter(%rip), %rax
	cmpl	(%rax), %ebx
	jnb	.L35
	movq	buffer(%rip), %rax
	movq	8(%rsp), %rdi
	movq	%r15, %rdx
	movl	$2, %esi
	movq	(%rax,%rbx,8), %rcx
	xorl	%eax, %eax
	incq	%rbx
	call	__fprintf_chk@PLT
	jmp	.L23
.L35:
	movabsq	$19999999999, %rax
	cmpq	%r13, %rax
	jnb	.L25
	xorl	%edi, %edi
	call	time@PLT
	cvtsi2sdq	%r12, %xmm0
	movsd	.LC6(%rip), %xmm1
	mulsd	%xmm0, %xmm1
	mulsd	.LC7(%rip), %xmm1
	subq	%rbp, %rax
	js	.L26
	cvtsi2sdq	%rax, %xmm2
	jmp	.L27
.L26:
	movq	%rax, %rdx
	andl	$1, %eax
	shrq	%rdx
	orq	%rax, %rdx
	cvtsi2sdq	%rdx, %xmm2
	addsd	%xmm2, %xmm2
.L27:
	divsd	%xmm2, %xmm0
	leaq	.LC8(%rip), %rsi
	movb	$2, %al
	xorl	%r13d, %r13d
	movl	$2, %edi
	call	__printf_chk@PLT
.L25:
	movq	counter(%rip), %rax
	xorl	%edx, %edx
	addq	$268435456, %r12
	addq	$268435456, %r13
	movl	%edx, (%rax)
	movl	$1, %eax
	salq	$48, %rax
	cmpq	%rax, %r12
	jne	.L28
	xorl	%edi, %edi
	call	time@PLT
	subq	%rbp, %rax
	movq	%rax, %rdx
	js	.L29
	cvtsi2sdq	%rax, %xmm1
	jmp	.L30
.L29:
	movq	%rdx, %rcx
	shrq	%rax
	andl	$1, %ecx
	orq	%rcx, %rax
	cvtsi2sdq	%rax, %xmm1
	addsd	%xmm1, %xmm1
.L30:
	movsd	.LC9(%rip), %xmm0
	leaq	.LC10(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	divsd	%xmm1, %xmm0
	call	__printf_chk@PLT
	movq	8(%rsp), %rdi
	call	fclose@PLT
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4596:
	.size	main, .-main
	.section	.rodata.str1.1
.LC11:
	.string	"_Z8testFuncv"
.LC12:
	.string	"_Z10threadWorklPjPl"
.LC13:
	.string	"Chest1"
.LC14:
	.string	"Chest2"
.LC15:
	.string	"stonks"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4626:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_ZL8testFuncv(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZL10threadWorklPjPl(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	movl	$216, %r9d
	leaq	_ZL6Chest1(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC14(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$216, %r9d
	leaq	_ZL6Chest2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$48, %r9d
	movq	%rdx, %rcx
	leaq	_ZL6stonks(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r8
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4626:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.text.startup
	.type	_GLOBAL__sub_I_buffer, @function
_GLOBAL__sub_I_buffer:
.LFB5345:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
	leaq	__dso_handle(%rip), %rdx
	leaq	structureSeeds(%rip), %rsi
	leaq	_ZNSt6vectorIlSaIlEED1Ev(%rip), %rdi
	movq	%rax, structureSeeds(%rip)
	movq	%rax, 8+structureSeeds(%rip)
	movq	%rax, 16+structureSeeds(%rip)
	jmp	__cxa_atexit@PLT
	.cfi_endproc
.LFE5345:
	.size	_GLOBAL__sub_I_buffer, .-_GLOBAL__sub_I_buffer
	.section	.init_array
	.align 8
	.quad	_GLOBAL__sub_I_buffer
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	structSeedsArr
	.bss
	.align 8
	.type	structSeedsArr, @object
	.size	structSeedsArr, 8
structSeedsArr:
	.zero	8
	.globl	structureSeeds
	.align 16
	.type	structureSeeds, @object
	.size	structureSeeds, 24
structureSeeds:
	.zero	24
	.globl	counter
	.align 8
	.type	counter, @object
	.size	counter, 8
counter:
	.zero	8
	.globl	buffer
	.align 8
	.type	buffer, @object
	.size	buffer, 8
buffer:
	.zero	8
	.local	_ZL6stonks
	.comm	_ZL6stonks,48,32
	.section	.rodata
	.align 32
	.type	_ZL6Chest2, @object
	.size	_ZL6Chest2, 216
_ZL6Chest2:
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.long	3
	.long	1
	.zero	8
	.long	7
	.long	1
	.long	1
	.long	1
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.long	6
	.long	1
	.zero	8
	.zero	8
	.zero	8
	.long	7
	.long	3
	.zero	64
	.align 32
	.type	_ZL6Chest1, @object
	.size	_ZL6Chest1, 216
_ZL6Chest1:
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.long	7
	.long	1
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.long	8
	.long	1
	.long	7
	.long	1
	.zero	8
	.zero	8
	.zero	8
	.long	1
	.long	1
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC6:
	.long	0
	.long	1022361600
	.align 8
.LC7:
	.long	0
	.long	1079574528
	.align 8
.LC9:
	.long	0
	.long	1123024896
	.hidden	__dso_handle
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <vector>
#include <iomanip>
#include <sstream>
#include <string>
#include <fstream>
#include <thread>
#include <ctime>
#include <stdio.h>
__device__ static inline void setSeed(int64_t *seed)
{
    *seed = (*seed ^ 0x5deece66d) & ((1LL << 48) - 1);
}

__device__ static inline int next(int64_t *seed, const int bits)
{
    *seed = (*seed * 0x5deece66d + 0xb) & ((1LL << 48) - 1);
    return (int) (*seed >> (48 - bits));
}

__device__ static inline int nextInt(int64_t *seed, const int n)
{
    int bits, val;
    const int m = n - 1;

    if((m & n) == 0) return (int) ((n * (int64_t)next(seed, 31)) >> 31);

    do {
        bits = next(seed, 31);
        val = bits % n;
    }
    while (bits - val + m < 0);
    return val;
}
__device__ static inline void skip65(int64_t *seed){
    *seed = (*seed * 0xB4500F159B6D  + 0x5593A16ED14B ) & ((1LL << 48) - 1);
}
__device__ static inline void skip63(int64_t *seed){
    *seed = (*seed * 0x89A36E758065 + 0xD75D8F3C9E9 ) & ((1LL << 48) - 1);
}



#define BLOCK_SIZE (256)
#define WORK_SIZE_BITS 20
#define SEEDS_PER_CALL ((1ULL << (WORK_SIZE_BITS)) * (BLOCK_SIZE))

#define GPU_ASSERT(code) gpuAssert((code), __FILE__, __LINE__)
inline void gpuAssert(hipError_t code, const char *file, int line) {
  if (code != hipSuccess) {
    fprintf(stderr, "GPUassert: %s (code %d) %s %d\n", hipGetErrorString(code), code, file, line);
    exit(code);
  }
}


enum Item{
    unset,
    saddle,
    bread,
    bucketEmpty,
    appleGold,
    record,
    wheat,
    gunpowder,
    silk,
    ingotIron,
    redstone
};
struct Pos
{
    int x, z;
};

struct ItemStack{
    Item id;
    int amount;
};
const __device__ ItemStack Chest1[27] = {
    {},
    {},
    {},
    {},
    {},
    {gunpowder, 1}, //5
    {}, //6
    {}, //7 
    {}, //8
    {}, //9
    {}, //10
    {}, //11
    {}, //12
    {}, //13
    {}, //14
    {}, //15
    {}, //16
    {}, //17
    {}, //18
    {}, //19
    {}, //20
    {silk, 1}, //21
    {gunpowder, 1}, //22
    {}, //23
    {}, //24
    {}, //25
    {saddle, 1}, //26
};
const __device__ ItemStack Chest2[27] = {
    {},
    {},
    {},
    {},
    {},
    {bucketEmpty, 1}, //5
    {}, //6
    {gunpowder, 1}, //7
    {saddle, 1}, //8
    {}, //9
    {}, //10
    {}, //11
    {}, //12
    {}, //13
    {wheat, 1}, //14
    {}, //15
    {}, //16
    {}, //17
    {gunpowder, 3}, //18
};
//__device__ ItemStack *Chest1;
//__device__ ItemStack *Chest2;
__device__ static void getItem(ItemStack* tempItem, int64_t* seed){

    int x = nextInt(seed, 11);
    if(x == 0){
        tempItem->id = saddle;
        tempItem->amount = 1;
    }
    if(x == 1){
        tempItem->id = ingotIron;
        tempItem->amount = nextInt(seed, 4) + 1;
    }
    if(x == 2){
        tempItem->id = bread;
        tempItem->amount = 1;
    }
    if(x == 3){
        tempItem->id = wheat;
        tempItem->amount = nextInt(seed, 4) + 1;
    }
    if(x == 4){
        tempItem->id = gunpowder;
        tempItem->amount = nextInt(seed, 4) + 1;
    }
    if(x == 5){
        tempItem->id = silk;
        tempItem->amount = nextInt(seed, 4) + 1;
    }
    if(x == 6){
        tempItem->id = bucketEmpty;
        tempItem->amount = 1;
    }
    if(x == 7 && nextInt(seed, 100) == 0){
        tempItem->id = appleGold;
    }
    if(x == 8 && nextInt(seed, 2) == 0){
        tempItem->id = redstone;
        tempItem->amount = nextInt(seed, 4) + 1;
    }
    if(x == 9 && nextInt(seed, 10) == 0){
        tempItem->id = record;
        tempItem->amount = 1;
        //We don't have one anyway so I'm unconcerned
    }
    if(x > 9){
        tempItem->id = unset;
        tempItem->amount = 1;
    }

}
/*__device__ static void getItem(ItemStack* tempItem, int64_t* seed){
    int x = nextInt(seed, 11);
    switch(x){
        case 0:
            tempItem->id = saddle;
            tempItem->amount = 1;
        case 1:
            tempItem->id = ingotIron;
            tempItem->amount = nextInt(seed, 4) + 1;
        case 2:
            tempItem->id = bread;
            tempItem->amount = 1;
        case 3:
            tempItem->id = wheat;
            tempItem->amount = nextInt(seed, 4) + 1;
        case 4:
            tempItem->id = gunpowder;
            tempItem->amount = nextInt(seed, 4) + 1;
        case 5:
            tempItem->id = silk;
            tempItem->amount = nextInt(seed, 4) + 1;
        case 6:
            tempItem->id = bucketEmpty;
            tempItem->amount = 1;
        case 7:
            if(nextInt(seed, 100) == 0){
                tempItem->id = appleGold;
                tempItem->amount = 1;
            }
        case 8:
            if(nextInt(seed, 2) == 0){
                tempItem->id = redstone;
                tempItem->amount = nextInt(seed, 4) + 1;
            }
        case 9:
            if(nextInt(seed, 10) == 0){
                tempItem->id = record;
                tempItem->amount = 1;
                //We don't have one anyway so I'm unconcerned
            }
        default:
            tempItem->id = unset;
            tempItem->amount = 1;
    }
}*/
__device__ static bool testSeed(int64_t seed){
    int64_t testSeed = seed;
    int64_t permutationSeed = testSeed;
    int chestCounter = 0;
    int itemCounter = 0;
    int firstChest = 0;
    ItemStack firstChestSim[27];
    ItemStack secondChestSim[27];
    for(int i = 0; i < 2; i++){
        for(int i2 = 0; i2 < 3; i2++){
            int curChest = 0;
            /*
                int xChest = (x + random.nextInt(xWiggle * 2 + 1)) - xWiggle;
                int yChest = ySpawner;
                int zChest = (z + random.nextInt(zWiggle * 2 + 1)) - zWiggle;
            */
            int xChest = (nextInt(&permutationSeed, 7));
            int zChest = (nextInt(&permutationSeed, 5));
            if(xChest == 6 && zChest == 2)
                curChest = 2;
            else if(xChest == 4 && zChest == 4)
                curChest = 1;
            if(curChest == firstChest){
                continue;
            }
            if((xChest == 6 && zChest == 2) || xChest == 4 && zChest == 4){
                for(int i3 = 0; i3 <= 8; i3++){
                    ItemStack it;
                    getItem(&it, &permutationSeed);
                    if(it.id != 0){
                        int itemIndex = nextInt(&permutationSeed, 26);
                        if(Chest1[itemIndex].id != 0 && curChest == 1){
                            if(firstChestSim[itemIndex].id == it.id && it.id > record){
                                firstChestSim[itemIndex].amount += it.amount;
                            }
                            else{
                                firstChestSim[itemIndex].id = it.id;
                                firstChestSim[itemIndex].amount = it.amount;
                            }
                        }  
                        if(Chest2[itemIndex].id != 0 && curChest == 2){
                            if(secondChestSim[itemIndex].id == it.id && it.id > record){
                                secondChestSim[itemIndex].amount += it.amount;
                            }
                            else{
                                secondChestSim[itemIndex].id = it.id;
                                secondChestSim[itemIndex].amount = it.amount;
                            }
                        }
                    }
                }
            }
            if(firstChest == 0){
                firstChest = curChest;
            }
        }
    }
    for(int i = 0; i < 27; i++){
        if((firstChestSim[i].id != Chest1[i].id || firstChestSim[i].amount != Chest1[i].amount) || (secondChestSim[i].id != Chest2[i].id || secondChestSim[i].amount != Chest2[i].amount)){
            return false;
        }

    }
    return true;
}
__global__ __launch_bounds__(BLOCK_SIZE,2) static void threadWork(int64_t offset, uint32_t* counter, int64_t* buffer){
    uint64_t seed = (blockIdx.x * blockDim.x + threadIdx.x) + offset;
    int64_t structureSeed = seed;
    int count = 0;
    setSeed(&structureSeed);
    nextInt(&structureSeed, 16);
    nextInt(&structureSeed, 128);
    nextInt(&structureSeed, 16);
    int xWiggle = nextInt(&structureSeed, 2) + 2;
    int zWiggle = nextInt(&structureSeed, 2) + 2;
    if(xWiggle == 3 && zWiggle == 2){
        skip63(&structureSeed);
        if(testSeed(structureSeed)){
            buffer[atomicAdd(counter, 1)] = seed;
        }
    }
}
__device__ int64_t stonks[] = {3033227586,
    11299383782,
    19174124756,
    26213759191,
    30882125013,
    31573082574};
__global__ __launch_bounds__(1,1) static void testFunc(){
    for(int64_t i = 0; i < 6; i++){
        int64_t structureSeed = stonks[i];
        skip63(&structureSeed);
        if(testSeed(structureSeed)){
            printf("THIS SEED IS STONKS: %lld\n", stonks[i]);
        }
        else{
            printf("THIS SEED IS NOT STONKS: %lld\n", stonks[i]);
        }
    }
}

/*__global__ __launch_bounds__(1,1) static void setupChestTables(){
    Chest1 = (ItemStack*) malloc(sizeof(ItemStack) * 27);
    Chest2 = (ItemStack*) malloc(sizeof(ItemStack) * 27);

    Chest1[5].id = gunpowder;
    Chest1[5].amount = 1;
    Chest1[21].id = silk;
    Chest1[21].amount = 1;
    Chest1[22].id = gunpowder;
    Chest1[22].amount = 1;
    Chest1[26].id = saddle;
    Chest1[26].amount = 1;

    Chest2[5].id = bucketEmpty;
    Chest2[5].amount = 1;
    Chest2[7].id = gunpowder;
    Chest2[7].amount = 2;
    Chest2[8].id = saddle;
    Chest2[8].amount = 1;
    Chest2[14].id = wheat;
    Chest2[14].amount = 1;
    Chest2[18].id = gunpowder;
    Chest2[18].amount = 3;
}*/
int64_t* buffer;
uint32_t* counter;

std::vector<int64_t> structureSeeds;
int64_t* structSeedsArr;
int main(int argc, char **argv ){
    int64_t startValue  = 0;
    int64_t total       = 281474976710656; 
    time_t start = time(NULL);
    FILE* fp = fopen("seananners-dloot.txt", "w+");
    double seconds_per_structure_seed = 0.0;
    int thread = 0;
    int curr = 0;

    uint64_t amount = total - startValue;
    int tmpCount = 0;
    GPU_ASSERT(hipMallocManaged(&buffer, sizeof(int64_t) * SEEDS_PER_CALL));
    GPU_ASSERT(hipPeekAtLastError());
    GPU_ASSERT(hipMallocManaged(&counter, sizeof(uint32_t)));
    GPU_ASSERT(hipPeekAtLastError());

    //setupChestTables<<<1,1>>>();
    //printf("Chest tables set up\n");

    //testFunc<<<1,1>>>();
    for(int i = 0; i < 27; i++){
        printf("%d, %d index: %d\n", Chest1[i].id, Chest1[i].amount, i);
    }
    for(int i = 0; i < 27; i++){
        printf("%d, %d index: %d\n", Chest2[i].id, Chest2[i].amount, i);
    }
    GPU_ASSERT(hipPeekAtLastError());
    GPU_ASSERT(hipDeviceSynchronize());
    hipSetDevice(0);
    GPU_ASSERT(hipPeekAtLastError());
    GPU_ASSERT(hipDeviceSynchronize());
    uint64_t countOut = 0;
    uint64_t tempCount;
    for(int64_t offset = 0; offset < amount; offset += SEEDS_PER_CALL){
        int64_t value = startValue + offset;
        threadWork<<<1ULL<<WORK_SIZE_BITS,BLOCK_SIZE>>>(value, counter, buffer);
        GPU_ASSERT(hipPeekAtLastError());
        GPU_ASSERT(hipDeviceSynchronize());  
        for(int i = 0; i < *counter; i++){
            int64_t timeGuess = buffer[i];
            fprintf(fp, "%lld\n", timeGuess);
        }
        if(countOut >= 20000000000){
            time_t tempTime = time(NULL);
            uint64_t tempDiff = tempTime - start;
            double sps = (double)offset/(double)tempDiff;
            double percent = ((double)offset/(double)amount) * 100.0;
            printf("Seeds Per Second: %f\tProgress: %f\n", sps, percent);
            countOut = 0;
        }
        *counter = 0;
        countOut += SEEDS_PER_CALL;
    }
    time_t end = time(NULL);
    uint64_t diff = end - start;
    double seedsPerSec = (double)total/(double)diff;
    printf("Time taken: %lld\nSeeds per second: %15.9f", diff, seedsPerSec);
    fclose(fp);
    return 0;
}
	.text
	.file	"seananners_dloot.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.section	.text._ZNSt6vectorIlSaIlEED2Ev,"axG",@progbits,_ZNSt6vectorIlSaIlEED2Ev,comdat
	.weak	_ZNSt6vectorIlSaIlEED2Ev        # -- Begin function _ZNSt6vectorIlSaIlEED2Ev
	.p2align	1, 0x90
	.type	_ZNSt6vectorIlSaIlEED2Ev,@function
_ZNSt6vectorIlSaIlEED2Ev:               # @_ZNSt6vectorIlSaIlEED2Ev
	.cfi_startproc
# %bb.0:
	movq	(%rdi), %rdi
	testq	%rdi, %rdi
	jne	_ZdlPv                          # TAILCALL
# %bb.1:                                # %_ZNSt12_Vector_baseIlSaIlEED2Ev.exit
	retq
.Lfunc_end0:
	.size	_ZNSt6vectorIlSaIlEED2Ev, .Lfunc_end0-_ZNSt6vectorIlSaIlEED2Ev
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	1127219200                      # 0x43300000
	.long	1160773632                      # 0x45300000
	.long	0                               # 0x0
	.long	0                               # 0x0
.LCPI1_1:
	.quad	0x4330000000000000              # double 4503599627370496
	.quad	0x4530000000000000              # double 1.9342813113834067E+25
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI1_2:
	.quad	0x3cf0000000000000              # double 3.5527136788005009E-15
.LCPI1_3:
	.quad	0x4059000000000000              # double 100
.LCPI1_4:
	.quad	0x42f0000000000000              # double 281474976710656
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	xorl	%edi, %edi
	callq	time
	movq	%rax, (%rsp)                    # 8-byte Spill
	movl	$.L.str, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	movq	%rax, %rbx
	movl	$buffer, %edi
	movl	$2147483648, %esi               # imm = 0x80000000
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	jne	.LBB1_1
# %bb.3:                                # %_Z9gpuAssert10hipError_tPKci.exit
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.5:                                # %_Z9gpuAssert10hipError_tPKci.exit47
	movl	$counter, %edi
	movl	$4, %esi
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.7:                                # %_Z9gpuAssert10hipError_tPKci.exit49
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB1_33
# %bb.8:                                # %_Z9gpuAssert10hipError_tPKci.exit51.preheader
	xorl	%ebp, %ebp
.LBB1_9:                                # %_Z9gpuAssert10hipError_tPKci.exit51
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str.3, %edi
	movl	%ebp, %ecx
	xorl	%eax, %eax
	callq	printf
	incl	%ebp
	cmpl	$27, %ebp
	jne	.LBB1_9
# %bb.10:                               # %.preheader.preheader
	xorl	%ebp, %ebp
.LBB1_11:                               # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str.3, %edi
	movl	%ebp, %ecx
	xorl	%eax, %eax
	callq	printf
	incl	%ebp
	cmpl	$27, %ebp
	jne	.LBB1_11
# %bb.12:
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB1_13
# %bb.14:                               # %_Z9gpuAssert10hipError_tPKci.exit53
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB1_15
# %bb.16:                               # %_Z9gpuAssert10hipError_tPKci.exit55
	xorl	%edi, %edi
	callq	hipSetDevice
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB1_17
# %bb.18:                               # %_Z9gpuAssert10hipError_tPKci.exit57
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB1_24
# %bb.19:                               # %_Z9gpuAssert10hipError_tPKci.exit59.preheader.preheader
	movabsq	$4294967552, %rax               # imm = 0x100000100
	leaq	1048320(%rax), %r12
	movl	$268435456, %r14d               # imm = 0x10000000
	xorl	%r15d, %r15d
	xorl	%r13d, %r13d
.LBB1_20:                               # %_Z9gpuAssert10hipError_tPKci.exit59.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_28 Depth 2
	movq	%r12, %rdi
	movl	$1, %esi
	movabsq	$4294967552, %rdx               # imm = 0x100000100
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_22
# %bb.21:                               #   in Loop: Header=BB1_20 Depth=1
	movq	counter(%rip), %rsi
	movq	buffer(%rip), %rdx
	movq	%r13, %rdi
	callq	_ZL25__device_stub__threadWorklPjPl
.LBB1_22:                               #   in Loop: Header=BB1_20 Depth=1
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB1_23
# %bb.25:                               # %_Z9gpuAssert10hipError_tPKci.exit61
                                        #   in Loop: Header=BB1_20 Depth=1
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB1_34
# %bb.26:                               # %_Z9gpuAssert10hipError_tPKci.exit63.preheader
                                        #   in Loop: Header=BB1_20 Depth=1
	movq	counter(%rip), %rax
	cmpl	$0, (%rax)
	je	.LBB1_29
# %bb.27:                               # %_Z9gpuAssert10hipError_tPKci.exit63.preheader104
                                        #   in Loop: Header=BB1_20 Depth=1
	xorl	%ebp, %ebp
.LBB1_28:                               # %_Z9gpuAssert10hipError_tPKci.exit63
                                        #   Parent Loop BB1_20 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	buffer(%rip), %rax
	movq	(%rax,%rbp,8), %rdx
	movl	$.L.str.4, %esi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	callq	fprintf
	incq	%rbp
	movq	counter(%rip), %rax
	movl	(%rax), %ecx
	cmpq	%rcx, %rbp
	jb	.LBB1_28
.LBB1_29:                               # %_Z9gpuAssert10hipError_tPKci.exit63._crit_edge
                                        #   in Loop: Header=BB1_20 Depth=1
	movq	%r15, %rcx
	shrq	$11, %rcx
	cmpq	$9765624, %rcx                  # imm = 0x9502F8
	jbe	.LBB1_31
# %bb.30:                               #   in Loop: Header=BB1_20 Depth=1
	xorl	%edi, %edi
	callq	time
	subq	(%rsp), %rax                    # 8-byte Folded Reload
	xorps	%xmm1, %xmm1
	cvtsi2sd	%r13, %xmm1
	movq	%rax, %xmm0
	punpckldq	.LCPI1_0(%rip), %xmm0   # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
	subpd	.LCPI1_1(%rip), %xmm0
	movapd	%xmm0, %xmm2
	unpckhpd	%xmm0, %xmm2                    # xmm2 = xmm2[1],xmm0[1]
	addsd	%xmm0, %xmm2
	movapd	%xmm1, %xmm0
	divsd	%xmm2, %xmm0
	mulsd	.LCPI1_2(%rip), %xmm1
	mulsd	.LCPI1_3(%rip), %xmm1
	movl	$.L.str.5, %edi
	movb	$2, %al
	callq	printf
	movq	counter(%rip), %rax
	xorl	%r15d, %r15d
.LBB1_31:                               # %_Z9gpuAssert10hipError_tPKci.exit59
                                        #   in Loop: Header=BB1_20 Depth=1
	movl	$0, (%rax)
	addq	%r14, %r15
	leaq	(%r14,%r13), %rax
	shrq	$28, %r13
	cmpq	$1048575, %r13                  # imm = 0xFFFFF
	movq	%rax, %r13
	jb	.LBB1_20
# %bb.32:
	xorl	%edi, %edi
	callq	time
	subq	(%rsp), %rax                    # 8-byte Folded Reload
	movq	%rax, %xmm0
	punpckldq	.LCPI1_0(%rip), %xmm0   # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
	subpd	.LCPI1_1(%rip), %xmm0
	movapd	%xmm0, %xmm1
	unpckhpd	%xmm0, %xmm1                    # xmm1 = xmm1[1],xmm0[1]
	addsd	%xmm0, %xmm1
	movsd	.LCPI1_4(%rip), %xmm0           # xmm0 = mem[0],zero
	divsd	%xmm1, %xmm0
	movl	$.L.str.6, %edi
	movq	%rax, %rsi
	movb	$1, %al
	callq	printf
	movq	%rbx, %rdi
	callq	fclose
	xorl	%eax, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_34:
	.cfi_def_cfa_offset 64
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.7, %esi
	movl	$.L.str.2, %r8d
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	%ebp, %ecx
	movl	$395, %r9d                      # imm = 0x18B
	jmp	.LBB1_2
.LBB1_23:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.7, %esi
	movl	$.L.str.2, %r8d
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	%ebp, %ecx
	movl	$394, %r9d                      # imm = 0x18A
.LBB1_2:
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebp, %edi
	callq	exit
.LBB1_1:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.7, %esi
	movl	$.L.str.2, %r8d
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	%ebp, %ecx
	movl	$369, %r9d                      # imm = 0x171
	jmp	.LBB1_2
.LBB1_4:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.7, %esi
	movl	$.L.str.2, %r8d
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	%ebp, %ecx
	movl	$370, %r9d                      # imm = 0x172
	jmp	.LBB1_2
.LBB1_6:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.7, %esi
	movl	$.L.str.2, %r8d
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	%ebp, %ecx
	movl	$371, %r9d                      # imm = 0x173
	jmp	.LBB1_2
.LBB1_33:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.7, %esi
	movl	$.L.str.2, %r8d
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	%ebp, %ecx
	movl	$372, %r9d                      # imm = 0x174
	jmp	.LBB1_2
.LBB1_13:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.7, %esi
	movl	$.L.str.2, %r8d
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	%ebp, %ecx
	movl	$384, %r9d                      # imm = 0x180
	jmp	.LBB1_2
.LBB1_15:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.7, %esi
	movl	$.L.str.2, %r8d
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	%ebp, %ecx
	movl	$385, %r9d                      # imm = 0x181
	jmp	.LBB1_2
.LBB1_17:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.7, %esi
	movl	$.L.str.2, %r8d
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	%ebp, %ecx
	movl	$387, %r9d                      # imm = 0x183
	jmp	.LBB1_2
.LBB1_24:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.7, %esi
	movl	$.L.str.2, %r8d
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	%ebp, %ecx
	movl	$388, %r9d                      # imm = 0x184
	jmp	.LBB1_2
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.type	_ZL25__device_stub__threadWorklPjPl,@function # -- Begin function _ZL25__device_stub__threadWorklPjPl
_ZL25__device_stub__threadWorklPjPl:    # @_ZL25__device_stub__threadWorklPjPl
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL10threadWorklPjPl, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_ZL25__device_stub__threadWorklPjPl, .Lfunc_end2-_ZL25__device_stub__threadWorklPjPl
	.cfi_endproc
                                        # -- End function
	.section	.text.startup,"ax",@progbits
	.type	_GLOBAL__sub_I_seananners_dloot.hip,@function # -- Begin function _GLOBAL__sub_I_seananners_dloot.hip
_GLOBAL__sub_I_seananners_dloot.hip:    # @_GLOBAL__sub_I_seananners_dloot.hip
	.cfi_startproc
# %bb.0:
	xorps	%xmm0, %xmm0
	movups	%xmm0, structureSeeds(%rip)
	movq	$0, structureSeeds+16(%rip)
	movl	$_ZNSt6vectorIlSaIlEED2Ev, %edi
	movl	$structureSeeds, %esi
	movl	$__dso_handle, %edx
	jmp	__cxa_atexit                    # TAILCALL
.Lfunc_end3:
	.size	_GLOBAL__sub_I_seananners_dloot.hip, .Lfunc_end3-_GLOBAL__sub_I_seananners_dloot.hip
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	subq	$32, %rsp
	.cfi_adjust_cfa_offset 32
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL10threadWorklPjPl, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$stonks, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$48, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$_ZL6Chest1, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movl	$216, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$_ZL6Chest2, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movl	$216, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$__hip_module_dtor, %edi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	stonks,@object                  # @stonks
	.local	stonks
	.comm	stonks,48,16
	.type	buffer,@object                  # @buffer
	.bss
	.globl	buffer
	.p2align	3, 0x0
buffer:
	.quad	0
	.size	buffer, 8

	.type	counter,@object                 # @counter
	.globl	counter
	.p2align	3, 0x0
counter:
	.quad	0
	.size	counter, 8

	.type	structureSeeds,@object          # @structureSeeds
	.globl	structureSeeds
	.p2align	3, 0x0
structureSeeds:
	.zero	24
	.size	structureSeeds, 24

	.hidden	__dso_handle
	.type	structSeedsArr,@object          # @structSeedsArr
	.globl	structSeedsArr
	.p2align	3, 0x0
structSeedsArr:
	.quad	0
	.size	structSeedsArr, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"seananners-dloot.txt"
	.size	.L.str, 21

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"w+"
	.size	.L.str.1, 3

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/BoySanic/seananners/master/seananners_dloot.hip"
	.size	.L.str.2, 110

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"%d, %d index: %d\n"
	.size	.L.str.3, 18

	.type	_ZL6Chest1,@object              # @_ZL6Chest1
	.section	.rodata,"a",@progbits
	.p2align	4, 0x0
_ZL6Chest1:
	.zero	216
	.size	_ZL6Chest1, 216

	.type	_ZL6Chest2,@object              # @_ZL6Chest2
	.p2align	4, 0x0
_ZL6Chest2:
	.zero	216
	.size	_ZL6Chest2, 216

	.type	_ZL10threadWorklPjPl,@object    # @_ZL10threadWorklPjPl
	.p2align	3, 0x0
_ZL10threadWorklPjPl:
	.quad	_ZL25__device_stub__threadWorklPjPl
	.size	_ZL10threadWorklPjPl, 8

	.type	.L.str.4,@object                # @.str.4
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.4:
	.asciz	"%lld\n"
	.size	.L.str.4, 6

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Seeds Per Second: %f\tProgress: %f\n"
	.size	.L.str.5, 35

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Time taken: %lld\nSeeds per second: %15.9f"
	.size	.L.str.6, 42

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"GPUassert: %s (code %d) %s %d\n"
	.size	.L.str.7, 31

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_ZL10threadWorklPjPl"
	.size	.L__unnamed_1, 21

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"stonks"
	.size	.L__unnamed_2, 7

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_ZL6Chest1"
	.size	.L__unnamed_3, 11

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_ZL6Chest2"
	.size	.L__unnamed_4, 11

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	_GLOBAL__sub_I_seananners_dloot.hip
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _ZL25__device_stub__threadWorklPjPl
	.addrsig_sym __gxx_personality_v0
	.addrsig_sym _GLOBAL__sub_I_seananners_dloot.hip
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym stonks
	.addrsig_sym buffer
	.addrsig_sym counter
	.addrsig_sym structureSeeds
	.addrsig_sym __dso_handle
	.addrsig_sym _ZL6Chest1
	.addrsig_sym _ZL6Chest2
	.addrsig_sym _ZL10threadWorklPjPl
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.p2align	2                               ; -- Begin function _ZL8testSeedl
	.type	_ZL8testSeedl,@function
_ZL8testSeedl:                          ; @_ZL8testSeedl
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v10, 0
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr4
.LBB0_1:                                ; %.preheader107
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_2 Depth 2
                                        ;       Child Loop BB0_3 Depth 3
                                        ;       Child Loop BB0_5 Depth 3
                                        ;       Child Loop BB0_9 Depth 3
                                        ;         Child Loop BB0_10 Depth 4
                                        ;         Child Loop BB0_17 Depth 4
                                        ;         Child Loop BB0_27 Depth 4
                                        ;         Child Loop BB0_57 Depth 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, s0, -1
	s_mov_b32 s4, 0
.LBB0_2:                                ; %.preheader106
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_3 Depth 3
                                        ;       Child Loop BB0_5 Depth 3
                                        ;       Child Loop BB0_9 Depth 3
                                        ;         Child Loop BB0_10 Depth 4
                                        ;         Child Loop BB0_17 Depth 4
                                        ;         Child Loop BB0_27 Depth 4
                                        ;         Child Loop BB0_57 Depth 4
	s_mov_b32 s0, 0
.LBB0_3:                                ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v1
	v_lshl_add_u32 v0, v0, 2, v0
	v_add3_u32 v0, v1, v7, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, 0xffff, v0
	v_alignbit_b32 v0, v7, v6, 17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v1, 0x92492493, v0
	v_lshrrev_b32_e32 v1, 2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, v1, 7
	v_sub_nc_u32_e32 v3, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v3, v0
	v_add_nc_u32_e32 v0, -7, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, 0, v0
	v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_3
; %bb.4:                                ; %_ZL7nextIntPli.exit.preheader
                                        ;   in Loop: Header=BB0_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s0, 0
.LBB0_5:                                ; %_ZL7nextIntPli.exit
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v6, 11
	v_mul_lo_u32 v7, 0xdeece66d, v7
	v_lshl_add_u32 v6, v6, 2, v6
	v_add3_u32 v1, v7, v1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v1, 0xffff, v1
	v_alignbit_b32 v6, v1, v0, 17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v7, 0x66666667, v6
	v_lshrrev_b32_e32 v7, 1, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v7, v7, 2, v7
	v_sub_nc_u32_e32 v8, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, v8, v6
	v_add_nc_u32_e32 v6, -5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, 0, v6
	v_dual_mov_b32 v7, v1 :: v_dual_mov_b32 v6, v0
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_5
; %bb.6:                                ; %_ZL7nextIntPli.exit75
                                        ;   in Loop: Header=BB0_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_eq_u32_e32 vcc_lo, 4, v3
	v_cmp_eq_u32_e64 s0, 4, v8
	v_cmp_eq_u32_e64 s1, 6, v3
	v_cmp_eq_u32_e64 s2, 2, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s5, vcc_lo, s0
	v_cndmask_b32_e64 v3, 0, 1, s5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_and_b32 s2, s1, s2
	s_mov_b32 s1, exec_lo
	v_cndmask_b32_e64 v11, v3, 2, s2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e64 v11, v10
	s_cbranch_execz .LBB0_72
; %bb.7:                                ;   in Loop: Header=BB0_2 Depth=2
	s_or_b32 s0, s2, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_71
; %bb.8:                                ; %.preheader105.preheader
                                        ;   in Loop: Header=BB0_2 Depth=2
	s_mov_b32 s7, 0
.LBB0_9:                                ; %.preheader105
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_2 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_10 Depth 4
                                        ;         Child Loop BB0_17 Depth 4
                                        ;         Child Loop BB0_27 Depth 4
                                        ;         Child Loop BB0_57 Depth 4
	s_mov_b32 s0, 0
.LBB0_10:                               ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_2 Depth=2
                                        ;       Parent Loop BB0_9 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v1
	v_lshl_add_u32 v0, v0, 2, v0
	v_add3_u32 v13, v1, v7, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, 0xffff, v13
	v_alignbit_b32 v0, v7, v6, 17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v1, 0x2e8ba2e9, v0
	v_lshrrev_b32_e32 v1, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, v1, 11
	v_sub_nc_u32_e32 v12, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v12, v0
	v_add_nc_u32_e32 v0, -11, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, 0, v0
	v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_10
; %bb.11:                               ; %_ZL7nextIntPli.exit.i
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
                                        ; implicit-def: $vgpr0_vgpr1
	v_cmpx_lt_i32_e32 4, v12
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_37
; %bb.12:                               ; %NodeBlock255
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_mov_b32 s8, exec_lo
                                        ; implicit-def: $vgpr0_vgpr1
	v_cmpx_lt_i32_e32 6, v12
	s_xor_b32 s8, exec_lo, s8
	s_cbranch_execz .LBB0_30
; %bb.13:                               ; %NodeBlock253
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_mov_b32 s9, exec_lo
                                        ; implicit-def: $vgpr0_vgpr1
	v_cmpx_lt_i32_e32 7, v12
	s_xor_b32 s9, exec_lo, s9
	s_cbranch_execz .LBB0_25
; %bb.14:                               ; %NodeBlock251
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_mov_b32 s10, exec_lo
                                        ; implicit-def: $vgpr0_vgpr1
	v_cmpx_lt_i32_e32 8, v12
	s_xor_b32 s10, exec_lo, s10
	s_cbranch_execz .LBB0_20
; %bb.15:                               ; %LeafBlock
                                        ;   in Loop: Header=BB0_9 Depth=3
	v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
	s_mov_b32 s11, exec_lo
	v_cmpx_eq_u32_e32 9, v12
	s_cbranch_execz .LBB0_19
; %bb.16:                               ; %.preheader104.preheader
                                        ;   in Loop: Header=BB0_9 Depth=3
	v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
	s_mov_b32 s12, 0
.LBB0_17:                               ; %.preheader104
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_2 Depth=2
                                        ;       Parent Loop BB0_9 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v8, 11
	v_mul_lo_u32 v3, 0xdeece66d, v9
	v_lshl_add_u32 v8, v8, 2, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v3, v1, v8
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v8, v1, v0, 17
	v_mul_hi_u32 v3, 0x66666667, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v3, 2, v3
	v_mul_lo_u32 v3, v3, 10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v8, v3
	v_sub_nc_u32_e32 v8, v3, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v8, -10, v8
	v_cmp_gt_i32_e32 vcc_lo, 0, v8
	v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_17
; %bb.18:                               ; %_ZL7nextIntPli.exit43.i
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_or_b32 exec_lo, exec_lo, s12
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e64 v5, v5, 1, vcc_lo
	v_cndmask_b32_e64 v4, v4, 5, vcc_lo
.LBB0_19:                               ; %Flow270
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_or_b32 exec_lo, exec_lo, s11
.LBB0_20:                               ; %Flow272
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_and_not1_saveexec_b32 s10, s10
	s_cbranch_execz .LBB0_24
; %bb.21:                               ;   in Loop: Header=BB0_9 Depth=3
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v6, 11
	v_mul_lo_u32 v3, 0xdeece66d, v7
	v_lshl_add_u32 v8, v6, 2, v6
	s_mov_b32 s11, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v3, v1, v8
	v_and_b32_e32 v3, 0x8000, v8
	v_and_b32_e32 v1, 0xffff, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_eq_u64_e32 0, v[2:3]
; %bb.22:                               ;   in Loop: Header=BB0_9 Depth=3
	v_mad_u64_u32 v[14:15], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v8
	v_lshl_add_u32 v0, v0, 2, v0
	v_mov_b32_e32 v4, 10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v1, v15, v0
	v_bfe_u32 v1, v0, 14, 2
	v_and_b32_e32 v15, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v0, v14 :: v_dual_add_nc_u32 v5, 1, v1
	v_mov_b32_e32 v1, v15
; %bb.23:                               ; %Flow271
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_or_b32 exec_lo, exec_lo, s11
.LBB0_24:                               ; %Flow273
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_25:                               ; %Flow274
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_and_not1_saveexec_b32 s9, s9
	s_cbranch_execz .LBB0_29
; %bb.26:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_9 Depth=3
	v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
	s_mov_b32 s10, 0
.LBB0_27:                               ; %.preheader.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_2 Depth=2
                                        ;       Parent Loop BB0_9 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v8, 11
	v_mul_lo_u32 v3, 0xdeece66d, v9
	v_lshl_add_u32 v8, v8, 2, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v3, v1, v8
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v8, v1, v0, 17
	v_mul_hi_u32 v3, 0x51eb851f, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v3, 5, v3
	v_mul_lo_u32 v3, 0x64, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v8, v3
	v_sub_nc_u32_e32 v8, v3, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v8, 0xffffff9c, v8
	v_cmp_gt_i32_e32 vcc_lo, 0, v8
	v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_27
; %bb.28:                               ; %_ZL7nextIntPli.exit41.i
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_or_b32 exec_lo, exec_lo, s10
	v_cmp_ne_u32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e32 v4, 4, v4, vcc_lo
.LBB0_29:                               ; %Flow275
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_30:                               ; %Flow278
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_and_not1_saveexec_b32 s8, s8
	s_cbranch_execz .LBB0_36
; %bb.31:                               ; %NodeBlock249
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_mov_b32 s9, exec_lo
                                        ; implicit-def: $sgpr11
                                        ; implicit-def: $sgpr10
	v_cmpx_lt_i32_e32 5, v12
	s_xor_b32 s9, exec_lo, s9
; %bb.32:                               ;   in Loop: Header=BB0_9 Depth=3
	s_mov_b32 s10, 1
	s_mov_b32 s11, 3
; %bb.33:                               ; %Flow276
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_or_saveexec_b32 s9, s9
	v_dual_mov_b32 v4, s11 :: v_dual_mov_b32 v5, s10
	v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
	s_xor_b32 exec_lo, exec_lo, s9
; %bb.34:                               ;   in Loop: Header=BB0_9 Depth=3
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v6, 11
	v_mul_lo_u32 v3, 0xdeece66d, v13
	v_lshl_add_u32 v4, v6, 2, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v1, v3, v1, v4
	v_mov_b32_e32 v4, 8
	v_bfe_u32 v3, v1, 14, 2
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v5, 1, v3
; %bb.35:                               ; %Flow277
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_36:                               ; %Flow279
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s8
.LBB0_37:                               ; %Flow288
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_55
; %bb.38:                               ; %NodeBlock247
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_mov_b32 s8, exec_lo
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr0_vgpr1
	v_cmpx_lt_i32_e32 1, v12
	s_xor_b32 s8, exec_lo, s8
	s_cbranch_execz .LBB0_48
; %bb.39:                               ; %NodeBlock245
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_mov_b32 s9, exec_lo
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr0_vgpr1
	v_cmpx_lt_i32_e32 2, v12
	s_xor_b32 s9, exec_lo, s9
	s_cbranch_execz .LBB0_45
; %bb.40:                               ; %NodeBlock243
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_mov_b32 s10, exec_lo
                                        ; implicit-def: $sgpr11
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr0_vgpr1
	v_cmpx_lt_i32_e32 3, v12
	s_xor_b32 s10, exec_lo, s10
; %bb.41:                               ;   in Loop: Header=BB0_9 Depth=3
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v6, 11
	v_mul_lo_u32 v3, 0xdeece66d, v13
	v_lshl_add_u32 v4, v6, 2, v6
	s_mov_b32 s11, 7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v3, v1, v4
	v_bfe_u32 v3, v1, 14, 2
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v5, 1, v3
; %bb.42:                               ; %Flow280
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_or_saveexec_b32 s10, s10
	v_mov_b32_e32 v4, s11
	s_xor_b32 exec_lo, exec_lo, s10
; %bb.43:                               ;   in Loop: Header=BB0_9 Depth=3
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v6, 11
	v_mul_lo_u32 v3, 0xdeece66d, v13
	v_lshl_add_u32 v4, v6, 2, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v1, v3, v1, v4
	v_mov_b32_e32 v4, 6
	v_bfe_u32 v3, v1, 14, 2
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v5, 1, v3
; %bb.44:                               ; %Flow281
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_45:                               ; %Flow282
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_and_not1_saveexec_b32 s9, s9
; %bb.46:                               ;   in Loop: Header=BB0_9 Depth=3
	v_dual_mov_b32 v4, 2 :: v_dual_mov_b32 v5, 1
	v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
; %bb.47:                               ; %Flow283
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_48:                               ; %Flow286
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_and_not1_saveexec_b32 s8, s8
	s_cbranch_execz .LBB0_54
; %bb.49:                               ; %NodeBlock
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_mov_b32 s9, exec_lo
                                        ; implicit-def: $sgpr10
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr0_vgpr1
	v_cmpx_lt_i32_e32 0, v12
	s_xor_b32 s9, exec_lo, s9
; %bb.50:                               ;   in Loop: Header=BB0_9 Depth=3
	v_mad_u64_u32 v[0:1], null, 0xdeece66d, v6, 11
	v_mul_lo_u32 v3, 0xdeece66d, v13
	v_lshl_add_u32 v4, v6, 2, v6
	s_mov_b32 s10, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v3, v1, v4
	v_bfe_u32 v3, v1, 14, 2
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v5, 1, v3
; %bb.51:                               ; %Flow284
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_or_saveexec_b32 s9, s9
	v_mov_b32_e32 v4, s10
	s_xor_b32 exec_lo, exec_lo, s9
; %bb.52:                               ;   in Loop: Header=BB0_9 Depth=3
	v_dual_mov_b32 v4, 1 :: v_dual_mov_b32 v5, 1
	v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
; %bb.53:                               ; %Flow285
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_54:                               ; %Flow287
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s8
.LBB0_55:                               ; %_ZL7getItemP9ItemStackPl.exit
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_lt_u32_e32 vcc_lo, 9, v12
	s_mov_b32 s8, exec_lo
	v_cndmask_b32_e64 v5, v5, 1, vcc_lo
	v_cndmask_b32_e64 v4, v4, 0, vcc_lo
	v_cmpx_ne_u32_e32 0, v4
	s_cbranch_execz .LBB0_70
; %bb.56:                               ; %.preheader103.preheader
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_mov_b32 s0, 0
.LBB0_57:                               ; %.preheader103
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_2 Depth=2
                                        ;       Parent Loop BB0_9 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, 0xdeece66d, v0, 11
	v_mul_lo_u32 v1, 0xdeece66d, v1
	v_lshl_add_u32 v0, v0, 2, v0
	v_add3_u32 v0, v1, v7, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, 0xffff, v0
	v_alignbit_b32 v0, v7, v6, 17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v1, 0x4ec4ec4f, v0
	v_lshrrev_b32_e32 v1, 3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, v1, 26
	v_sub_nc_u32_e32 v8, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v8, v0
	v_subrev_nc_u32_e32 v0, 26, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, 0, v0
	v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_57
; %bb.58:                               ; %_ZL7nextIntPli.exit78
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v9, v2
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, _ZL6Chest1@rel32@lo+4
	s_addc_u32 s11, s11, _ZL6Chest1@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[8:9]
	v_add_co_u32 v12, vcc_lo, v0, s10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v13, vcc_lo, s11, v1, vcc_lo
	global_load_b32 v3, v[12:13], off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 0, v3
	s_and_b32 s0, s5, vcc_lo
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_63
; %bb.59:                               ;   in Loop: Header=BB0_9 Depth=3
	v_lshl_add_u32 v3, v8, 3, s32
	v_cmp_gt_i32_e64 s0, 6, v4
	scratch_load_b32 v9, v3, off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, v9, v4
	s_or_b32 s0, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s10, s0
	s_xor_b32 s0, exec_lo, s10
	s_cbranch_execz .LBB0_61
; %bb.60:                               ;   in Loop: Header=BB0_9 Depth=3
	scratch_store_b64 v3, v[4:5], off
                                        ; implicit-def: $vgpr3
.LBB0_61:                               ; %Flow267
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_63
; %bb.62:                               ;   in Loop: Header=BB0_9 Depth=3
	scratch_load_b32 v9, v3, off offset:4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v9, v9, v5
	scratch_store_b32 v3, v9, off offset:4
.LBB0_63:                               ;   in Loop: Header=BB0_9 Depth=3
	s_or_b32 exec_lo, exec_lo, s9
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, _ZL6Chest2@rel32@lo+4
	s_addc_u32 s11, s11, _ZL6Chest2@rel32@hi+12
	v_add_co_u32 v0, vcc_lo, v0, s10
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
	s_and_b32 s0, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_69
; %bb.64:                               ;   in Loop: Header=BB0_9 Depth=3
	s_add_i32 s0, s32, 0xe0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_lshl_add_u32 v0, v8, 3, s0
	v_cmp_gt_i32_e64 s0, 6, v4
	scratch_load_b32 v1, v0, off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, v1, v4
	s_or_b32 s0, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s10, s0
	s_xor_b32 s0, exec_lo, s10
	s_cbranch_execz .LBB0_66
; %bb.65:                               ;   in Loop: Header=BB0_9 Depth=3
	scratch_store_b64 v0, v[4:5], off
                                        ; implicit-def: $vgpr0
.LBB0_66:                               ; %Flow264
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_68
; %bb.67:                               ;   in Loop: Header=BB0_9 Depth=3
	scratch_load_b32 v1, v0, off offset:4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v1, v1, v5
	scratch_store_b32 v0, v1, off offset:4
.LBB0_68:                               ; %Flow265
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_69:                               ; %Flow266
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
.LBB0_70:                               ; %Flow269
                                        ;   in Loop: Header=BB0_9 Depth=3
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s7, s7, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s7, 9
	s_cbranch_scc1 .LBB0_9
.LBB0_71:                               ; %Flow290
                                        ;   in Loop: Header=BB0_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s6
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	v_cndmask_b32_e32 v10, v10, v11, vcc_lo
.LBB0_72:                               ; %Flow291
                                        ;   in Loop: Header=BB0_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_add_i32 s4, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s4, 3
	s_cbranch_scc0 .LBB0_2
; %bb.73:                               ;   in Loop: Header=BB0_1 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_mov_b32 s0, 0
	s_cbranch_vccnz .LBB0_1
; %bb.74:                               ; %.preheader.preheader
	scratch_load_b32 v0, off, s32
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_87
; %bb.75:                               ; %.lr.ph.preheader
	s_add_i32 s0, s32, 0xe0
	v_or_b32_e64 v0, 4, s32
	v_or_b32_e64 v1, 4, s0
	s_mov_b32 s6, 0
	s_mov_b32 s5, 0
	s_mov_b32 s8, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _ZL6Chest2@rel32@lo+8
	s_addc_u32 s1, s1, _ZL6Chest2@rel32@hi+16
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, _ZL6Chest1@rel32@lo+12
	s_addc_u32 s3, s3, _ZL6Chest1@rel32@hi+20
                                        ; implicit-def: $sgpr7
                                        ; implicit-def: $sgpr9
                                        ; implicit-def: $sgpr10
.LBB0_76:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	scratch_load_b32 v2, v0, off
	s_add_u32 s12, s2, -4
	s_addc_u32 s13, s3, -1
	s_and_not1_b32 s10, s10, exec_lo
	s_load_b32 s11, s[12:13], 0x0
	s_or_b32 s9, s9, exec_lo
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, s11, v2
	s_and_b32 s11, s6, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s10, s10, s11
	s_and_saveexec_b32 s11, vcc_lo
	s_cbranch_execz .LBB0_85
; %bb.77:                               ;   in Loop: Header=BB0_76 Depth=1
	scratch_load_b32 v2, v1, off offset:-4
	s_add_u32 s12, s0, -4
	s_addc_u32 s13, s1, -1
	s_mov_b32 s14, -1
	s_load_b32 s12, s[12:13], 0x0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, s12, v2
                                        ; implicit-def: $sgpr12
	s_and_saveexec_b32 s13, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s13, exec_lo, s13
	s_cbranch_execz .LBB0_84
; %bb.78:                               ;   in Loop: Header=BB0_76 Depth=1
	scratch_load_b32 v2, v1, off
	s_load_b32 s12, s[0:1], 0x0
	s_mov_b32 s15, -1
	s_mov_b32 s16, s6
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, s12, v2
                                        ; implicit-def: $sgpr12
	s_and_saveexec_b32 s14, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s14, exec_lo, s14
	s_cbranch_execz .LBB0_83
; %bb.79:                               ;   in Loop: Header=BB0_76 Depth=1
	s_cmp_gt_u32 s8, 25
	s_cselect_b32 s12, -1, 0
	s_cmp_lg_u32 s8, 26
	s_cbranch_scc0 .LBB0_81
; %bb.80:                               ; %.preheader
                                        ;   in Loop: Header=BB0_76 Depth=1
	v_add_nc_u32_e32 v2, 4, v0
	s_load_b32 s15, s[2:3], 0x0
	s_add_u32 s0, s0, 8
	v_add_nc_u32_e32 v0, 8, v0
	v_add_nc_u32_e32 v1, 8, v1
	scratch_load_b32 v2, v2, off
	s_addc_u32 s1, s1, 0
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
	s_add_i32 s8, s8, 1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, s15, v2
	s_or_not1_b32 s15, vcc_lo, exec_lo
	s_branch .LBB0_82
.LBB0_81:                               ;   in Loop: Header=BB0_76 Depth=1
                                        ; implicit-def: $sgpr8
                                        ; implicit-def: $sgpr0_sgpr1
                                        ; implicit-def: $sgpr2_sgpr3
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr1
.LBB0_82:                               ; %Flow261
                                        ;   in Loop: Header=BB0_76 Depth=1
	s_and_not1_b32 s16, s6, exec_lo
	s_and_b32 s17, s12, exec_lo
	s_or_not1_b32 s15, s15, exec_lo
	s_or_b32 s16, s16, s17
.LBB0_83:                               ; %Flow260
                                        ;   in Loop: Header=BB0_76 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s6, s6, exec_lo
	s_and_b32 s14, s16, exec_lo
	s_or_b32 s6, s6, s14
	s_or_not1_b32 s14, s15, exec_lo
.LBB0_84:                               ; %Flow259
                                        ;   in Loop: Header=BB0_76 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s10, s10, exec_lo
	s_and_b32 s6, s6, exec_lo
	s_and_not1_b32 s9, s9, exec_lo
	s_and_b32 s13, s14, exec_lo
	s_or_b32 s10, s10, s6
	s_or_b32 s9, s9, s13
	s_mov_b32 s6, s12
.LBB0_85:                               ; %Flow
                                        ;   in Loop: Header=BB0_76 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s11, exec_lo, s9
	s_or_b32 s5, s11, s5
	s_and_not1_b32 s7, s7, exec_lo
	s_and_b32 s11, s10, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s7, s7, s11
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_76
; %bb.86:                               ; %Flow262
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s0, s7, exec_lo
.LBB0_87:                               ; %Flow263
	s_or_b32 exec_lo, exec_lo, s4
	v_cndmask_b32_e64 v0, 0, 1, s0
	s_setpc_b64 s[30:31]
.Lfunc_end0:
	.size	_ZL8testSeedl, .Lfunc_end0-_ZL8testSeedl
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 2808
; NumSgprs: 35
; NumVgprs: 16
; ScratchSize: 448
; MemoryBound: 0
	.section	.text._ZL10threadWorklPjPl,"axG",@progbits,_ZL10threadWorklPjPl,comdat
	.globl	_ZL10threadWorklPjPl            ; -- Begin function _ZL10threadWorklPjPl
	.p2align	8
	.type	_ZL10threadWorklPjPl,@function
_ZL10threadWorklPjPl:                   ; @_ZL10threadWorklPjPl
; %bb.0:
	s_mov_b64 s[18:19], s[0:1]
	s_load_b32 s0, s[0:1], 0x24
	s_load_b128 s[20:23], s[18:19], 0x0
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
	v_add_co_u32 v16, s0, v1, s20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v17, null, 0, s21, s0
	s_mov_b32 s0, 0x73c4cd04
	v_xor_b32_e32 v2, 0xdeece66d, v16
	s_movk_i32 s1, 0x2d38
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v0, 5, v17
	v_mul_lo_u32 v3, 0x32eb, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, 0x772c5f11, v0
	v_mad_u64_u32 v[0:1], null, 0x772c5f11, v2, s[0:1]
	v_add3_u32 v1, v4, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[2:3], null, 0xdeece66d, v0, 11
	v_lshl_add_u32 v0, v0, 2, v0
	v_mul_lo_u32 v4, 0xdeece66d, v1
	v_and_b32_e32 v1, 0x8000, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e64 s0, 0, v1
	v_add3_u32 v0, v4, v3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v4, 0x8000, v0
	v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, vcc_lo
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_5
; %bb.1:
	s_mov_b32 s0, 0xd8f3c9e9
	s_movk_i32 s1, 0xd75
	v_mul_lo_u32 v3, 0x89a3, v2
	v_mul_lo_u32 v4, 0x6e758065, v0
	v_mad_u64_u32 v[0:1], null, 0x6e758065, v2, s[0:1]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _ZL8testSeedl@rel32@lo+4
	s_addc_u32 s1, s1, _ZL8testSeedl@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v4, v1, v3
	v_and_b32_e32 v1, 0xffff, v1
	s_swappc_b64 s[30:31], s[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v0, 1, v0
	v_cmp_eq_u32_e32 vcc_lo, 1, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_5
; %bb.2:
	s_load_b64 s[0:1], s[18:19], 0x10
	s_mov_b32 s3, exec_lo
	s_mov_b32 s2, exec_lo
	v_mbcnt_lo_u32_b32 v0, s3, 0
                                        ; implicit-def: $vgpr1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_4
; %bb.3:
	s_bcnt1_i32_b32 s3, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s3
	global_atomic_add_u32 v1, v1, v2, s[22:23] glc
.LBB1_4:
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s2, v0
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[16:17], off
.LBB1_5:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL10threadWorklPjPl
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 448
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 33
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL10threadWorklPjPl,"axG",@progbits,_ZL10threadWorklPjPl,comdat
.Lfunc_end1:
	.size	_ZL10threadWorklPjPl, .Lfunc_end1-_ZL10threadWorklPjPl
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 480
; NumSgprs: 35
; NumVgprs: 18
; ScratchSize: 448
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 35
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2align	2                               ; -- Begin function __ockl_printf_append_string_n
	.type	__ockl_printf_append_string_n,@function
__ockl_printf_append_string_n:          ; @__ockl_printf_append_string_n
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, 0, v[2:3]
	v_mov_b32_e32 v10, v0
	s_and_b32 s0, vcc_lo, exec_lo
	s_cbranch_scc0 .LBB2_89
; %bb.1:
	s_load_b64 s[2:3], s[8:9], 0x50
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_mov_b32 v13, 2 :: v_dual_and_b32 v0, -3, v10
	v_dual_mov_b32 v14, 1 :: v_dual_mov_b32 v7, v1
	v_dual_mov_b32 v32, 0 :: v_dual_and_b32 v35, 2, v10
	v_mbcnt_lo_u32_b32 v36, -1, 0
	v_mov_b32_e32 v6, v0
	s_mov_b32 s10, 0
.LBB2_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_5 Depth 2
                                        ;     Child Loop BB2_15 Depth 2
                                        ;     Child Loop BB2_24 Depth 2
                                        ;     Child Loop BB2_33 Depth 2
                                        ;     Child Loop BB2_42 Depth 2
                                        ;     Child Loop BB2_51 Depth 2
                                        ;     Child Loop BB2_60 Depth 2
                                        ;     Child Loop BB2_67 Depth 2
                                        ;     Child Loop BB2_72 Depth 2
                                        ;     Child Loop BB2_78 Depth 2
                                        ;     Child Loop BB2_86 Depth 2
	v_cmp_gt_u64_e32 vcc_lo, 56, v[4:5]
	v_dual_cndmask_b32 v34, 0, v5 :: v_dual_cndmask_b32 v33, 56, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_u32_e32 vcc_lo, 7, v33
	s_cbranch_vccnz .LBB2_6
; %bb.3:                                ;   in Loop: Header=BB2_2 Depth=1
	v_cmp_eq_u32_e32 vcc_lo, 0, v33
	s_cbranch_vccnz .LBB2_7
; %bb.4:                                ; %.preheader31.preheader
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v8, 0
	v_lshlrev_b64 v[11:12], 3, v[33:34]
	v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v16, v3
	v_mov_b32_e32 v15, v2
	s_mov_b64 s[4:5], 0
.LBB2_5:                                ; %.preheader31
                                        ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	flat_load_u8 v0, v[15:16]
	v_mov_b32_e32 v18, s10
	v_add_co_u32 v15, vcc_lo, v15, 1
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v16, vcc_lo
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_and_b32_e32 v17, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[17:18], s4, v[17:18]
	s_add_u32 s4, s4, 8
	s_addc_u32 s5, s5, 0
	v_cmp_ne_u32_e64 s0, s4, v11
	v_or_b32_e32 v9, v18, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_or_b32_e32 v8, v17, v8
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB2_5
	s_branch .LBB2_8
.LBB2_6:                                ;   in Loop: Header=BB2_2 Depth=1
	s_mov_b32 s1, -1
                                        ; implicit-def: $sgpr0
	s_branch .LBB2_9
.LBB2_7:                                ;   in Loop: Header=BB2_2 Depth=1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
.LBB2_8:                                ; %Flow174
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_mov_b32 s1, 0
	s_mov_b32 s0, 0
.LBB2_9:                                ; %Flow176
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_11
; %bb.10:                               ;   in Loop: Header=BB2_2 Depth=1
	flat_load_u8 v0, v[2:3]
	s_waitcnt vmcnt(1)
	s_clause 0x4
	flat_load_u8 v8, v[2:3] offset:1
	flat_load_u8 v9, v[2:3] offset:2
	flat_load_u8 v11, v[2:3] offset:3
	flat_load_u8 v12, v[2:3] offset:5
	flat_load_u8 v15, v[2:3] offset:4
	v_mov_b32_e32 v16, v32
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_and_b32_e32 v0, 0xffff, v0
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v8, 8, v8
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v9, 16, v9
	s_clause 0x1
	flat_load_u8 v17, v[2:3] offset:7
	flat_load_d16_hi_u8 v16, v[2:3] offset:6
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v11, 24, v11
	v_or_b32_e32 v0, v8, v0
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v8, 8, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v0, v0, v9, v11
	s_waitcnt vmcnt(2)
	v_or3_b32 v8, 0, v15, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_or3_b32 v11, v0, 0, 0
	v_add_nc_u32_e32 v0, -8, v33
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v9, 24, v17
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_or3_b32 v9, v8, v16, v9
	v_or3_b32 v8, v11, 0, 0
	v_add_co_u32 v11, vcc_lo, v2, 8
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v3, vcc_lo
	s_branch .LBB2_12
.LBB2_11:                               ;   in Loop: Header=BB2_2 Depth=1
	v_mov_b32_e32 v12, v3
	v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v11, v2
.LBB2_12:                               ; %.loopexit32
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_u32_e32 vcc_lo, 7, v0
	s_cbranch_vccnz .LBB2_17
; %bb.13:                               ;   in Loop: Header=BB2_2 Depth=1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_cbranch_vccnz .LBB2_16
; %bb.14:                               ; %.preheader29.preheader
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_mov_b64 s[0:1], 0
	s_mov_b64 s[4:5], 0
.LBB2_15:                               ; %.preheader29
                                        ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v17, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v18, vcc_lo, s5, v12, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_ne_u32_e32 vcc_lo, s4, v0
	flat_load_u8 v17, v[17:18]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v18, s10 :: v_dual_and_b32 v17, 0xffff, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[17:18], s0, v[17:18]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	v_or_b32_e32 v16, v18, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v15, v17, v15
	s_cbranch_vccnz .LBB2_15
.LBB2_16:                               ; %Flow169
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_mov_b32 s1, 0
	s_mov_b32 s0, 0
	s_branch .LBB2_18
.LBB2_17:                               ;   in Loop: Header=BB2_2 Depth=1
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr15_vgpr16
                                        ; implicit-def: $sgpr0
.LBB2_18:                               ; %Flow171
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_20
; %bb.19:                               ;   in Loop: Header=BB2_2 Depth=1
	s_clause 0x5
	flat_load_u8 v15, v[11:12]
	flat_load_u8 v16, v[11:12] offset:1
	flat_load_u8 v17, v[11:12] offset:2
	flat_load_u8 v18, v[11:12] offset:3
	flat_load_u8 v19, v[11:12] offset:5
	flat_load_u8 v20, v[11:12] offset:4
	v_dual_mov_b32 v21, v32 :: v_dual_add_nc_u32 v0, -8, v0
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_and_b32_e32 v15, 0xffff, v15
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v16, 8, v16
	s_clause 0x1
	flat_load_u8 v22, v[11:12] offset:7
	flat_load_d16_hi_u8 v21, v[11:12] offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v17, 16, v17
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v18, 24, v18
	v_add_co_u32 v11, vcc_lo, v11, 8
	v_or_b32_e32 v15, v16, v15
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v16, 8, v19
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v15, v15, v17, v18
	s_waitcnt vmcnt(2)
	v_or3_b32 v16, 0, v20, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v15, v15, 0, 0
	v_or3_b32 v15, v15, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v17, 24, v22
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v16, v16, v21, v17
	s_branch .LBB2_21
.LBB2_20:                               ;   in Loop: Header=BB2_2 Depth=1
	v_mov_b32_e32 v0, s0
.LBB2_21:                               ; %.loopexit30
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_u32_e32 vcc_lo, 7, v0
	s_cbranch_vccnz .LBB2_26
; %bb.22:                               ;   in Loop: Header=BB2_2 Depth=1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_cbranch_vccnz .LBB2_25
; %bb.23:                               ; %.preheader27.preheader
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_mov_b64 s[0:1], 0
	s_mov_b64 s[4:5], 0
.LBB2_24:                               ; %.preheader27
                                        ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v19, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v20, vcc_lo, s5, v12, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_ne_u32_e32 vcc_lo, s4, v0
	flat_load_u8 v19, v[19:20]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v20, s10 :: v_dual_and_b32 v19, 0xffff, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[19:20], s0, v[19:20]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	v_or_b32_e32 v18, v20, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v17, v19, v17
	s_cbranch_vccnz .LBB2_24
.LBB2_25:                               ; %Flow164
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_mov_b32 s1, 0
	s_mov_b32 s0, 0
	s_branch .LBB2_27
.LBB2_26:                               ;   in Loop: Header=BB2_2 Depth=1
	s_mov_b32 s1, -1
                                        ; implicit-def: $sgpr0
.LBB2_27:                               ; %Flow166
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_29
; %bb.28:                               ;   in Loop: Header=BB2_2 Depth=1
	s_clause 0x5
	flat_load_u8 v17, v[11:12]
	flat_load_u8 v18, v[11:12] offset:1
	flat_load_u8 v19, v[11:12] offset:2
	flat_load_u8 v20, v[11:12] offset:3
	flat_load_u8 v21, v[11:12] offset:5
	flat_load_u8 v22, v[11:12] offset:4
	v_dual_mov_b32 v23, v32 :: v_dual_add_nc_u32 v0, -8, v0
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_and_b32_e32 v17, 0xffff, v17
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v18, 8, v18
	s_clause 0x1
	flat_load_u8 v24, v[11:12] offset:7
	flat_load_d16_hi_u8 v23, v[11:12] offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v19, 16, v19
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v20, 24, v20
	v_add_co_u32 v11, vcc_lo, v11, 8
	v_or_b32_e32 v17, v18, v17
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v18, 8, v21
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v17, v17, v19, v20
	s_waitcnt vmcnt(2)
	v_or3_b32 v18, 0, v22, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v17, v17, 0, 0
	v_or3_b32 v17, v17, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v19, 24, v24
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v18, v18, v23, v19
	s_branch .LBB2_30
.LBB2_29:                               ;   in Loop: Header=BB2_2 Depth=1
	v_mov_b32_e32 v0, s0
.LBB2_30:                               ; %.loopexit28
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_u32_e32 vcc_lo, 7, v0
	s_cbranch_vccnz .LBB2_35
; %bb.31:                               ;   in Loop: Header=BB2_2 Depth=1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_cbranch_vccnz .LBB2_34
; %bb.32:                               ; %.preheader25.preheader
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_mov_b64 s[0:1], 0
	s_mov_b64 s[4:5], 0
.LBB2_33:                               ; %.preheader25
                                        ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v21, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v22, vcc_lo, s5, v12, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_ne_u32_e32 vcc_lo, s4, v0
	flat_load_u8 v21, v[21:22]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v22, s10 :: v_dual_and_b32 v21, 0xffff, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[21:22], s0, v[21:22]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	v_or_b32_e32 v20, v22, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v19, v21, v19
	s_cbranch_vccnz .LBB2_33
.LBB2_34:                               ; %Flow159
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_mov_b32 s1, 0
	s_mov_b32 s0, 0
	s_branch .LBB2_36
.LBB2_35:                               ;   in Loop: Header=BB2_2 Depth=1
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr19_vgpr20
                                        ; implicit-def: $sgpr0
.LBB2_36:                               ; %Flow161
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_38
; %bb.37:                               ;   in Loop: Header=BB2_2 Depth=1
	s_clause 0x5
	flat_load_u8 v19, v[11:12]
	flat_load_u8 v20, v[11:12] offset:1
	flat_load_u8 v21, v[11:12] offset:2
	flat_load_u8 v22, v[11:12] offset:3
	flat_load_u8 v23, v[11:12] offset:5
	flat_load_u8 v24, v[11:12] offset:4
	v_dual_mov_b32 v25, v32 :: v_dual_add_nc_u32 v0, -8, v0
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_and_b32_e32 v19, 0xffff, v19
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v20, 8, v20
	s_clause 0x1
	flat_load_u8 v26, v[11:12] offset:7
	flat_load_d16_hi_u8 v25, v[11:12] offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v21, 16, v21
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v22, 24, v22
	v_add_co_u32 v11, vcc_lo, v11, 8
	v_or_b32_e32 v19, v20, v19
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v20, 8, v23
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v19, v19, v21, v22
	s_waitcnt vmcnt(2)
	v_or3_b32 v20, 0, v24, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v19, v19, 0, 0
	v_or3_b32 v19, v19, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v21, 24, v26
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v20, v20, v25, v21
	s_branch .LBB2_39
.LBB2_38:                               ;   in Loop: Header=BB2_2 Depth=1
	v_mov_b32_e32 v0, s0
.LBB2_39:                               ; %.loopexit26
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_u32_e32 vcc_lo, 7, v0
	s_cbranch_vccnz .LBB2_44
; %bb.40:                               ;   in Loop: Header=BB2_2 Depth=1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_cbranch_vccnz .LBB2_43
; %bb.41:                               ; %.preheader23.preheader
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_mov_b64 s[0:1], 0
	s_mov_b64 s[4:5], 0
.LBB2_42:                               ; %.preheader23
                                        ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v23, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v24, vcc_lo, s5, v12, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_ne_u32_e32 vcc_lo, s4, v0
	flat_load_u8 v23, v[23:24]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v24, s10 :: v_dual_and_b32 v23, 0xffff, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[23:24], s0, v[23:24]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	v_or_b32_e32 v22, v24, v22
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v21, v23, v21
	s_cbranch_vccnz .LBB2_42
.LBB2_43:                               ; %Flow154
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_mov_b32 s1, 0
	s_mov_b32 s0, 0
	s_branch .LBB2_45
.LBB2_44:                               ;   in Loop: Header=BB2_2 Depth=1
	s_mov_b32 s1, -1
                                        ; implicit-def: $sgpr0
.LBB2_45:                               ; %Flow156
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_47
; %bb.46:                               ;   in Loop: Header=BB2_2 Depth=1
	s_clause 0x5
	flat_load_u8 v21, v[11:12]
	flat_load_u8 v22, v[11:12] offset:1
	flat_load_u8 v23, v[11:12] offset:2
	flat_load_u8 v24, v[11:12] offset:3
	flat_load_u8 v25, v[11:12] offset:5
	flat_load_u8 v26, v[11:12] offset:4
	v_dual_mov_b32 v27, v32 :: v_dual_add_nc_u32 v0, -8, v0
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_and_b32_e32 v21, 0xffff, v21
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v22, 8, v22
	s_clause 0x1
	flat_load_u8 v28, v[11:12] offset:7
	flat_load_d16_hi_u8 v27, v[11:12] offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v23, 16, v23
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v24, 24, v24
	v_add_co_u32 v11, vcc_lo, v11, 8
	v_or_b32_e32 v21, v22, v21
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v22, 8, v25
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v21, v21, v23, v24
	s_waitcnt vmcnt(2)
	v_or3_b32 v22, 0, v26, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v21, v21, 0, 0
	v_or3_b32 v21, v21, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v23, 24, v28
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v22, v22, v27, v23
	s_branch .LBB2_48
.LBB2_47:                               ;   in Loop: Header=BB2_2 Depth=1
	v_mov_b32_e32 v0, s0
.LBB2_48:                               ; %.loopexit24
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_u32_e32 vcc_lo, 7, v0
	s_cbranch_vccnz .LBB2_53
; %bb.49:                               ;   in Loop: Header=BB2_2 Depth=1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_cbranch_vccnz .LBB2_52
; %bb.50:                               ; %.preheader21.preheader
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_mov_b64 s[0:1], 0
	s_mov_b64 s[4:5], 0
.LBB2_51:                               ; %.preheader21
                                        ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v25, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v26, vcc_lo, s5, v12, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_ne_u32_e32 vcc_lo, s4, v0
	flat_load_u8 v25, v[25:26]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v26, s10 :: v_dual_and_b32 v25, 0xffff, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[25:26], s0, v[25:26]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	v_or_b32_e32 v24, v26, v24
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v23, v25, v23
	s_cbranch_vccnz .LBB2_51
.LBB2_52:                               ; %Flow149
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_mov_b32 s1, 0
	s_mov_b32 s0, 0
	s_branch .LBB2_54
.LBB2_53:                               ;   in Loop: Header=BB2_2 Depth=1
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr23_vgpr24
                                        ; implicit-def: $sgpr0
.LBB2_54:                               ; %Flow151
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_56
; %bb.55:                               ;   in Loop: Header=BB2_2 Depth=1
	s_clause 0x5
	flat_load_u8 v23, v[11:12]
	flat_load_u8 v24, v[11:12] offset:1
	flat_load_u8 v25, v[11:12] offset:2
	flat_load_u8 v26, v[11:12] offset:3
	flat_load_u8 v27, v[11:12] offset:5
	flat_load_u8 v28, v[11:12] offset:4
	v_dual_mov_b32 v29, v32 :: v_dual_add_nc_u32 v0, -8, v0
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_and_b32_e32 v23, 0xffff, v23
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v24, 8, v24
	s_clause 0x1
	flat_load_u8 v30, v[11:12] offset:7
	flat_load_d16_hi_u8 v29, v[11:12] offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v25, 16, v25
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v26, 24, v26
	v_add_co_u32 v11, vcc_lo, v11, 8
	v_or_b32_e32 v23, v24, v23
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v24, 8, v27
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v23, v23, v25, v26
	s_waitcnt vmcnt(2)
	v_or3_b32 v24, 0, v28, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v23, v23, 0, 0
	v_or3_b32 v23, v23, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v25, 24, v30
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v24, v24, v29, v25
	s_branch .LBB2_57
.LBB2_56:                               ;   in Loop: Header=BB2_2 Depth=1
	v_mov_b32_e32 v0, s0
.LBB2_57:                               ; %.loopexit22
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_u32_e32 vcc_lo, 7, v0
	s_cbranch_vccnz .LBB2_62
; %bb.58:                               ;   in Loop: Header=BB2_2 Depth=1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	v_mov_b32_e32 v25, 0
	v_mov_b32_e32 v26, 0
	s_cbranch_vccnz .LBB2_61
; %bb.59:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB2_2 Depth=1
	v_dual_mov_b32 v28, v12 :: v_dual_mov_b32 v27, v11
	s_mov_b64 s[0:1], 0
.LBB2_60:                               ; %.preheader
                                        ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	flat_load_u8 v29, v[27:28]
	v_mov_b32_e32 v30, s10
	v_add_nc_u32_e32 v0, -1, v0
	v_add_co_u32 v27, vcc_lo, v27, 1
	v_add_co_ci_u32_e32 v28, vcc_lo, 0, v28, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_and_b32_e32 v29, 0xffff, v29
	v_lshlrev_b64 v[29:30], s0, v[29:30]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v26, v30, v26
	v_or_b32_e32 v25, v29, v25
	s_cbranch_vccnz .LBB2_60
.LBB2_61:                               ; %Flow144
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_mov_b32 s0, 0
	s_branch .LBB2_63
.LBB2_62:                               ;   in Loop: Header=BB2_2 Depth=1
	s_mov_b32 s0, -1
.LBB2_63:                               ; %Flow146
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB2_65
; %bb.64:                               ;   in Loop: Header=BB2_2 Depth=1
	s_clause 0x5
	flat_load_u8 v0, v[11:12]
	flat_load_u8 v25, v[11:12] offset:1
	flat_load_u8 v26, v[11:12] offset:2
	flat_load_u8 v27, v[11:12] offset:3
	flat_load_u8 v28, v[11:12] offset:5
	flat_load_u8 v29, v[11:12] offset:4
	v_mov_b32_e32 v30, v32
	s_clause 0x1
	flat_load_u8 v31, v[11:12] offset:7
	flat_load_d16_hi_u8 v30, v[11:12] offset:6
	s_waitcnt vmcnt(7) lgkmcnt(0)
	v_and_b32_e32 v0, 0xffff, v0
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v11, 8, v25
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v12, 16, v26
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v25, 8, v28
	v_or_b32_e32 v0, v11, v0
	v_lshlrev_b32_e32 v11, 24, v27
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v0, v0, v12, v11
	s_waitcnt vmcnt(2)
	v_or3_b32 v11, 0, v29, v25
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v12, 24, v31
	v_or3_b32 v0, v0, 0, 0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or3_b32 v26, v11, v30, v12
	v_or3_b32 v25, v0, 0, 0
.LBB2_65:                               ; %.loopexit
                                        ;   in Loop: Header=BB2_2 Depth=1
	v_mov_b32_e32 v31, v36
	v_mov_b32_e32 v11, 0
	v_mov_b32_e32 v12, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v31
	v_cmp_ne_u32_e32 vcc_lo, s0, v31
	s_and_b32 s1, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB2_68
; %bb.66:                               ;   in Loop: Header=BB2_2 Depth=1
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[29:30], v32, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[11:12], v32, s[2:3] offset:40
	global_load_b64 v[27:28], v32, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v0, v12, v30
	v_and_b32_e32 v11, v11, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v0, v0, 24
	v_mul_hi_u32 v12, v11, 24
	v_mul_lo_u32 v11, v11, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, v12, v0
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v27, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, v28, v0, vcc_lo
	global_load_b64 v[27:28], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v32, v[27:30], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[29:30]
	s_and_b32 s1, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB2_68
.LBB2_67:                               ; %.preheader3.i.i19
                                        ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[27:28], v32, s[2:3] offset:40
	global_load_b64 v[37:38], v32, s[2:3]
	v_dual_mov_b32 v30, v12 :: v_dual_mov_b32 v29, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v28, v30
	v_and_b32_e32 v11, v27, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v0, v0, 24
	v_mul_hi_u32 v12, v11, 24
	v_mul_lo_u32 v11, v11, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, v12, v0
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v37, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, v38, v0, vcc_lo
	global_load_b64 v[27:28], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v32, v[27:30], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[29:30]
	v_cndmask_b32_e64 v0, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 1, v0
	s_and_b32 s1, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB2_67
.LBB2_68:                               ; %.loopexit4.i.i14
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[37:38], v32, s[2:3] offset:40
	global_load_b128 v[27:30], v32, s[2:3]
	v_cmp_eq_u32_e32 vcc_lo, s0, v31
	v_readfirstlane_b32 s4, v11
	v_readfirstlane_b32 s5, v12
	v_cndmask_b32_e64 v0, 0, 1, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cmp_ne_u32_e64 s0, 1, v0
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v37
	v_readfirstlane_b32 s7, v38
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s11, s6, 24
	s_mul_i32 s12, s6, 24
	s_cbranch_vccnz .LBB2_70
; %bb.69:                               ;   in Loop: Header=BB2_2 Depth=1
	s_add_i32 s13, s11, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v37, vcc_lo, v27, s12
	v_dual_mov_b32 v11, exec_lo :: v_dual_mov_b32 v12, v32
	v_add_co_ci_u32_e32 v38, vcc_lo, s13, v28, vcc_lo
	global_store_b128 v[37:38], v[11:14], off offset:8
.LBB2_70:                               ;   in Loop: Header=BB2_2 Depth=1
	v_cmp_lt_u64_e32 vcc_lo, 56, v[4:5]
	v_or_b32_e32 v0, v6, v35
	v_lshlrev_b32_e32 v11, 2, v33
	s_lshl_b64 s[6:7], s[6:7], 12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v0, v6, vcc_lo
	v_add_nc_u32_e32 v6, 28, v11
	v_lshlrev_b64 v[11:12], 6, v[31:32]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v29, vcc_lo, v29, s6
	v_add_co_ci_u32_e32 v30, vcc_lo, s7, v30, vcc_lo
	v_and_b32_e32 v6, 0x1e0, v6
	v_and_b32_e32 v0, 0xffffff1f, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v11, vcc_lo, v29, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, v30, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_or_b32_e32 v6, v0, v6
	s_and_b32 vcc_lo, exec_lo, s0
	s_clause 0x3
	global_store_b128 v[11:12], v[6:9], off
	global_store_b128 v[11:12], v[15:18], off offset:16
	global_store_b128 v[11:12], v[19:22], off offset:32
	global_store_b128 v[11:12], v[23:26], off offset:48
	s_cbranch_vccnz .LBB2_77
; %bb.71:                               ;   in Loop: Header=BB2_2 Depth=1
	s_clause 0x1
	global_load_b64 v[19:20], v32, s[2:3] offset:32 glc
	global_load_b64 v[6:7], v32, s[2:3] offset:40
	v_dual_mov_b32 v17, s4 :: v_dual_mov_b32 v18, s5
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v6
	v_readfirstlane_b32 s7, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[6:7], s[4:5]
	s_mul_i32 s7, s7, 24
	s_mul_hi_u32 s13, s6, 24
	s_mul_i32 s6, s6, 24
	s_add_i32 s13, s13, s7
	v_add_co_u32 v15, vcc_lo, v27, s6
	v_add_co_ci_u32_e32 v16, vcc_lo, s13, v28, vcc_lo
	global_store_b64 v[15:16], v[19:20], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v32, v[17:20], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[19:20]
	s_cbranch_vccnz .LBB2_73
.LBB2_72:                               ; %.preheader1.i.i17
                                        ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
	s_sleep 1
	global_store_b64 v[15:16], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v32, v[6:9], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
	v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
	v_cndmask_b32_e64 v0, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 1, v0
	s_and_b32 s6, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB2_72
.LBB2_73:                               ; %.loopexit2.i.i18
                                        ;   in Loop: Header=BB2_2 Depth=1
	global_load_b64 v[6:7], v32, s[2:3] offset:16
	v_mbcnt_lo_u32_b32 v0, exec_lo, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
	s_and_b32 s6, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB2_75
; %bb.74:                               ;   in Loop: Header=BB2_2 Depth=1
	s_bcnt1_i32_b32 s6, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v31, s6
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[6:7], v[31:32], off offset:8
.LBB2_75:                               ;   in Loop: Header=BB2_2 Depth=1
	s_waitcnt vmcnt(0)
	global_load_b64 v[8:9], v[6:7], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]
	s_cbranch_vccnz .LBB2_77
; %bb.76:                               ;   in Loop: Header=BB2_2 Depth=1
	global_load_b32 v31, v[6:7], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v31
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[8:9], v[31:32], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_77:                               ; %__ockl_hsa_signal_add.exit.i.i15
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_add_i32 s11, s11, s1
	v_add_co_u32 v0, vcc_lo, v27, s12
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v28, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
.LBB2_78:                               ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v0, 1
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB2_80
; %bb.79:                               ;   in Loop: Header=BB2_78 Depth=2
	global_load_b32 v0, v[6:7], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v0, 1, v0
.LBB2_80:                               ;   in Loop: Header=BB2_78 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v0
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB2_82
; %bb.81:                               ;   in Loop: Header=BB2_78 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB2_83
.LBB2_82:                               ;   in Loop: Header=BB2_78 Depth=2
	s_mov_b32 s1, -1
.LBB2_83:                               ; %Flow132
                                        ;   in Loop: Header=BB2_78 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_78
; %bb.84:                               ;   in Loop: Header=BB2_2 Depth=1
	global_load_b128 v[6:9], v[11:12], off
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB2_87
; %bb.85:                               ;   in Loop: Header=BB2_2 Depth=1
	s_clause 0x2
	global_load_b64 v[8:9], v32, s[2:3] offset:40
	global_load_b64 v[17:18], v32, s[2:3] offset:24 glc
	global_load_b64 v[11:12], v32, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v0, vcc_lo, v8, 1
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v15, vcc_lo, v0, s4
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[15:16]
	v_dual_cndmask_b32 v16, v16, v19 :: v_dual_cndmask_b32 v15, v15, v0
	v_and_b32_e32 v0, v16, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v8, v15, v8
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v8, 24
	v_mul_lo_u32 v8, v8, 24
	v_add_nc_u32_e32 v0, v9, v0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v11, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, v12, v0, vcc_lo
	global_store_b64 v[8:9], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v32, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[17:18]
	v_dual_mov_b32 v18, v12 :: v_dual_mov_b32 v17, v11
	s_cbranch_vccnz .LBB2_87
.LBB2_86:                               ; %.preheader.i.i16
                                        ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[8:9], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v32, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[17:18]
	v_dual_mov_b32 v18, v12 :: v_dual_mov_b32 v17, v11
	v_cndmask_b32_e64 v0, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 1, v0
	s_and_b32 s0, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB2_86
.LBB2_87:                               ; %__ockl_hostcall_preview.exit20
                                        ;   in Loop: Header=BB2_2 Depth=1
	v_sub_co_u32 v4, vcc_lo, v4, v33
	v_sub_co_ci_u32_e32 v5, vcc_lo, v5, v34, vcc_lo
	v_add_co_u32 v2, s0, v2, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v3, s0, v3, v34, s0
	v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB2_2
; %bb.88:                               ; %Flow177
	s_mov_b32 s0, 0
	s_branch .LBB2_90
.LBB2_89:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr6_vgpr7
.LBB2_90:                               ; %Flow193
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB2_114
; %bb.91:
	s_load_b64 s[2:3], s[8:9], 0x50
	v_mbcnt_lo_u32_b32 v2, -1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s1, v2
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	v_cmp_ne_u32_e64 s0, s1, v2
	v_cmp_eq_u32_e32 vcc_lo, s1, v2
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s0, s0, exec_lo
	s_cbranch_scc1 .LBB2_94
; %bb.92:
	v_mov_b32_e32 v0, 0
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[5:6], v0, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v0, s[2:3] offset:40
	global_load_b64 v[7:8], v0, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v3, 24
	v_mul_lo_u32 v4, v4, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v9, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, s0, v7, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v4, s0, v8, v4, s0
	global_load_b64 v[3:4], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v0, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e64 s0, v[8:9], v[5:6]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s0, s0, exec_lo
	s_cbranch_scc1 .LBB2_94
.LBB2_93:                               ; %.preheader3.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[3:4], v0, s[2:3] offset:40
	global_load_b64 v[11:12], v0, s[2:3]
	v_dual_mov_b32 v5, v8 :: v_dual_mov_b32 v6, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v7, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v7, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, s0, v11, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v4, s0, v12, v4, s0
	global_load_b64 v[3:4], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v0, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e64 s0, v[8:9], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, 0, 1, s0
	v_cmp_ne_u32_e64 s0, 1, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s0, s0, exec_lo
	s_cbranch_scc1 .LBB2_93
.LBB2_94:                               ; %.loopexit4.i.i
	v_mov_b32_e32 v3, 0
	v_cndmask_b32_e64 v0, 0, 1, vcc_lo
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_and_not1_b32 vcc_lo, exec_lo, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[11:12], v3, s[2:3] offset:40
	global_load_b128 v[4:7], v3, s[2:3]
	v_cmp_ne_u32_e64 s0, 1, v0
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v11
	v_readfirstlane_b32 s7, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_cbranch_vccnz .LBB2_96
; %bb.95:
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v4, s9
	v_dual_mov_b32 v11, exec_lo :: v_dual_mov_b32 v12, v3
	v_add_co_ci_u32_e32 v9, vcc_lo, s10, v5, vcc_lo
	v_dual_mov_b32 v13, 2 :: v_dual_mov_b32 v14, 1
	global_store_b128 v[8:9], v[11:14], off offset:8
.LBB2_96:
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[8:9], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, s6
	s_mov_b32 s12, 0
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_b32_e32 v0, 0xffffff1f, v10
	v_add_co_u32 v6, vcc_lo, v2, v8
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, s13
	s_delay_alu instid0(VALU_DEP_4)
	v_or_b32_e32 v0, 32, v0
	v_dual_mov_b32 v2, v3 :: v_dual_mov_b32 v11, s15
	v_mov_b32_e32 v10, s14
	s_and_b32 vcc_lo, exec_lo, s0
	s_clause 0x3
	global_store_b128 v[6:7], v[0:3], off
	global_store_b128 v[6:7], v[8:11], off offset:16
	global_store_b128 v[6:7], v[8:11], off offset:32
	global_store_b128 v[6:7], v[8:11], off offset:48
	s_cbranch_vccnz .LBB2_104
; %bb.97:
	v_mov_b32_e32 v10, 0
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v10, s[2:3] offset:40
	v_dual_mov_b32 v11, s4 :: v_dual_mov_b32 v12, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, s5, v1
	v_and_b32_e32 v0, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v2, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v2, v1
	v_add_co_u32 v8, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v5, v1, vcc_lo
	global_store_b64 v[8:9], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[13:14]
	s_cbranch_vccnz .LBB2_100
; %bb.98:
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
.LBB2_99:                               ; %.preheader1.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[8:9], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v10, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[2:3]
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 1, v2
	v_dual_mov_b32 v2, v11 :: v_dual_mov_b32 v3, v12
	s_and_b32 s6, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB2_99
.LBB2_100:                              ; %.loopexit2.i.i
	global_load_b64 v[0:1], v10, s[2:3] offset:16
	v_mbcnt_lo_u32_b32 v2, exec_lo, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	s_and_b32 s6, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB2_102
; %bb.101:
	s_bcnt1_i32_b32 s6, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s6
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB2_102:
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB2_104
; %bb.103:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_104:                              ; %__ockl_hsa_signal_add.exit.i.i
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB2_105:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB2_107
; %bb.106:                              ;   in Loop: Header=BB2_105 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB2_107:                              ;   in Loop: Header=BB2_105 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB2_109
; %bb.108:                              ;   in Loop: Header=BB2_105 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB2_110
.LBB2_109:                              ;   in Loop: Header=BB2_105 Depth=1
	s_mov_b32 s1, -1
.LBB2_110:                              ; %Flow182
                                        ;   in Loop: Header=BB2_105 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_105
; %bb.111:
	global_load_b128 v[6:9], v[6:7], off
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB2_114
; %bb.112:
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[2:3], v8, s[2:3] offset:40
	global_load_b64 v[9:10], v8, s[2:3] offset:24 glc
	global_load_b64 v[4:5], v8, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v12 :: v_dual_cndmask_b32 v0, v0, v11
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v0, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v11, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v9
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v10
	global_store_b64 v[4:5], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v8, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[9:10]
	s_cbranch_vccnz .LBB2_114
.LBB2_113:                              ; %.preheader.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[2:3]
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 1, v2
	v_dual_mov_b32 v2, v9 :: v_dual_mov_b32 v3, v10
	s_and_b32 s0, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB2_113
.LBB2_114:                              ; %.loopexit33
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
	s_waitcnt lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end2:
	.size	__ockl_printf_append_string_n, .Lfunc_end2-__ockl_printf_append_string_n
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 5484
; NumSgprs: 34
; NumVgprs: 39
; ScratchSize: 0
; MemoryBound: 0
	.section	.text._ZL8testFuncv,"axG",@progbits,_ZL8testFuncv,comdat
	.globl	_ZL8testFuncv                   ; -- Begin function _ZL8testFuncv
	.p2align	8
	.type	_ZL8testFuncv,@function
_ZL8testFuncv:                          ; @_ZL8testFuncv
; %bb.0:
	s_load_b64 s[24:25], s[0:1], 0x50
	s_mov_b64 s[18:19], s[0:1]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str.1@rel32@lo+4
	s_addc_u32 s1, s1, .str.1@rel32@hi+12
	v_mbcnt_lo_u32_b32 v50, -1, 0
	s_cmp_lg_u64 s[0:1], 0
	v_dual_mov_b32 v45, 0 :: v_dual_mov_b32 v48, 2
	s_cselect_b32 s28, 31, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	v_mov_b32_e32 v49, 1
	v_mov_b32_e32 v43, 33
	s_cmp_lg_u64 s[0:1], 0
	s_mov_b32 s20, 0
	s_mov_b64 s[26:27], 0
	s_cselect_b32 s29, 27, 0
	s_mov_b32 s32, 0
.LBB3_1:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_4 Depth 2
                                        ;     Child Loop BB3_9 Depth 2
                                        ;     Child Loop BB3_15 Depth 2
                                        ;     Child Loop BB3_23 Depth 2
                                        ;     Child Loop BB3_26 Depth 2
                                        ;     Child Loop BB3_31 Depth 2
                                        ;     Child Loop BB3_37 Depth 2
                                        ;     Child Loop BB3_45 Depth 2
                                        ;     Child Loop BB3_50 Depth 2
                                        ;     Child Loop BB3_55 Depth 2
                                        ;     Child Loop BB3_61 Depth 2
                                        ;     Child Loop BB3_69 Depth 2
                                        ;     Child Loop BB3_72 Depth 2
                                        ;     Child Loop BB3_77 Depth 2
                                        ;     Child Loop BB3_83 Depth 2
                                        ;     Child Loop BB3_91 Depth 2
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, stonks@rel32@lo+4
	s_addc_u32 s1, s1, stonks@rel32@hi+12
	s_lshl_b64 s[2:3], s[26:27], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_load_b64 v[41:42], v45, s[0:1]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _ZL8testSeedl@rel32@lo+4
	s_addc_u32 s1, s1, _ZL8testSeedl@rel32@hi+12
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v0, 0x89a3, v41
	v_mul_hi_u32 v1, 0x6e758065, v41
	v_mul_lo_u32 v2, 0x6e758065, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, v1, v0
	v_mul_lo_u32 v1, 0x6e758065, v41
	v_add_nc_u32_e32 v2, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, 0xd8f3c9e9, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, 0xd75, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_and_b32_e32 v1, 0xffff, v1
	s_swappc_b64 s[30:31], s[0:1]
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_and_b32 s0, vcc_lo, exec_lo
	s_mov_b32 s0, -1
	s_cbranch_scc0 .LBB3_47
; %bb.2:                                ;   in Loop: Header=BB3_1 Depth=1
	v_mov_b32_e32 v44, v50
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v44
	v_cmp_ne_u32_e32 vcc_lo, s0, v44
	s_and_b32 s1, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB3_5
; %bb.3:                                ;   in Loop: Header=BB3_1 Depth=1
	global_load_b64 v[2:3], v45, s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v45, s[24:25] offset:40
	global_load_b64 v[4:5], v45, s[24:25]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v45, v[0:3], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
	s_and_b32 s1, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB3_5
.LBB3_4:                                ; %.preheader3.i.i.i16
                                        ;   Parent Loop BB3_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[0:1], v45, s[24:25] offset:40
	global_load_b64 v[6:7], v45, s[24:25]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v4, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v45, v[0:3], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
	v_cndmask_b32_e64 v0, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 1, v0
	s_and_b32 s1, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB3_4
.LBB3_5:                                ; %.loopexit4.i.i.i11
                                        ;   in Loop: Header=BB3_1 Depth=1
	s_clause 0x1
	global_load_b64 v[6:7], v45, s[24:25] offset:40
	global_load_b128 v[0:3], v45, s[24:25]
	v_cmp_eq_u32_e32 vcc_lo, s0, v44
	v_readfirstlane_b32 s2, v4
	v_readfirstlane_b32 s3, v5
	v_cndmask_b32_e64 v8, 0, 1, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cmp_ne_u32_e64 s0, 1, v8
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_cbranch_vccnz .LBB3_7
; %bb.6:                                ;   in Loop: Header=BB3_1 Depth=1
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v0, s7
	v_dual_mov_b32 v46, exec_lo :: v_dual_mov_b32 v47, v45
	v_add_co_ci_u32_e32 v5, vcc_lo, s8, v1, vcc_lo
	global_store_b128 v[4:5], v[46:49], off offset:8
.LBB3_7:                                ;   in Loop: Header=BB3_1 Depth=1
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[4:5], 6, v[44:45]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v4
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v5, vcc_lo
	v_mov_b32_e32 v2, s20
	v_dual_mov_b32 v44, v45 :: v_dual_mov_b32 v3, s21
	v_dual_mov_b32 v46, v45 :: v_dual_mov_b32 v5, s23
	v_mov_b32_e32 v4, s22
	s_and_b32 vcc_lo, exec_lo, s0
	s_clause 0x3
	global_store_b128 v[6:7], v[43:46], off
	global_store_b128 v[6:7], v[2:5], off offset:16
	global_store_b128 v[6:7], v[2:5], off offset:32
	global_store_b128 v[6:7], v[2:5], off offset:48
	s_cbranch_vccnz .LBB3_14
; %bb.8:                                ;   in Loop: Header=BB3_1 Depth=1
	s_clause 0x1
	global_load_b64 v[12:13], v45, s[24:25] offset:32 glc
	global_load_b64 v[2:3], v45, s[24:25] offset:40
	v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s4, v2
	v_readfirstlane_b32 s5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[4:5], s[2:3]
	s_mul_i32 s5, s5, 24
	s_mul_hi_u32 s8, s4, 24
	s_mul_i32 s4, s4, 24
	s_add_i32 s8, s8, s5
	v_add_co_u32 v8, vcc_lo, v0, s4
	v_add_co_ci_u32_e32 v9, vcc_lo, s8, v1, vcc_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v45, v[10:13], s[24:25] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[12:13]
	s_cbranch_vccnz .LBB3_10
.LBB3_9:                                ; %.preheader1.i.i.i14
                                        ;   Parent Loop BB3_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v45, v[2:5], s[24:25] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_cndmask_b32_e64 v4, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 1, v4
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_and_b32 s4, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB3_9
.LBB3_10:                               ; %.loopexit2.i.i.i15
                                        ;   in Loop: Header=BB3_1 Depth=1
	global_load_b64 v[2:3], v45, s[24:25] offset:16
	v_mbcnt_lo_u32_b32 v4, exec_lo, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	s_and_b32 s4, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB3_12
; %bb.11:                               ;   in Loop: Header=BB3_1 Depth=1
	s_bcnt1_i32_b32 s4, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v44, s4
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[44:45], off offset:8
.LBB3_12:                               ;   in Loop: Header=BB3_1 Depth=1
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB3_14
; %bb.13:                               ;   in Loop: Header=BB3_1 Depth=1
	global_load_b32 v44, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s4, v44
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[44:45], off
	s_and_b32 m0, s4, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB3_14:                               ; %__ockl_hsa_signal_add.exit.i.i.i12
                                        ;   in Loop: Header=BB3_1 Depth=1
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB3_15:                               ;   Parent Loop BB3_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB3_17
; %bb.16:                               ;   in Loop: Header=BB3_15 Depth=2
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB3_17:                               ;   in Loop: Header=BB3_15 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB3_19
; %bb.18:                               ;   in Loop: Header=BB3_15 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB3_20
.LBB3_19:                               ;   in Loop: Header=BB3_15 Depth=2
	s_mov_b32 s1, -1
.LBB3_20:                               ; %Flow188
                                        ;   in Loop: Header=BB3_15 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB3_15
; %bb.21:                               ;   in Loop: Header=BB3_1 Depth=1
	global_load_b64 v[0:1], v[6:7], off
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB3_24
; %bb.22:                               ;   in Loop: Header=BB3_1 Depth=1
	s_clause 0x2
	global_load_b64 v[6:7], v45, s[24:25] offset:40
	global_load_b64 v[4:5], v45, s[24:25] offset:24 glc
	global_load_b64 v[8:9], v45, s[24:25]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v6, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v10, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
	v_and_b32_e32 v7, v3, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v6, v2, v6
	v_mul_lo_u32 v7, v7, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v6, 24
	v_mul_lo_u32 v6, v6, 24
	v_add_nc_u32_e32 v7, v10, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v8, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, v9, v7, vcc_lo
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v45, v[2:5], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
	v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
	s_cbranch_vccnz .LBB3_24
.LBB3_23:                               ; %.preheader.i.i.i13
                                        ;   Parent Loop BB3_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v45, v[2:5], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
	v_cndmask_b32_e64 v4, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 1, v4
	v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
	s_and_b32 s0, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB3_23
.LBB3_24:                               ; %__ockl_printf_begin.exit17
                                        ;   in Loop: Header=BB3_1 Depth=1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str.1@rel32@lo+4
	s_addc_u32 s1, s1, .str.1@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
	v_dual_mov_b32 v4, s28 :: v_dual_mov_b32 v5, 0
	s_mov_b64 s[8:9], s[18:19]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_swappc_b64 s[30:31], s[2:3]
	v_mov_b32_e32 v44, v50
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v44
	v_dual_mov_b32 v40, v1 :: v_dual_mov_b32 v5, 0
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, s0, v44
	s_and_b32 s1, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB3_27
; %bb.25:                               ;   in Loop: Header=BB3_1 Depth=1
	global_load_b64 v[3:4], v45, s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v45, s[24:25] offset:40
	global_load_b64 v[5:6], v45, s[24:25]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, v2, v4
	v_and_b32_e32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v2, 24
	v_mul_hi_u32 v7, v1, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v7, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v5, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v45, v[1:4], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[3:4]
	s_and_b32 s1, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB3_27
.LBB3_26:                               ; %.preheader3.i.i.i23
                                        ;   Parent Loop BB3_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[1:2], v45, s[24:25] offset:40
	global_load_b64 v[7:8], v45, s[24:25]
	v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v6
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v2, v4
	v_and_b32_e32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v2, 24
	v_mul_hi_u32 v5, v1, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v5, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v7, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v8, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v45, v[1:4], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[3:4]
	v_cndmask_b32_e64 v1, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 1, v1
	s_and_b32 s1, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB3_26
.LBB3_27:                               ; %.loopexit4.i.i.i18
                                        ;   in Loop: Header=BB3_1 Depth=1
	s_clause 0x1
	global_load_b64 v[7:8], v45, s[24:25] offset:40
	global_load_b128 v[1:4], v45, s[24:25]
	v_cmp_eq_u32_e32 vcc_lo, s0, v44
	v_readfirstlane_b32 s2, v5
	v_readfirstlane_b32 s3, v6
	v_cndmask_b32_e64 v9, 0, 1, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cmp_ne_u32_e64 s0, 1, v9
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v7
	v_readfirstlane_b32 s5, v8
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_cbranch_vccnz .LBB3_29
; %bb.28:                               ;   in Loop: Header=BB3_1 Depth=1
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v1, s7
	v_dual_mov_b32 v46, exec_lo :: v_dual_mov_b32 v47, v45
	v_add_co_ci_u32_e32 v6, vcc_lo, s8, v2, vcc_lo
	global_store_b128 v[5:6], v[46:49], off offset:8
.LBB3_29:                               ;   in Loop: Header=BB3_1 Depth=1
	s_lshl_b64 s[4:5], s[4:5], 12
	s_mov_b32 s21, s20
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v3, s4
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
	v_lshlrev_b64 v[3:4], 6, v[44:45]
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_b32_e32 v0, 0xffffff1d, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v5, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, v6, v4, vcc_lo
	v_mov_b32_e32 v3, s20
	s_delay_alu instid0(VALU_DEP_4)
	v_or_b32_e32 v39, 34, v0
	v_dual_mov_b32 v4, s21 :: v_dual_mov_b32 v5, s22
	v_mov_b32_e32 v6, s23
	s_and_b32 vcc_lo, exec_lo, s0
	s_clause 0x3
	global_store_b128 v[7:8], v[39:42], off
	global_store_b128 v[7:8], v[3:6], off offset:16
	global_store_b128 v[7:8], v[3:6], off offset:32
	global_store_b128 v[7:8], v[3:6], off offset:48
	s_cbranch_vccnz .LBB3_36
; %bb.30:                               ;   in Loop: Header=BB3_1 Depth=1
	s_clause 0x1
	global_load_b64 v[11:12], v45, s[24:25] offset:32 glc
	global_load_b64 v[3:4], v45, s[24:25] offset:40
	v_dual_mov_b32 v9, s2 :: v_dual_mov_b32 v10, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s4, v3
	v_readfirstlane_b32 s5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[4:5], s[2:3]
	s_mul_i32 s5, s5, 24
	s_mul_hi_u32 s8, s4, 24
	s_mul_i32 s4, s4, 24
	s_add_i32 s8, s8, s5
	v_add_co_u32 v7, vcc_lo, v1, s4
	v_add_co_ci_u32_e32 v8, vcc_lo, s8, v2, vcc_lo
	global_store_b64 v[7:8], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v45, v[9:12], s[24:25] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[11:12]
	s_cbranch_vccnz .LBB3_32
.LBB3_31:                               ; %.preheader1.i.i.i21
                                        ;   Parent Loop BB3_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s3
	s_sleep 1
	global_store_b64 v[7:8], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v45, v[3:6], s[24:25] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	v_cndmask_b32_e64 v0, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 1, v0
	s_and_b32 s4, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB3_31
.LBB3_32:                               ; %.loopexit2.i.i.i22
                                        ;   in Loop: Header=BB3_1 Depth=1
	global_load_b64 v[3:4], v45, s[24:25] offset:16
	v_mbcnt_lo_u32_b32 v0, exec_lo, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
	s_and_b32 s4, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB3_34
; %bb.33:                               ;   in Loop: Header=BB3_1 Depth=1
	s_bcnt1_i32_b32 s4, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v44, s4
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[44:45], off offset:8
.LBB3_34:                               ;   in Loop: Header=BB3_1 Depth=1
	s_waitcnt vmcnt(0)
	global_load_b64 v[5:6], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
	s_cbranch_vccnz .LBB3_36
; %bb.35:                               ;   in Loop: Header=BB3_1 Depth=1
	global_load_b32 v44, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s4, v44
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[5:6], v[44:45], off
	s_and_b32 m0, s4, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB3_36:                               ; %__ockl_hsa_signal_add.exit.i.i.i19
                                        ;   in Loop: Header=BB3_1 Depth=1
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v1, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB3_37:                               ;   Parent Loop BB3_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB3_39
; %bb.38:                               ;   in Loop: Header=BB3_37 Depth=2
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB3_39:                               ;   in Loop: Header=BB3_37 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB3_41
; %bb.40:                               ;   in Loop: Header=BB3_37 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB3_42
.LBB3_41:                               ;   in Loop: Header=BB3_37 Depth=2
	s_mov_b32 s1, -1
.LBB3_42:                               ; %Flow174
                                        ;   in Loop: Header=BB3_37 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB3_37
; %bb.43:                               ;   in Loop: Header=BB3_1 Depth=1
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB3_46
; %bb.44:                               ;   in Loop: Header=BB3_1 Depth=1
	s_clause 0x2
	global_load_b64 v[4:5], v45, s[24:25] offset:40
	global_load_b64 v[2:3], v45, s[24:25] offset:24 glc
	global_load_b64 v[6:7], v45, s[24:25]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v8, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v8, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v9 :: v_dual_cndmask_b32 v0, v0, v8
	v_and_b32_e32 v5, v1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v0, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v8, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v8, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v6, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, v7, v5, vcc_lo
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v45, v[0:3], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
	v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
	s_cbranch_vccnz .LBB3_46
.LBB3_45:                               ; %.preheader.i.i.i20
                                        ;   Parent Loop BB3_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v45, v[0:3], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 1, v2
	v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
	s_and_b32 s0, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB3_45
.LBB3_46:                               ; %Flow172
                                        ;   in Loop: Header=BB3_1 Depth=1
	s_mov_b32 s0, 0
.LBB3_47:                               ; %Flow228
                                        ;   in Loop: Header=BB3_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB3_92
; %bb.48:                               ;   in Loop: Header=BB3_1 Depth=1
	v_mov_b32_e32 v44, v50
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v44
	v_cmp_ne_u32_e32 vcc_lo, s0, v44
	s_and_b32 s1, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB3_51
; %bb.49:                               ;   in Loop: Header=BB3_1 Depth=1
	global_load_b64 v[2:3], v45, s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v45, s[24:25] offset:40
	global_load_b64 v[4:5], v45, s[24:25]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v45, v[0:3], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
	s_and_b32 s1, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB3_51
.LBB3_50:                               ; %.preheader3.i.i.i
                                        ;   Parent Loop BB3_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[0:1], v45, s[24:25] offset:40
	global_load_b64 v[6:7], v45, s[24:25]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v4, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v45, v[0:3], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
	v_cndmask_b32_e64 v0, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 1, v0
	s_and_b32 s1, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB3_50
.LBB3_51:                               ; %.loopexit4.i.i.i
                                        ;   in Loop: Header=BB3_1 Depth=1
	s_clause 0x1
	global_load_b64 v[6:7], v45, s[24:25] offset:40
	global_load_b128 v[0:3], v45, s[24:25]
	v_cmp_eq_u32_e32 vcc_lo, s0, v44
	v_readfirstlane_b32 s2, v4
	v_readfirstlane_b32 s3, v5
	v_cndmask_b32_e64 v8, 0, 1, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cmp_ne_u32_e64 s0, 1, v8
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_cbranch_vccnz .LBB3_53
; %bb.52:                               ;   in Loop: Header=BB3_1 Depth=1
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v0, s7
	v_dual_mov_b32 v46, exec_lo :: v_dual_mov_b32 v47, v45
	v_add_co_ci_u32_e32 v5, vcc_lo, s8, v1, vcc_lo
	global_store_b128 v[4:5], v[46:49], off offset:8
.LBB3_53:                               ;   in Loop: Header=BB3_1 Depth=1
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[4:5], 6, v[44:45]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v4
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v5, vcc_lo
	v_mov_b32_e32 v2, s20
	v_dual_mov_b32 v44, v45 :: v_dual_mov_b32 v3, s21
	v_dual_mov_b32 v46, v45 :: v_dual_mov_b32 v5, s23
	v_mov_b32_e32 v4, s22
	s_and_b32 vcc_lo, exec_lo, s0
	s_clause 0x3
	global_store_b128 v[6:7], v[43:46], off
	global_store_b128 v[6:7], v[2:5], off offset:16
	global_store_b128 v[6:7], v[2:5], off offset:32
	global_store_b128 v[6:7], v[2:5], off offset:48
	s_cbranch_vccnz .LBB3_60
; %bb.54:                               ;   in Loop: Header=BB3_1 Depth=1
	s_clause 0x1
	global_load_b64 v[12:13], v45, s[24:25] offset:32 glc
	global_load_b64 v[2:3], v45, s[24:25] offset:40
	v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s4, v2
	v_readfirstlane_b32 s5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[4:5], s[2:3]
	s_mul_i32 s5, s5, 24
	s_mul_hi_u32 s8, s4, 24
	s_mul_i32 s4, s4, 24
	s_add_i32 s8, s8, s5
	v_add_co_u32 v8, vcc_lo, v0, s4
	v_add_co_ci_u32_e32 v9, vcc_lo, s8, v1, vcc_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v45, v[10:13], s[24:25] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[12:13]
	s_cbranch_vccnz .LBB3_56
.LBB3_55:                               ; %.preheader1.i.i.i
                                        ;   Parent Loop BB3_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v45, v[2:5], s[24:25] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_cndmask_b32_e64 v4, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 1, v4
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_and_b32 s4, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB3_55
.LBB3_56:                               ; %.loopexit2.i.i.i
                                        ;   in Loop: Header=BB3_1 Depth=1
	global_load_b64 v[2:3], v45, s[24:25] offset:16
	v_mbcnt_lo_u32_b32 v4, exec_lo, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	s_and_b32 s4, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB3_58
; %bb.57:                               ;   in Loop: Header=BB3_1 Depth=1
	s_bcnt1_i32_b32 s4, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v44, s4
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[44:45], off offset:8
.LBB3_58:                               ;   in Loop: Header=BB3_1 Depth=1
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB3_60
; %bb.59:                               ;   in Loop: Header=BB3_1 Depth=1
	global_load_b32 v44, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s4, v44
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[44:45], off
	s_and_b32 m0, s4, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB3_60:                               ; %__ockl_hsa_signal_add.exit.i.i.i
                                        ;   in Loop: Header=BB3_1 Depth=1
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB3_61:                               ;   Parent Loop BB3_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB3_63
; %bb.62:                               ;   in Loop: Header=BB3_61 Depth=2
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB3_63:                               ;   in Loop: Header=BB3_61 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB3_65
; %bb.64:                               ;   in Loop: Header=BB3_61 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB3_66
.LBB3_65:                               ;   in Loop: Header=BB3_61 Depth=2
	s_mov_b32 s1, -1
.LBB3_66:                               ; %Flow217
                                        ;   in Loop: Header=BB3_61 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB3_61
; %bb.67:                               ;   in Loop: Header=BB3_1 Depth=1
	global_load_b64 v[0:1], v[6:7], off
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB3_70
; %bb.68:                               ;   in Loop: Header=BB3_1 Depth=1
	s_clause 0x2
	global_load_b64 v[6:7], v45, s[24:25] offset:40
	global_load_b64 v[4:5], v45, s[24:25] offset:24 glc
	global_load_b64 v[8:9], v45, s[24:25]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v6, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v10, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
	v_and_b32_e32 v7, v3, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v6, v2, v6
	v_mul_lo_u32 v7, v7, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v6, 24
	v_mul_lo_u32 v6, v6, 24
	v_add_nc_u32_e32 v7, v10, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v8, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, v9, v7, vcc_lo
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v45, v[2:5], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
	v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
	s_cbranch_vccnz .LBB3_70
.LBB3_69:                               ; %.preheader.i.i.i
                                        ;   Parent Loop BB3_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v45, v[2:5], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
	v_cndmask_b32_e64 v4, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 1, v4
	v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
	s_and_b32 s0, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB3_69
.LBB3_70:                               ; %__ockl_printf_begin.exit
                                        ;   in Loop: Header=BB3_1 Depth=1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
	v_dual_mov_b32 v4, s29 :: v_dual_mov_b32 v5, 0
	s_mov_b64 s[8:9], s[18:19]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_swappc_b64 s[30:31], s[2:3]
	v_mov_b32_e32 v44, v50
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v44
	v_dual_mov_b32 v40, v1 :: v_dual_mov_b32 v5, 0
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, s0, v44
	s_and_b32 s1, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB3_73
; %bb.71:                               ;   in Loop: Header=BB3_1 Depth=1
	global_load_b64 v[3:4], v45, s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v45, s[24:25] offset:40
	global_load_b64 v[5:6], v45, s[24:25]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v2, v2, v4
	v_and_b32_e32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v2, 24
	v_mul_hi_u32 v7, v1, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v7, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v5, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v45, v[1:4], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[3:4]
	s_and_b32 s1, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB3_73
.LBB3_72:                               ; %.preheader3.i.i.i10
                                        ;   Parent Loop BB3_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[1:2], v45, s[24:25] offset:40
	global_load_b64 v[7:8], v45, s[24:25]
	v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v6
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v2, v4
	v_and_b32_e32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v2, 24
	v_mul_hi_u32 v5, v1, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v5, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v7, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v8, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[5:6], v45, v[1:4], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[3:4]
	v_cndmask_b32_e64 v1, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 1, v1
	s_and_b32 s1, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB3_72
.LBB3_73:                               ; %.loopexit4.i.i.i5
                                        ;   in Loop: Header=BB3_1 Depth=1
	s_clause 0x1
	global_load_b64 v[7:8], v45, s[24:25] offset:40
	global_load_b128 v[1:4], v45, s[24:25]
	v_cmp_eq_u32_e32 vcc_lo, s0, v44
	v_readfirstlane_b32 s2, v5
	v_readfirstlane_b32 s3, v6
	v_cndmask_b32_e64 v9, 0, 1, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cmp_ne_u32_e64 s0, 1, v9
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v7
	v_readfirstlane_b32 s5, v8
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_cbranch_vccnz .LBB3_75
; %bb.74:                               ;   in Loop: Header=BB3_1 Depth=1
	s_add_i32 s8, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v1, s7
	v_dual_mov_b32 v46, exec_lo :: v_dual_mov_b32 v47, v45
	v_add_co_ci_u32_e32 v6, vcc_lo, s8, v2, vcc_lo
	global_store_b128 v[5:6], v[46:49], off offset:8
.LBB3_75:                               ;   in Loop: Header=BB3_1 Depth=1
	s_lshl_b64 s[4:5], s[4:5], 12
	s_mov_b32 s21, s20
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v3, s4
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
	v_lshlrev_b64 v[3:4], 6, v[44:45]
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_b32_e32 v0, 0xffffff1d, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v5, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, v6, v4, vcc_lo
	v_mov_b32_e32 v3, s20
	s_delay_alu instid0(VALU_DEP_4)
	v_or_b32_e32 v39, 34, v0
	v_dual_mov_b32 v4, s21 :: v_dual_mov_b32 v5, s22
	v_mov_b32_e32 v6, s23
	s_and_b32 vcc_lo, exec_lo, s0
	s_clause 0x3
	global_store_b128 v[7:8], v[39:42], off
	global_store_b128 v[7:8], v[3:6], off offset:16
	global_store_b128 v[7:8], v[3:6], off offset:32
	global_store_b128 v[7:8], v[3:6], off offset:48
	s_cbranch_vccnz .LBB3_82
; %bb.76:                               ;   in Loop: Header=BB3_1 Depth=1
	s_clause 0x1
	global_load_b64 v[11:12], v45, s[24:25] offset:32 glc
	global_load_b64 v[3:4], v45, s[24:25] offset:40
	v_dual_mov_b32 v9, s2 :: v_dual_mov_b32 v10, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s4, v3
	v_readfirstlane_b32 s5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[4:5], s[2:3]
	s_mul_i32 s5, s5, 24
	s_mul_hi_u32 s8, s4, 24
	s_mul_i32 s4, s4, 24
	s_add_i32 s8, s8, s5
	v_add_co_u32 v7, vcc_lo, v1, s4
	v_add_co_ci_u32_e32 v8, vcc_lo, s8, v2, vcc_lo
	global_store_b64 v[7:8], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v45, v[9:12], s[24:25] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[11:12]
	s_cbranch_vccnz .LBB3_78
.LBB3_77:                               ; %.preheader1.i.i.i8
                                        ;   Parent Loop BB3_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s3
	s_sleep 1
	global_store_b64 v[7:8], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v45, v[3:6], s[24:25] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	v_cndmask_b32_e64 v0, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 1, v0
	s_and_b32 s4, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB3_77
.LBB3_78:                               ; %.loopexit2.i.i.i9
                                        ;   in Loop: Header=BB3_1 Depth=1
	global_load_b64 v[3:4], v45, s[24:25] offset:16
	v_mbcnt_lo_u32_b32 v0, exec_lo, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
	s_and_b32 s4, vcc_lo, exec_lo
	s_cbranch_scc1 .LBB3_80
; %bb.79:                               ;   in Loop: Header=BB3_1 Depth=1
	s_bcnt1_i32_b32 s4, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v44, s4
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[44:45], off offset:8
.LBB3_80:                               ;   in Loop: Header=BB3_1 Depth=1
	s_waitcnt vmcnt(0)
	global_load_b64 v[5:6], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
	s_cbranch_vccnz .LBB3_82
; %bb.81:                               ;   in Loop: Header=BB3_1 Depth=1
	global_load_b32 v44, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s4, v44
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[5:6], v[44:45], off
	s_and_b32 m0, s4, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB3_82:                               ; %__ockl_hsa_signal_add.exit.i.i.i6
                                        ;   in Loop: Header=BB3_1 Depth=1
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v1, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB3_83:                               ;   Parent Loop BB3_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB3_85
; %bb.84:                               ;   in Loop: Header=BB3_83 Depth=2
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB3_85:                               ;   in Loop: Header=BB3_83 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB3_87
; %bb.86:                               ;   in Loop: Header=BB3_83 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB3_88
.LBB3_87:                               ;   in Loop: Header=BB3_83 Depth=2
	s_mov_b32 s1, -1
.LBB3_88:                               ; %Flow203
                                        ;   in Loop: Header=BB3_83 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB3_83
; %bb.89:                               ;   in Loop: Header=BB3_1 Depth=1
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB3_92
; %bb.90:                               ;   in Loop: Header=BB3_1 Depth=1
	s_clause 0x2
	global_load_b64 v[4:5], v45, s[24:25] offset:40
	global_load_b64 v[2:3], v45, s[24:25] offset:24 glc
	global_load_b64 v[6:7], v45, s[24:25]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v8, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v8, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v9 :: v_dual_cndmask_b32 v0, v0, v8
	v_and_b32_e32 v5, v1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v0, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v8, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v8, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v6, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, v7, v5, vcc_lo
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v45, v[0:3], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
	v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
	s_cbranch_vccnz .LBB3_92
.LBB3_91:                               ; %.preheader.i.i.i7
                                        ;   Parent Loop BB3_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v45, v[0:3], s[24:25] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
	v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
	s_cbranch_vccz .LBB3_91
.LBB3_92:                               ; %__ockl_printf_append_args.exit
                                        ;   in Loop: Header=BB3_1 Depth=1
	s_add_u32 s26, s26, 1
	s_addc_u32 s27, s27, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u64 s[26:27], 6
	s_cbranch_scc0 .LBB3_1
; %bb.93:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL8testFuncv
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 448
		.amdhsa_kernarg_size 256
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 51
		.amdhsa_next_free_sgpr 33
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL8testFuncv,"axG",@progbits,_ZL8testFuncv,comdat
.Lfunc_end3:
	.size	_ZL8testFuncv, .Lfunc_end3-_ZL8testFuncv
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5676
; NumSgprs: 35
; NumVgprs: 51
; ScratchSize: 448
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 35
; NumVGPRsForWavesPerEU: 51
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	stonks                  ; @stonks
	.type	stonks,@object
	.data
	.globl	stonks
	.p2align	4, 0x0
stonks:
	.quad	3033227586                      ; 0xb4cb6142
	.quad	11299383782                     ; 0x2a17ee9e6
	.quad	19174124756                     ; 0x476ddecd4
	.quad	26213759191                     ; 0x61a7638d7
	.quad	30882125013                     ; 0x730b7d4d5
	.quad	31573082574                     ; 0x759e701ce
	.size	stonks, 48

	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"THIS SEED IS STONKS: %lld\n"
	.size	.str, 27

	.type	.str.1,@object                  ; @.str.1
.str.1:
	.asciz	"THIS SEED IS NOT STONKS: %lld\n"
	.size	.str.1, 31

	.type	_ZL6Chest1,@object              ; @_ZL6Chest1
	.section	.rodata,"a",@progbits
	.p2align	4, 0x0
_ZL6Chest1:
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.long	7                               ; 0x7
	.long	1                               ; 0x1
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.long	8                               ; 0x8
	.long	1                               ; 0x1
	.long	7                               ; 0x7
	.long	1                               ; 0x1
	.zero	8
	.zero	8
	.zero	8
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.size	_ZL6Chest1, 216

	.type	_ZL6Chest2,@object              ; @_ZL6Chest2
	.p2align	4, 0x0
_ZL6Chest2:
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.long	3                               ; 0x3
	.long	1                               ; 0x1
	.zero	8
	.long	7                               ; 0x7
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.zero	8
	.long	6                               ; 0x6
	.long	1                               ; 0x1
	.zero	8
	.zero	8
	.zero	8
	.long	7                               ; 0x7
	.long	3                               ; 0x3
	.zero	64
	.size	_ZL6Chest2, 216

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym stonks
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 256
    .name:           _ZL10threadWorklPjPl
    .private_segment_fixed_size: 448
    .sgpr_count:     35
    .sgpr_spill_count: 0
    .symbol:         _ZL10threadWorklPjPl.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     18
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         4
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         12
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         14
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         16
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         18
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         20
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         22
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         40
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         64
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         80
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 256
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1
    .name:           _ZL8testFuncv
    .private_segment_fixed_size: 448
    .sgpr_count:     35
    .sgpr_spill_count: 0
    .symbol:         _ZL8testFuncv.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     51
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
