#include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>

#define __DEBUG

#define VSQR 0.1
#define TSCALE 1.0

#define CUDA_CALL(err) __cudaSafeCall(err, __FILE__, __LINE__)
#define CUDA_CHK_ERR() __cudaCheckError(__FILE__, __LINE__)

/**************************************
 * void __cudaSafeCall(cudaError err, const char *file, const int line)
 * void __cudaCheckError(const char *file, const int line)
 *
 * These routines were taken from the GPU Computing SDK
 * (http://developer.nvidia.com/gpu-computing-sdk) include file "cutil.h"
 **************************************/
inline void __cudaSafeCall(cudaError err, const char* file, const int line) {
#ifdef __DEBUG

#pragma warning(push)
#pragma warning(disable : 4127) // Prevent warning on do-while(0);
    do {
        if (cudaSuccess != err) {
            fprintf(stderr, "cudaSafeCall() failed at %s:%i : %s\n", file, line, cudaGetErrorString(err));
            exit(-1);
        }
    } while (0);
#pragma warning(pop)
#endif // __DEBUG
    return;
}

inline void __cudaCheckError(const char* file, const int line) {
#ifdef __DEBUG
#pragma warning(push)
#pragma warning(disable : 4127) // Prevent warning on do-while(0);
    do {
        cudaError_t err = cudaGetLastError();
        if (cudaSuccess != err) {
            fprintf(stderr, "cudaCheckError() failed at %s:%i : %s.\n", file, line, cudaGetErrorString(err));
            exit(-1);
        }
        // More careful checking. However, this will affect performance.
        // Comment if not needed.
        /*err = cudaThreadSynchronize();
        if( cudaSuccess != err )
        {
          fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s.\n",
                   file, line, cudaGetErrorString( err ) );
          exit( -1 );
        }*/
    } while (0);
#pragma warning(pop)
#endif // __DEBUG
    return;
}

int tpdt(double* t, double dt, double end_time);
__device__ double f_gpu(double p, double t) { return -expf(-TSCALE * t) * p; }

__global__ void evolve_gpu(double* un, double* uc, double* uo, double* pebbles, int n, double h, double dt, double t)
{
    __shared__ int i, j, idx;

    idx = (blockIdx.y * gridDim.x + blockIdx.x) * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x + threadIdx.x);

    i = idx / n;
    j = idx % n;

    if (i == 0 || i == n - 1 || j == 0 || j == n - 1)
        un[idx] = 0.;
    else
        un[idx] = 2 * uc[idx] - uo[idx] + VSQR * (dt * dt) * ((uc[idx - 1] + uc[idx + 1] + uc[idx + n] + uc[idx - n] + 0.25 * (uc[idx - 1 - n] + uc[idx - 1 + n] + uc[idx + 1 - n] + uc[idx + 1 + n]) - 5 * uc[idx]) / (h * h) + f_gpu(pebbles[idx], t));
}

void run_gpu(double* u, double* u0, double* u1, double* pebbles, int n, double h, double end_time, int nthreads) {
    cudaEvent_t kstart, kstop;
    float ktime;

    /* HW2: Define your local variables here */
    // declare the variables
    double* gpu_uc;
    double* gpu_uo;
    double* gpu_un;
    double* gpu_pebbles;

    /* Set up device timers */
    CUDA_CALL(cudaSetDevice(0));
    CUDA_CALL(cudaEventCreate(&kstart));
    CUDA_CALL(cudaEventCreate(&kstop));

    /* HW2: Add CUDA kernel call preperation code here */
    // malloc mem on GPU and copy the content
    cudaMalloc((void**)&gpu_uc, sizeof(double) * n * n);
    cudaMalloc((void**)&gpu_uo, sizeof(double) * n * n);
    cudaMalloc((void**)&gpu_un, sizeof(double) * n * n);
    cudaMalloc((void**)&gpu_pebbles, sizeof(double) * n * n);
    cudaMemcpy((void*)gpu_uo, (void*)u0, sizeof(double) * n * n, cudaMemcpyHostToDevice);
    cudaMemcpy((void*)gpu_uc, (void*)u1, sizeof(double) * n * n, cudaMemcpyHostToDevice);
    cudaMemcpy((void*)gpu_pebbles, (void*)pebbles, sizeof(double) * n * n, cudaMemcpyHostToDevice);
    double t = 0., dt = h / 2.;

    int grid_size = n / nthreads;
    int block_size = nthreads;

    dim3 grid(grid_size, grid_size);
    dim3 block(block_size, block_size);

    /* Start GPU computation timer */
    CUDA_CALL(cudaEventRecord(kstart, 0));

    /* HW2: Add main lake simulation loop here */
    // do the calculation
    while (1) {
        evolve_gpu<<<grid, block>>>(gpu_un, gpu_uc, gpu_uo, gpu_pebbles, n, h, dt, t);

        cudaMemcpy((void*)gpu_uo, (void*)gpu_uc, sizeof(double) * n * n, cudaMemcpyDeviceToDevice);
        cudaMemcpy((void*)gpu_uc, (void*)gpu_un, sizeof(double) * n * n, cudaMemcpyDeviceToDevice);

        if (!tpdt(&t, dt, end_time))
            break;
    }
    
    cudaMemcpy((void*)u, (void*)gpu_un, sizeof(double) * n * n, cudaMemcpyDeviceToHost);

    /* Stop GPU computation timer */
    CUDA_CALL(cudaEventRecord(kstop, 0));
    CUDA_CALL(cudaEventSynchronize(kstop));
    CUDA_CALL(cudaEventElapsedTime(&ktime, kstart, kstop));
    printf("GPU computation: %f msec\n", ktime);

    /* HW2: Add post CUDA kernel call processing and cleanup here */

    /* timer cleanup */
    CUDA_CALL(cudaEventDestroy(kstart));
    CUDA_CALL(cudaEventDestroy(kstop));
}

	.file	"tmpxft_0022a7ab_00000000-6_lakegpu.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2033:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata._Z14__cudaSafeCall9cudaErrorPKci.str1.1,"aMS",@progbits,1
.LC0:
	.string	"cudaSafeCall() failed at %s:%i : %s\n"
	.section	.text._Z14__cudaSafeCall9cudaErrorPKci,"axG",@progbits,_Z14__cudaSafeCall9cudaErrorPKci,comdat
	.weak	_Z14__cudaSafeCall9cudaErrorPKci
	.type	_Z14__cudaSafeCall9cudaErrorPKci, @function
_Z14__cudaSafeCall9cudaErrorPKci:
.LFB2027:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L2
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	%rsi, %rbx
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	movl	%edx, 12(%rsp)
	call	cudaGetErrorString@PLT
	movq	stderr(%rip), %rdi
	movq	%rbx, %rcx
	movl	12(%rsp), %r8d
	movq	%rax, %r9
	leaq	.LC0(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L2:
	.cfi_def_cfa_offset 8
	.cfi_restore 3
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z14__cudaSafeCall9cudaErrorPKci, .-_Z14__cudaSafeCall9cudaErrorPKci
	.text
	.globl	_Z5f_gpudd
	.type	_Z5f_gpudd, @function
_Z5f_gpudd:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2029:
	.size	_Z5f_gpudd, .-_Z5f_gpudd
	.globl	_Z40__device_stub__Z10evolve_gpuPdS_S_S_idddPdS_S_S_iddd
	.type	_Z40__device_stub__Z10evolve_gpuPdS_S_S_idddPdS_S_S_iddd, @function
_Z40__device_stub__Z10evolve_gpuPdS_S_S_idddPdS_S_S_iddd:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movl	%r8d, 28(%rsp)
	movsd	%xmm0, 16(%rsp)
	movsd	%xmm1, 8(%rsp)
	movsd	%xmm2, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	%rsp, %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	80(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z10evolve_gpuPdS_S_S_iddd(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 240
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L10:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z40__device_stub__Z10evolve_gpuPdS_S_S_idddPdS_S_S_iddd, .-_Z40__device_stub__Z10evolve_gpuPdS_S_S_idddPdS_S_S_iddd
	.globl	_Z10evolve_gpuPdS_S_S_iddd
	.type	_Z10evolve_gpuPdS_S_S_iddd, @function
_Z10evolve_gpuPdS_S_S_iddd:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z10evolve_gpuPdS_S_S_idddPdS_S_S_iddd
	.cfi_endproc
.LFE2056:
	.size	_Z10evolve_gpuPdS_S_S_iddd, .-_Z10evolve_gpuPdS_S_S_iddd
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/unique-cloud/Lake-Surface-Wave-Simulation/master/cuda/lakegpu.cu"
.LC4:
	.string	"GPU computation: %f msec\n"
	.text
	.globl	_Z7run_gpuPdS_S_S_iddi
	.type	_Z7run_gpuPdS_S_S_iddi, @function
_Z7run_gpuPdS_S_S_iddi:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rsi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rdx, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rcx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdi, %r12
	xorl	%edi, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%r8d, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	leaq	.LC1(%rip), %rbx
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	movl	%r9d, 28(%rsp)
	movsd	%xmm0, 8(%rsp)
	movsd	%xmm1, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	call	cudaSetDevice@PLT
	movl	$92, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	movl	$93, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	leaq	48(%rsp), %rdi
	call	cudaEventCreate@PLT
	movl	$94, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	movslq	%ebp, %rax
	leaq	56(%rsp), %rdi
	imulq	%rax, %rax
	salq	$3, %rax
	movq	%rax, %rsi
	movq	%rax, (%rsp)
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	leaq	64(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	leaq	72(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	leaq	80(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdx
	movq	64(%rsp), %rdi
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	56(%rsp), %rdi
	movq	%r14, %rsi
	movl	$1, %ecx
	leaq	88(%rsp), %r14
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	80(%rsp), %rdi
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	28(%rsp), %r9d
	movl	%ebp, %eax
	xorl	%esi, %esi
	cltd
	movsd	8(%rsp), %xmm3
	movq	40(%rsp), %rdi
	movq	$0x000000000, 88(%rsp)
	idivl	%r9d
	movl	%r9d, 108(%rsp)
	movl	%r9d, 112(%rsp)
	movl	$1, 104(%rsp)
	movl	$1, 116(%rsp)
	mulsd	.LC3(%rip), %xmm3
	movq	%xmm3, %r13
	movl	%eax, 96(%rsp)
	movl	%eax, 100(%rsp)
	call	cudaEventRecord@PLT
	movl	$114, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
.L17:
	movl	116(%rsp), %ecx
	movq	108(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	96(%rsp), %rdi
	movl	104(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	movsd	88(%rsp), %xmm2
	movsd	8(%rsp), %xmm0
	movq	%r13, %xmm1
	movl	%ebp, %r8d
	movq	80(%rsp), %rcx
	movq	64(%rsp), %rdx
	movq	56(%rsp), %rsi
	movq	72(%rsp), %rdi
	call	_Z40__device_stub__Z10evolve_gpuPdS_S_S_idddPdS_S_S_iddd
.L16:
	movq	(%rsp), %rdx
	movq	56(%rsp), %rsi
	movl	$3, %ecx
	movq	64(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	56(%rsp), %rdi
	movq	(%rsp), %rdx
	movl	$3, %ecx
	movq	72(%rsp), %rsi
	call	cudaMemcpy@PLT
	movsd	16(%rsp), %xmm1
	movq	%r13, %xmm0
	movq	%r14, %rdi
	call	_Z4tpdtPddd@PLT
	testl	%eax, %eax
	jne	.L17
	movq	(%rsp), %rdx
	movq	72(%rsp), %rsi
	movl	$2, %ecx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$131, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	movq	48(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movl	$132, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rsi
	leaq	36(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movl	$133, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	36(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	40(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movl	$139, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	movq	48(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movl	$140, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z14__cudaSafeCall9cudaErrorPKci
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	_Z7run_gpuPdS_S_S_iddi, .-_Z7run_gpuPdS_S_S_iddi
	.section	.rodata.str1.1
.LC5:
	.string	"_Z10evolve_gpuPdS_S_S_iddd"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10evolve_gpuPdS_S_S_iddd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2058:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC3:
	.long	0
	.long	1071644672
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>

#define __DEBUG

#define VSQR 0.1
#define TSCALE 1.0

#define CUDA_CALL(err) __cudaSafeCall(err, __FILE__, __LINE__)
#define CUDA_CHK_ERR() __cudaCheckError(__FILE__, __LINE__)

/**************************************
 * void __cudaSafeCall(cudaError err, const char *file, const int line)
 * void __cudaCheckError(const char *file, const int line)
 *
 * These routines were taken from the GPU Computing SDK
 * (http://developer.nvidia.com/gpu-computing-sdk) include file "cutil.h"
 **************************************/
inline void __cudaSafeCall(hipError_t err, const char* file, const int line) {
#ifdef __DEBUG

#pragma warning(push)
#pragma warning(disable : 4127) // Prevent warning on do-while(0);
    do {
        if (hipSuccess != err) {
            fprintf(stderr, "cudaSafeCall() failed at %s:%i : %s\n", file, line, hipGetErrorString(err));
            exit(-1);
        }
    } while (0);
#pragma warning(pop)
#endif // __DEBUG
    return;
}

inline void __cudaCheckError(const char* file, const int line) {
#ifdef __DEBUG
#pragma warning(push)
#pragma warning(disable : 4127) // Prevent warning on do-while(0);
    do {
        hipError_t err = hipGetLastError();
        if (hipSuccess != err) {
            fprintf(stderr, "cudaCheckError() failed at %s:%i : %s.\n", file, line, hipGetErrorString(err));
            exit(-1);
        }
        // More careful checking. However, this will affect performance.
        // Comment if not needed.
        /*err = cudaThreadSynchronize();
        if( cudaSuccess != err )
        {
          fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s.\n",
                   file, line, cudaGetErrorString( err ) );
          exit( -1 );
        }*/
    } while (0);
#pragma warning(pop)
#endif // __DEBUG
    return;
}

int tpdt(double* t, double dt, double end_time);
__device__ double f_gpu(double p, double t) { return -expf(-TSCALE * t) * p; }

__global__ void evolve_gpu(double* un, double* uc, double* uo, double* pebbles, int n, double h, double dt, double t)
{
    __shared__ int i, j, idx;

    idx = (blockIdx.y * gridDim.x + blockIdx.x) * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x + threadIdx.x);

    i = idx / n;
    j = idx % n;

    if (i == 0 || i == n - 1 || j == 0 || j == n - 1)
        un[idx] = 0.;
    else
        un[idx] = 2 * uc[idx] - uo[idx] + VSQR * (dt * dt) * ((uc[idx - 1] + uc[idx + 1] + uc[idx + n] + uc[idx - n] + 0.25 * (uc[idx - 1 - n] + uc[idx - 1 + n] + uc[idx + 1 - n] + uc[idx + 1 + n]) - 5 * uc[idx]) / (h * h) + f_gpu(pebbles[idx], t));
}

void run_gpu(double* u, double* u0, double* u1, double* pebbles, int n, double h, double end_time, int nthreads) {
    hipEvent_t kstart, kstop;
    float ktime;

    /* HW2: Define your local variables here */
    // declare the variables
    double* gpu_uc;
    double* gpu_uo;
    double* gpu_un;
    double* gpu_pebbles;

    /* Set up device timers */
    CUDA_CALL(hipSetDevice(0));
    CUDA_CALL(hipEventCreate(&kstart));
    CUDA_CALL(hipEventCreate(&kstop));

    /* HW2: Add CUDA kernel call preperation code here */
    // malloc mem on GPU and copy the content
    hipMalloc((void**)&gpu_uc, sizeof(double) * n * n);
    hipMalloc((void**)&gpu_uo, sizeof(double) * n * n);
    hipMalloc((void**)&gpu_un, sizeof(double) * n * n);
    hipMalloc((void**)&gpu_pebbles, sizeof(double) * n * n);
    hipMemcpy((void*)gpu_uo, (void*)u0, sizeof(double) * n * n, hipMemcpyHostToDevice);
    hipMemcpy((void*)gpu_uc, (void*)u1, sizeof(double) * n * n, hipMemcpyHostToDevice);
    hipMemcpy((void*)gpu_pebbles, (void*)pebbles, sizeof(double) * n * n, hipMemcpyHostToDevice);
    double t = 0., dt = h / 2.;

    int grid_size = n / nthreads;
    int block_size = nthreads;

    dim3 grid(grid_size, grid_size);
    dim3 block(block_size, block_size);

    /* Start GPU computation timer */
    CUDA_CALL(hipEventRecord(kstart, 0));

    /* HW2: Add main lake simulation loop here */
    // do the calculation
    while (1) {
        evolve_gpu<<<grid, block>>>(gpu_un, gpu_uc, gpu_uo, gpu_pebbles, n, h, dt, t);

        hipMemcpy((void*)gpu_uo, (void*)gpu_uc, sizeof(double) * n * n, hipMemcpyDeviceToDevice);
        hipMemcpy((void*)gpu_uc, (void*)gpu_un, sizeof(double) * n * n, hipMemcpyDeviceToDevice);

        if (!tpdt(&t, dt, end_time))
            break;
    }
    
    hipMemcpy((void*)u, (void*)gpu_un, sizeof(double) * n * n, hipMemcpyDeviceToHost);

    /* Stop GPU computation timer */
    CUDA_CALL(hipEventRecord(kstop, 0));
    CUDA_CALL(hipEventSynchronize(kstop));
    CUDA_CALL(hipEventElapsedTime(&ktime, kstart, kstop));
    printf("GPU computation: %f msec\n", ktime);

    /* HW2: Add post CUDA kernel call processing and cleanup here */

    /* timer cleanup */
    CUDA_CALL(hipEventDestroy(kstart));
    CUDA_CALL(hipEventDestroy(kstop));
}

	.text
	.file	"lakegpu.hip"
	.globl	_Z25__device_stub__evolve_gpuPdS_S_S_iddd # -- Begin function _Z25__device_stub__evolve_gpuPdS_S_S_iddd
	.type	_Z25__device_stub__evolve_gpuPdS_S_S_iddd,@function
_Z25__device_stub__evolve_gpuPdS_S_S_iddd: # @_Z25__device_stub__evolve_gpuPdS_S_S_iddd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	40(%rsp), %r8
	movsd	%xmm0, (%r8)
	leaq	32(%rsp), %r9
	movsd	%xmm1, (%r9)
	leaq	24(%rsp), %r10
	movsd	%xmm2, (%r10)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	movq	%r10, 56(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10evolve_gpuPdS_S_S_iddd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__evolve_gpuPdS_S_S_iddd, .Lfunc_end0-_Z25__device_stub__evolve_gpuPdS_S_S_iddd
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z7run_gpuPdS_S_S_iddi
.LCPI1_0:
	.quad	0x3fe0000000000000              # double 0.5
	.text
	.globl	_Z7run_gpuPdS_S_S_iddi
	.type	_Z7run_gpuPdS_S_S_iddi,@function
_Z7run_gpuPdS_S_S_iddi:                 # @_Z7run_gpuPdS_S_S_iddi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %ebp
	movsd	%xmm1, 88(%rsp)                 # 8-byte Spill
	movsd	%xmm0, 48(%rsp)                 # 8-byte Spill
	movl	%r8d, %ebx
	movq	%rcx, %r15
	movq	%rdx, %r12
	movq	%rsi, %r13
	movq	%rdi, %r14
	xorl	%edi, %edi
	callq	hipSetDevice
	testl	%eax, %eax
	jne	.LBB1_1
# %bb.3:                                # %_Z14__cudaSafeCall10hipError_tPKci.exit
	leaq	32(%rsp), %rdi
	callq	hipEventCreate
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.5:                                # %_Z14__cudaSafeCall10hipError_tPKci.exit44
	movq	%r12, 80(%rsp)                  # 8-byte Spill
	movq	%r15, (%rsp)                    # 8-byte Spill
	movl	%ebp, 40(%rsp)                  # 4-byte Spill
	movq	%r14, 72(%rsp)                  # 8-byte Spill
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.7:                                # %_Z14__cudaSafeCall10hipError_tPKci.exit46
	movslq	%ebx, %r12
	movq	%r12, %r15
	imulq	%r12, %r15
	shlq	$3, %r15
	leaq	8(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	leaq	64(%rsp), %rbp
	movq	%rbp, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	leaq	96(%rsp), %r14
	movq	%r14, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%rbp), %rdi
	movq	%r13, %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rax
	movq	(%rax), %rdi
	movq	80(%rsp), %rsi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r14), %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	$0, 56(%rsp)
	movl	%r12d, %eax
	cltd
	movl	40(%rsp), %ebp                  # 4-byte Reload
	idivl	%ebp
	movl	%eax, %r14d
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	testl	%eax, %eax
	jne	.LBB1_23
# %bb.8:
	movsd	.LCPI1_0(%rip), %xmm0           # xmm0 = mem[0],zero
	mulsd	48(%rsp), %xmm0                 # 8-byte Folded Reload
	movsd	%xmm0, (%rsp)                   # 8-byte Spill
	movq	%r14, %r12
	shlq	$32, %r12
	orq	%r14, %r12
	movl	%ebp, %eax
	movq	%rax, %r13
	shlq	$32, %r13
	orq	%rax, %r13
	leaq	56(%rsp), %r14
.LBB1_9:                                # %_Z14__cudaSafeCall10hipError_tPKci.exit48
                                        # =>This Inner Loop Header: Depth=1
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_11
# %bb.10:                               #   in Loop: Header=BB1_9 Depth=1
	movq	24(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	64(%rsp), %rdx
	movq	96(%rsp), %rcx
	movsd	56(%rsp), %xmm2                 # xmm2 = mem[0],zero
	movl	%ebx, %r8d
	movsd	48(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	movsd	(%rsp), %xmm1                   # 8-byte Reload
                                        # xmm1 = mem[0],zero
	callq	_Z25__device_stub__evolve_gpuPdS_S_S_iddd
.LBB1_11:                               #   in Loop: Header=BB1_9 Depth=1
	movq	64(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	%r15, %rdx
	movl	$3, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	%r15, %rdx
	movl	$3, %ecx
	callq	hipMemcpy
	movq	%r14, %rdi
	movsd	(%rsp), %xmm0                   # 8-byte Reload
                                        # xmm0 = mem[0],zero
	movsd	88(%rsp), %xmm1                 # 8-byte Reload
                                        # xmm1 = mem[0],zero
	callq	_Z4tpdtPddd
	testl	%eax, %eax
	jne	.LBB1_9
# %bb.12:
	movq	24(%rsp), %rsi
	movq	72(%rsp), %rdi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	testl	%eax, %eax
	jne	.LBB1_13
# %bb.14:                               # %_Z14__cudaSafeCall10hipError_tPKci.exit50
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	testl	%eax, %eax
	jne	.LBB1_15
# %bb.16:                               # %_Z14__cudaSafeCall10hipError_tPKci.exit52
	movq	32(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	44(%rsp), %rdi
	callq	hipEventElapsedTime
	testl	%eax, %eax
	jne	.LBB1_17
# %bb.18:                               # %_Z14__cudaSafeCall10hipError_tPKci.exit54
	xorps	%xmm0, %xmm0
	cvtss2sd	44(%rsp), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	movq	32(%rsp), %rdi
	callq	hipEventDestroy
	testl	%eax, %eax
	jne	.LBB1_19
# %bb.20:                               # %_Z14__cudaSafeCall10hipError_tPKci.exit56
	movq	16(%rsp), %rdi
	callq	hipEventDestroy
	testl	%eax, %eax
	jne	.LBB1_21
# %bb.22:                               # %_Z14__cudaSafeCall10hipError_tPKci.exit58
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_1:
	.cfi_def_cfa_offset 160
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.2, %esi
	movl	$.L.str, %edx
	movq	%rbx, %rdi
	movl	$92, %ecx
	jmp	.LBB1_2
.LBB1_4:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.2, %esi
	movl	$.L.str, %edx
	movq	%rbx, %rdi
	movl	$93, %ecx
	jmp	.LBB1_2
.LBB1_6:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.2, %esi
	movl	$.L.str, %edx
	movq	%rbx, %rdi
	movl	$94, %ecx
	jmp	.LBB1_2
.LBB1_23:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.2, %esi
	movl	$.L.str, %edx
	movq	%rbx, %rdi
	movl	$114, %ecx
	jmp	.LBB1_2
.LBB1_13:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.2, %esi
	movl	$.L.str, %edx
	movq	%rbx, %rdi
	movl	$131, %ecx
	jmp	.LBB1_2
.LBB1_15:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.2, %esi
	movl	$.L.str, %edx
	movq	%rbx, %rdi
	movl	$132, %ecx
	jmp	.LBB1_2
.LBB1_17:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.2, %esi
	movl	$.L.str, %edx
	movq	%rbx, %rdi
	movl	$133, %ecx
	jmp	.LBB1_2
.LBB1_19:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.2, %esi
	movl	$.L.str, %edx
	movq	%rbx, %rdi
	movl	$139, %ecx
	jmp	.LBB1_2
.LBB1_21:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.2, %esi
	movl	$.L.str, %edx
	movq	%rbx, %rdi
	movl	$140, %ecx
.LBB1_2:
	movq	%rax, %r8
	xorl	%eax, %eax
	callq	fprintf
	movl	$-1, %edi
	callq	exit
.Lfunc_end1:
	.size	_Z7run_gpuPdS_S_S_iddi, .Lfunc_end1-_Z7run_gpuPdS_S_S_iddi
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10evolve_gpuPdS_S_S_iddd, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10evolve_gpuPdS_S_S_iddd,@object # @_Z10evolve_gpuPdS_S_S_iddd
	.section	.rodata,"a",@progbits
	.globl	_Z10evolve_gpuPdS_S_S_iddd
	.p2align	3, 0x0
_Z10evolve_gpuPdS_S_S_iddd:
	.quad	_Z25__device_stub__evolve_gpuPdS_S_S_iddd
	.size	_Z10evolve_gpuPdS_S_S_iddd, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/unique-cloud/Lake-Surface-Wave-Simulation/master/cuda/lakegpu.hip"
	.size	.L.str, 128

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"GPU computation: %f msec\n"
	.size	.L.str.1, 26

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"cudaSafeCall() failed at %s:%i : %s\n"
	.size	.L.str.2, 37

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10evolve_gpuPdS_S_S_iddd"
	.size	.L__unnamed_1, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__evolve_gpuPdS_S_S_iddd
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10evolve_gpuPdS_S_S_iddd
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10evolve_gpuPdS_S_S_iddd ; -- Begin function _Z10evolve_gpuPdS_S_S_iddd
	.globl	_Z10evolve_gpuPdS_S_S_iddd
	.p2align	8
	.type	_Z10evolve_gpuPdS_S_S_iddd,@function
_Z10evolve_gpuPdS_S_S_iddd:             ; @_Z10evolve_gpuPdS_S_S_iddd
; %bb.0:
	s_clause 0x2
	s_load_b32 s12, s[0:1], 0x20
	s_load_b32 s2, s[0:1], 0x40
	s_load_b32 s3, s[0:1], 0x4c
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s13, s12, 31
	s_mul_i32 s2, s2, s15
	s_add_i32 s4, s12, s13
	s_lshr_b32 s5, s3, 16
	s_xor_b32 s4, s4, s13
	s_add_i32 s2, s2, s14
	v_cvt_f32_u32_e32 v1, s4
	s_mov_b32 s15, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v4, v1
	v_bfe_u32 v1, v0, 10, 10
	v_mad_u64_u32 v[2:3], null, s2, s5, v[1:2]
	v_and_b32_e32 v3, 0x3ff, v0
	s_and_b32 s2, s3, 0xffff
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v4, v1
	v_mad_u64_u32 v[0:1], null, v2, s2, v[3:4]
	s_sub_i32 s2, 0, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, s2, v4
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v2, v4, v2
	v_add_nc_u32_e32 v3, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v3, v3, v1
	v_add_nc_u32_e32 v2, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v3, v2
	v_mul_lo_u32 v4, v2, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v4
	v_subrev_nc_u32_e32 v5, s4, v3
	v_cmp_le_u32_e32 vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_add_nc_u32 v4, 1, v2
	v_cndmask_b32_e32 v2, v2, v4, vcc_lo
	v_xor_b32_e32 v5, s13, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s4, v3
	v_add_nc_u32_e32 v4, 1, v2
	s_load_b256 s[4:11], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, v2, v4, vcc_lo
	v_xor_b32_e32 v2, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v2, v5
                                        ; implicit-def: $vgpr2_vgpr3
	v_cmp_eq_u32_e64 s14, 0, v4
	v_cmpx_ne_u32_e32 0, v4
	s_cbranch_execz .LBB0_4
; %bb.1:
	v_mul_lo_u32 v2, v4, s12
	s_add_i32 s3, s12, -1
	s_mov_b32 s16, -1
	v_cmp_ne_u32_e32 vcc_lo, s3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v0, v2
	v_cmp_ne_u32_e64 s2, 0, v2
	v_cmp_ne_u32_e64 s3, s3, v2
                                        ; implicit-def: $vgpr2_vgpr3
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB0_3
; %bb.2:
	v_subrev_nc_u32_e32 v2, s12, v0
	v_lshlrev_b64 v[14:15], 3, v[0:1]
	s_lshl_b64 s[12:13], s[12:13], 3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v2
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s6, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v15, vcc_lo
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v16, vcc_lo, v4, s12
	v_add_co_ci_u32_e32 v17, vcc_lo, s13, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v18, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v19, vcc_lo, s7, v3, vcc_lo
	s_clause 0x5
	global_load_b64 v[20:21], v[4:5], off offset:8
	global_load_b128 v[2:5], v[4:5], off offset:-8
	global_load_b128 v[6:9], v[16:17], off offset:-8
	global_load_b128 v[10:13], v[18:19], off offset:-8
	global_load_b64 v[18:19], v[18:19], off offset:8
	global_load_b64 v[16:17], v[16:17], off offset:8
	s_clause 0x1
	s_load_b128 s[16:19], s[0:1], 0x28
	s_load_b64 s[0:1], s[0:1], 0x38
	s_waitcnt vmcnt(4)
	v_add_f64 v[2:3], v[2:3], v[20:21]
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_f64_e64 v20, -s[0:1]
	s_waitcnt vmcnt(2)
	v_add_f64 v[6:7], v[10:11], v[6:7]
	s_mov_b32 s0, 0x9999999a
	s_mov_b32 s1, 0x3fb99999
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[2:3], v[2:3], v[8:9]
	s_waitcnt vmcnt(1)
	v_add_f64 v[6:7], v[6:7], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[2:3], v[2:3], v[12:13]
	v_add_co_u32 v12, vcc_lo, s8, v14
	s_waitcnt vmcnt(0)
	v_add_f64 v[6:7], v[6:7], v[16:17]
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v15, vcc_lo
	v_add_co_u32 v14, vcc_lo, s10, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s11, v15, vcc_lo
	global_load_b64 v[12:13], v[12:13], off
	global_load_b64 v[14:15], v[14:15], off
	v_fma_f64 v[2:3], 0x3fd00000, v[6:7], v[2:3]
	v_mul_f64 v[6:7], s[16:17], s[16:17]
	s_xor_b32 s16, exec_lo, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], 0xc0140000, v[4:5], v[2:3]
	v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], v[2:3]
	v_div_scale_f64 v[18:19], vcc_lo, v[2:3], v[6:7], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[10:11], v[8:9]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[8:9], v[10:11], 1.0
	v_fma_f64 v[10:11], v[10:11], v[16:17], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], -v[8:9], v[10:11], 1.0
	v_fma_f64 v[10:11], v[10:11], v[16:17], v[10:11]
	s_waitcnt vmcnt(1)
	v_fma_f64 v[4:5], v[4:5], 2.0, -v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[16:17], v[18:19], v[10:11]
	v_fma_f64 v[8:9], -v[8:9], v[16:17], v[18:19]
	v_mul_f32_e32 v18, 0x3fb8aa3b, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v19, 0x3fb8aa3b, v20, -v18
	v_rndne_f32_e32 v21, v18
	v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmamk_f32 v10, v20, 0x32a5705f, v19 :: v_dual_sub_f32 v11, v18, v21
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v20
	v_add_f32_e32 v10, v11, v10
	v_cvt_i32_f32_e32 v11, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v10, v10
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v10, v10, v11
	v_cndmask_b32_e32 v10, 0, v10, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v16, 0x7f800000, v10, vcc_lo
	v_mul_f64 v[10:11], s[18:19], s[18:19]
	v_div_fixup_f64 v[2:3], v[8:9], v[6:7], v[2:3]
	v_cvt_f64_f32_e32 v[6:7], v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[8:9], v[10:11], s[0:1]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[2:3], -v[14:15], v[6:7], v[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[2:3], v[8:9], v[2:3], v[4:5]
.LBB0_3:                                ; %Flow64
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s14, exec_lo
	s_and_b32 s1, s16, exec_lo
	s_or_b32 s14, s0, s1
.LBB0_4:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s15
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s0, s14
; %bb.5:
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
; %bb.6:
	s_or_b32 exec_lo, exec_lo, s0
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10evolve_gpuPdS_S_S_iddd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10evolve_gpuPdS_S_S_iddd, .Lfunc_end0-_Z10evolve_gpuPdS_S_S_iddd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1056
; NumSgprs: 22
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           8
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10evolve_gpuPdS_S_S_iddd
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z10evolve_gpuPdS_S_S_iddd.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
