#include "includes.h"
const int  Nthreads = 1024,  NrankMax = 3, nt0max = 71, NchanMax = 1024;

//////////////////////////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void getW(const double *Params, double *wtw, double *W){

int Nfilt, nt0, tid, bid, i, t, Nrank,k, tmax;
double x, x0, xmax;
volatile __shared__ double sW[nt0max*NrankMax], swtw[nt0max*nt0max], xN[1];

nt0       = (int) Params[4];
Nrank       = (int) Params[6];
Nfilt    	=   (int) Params[1];
tmax = (int) Params[11];

tid 		= threadIdx.x;
bid 		= blockIdx.x;

for (k=0;k<nt0;k++)
swtw[tid + k*nt0] = wtw[tid + k*nt0 + bid * nt0 * nt0];
for (k=0;k<Nrank;k++)
sW[tid + k*nt0] = W[tid + bid * nt0  + k * nt0*Nfilt];
__syncthreads();


// for each svd
for(k=0;k<Nrank;k++){
for (i=0;i<100;i++){
// compute projection of wtw
x = 0.0f;
for (t=0;t<nt0;t++)
x+= swtw[tid + t*nt0] * sW[t + k*nt0];

__syncthreads();
if (i<99){
sW[tid + k*nt0] = x;
__syncthreads();

if (tid==0){
x0 = 0.00001f;
for(t=0;t<nt0;t++)
x0+= sW[t + k*nt0] * sW[t + k*nt0];
xN[0] = sqrt(x0);
}
__syncthreads();

sW[tid + k*nt0] = x/xN[0];
__syncthreads();
}
}

// now subtract off this svd from wtw
for (t=0;t<nt0;t++)
swtw[tid + t*nt0] -= sW[t+k*nt0] * x;

__syncthreads();
}


xmax = sW[tmax];
__syncthreads();

sW[tid] = - sW[tid] * copysign(1.0, xmax);

// now write W back
for (k=0;k<Nrank;k++)
W[tid + bid * nt0  + k * nt0*Nfilt] = sW[tid + k*nt0];

}
	.file	"tmpxft_002dd1b3_00000000-6_getW.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z29__device_stub__Z4getWPKdPdS1_PKdPdS1_
	.type	_Z29__device_stub__Z4getWPKdPdS1_PKdPdS1_, @function
_Z29__device_stub__Z4getWPKdPdS1_PKdPdS1_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z4getWPKdPdS1_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z29__device_stub__Z4getWPKdPdS1_PKdPdS1_, .-_Z29__device_stub__Z4getWPKdPdS1_PKdPdS1_
	.globl	_Z4getWPKdPdS1_
	.type	_Z4getWPKdPdS1_, @function
_Z4getWPKdPdS1_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z4getWPKdPdS1_PKdPdS1_
	.cfi_endproc
.LFE2033:
	.size	_Z4getWPKdPdS1_, .-_Z4getWPKdPdS1_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z4getWPKdPdS1_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z4getWPKdPdS1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
const int  Nthreads = 1024,  NrankMax = 3, nt0max = 71, NchanMax = 1024;

//////////////////////////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void getW(const double *Params, double *wtw, double *W){

int Nfilt, nt0, tid, bid, i, t, Nrank,k, tmax;
double x, x0, xmax;
volatile __shared__ double sW[nt0max*NrankMax], swtw[nt0max*nt0max], xN[1];

nt0       = (int) Params[4];
Nrank       = (int) Params[6];
Nfilt    	=   (int) Params[1];
tmax = (int) Params[11];

tid 		= threadIdx.x;
bid 		= blockIdx.x;

for (k=0;k<nt0;k++)
swtw[tid + k*nt0] = wtw[tid + k*nt0 + bid * nt0 * nt0];
for (k=0;k<Nrank;k++)
sW[tid + k*nt0] = W[tid + bid * nt0  + k * nt0*Nfilt];
__syncthreads();


// for each svd
for(k=0;k<Nrank;k++){
for (i=0;i<100;i++){
// compute projection of wtw
x = 0.0f;
for (t=0;t<nt0;t++)
x+= swtw[tid + t*nt0] * sW[t + k*nt0];

__syncthreads();
if (i<99){
sW[tid + k*nt0] = x;
__syncthreads();

if (tid==0){
x0 = 0.00001f;
for(t=0;t<nt0;t++)
x0+= sW[t + k*nt0] * sW[t + k*nt0];
xN[0] = sqrt(x0);
}
__syncthreads();

sW[tid + k*nt0] = x/xN[0];
__syncthreads();
}
}

// now subtract off this svd from wtw
for (t=0;t<nt0;t++)
swtw[tid + t*nt0] -= sW[t+k*nt0] * x;

__syncthreads();
}


xmax = sW[tmax];
__syncthreads();

sW[tid] = - sW[tid] * copysign(1.0, xmax);

// now write W back
for (k=0;k<Nrank;k++)
W[tid + bid * nt0  + k * nt0*Nfilt] = sW[tid + k*nt0];

}
	.text
	.file	"getW.hip"
	.globl	_Z19__device_stub__getWPKdPdS1_ # -- Begin function _Z19__device_stub__getWPKdPdS1_
	.type	_Z19__device_stub__getWPKdPdS1_,@function
_Z19__device_stub__getWPKdPdS1_:        # @_Z19__device_stub__getWPKdPdS1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4getWPKdPdS1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z19__device_stub__getWPKdPdS1_, .Lfunc_end0-_Z19__device_stub__getWPKdPdS1_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4getWPKdPdS1_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z4getWPKdPdS1_,@object         # @_Z4getWPKdPdS1_
	.section	.rodata,"a",@progbits
	.globl	_Z4getWPKdPdS1_
	.p2align	3, 0x0
_Z4getWPKdPdS1_:
	.quad	_Z19__device_stub__getWPKdPdS1_
	.size	_Z4getWPKdPdS1_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z4getWPKdPdS1_"
	.size	.L__unnamed_1, 16

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z19__device_stub__getWPKdPdS1_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z4getWPKdPdS1_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z4getWPKdPdS1_         ; -- Begin function _Z4getWPKdPdS1_
	.globl	_Z4getWPKdPdS1_
	.p2align	8
	.type	_Z4getWPKdPdS1_,@function
_Z4getWPKdPdS1_:                        ; @_Z4getWPKdPdS1_
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_lshlrev_b32_e32 v11, 3, v0
	s_waitcnt lgkmcnt(0)
	s_clause 0x3
	s_load_b64 s[0:1], s[4:5], 0x20
	s_load_b64 s[10:11], s[4:5], 0x30
	s_load_b64 s[8:9], s[4:5], 0x58
	s_load_b64 s[12:13], s[4:5], 0x8
	s_waitcnt lgkmcnt(0)
	v_cvt_i32_f64_e32 v1, s[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, 1, v1
	v_readfirstlane_b32 s4, v1
	v_cmp_lt_i32_e64 s0, 0, v1
	s_cbranch_vccnz .LBB0_3
; %bb.1:                                ; %.lr.ph
	s_delay_alu instid0(VALU_DEP_2)
	s_mul_i32 s1, s15, s4
	v_lshlrev_b32_e32 v3, 3, v0
	v_mad_u64_u32 v[1:2], null, s1, s4, v[0:1]
	s_ashr_i32 s5, s4, 31
	s_lshl_b32 s14, s4, 3
	s_mov_b64 s[16:17], src_shared_base
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	s_lshl_b64 s[6:7], s[4:5], 3
	s_mov_b32 s5, s4
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[4:5], v[1:2], off
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_add_co_u32 v1, s1, v1, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v2, s1, s7, v2, s1
	v_cndmask_b32_e64 v7, 0, s17, vcc_lo
	v_cndmask_b32_e32 v6, 0, v3, vcc_lo
	v_add_nc_u32_e32 v3, s14, v3
	s_add_i32 s5, s5, -1
	s_cmp_eq_u32 s5, 0
	s_waitcnt vmcnt(0)
	flat_store_b64 v[6:7], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
	s_cbranch_scc0 .LBB0_2
.LBB0_3:                                ; %.preheader109
	v_cvt_i32_f64_e32 v2, s[12:13]
	v_cvt_i32_f64_e32 v1, s[10:11]
	v_lshl_add_u32 v10, v0, 3, 0x9d90
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v9, s4, v2
	v_cmp_gt_i32_e32 vcc_lo, 1, v1
	v_readfirstlane_b32 s5, v1
	v_cmp_lt_i32_e64 s1, 0, v1
	s_cbranch_vccnz .LBB0_6
; %bb.4:                                ; %.lr.ph112
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_lshl_add_u32 v3, v0, 3, 0x9d90
	s_mov_b64 s[6:7], src_shared_base
	s_lshl_b32 s10, s4, 3
	s_mov_b32 s6, s5
.LBB0_5:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s6, s6, -1
	s_cmp_lg_u32 s6, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 3, v[1:2]
	v_add_nc_u32_e32 v1, v1, v9
	v_add_co_u32 v4, vcc_lo, s2, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	global_load_b64 v[4:5], v[4:5], off
	v_cndmask_b32_e64 v7, 0, s7, vcc_lo
	v_cndmask_b32_e32 v6, 0, v3, vcc_lo
	v_add_nc_u32_e32 v3, s10, v3
	s_waitcnt vmcnt(0)
	flat_store_b64 v[6:7], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
	s_cbranch_scc1 .LBB0_5
.LBB0_6:                                ; %._crit_edge
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v12, 0, 1, s1
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB0_23
; %bb.7:                                ; %.preheader108.lr.ph
	s_mov_b64 s[6:7], src_shared_base
	v_cmp_eq_u32_e64 s1, 0, v0
	v_dual_mov_b32 v2, s7 :: v_dual_mov_b32 v1, 0x9d88
	s_brev_b32 s10, 1
	s_mov_b32 s11, 0x3ee4f8b5
	s_mov_b32 s6, 0
	s_lshl_b32 s12, s4, 3
	s_mov_b32 s13, 0x9d90
.LBB0_8:                                ; %.preheader108
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_9 Depth 2
                                        ;       Child Loop BB0_11 Depth 3
                                        ;       Child Loop BB0_16 Depth 3
                                        ;     Child Loop BB0_21 Depth 2
	v_mad_u64_u32 v[3:4], null, s6, s4, v[0:1]
	s_mov_b32 s14, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v3, v3, 3, 0x9d90
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v5, 0, v3, vcc_lo
	v_cndmask_b32_e64 v6, 0, s7, vcc_lo
.LBB0_9:                                ; %.preheader106
                                        ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_11 Depth 3
                                        ;       Child Loop BB0_16 Depth 3
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_12
; %bb.10:                               ; %.lr.ph115.preheader
                                        ;   in Loop: Header=BB0_9 Depth=2
	v_mov_b32_e32 v7, v11
	s_mov_b32 s16, s13
	s_mov_b32 s17, s4
.LBB0_11:                               ; %.lr.ph115
                                        ;   Parent Loop BB0_8 Depth=1
                                        ;     Parent Loop BB0_9 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v7
	s_cmp_lg_u32 s16, -1
	s_cselect_b32 s18, s16, 0
	s_cselect_b32 s19, s7, 0
	v_cndmask_b32_e64 v14, 0, s7, vcc_lo
	v_cndmask_b32_e32 v13, 0, v7, vcc_lo
	v_dual_mov_b32 v15, s18 :: v_dual_mov_b32 v16, s19
	v_add_nc_u32_e32 v7, s12, v7
	flat_load_b64 v[13:14], v[13:14] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b64 v[15:16], v[15:16] glc dlc
	s_waitcnt vmcnt(0)
	s_add_i32 s17, s17, -1
	s_add_i32 s16, s16, 8
	s_cmp_lg_u32 s17, 0
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[3:4], v[13:14], v[15:16], v[3:4]
	s_cbranch_scc1 .LBB0_11
.LBB0_12:                               ; %._crit_edge116
                                        ;   in Loop: Header=BB0_9 Depth=2
	s_cmpk_eq_i32 s14, 0x63
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_19
; %bb.13:                               ;   in Loop: Header=BB0_9 Depth=2
	flat_store_b64 v[5:6], v[3:4] dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s16, s1
	s_cbranch_execz .LBB0_18
; %bb.14:                               ; %.preheader
                                        ;   in Loop: Header=BB0_9 Depth=2
	v_dual_mov_b32 v7, s10 :: v_dual_mov_b32 v8, s11
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_17
; %bb.15:                               ; %.lr.ph119.preheader
                                        ;   in Loop: Header=BB0_9 Depth=2
	v_dual_mov_b32 v7, s10 :: v_dual_mov_b32 v8, s11
	s_mov_b32 s17, s13
	s_mov_b32 s18, s4
.LBB0_16:                               ; %.lr.ph119
                                        ;   Parent Loop BB0_8 Depth=1
                                        ;     Parent Loop BB0_9 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_cmp_lg_u32 s17, -1
	s_cselect_b32 s21, s7, 0
	s_cselect_b32 s20, s17, 0
	s_add_i32 s18, s18, -1
	v_dual_mov_b32 v13, s20 :: v_dual_mov_b32 v14, s21
	s_add_i32 s17, s17, 8
	s_cmp_lg_u32 s18, 0
	flat_load_b64 v[15:16], v[13:14] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b64 v[13:14], v[13:14] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[7:8], v[15:16], v[13:14], v[7:8]
	s_cbranch_scc1 .LBB0_16
.LBB0_17:                               ; %._crit_edge120
                                        ;   in Loop: Header=BB0_9 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[7:8]
	v_cndmask_b32_e64 v13, 0, 1, vcc_lo
	v_lshlrev_b32_e32 v13, 8, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[7:8], v[7:8], v13
	v_rsq_f64_e32 v[13:14], v[7:8]
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[15:16], v[7:8], v[13:14]
	v_mul_f64 v[13:14], v[13:14], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], -v[13:14], v[15:16], 0.5
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	v_fma_f64 v[13:14], v[13:14], v[17:18], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], -v[15:16], v[15:16], v[7:8]
	v_fma_f64 v[15:16], v[17:18], v[13:14], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], -v[15:16], v[15:16], v[7:8]
	v_fma_f64 v[13:14], v[17:18], v[13:14], v[15:16]
	v_cndmask_b32_e64 v15, 0, 0xffffff80, vcc_lo
	v_cmp_class_f64_e64 vcc_lo, v[7:8], 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[13:14], v[13:14], v15
	v_dual_cndmask_b32 v8, v14, v8 :: v_dual_cndmask_b32 v7, v13, v7
	flat_store_b64 v[1:2], v[7:8] dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_18:                               ; %Flow195
                                        ;   in Loop: Header=BB0_9 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	flat_load_b64 v[7:8], v[1:2] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_div_scale_f64 v[13:14], null, v[7:8], v[7:8], v[3:4]
	v_div_scale_f64 v[19:20], vcc_lo, v[3:4], v[7:8], v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[15:16], v[13:14]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[17:18], v[19:20], v[15:16]
	v_fma_f64 v[13:14], -v[13:14], v[17:18], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[13:14], v[13:14], v[15:16], v[17:18]
	v_div_fixup_f64 v[7:8], v[13:14], v[7:8], v[3:4]
	flat_store_b64 v[5:6], v[7:8] dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_19:                               ;   in Loop: Header=BB0_9 Depth=2
	s_add_i32 s14, s14, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_eq_i32 s14, 0x64
	s_cbranch_scc0 .LBB0_9
; %bb.20:                               ; %.preheader107
                                        ;   in Loop: Header=BB0_8 Depth=1
	v_mov_b32_e32 v5, v11
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b32 s14, s13
	s_mov_b32 s16, s4
	s_cbranch_vccnz .LBB0_22
.LBB0_21:                               ; %.lr.ph124
                                        ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_cmp_lg_u32 s14, -1
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	s_cselect_b32 s17, s14, 0
	s_cselect_b32 s18, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v13, s17 :: v_dual_mov_b32 v14, s18
	v_cndmask_b32_e64 v7, 0, s7, vcc_lo
	v_cndmask_b32_e32 v6, 0, v5, vcc_lo
	v_add_nc_u32_e32 v5, s12, v5
	flat_load_b64 v[13:14], v[13:14] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b64 v[15:16], v[6:7] glc dlc
	s_waitcnt vmcnt(0)
	s_add_i32 s16, s16, -1
	s_add_i32 s14, s14, 8
	s_cmp_lg_u32 s16, 0
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[13:14], -v[3:4], v[13:14], v[15:16]
	flat_store_b64 v[6:7], v[13:14] dlc
	s_waitcnt_vscnt null, 0x0
	s_cbranch_scc1 .LBB0_21
.LBB0_22:                               ; %._crit_edge125
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_add_i32 s6, s6, 1
	s_add_i32 s13, s13, s12
	s_cmp_lg_u32 s6, s5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_8
.LBB0_23:                               ; %._crit_edge127
	v_cvt_i32_f64_e32 v1, s[8:9]
	v_cmp_ne_u32_e32 vcc_lo, -1, v10
	v_cndmask_b32_e32 v3, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	s_lshl_b32 s0, s0, 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s6, s0, 0x9d90
	s_mov_b64 s[0:1], src_shared_base
	s_cmp_lg_u32 s6, -1
	v_cndmask_b32_e64 v4, 0, s1, vcc_lo
	s_cselect_b32 s0, s6, 0
	s_cselect_b32 s6, s1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s6
	s_mov_b32 s0, 0x3ff00000
	v_cmp_ne_u32_e32 vcc_lo, 1, v12
	flat_load_b64 v[1:2], v[1:2] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	flat_load_b64 v[5:6], v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v1, 0
	s_and_b32 vcc_lo, exec_lo, vcc_lo
	v_bfi_b32 v2, 0x7fffffff, s0, v2
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[1:2], v[1:2], -v[5:6]
	flat_store_b64 v[3:4], v[1:2] dlc
	s_waitcnt_vscnt null, 0x0
	s_cbranch_vccnz .LBB0_26
; %bb.24:                               ; %.lr.ph130
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_lshl_b32 s0, s4, 3
.LBB0_25:                               ; =>This Inner Loop Header: Depth=1
	v_cmp_ne_u32_e32 vcc_lo, -1, v10
	s_add_i32 s5, s5, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s5, 0
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	v_cndmask_b32_e32 v2, 0, v10, vcc_lo
	v_add_nc_u32_e32 v10, s0, v10
	flat_load_b64 v[3:4], v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 3, v[1:2]
	v_add_nc_u32_e32 v1, v1, v9
	v_add_co_u32 v5, vcc_lo, s2, v5
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b64 v[5:6], v[3:4], off
	s_cbranch_scc1 .LBB0_25
.LBB0_26:                               ; %._crit_edge131
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4getWPKdPdS1_
		.amdhsa_group_segment_fixed_size 42040
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z4getWPKdPdS1_, .Lfunc_end0-_Z4getWPKdPdS1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1656
; NumSgprs: 24
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 42040 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 42040
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4getWPKdPdS1_
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z4getWPKdPdS1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     21
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
