<p>As in the topic...</p>

<p>I was thinking about something like "in memory changes".
On recent blogs by Jaroslaw Kowalski i have found similar approach
but i was thinking about sth much simpler  </p>

The best book on this topic is
Reuse Methodology Manual
.  It covers both VHDL and Verilog.
And in particular some issues that don't have an exact match in software:
No latches
Be careful with resets
Check your internal and external timing
Use only synthesizable code
Register your outputs of all modules
Be careful with blocking vs. non-blocking assignments
Be careful with sensitive lists for combinatorial logic (or use @(*) in Verilog)
Some that are the same include
Use CM
Have code reviews
Test (simulate) your code
Reuse code when appropriate
Have an up-to-date schedule
Have a spec or use cases or an Agile customer