<p>I have a "watcher" module that is currently using global hierarchies inside it.  I need to instantiate a second instance of this with a second global hierarchy.</p>

<p>Currently:</p>

<pre><code>module watcher;
wire sig = `HIER.sig;
wire bar = `HIER.foo.bar;
...
endmodule

watcher w; // instantiation
</code></pre>

<p>Desired:</p>

<pre><code>module watcher(input base_hier);
wire sig = base_hier.sig;
wire bar = base_hier.foo.bar;
...
endmodule

watcher w1(`HIER1); // instantiation
watcher w2(`HIER2); // second instantiation, except with a different hierarchy
</code></pre>

<p>My best idea is to use vpp (the Verilog preprocessor) to brute-force generate two virtually-identical modules (one with each hierarchy), but is there a more elegant way?</p>

My preference is to have a single module (or a small number of modules) in your testbench that contains all your probes but no other functionality. All other modules in your testbench that require probes then connect to that "probe module". Use SystemVerilog interfaces in preference to raw wires if that's an option for you. This circumvents your problem since no watcher will require global hierarchies and your testbench on the whole will be considerably easier to maintain. See the
Law of Demeter
.
Alternatively... (but this puts hierarchy in your instantiations...)
```
```
module watcher(sig, bar);
  input sig;
  input bar;
...
endmodule

watcher w1(`HIER1.sig, `HIER1.foo.bar); // instantiation
watcher w2(`HIER2.sig, `HIER2.foo.bar); // second instantiation, except with a different hierarchy
```
```
Subsequently you can also:
```
```
`define WATCHER_INST(NAME, HIER) watcher NAME(HIER.sig, HIER.foo.sig)

`WATCHER_INST(w1, `HIER1);
`WATCHER_INST(w2, `HIER2);
```
```