"D:/Efinity/2023.2/bin/efx_map" --project "Ti60_Demo" --root "example_top" --write-efx-verilog "C:/Users/32954/Desktop/fpga2/finaltry/1051/outflow/Ti60_Demo.map.v" --write-premap-module "C:/Users/32954/Desktop/fpga2/finaltry/1051/outflow/Ti60_Demo.elab.vdb" --binary-db "C:/Users/32954/Desktop/fpga2/finaltry/1051/outflow/Ti60_Demo.vdb" --device "Ti60F225" --family "Titanium" --veri_option "verilog_mode=verilog_2k,vhdl_mode=vhdl_2008" --work-dir "C:/Users/32954/Desktop/fpga2/finaltry/1051/work_syn" --output-dir "C:/Users/32954/Desktop/fpga2/finaltry/1051/outflow" --project-xml "C:/Users/32954/Desktop/fpga2/finaltry/1051/Ti60_Demo.xml" --I "C:/Users/32954/Desktop/fpga2/finaltry/1051" --I "C:/Users/32954/Desktop/fpga2/finaltry/1051/ip/R0_FIFO" --I "C:/Users/32954/Desktop/fpga2/finaltry/1051/ip/DdrCtrl" --I "C:/Users/32954/Desktop/fpga2/finaltry/1051/ip/FIFO_W48R24" --I "C:/Users/32954/Desktop/fpga2/finaltry/1051/ip/W0_FIFO_32" --I "C:/Users/32954/Desktop/fpga2/finaltry/1051/ip/R0_FIFO_32" --I "C:/Users/32954/Desktop/fpga2/finaltry/1051/ip/asyn_fifo" --I "C:/Users/32954/Desktop/fpga2/finaltry/1051/ip/divider_ip" --I "C:/Users/32954/Desktop/fpga2/finaltry/1051/ip/my_bram_ip"