"D:/Efinity/2023.2/bin/efx_map" --project "Bilinear_interpolation_prj" --root "data_in_uart_control_top" --write-efx-verilog "D:/FPGA_Competition/FPGAprojects/data_in_uart_control_new/Bilinear_interpolation_prj/outflow/Bilinear_interpolation_prj.map.v" --write-premap-module "D:/FPGA_Competition/FPGAprojects/data_in_uart_control_new/Bilinear_interpolation_prj/outflow/Bilinear_interpolation_prj.elab.vdb" --binary-db "D:/FPGA_Competition/FPGAprojects/data_in_uart_control_new/Bilinear_interpolation_prj/outflow/Bilinear_interpolation_prj.vdb" --device "Ti60F225" --family "Titanium" --veri_option "verilog_mode=verilog_2k,vhdl_mode=vhdl_2008" --work-dir "D:/FPGA_Competition/FPGAprojects/data_in_uart_control_new/Bilinear_interpolation_prj/work_syn" --output-dir "D:/FPGA_Competition/FPGAprojects/data_in_uart_control_new/Bilinear_interpolation_prj/outflow" --project-xml "D:/FPGA_Competition/FPGAprojects/data_in_uart_control_new/Bilinear_interpolation_prj/Bilinear_interpolation_prj.xml" --I "D:/FPGA_Competition/FPGAprojects/data_in_uart_control_new/Bilinear_interpolation_prj" --I "D:/FPGA_Competition/FPGAprojects/data_in_uart_control_new/Bilinear_interpolation_prj/ip/asyn_fifo" --I "D:/FPGA_Competition/FPGAprojects/data_in_uart_control_new/Bilinear_interpolation_prj/ip/my_bram_ip" --I "D:/FPGA_Competition/FPGAprojects/data_in_uart_control_new/Bilinear_interpolation_prj/ip/divider_ip" --I "D:/FPGA_Competition/FPGAprojects/data_in_uart_control_new/Bilinear_interpolation_prj/ip/data_in_fifo"