#!/bin/bash -f
#*********************************************************************************************************
# Vivado (TM) v2022.2 (64-bit)
#
# Filename    : design_1.sh
# Simulator   : Synopsys Verilog Compiler Simulator
# Description : Simulation script for compiling, elaborating and verifying the project source files.
#               The script will automatically create the design libraries sub-directories in the run
#               directory, add the library logical mappings in the simulator setup file, create default
#               'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Thu Jul 11 12:44:05 +0800 2024
# SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022
#
# Tool Version Limit: 2022.10 
#
# usage: design_1.sh [-help]
# usage: design_1.sh [-lib_map_path]
# usage: design_1.sh [-noclean_files]
# usage: design_1.sh [-reset_run]
#
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
# that points to these libraries and rerun export_simulation. For more information about this switch please
# type 'export_simulation -help' in the Tcl shell.
#
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
# executing this script. Please type 'design_1.sh -help' for more information.
#
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#*********************************************************************************************************

# Directory path for design sources and include directories (if any) wrt this path
ref_dir="."

# Override directory with 'export_sim_ref_dir' env path value if set in the shell
if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
  ref_dir="$export_sim_ref_dir"
fi

# Set vlogan compile options
vlogan_opts="-full64 "

# Set vhdlan compile options
vhdlan_opts="-full64 "

# Set vcs elaboration options
vcs_elab_opts="-full64 -debug_acc+pp+dmptf -t ps -licqueue -l elaborate.log "

# Set vcs simulation options
vcs_sim_opts="-ucli -licqueue -l simulate.log "

# Design libraries
design_libs=(xilinx_vip xpm axi_infrastructure_v1_1_0 axi_vip_v1_1_13 zynq_ultra_ps_e_vip_v1_0_13 xil_defaultlib ahblite_axi_bridge_v3_0_22 xlconstant_v1_1_7 lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 generic_baseblocks_v2_1_0 fifo_generator_v13_2_7 axi_data_fifo_v2_1_26 axi_register_slice_v2_1_27 axi_protocol_converter_v2_1_27)

# Simulation root library directory
sim_lib_dir="vcs_lib"

# Script info
echo -e "design_1.sh - Script generated by export_simulation (Vivado v2022.2 (64-bit)-id)\n"

# Main steps
run()
{
  check_args $# $1
  setup $1 $2
  compile
  elaborate
  simulate
}

# RUN_STEP: <compile>
compile()
{
  vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/abef/hdl" +incdir+"$ref_dir/../../../bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" +incdir+"G:/xilinx/Vivado/2022.2/data/xilinx_vip/include" \
    "G:/xilinx/Vivado/2022.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
    "G:/xilinx/Vivado/2022.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
    "G:/xilinx/Vivado/2022.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
    "G:/xilinx/Vivado/2022.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
    "G:/xilinx/Vivado/2022.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
    "G:/xilinx/Vivado/2022.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
    "G:/xilinx/Vivado/2022.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
    "G:/xilinx/Vivado/2022.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
    "G:/xilinx/Vivado/2022.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
  2>&1 | tee -a vlogan.log

  vlogan -work xpm $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/abef/hdl" +incdir+"$ref_dir/../../../bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" +incdir+"G:/xilinx/Vivado/2022.2/data/xilinx_vip/include" \
    "G:/xilinx/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
    "G:/xilinx/Vivado/2022.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
  2>&1 | tee -a vlogan.log

  vhdlan -work xpm $vhdlan_opts \
    "G:/xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd" \
  2>&1 | tee -a vhdlan.log

  vlogan -work axi_infrastructure_v1_1_0 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/abef/hdl" +incdir+"$ref_dir/../../../bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" +incdir+"G:/xilinx/Vivado/2022.2/data/xilinx_vip/include" \
    "$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work axi_vip_v1_1_13 $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/abef/hdl" +incdir+"$ref_dir/../../../bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" +incdir+"G:/xilinx/Vivado/2022.2/data/xilinx_vip/include" \
    "$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/ffc2/hdl/axi_vip_v1_1_vl_rfs.sv" \
  2>&1 | tee -a vlogan.log

  vlogan -work zynq_ultra_ps_e_vip_v1_0_13 $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/abef/hdl" +incdir+"$ref_dir/../../../bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" +incdir+"G:/xilinx/Vivado/2022.2/data/xilinx_vip/include" \
    "$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/abef/hdl/zynq_ultra_ps_e_vip_v1_0_vl_rfs.sv" \
  2>&1 | tee -a vlogan.log

  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/abef/hdl" +incdir+"$ref_dir/../../../bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" +incdir+"G:/xilinx/Vivado/2022.2/data/xilinx_vip/include" \
    "$ref_dir/../../../bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/sim/design_1_zynq_ultra_ps_e_0_0_vip_wrapper.v" \
  2>&1 | tee -a vlogan.log

  vhdlan -work ahblite_axi_bridge_v3_0_22 $vhdlan_opts \
    "$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/a50c/hdl/ahblite_axi_bridge_v3_0_vh_rfs.vhd" \
  2>&1 | tee -a vhdlan.log

  vhdlan -work xil_defaultlib $vhdlan_opts \
    "$ref_dir/../../../bd/design_1/ip/design_1_ahblite_axi_bridge_0_0/sim/design_1_ahblite_axi_bridge_0_0.vhd" \
    "$ref_dir/../../../bd/design_1/ip/design_1_ahblite_axi_bridge_1_0/sim/design_1_ahblite_axi_bridge_1_0.vhd" \
  2>&1 | tee -a vhdlan.log

  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/abef/hdl" +incdir+"$ref_dir/../../../bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" +incdir+"G:/xilinx/Vivado/2022.2/data/xilinx_vip/include" \
    "$ref_dir/../../../bd/design_1/ipshared/228e/EGRET_CFG_axi.v" \
    "$ref_dir/../../../bd/design_1/ipshared/228e/EGRET_cfg.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_EGRET_cfg_0_0/sim/design_1_EGRET_cfg_0_0.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work xlconstant_v1_1_7 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/abef/hdl" +incdir+"$ref_dir/../../../bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" +incdir+"G:/xilinx/Vivado/2022.2/data/xilinx_vip/include" \
    "$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/badb/hdl/xlconstant_v1_1_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/abef/hdl" +incdir+"$ref_dir/../../../bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" +incdir+"G:/xilinx/Vivado/2022.2/data/xilinx_vip/include" \
    "$ref_dir/../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/common/rtl/BUFGCE.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ahb/ahb.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ahb/ahb_fifo.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ahb/ahb_fifo_counter.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ahb/ahb_fifo_entry.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/apb/apb.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/apb/apb_bridge.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fmau/rtl/booth_code_25_bit.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/iu/rtl/booth_code_33_bit.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/system/cpu_sub_system_ahb.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/system/err_gen.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/system/fpga_clk_gen.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fpga/rtl/fpga_ram.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/clk/rtl/gated_clk_cell.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/gpio/gpio.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/gpio/gpio_apbif.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/gpio/gpio_ctrl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/mem/mem_ctrl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/iu/rtl/multiplier_33x33_partial.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/cpu/rtl/openE906.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/biu/rtl/pa_ahbl_if.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/biu/rtl/pa_ahbl_if_fo.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/bmu/rtl/pa_bmu_bus_if.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/bmu/rtl/pa_bmu_dbus_if.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/bmu/rtl/pa_bmu_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/clic/rtl/pa_clic_arb.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/clic/rtl/pa_clic_arb_32to1_kernel.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/clic/rtl/pa_clic_arb_kernel.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/clic/rtl/pa_clic_busif.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/clic/rtl/pa_clic_cpuif_2cycle.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/clic/rtl/pa_clic_ctrl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/clic/rtl/pa_clic_expand.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/clic/rtl/pa_clic_ff1_onehot.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/clic/rtl/pa_clic_kid.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/clic/rtl/pa_clic_kid_dummy.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/clic/rtl/pa_clic_sel.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/clic/rtl/pa_clic_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/clint/rtl/pa_clint_busif.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/clint/rtl/pa_clint_regs.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/clint/rtl/pa_clint_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/clk/rtl/pa_clk_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/clk/rtl/pa_clkrst_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/cpu/rtl/pa_core.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/cpu/rtl/pa_core_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/cp0/rtl/pa_cp0_ext_csr.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/cp0/rtl/pa_cp0_ext_inst.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/cp0/rtl/pa_cp0_float_csr.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/cp0/rtl/pa_cp0_info_csr.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/cp0/rtl/pa_cp0_iui.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/cp0/rtl/pa_cp0_regs.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/cp0/rtl/pa_cp0_special.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/cp0/rtl/pa_cp0_srst.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/cp0/rtl/pa_cp0_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/cp0/rtl/pa_cp0_trap_csr.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/biu/rtl/pa_dahbl_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/lsu/rtl/pa_dcache_data_array.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/lsu/rtl/pa_dcache_dirty_array.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/lsu/rtl/pa_dcache_tag_array.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/lsu/rtl/pa_dcache_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/dtu/rtl/pa_dtu_cdc.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/dtu/rtl/pa_dtu_cdc_lvl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/dtu/rtl/pa_dtu_cdc_pulse.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/dtu/rtl/pa_dtu_ctrl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/dtu/rtl/pa_dtu_dbginfo.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/dtu/rtl/pa_dtu_m_iie_all.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/dtu/rtl/pa_dtu_mcontrol_0.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/dtu/rtl/pa_dtu_mcontrol_1.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/dtu/rtl/pa_dtu_mcontrol_2.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/dtu/rtl/pa_dtu_mcontrol_output_select.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/dtu/rtl/pa_dtu_pcfifo.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/dtu/rtl/pa_dtu_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/dtu/rtl/pa_dtu_trigger_module.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fpga/rtl/pa_f_spsram_1024x32.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fpga/rtl/pa_f_spsram_2048x32.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fpga/rtl/pa_f_spsram_256x4.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fpga/rtl/pa_f_spsram_256x40.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fpga/rtl/pa_f_spsram_256x41.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fpga/rtl/pa_f_spsram_512x16.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/falu/rtl/pa_fadd_lop_s1_s.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/falu/rtl/pa_fadd_nm_shift_single.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/falu/rtl/pa_fadd_shift_sub_single.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/falu/rtl/pa_fadd_single.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/falu/rtl/pa_falu_ctrl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/falu/rtl/pa_falu_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/falu/rtl/pa_fcnvt_ftoi_s.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/falu/rtl/pa_fcnvt_itof_s.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/falu/rtl/pa_fcnvt_single.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fdsu/rtl/pa_fdsu_ctrl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fdsu/rtl/pa_fdsu_ff1.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fdsu/rtl/pa_fdsu_pack_single.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fdsu/rtl/pa_fdsu_prepare.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fdsu/rtl/pa_fdsu_round_single.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fdsu/rtl/pa_fdsu_special.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fdsu/rtl/pa_fdsu_srt_single.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fdsu/rtl/pa_fdsu_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fmau/rtl/pa_fmau_ctrl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fmau/rtl/pa_fmau_dp.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fmau/rtl/pa_fmau_ex1_special_judge.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fmau/rtl/pa_fmau_frac_add.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fmau/rtl/pa_fmau_frac_mult.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fmau/rtl/pa_fmau_frac_shift.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fmau/rtl/pa_fmau_lza_single.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fmau/rtl/pa_fmau_multiplier_24x24_partial.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fmau/rtl/pa_fmau_src2_shifter_single.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fmau/rtl/pa_fmau_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fpu/rtl/pa_fpu_ctrl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fpu/rtl/pa_fpu_dp.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fpu/rtl/pa_fpu_frbus.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fpu/rtl/pa_fpu_src_type.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/fpu/rtl/pa_fpu_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/falu/rtl/pa_fspu_single.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/pmu/rtl/pa_hpcp_cnt.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/pmu/rtl/pa_hpcp_event.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/pmu/rtl/pa_hpcp_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/biu/rtl/pa_iahbl_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/idu/rtl/pa_idu_ctrl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/idu/rtl/pa_idu_decd_dsp.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/idu/rtl/pa_idu_decd_fp.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/idu/rtl/pa_idu_decd_rv32c.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/idu/rtl/pa_idu_decd_rv32fd.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/idu/rtl/pa_idu_decd_rv32im.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/idu/rtl/pa_idu_decd_rv32x.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/idu/rtl/pa_idu_dp.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/idu/rtl/pa_idu_fpr.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/idu/rtl/pa_idu_gpr.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/idu/rtl/pa_idu_hs.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/idu/rtl/pa_idu_id_fp.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/idu/rtl/pa_idu_reg.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/idu/rtl/pa_idu_reg32.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/idu/rtl/pa_idu_reg32_high.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/idu/rtl/pa_idu_reg_sp.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/idu/rtl/pa_idu_split.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/idu/rtl/pa_idu_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ifu/rtl/pa_ifu_bht.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ifu/rtl/pa_ifu_bht_array.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ifu/rtl/pa_ifu_btb.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ifu/rtl/pa_ifu_btb_entry.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ifu/rtl/pa_ifu_ctrl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ifu/rtl/pa_ifu_ibuf.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ifu/rtl/pa_ifu_ibuf_entry.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ifu/rtl/pa_ifu_ibuf_pop_entry.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ifu/rtl/pa_ifu_icache.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ifu/rtl/pa_ifu_icache_data_array.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ifu/rtl/pa_ifu_icache_tag_array.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ifu/rtl/pa_ifu_id_pred.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ifu/rtl/pa_ifu_ifetch.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ifu/rtl/pa_ifu_ipack.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ifu/rtl/pa_ifu_ipack_entry.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ifu/rtl/pa_ifu_pcgen.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ifu/rtl/pa_ifu_pre_decd.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ifu/rtl/pa_ifu_ras.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ifu/rtl/pa_ifu_ras_entry.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ifu/rtl/pa_ifu_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ifu/rtl/pa_ifu_vec.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/iu/rtl/pa_iu_addr_gen.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/iu/rtl/pa_iu_alu.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/iu/rtl/pa_iu_bju.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/iu/rtl/pa_iu_ctrl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/iu/rtl/pa_iu_div.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/iu/rtl/pa_iu_div_shift2_kernel.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/iu/rtl/pa_iu_mul.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/iu/rtl/pa_iu_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/lsu/rtl/pa_lsu_ag.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/lsu/rtl/pa_lsu_arb.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/lsu/rtl/pa_lsu_dahbif.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/lsu/rtl/pa_lsu_dc.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/lsu/rtl/pa_lsu_dtif.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/lsu/rtl/pa_lsu_icc.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/lsu/rtl/pa_lsu_lfb.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/lsu/rtl/pa_lsu_lm.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/lsu/rtl/pa_lsu_ncb.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/lsu/rtl/pa_lsu_rdl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/lsu/rtl/pa_lsu_stb.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/lsu/rtl/pa_lsu_stb_entry.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/lsu/rtl/pa_lsu_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/lsu/rtl/pa_lsu_vb.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/lsu/rtl/pa_lsu_vb_entry.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/lsu/rtl/pa_lsu_wb_entry.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/pmp/rtl/pa_pmp_acc_arb.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/pmp/rtl/pa_pmp_comp_hit.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/pmp/rtl/pa_pmp_enc.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/pmp/rtl/pa_pmp_regs.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/pmp/rtl/pa_pmp_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/rst/rtl/pa_rst_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/rtu/rtl/pa_rtu_cbus.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/rtu/rtl/pa_rtu_int.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/rtu/rtl/pa_rtu_lockup.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/rtu/rtl/pa_rtu_rbus.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/rtu/rtl/pa_rtu_retire.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/rtu/rtl/pa_rtu_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/biu/rtl/pa_sahbl_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/lsu/rtl/pa_spsram_1024x32.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/lsu/rtl/pa_spsram_2048x32.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/lsu/rtl/pa_spsram_256x4.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/lsu/rtl/pa_spsram_256x40.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ifu/rtl/pa_spsram_256x41.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/ifu/rtl/pa_spsram_512x16.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/cpu/rtl/pa_sys_io.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/sysmap/rtl/pa_sysmap_access.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/sysmap/rtl/pa_sysmap_busif.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/sysmap/rtl/pa_sysmap_hit.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/sysmap/rtl/pa_sysmap_reg.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/sysmap/rtl/pa_sysmap_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/tcipif/rtl/pa_tcipif_behavior_bus.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/tcipif/rtl/pa_tcipif_dummy_bus.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/tcipif/rtl/pa_tcipif_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/pmu/pmu.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/system/px_had_sync.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/smpu/smpu_comp_hit.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/smpu/smpu_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/mem/soc_fpga_ram.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/system/sync.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/system/tap2_sm.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/tdt/rtl/debug/tdt_apb_master.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/tdt/rtl/debug/tdt_dm.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/tdt/rtl/top/tdt_dm_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/tdt/rtl/top/tdt_dmi.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/tdt/rtl/debug/tdt_dmi_pulse_sync.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/tdt/rtl/top/tdt_dmi_rst_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/tdt/rtl/debug/tdt_dmi_sync_dff.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/tdt/rtl/top/tdt_dmi_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/tdt/rtl/debug/tdt_dtm_chain.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/tdt/rtl/debug/tdt_dtm_ctrl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/tdt/rtl/debug/tdt_dtm_idr.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/tdt/rtl/debug/tdt_dtm_io.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/tdt/rtl/debug/tdt_dtm_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/tdt/rtl/common/tdt_gated_clk_cell.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/tdt/rtl/top/tdt_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/timer/timer.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/uart/uart.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/uart/uart_apb_reg.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/uart/uart_baud_gen.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/uart/uart_ctrl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/uart/uart_receive.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/uart/uart_trans.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/wic/wic.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/wic/wic_awake_en_32.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/wic/wic_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/d07d/system/soc.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_soc_e906_0_0/sim/design_1_soc_e906_0_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_ila_0_1/sim/design_1_ila_0_1.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_xlconstant_1_0/sim/design_1_xlconstant_1_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_system_ila_0_0/bd_0/sim/bd_f60c.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/sim/bd_f60c_ila_lib_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_system_ila_0_0/sim/design_1_system_ila_0_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_xlconstant_2_0/sim/design_1_xlconstant_2_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_ila_1_2/sim/design_1_ila_1_2.v" \
  2>&1 | tee -a vlogan.log

  vhdlan -work lib_cdc_v1_0_2 $vhdlan_opts \
    "$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd" \
  2>&1 | tee -a vhdlan.log

  vhdlan -work proc_sys_reset_v5_0_13 $vhdlan_opts \
    "$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
  2>&1 | tee -a vhdlan.log

  vhdlan -work xil_defaultlib $vhdlan_opts \
    "$ref_dir/../../../bd/design_1/ip/design_1_proc_sys_reset_1_0/sim/design_1_proc_sys_reset_1_0.vhd" \
  2>&1 | tee -a vhdlan.log

  vlogan -work generic_baseblocks_v2_1_0 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/abef/hdl" +incdir+"$ref_dir/../../../bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" +incdir+"G:/xilinx/Vivado/2022.2/data/xilinx_vip/include" \
    "$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work fifo_generator_v13_2_7 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/abef/hdl" +incdir+"$ref_dir/../../../bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" +incdir+"G:/xilinx/Vivado/2022.2/data/xilinx_vip/include" \
    "$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/83df/simulation/fifo_generator_vlog_beh.v" \
  2>&1 | tee -a vlogan.log

  vhdlan -work fifo_generator_v13_2_7 $vhdlan_opts \
    "$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/83df/hdl/fifo_generator_v13_2_rfs.vhd" \
  2>&1 | tee -a vhdlan.log

  vlogan -work fifo_generator_v13_2_7 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/abef/hdl" +incdir+"$ref_dir/../../../bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" +incdir+"G:/xilinx/Vivado/2022.2/data/xilinx_vip/include" \
    "$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/83df/hdl/fifo_generator_v13_2_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work axi_data_fifo_v2_1_26 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/abef/hdl" +incdir+"$ref_dir/../../../bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" +incdir+"G:/xilinx/Vivado/2022.2/data/xilinx_vip/include" \
    "$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/3111/hdl/axi_data_fifo_v2_1_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work axi_register_slice_v2_1_27 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/abef/hdl" +incdir+"$ref_dir/../../../bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" +incdir+"G:/xilinx/Vivado/2022.2/data/xilinx_vip/include" \
    "$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/f0b4/hdl/axi_register_slice_v2_1_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work axi_protocol_converter_v2_1_27 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/abef/hdl" +incdir+"$ref_dir/../../../bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" +incdir+"G:/xilinx/Vivado/2022.2/data/xilinx_vip/include" \
    "$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/aeb3/hdl/axi_protocol_converter_v2_1_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/abef/hdl" +incdir+"$ref_dir/../../../bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/d07d/src" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../vivado_e906_zcu.gen/sources_1/bd/design_1/ipshared/fd26/hdl/verilog" +incdir+"G:/xilinx/Vivado/2022.2/data/xilinx_vip/include" \
    "$ref_dir/../../../bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0.v" \
    "$ref_dir/../../../bd/design_1/sim/design_1.v" \
  2>&1 | tee -a vlogan.log


  vlogan -work xil_defaultlib $vlogan_opts +v2k \
    glbl.v \
  2>&1 | tee -a vlogan.log
}

# RUN_STEP: <elaborate>
elaborate()
{
  vcs $vcs_elab_opts xil_defaultlib.design_1 xil_defaultlib.glbl -o design_1_simv
}

# RUN_STEP: <simulate>
simulate()
{
  ./design_1_simv $vcs_sim_opts -do simulate.do
}

# STEP: setup
setup()
{
  case $1 in
    "-lib_map_path" )
      if [[ ($2 == "") ]]; then
        echo -e "ERROR: Simulation library directory path not specified (type \"./design_1.sh -help\" for more information)\n"
        exit 1
      fi
      create_lib_mappings $2
    ;;
    "-reset_run" )
      reset_run
      echo -e "INFO: Simulation run files deleted.\n"
      exit 0
    ;;
    "-noclean_files" )
      # do not remove previous data
    ;;
    * )
      create_lib_mappings $2
  esac

  create_lib_dir

  # Add any setup/initialization commands here:-

  # <user specific commands>

}

# Define design library mappings
create_lib_mappings()
{
  file="synopsys_sim.setup"
  if [[ -e $file ]]; then
    if [[ ($1 == "") ]]; then
      return
    else
      rm -rf $file
    fi
  fi

  touch $file

  lib_map_path=""
  if [[ ($1 != "") ]]; then
    lib_map_path="$1"
  fi

  for (( i=0; i<${#design_libs[*]}; i++ )); do
    lib="${design_libs[i]}"
    mapping="$lib:$sim_lib_dir/$lib"
    echo $mapping >> $file
  done

  if [[ ($lib_map_path != "") ]]; then
    incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
    echo $incl_ref >> $file
  fi
}

# Create design library directory paths
create_lib_dir()
{
  if [[ -e $sim_lib_dir ]]; then
    rm -rf $sim_lib_dir
  fi

  for (( i=0; i<${#design_libs[*]}; i++ )); do
    lib="${design_libs[i]}"
    lib_dir="$sim_lib_dir/$lib"
    if [[ ! -e $lib_dir ]]; then
      mkdir -p $lib_dir
    fi
  done
}

# Delete generated data from the previous run
reset_run()
{
  files_to_remove=(ucli.key design_1_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc design_1_simv.daidir)
  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
    file="${files_to_remove[i]}"
    if [[ -e $file ]]; then
      rm -rf $file
    fi
  done

  create_lib_dir
}

# Check command line arguments
check_args()
{
  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
    echo -e "ERROR: Unknown option specified '$2' (type \"./design_1.sh -help\" for more information)\n"
    exit 1
  fi

  if [[ ($2 == "-help" || $2 == "-h") ]]; then
    usage
  fi
}

# Script usage
usage()
{
  msg="Usage: design_1.sh [-help]\n\
Usage: design_1.sh [-lib_map_path]\n\
Usage: design_1.sh [-reset_run]\n\
Usage: design_1.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
-noclean_files switch.\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
  echo -e $msg
  exit 1
}

# Launch script
run $1 $2
