#!/bin/bash -f
#*********************************************************************************************************
# Vivado (TM) v2020.2 (64-bit)
#
# Filename    : design_1.sh
# Simulator   : Synopsys Verilog Compiler Simulator
# Description : Simulation script for compiling, elaborating and verifying the project source files.
#               The script will automatically create the design libraries sub-directories in the run
#               directory, add the library logical mappings in the simulator setup file, create default
#               'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Tue May 07 09:21:42 +0800 2024
# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
#
# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
#
# usage: design_1.sh [-help]
# usage: design_1.sh [-lib_map_path]
# usage: design_1.sh [-noclean_files]
# usage: design_1.sh [-reset_run]
#
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
# that points to these libraries and rerun export_simulation. For more information about this switch please
# type 'export_simulation -help' in the Tcl shell.
#
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
# executing this script. Please type 'design_1.sh -help' for more information.
#
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#*********************************************************************************************************

# Directory path for design sources and include directories (if any) wrt this path
ref_dir="."

# Override directory with 'export_sim_ref_dir' env path value if set in the shell
if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
  ref_dir="$export_sim_ref_dir"
fi

# Command line options
vlogan_opts="-full64"
vhdlan_opts="-full64"
vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
vcs_sim_opts="-ucli -licqueue -l simulate.log"

# Design libraries
design_libs=(xpm xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_13 axi_infrastructure_v1_1_0 fifo_generator_v13_2_5 axi_clock_converter_v2_1_21 generic_baseblocks_v2_1_0 axi_data_fifo_v2_1_21 axi_register_slice_v2_1_22 axi_protocol_converter_v2_1_22)

# Simulation root library directory
sim_lib_dir="vcs_lib"

# Script info
echo -e "design_1.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"

# Main steps
run()
{
  check_args $# $1
  setup $1 $2
  compile
  elaborate
  simulate
}

# RUN_STEP: <compile>
compile()
{
  # Compile design files
  vlogan -work xpm $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ip/design_1_e203_axi_0_0/src/clk_wiz_0" +incdir+"$ref_dir/../../../bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/d0f7" \
    "C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
    "C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
  2>&1 | tee -a vlogan.log

  vhdlan -work xpm $vhdlan_opts \
    "C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
  2>&1 | tee -a vhdlan.log

  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ip/design_1_e203_axi_0_0/src/clk_wiz_0" +incdir+"$ref_dir/../../../bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/d0f7" \
    "$ref_dir/../../../bd/design_1/ip/design_1_e203_axi_0_0/src/clk_wiz_0/clk_wiz_0_clk_wiz.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_e203_axi_0_0/src/clk_wiz_0/clk_wiz_0.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/adv_timer_apb_if.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/apb_adv_timer.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/apb_gpio.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/apb_i2c.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/apb_spi_master.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/apb_uart.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/comparator.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_biu.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_clk_ctrl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_clkgate.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_core.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_cpu.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_cpu_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_dtcm_ctrl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_dtcm_ram.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_exu.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_exu_alu.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_exu_alu_bjp.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_exu_alu_csrctrl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_exu_alu_dpath.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_exu_alu_lsuagu.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_exu_alu_muldiv.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_exu_alu_rglr.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_exu_branchslv.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_exu_commit.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_exu_csr.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_exu_decode.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_exu_disp.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_exu_excp.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_exu_longpwbck.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_exu_nice.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_exu_oitf.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_exu_regfile.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_exu_wbck.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_ifu.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_ifu_ifetch.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_ifu_ift2icb.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_ifu_litebpu.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_ifu_minidec.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_irq_sync.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_itcm_ctrl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_itcm_ram.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_lsu.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_lsu_ctrl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_reset_ctrl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_soc_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_srams.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_subsys_clint.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_subsys_gfcm.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_subsys_hclkgen.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_subsys_hclkgen_rstsync.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_subsys_main.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_subsys_mems.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_subsys_nice_core.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_subsys_perips.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_subsys_plic.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_subsys_pll.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_subsys_pllclkdiv.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/e203_subsys_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/i2c_master_bit_ctrl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/i2c_master_byte_ctrl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/input_stage.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/io_generic_fifo.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/prescaler.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_1cyc_sram_ctrl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_AsyncResetReg.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_AsyncResetRegVec.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_AsyncResetRegVec_1.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_AsyncResetRegVec_129.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_AsyncResetRegVec_36.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_DeglitchShiftRegister.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_LevelGateway.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_ResetCatchAndSync.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_ResetCatchAndSync_2.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_aon.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_aon_lclkgen_regs.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_aon_porrst.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_aon_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_aon_wrapper.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_clint.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_clint_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_debug_csr.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_debug_module.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_debug_ram.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_debug_rom.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_expl_axi_slv.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_flash_qspi.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_flash_qspi_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_gnrl_bufs.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_gnrl_dffs.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_gnrl_icbs.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_gnrl_ram.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_hclkgen_regs.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_icb1to16_bus.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_icb1to2_bus.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_icb1to8_bus.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_jtag_dtm.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_jtaggpioport.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_mrom.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_mrom_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_plic_man.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_plic_top.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_pmu.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_pmu_core.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_qspi_arbiter.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_qspi_fifo.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_qspi_media.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_qspi_physical.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_queue.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_queue_1.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_repeater_6.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_rtc.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_sim_ram.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_spi_flashmap.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_sram_icb_ctrl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_tl_repeater_5.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_tlfragmenter_qspi_1.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_tlwidthwidget_qspi.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/sirv_wdog.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/spi_master_apb_if.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/spi_master_clkgen.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/spi_master_controller.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/spi_master_fifo.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/spi_master_rx.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/spi_master_tx.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/timer_cntrl.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/timer_module.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/uart_interrupt.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/uart_rx.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/uart_tx.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/up_down_counter.v" \
    "$ref_dir/../../../bd/design_1/ipshared/5244/src/system.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_e203_axi_0_0/sim/design_1_e203_axi_0_0.v" \
    "$ref_dir/../../../bd/design_1/ipshared/a68b/hdl/conv_axi_v2_v1_0_S00_AXI.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ip/design_1_e203_axi_0_0/src/clk_wiz_0" +incdir+"$ref_dir/../../../bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/d0f7" \
    "$ref_dir/../../../bd/design_1/ipshared/a68b/src/acc_reg.sv" \
    "$ref_dir/../../../bd/design_1/ipshared/a68b/src/controller.sv" \
    "$ref_dir/../../../bd/design_1/ipshared/a68b/src/conv_pe.sv" \
    "$ref_dir/../../../bd/design_1/ipshared/a68b/src/im2col.sv" \
    "$ref_dir/../../../bd/design_1/ipshared/a68b/src/img_buffer.sv" \
    "$ref_dir/../../../bd/design_1/ipshared/a68b/src/input_buffer.sv" \
    "$ref_dir/../../../bd/design_1/ipshared/a68b/src/lib_fifo.sv" \
    "$ref_dir/../../../bd/design_1/ipshared/a68b/src/lib_reg.sv" \
    "$ref_dir/../../../bd/design_1/ipshared/a68b/src/matu.sv" \
    "$ref_dir/../../../bd/design_1/ipshared/a68b/src/output_buffer.sv" \
    "$ref_dir/../../../bd/design_1/ipshared/a68b/src/pe.sv" \
    "$ref_dir/../../../bd/design_1/ipshared/a68b/src/reorder.sv" \
    "$ref_dir/../../../bd/design_1/ipshared/a68b/src/sa.sv" \
    "$ref_dir/../../../bd/design_1/ipshared/a68b/src/top_conv_acc.sv" \
    "$ref_dir/../../../bd/design_1/ipshared/a68b/src/top_conv_fc.sv" \
    "$ref_dir/../../../bd/design_1/ipshared/a68b/src/top_im2col.sv" \
    "$ref_dir/../../../bd/design_1/ipshared/a68b/src/weight_buffer.sv" \
  2>&1 | tee -a vlogan.log

  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ip/design_1_e203_axi_0_0/src/clk_wiz_0" +incdir+"$ref_dir/../../../bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/d0f7" \
    "$ref_dir/../../../bd/design_1/ipshared/a68b/hdl/conv_axi_v2_v1_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_conv_axi_v2_0_0/sim/design_1_conv_axi_v2_0_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_clk_wiz.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.v" \
  2>&1 | tee -a vlogan.log

  vhdlan -work lib_cdc_v1_0_2 $vhdlan_opts \
    "$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd" \
  2>&1 | tee -a vhdlan.log

  vhdlan -work proc_sys_reset_v5_0_13 $vhdlan_opts \
    "$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
  2>&1 | tee -a vhdlan.log

  vhdlan -work xil_defaultlib $vhdlan_opts \
    "$ref_dir/../../../bd/design_1/ip/design_1_proc_sys_reset_0_0/sim/design_1_proc_sys_reset_0_0.vhd" \
  2>&1 | tee -a vhdlan.log

  vlogan -work axi_infrastructure_v1_1_0 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ip/design_1_e203_axi_0_0/src/clk_wiz_0" +incdir+"$ref_dir/../../../bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/d0f7" \
    "$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work fifo_generator_v13_2_5 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ip/design_1_e203_axi_0_0/src/clk_wiz_0" +incdir+"$ref_dir/../../../bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/d0f7" \
    "$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/276e/simulation/fifo_generator_vlog_beh.v" \
  2>&1 | tee -a vlogan.log

  vhdlan -work fifo_generator_v13_2_5 $vhdlan_opts \
    "$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/276e/hdl/fifo_generator_v13_2_rfs.vhd" \
  2>&1 | tee -a vhdlan.log

  vlogan -work fifo_generator_v13_2_5 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ip/design_1_e203_axi_0_0/src/clk_wiz_0" +incdir+"$ref_dir/../../../bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/d0f7" \
    "$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/276e/hdl/fifo_generator_v13_2_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work axi_clock_converter_v2_1_21 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ip/design_1_e203_axi_0_0/src/clk_wiz_0" +incdir+"$ref_dir/../../../bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/d0f7" \
    "$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/1304/hdl/axi_clock_converter_v2_1_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ip/design_1_e203_axi_0_0/src/clk_wiz_0" +incdir+"$ref_dir/../../../bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/d0f7" \
    "$ref_dir/../../../bd/design_1/ip/design_1_auto_cc_0/sim/design_1_auto_cc_0.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work generic_baseblocks_v2_1_0 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ip/design_1_e203_axi_0_0/src/clk_wiz_0" +incdir+"$ref_dir/../../../bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/d0f7" \
    "$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work axi_data_fifo_v2_1_21 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ip/design_1_e203_axi_0_0/src/clk_wiz_0" +incdir+"$ref_dir/../../../bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/d0f7" \
    "$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/54c0/hdl/axi_data_fifo_v2_1_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work axi_register_slice_v2_1_22 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ip/design_1_e203_axi_0_0/src/clk_wiz_0" +incdir+"$ref_dir/../../../bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/d0f7" \
    "$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/af2c/hdl/axi_register_slice_v2_1_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work axi_protocol_converter_v2_1_22 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ip/design_1_e203_axi_0_0/src/clk_wiz_0" +incdir+"$ref_dir/../../../bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/d0f7" \
    "$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/5cee/hdl/axi_protocol_converter_v2_1_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ip/design_1_e203_axi_0_0/src/clk_wiz_0" +incdir+"$ref_dir/../../../bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/5244/src" +incdir+"$ref_dir/../../../../e203_cnn_soc.gen/sources_1/bd/design_1/ipshared/d0f7" \
    "$ref_dir/../../../bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0.v" \
    "$ref_dir/../../../bd/design_1/sim/design_1.v" \
  2>&1 | tee -a vlogan.log


  vlogan -work xil_defaultlib $vlogan_opts +v2k \
    glbl.v \
  2>&1 | tee -a vlogan.log

}

# RUN_STEP: <elaborate>
elaborate()
{
  vcs $vcs_elab_opts xil_defaultlib.design_1 xil_defaultlib.glbl -o design_1_simv
}

# RUN_STEP: <simulate>
simulate()
{
  ./design_1_simv $vcs_sim_opts -do simulate.do
}

# STEP: setup
setup()
{
  case $1 in
    "-lib_map_path" )
      if [[ ($2 == "") ]]; then
        echo -e "ERROR: Simulation library directory path not specified (type \"./design_1.sh -help\" for more information)\n"
        exit 1
      fi
      create_lib_mappings $2
    ;;
    "-reset_run" )
      reset_run
      echo -e "INFO: Simulation run files deleted.\n"
      exit 0
    ;;
    "-noclean_files" )
      # do not remove previous data
    ;;
    * )
      create_lib_mappings $2
  esac

  create_lib_dir

  # Add any setup/initialization commands here:-

  # <user specific commands>

}

# Define design library mappings
create_lib_mappings()
{
  file="synopsys_sim.setup"
  if [[ -e $file ]]; then
    if [[ ($1 == "") ]]; then
      return
    else
      rm -rf $file
    fi
  fi

  touch $file

  lib_map_path=""
  if [[ ($1 != "") ]]; then
    lib_map_path="$1"
  fi

  for (( i=0; i<${#design_libs[*]}; i++ )); do
    lib="${design_libs[i]}"
    mapping="$lib:$sim_lib_dir/$lib"
    echo $mapping >> $file
  done

  if [[ ($lib_map_path != "") ]]; then
    incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
    echo $incl_ref >> $file
  fi
}

# Create design library directory paths
create_lib_dir()
{
  if [[ -e $sim_lib_dir ]]; then
    rm -rf $sim_lib_dir
  fi

  for (( i=0; i<${#design_libs[*]}; i++ )); do
    lib="${design_libs[i]}"
    lib_dir="$sim_lib_dir/$lib"
    if [[ ! -e $lib_dir ]]; then
      mkdir -p $lib_dir
    fi
  done
}

# Delete generated data from the previous run
reset_run()
{
  files_to_remove=(ucli.key design_1_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc design_1_simv.daidir)
  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
    file="${files_to_remove[i]}"
    if [[ -e $file ]]; then
      rm -rf $file
    fi
  done

  create_lib_dir
}

# Check command line arguments
check_args()
{
  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
    echo -e "ERROR: Unknown option specified '$2' (type \"./design_1.sh -help\" for more information)\n"
    exit 1
  fi

  if [[ ($2 == "-help" || $2 == "-h") ]]; then
    usage
  fi
}

# Script usage
usage()
{
  msg="Usage: design_1.sh [-help]\n\
Usage: design_1.sh [-lib_map_path]\n\
Usage: design_1.sh [-reset_run]\n\
Usage: design_1.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
-noclean_files switch.\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
  echo -e $msg
  exit 1
}

# Launch script
run $1 $2
