#!/bin/bash -f
#*********************************************************************************************************
# Vivado (TM) v2021.1 (64-bit)
#
# Filename    : design_1.sh
# Simulator   : Synopsys Verilog Compiler Simulator
# Description : Simulation script for compiling, elaborating and verifying the project source files.
#               The script will automatically create the design libraries sub-directories in the run
#               directory, add the library logical mappings in the simulator setup file, create default
#               'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sun Oct 08 21:01:20 +0800 2023
# SW Build 3247384 on Thu Jun 10 19:36:33 MDT 2021
#
# Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. 
#
# usage: design_1.sh [-help]
# usage: design_1.sh [-lib_map_path]
# usage: design_1.sh [-noclean_files]
# usage: design_1.sh [-reset_run]
#
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
# that points to these libraries and rerun export_simulation. For more information about this switch please
# type 'export_simulation -help' in the Tcl shell.
#
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
# executing this script. Please type 'design_1.sh -help' for more information.
#
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#*********************************************************************************************************

# Directory path for design sources and include directories (if any) wrt this path
ref_dir="."

# Override directory with 'export_sim_ref_dir' env path value if set in the shell
if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
  ref_dir="$export_sim_ref_dir"
fi

# Set vlogan compile options
vlogan_opts="-full64"

# Set vhdlan compile options
vhdlan_opts="-full64"

# Set vcs elaboration options
vcs_elab_opts="-full64 -debug_acc+pp+dmptf -t ps -licqueue -l elaborate.log"

# Set vcs simulation options
vcs_sim_opts="-ucli -licqueue -l simulate.log"

# Design libraries
design_libs=(xilinx_vip xpm axi_infrastructure_v1_1_0 axi_vip_v1_1_10 processing_system7_vip_v1_0_12 xil_defaultlib lib_pkg_v1_0_2 fifo_generator_v13_2_5 lib_fifo_v1_0_14 lib_srl_fifo_v1_0_2 lib_cdc_v1_0_2 axi_datamover_v5_1_26 axi_sg_v4_1_13 axi_dma_v7_1_25 generic_baseblocks_v2_1_0 axi_register_slice_v2_1_24 axi_data_fifo_v2_1_23 axi_crossbar_v2_1_25 proc_sys_reset_v5_0_13 gigantic_mux xlconcat_v2_1_4 axis_infrastructure_v1_1_0 axis_register_slice_v1_1_24 axis_subset_converter_v1_1_24 blk_mem_gen_v8_4_4 lib_bmg_v1_0_13 axi_vdma_v6_3_12 xlconstant_v1_1_7 axi_lite_ipif_v3_0_4 interrupt_control_v3_1_4 axi_gpio_v2_0_26 v_tc_v6_2_2 v_tc_v6_1_13 v_vid_in_axi4s_v4_0_9 v_axi4s_vid_out_v4_0_12 axis_broadcaster_v1_1_23 axi_protocol_converter_v2_1_24)

# Simulation root library directory
sim_lib_dir="vcs_lib"

# Script info
echo -e "design_1.sh - Script generated by export_simulation (Vivado v2021.1 (64-bit)-id)\n"

# Main steps
run()
{
  check_args $# $1
  setup $1 $2
  compile
  elaborate
  simulate
}

# RUN_STEP: <compile>
compile()
{
  vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "H:/Xilinx/Vivado/2021.1/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
    "H:/Xilinx/Vivado/2021.1/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
    "H:/Xilinx/Vivado/2021.1/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
    "H:/Xilinx/Vivado/2021.1/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
    "H:/Xilinx/Vivado/2021.1/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
    "H:/Xilinx/Vivado/2021.1/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
    "H:/Xilinx/Vivado/2021.1/data/xilinx_vip/hdl/axi_vip_if.sv" \
    "H:/Xilinx/Vivado/2021.1/data/xilinx_vip/hdl/clk_vip_if.sv" \
    "H:/Xilinx/Vivado/2021.1/data/xilinx_vip/hdl/rst_vip_if.sv" \
  2>&1 | tee -a vlogan.log

  vlogan -work xpm $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "H:/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
    "H:/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \
    "H:/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
  2>&1 | tee -a vlogan.log

  vhdlan -work xpm $vhdlan_opts \
    "H:/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_VCOMP.vhd" \
  2>&1 | tee -a vhdlan.log

  vlogan -work axi_infrastructure_v1_1_0 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work axi_vip_v1_1_10 $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/0980/hdl/axi_vip_v1_1_vl_rfs.sv" \
  2>&1 | tee -a vlogan.log

  vlogan -work processing_system7_vip_v1_0_12 $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl/processing_system7_vip_v1_0_vl_rfs.sv" \
  2>&1 | tee -a vlogan.log

  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.v" \
  2>&1 | tee -a vlogan.log

  vhdlan -work lib_pkg_v1_0_2 $vhdlan_opts \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/0513/hdl/lib_pkg_v1_0_rfs.vhd" \
  2>&1 | tee -a vhdlan.log

  vlogan -work fifo_generator_v13_2_5 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/276e/simulation/fifo_generator_vlog_beh.v" \
  2>&1 | tee -a vlogan.log

  vhdlan -work fifo_generator_v13_2_5 $vhdlan_opts \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/276e/hdl/fifo_generator_v13_2_rfs.vhd" \
  2>&1 | tee -a vhdlan.log

  vlogan -work fifo_generator_v13_2_5 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/276e/hdl/fifo_generator_v13_2_rfs.v" \
  2>&1 | tee -a vlogan.log

  vhdlan -work lib_fifo_v1_0_14 $vhdlan_opts \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/a5cb/hdl/lib_fifo_v1_0_rfs.vhd" \
  2>&1 | tee -a vhdlan.log

  vhdlan -work lib_srl_fifo_v1_0_2 $vhdlan_opts \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd" \
  2>&1 | tee -a vhdlan.log

  vhdlan -work lib_cdc_v1_0_2 $vhdlan_opts \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd" \
  2>&1 | tee -a vhdlan.log

  vhdlan -work axi_datamover_v5_1_26 $vhdlan_opts \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1e21/hdl/axi_datamover_v5_1_vh_rfs.vhd" \
  2>&1 | tee -a vhdlan.log

  vhdlan -work axi_sg_v4_1_13 $vhdlan_opts \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/4919/hdl/axi_sg_v4_1_rfs.vhd" \
  2>&1 | tee -a vhdlan.log

  vhdlan -work axi_dma_v7_1_25 $vhdlan_opts \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1faa/hdl/axi_dma_v7_1_vh_rfs.vhd" \
  2>&1 | tee -a vhdlan.log

  vhdlan -work xil_defaultlib $vhdlan_opts \
    "$ref_dir/../../../bd/design_1/ip/design_1_axi_dma_1_0/sim/design_1_axi_dma_1_0.vhd" \
  2>&1 | tee -a vhdlan.log

  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../bd/design_1/ip/design_1_Accel_Conv_0_1/sim/design_1_Accel_Conv_0_1.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work generic_baseblocks_v2_1_0 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work axi_register_slice_v2_1_24 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8f68/hdl/axi_register_slice_v2_1_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work axi_data_fifo_v2_1_23 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/94ec/hdl/axi_data_fifo_v2_1_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work axi_crossbar_v2_1_25 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../bd/design_1/ip/design_1_xbar_2/sim/design_1_xbar_2.v" \
  2>&1 | tee -a vlogan.log

  vhdlan -work proc_sys_reset_v5_0_13 $vhdlan_opts \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
  2>&1 | tee -a vhdlan.log

  vhdlan -work xil_defaultlib $vhdlan_opts \
    "$ref_dir/../../../bd/design_1/ip/design_1_rst_ps7_0_142M_1/sim/design_1_rst_ps7_0_142M_1.vhd" \
  2>&1 | tee -a vhdlan.log

  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../bd/design_1/ip/design_1_xbar_3/sim/design_1_xbar_3.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_system_ila_0_0/bd_0/sim/bd_f60c.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/sim/bd_f60c_ila_lib_0.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work gigantic_mux $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/d322/hdl/gigantic_mux_v1_0_cntr.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/bd_f60c_g_inst_0_gigantic_mux.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work xlconcat_v2_1_4 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_2/sim/bd_f60c_slot_0_aw_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_3/sim/bd_f60c_slot_0_w_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_4/sim/bd_f60c_slot_0_b_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_5/sim/bd_f60c_slot_0_ar_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_6/sim/bd_f60c_slot_0_r_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_7/sim/bd_f60c_slot_1_aw_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_8/sim/bd_f60c_slot_1_w_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_9/sim/bd_f60c_slot_1_b_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_10/sim/bd_f60c_slot_1_ar_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_11/sim/bd_f60c_slot_1_r_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_system_ila_0_0/sim/design_1_system_ila_0_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/sim/ila_0.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/564b/src/cmos_8_16bit.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/564b/src/alinx_ov5640.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_alinx_ov5640_0_0/sim/design_1_alinx_ov5640_0_0.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work axis_infrastructure_v1_1_0 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl/axis_infrastructure_v1_1_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work axis_register_slice_v1_1_24 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8d66/hdl/axis_register_slice_v1_1_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_0_0/hdl/tdata_design_1_axis_subset_converter_0_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_0_0/hdl/tuser_design_1_axis_subset_converter_0_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_0_0/hdl/tstrb_design_1_axis_subset_converter_0_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_0_0/hdl/tkeep_design_1_axis_subset_converter_0_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_0_0/hdl/tid_design_1_axis_subset_converter_0_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_0_0/hdl/tdest_design_1_axis_subset_converter_0_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_0_0/hdl/tlast_design_1_axis_subset_converter_0_0.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work axis_subset_converter_v1_1_24 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cdd1/hdl/axis_subset_converter_v1_1_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_0_0/hdl/top_design_1_axis_subset_converter_0_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_0_0/sim/design_1_axis_subset_converter_0_0.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work blk_mem_gen_v8_4_4 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/2985/simulation/blk_mem_gen_v8_4.v" \
  2>&1 | tee -a vlogan.log

  vhdlan -work lib_bmg_v1_0_13 $vhdlan_opts \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/af67/hdl/lib_bmg_v1_0_rfs.vhd" \
  2>&1 | tee -a vhdlan.log

  vlogan -work axi_vdma_v6_3_12 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl/axi_vdma_v6_3_rfs.v" \
  2>&1 | tee -a vlogan.log

  vhdlan -work axi_vdma_v6_3_12 $vhdlan_opts \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl/axi_vdma_v6_3_rfs.vhd" \
  2>&1 | tee -a vhdlan.log

  vhdlan -work xil_defaultlib $vhdlan_opts \
    "$ref_dir/../../../bd/design_1/ip/design_1_axi_vdma_0_0/sim/design_1_axi_vdma_0_0.vhd" \
  2>&1 | tee -a vhdlan.log

  vlogan -work xlconstant_v1_1_7 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/fcfc/hdl/xlconstant_v1_1_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../bd/design_1/ip/design_1_xlconstant_0_0/sim/design_1_xlconstant_0_0.v" \
  2>&1 | tee -a vlogan.log

  vhdlan -work axi_lite_ipif_v3_0_4 $vhdlan_opts \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd" \
  2>&1 | tee -a vhdlan.log

  vhdlan -work interrupt_control_v3_1_4 $vhdlan_opts \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/a040/hdl/interrupt_control_v3_1_vh_rfs.vhd" \
  2>&1 | tee -a vhdlan.log

  vhdlan -work axi_gpio_v2_0_26 $vhdlan_opts \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/65b4/hdl/axi_gpio_v2_0_vh_rfs.vhd" \
  2>&1 | tee -a vhdlan.log

  vhdlan -work xil_defaultlib $vhdlan_opts \
    "$ref_dir/../../../bd/design_1/ip/design_1_axi_gpio_0_0/sim/design_1_axi_gpio_0_0.vhd" \
  2>&1 | tee -a vhdlan.log

  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/9097/src/mmcme2_drp.v" \
  2>&1 | tee -a vlogan.log

  vhdlan -work xil_defaultlib $vhdlan_opts \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/9097/src/axi_dynclk_S00_AXI.vhd" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/9097/src/axi_dynclk.vhd" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axi_dynclk_0_0/sim/design_1_axi_dynclk_0_0.vhd" \
  2>&1 | tee -a vhdlan.log

  vhdlan -work v_tc_v6_2_2 $vhdlan_opts \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/7f10/hdl/v_tc_v6_2_vh_rfs.vhd" \
  2>&1 | tee -a vhdlan.log

  vhdlan -work xil_defaultlib $vhdlan_opts \
    "$ref_dir/../../../bd/design_1/ip/design_1_v_tc_0_0/sim/design_1_v_tc_0_0.vhd" \
  2>&1 | tee -a vhdlan.log

  vhdlan -work v_tc_v6_1_13 $vhdlan_opts \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b92e/hdl/v_tc_v6_1_vh_rfs.vhd" \
  2>&1 | tee -a vhdlan.log

  vlogan -work v_vid_in_axi4s_v4_0_9 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b2aa/hdl/v_vid_in_axi4s_v4_0_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work v_axi4s_vid_out_v4_0_12 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/2f8d/hdl/v_axi4s_vid_out_v4_0_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../bd/design_1/ip/design_1_v_axi4s_vid_out_0_0/sim/design_1_v_axi4s_vid_out_0_0.v" \
  2>&1 | tee -a vlogan.log

  vhdlan -work xil_defaultlib $vhdlan_opts \
    "$ref_dir/../../../bd/design_1/ip/design_1_axi_vdma_1_0/sim/design_1_axi_vdma_1_0.vhd" \
  2>&1 | tee -a vhdlan.log

  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../bd/design_1/ipshared/051a/src/i2c_extender.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_i2c_extender_0_0/sim/design_1_i2c_extender_0_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_ila_3_0/sim/design_1_ila_3_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_1_1/hdl/tdata_design_1_axis_subset_converter_1_1.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_1_1/hdl/tuser_design_1_axis_subset_converter_1_1.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_1_1/hdl/tstrb_design_1_axis_subset_converter_1_1.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_1_1/hdl/tkeep_design_1_axis_subset_converter_1_1.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_1_1/hdl/tid_design_1_axis_subset_converter_1_1.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_1_1/hdl/tdest_design_1_axis_subset_converter_1_1.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_1_1/hdl/tlast_design_1_axis_subset_converter_1_1.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_1_1/hdl/top_design_1_axis_subset_converter_1_1.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_1_1/sim/design_1_axis_subset_converter_1_1.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/Add_Char1.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/Add_Char1_letter.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/Add_Char2.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/Add_Char3.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/Add_Char4.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/Add_Char5.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/Add_Char6.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/Add_Rectangle.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/AXIvideo2Mat.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/Block_proc.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/fifo_w16_d1_A.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/fifo_w16_d2_A.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/fifo_w16_d3_A.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/fifo_w16_d4_A.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/fifo_w16_d5_A.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/fifo_w16_d6_A.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/fifo_w16_d7_A.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/fifo_w8_d1_A.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/fifo_w8_d2_A.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/fifo_w8_d3_A.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/fifo_w8_d4_A.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/fifo_w8_d5_A.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/fifo_w8_d6_A.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/fifo_w8_d7_A.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/fifo_w8_d8_A.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/hls_rect.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/hls_rect_AXILiteS_s_axi.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/hls_rect_entry3.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/hls_rect_entry304.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/Mat2AXIvideo.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/start_for_Add_ChadEe.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/start_for_Add_ChaeOg.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/start_for_Add_ChafYi.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/start_for_Add_Chag8j.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/start_for_Add_Chahbi.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/start_for_Add_Chaibs.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/start_for_Add_RecjbC.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/start_for_Block_pcud.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/start_for_hls_recbkb.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/cc2d/hdl/verilog/start_for_Mat2AXIkbM.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_hls_rect_0_3/sim/design_1_hls_rect_0_3.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_2_1/hdl/tdata_design_1_axis_subset_converter_2_1.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_2_1/hdl/tuser_design_1_axis_subset_converter_2_1.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_2_1/hdl/tstrb_design_1_axis_subset_converter_2_1.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_2_1/hdl/tkeep_design_1_axis_subset_converter_2_1.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_2_1/hdl/tid_design_1_axis_subset_converter_2_1.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_2_1/hdl/tdest_design_1_axis_subset_converter_2_1.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_2_1/hdl/tlast_design_1_axis_subset_converter_2_1.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_2_1/hdl/top_design_1_axis_subset_converter_2_1.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_2_1/sim/design_1_axis_subset_converter_2_1.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_ila_0_2/sim/design_1_ila_0_2.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_ila_1_0/sim/design_1_ila_1_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_ila_1_1/sim/design_1_ila_1_1.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_3_0/hdl/tdata_design_1_axis_subset_converter_3_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_3_0/hdl/tuser_design_1_axis_subset_converter_3_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_3_0/hdl/tstrb_design_1_axis_subset_converter_3_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_3_0/hdl/tkeep_design_1_axis_subset_converter_3_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_3_0/hdl/tid_design_1_axis_subset_converter_3_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_3_0/hdl/tdest_design_1_axis_subset_converter_3_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_3_0/hdl/tlast_design_1_axis_subset_converter_3_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_3_0/hdl/top_design_1_axis_subset_converter_3_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_3_0/sim/design_1_axis_subset_converter_3_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_broadcaster_0_0/hdl/tdata_design_1_axis_broadcaster_0_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_broadcaster_0_0/hdl/tuser_design_1_axis_broadcaster_0_0.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work axis_broadcaster_v1_1_23 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/68e1/hdl/axis_broadcaster_v1_1_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_broadcaster_0_0/hdl/top_design_1_axis_broadcaster_0_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_broadcaster_0_0/sim/design_1_axis_broadcaster_0_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_ila_1_2/sim/design_1_ila_1_2.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_ila_1_3/sim/design_1_ila_1_3.v" \
  2>&1 | tee -a vlogan.log

  vhdlan -work xil_defaultlib $vhdlan_opts \
    "$ref_dir/../../../bd/design_1/ip/design_1_axi_vdma_2_0/sim/design_1_axi_vdma_2_0.vhd" \
  2>&1 | tee -a vhdlan.log

  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../bd/design_1/ip/design_1_ila_1_4/sim/design_1_ila_1_4.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/35de/hdl/verilog/Convert.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/35de/hdl/verilog/Convert_quant_table.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/35de/hdl/verilog/Downsample.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/35de/hdl/verilog/hls_preprocess.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/35de/hdl/verilog/hls_preprocess_AXILiteS_s_axi.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/35de/hdl/verilog/Mat2AXIvideo.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/35de/hdl/verilog/start_for_Convertcud.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/35de/hdl/verilog/start_for_Downsambkb.v" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/35de/hdl/verilog/start_for_Mat2AXIdEe.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_hls_preprocess_0_0/sim/design_1_hls_preprocess_0_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_4_0/hdl/tdata_design_1_axis_subset_converter_4_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_4_0/hdl/tuser_design_1_axis_subset_converter_4_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_4_0/hdl/tstrb_design_1_axis_subset_converter_4_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_4_0/hdl/tkeep_design_1_axis_subset_converter_4_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_4_0/hdl/tid_design_1_axis_subset_converter_4_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_4_0/hdl/tdest_design_1_axis_subset_converter_4_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_4_0/hdl/tlast_design_1_axis_subset_converter_4_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_4_0/hdl/top_design_1_axis_subset_converter_4_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_axis_subset_converter_4_0/sim/design_1_axis_subset_converter_4_0.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work axi_protocol_converter_v2_1_24 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/6e0d/hdl/axi_protocol_converter_v2_1_vl_rfs.v" \
  2>&1 | tee -a vlogan.log

  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/f42d/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/8713/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/66f2/hdl" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/b205/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ipshared/c968/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_alinx_ov5640_0_0/src/ila_0/hdl/verilog" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_rect_0_3/drivers/hls_rect_v1_0/src" +incdir+"$ref_dir/../../../../VideoDetectionProject.gen/sources_1/bd/design_1/ip/design_1_hls_preprocess_0_0/drivers/hls_preprocess_v1_0/src" +incdir+"H:/Xilinx/Vivado/2021.1/data/xilinx_vip/include" \
    "$ref_dir/../../../bd/design_1/ip/design_1_auto_pc_0/sim/design_1_auto_pc_0.v" \
    "$ref_dir/../../../bd/design_1/ip/design_1_auto_pc_1/sim/design_1_auto_pc_1.v" \
    "$ref_dir/../../../bd/design_1/sim/design_1.v" \
  2>&1 | tee -a vlogan.log


  vlogan -work xil_defaultlib $vlogan_opts +v2k \
    glbl.v \
  2>&1 | tee -a vlogan.log
}

# RUN_STEP: <elaborate>
elaborate()
{
  vcs $vcs_elab_opts xil_defaultlib.design_1 xil_defaultlib.glbl -o design_1_simv
}

# RUN_STEP: <simulate>
simulate()
{
  ./design_1_simv $vcs_sim_opts -do simulate.do
}

# STEP: setup
setup()
{
  case $1 in
    "-lib_map_path" )
      if [[ ($2 == "") ]]; then
        echo -e "ERROR: Simulation library directory path not specified (type \"./design_1.sh -help\" for more information)\n"
        exit 1
      fi
      create_lib_mappings $2
    ;;
    "-reset_run" )
      reset_run
      echo -e "INFO: Simulation run files deleted.\n"
      exit 0
    ;;
    "-noclean_files" )
      # do not remove previous data
    ;;
    * )
      create_lib_mappings $2
  esac

  create_lib_dir

  # Add any setup/initialization commands here:-

  # <user specific commands>

}

# Define design library mappings
create_lib_mappings()
{
  file="synopsys_sim.setup"
  if [[ -e $file ]]; then
    if [[ ($1 == "") ]]; then
      return
    else
      rm -rf $file
    fi
  fi

  touch $file

  lib_map_path=""
  if [[ ($1 != "") ]]; then
    lib_map_path="$1"
  fi

  for (( i=0; i<${#design_libs[*]}; i++ )); do
    lib="${design_libs[i]}"
    mapping="$lib:$sim_lib_dir/$lib"
    echo $mapping >> $file
  done

  if [[ ($lib_map_path != "") ]]; then
    incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
    echo $incl_ref >> $file
  fi
}

# Create design library directory paths
create_lib_dir()
{
  if [[ -e $sim_lib_dir ]]; then
    rm -rf $sim_lib_dir
  fi

  for (( i=0; i<${#design_libs[*]}; i++ )); do
    lib="${design_libs[i]}"
    lib_dir="$sim_lib_dir/$lib"
    if [[ ! -e $lib_dir ]]; then
      mkdir -p $lib_dir
    fi
  done
}

# Delete generated data from the previous run
reset_run()
{
  files_to_remove=(ucli.key design_1_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc design_1_simv.daidir)
  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
    file="${files_to_remove[i]}"
    if [[ -e $file ]]; then
      rm -rf $file
    fi
  done

  create_lib_dir
}

# Check command line arguments
check_args()
{
  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
    echo -e "ERROR: Unknown option specified '$2' (type \"./design_1.sh -help\" for more information)\n"
    exit 1
  fi

  if [[ ($2 == "-help" || $2 == "-h") ]]; then
    usage
  fi
}

# Script usage
usage()
{
  msg="Usage: design_1.sh [-help]\n\
Usage: design_1.sh [-lib_map_path]\n\
Usage: design_1.sh [-reset_run]\n\
Usage: design_1.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
-noclean_files switch.\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
  echo -e $msg
  exit 1
}

# Launch script
run $1 $2
