"S:/DevTools/Efinity/bin/efx_map" --project "DDR3_MC" --root "example_top" --write-efx-verilog "F:/Project/yls/Project3/uart_showchar_fillbrank_updown2/efinity_project/outflow/DDR3_MC.map.v" --write-premap-module "F:/Project/yls/Project3/uart_showchar_fillbrank_updown2/efinity_project/outflow/DDR3_MC.elab.vdb" --binary-db "F:/Project/yls/Project3/uart_showchar_fillbrank_updown2/efinity_project/outflow/DDR3_MC.vdb" --device "Ti60F225" --family "Titanium" --mode "speed" --max_ram "-1" --max_mult "-1" --infer-clk-enable "3" --infer-sync-set-reset "1" --fanout-limit "0" --seq_opt "0" --retiming "1" --dsp-mac-packing "1" --dsp-input-regs-packing "1" --dsp-output-regs-packing "1" --bram_output_regs_packing "1" --blast_const_operand_adders "1" --operator-sharing "0" --optimize-adder-tree "0" --pack-luts-to-comb4 "0" --min-sr-fanout "0" --seq-opt-sync-only "0" --blackbox-error "1" --allow-const-ram-index "0" --hdl-compile-unit "1" --create-onehot-fsms "0" --min-ce-fanout "0" --mult-decomp-retime "0" --optimize-zero-init-rom "1" --insert-carry-skip "0" --veri_option "verilog_mode=verilog_2k,vhdl_mode=vhdl_2008" --work-dir "F:/Project/yls/Project3/uart_showchar_fillbrank_updown2/efinity_project/work_syn" --output-dir "F:/Project/yls/Project3/uart_showchar_fillbrank_updown2/efinity_project/outflow" --project-xml "F:/Project/yls/Project3/uart_showchar_fillbrank_updown2/efinity_project/DDR3_MC.xml" --I "F:/Project/yls/Project3/uart_showchar_fillbrank_updown2/efinity_project" --I "F:/Project/yls/Project3/uart_showchar_fillbrank_updown2/efinity_project/ip/dsi_tx" --I "F:/Project/yls/Project3/uart_showchar_fillbrank_updown2/efinity_project/ip/efx_ddr3_axi_1" --I "F:/Project/yls/Project3/uart_showchar_fillbrank_updown2/efinity_project/ip/fifo_efinity"