#!/bin/bash
#
#  VlogHammer -- A Verilog Synthesis Regression Test
#
#  Copyright (C) 2013  Clifford Wolf <clifford@clifford.at>
#  
#  Permission to use, copy, modify, and/or distribute this software for any
#  purpose with or without fee is hereby granted, provided that the above
#  copyright notice and this permission notice appear in all copies.
#  
#  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
#  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
#  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
#  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
#  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
#  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
#  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
#

set -ex
ALL_MODES="default abc lateopt noopt nomap simlib simgates minimal"

rm -rf check_yosys_*
for mode in $ALL_MODES; do
	make mrproper
	make -j6 -l8 YOSYS_MODE=$mode syn_yosys
	make -j6 -l8 YOSYS_MODE=$mode check_yosys
	mv check_yosys check_yosys_$mode
done

set +x
make mrproper

echo
for mode in $ALL_MODES; do
	echo -e "$mode\\t$(ls check_yosys_$mode/*.err 2> /dev/null | wc -l | gawk '{print $1;}') errors"
done | expand -t20
echo

