Renesas/Swin-Tiny-ONNX

Swin-Tiny (ONNX) – Renesas X5H

Requested under the name "Swin_transformer"; renamed here to Swin-Tiny to match the actual source checkpoint (swin_tiny_16xb64_in1k). Confirm or rename back if a different Swin variant/size was intended.

Introduction

This repository hosts Swin Transformer (Tiny) targeting the Renesas R-Car X5H platform for image classification inference on the NPX6 NPU.

• Model Architecture: Swin Transformer — Tiny
• Source Model: timm/swin_tiny_patch4_window7_224.ms_in1k — OpenMMLab config swin_tiny_16xb64_in1k
• Task: Image Classification (ImageNet-1k)
• Input Resolution: 224 × 224 (standard for Swin-Tiny / IN1k)

Deployment Flow

The FP32 ONNX model is auto-cast to INT8 by the Renesas MWMX toolchain at compile time — no separate quantization step is required.

swin_tiny_16xb64_in1k.onnx (FP32)
        │
        └─▶  MWMX Runtime  ──▶  INT8 auto-cast  ──▶  NPX6 NPU

Provided Artifacts

Artifact	Status	Notes
FP32 (ONNX)	✅	fp32/swin-tiny_16xb64_in1k.onnx — FP32 ONNX export

Performance

Measured on Renesas R-Car X5H via the MWMX runtime (APM80 ship-performance CI pipeline).

Benchmark configuration: Single NPU · Batch size: 1 · Input: 3 × 224 × 224

Runtime	Precision	Device	Latency (ms)	Type
MWMX Runtime	INT8 (auto)	X5H · 1× NPU · 1 Core · 850 MHz	40.403	Measured
MWMX Runtime	INT8 (auto)	X5H · 1× NPU · 1 Core · 850 MHz	40.478	Measured (2026-09-16)
MWMX Runtime	INT8 (auto)	X5H · 1× NPU · 12 Cores · 850 MHz	16.290	Measured

Cross-validation: a second benchmark run exists (int8/benchmarks/x5h_mwmx_npu_apm50_*core.yaml, internal "APM50" CI pipeline) using the swin_tiny_3rdparty_in1k checkpoint variant instead of swin_tiny_16xb64_in1k. Latencies are very close to the numbers above (40.377565 ms @ 1 core, 16.323933 ms @ 12 cores), cross-validating the original APM80 measurements despite the different checkpoint source.

Accuracy

TBD — not yet measured/published for this repo.

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ONNX Runtime – Renesas EP v2.1.0 (MWMX 2.2 ENG4)

Measured on R-Car X5H with ONNX Runtime + Renesas Execution Provider (INT8 auto-cast); nodes the NPU cannot run fall back to the CPU EP. Batch size 1, 1 NPU. Source: ORT Renesas EP test report, status 2026-09-30. This section supersedes earlier ORT figures in this card.

Component	AI Cores	Latency (ms)	Throughput (fps)	NPU Inference (ms)	NPU %	CPU + Overhead %	Portable pkg NPU-only (ms)
Full model	1	19.194	52.1	17.388	90.6 %	9.4 %	—
Full model	12	12.642	79.1	—	—	—	—

12-core latency is not always lower than 1-core: small models are dominated by CPU-side overhead.

Graph partitioning (NPU vs CPU nodes)

Component	Total Nodes	NPU Nodes	CPU Nodes (Q/DQ inserted)	NPU %	CPU %
Full model	373	370	3 (1)	99.2 %	0.8 %

Accuracy (ORT)

Runtime / Precision	Result
CPU EP · FP32 reference	Top-1 81.3 % · Top-5 95.8 %
Renesas EP + CPU EP · INT8 · v2.1.0	Top-1 79.8 % · Top-5 94.4 %

Evaluated on a subset (1k images), not the full validation set.

Compile notes (from the test workbook)

• Nodes dispatched to CPU for better accuracy: 62

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Runtime Details

MWMX Runtime

• Engine: Renesas MWMX (Middleware MX) native inference runtime
• Input format: FP32 ONNX (compiled by the MWMX toolchain)
• NPU execution precision: INT8 (auto-cast by MWMX toolchain)
• Execution target: NPX6-48K NPU on R-Car X5H

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Prerequisites

To run inference on Renesas R-Car X5H, you need:

1. Renesas R-Car X5H board with NPX6 NPU
2. Renesas MWMX Runtime
3. Hugging Face CLI to download the model

Download

hf download Renesas/Swin-Tiny-ONNX --repo-type=model --include "fp32/*"

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Benchmark Methodology

• HIL runs: Hardware-in-the-loop — measured on physical R-Car X5H silicon via the MWMX runtime (metawaremx_runtime CI pipeline, "APM80" ship-performance target)
• Precision: FP32 ONNX input; INT8 execution (auto-cast by MWMX)
• Slices: results reported for both 1 AI core and 12 AI cores per NPU instance