# rand500
CUDA_VISIBLE_DEVICES=0 python max_cover_egn-naive.py --cfg cfg/max_cover_rand500.yaml --lr 1e-5 --reg 500 --timestamp rand500-5-3-1;
CUDA_VISIBLE_DEVICES=0 python max_cover_egn-naive.py --cfg cfg/max_cover_rand500.yaml --lr 1e-5 --reg 500 --timestamp rand500-5-3-2;
CUDA_VISIBLE_DEVICES=0 python max_cover_egn-naive.py --cfg cfg/max_cover_rand500.yaml --lr 1e-5 --reg 500 --timestamp rand500-5-3-3;
CUDA_VISIBLE_DEVICES=0 python max_cover_egn-naive.py --cfg cfg/max_cover_rand500.yaml --lr 1e-5 --reg 500 --timestamp rand500-5-3-4;
CUDA_VISIBLE_DEVICES=0 python max_cover_egn-naive.py --cfg cfg/max_cover_rand500.yaml --lr 1e-5 --reg 500 --timestamp rand500-5-3-5;

# rand1000
CUDA_VISIBLE_DEVICES=0 python max_cover_egn-naive.py --cfg cfg/max_cover_rand1000.yaml --lr 1e-5 --reg 500 --timestamp rand1000-5-3-1;
CUDA_VISIBLE_DEVICES=0 python max_cover_egn-naive.py --cfg cfg/max_cover_rand1000.yaml --lr 1e-5 --reg 500 --timestamp rand1000-5-3-2;
CUDA_VISIBLE_DEVICES=0 python max_cover_egn-naive.py --cfg cfg/max_cover_rand1000.yaml --lr 1e-5 --reg 500 --timestamp rand1000-5-3-3;
CUDA_VISIBLE_DEVICES=0 python max_cover_egn-naive.py --cfg cfg/max_cover_rand1000.yaml --lr 1e-5 --reg 500 --timestamp rand1000-5-3-4;
CUDA_VISIBLE_DEVICES=0 python max_cover_egn-naive.py --cfg cfg/max_cover_rand1000.yaml --lr 1e-5 --reg 500 --timestamp rand1000-5-3-5;

# rail
CUDA_VISIBLE_DEVICES=0 python max_cover_egn-naive.py --cfg cfg/max_cover_rail.yaml --lr 1e-5 --reg 10 --timestamp rail-5-1-1;
CUDA_VISIBLE_DEVICES=0 python max_cover_egn-naive.py --cfg cfg/max_cover_rail.yaml --lr 1e-5 --reg 10 --timestamp rail-5-1-2;
CUDA_VISIBLE_DEVICES=0 python max_cover_egn-naive.py --cfg cfg/max_cover_rail.yaml --lr 1e-5 --reg 10 --timestamp rail-5-1-3;
CUDA_VISIBLE_DEVICES=0 python max_cover_egn-naive.py --cfg cfg/max_cover_rail.yaml --lr 1e-5 --reg 10 --timestamp rail-5-1-4;
CUDA_VISIBLE_DEVICES=0 python max_cover_egn-naive.py --cfg cfg/max_cover_rail.yaml --lr 1e-5 --reg 10 --timestamp rail-5-1-5;

# twitch
CUDA_VISIBLE_DEVICES=0 python max_cover_egn-naive.py --cfg cfg/max_cover_twitch.yaml --lr 1e-1 --reg 10 --timestamp twitch-1-1-1;
CUDA_VISIBLE_DEVICES=0 python max_cover_egn-naive.py --cfg cfg/max_cover_twitch.yaml --lr 1e-1 --reg 10 --timestamp twitch-1-1-2;
CUDA_VISIBLE_DEVICES=0 python max_cover_egn-naive.py --cfg cfg/max_cover_twitch.yaml --lr 1e-1 --reg 10 --timestamp twitch-1-1-3;
CUDA_VISIBLE_DEVICES=0 python max_cover_egn-naive.py --cfg cfg/max_cover_twitch.yaml --lr 1e-1 --reg 10 --timestamp twitch-1-1-4;
CUDA_VISIBLE_DEVICES=0 python max_cover_egn-naive.py --cfg cfg/max_cover_twitch.yaml --lr 1e-1 --reg 10 --timestamp twitch-1-1-5;
