CUDA_VISIBLE_DEVICES=2 python max_cover_cardnn-notto-hgs.py --cfg cfg/max_cover_rand500.yaml --lr 1e-5 --reg 0.15 --timestamp cardnn_notto_hgs_rand500-1;
CUDA_VISIBLE_DEVICES=2 python max_cover_cardnn-notto-hgs.py --cfg cfg/max_cover_rand500.yaml --lr 1e-5 --reg 0.15 --timestamp cardnn_notto_hgs_rand500-2;
CUDA_VISIBLE_DEVICES=2 python max_cover_cardnn-notto-hgs.py --cfg cfg/max_cover_rand500.yaml --lr 1e-5 --reg 0.15 --timestamp cardnn_notto_hgs_rand500-3;
CUDA_VISIBLE_DEVICES=2 python max_cover_cardnn-notto-hgs.py --cfg cfg/max_cover_rand500.yaml --lr 1e-5 --reg 0.15 --timestamp cardnn_notto_hgs_rand500-4;
CUDA_VISIBLE_DEVICES=2 python max_cover_cardnn-notto-hgs.py --cfg cfg/max_cover_rand500.yaml --lr 1e-5 --reg 0.15 --timestamp cardnn_notto_hgs_rand500-5;

CUDA_VISIBLE_DEVICES=2 python max_cover_cardnn-notto-hgs.py --cfg cfg/max_cover_rand1000.yaml --lr 1e-5 --reg 0.15 --timestamp cardnn_notto_hgs_rand1000-1;
CUDA_VISIBLE_DEVICES=2 python max_cover_cardnn-notto-hgs.py --cfg cfg/max_cover_rand1000.yaml --lr 1e-5 --reg 0.15 --timestamp cardnn_notto_hgs_rand1000-2;
CUDA_VISIBLE_DEVICES=2 python max_cover_cardnn-notto-hgs.py --cfg cfg/max_cover_rand1000.yaml --lr 1e-5 --reg 0.15 --timestamp cardnn_notto_hgs_rand1000-3;
CUDA_VISIBLE_DEVICES=2 python max_cover_cardnn-notto-hgs.py --cfg cfg/max_cover_rand1000.yaml --lr 1e-5 --reg 0.15 --timestamp cardnn_notto_hgs_rand1000-4;
CUDA_VISIBLE_DEVICES=2 python max_cover_cardnn-notto-hgs.py --cfg cfg/max_cover_rand1000.yaml --lr 1e-5 --reg 0.15 --timestamp cardnn_notto_hgs_rand1000-5;

CUDA_VISIBLE_DEVICES=2 python max_cover_cardnn-notto-hgs.py --cfg cfg/max_cover_twitch.yaml --lr 1e-4 --reg 0.01 --timestamp cardnn_notto_hgs_twitch-1;
CUDA_VISIBLE_DEVICES=2 python max_cover_cardnn-notto-hgs.py --cfg cfg/max_cover_twitch.yaml --lr 1e-4 --reg 0.01 --timestamp cardnn_notto_hgs_twitch-2;
CUDA_VISIBLE_DEVICES=2 python max_cover_cardnn-notto-hgs.py --cfg cfg/max_cover_twitch.yaml --lr 1e-4 --reg 0.01 --timestamp cardnn_notto_hgs_twitch-3;
CUDA_VISIBLE_DEVICES=2 python max_cover_cardnn-notto-hgs.py --cfg cfg/max_cover_twitch.yaml --lr 1e-4 --reg 0.01 --timestamp cardnn_notto_hgs_twitch-4;
CUDA_VISIBLE_DEVICES=2 python max_cover_cardnn-notto-hgs.py --cfg cfg/max_cover_twitch.yaml --lr 1e-4 --reg 0.01 --timestamp cardnn_notto_hgs_twitch-5;

CUDA_VISIBLE_DEVICES=2 python max_cover_cardnn-notto-hgs.py --cfg cfg/max_cover_rail.yaml --lr 1e-5 --reg 0.15 --timestamp cardnn_notto_hgs_rail-1;
CUDA_VISIBLE_DEVICES=2 python max_cover_cardnn-notto-hgs.py --cfg cfg/max_cover_rail.yaml --lr 1e-5 --reg 0.15 --timestamp cardnn_notto_hgs_rail-2;
CUDA_VISIBLE_DEVICES=2 python max_cover_cardnn-notto-hgs.py --cfg cfg/max_cover_rail.yaml --lr 1e-5 --reg 0.15 --timestamp cardnn_notto_hgs_rail-3;
CUDA_VISIBLE_DEVICES=2 python max_cover_cardnn-notto-hgs.py --cfg cfg/max_cover_rail.yaml --lr 1e-5 --reg 0.15 --timestamp cardnn_notto_hgs_rail-4;
CUDA_VISIBLE_DEVICES=2 python max_cover_cardnn-notto-hgs.py --cfg cfg/max_cover_rail.yaml --lr 1e-5 --reg 0.15 --timestamp cardnn_notto_hgs_rail-5;


