# rand500
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand500.yaml --lr 1e-1 --reg 10 --timestamp rand500-1-1-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand500.yaml --lr 1e-1 --reg 100 --timestamp rand500-1-2-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand500.yaml --lr 1e-1 --reg 500 --timestamp rand500-1-3-1;

CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand500.yaml --lr 1e-2 --reg 10 --timestamp rand500-2-1-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand500.yaml --lr 1e-2 --reg 100 --timestamp rand500-2-2-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand500.yaml --lr 1e-2 --reg 500 --timestamp rand500-2-3-1;

CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand500.yaml --lr 1e-3 --reg 10 --timestamp rand500-3-1-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand500.yaml --lr 1e-3 --reg 100 --timestamp rand500-3-2-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand500.yaml --lr 1e-3 --reg 500 --timestamp rand500-3-3-1;

CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand500.yaml --lr 1e-4 --reg 10 --timestamp rand500-4-1-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand500.yaml --lr 1e-4 --reg 100 --timestamp rand500-4-2-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand500.yaml --lr 1e-4 --reg 500 --timestamp rand500-4-3-1;

CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand500.yaml --lr 1e-5 --reg 10 --timestamp rand500-5-1-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand500.yaml --lr 1e-5 --reg 100 --timestamp rand500-5-2-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand500.yaml --lr 1e-5 --reg 500 --timestamp rand500-5-3-1;

# rand1000
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand1000.yaml --lr 1e-1 --reg 10 --timestamp rand1000-1-1-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand1000.yaml --lr 1e-1 --reg 100 --timestamp rand1000-1-2-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand1000.yaml --lr 1e-1 --reg 500 --timestamp rand1000-1-3-1;

CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand1000.yaml --lr 1e-2 --reg 10 --timestamp rand1000-2-1-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand1000.yaml --lr 1e-2 --reg 100 --timestamp rand1000-2-2-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand1000.yaml --lr 1e-2 --reg 500 --timestamp rand1000-2-3-1;

CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand1000.yaml --lr 1e-3 --reg 10 --timestamp rand1000-3-1-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand1000.yaml --lr 1e-3 --reg 100 --timestamp rand1000-3-2-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand1000.yaml --lr 1e-3 --reg 500 --timestamp rand1000-3-3-1;

CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand1000.yaml --lr 1e-4 --reg 10 --timestamp rand1000-4-1-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand1000.yaml --lr 1e-4 --reg 100 --timestamp rand1000-4-2-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand1000.yaml --lr 1e-4 --reg 500 --timestamp rand1000-4-3-1;

CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand1000.yaml --lr 1e-5 --reg 10 --timestamp rand1000-5-1-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand1000.yaml --lr 1e-5 --reg 100 --timestamp rand1000-5-2-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rand1000.yaml --lr 1e-5 --reg 500 --timestamp rand1000-5-3-1;

# rail
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rail.yaml --lr 1e-1 --reg 10 --timestamp rail-1-1-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rail.yaml --lr 1e-1 --reg 100 --timestamp rail-1-2-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rail.yaml --lr 1e-1 --reg 500 --timestamp rail-1-3-1;

CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rail.yaml --lr 1e-2 --reg 10 --timestamp rail-2-1-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rail.yaml --lr 1e-2 --reg 100 --timestamp rail-2-2-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rail.yaml --lr 1e-2 --reg 500 --timestamp rail-2-3-1;

CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rail.yaml --lr 1e-3 --reg 10 --timestamp rail-3-1-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rail.yaml --lr 1e-3 --reg 100 --timestamp rail-3-2-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rail.yaml --lr 1e-3 --reg 500 --timestamp rail-3-3-1;

CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rail.yaml --lr 1e-4 --reg 10 --timestamp rail-4-1-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rail.yaml --lr 1e-4 --reg 100 --timestamp rail-4-2-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rail.yaml --lr 1e-4 --reg 500 --timestamp rail-4-3-1;

CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rail.yaml --lr 1e-5 --reg 10 --timestamp rail-5-1-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rail.yaml --lr 1e-5 --reg 100 --timestamp rail-5-2-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_rail.yaml --lr 1e-5 --reg 500 --timestamp rail-5-3-1;

# twitch
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_twitch.yaml --lr 1e-1 --reg 10 --timestamp twitch-1-1-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_twitch.yaml --lr 1e-1 --reg 100 --timestamp twitch-1-2-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_twitch.yaml --lr 1e-1 --reg 500 --timestamp twitch-1-3-1;

CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_twitch.yaml --lr 1e-2 --reg 10 --timestamp twitch-2-1-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_twitch.yaml --lr 1e-2 --reg 100 --timestamp twitch-2-2-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_twitch.yaml --lr 1e-2 --reg 500 --timestamp twitch-2-3-1;

CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_twitch.yaml --lr 1e-3 --reg 10 --timestamp twitch-3-1-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_twitch.yaml --lr 1e-3 --reg 100 --timestamp twitch-3-2-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_twitch.yaml --lr 1e-3 --reg 500 --timestamp twitch-3-3-1;

CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_twitch.yaml --lr 1e-4 --reg 10 --timestamp twitch-4-1-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_twitch.yaml --lr 1e-4 --reg 100 --timestamp twitch-4-2-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_twitch.yaml --lr 1e-4 --reg 500 --timestamp twitch-4-3-1;

CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_twitch.yaml --lr 1e-5 --reg 10 --timestamp twitch-5-1-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_twitch.yaml --lr 1e-5 --reg 100 --timestamp twitch-5-2-1;
CUDA_VISIBLE_DEVICES=3 python max_cover_egn-naive.py --cfg cfg/max_cover_twitch.yaml --lr 1e-5 --reg 500 --timestamp twitch-5-3-1;

