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https://www.phoronix.com/news/AMD-Versal-2-Linux-Upstreaming
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AMD Begins Work Upstreaming More Versal 2 SoC Support For Linux
|
Michael Larabel
|
Back in April AMD announced the Versal Gen 2 Adaptive SoCs for AI-driven embedded systems. In preparing for Versal2 evaluation kits expected around the middle of the year and production silicon by the end of 2025, AMD software engineers have begun ramping up their open-source and upstream-focused Linux driver support.
The Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 SoCs were announced back in April for these chips with Arm Cortex-A78AE cores focused on providing end-to-end acceleration for embedded systems. Ahead of their availability expected in 2025, the Linux upstreaming effort has become more apparent in recent weeks.
Up until recently there hasn't been much in the way of AMD "Versal2" patches for the Linux kernel... Back in July was the start and just consisted of some patches for the AMD Versal Gen 2 DMA IP. Since last month though it's been picking up with new patches like enabling Versal Gen 2 10GbE network device support. Versal Gen2 is relying on Cadence Macb for 10G / 5G / 2.5G / 1G networking support -- a big improvement over the 1G support in the original AMD-Xilinx Versal. Plus there has been SPI driver patches for device reset support and other bits.
The very latest today is AMD engineers posting a set of patches for the AMD MDB "pcie-amd-mdb" Linux kernel driver. MDB in this context is the Multimedia DMA Bridge and is a new IP core with Versal Gen2. The Multimedia DMA Bridge module on Versal Gen2 works for providing PCIe Gen5 controller support on this SoC and is relying on Synopsys DesignWare IP. Those AMD MDB driver patches for Linux were posted today to the kernel mailing list and are beginning to undergo review.
It's good seeing this AMD Versal Gen2 SoC support coming about and hopefully all the features / IP blocks will be wired up to upstream and open-source Linux kernel driver support by the time the production silicon is out in late 2025.
| 1
| 1,760,718,839.826838
|
https://www.phoronix.com/news/AMD-Per-Core-Energy-Linux-6.14
|
AMD Per-Core Energy Counter Support Slated For Linux 6.14
|
Michael Larabel
|
While the Linux 6.13 merge window just closed yesterday in landing all of the new features and functionality for that first kernel version of 2025, already for the Linux 6.14 kernel cycle to follow a feature was queued up early this morning in a TIP branch: AMD per-core energy counter support.
The past few months AMD Linux engineers have been working on per-core energy counter support under the Linux Runtime Average Power Limiting (RAPL) infrastructure. After going through the v7 patches, they are now ready for the mainline Linux kernel once Linux 6.14 rolls around with its merge window in late January / early February.
The AMD per-core energy counter patch series explains:
"Currently the energy-cores event in the power PMU aggregates energy consumption data at a package level. On the other hand the core energy RAPL counter in AMD CPUs has a core scope (which means the energy consumption is recorded separately for each core). Earlier efforts to add the core event in the power PMU had failed [1], due to the difference in the scope of these two events. Hence, there is a need for a new core scope PMU.
This patchset adds a new "power_core" PMU alongside the existing "power" PMU, which will be responsible for collecting the new "energy-core" event.
Tested the package level and core level PMU counters with workloads pinned to different CPUs." As of this morning, the patches were picked up by the tip/tip.git's perf/core branch.
With the patches now queued as part of the TIP branch and with two months to go until the Linux 6.14 cycle, it looks like the per-core energy counter support is ready to roll with that next kernel cycle. Linux 6.14 is also going to be exciting for AMD customers with the AMDXDNA driver ready for inclusion in supporting the Ryzen AI NPU on the mainline Linux kernel.
| 2
| 1,760,718,840.26392
|
https://www.phoronix.com/news/AMD-CDNA-GFX9.4.4-FW
|
AMD GFX9.4.4 CDNA Firmware Published, More GFX950 Changes Point To Being MI350
|
Michael Larabel
|
There are some new open-source/Linux details to note when it comes to the AMD accelerators in the Instinct "CDNA" land.
Since writing last week about AMD GFX950 patches beginning to appear within the LLVM 20 Git codebase for the AMDGPU shader back-end, GFX950 patches have continued and are on the heavier side...
As of writing there are now 77 pull requests relating to the AMD GFX950 with the compiler back-end support and more than 62 patches have been merged so far into LLVM Git. These pulls are for supporting a number of new instructions with GFX950, a new scheduler model, and other changes but mostly pertaining to new instructions with the GFX950 target.
With all of these GFX950 changes building up over the existing GFX94x targets, it would seem to align with being for the Instinct MI350 series due out in 2025 rather than the MI325X... Plus if GFX950 was the MI325X, AMD's open-source upstream driver support there would be very tardy and much later than we are used to seeing of new hardware support upstreamed months in advance of launch. So given the timing of this GFX950 upstreaming work and the number of changes, it's looking more solid that GFX950 is indeed the graphics IP of the Instinct MI350 series.
Separately, hitting the linux-firmware.git tree of firmware binaries today were a number of AMD GPU updates/additions. Notable there is adding GC 9.4.4 firmware. The timing of that and AMD typically not committing public firmware binaries until closer to new launches would seem to indicate that GC 4.4.4 / GFX944 correlates to the Instinct MI325X.
Also added alongside GC 9.4.4 were PSP 13.0.14, SDMA 4.4.5, and SMU 13.0.14 IP firmware. Plus updates to the firmware files for many existing Instinct/Radeon products.
Long story short, AMD's open-source/Linux graphics driver engineers remain quite busy with GFX950 enablement that looks like it is for the Instinct MI350 series. This follows the engineers having spent the past several months prior working on the RDNA4 upstreaming on the consumer Radeon side to prep for launch-day Linux support.
| 1
| 1,760,718,840.846439
|
https://www.phoronix.com/news/AMD-Zen-5-Perf-Events-Linux-613
|
New AMD Zen 5 Perf Events Going Into Linux 6.13
|
Michael Larabel
|
Sent out last night for the ongoing Linux 6.13 merge window were all of the perf tool changes for the wonderful "perf" subsystem for performance profiling and the like. In addition to adding the HWMON PMU to "perf stat", leader sampling for inherited task events, and various other tooling improvements, there are also vendor event updates. Most notable with the updated CPU vendor events are new AMD Zen 5 processor events.
The AMD Zen 5 additions with the perf updates for Linux 6.13 include adding new data fabric events, data fabric metrics, and updated data cache fill events.
There are new data fabric events around read/write data beats to each DRAM channel, upstream DMA read/write data beats between local sockets and each I/O root complex, inbound data beats between local sockets and core-to-fabric interfaces, and outbound data beats between local sockets and remote sockets via cross-socket links. The new data fabric metrics for Zen 5 are around DRAM read/write bandwidth for local and remote sockets as well as DMA read/write bandwidth and core inbound/outbound data bandwidth.
These AMD Zen 5 perf event additions will benefit the new AMD EPYC 9005 "Turin" servers and whatever additional EPYC Zen 5 processors follow.
More details on these perf event updates for Zen 5 and other perf tool changes for this next version of the Linux kernel, see this pull request.
| 1
| 1,760,718,841.820859
|
https://www.phoronix.com/news/AMD-I3C-DW-Linux-6.13
|
AMD I3C Controller ACPI Support Added To DesignWare Driver In Linux 6.13
|
Michael Larabel
|
The I3C subsystem updates were submitted for the Linux 6.13 kernel on Monday and include support for another I3C HCI controller used on AMD systems.
The MIPI I3C updates for the Linux 6.13 kernel are mostly on the smaller side with just some core fixes but adding support for the AMD I3C controller via ACPI within the DesignWare driver.
AMD support is added onto the Synopsys DesignWare I3C master driver that is used by several different hardware vendors. The dw-i3c-master driver adds the "AMDI0015" ACPI device ID so it can be properly loaded on AMD platforms via ACPI. Beyond that ID and one qurik, it's following all of the common DesignWare I3C driver code paths. As for the one AMD I3C quirk:
"The AMD Legacy I3C is having a problem with its IP, specifically with the push-pull and open-drain pull-up registers. These registers need to be manually programmed for every CCC submission to align with the duty cycle. Therefore, add a quirk to address this issue." This AMD I3C DesignWare driver support will ultimately help out modern AMD EPYC servers.
The patch series for these dw-i3c-master additions from AMD explains:
"The AMD EPYC platform design has DIMMs connected over the I3C bus, with each DIMM containing three components: SPD, PMIC, and RCD.
To access component-specific information within the DIMMs, such as initial dynamic address, static address, and provisional ID, ACPI support is necessary for the I3C core. This requires adding ACPI binding to the dw-i3c-master driver and retrieving slave information from the AMD ASL.
Currently, the code is closely tied to dt-bindings. This initial set aims to decouple some of these bindings by adding the AMD-specific _HID, enabling the current driver to support ACPI-enabled x86 systems." That AMD addition is the main highlight of the I3C changes for 6.13.
| 2
| 1,760,718,841.974211
|
https://www.phoronix.com/news/AMDXDNA-DRM-Misc-Next
|
AMDXDNA Driver For Ryzen AI Now Ready To Appear In The Linux Kernel
|
Michael Larabel
|
The AMDXDNA kernel driver for Linux systems that was made open-source in January for supporting the Ryzen AI NPU on laptop SoCs going back to the Ryzen 7040 "Phoenix" series is now one step away from appearing in the mainline Linux kernel in the near future.
While the AMDXDNA kernel driver was made public and open-source back in January, it wasn't until July that the AMDXDNA driver began its review process to work its way into the upstream Linux kernel. The AMDXDNA driver has gone through eleven rounds of review and revisions over the past few months but is now ready to appear in the mainline kernel.
Following the AMDXDNA v11 patches being posted, on Friday the AMDXDNA driver patches were merged into the drm-misc-next branch. With that when the drm-misc-next is then pulled into DRM-Next, it's then going to the mainline Linux kernel.
The timing is a bit of a tough spot. This more than likely means we'll see the AMDXDNA driver debut for the Linux 6.14 kernel cycle. We are half-way through the two week Linux 6.13 merge window. Typically new drivers can be added late since it doesn't risk regressing existing hardware support. But as drm-misc-next already has a variety of other non-AMDXDNA patches queuing, it doesn't look like they'll try a secondary pull of changes to DRM-Next in the coming days and to then squeeze into the current Linux 6.13 cycle. So short of any last minute wrangling over the coming days, the AMDXDNA driver is destined to appear in the Linux 6.14 kernel rather than the current Linux 6.13 cycle.
In any event it's now an achievement that the AMDXDNA driver has been picked up into drm-misc-next as it's now taken care of all the necessary changes to be an upstreamed accelerator driver.
It's been a long journey for the AMDXDNA driver especially with the Ryzen AI NPUs appearing in notebooks now for nearly two years, but nevertheless it's open-source and finally ready for the mainline kernel. Assuming AMDXDNA goes into Linux 6.14 rather than squeezing it into Linux 6.13, the v6.14 kernel stable release will be out around April~May.
Over in user-space, the AMD Xilinx XRT and AMD AIE Plugin for IREE allow for interacting with the Ryzen AI NPU by way of this kernel driver. There is also supposed to be coming the AMD Unified AI Software Stack that prior indications would be around the end of 2024... There's just a few weeks left to the calendar year so we will see if it makes it or not before the end of Q4. Whether that AMD Unified AI Software Stack brings a new user-space solution or just layers atop say the IREE plug-in remains to be seen.
| 11
| 1,760,718,842.81006
|
https://www.phoronix.com/news/Linux-6.13-AMD-CPU
|
Many AMD CPU Feature Additions Land In Linux 6.13
|
Michael Larabel
|
The in-development Linux 6.13 kernel is bringing a lot of exciting improvements for AMD Linux customers.
In addition to AMD P-State being the default now for 5th Gen EPYC CPUs rather than the generic ACPI CPUFreq driver to provide greater power efficiency, there is a lot more in tow. There is also the introduction of the AMD 3D V-Cache Optimizer driver and other changes. Merged yesterday providing several new AMD features was the x86/cpu pull request that is predominantly AMD processor changes. The x86/cpu highlights for the Linux 6.13 merge window include:
- Add a feature flag which denotes AMD CPUs supporting workload classification with the purpose of using such hints when making scheduling decisions
- Determine the boost enumerator for each AMD core based on its type: efficiency or performance, in the cppc driver
- Add the type of a CPU to the topology CPU descriptor with the goal of supporting and making decisions based on the type of the respective core
- Add a feature flag to denote AMD cores which have heterogeneous topology and enable SD_ASYM_PACKING for those
- Check microcode revisions before disabling PCID on Intel
- Cleanups and fixlets A lot continues to be going on around better supporting AMD heterogeneous processors under Linux with a mix of performance "classic" and efficiency "dense" cores. There's the AMD heterogeneous topology patches in this pull, workload classification bits, and other bits.
Separately was also the x86/sev pull request of AMD Secure Encrypted Virtualization (SEV) updates for Linux 6.13:
- Do the proper memory conversion of guest memory in order to be able to kexec kernels in SNP guests along with other adjustments and cleanups to that effect
- Start converting and moving functionality from the sev-guest driver intocore code with the purpose of supporting the secure TSC SNP feature where the hypervisor cannot influence the TSC exposed to the guest anymore
- Add a "nosnp" cmdline option in order to be able to disable SNP support in the hypervisor and thus free-up resources which are not going to be used Plus other AMD changes still coming for Linux 6.13 by way of the x86 platform drivers and AMDGPU/AMDKFD kernel graphics driver changes, among updates in other subsystems too for AMD's growing variety of products.
| 5
| 1,760,718,843.767199
|
https://www.phoronix.com/news/AMD-Bus-Lock-Trap-Linux-6.13
|
AMD Bus Lock Trap Support Merged For Linux 6.13
|
Michael Larabel
|
Going back to early in the year AMD Linux engineers began preparing support for a new Bus Lock Trap feature with Zen 5 CPUs. With the in-development Linux 6.13 kernel that support is being merged.
Years after Intel Linux engineers worked out the split lock detection and bus lock detection for the Linux kernel and their processors to warn or kill on offending applications given the negative performance impact those locks can have on overall system performance, AMD Zen 5 systems running Linux 6.13+ will be able to leverage Bus Lock Trap.
The AMD Bus Lock Trap support with modern Ryzen/EPYC Zen 5 processors is now wired up with Linux 6.13. The Linux kernel code builds off the foundation laid out by Intel engineers. The AMD Bus Lock Trap feature will raise a #DB exception on occurrence of a bus lock when outside of the kernel (ring zero). Knowing about bus/split locks with either a warning or killing the app can be important for overall system performance health.
The work had been queued ahead of Linux 6.12 but the tip/tip.git's x86/splitlock branch ultimately wasn't sent in for the prior merge window. This week though the code was submitted and since merged for Linux 6.13.
With Linux 6.13 the split lock detection and bus lock detection is also now behind a "CONFIG_X86_BUS_LOCK_DETECT" Kconfig build time switch for those wishing to toggle the support. More details on the functionality can be found via the kernel documentation.
| 0
| 1,760,718,844.45971
|
https://www.phoronix.com/news/Linux-Clear-VMLOAD-VMSAVE-Zen4
|
Linux Fixes Hosts Randomly Rebooting During Virtualization With Ryzen 7000/8000 CPUs
|
Michael Larabel
|
Ahead of the Linux 6.12 kernel release expected today there is a last minute "x86/urgent" pull request. Notable with this last minute x86 urgent fixes for Linux 6.12 -- and also to be back-ported to prior kernel versions -- is working around an issue with AMD Ryzen Zen 4 client processors such as the Ryzen 7000/8000 series processors when making use of virtualization that could lead to the host randomly being rebooted.
The issue originates from this bug report back in July over random host rebooots when using AMD Ryzen 7000/8000 series CPUs and using nested virtual machines. The bug report noted:
"Running nested VMs on AMD Ryzen 7000/8000 (ZEN4) CPUs results in random host's reboots.
There is no kernel panic, no log entries, no relevant output to serial console. It is as if platform is simply hard reset. It seems time to reproduce it varies from system to system and can be dependent on workload and even specific CPU model." Fast forward several months, the issue is that VMLOAD/VMSAVE support is being wrongly advertised on the Zen 4 client processors. So the change for Linux 6.12 and prior stable kernel versions is to clear the VMLOAD/VMSAVE capability for the Zen 4 client SoCs. VMLOAD/VMSAVE remains supported and enabled for the AMD EPYC 4004/8004/9004 server processors with this issue just affecting the Ryzen client processors.
The patch by AMD Linux engineer Mario Limonciello explains:
"A number of Zen4 client SoCs advertise the ability to use virtualized VMLOAD/VMSAVE, but using these instructions is reported to be a cause of a random host reboot.
These instructions aren't intended to be advertised on Zen4 client so clear the capability." This fix is in the x86/urgent pull request. Also on the AMD side there is a fix for for a Kdump kernel failure on AMD Secure Memory Encryption (SME) systems when the kernel is built with CONFIG_IMA_KEXEC enabled.
| 36
| 1,760,718,844.647002
|
https://www.phoronix.com/news/AMD-3DV-Optimizer-Linux-6.13
|
AMD 3D V-Cache Optimizer Driver To Be Merged For Linux 6.13
|
Michael Larabel
|
Last month AMD Linux engineers posted patches for a 3D V-Cache Optimizer driver for Linux that allows the user to communicate their cache vs. frequency preference depending upon workload and for the 3D V-Cache processors where some CCDs have the larger cache but not all. That driver is now ready for appearing in the upcoming Linux 6.13 kernel.
The Ryzen X3D processors with 3D V-Cache for some core complex dies (CCDs) but not all can now have a bias set under Linux whether it should be optimized for frequency mode or cache mode. When the 3D V-Cache optimizer driver is set to frequency mode, cores with the faster CCD are prioritized over the larger cache but lower clocked CCD.
Alternatively, the "cache mode" of the 3D V-Cache Optimizer Driver sets the preference to cores within the CCD where there is the larger L3 cache before the CCD with the smaller L3 cache.
The 3D V-Cache frequency vs. cache mode preference with this driver can be set by users via the /sys/bus/platform/drivers/amd_x3d_vcache/AMDI0101\:00/amd_x3d_mode file. Writing a value to that sysfs file of "frequency" will set the frequency mode while "cache" will set the cache mode. Of course, reading from that file will tell you what mode the optimizer driver is currently functioning.
As of yesterday the AMD 3D V-Cache Optimizer Driver "amd_3d_vcache" was queued into platform-drivers-x86.git's for-next branch. With it hitting that branch, it's now set to be merged for the upcoming Linux 6.13 merge window. The Linux 6.13 merge window is expected to begin next week while the stable Linux 6.13 kernel won't be out until around late January or early February. Some Linux distributions though like CachyOS have already decided to back-port this driver for their kernel builds.
| 17
| 1,760,718,845.455691
|
https://www.phoronix.com/news/AMD-ZenDNN-5.0-Released
|
AMD Releases ZenDNN 5.0 For Deep Neural Network Library Optimized For Zen 5 EPYC
|
Michael Larabel
|
AMD ZenDNN 5.0 was rolled out this morning as the newest version of this deep neural network library that is compatible with Intel's oneDNN APIs and infrastructure. ZenDNN 5.0 is now optimized for AMD Zen 5 processors such as the EPYC 9005 series. ZenDNN 5.0 also ships performance enhancements for generative large language models (LLMs) with its PyTorch plug-in.
ZenDNN 5.0 is optimized for 5th Gen AMD EPYC "Turin" processors while it will also work better than prior ZenDNN releases on the new Ryzen 9000 series Zen 5 desktop processors. ZenDNN 5.0 is also compatible with the AMD BLIS 5.0 library, EPYC-specific enhancements to MATMUL operators and related fusions, aut-tuning for BF16, performance enhancements focused on LLMs, optimized Scalar Dot Product Attention (SDPA), support for BF16 precision within the Recommender System models in PyTorch, and graph optimizations and pattern matching improvements within the PyTorch plug-in.
ZenDNN 5.0 has been tested with TensorFlow 2.16+ and PyTorch 2.0+. This morning's ZenDNN 5.0 release announcement notes:
"The focus of the ZenDNN 5.0 release is on delivering support for Zen5 AMD EPYC™ architectures, as well as performance enhancements for generative LLM models through the PyTorch plug-in. The list of models supported includes architectures such as Llama2 and Llama3, Phi2, Phi3, Qwen, ChatGLM, and GPT. The release also delivers performance improvements to non generative LLM models such as BERT." AMD ZenDNN is available under an Apache 2.0 license.
| 4
| 1,760,718,846.293734
|
https://www.phoronix.com/news/AMD-Next-Gen-Fortran-Compiler
|
AMD Developing Next-Gen Fortran Compiler Based On Flang, Optimized For AMD GPUs
|
Michael Larabel
|
AMD today went public with details on the "AMD Next-Gen Fortran Compiler" as a new Fortran compiler they are working on based on LLVM's Flang.
The AMD Next-Gen Fortran Compiler is a new open-source Fortran compiler focused on OpenMP offloading to AMD GPUs with a direct interface to ROCm and HIP.
This downstream of Flang is focused on AMD GPU offloading and interacting with the ROCm compute stack. This downstream is open-source and tested across various Linux distributions while using the ROCm driver.
This is akin to AMD's AOMP compiler efforts as their LLVM downstream focused on providing the latest OpenMP offload support to AMD GPUs... But at least for now this "next-gen" compiler is being developed via a separate codebase from AOMP.
This also isn't to be confused with AMD's CPU compiler efforts... Over in AOCC land for the AMD Optimizing C/C++ Compiler they have already been shipping a Flang version for Fortran support catered to the AMD Zen-based processors. But with this Next-Gen Fortran Compiler it's on the GPU front. Yes, AMD's multiple downstreams of LLVM for different product families can get a bit confusing and overlapping in some areas.
AMD today published this ROCm blog post outlining their Next-Gen Fortran Compiler. For now at least the GitHub repository being worked on for this new Fortran compiler is under AMD's InfinityHub CI tree.
| 23
| 1,760,718,846.449027
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https://www.phoronix.com/news/GCC-AVX512-Two-Epi-AMD-Zen-5
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GCC 15 Lands New Optimization For AMD Zen 4 & Zen 5 CPUs
|
Michael Larabel
|
Merged today for the upcoming GCC 15 stable release is a new "X86_TUNE_AVX512_TWO_EPILOGUES" tuning optimization that is enabled by default for AMD Zen 4 and Zen 5 processors.
SUSE compiler engineer Richard Biener wrote the patch adding this "X86_TUNE_AVX512_TWO_EPILOGUES" tuning and its default enabling when targeting either AMD Zen 4 or AMD Zen 5 processors. Biener explains in the now committed patch:
"The following adds X86_TUNE_AVX512_TWO_EPILOGUES tuning and directs the vectorizer to produce both a vector AVX2 and SSE epilogue for AVX512 vectorized loops when set. The tuning is enabled by default for Zen4 and Zen5 where I benchmarked it to be overall positive on SPEC CPU 2017 both in performance and overall code size. In particular it speeds up 525.x264_r which with only an AVX2 epilogue ends up in unvectorized code at the moment." No firm numbers from SPEC CPU 2017 or any other benchmarks were shared for helping to quantify the actual performance impact of this additional AMD Zen 5/4 tuning.
With the patch now in Git it will be part of the upcoming GCC 15.1 stable release due out in the early months of 2025.
| 7
| 1,760,718,847.4601
|
https://www.phoronix.com/news/AMD-XDNA-Linux-Driver-v9
|
AMD's Ninth Iteration Of Their XDNA Linux Driver Posted For Ryzen AI
|
Michael Larabel
|
Yesterday brought the eighth and ninth iteration of the AMD XDNA Linux kernel driver posted for review for enabling the Ryzen AI branded NPUs found in their recent SoCs.
On Monday the AMD XDNA v8 driver patches were posted for review followed by another iteration of that due to a miss-merged line accidentally in the v8 patches. This open-source kernel driver continues to be refined by AMD for supporting the AMD Ryzen AI NPUs that have been found in the Ryzen laptops for roughly the past two years.
The AMD XDNA kernel driver goes along with AMD's XRT and AIE Plugin for IREE user-space components for getting AI workloads like ONNX RT working atop the neural processing unit hardware. The AMD XDNA kernel driver is open-source but does depend upon a closed-source binary, similar to the state of most GPU drivers these days.
It was just early in 2024 that AMD made the XDNA kernel driver code public on GitHub while the past few months have been working on getting the code reviewed to get it upstreamed for the mainline kernel. But as far as when this AMD Ryzen AI kernel driver will be upstreamed remains to be seen. The driver is settling down and there has been less churn between XDNA driver revisions. The Linux 6.13 merge window is slated to open next week and will then be open for the following two weeks. But with the v8/v9 patches only published yesterday, it remains to be seen if upstream maintainers are happy with the latest condition of the driver and if they'll be comfortable ushering it along for the Linux v6.13 cycle. Otherwise we're looking at Linux v6.14 for the AMD XDNA driver to potentially be merged and then will be found in stable Linux distributions in the spring~summer of 2025.
Those wanting to try out the latest AMD XDNA kernel driver now for Ryzen AI hardware can find it on the Linux kernel mailing list.
| 5
| 1,760,718,848.424008
|
https://www.phoronix.com/news/AMD-ERAPS-Linux
|
Linux Preps New AMD ERAPS Feature With EPYC Turin To Benefit Performance
|
Michael Larabel
|
Posted to the Linux kernel mailing list last week and now queued already via tip/tip.git's "x86/cpu" Git branch is support for a new AMD CPU feature we haven't heard about until now... ERAPS, the Enhanced Return Address Prediction Security.
AMD ERAPS (Enhanced Return Address Prediction Security) hasn't yet appeared in AMD's public official programming documentation (besides simply noting the bit position of the ERAPS indicator) nor was it mentioned as part of the EPYC 9005 "Turin" series briefings.
AMD ERAPS aims to help recover some of the performance of security mitigations introduced following the Spectre class vulnerabilities over the past several years. ERAPS is a new defense for mitigating certain classes of speculative attacks such as Return Stack Buffer (RSB) poisoning attacks.
The message on the patch allowing the Linux kernel to make use of ERAPS on Turin and future processors further explains:
"Remove explicit RET stuffing / filling on VMEXITs and context switches on AMD CPUs with the ERAPS feature (Zen5).
With the Enhanced Return Address Prediction Security feature, any hardware TLB flush results in flushing of the RSB (aka RAP in AMD spec). This guarantees an RSB flush across context switches. The feature also explicitly tags host and guest addresses - eliminating the need for explicit flushing of the RSB on VMEXIT.
The BTC_NO feature in AMD CPUs ensures RET predictions do not speculate from outside the RSB. Together, the BTC_NO and ERAPS features ensure no flushing or stuffing of the RSB is necessary anymore."
With this AMD ERAPS feature now in TIP's x86/cpu branch, it's likely going to be merged for the upcoming Linux 6.13 cycle.
I will be checking out this new AMD ERAPS enablement for the Linux kernel to see if it provides any measurable benefit to the performance for the new EPYC 9005 series server processors across real-world workloads.
| 1
| 1,760,718,848.452077
|
https://www.phoronix.com/news/AMD-Hetero-Topo-Linux-6.13
|
AMD Heterogeneous CPU Design Topology Patches Coming For Linux 6.13
|
Michael Larabel
|
The latest patches from AMD Linux engineers for working on x86 heterogeneous design identification were queued last week for introduction in the Linux 6.13 kernel.
The x86 Heterogeneous design identification patch series was queued last week into tip/tip.git's "x86/cpu" Git branch, thereby making it material for adding to the Linux 6.13 merge window barring any last minute issues from coming to light. As explained there by AMD Linux engineer Mario Limonciello:
"This series adds topology identification for Intel and AMD processors and uses this identification in the AMD CPPC code to identify the boost numerator.
This series was previously submitted as, but this was based on some patches in linux-pm/linux-next that will be dropped.
Instead the series is now based on tip/master.
This also pulls one patch from Pawan's series and adjusts it for all feedback while adding AMD support at the same time." As part of the patch series is the patch to use the heterogeneous core topology for identifying the boost numerator:
"AMD heterogeneous designs include two types of cores:
* Performance
* Efficiency
Each core type has different highest performance values configured by the platform. Drivers such as `amd_pstate` need to identify the type of core to correctly set an appropriate boost numerator to calculate the maximum frequency.
X86_FEATURE_AMD_HETEROGENEOUS_CORES is used to identify whether the SoC supports heterogeneous core type by reading CPUID leaf Fn_0x80000026.
On performance cores the scaling factor of 196 is used. On efficiency cores the scaling factor is the value reported as the highest perf. Efficiency cores have the same preferred core rankings." Another patch added to tip/tip.git's x86/cpu branch is for introducing the AMD Workload Classification feature bit. This indicates whether the CPU supports workload-based heuristic feedback to the OS for scheduling decisions.
These patches are just the latest in long running work going on months for better optimizing current and future AMD processors that feature a mix of classic (performance) and dense (efficiency) CPU cores for better power and performance handling under Linux.
The Linux 6.13 merge window will be opening up during the back half of November while the stable kernel will be out in February.
| 7
| 1,760,718,849.428752
|
https://www.phoronix.com/news/AMD-New-SRSO-Inception-Linux
|
AMD Posts New Linux Mitigation Handling For SRSO/Inception
|
Michael Larabel
|
AMD Linux engineer Borislav Petkov kicked off the new week by volleying a patch for adjusting the Speculative Return Stack Overflow (SRSO, a.k.a. "Inception") vulnerability mitigation handling for capabilities to be found with affected processors running on newer CPU microcode.
SRSO/Inception as a reminder was made public in August 2023 as a vulnerability with AMD CPUs from Zen 1 to Zen 4. Per the kernel.org documentation as a refresher:
"AMD CPUs predict RET instructions using a Return Address Predictor (aka Return Address Stack/Return Stack Buffer). In some cases, a non-architectural CALL instruction (i.e., an instruction predicted to be a CALL but is not actually a CALL) can create an entry in the RAP which may be used to predict the target of a subsequent RET instruction.
The specific circumstances that lead to this varies by microarchitecture but the concern is that an attacker can mis-train the CPU BTB to predict non-architectural CALL instructions in kernel space and use this to control the speculative target of a subsequent kernel RET, potentially leading to information disclosure via a speculative side-channel." While AMD Zen 5 on Linux has been reporting "not affected" to the SRSO/Inception vulnerability today's kernel patch may help better control the SRSO mitigation for prior Ryzen and EPYC CPUs. The patch out today is around two new bits of "SRSO_USER_KERNEL_NO" for indicating the CPU is not subject to SRSO across user/kernel boundaries and "SRSO_MSR_FIX" for indicating that software can use the BpSpecReduce path for mitigating SRSO.
The patch from Petkov explains:
"If the machine has:
CPUID Fn8000_0021_EAX[30] (SRSO_USER_KERNEL_NO) -- If this bit is 1, it indicates the CPU is not subject to the SRSO vulnerability across user/kernel boundaries.
have it fall back to IBPB on VMEXIT only, in the case it is going to run VMs:
Speculative Return Stack Overflow: CPU user/kernel transitions protected, falling back to IBPB-on-VMEXIT Speculative Return Stack Overflow: Mitigation: IBPB on VMEXIT only
Then, upon KVM module load and in case the machine has
CPUID Fn8000_0021_EAX[31] (SRSO_MSR_FIX). If this bit is 1, it indicates that software may use MSR BP_CFG[BpSpecReduce] to mitigate SRSO.
enable this BpSpecReduce bit to mitigate SRSO across guest/host boundaries." Both SRSO_USER_KERNEL_NO and SRSO_MSR_FIX are mentioned in this February 2024 whitepaper on a technical update around SRSO. It's not clear though why it has taken one and a half years for the Linux kernel to now be adapted for the "new" SRSO_MSR_FIX and SRSO_USER_KERNEL_NO capabilities. In any event, this kernel patch is now out for review on the Linux kernel mailing list to adapt the SRSO mitigation.
| 0
| 1,760,718,850.272759
|
https://www.phoronix.com/news/AMD-Ryzen-7-9800X3D
|
AMD Formally Announces Ryzen 7 9800X3D Specs - Should Be Great For Linux Creators
|
Michael Larabel
|
AMD has been teasing the Ryzen 9000X3D Zen 5 CPUs with 3D V-Cache and today they formally announced the specs of the Ryzen 7 9800X3D processor that will begin shipping 7 November.
The Ryzen 7 9800X3D is AMD's 8-core / 16-thread processor with 64MB of 3D V-Cache. This uses 2nd Gen AMD 3D V-Cache where the 64MB of cache is now underneath the processor cores so that the CCD is positioned closer to the heatsink/cooler. The intent is that the new 3D V-Cache processors will run cooler than prior generation 3D V-Cache processors.
The AMD Ryzen 7 9800X3D will boost up to 5.2GHz and feature a 4.7GHz while total it provides 104MB of cache. This 120 Watt processor will have a suggested retail price of $479 USD. Again, expect retail availability on 7 November.
Under Microsoft Windows 11, AMD is promoting the Ryzen 7 9800X3D today as the new leading gaming processor with 8% uplift over the Ryzen 7 7800X3D and up to an average 20% gaming improvement over the Intel Core Ultra 9 285K Arrow Lake processor. That's under Windows with a focus on gaming... Expect many Linux benchmarks to come at launch.
More details on the Ryzen 7 9800X3D specs via AMD.com.
| 57
| 1,760,718,850.328458
|
https://www.phoronix.com/news/AMD-STB-For-Desktop-Ryzen
|
AMD STB Support Extended To Latest Ryzen 9000 Series Desktop CPUs
|
Michael Larabel
|
It turns out the latest AMD Ryzen desktop processors offer support for AMD Smart Trace Buffer (STB) that previously was only limited to mobile platforms.
Sent out today were a set of eight Linux kernel patches around the AMD Platform Management Controller (PMC) driver. Notable there is confirmation that AMD STB support is extended to the latest Ryzen desktop processors. One of the patches confirm the newly-added desktop support:
"Previously, AMD's Ryzen Desktop SoCs did not include support for STB. However, to accommodate this recent change, PMFW has implemented a new message port pair mechanism for handling messages, arguments, and responses, specifically designed for distinguishing from Mobile SoCs. Therefore, it is necessary to update the driver to properly handle this incoming change." The patch adds AMD STB support on the desktop side for Family 1Ah Model 44h processors, a.k.a. Ryzen 9000 "Granite Ridge" desktop CPUs.
As previously explained of AMD Smart Trace Buffer, it's a debugging facility to help analyze the last feature that was running on the system before hitting a failure. It's a non-intrusive way for helping to analyze CPU issues with this always-running trace buffer in the background. Now it turns out AMD STB is supported on the latest Ryzen desktop class processors.
The 8 patch series also prepares STB support for Family 1Ah Model 70h processors as well as updating the IP information for newer SoCs.
| 0
| 1,760,718,851.408226
|
https://www.phoronix.com/news/Meltdown-Lite-Zen-5-Linux-Fix
|
Linux Adjusts "Meltdown Lite" Mitigation Handling On Newer Zen 5 CPUs
|
Michael Larabel
|
Linus Torvalds took to some coding himself today to fix a user-address masking non-canonical speculation issue. The Linux kernel needed an adaptation for this "Meltdown Lite" issue due to different behavior with the latest AMD Zen 5 processors.
Linus Torvalds authored and committed today the patch x86: fix user address masking non-canonical speculation issue. In there he explains:
"It turns out that AMD has a "Meltdown Lite(tm)" issue with non-canonical accesses in kernel space. And so using just the high bit to decide whether an access is in user space or kernel space ends up with the good old "leak speculative data" if you have the right gadget using the result:
CVE-2020-12965 “Transient Execution of Non-Canonical Accesses“
Now, the kernel surrounds the access with a STAC/CLAC pair, and those instructions end up serializing execution on older Zen architectures, which closes the speculation window.
But that was true only up until Zen 5, which renames the AC bit. That improves performance of STAC/CLAC a lot, but also means that the speculation window is now open.
Note that this affects not just the new address masking, but also the regular valid_user_address() check used by access_ok(), and the asm version of the sign bit check in the get_user() helpers.
It does not affect put_user() or clear_user() variants, since there's no speculative result to be used in a gadget for those operations." AMD Linux engineer Borislav Petkov commented earlier this week on the Linux kernel mailing list around the difference now with AMD Zen 5 CPUs:
"So I was able to get some info: CLAC/STAC in everything Zen4 and older is serializing so there's no issue there.
Zen5 is a different story and AC is being renamed there and thus, non-serializing. So we'd need to do something there, perhaps something like Josh's patch...
But the good thing is we can alternative it out only for those machines, apart from the rest." The patch is now in the kernel ahead of the Linux 6.12-rc5 release this weekend and will likely be back-ported to existing stable kernel versions over the coming days.
More background information on the prior AMD security issue now adapted for Zen 5 coverage can be found via this security bulletin and via CVE-2020-12965 that was made public back in 2022.
| 15
| 1,760,718,852.512235
|
https://www.phoronix.com/news/PCIe-TPH-For-Linux-6.13
|
PCIe TPH Coming With Linux 6.13 To Further Enhance 5th Gen AMD EPYC Performance
|
Michael Larabel
|
Going back to earlier in the year AMD Linux engineers have been prepping the kernel for PCI Express TLP Processing Hints (TPH) support that allows for hints that can be injected to improve latency and lowering traffic congestion when there are several possible cache locations on the server with the TPH noting the optimal location of a Transaction Layer Packet (TLP). This PCIe TPH support is set to be merged upstream with the forthcoming Linux 6.13 cycle.
PCIe TPH support is an exciting addition to the PCI Express specification. AMD engineers have been pursuing the Linux support for it with this capability being found in the new 5th Gen AMD EPYC "Turin" platform. AMD engineers spent the past several months working out the core Linux infrastructure for PCIe TPH as well as adapting the Broadcom BNXT network driver to demonstrate PCIe TPH usage.
This PCIe TPH support goes along with AMD Smart Data Cache Injection as part of the new I/O functionality with the 5th Gen AMD EPYC server processors. SDCI in turn allows direct insertion of data from I/O devices into the L3 cache.
Queued up this past week into pci.git's "next" Git branch is the "TPH" branch that contains AMD's PCIe TPH enablement work. Thus for the Linux 6.13 merge window kicking off during the back half of November, this TPH functionality should be merged. Linux 6.13 in turn should be out as stable in February. It's too bad AMD wasn't able to get this functionality all upstreamed into the kernel ahead of the EPYC 9005 series debut earlier this month, but in any event it's on the way.
"TPH (TLP Processing Hints) is a PCIe feature that allows endpoint devices to provide optimization hints for requests that target memory space. These hints, in a format called Steering Tags (STs), are embedded in the requester's TLP headers, enabling the system hardware, such as the Root Complex, to better manage platform resources for these requests.
For example, on platforms with TPH-based direct data cache injection support, an endpoint device can include appropriate STs in its DMA traffic to specify which cache the data should be written to. This allows the CPU core to have a higher probability of getting data from cache, potentially improving performance and reducing latency in data processing."
For those interested in PCIe TLP Processing Hints functionality for the Linux kernel can see this documentation commit that goes over all the technical details of the support.
The EPYC 9005 Linux support overall is in great shape besides a few extra new features like PCIe TPH taking longer time to bake and make it upstream. The AMD EPYC 9005 series Linux performance is downright incredible as I've shown in a number of benchmarks already and more follow-up tests are on the way.
| 2
| 1,760,718,853.23841
|
https://www.phoronix.com/news/AMD-EPYC-9755-Linux-6.11-6.12
|
AMD EPYC 9755 Performance On The Linux 6.11 & Linux 6.12 Kernels
|
Michael Larabel
|
For the recently launched AMD EPYC 9005 series "Turin" processors there is good support out-of-the-box running on the likes of Linux 6.8 as found with Ubuntu 24.04 LTS. The one exception is if wanting to engage CPU power monitoring you need a RAPL/PowerCap patch that was just upstreamed in v6.12. But what about using a newer kernel for greater performance in light of all the upstream optimizations to the kernel in general? Here are some Linux 6.8 vs. 6.11 vs. 6.12 kernel benchmarks on a dual AMD EPYC 9755 server.
Linux 6.8 as shipped by Ubuntu 24.04 LTS is in good shape for 5th Gen AMD EPYC, but of course, I'm always excited about what's coming down the pipe in future kernel versions... There's been many great changes upstreamed to the kernel since that point earlier in the year. Linux 6.11 is the latest stable kernel version right now and what's found in the (non-LTS) Ubuntu 24.10. Linux 6.11 has some great features while Linux 6.12 is in development for releasing in November. Linux 6.12 is expected to be this year's Long Term Support (LTS) kernel version and it's super heavy on new features from real-time "PREEMPT_RT" to sched_ext to new hardware additions and much more.
So for some quick benchmarks today, here are some numbers I recently carried out comparing Linux 6.8 (Ubuntu 24.04 stock kernel) to Linux 6.11 upstream stable and then the Linux 6.12 Git development state as of last week.
The same AMD EPYC 9755 2P server was used for all these kernel benchmarks without any modifications to the software/hardware besides swapping out the kernel version employed. The 6.11 and 6.12 Git kernel builds were following the same mainline PPA kernel configuration.
For most workloads there were no big changes in performance going from Linux 6.8 earlier this year to Linux 6.12 currently under development...
Many of the workloads were only subtly faster on Linux 6.11~6.12 than Linux 6.8.
But for some benchmarks particularly those that are very kernel focused, there were indeed gains to find when upgrading from Linux 6.8 to Linux 6.11/6.12.
In many of the larger, real-world workloads there were minimal to small changes while in more of the micro-benchmarks and other focused areas there were some nice gains observed with Linux 6.11/6.12. With Linux 6.12 expected to be this year's LTS kernel version, it will find use by hyperscalers and other large organizations that maintain their own distributions / customized software stacks and tend to jump between the LTS kernel versions. Linux 6.12 overall is looking quite nice for 5th Gen AMD EPYC.
| 1
| 1,760,718,853.58388
|
https://www.phoronix.com/news/AMD-P-State-EPYC-Linux-Patches
|
AMD Posts Linux Patches For EPYC To Further Enhance Performance-Per-Watt By Default
|
Michael Larabel
|
Making for an exciting Monday morning, AMD Linux engineers have kicked off the new week with a patch series introducing an exciting and long-awaited change: using the AMD P-State CPU frequency scaling driver by default for EPYC server platforms moving forward rather than the ACPI CPUFreq driver.
Since Zen 2 Ryzen and EPYC CPUs has been support for ACPI CPPC (Collaborative Processor Performance Control) for allowing greater control over managing the performance/power state of AMD CPU cores. But it wasn't until 2021 that the AMD P-State driver for Linux came together for making use of ACPI CPPC for greater CPU frequency controls / power management compared to generic ACPI CPUFreq Linux driver. With Linux 6.5 it became the default for modern Ryzen CPUs of using AMD P-State on supported systems but the AMD EPYC server processors have kept to using the ACPI CPUFreq driver by default... That is finally now changing. (Sans the exception of EPYC 4004 having been on AMD P-State already due to being derived from the Ryzen parts.)
On any recent kernel the AMD P-State driver has typically worked quite well on Zen 2 / 3 / 4 / 5 hardware. There's been some exceptions with quirky motherboards like some Threadripper Zen 2 motherboards needing workarounds and such, but especially for Zen 4 and now Zen 5 the AMD P-State Linux driver has been working out great with Ryzen as I've shown in many benchmarks for power and performance.
Hitting the Linux kernel mailing list this Monday morning are two patches for beginning to default to using AMD P-State for EPYC platforms. But for now at least this default usage is being limited to Family 1Ah (EPYC 9005 series) and future platforms. Earlier AMD EPYC servers are sticking to ACPI CPUFreq for now at least pending additional testing or AMD feeling comfortable to make the change without risking existing AMD server customers.
In addition to the change to make amd_pstate default to EPYC 9005 (Family 1Ah), the other patch is for preventing frequency throttling on power-limited systems with AMD P-State active mode while using the performance governor.
The patch making the default change to AMD P-State for EPYC notes:
"Currently the default cpufreq driver for all the AMD EPYC servers is acpi-cpufreq. Going forward, switch to amd-pstate as the default driver on the AMD EPYC server platforms with CPU family 0x1A or higher. The default mode will be active mode.
Testing shows that amd-pstate with active mode and performance governor provides comparable or better performance per-watt against acpi-cpufreq + performance governor.
Likewise, amd-pstate with active mode and powersave governor with the energy_performance_preference=power (EPP=255) provides comparable or better performance per-watt against acpi-cpufreq + schedutil governor for a wide range of workloads.
Users can still revert to using acpi-cpufreq driver on these platforms with the "amd_pstate=disable" kernel commandline parameter." See this patch series for the proposed changes. I'll be running some performance and perf-per-Watt benchmarks on my side for EPYC Turin (and likely EPYC Genoa / Bergamo for reference and curiosity) with ACPI CPUFreq vs. AMD P-State shortly. Very excited to see this change materialize for switching to AMD P-State by default for EPYC moving forward. Hopefully the review process will go smoothly and we could potentially see these patches land for the Linux v6.13 cycle.
| 3
| 1,760,718,854.62738
|
https://www.phoronix.com/news/Linux-AMD-Fixes-IBPB-Older-CPUs
|
Linux Fixes Indirect Branch Predictor Barrier "IBPB" Handling For Older AMD CPUs
|
Michael Larabel
|
Merged today to Linux 6.12 Git were bug fixes to AMD's Indirect Branch Predictor Barrier (IBPB) handling that can be optionally used as part of the Retbleed and Speculative Return Stack Overflow (SRSO) mitigations on older AMD processors.
Indirect Branch Predictor Barriers are not used by default so the impact of this fixing is limited to those that opted into using IBPB for Retbleed/SRSO as part of the various mitigation kernel parameters. The impact is also just for AMD Zen 3 CPUs and older.
AMD Linux engineer Borislav Petkov explained in today's x86 bugs merge:
"This fixes the IBPB implementation of older AMDs (< gen4) that do not flush the RSB (Return Address Stack) so you can still do some leaking when using a "=ibpb" mitigation for Retbleed or SRSO. Fix it by doing the flushing in software on those generations.
IBPB is not the default setting so this is not likely to affect anybody in practice." So for anyone running on an older AMD processor and opted into using IBPB for the Retbleed/SRSO mitigations, the fixed-up proper handling is now in Linux 6.12 Git and should be back-ported to the stable kernel versions over the coming days.
| 4
| 1,760,718,855.515946
|
https://www.phoronix.com/news/AMD-P-State-EPYC-Linux-6.13
|
Linux 6.13 To Default To AMD P-State Driver For EPYC 9005 CPUs
|
Michael Larabel
|
It was just earlier this week that AMD posted Linux patches to switch EPYC over to using the AMD P-State driver rather than the long-used generic ACPI CPUFreq driver. This should lead to better power efficiency out-of-the-box and is a change being made just for EPYC 9005 "Turin" CPUs and future server processors. Already it's looking like this change will be introduced for the upcoming Linux 6.13 merge window.
On Monday the patches were posted so that the AMD EPYC 9005 series processors join the AMD Ryzen (Zen 2 and newer) processors in defaulting to the amd_pstate CPU frequency scaling driver rather than ACPI CPUFreq. For new 5th Gen AMD EPYC processors this should mean even better out-of-the-box power efficiency compared to the ACPI CPUFreq default. Existing AMD EPYC server customers can already switch over to AMD P-State assuming they have ACPI CPPC platform support but only now is AMD comfortable enough making this default change for their very newest server CPUs.
On Tuesday a pull request was submitted with the latest AMD P-State content for queuing into the Linux power management system's "-next" branch ahead of Linux 6.13. AMD Linux engineer Mario Limonciello wrote on that pull request:
"Update the amd-pstate driver to set the initial scaling frequency policy lower bound to be lowest non-linear frequency. This will have a slight power consumption impact but should lead to increased efficiency.
Also amd-pstate is enabled by default on servers starting with newer AMD Epyc processors.
Add various code cleanups to rename functions and remove redundant calls." Great seeing no time wasted there in getting this EPYC support by default queued up for amd-pstate so that it will make it into Linux 6.13. The Linux 6.13 merge window will be opening up during the back half of November while the stable kernel won't be launched until February.
I'm still working on some 5th Gen AMD EPYC AMD P-State vs. ACPI CPUFreq benchmarks and should have the numbers published in the coming days for performance and power efficiency.
| 4
| 1,760,718,855.555068
|
https://www.phoronix.com/news/AMD-AOMP-20.0-0-Compiler
|
AMD Releases AOMP 20.0-0 For Radeon/Instinct Compiler Offloading
|
Michael Larabel
|
Following last week's release of the LLVM/Clang-downstream AOCC 5.0 for optimized compiler support extended to Zen 5 CPUs, the GPU side of the house at AMD this week released AOMP 20.0-0 as their LLVM/Clang downstream focused on GPU device offloading.
AOMP remains the AMD-maintained LLVM/Clang downstream compiler focused on OpenMP API device offloading to Radeon GPUs and Instinct accelerators. AOMP pulls in all of the latest AMDGPU compiler back-end bits and associated device offload patches for what isn't currently within the upstream LLVM repository. But unlike the AOCC compiler, AOMP is open-source. The AOMP developers also do a good job ensuring their patches do work their way upstream where relevant in a timely fashion.
AOMP continues to track LLVM Git and hence the version 20.0-0 to mark their first release since LLVM Git was bumped to version 20 development. AOMP 20.0-0 pulls in the latest ROCm 6.2.2 source code, AOMP now creates the relevant rocm/clang/clang++ configuration files, the gpurun utility now has multiple device support using the "-md" argument, updates to AOMP example code, and other updates.
AOMP 20.0-0 also adds in ROCm SMI and AMD SMI as AOMP components. Lastly the gfx90c, gfx1103, gfx1150, gfx1151, and gfx1152 AMD GPU targets are now enabled. GFX115* are for the RDNA 3.5 refresh parts and gfx1103 is for the Radeon 780M and gfx90c is for the AMD APUs with Vega graphics.
Downloads and more details on the AOMP 20.0-0 release via ROCm on GitHub.
| 2
| 1,760,718,856.448065
|
https://www.phoronix.com/news/AMD-XDNA-Linux-Driver-v4
|
AMD XDNA Linux Driver Updated As It Nears The Upstream Kernel
|
Michael Larabel
|
Back in January AMD published an open-source XDNA Linux kernel driver for supporting their Ryzen AI NPUs. But it wasn't until July that the formal review process for the AMD XDNA driver began as the necessary prerequisite for getting picked up into the mainline Linux kernel. On Friday the fourth iteration of those patches for review were published as it hopefully is closing in on landing within the mainline kernel.
With the AMD Ryzen 7040 series having launched in mid-2023, as we approach the end of 2024 it's unfortunate that this AMD XDNA driver hasn't yet entered the mainline kernel for supporting the Ryzen AI NPUs found in those mobile SoCs over the past year and a half or so. As it stands right now if the fourth round of review goes well, the soonest this driver will be merged is for the Linux v6.13 merge window that is happening in mid-to-late November. But the stable Linux v6.13 kernel won't be out until next February... So for those concerned with the out-of-the-box support on the likes of Ubuntu or similar, it's not until next spring with the likes of Ubuntu 25.04 and others where there might be out-of-the-box Ryzen AI support on Linux -- two years after the AMD NPU first began premiering within laptops.
In any event the v4 patches are now out for review. The updated patches remove earlier debug buffer object code plus have various other code changes as a result of earlier code review.
Those interested can find the new AMD XDNA Ryzen AI driver patches on the dri-devel list for review. Going along with the kernel driver is the XRT and AMD AIE IREE Plugin for the user-space stack. There's also necessary NPU firmware needed for rounding out the support.
| 11
| 1,760,718,857.068432
|
https://www.phoronix.com/news/AMD-GPU-AI-Stack-Job-Details
|
AMD Job Posting Confirms More Details Around Their AI GPU Compute Stack Plans
|
Michael Larabel
|
A Friday evening job posting has confirmed and reinforced details around their future AI GPU compute stack, presumably what's been referred to as the Unified AI Software Stack.
The Unified AI Software Stack is to support AMD's full range of hardware from CPUs to GPUs and most recently NPUs within Ryzen AI parts. The Unified AI Software Stack will help with offloading to the most appropriate device/accelerator and provide a more cohesive developer experience than what's currently provided by AMD software.
Posted to the LLVM Discourse was the job posting that AMD is recruiting for an AI GPU compiler engineer with an MLIR and LLVM focus. We've known MLIR -- LLVM's modern intermediate representation -- is to be the common IR of the Unified AI Software Stack. MLIR has also played a role with their Peano compiler for Ryzen NPUs and the like.
The job posting also notes that IREE is to play a central role in their future AI compute stack too. IREE is the Intermediate Representation Execution Environment built atop MLIR for lowering machine learning models into a unified IR. IREE supports already ONNX, PyTorch, TensorFlow, JAX, and more. IREE also has an AMD ROCm back-end already plus can also output to Vulkan as well as Apple Metal and NVIDIA CUDA.
Those unfamiliar with IREE can visit IREE.dev. I have covered IREE in the past such as for machine learning acceleration with Vulkan and has been mentioned in the context of AMD's AI software efforts. AMD's Nod.ai acquisition was to recruit engineering talent around not only MLIR but IREE too.
Anyhow, the job posting sums up the new AI GPU compiler development engineer position as:
"We are building IREE as an open-source compiler and runtime solution to productionize ML for a variety of use cases and hardware targets: https://iree.dev/. In particular, we aim to provide broad and performant GPU coverage, from datacenter to mobile, via a unified open-source software stack. Our team develops an end-to-end AI solution: from ML framework integration, down to generating efficient kernels."
Great seeing them reaffirm their interest from "datacenter to mobile" and thus this compiler/run-time software likely part of the Unified AI Software Stack effort. And, of course, that this in-development software stack will be open-source. It's going to be very interesting to see how well this future AMD AI software compute stack performs and exactly how well rounded the support is going to be across their different product lines.
| 11
| 1,760,718,857.469983
|
https://www.phoronix.com/news/AMD-AOCC-5.0-Compiler
|
AMD AOCC 5.0 Compiler Released With Zen 5 Support, New Optimizations
|
Michael Larabel
|
With 5th Gen AMD EPYC "Turin" processors now launched, AMD provided a same-day release of their updated AMD Optimizing C/C++ Compiler "AOCC". This is AMD's downstream version of LLVM/Clang/Flang where they provide optimized AMD processor support with code that hasn't yet worked its way up into LLVM proper.
With the AOCC 5.0 release they now have their initial Zen 5 "Znver5" compiler support in place with -march=znver5 for catering to the AMD EPYC 9005 series processors as well as the Ryzen 9000 desktop hardware and Ryzen AI 300 series laptops. Besides adding Znver5, they have re-based their AOCC code against the LLVM Clang 17 state. Other AOCC 5.0 changes include:
- Based on LLVM 17.0.6 release (llvm.org, Nov 2023)
- Optimized support for AMD “Zen5” architecture
- Improved SLP and loop vectorization
- Improved LICM and loop optimizations
- Enhanced control/data flow optimizations
- Zen5 tuned AOCL-LibM 5.0 (AMD Math Library)
LLVM 17 is a year old now with LLVM 19.1 having recently debuted. It's with LLVM 20 Git and then back-ported to LLVM 19 where initial Znver5 support was merged upstream but it doesn't yet have all the tuning / cost table adjustments that for now is just carrying it over from Znver4.
Given AOCC 5.0 mentioning vectorization improvements and other optimizations, I'll be running some AOCC 5.0 compiler comparison benchmarks in the coming days on Phoronix.
AOCC 5.0 is distributed as binaries for Red Hat Enterprise Linux, Ubuntu / Debian, and SUSE SLES systems. Sadly no public open-source code for this compiler downstream from AMD to analyze their changes. As well, we still wish they would more actively (and punctually) push to get their AOCC optimizations upstream in LLVM. For those not minding a binary-only, EULA-protected vendor compiler you can find the new AOCC 5.0 compiler release at AMD.com. Stay tuned for some AOCC 5.0 benchmarks up against GCC and LLVM/Clang upstream soon.
| 7
| 1,760,718,858.424583
|
https://www.phoronix.com/news/AMD-Project-Caliptra-2026
|
AMD To Integrate "Project Caliptra" Into Products Beginning In 2026
|
Michael Larabel
|
As another interesting AMD announcement this week following their Advancing AI event yesterday where they launched the EPYC 9005 series and other new hardware, they've continued with a few more soft announcements in the lead-up to the OCP Global Summit happening next week. The latest interesting tid-bit is their plans to incorporate Project Caliptra into their products beginning in 2026.
Caliptra is an open-source root of trust project backed by Google, Microsoft, NVIDIA, and others. Caliptra aims to be an open-source silicon Root of Trust (RoT) to provide for better security within edge and confidential computing environments. Caliptra is primarily aimed at data center hardware such as CPUs / GPUs / TPUs / DPUs and consist both of silicon-level functionality as well as firmware guarantees. Project Caliptra was born out of the Open Compute Project (OCP).
AMD announced on the community.amd.com blog that they will begin integrating Caliptra into products beginning in 2026. AMD's
Alex Tzonkov noted:
"AMD has strategic plans to integrate Project Caliptra into its 2026+ product lineup."
AMD believes making use of Caliptra will lead to better transparency and collaboration around open-source security, more consistency and reliability, and enhanced security.
This will presumably be at least within AMD EPYC data center products while we'll see if it ends up touching any consumer products and if it's also adopted by their data center GPUs/accelerators. With the 2026 timeframe it's potentially for premiering with EPYC Zen 6 processors in mind depending upon how the next-generation timing plays out. We'll learn more as those 2026+ AMD wares approach. Hopefully Caliptra proves much more useful than AMD's Pluton integration, which it should given the open-source and in part OCP focus.
| 7
| 1,760,718,859.133787
|
https://www.phoronix.com/news/AMD-HFI-Linux-Driver-v2
|
AMD Hardware Feedback Interface "HFI" Driver Updated For Heterogeneous CPUs
|
Michael Larabel
|
Back in August I wrote about AMD beginning work on a new Linux driver to help with heterogeneous core CPUs. On Thursday a second iteration of the AMD HFI Linux driver patches were posted with this driver continuing to work its way toward the mainline kernel.
The AMD Hardware Feedback Interface (HFI) driver is designed to help with their heterogeneous core processors that contain a mix of classic and dense "C" cores. This HFI driver may also be useful for their 3D V-Cache processors where only some cores/CCDs have access to the larger L3 cache -- though on the 3D V-Cache side, yesterday AMD Linux engineers also posted a 3D V-Cache Performance Optimizer driver.
Mario Limonciello who has taken over work on this AMD HFI Linux driver explains of its operation and intent:
"The AMD Heterogeneous core design and Hardware Feedback Interface (HFI) provide behavioral classification and a dynamically updated ranking table for the scheduler to use when choosing cores for tasks.
Threads are classified during runtime into enumerated classes. Currently, the driver supports 3 classes (0 through 2). These classes represent thread performance/power characteristics that may benefit from special scheduling behaviors. The real-time thread classification is consumed by the operating system and is used to inform the scheduler of where the thread should be placed for optimal performance or energy efficiency.
The thread classification helps to select CPU from a ranking table that describes an efficiency and performance ranking for each classification from two dimensions.
The ranking data provided by the ranking table are numbers ranging from 0 to 255, where a higher performance value indicates higher performance capability and a higher efficiency value indicates greater efficiency. All the CPU cores are ranked into different class IDs. Within each class ranking, the cores may have different ranking values. Therefore, picking from each classification ID will later allow the scheduler to select the best core while threads are classified into the specified workload class." As for the impact, enabling the AMD HFI driver on heterogeneous core CPUs should be good for a 2~5% performance improvement across different benchmarks. But there is the downside of higher latency on context switching:
"On applicable hardware this series has between a 2% and 5% improvement across various benchmarks.
There is however a cost associated with clearing history on the process context switch. On average it increases the delay by 119ns, and also has a wider range in delays (the standard deviation is 25% greater)." Those wanting to try out the AMD HFI driver can find it on the Linux power management list while it undergoes review and hopefully will be upstreamed in the near future.
| 1
| 1,760,718,859.403681
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https://www.phoronix.com/news/AMD-Salina-400-Pollara-400
|
AMD Announces Pensando Salina 400 DPU & Pollara 400 Ultra Ethernet NIC
|
Michael Larabel
|
In addition to announcing the EPYC 9005 "Turin" processors and the latest on the AMD Instinct front, Lisa Su at the AMD Advancing AI event in San Francisco also announced the AMD Pensando Salina 400 DPU and AMD Pensando Pollara 400 Ultra Ethernet AI NIC.
The AMD Pensando Salina 400 data processing unit (DPU) is designed for hyperscalers and offers 400G networking with dual 400GE PCIe Gen 5 connections, 232 P4 MPU engines, up to 128GB DDR5 memory, and 16 x Arm Neoverse-N1 CPU cores. The AMD Pensando Salina 400 DPU is designed to handle software defined networking, firewalls, encryption, load balancing, network address translation, and storage offloading.
Also on the networking side, the AMD Pensando Pollara 400 was announced as the first Ultra Ethernet Consortium (UEC) ready AI NIC. The AMD Pensando Pollara 400 offers a programmable hardware pipeline, 400 Gbps bandwidth, and open-source drivers. It was just last year that the Ultra Ethernet Consortium was started by the likes of AMD, Intel, the Linux Foundation, Meta, HPE, and other organizations.
That's the brief overview on the AMD Pensando Salina 400 and AMD Pensando Pollara 400 products with not receiving much information on them in advance and spending most of my time/focus on the new 5th Gen AMD EPYC processors, a.k.a. the AMD EPYC 9965 / 9755 / 9565F CPU benchmarks.
| 4
| 1,760,718,860.362963
|
https://www.phoronix.com/news/AMD-Commits-Open-Security
|
AMD Announces Commitment To "Open Security Technologies"
|
Michael Larabel
|
After the AMD Advancing AI Event yesterday where they launched AMD 5th Gen EPYC processors, Instinct product updates, and new high-end networking gear, they also put out a blog post to affirm their "commitment to open security technologies in the data center."
In the post yesterday (although it appears to have been back-ported to Monday or not otherwise appearing in their RSS feed until after yesterday's event), they were talking up their commitment to open security technologies. This is with the Open Compute Project's OCP Global Summit happening next week in San Jose, California.
Among their demonstrations for the OCP Global Summit to affirm their commitment are around AMD EPYC supply chain security, AMD Instinct platform security compliance, and more. With EPYC they'll be showing various security features in action, including integrity verification of the firmware components. Of course, that's one of the areas we love hearing about the most are vendors going more for open-source firmware components with the likes of OpenBMC, Coreboot, and some areas AMD has been actively working on such as with open-source SEV firmware and most exciting is their openSIL effort for eventually replacing AGESA. Last month was their latest update on AMD openSIL delivery for those that missed it but would be interesting to see if any other openSIL news comes out of the OCP Global Summit.
And while on the matter of open-source firmware, just as I didn't have the chance to mention it in yesterday's AMD EPYC Turin articles, their new "Volcano" reference server is once again shipping with OpenBMC. Though shouldn't really be surprising at this stage given their Genoa and Siena reference platforms were also running with OpenBMC rather than a proprietary BMC firmware stack.
AMD's post about committing to open security technologies can be found on the community.amd.com blog.
| 5
| 1,760,718,860.716578
|
https://www.phoronix.com/news/AMD-3DV-Cache-Optimizer-Linux
|
AMD 3D V-Cache Performance Optimizer Driver Posted For Linux
|
Michael Larabel
|
AMD today quietly posted a new open-source Linux kernel driver for review... the AMD 3D V-Cache Performance Optimizer Driver. This AMD 3D V-Cache Performance Optimizer Driver for Linux is intended to help optimize performance on systems sporting 3D V-Cache such as the AMD Ryzen "X3D" parts and the EPYC "X" processors.
The AMD 3D V-Cache Performance Optimizer Driver provides an interface for user-space to indicate whether their workloads are more cache sensitive or prefer higher frequency operation. This interface sets a bias to alter the CPU core reordering depending upon whether you are desiring higher frequences or larger L3 cache usage for your application(s).
With this core reordering by the AMD 3D V-Cache Optimizer, in frequency mode the cores within the faster CCD are prioritized before the slower CCD. Meanwhile in the "cache mode" of operation, the cores within the large L3 cache CCD are prioritized.
For those that were hoping all future AMD 3D V-Cache processors would boast CCDs with all the same large L3 caches, the work on this driver now seems to indicate that this won't necessarily be the case. Given today is the first time this Linux driver has been publicly posted, it would seem that at least some future AMD processor models will continue with only a subset of the CCDs having the big cache sizes.
This new driver is gated by the new "AMD_3D_VCACHE" Kconfig option and the driver named x3d_vcache. When enabled and running on a AMD 3D V-Cache processor, the /sys/bus/platform/drivers/amd_x3d_vcache/AMDI0101:00/amd_x3d_mode sysfs file is exposed where users can write "frequency" for setting the high frequency preference or "cache" for preferring cores from the larger L3 CCD as a priority.
This new AMD 3D V-Cache Performance Optimizer driver for Linux is now out for review on the platform-driver-x86 mailing list. Hopefully it can get reviewed and queued up in time for the upcoming Linux v6.13 cycle.
| 32
| 1,760,718,861.26614
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https://www.phoronix.com/news/AMD-EPYC-Embedded-8004
|
AMD Announces EPYC Embedded 8004 Series
|
Michael Larabel
|
Building off last year's release of the EPYC 8004 "Siena" processors featuring up to sixty-four Zen 4C cores, AMD today announced the EPYC Embedded 8004 series.
The AMD EPYC Embedded 8004 series is much like the EPYC 8004 series but designed for compute-intensive embedded systems. These Zen 4C embedded processors aim to deliver 30% better performance-per-Watt compared to prior generation embedded processors and boast a 20% smaller form factor than the EPYC Embedded 9004 series.
The EPYC Embedded 8004 processors are available in 12 to 64 core configurations. AMD is supporting Yocto Linux alongside other Linux distributions for EPYC Embedded 8004 products.
More details on the AMD EPYC Embedded 8004 series processors via AMD.com.
| 4
| 1,760,718,862.227378
|
https://www.phoronix.com/news/AMD-135M-SLM
|
AMD Releases AMD-135M: An Open-Source Small Language Model
|
Michael Larabel
|
AMD today announced "AMD-135M" as their first small language model they are publicly releasing. AMD-135M is open-source with the training code, dataset, and weights all being open-source to help in the development of other SLMs and LLMs.
AMD-135M features speculative decoding and was trained from scratch using AMD Instinct MI250 accelerators with 670 billion tokens. Training using four MI250 nodes took six days. There is also an AMD-Llama-135M-code variant that has an additional 20 billion tokens of code data. AMD-135M is based on the LLaMA2 model architecture.
AMD is making all of the AMD-135M model assets open-source in hopes of helping other AI development -- and for AMD's part, hoping that the training and inferencing is happening from AMD hardware.
More details on the AMD-135M SLM via the AMD blog. AMD-135M is available via HuggingFace and GitHub.
| 9
| 1,760,718,863.126123
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https://www.phoronix.com/news/AMD-Linux-Hetero-Max-Detect
|
New AMD Linux Patches Aim To Further Boost Performance For Heterogeneous CPU Designs
|
Michael Larabel
|
A new set of patches from AMD Linux engineers today aim to boost the performance for heterogeneous CPU designs such as the recent Ryzen AI 300 "Strix Point" SoCs that have multiple core types.
Hitting the Linux kernel mailing list today is a new set of patches for properly detecting maximum performance values of heterogeneous AMD CPU designs. AMD Linux engineer Mario Limonciello explained in the patch series:
"AMD heterogeneous designs such as the Ryzen AI 300 series processors have multiple core types that can reach different maximum clock values.
This series uses the CPUID Fn_0x80000026 to detect such designs and to correct configure the boost numerator that is used to calculate maximum frequency.
...
AMD heterogeneous designs include two types of cores:
* Performance
* Efficiency
Each core type has different highest performance values configured by the platform. Drivers such as `amd_pstate` need to identify the type of core to correctly set an appropriate boost numerator to calculate the maximum frequency.
X86_FEATURE_HETERO_CORE_TOPOLOGY is used to identify whether the SoC supports heterogeneous core type by reading CPUID leaf Fn_0x80000026.
On performance cores the scaling factor of 196 is used. On efficiency cores the scaling factor is the value reported as the highest perf. Efficiency cores have the same preferred core rankings." See this patch series for those interested in this latest AMD Ryzen Linux performance work. It should help at least Ryzen AI 300 laptops and future heterogeneous designs.
I will be running some benchmarks in the coming days of these patches on the Ryzen AI 9 365 and Ryzen AI 9 HX 370 laptops that I have around.
| 3
| 1,760,718,863.884862
|
https://www.phoronix.com/news/Linux-6.12-Early-AMD-Zen-5
|
Early Linux 6.12 Kernel Benchmarks Showing Some Nice Gains On AMD Zen 5
|
Michael Larabel
|
With the Linux 6.12 merge window wrapping up this weekend and the bulk of the new feature merges now in the tree, I've begun running some Linux 6.12 benchmarks. Here is an initial look at Linux 6.10 vs. 6.11 vs. 6.12 Git on an AMD Ryzen 9 9950X desktop.
Many more benchmarks of Linux 6.12 will come after the merge window and on more diverse hardware platforms from desktop and mobile to servers, but for now here was an initial quick test run from this week in the pre-6.12-rc1 state.
The same kernel configuration used. Linux 6.12 Git was built from source since the Ubuntu Mainline Kernel PPA was broken as of testing. No other changes to this Ryzen 9 9950X system during tests besides swapping the kernel builds.
Many workloads were flat across the tested kernels on this AMD Zen 5 desktop.
Scheduler benchmarks were showing some nice gains thanks to scheduler work merged during the Linux 6.12 merge window these past two weeks.
RabbitMQ message passing was showing better performance too on Linux 6.12.
Memcached also showing nice improvements with Linux 6.12. It will be nice if these gains are carried over on the server hardware too with future Linux 6.12 testing.
Nginx was another server workload with slight improvements on Linux 6.12 for this AMD Zen 5 system.
Stay tuned for more Linux 6.12 benchmarks on different Intel and AMD systems following the Linux 6.12-rc1 kernel release expected on Sunday.
| 13
| 1,760,718,863.912533
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https://www.phoronix.com/news/LLVM-Clang-Znver5-Merged
|
Initial AMD Zen 5 "Znver5" Support Merged For LLVM/Clang
|
Michael Larabel
|
Last week the initial AMD Zen 5 "znver5" enablement for LLVM/Clang was posted by an AMD compiler engineer. That code has since undergone review and merged for LLVM 20 Git and yesterday then back-ported for LLVM 19.
This initial AMD Zen 5 enablement for LLVM/Clang adds the "-march=znver5" support and exposes the new ISA capabilities of AMD Zen 5 processors. However, the tuning itself is still catering to the existing Zen 4 processors. Future AMD patches will work on properly tuning the Znver5 target for Zen 5 processors.
During the LLVM code review the question of AMD taking so long to submit this LLVM support was questioned, especially with the GCC support for Znver5 coming early in 2024. The response to the tardy AMD Zen 5 support in LLVM was described as:
"We have a dependency in libpfm for llvm which requires legal clearances. In future, we will make sure this gets addressed in advance and will try to upload our patches in sync with GCC patches. Apologies for the inconvenience."
AMD will be working on the tuned support for Zen 5 processors but it may still "take some time" as noted in another code review comment:
"I will upload the rebased code addressing the format errors shortly. Yes PRs will work for tuning changes. I think it will take some time."
The initial AMD Zen 5 support was merged prior to the weekend and now in LLVM 20 Git. This was then back-ported for LLVM 19 via a separate pull to avoid causing an ABI break in LLVM 19.
Hopefully it won't take too much longer before the Znver5 tuning for LLVM/Clang and GCC compilers are complete.
| 3
| 1,760,718,864.849087
|
https://www.phoronix.com/news/Cloudflare-Goes-Genoa-X
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Cloudflare Goes With AMD EPYC Genoa-X For Their Next-Gen Servers
|
Michael Larabel
|
Cloudflare's always-interesting technical blog laid out their details today concerning their next-gen "12th Generation" in-house servers that will be powering their vast web infrastructure. With these next-gen Cloudflare servers they are going with AMD EPYC 9684X Genoa-X processors.
Cloudflare's current-gen servers are 1U designs powered by AMD EPYC 7713 "Milan" processors while their Gen 12 server has upgraded to the AMD EPYC 9684X Genoa-X processors. It's a great upgrade with now having 3D V-Cache, native AVX-512 support will help their AI/ML workloads and more, great PCI Express connectivity, etc. The AMD EPYC 9684X performance remains very strong with competitive power efficiency even more than one year after launch.
The Cloudflare Gen 12 Compute platform is using 384GB of DDR5-4800 memory across 12 memory channels, Samsung NVMe SSD storage, dual 25 Gbe Ethernet, and an 800 Watt power supply. With this generation they've also switched the server design from 1U to 2U for helping with cooling and other factors.
Cloudflare was deciding between the EPYC 9654, EPYC 9754, and EPYC 9684X processors for their next-gen server and ultimately went for the 3D V-Cache Genoa variant for the best performance.
Cloudflare noted in today's blog post they are already testing 5th Gen EPYC "Turin" servers as part of their planning and design discussion for their next-generation (Gen 13) server platform.
Those curious about Cloudflare's Genoa-X server design choices for powering their compute infrastructure can learn all the interesting technical details over on the Cloudflare blog.
| 2
| 1,760,718,865.387753
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https://www.phoronix.com/news/Linux-6.12-EDAC-RAS-AMD-PRM
|
Linux 6.12 EDAC Prepares For Address Translation On Future AMD Platforms
|
Michael Larabel
|
The Error Detection And Correction (EDAC) driver updates were among the early pull requests submitted for the Linux 6.12 kernel cycle in advance of this week's Linux Kernel Maintainer Summit in Austria. Among the EDAC work this cycle is preparing memory address translation support for future AMD platforms.
With these code updates for Linux 6.12 is the ability on future AMD platforms for translating normalized error addresses into system physical addresses using UEFI Platform Runtime Mechanism (PRM) support. The prior patches for this AMD PRM handling for EDAC explains:
"Platform Runtime Mechanism (PRM) introduces a means for the AML interpreter and OS drivers to invoke runtime handlers from platform firmware in order to remove the need for certain classes of SMIs.
...
Future AMD platforms will implement a PRM module in firmware that will include handlers for performing various types of address translation. The address translation PRM module is documented in chapter 22 of the publicly available "AMD Family 1Ah Models 00h–0Fh and Models 10h–1Fh ACPI v6.5 Porting Guide".
While the kernel currently has support for calling PRM handlers from the AML interpreter, it does not support calling PRM handlers directly from OS drivers. This series implements the direct call interface and uses it for translating normalized addresses to system physical addresses." With the Family 1Ah documentation being mentioned, this PRM support for error addresses to system physical addresses is likely for use with upcoming AMD EPYC "Turin" Zen 5 servers.
The EDAC updates for Linux 6.12 also fix an issue on the Intel side for older Elkhart Lake nad Ice Lake platforms where the system address is above the top-of-memory address. The old PPC4xx_EDAC driver is also removed since that older PowerPC platform support was previously removed from the mainline Linux kernel. Error injection for Zynq UltraScale+ platforms have also been fixed.
More details for those interested via this pull.
| 0
| 1,760,718,865.782831
|
https://www.phoronix.com/news/AMD-XDNA-Linux-Driver-v3
|
AMD XDNA Linux Driver v3 Published For Ryzen AI Upstreaming
|
Michael Larabel
|
AMD engineers continue work toward upstreaming their XDNA kernel driver for Linux in enabling the Ryzen AI NPU on open-source. The "v3" patches were posted on Wednesday but given the timing it looks like it will be missing out still on merging for the upcoming Linux 6.12 LTS cycle.
Back in July AMD finally posted the XDNA Linux driver patches for review in getting the kernel code evaluated for upstreaming into the mainline Linux kernel. That came after AMD posted the initial XDNA Linux code in January, a year after AMD APUs began appearing with the Ryzen AI NPU for helping with AI workloads.
In August the v2 XDNA driver patches were posted in addressing early code review comments from kernel developers.
The v3 patches posted yesterday update the AMD NPU driver documentation, change the AIE2_DEVM_SIZE size to 64M for accommodating firmware changes, and other code changes from prior code review comments. This "AMDXDNA" kernel driver continues being fitted to the kernel's "accel" accelerator subsystem that lives under the Direct Rendering Manager (DRM) driver umbrella.
Those interested can see the AMDXDNA v3 driver patches if spinning your own kernel build. Given the Linux 6.12 merge window is kicking off next week already, unless this is attempted as a late merge given it's for new hardware without risking existing hardware support, more than likely it's not going to land until at least Linux v6.13 in the new year.
| 4
| 1,760,718,866.594233
|
https://www.phoronix.com/news/AMD-Zen-5-LLVM-Enablement
|
AMD Submits Initial Zen 5 Enablement For LLVM/Clang Compiler
|
Michael Larabel
|
Early in the year we enjoyed seeing AMD Zen 5 "znver5" support upstreamed for the GCC 14 compiler in making it into that annual GNU Compiler Collection feature release. It was great seeing AMD Zen 5 support make it into this open-source compiler well ahead of any Zen 5 products being announced. Since then the GCC support for the new Znver5 target has continued to be improve upon meanwhile we've been waiting to see similar treatment for the LLVM/Clang compiler stack. Finally this week that AMD Zen 5 (znver5) support has been submitted for review in upstreaming it for LLVM.
I was delighted to check this morning and see there's finally a pull request pending for adding Znver5 to upstream LLVM. Yesterday this pull request was opened by an AMD compiler engineer for adding the Zen 5 support to upstream open-source LLVM.
This adds the "-march=znver5" support for Clang, the Family 1Ah detection, and enabling the new instructions added into Zen 5 over Zen 4. This LLVM patch is still making use of the AMD Zen 4 tuning data without any new tuning metrics submitted by AMD. In time they'll hopefully have the tuned support for Zen 5 CPUs ready for upstreaming.
One bit I did enjoy in going through this compiler patch is that as a code comment they've added a bit of a decoder for the AMD Zen 5 model IDs... So far the GCC and Linux kernel patches and other Family 1Ah patches have just treated the models as all Zen 5 as model IDs 128 or less. This code comment for the LLVM Znver5 patch actually lays out what models belong to what codenames. Codenames covered include Breithorn, Breithorn-Dense, Strix 1, Strix 2, Strix 3, Granite Ridge, Weisshorn, Krackan1, and Sarlak. Those codenames really shouldn't come as a surprise but I don't believe "Strix 3" has been brought up in rumors yet. AMD "Weisshorn" was previously reported elsewhere as rumored to be a Zen 6 codename but given that it's showing up as part of this Zen 5 listing leads to that potentially being an inaccurate description.
In any case this Znver5 patch for LLVM is now undergoing review for hopefully merging soon to LLVM Git. The timing is a bit unfortunate though. Besides coming more than six months after the initial GCC Znver5 patch, this pull request is coming just days before the LLVM 19 compiler is being released as stable -- and that code being branched back in August. LLVM 19 stable will be out this week or next and it's too bad this Znver5 support didn't make it into that six-month compiler release but hopefully it will be back-ported to one of the LLVM 19.1 point releases otherwise users will need to wait until LLVM 20 around March of next year.In any case this remains one of the areas I wish AMD would improve upon in providing compiler support sooner ahead of CPU launches given the long lead times between compiler releases and even longer until they are picked up by prominent Linux distributions. Intel does a good job here with often getting new core support 1~2 years ahead of time into GCC and Clang. LLVM 18 added Clearwater Forest and Panther Lake targets ahead of planned 2025 debut while only LLVM 20 or a LLVM 19 point release will be adding Zen 5 with the Ryzen AI 300 series and Ryzen 9000 series products already shipping.For those not wanting to wait on a supported compiler release or looking for something to run on your aging enterprise Linux distribution, AMD will presumably release soon an updated version of its LLVM-based AOCC compiler with Zen 5 support.
| 1
| 1,760,718,867.553167
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https://www.phoronix.com/news/AMD-Secure-AVIC-Guest-Support
|
AMD Posts Linux Patches For New Secure AVIC Guest Feature
|
Michael Larabel
|
AMD engineers today posted the first "request for comments" patches in enabling support for Secure AVIC guest handling as a new hardware feature with upcoming processors.
Secure AVIC guest support is a new capability for virtual machines (VMs) making use of Secure Encrypted Virtualization (SEV-SNP) with upcoming processors. Given the SEV-SNP mention, it's for EPYC class server processors. Today's patches do not indicate what generation of AMD processors will initially boast this capability.
The RFC Linux kernel patches explain this Secure AVIC guest support as:
"Secure AVIC is a new hardware feature in the AMD64 architecture to allow SEV-SNP guests to prevent hypervisor from generating unexpected interrupts to a vCPU or otherwise violate architectural assumptions around APIC behavior.
One of the significant differences from AVIC or emulated x2APIC is that Secure AVIC uses a guest-owned and managed APIC backing page. It also introduces additional fields in both the VMCB and the Secure AVIC backing page to aid the guest in limiting which interrupt vectors can be injected into the guest.
...
The Secure AVIC feature provides SEV-SNP guests hardware acceleration for performance sensitive APIC accesses while securely managing the guest-owned APIC state through the use of a private APIC backing page. This helps prevent malicious hypervisor from generating unexpected interrupts for a vCPU or otherwise violate architectural assumptions around APIC behavior.
Add a new x2APIC driver that will serve as the base of the Secure AVIC support." This Secure AVIC guest support depends upon Secure AVIC host support, with those kernel patches currently available via this AMD GitHub tree.
Those interested can now find this AMD Secure AVIC guest support under review on the Linux kernel mailing list. As it's just being posted today and under an RFC flag, it's far too late for appearing in the upcoming Linux v6.12 kernel and thus will appear in a kernel release likely at some point in 2025 depending upon how long the review/revision process takes. For some of these core features around VMs/security it has taken quite a bit of time to bake such as SEV-SNP in good shape on the mainline kernel finally with Linux 6.11.
| 1
| 1,760,718,867.601363
|
https://www.phoronix.com/news/AMD-openSIL-September-2024
|
AMD Reveals Latest Plans For Open-Source openSIL With Replacing AGESA, Zen 6 Milestone
|
Michael Larabel
|
Last year to much excitement in our community was the new AMD project announcement of openSIL as an open-source CPU silicon initialization project that is an advancement for open-source firmware and to eventually replace AMD's AGESA across both client and server processors. This week an exciting new update on AMD OpenSIL was shared and that they are still on-track for having it production-ready next year.
AMD openSIL was open-sourced last June and so far has been ported to select AMD reference boards along with an experimental port by Supermicro to one of their motherboards. It's been progressing steady and yesterday at the Open-Source Firmware Conference in Germany was a much anticipated status update on the openSIL project.
AMD firmware engineer Paul Grimes presented on the openSIL project at the OSFC conference on Wednesday in Germany. Here are some of the highlights from yesterday's OSFC 2024 presentation.
Last year their intentions were indicated that AMD expected to have openSIL production ready in the 2025~2026 timeframe. They're still on track. In fact, now they specifically name 6th Gen AMD EPYC "Zen 6" processors as having production-level feature, validation, and QA for openSIL.
Interestingly they also now outline that they will be publishing their AMD openSIL code for new platforms one quarter after the hardware launch. Not quite as ideal as developing completely in the open but understandably new hardware development is done in private especially as it pertains to sensitive areas around new/unannounced features, etc. The one quarter after drop is likely for going through legal review and any other internal processes.
Venice as a reminder is the codename for AMD EPYC Zen 6 processors.
AMD has been working on 5th Gen EPYC "Turin" support already and anticipate releasing its MIT open-source code before the end of the calendar year. Phoenix SoCs have also been seeing openSIL enablement ongoing.
AMD is also working to ramp up its open-source contributions to TianoCore albeit a slow process.
AMD is planning to upstream their EDKII-Turin platform code to TianoCore in the fourth quarter.
With Zen 6 processors is where the AMD openSIL support will be production-ready and become rather exciting... For AMD 6th Gen EPYC "Venice" the openSIL code will still be paired with Agesa-v10 as it's being phased out. This generation at least will still rely on pre-x86 PSP binaries.
Exciting with the note "bootable open source solution committed" for the Zen 6 era hardware.
And then for what sounds like could be Zen 7 is when more of the AGESA code will be phased out and openSIL incorporating more responsibilities. AMD will also be "strengthening" their Coreboot support as well as Tianocore contributions.
AMD is also working to establish a community-based governance model for the open-source openSIL project.
Also very notable with this slide is the continued confirmation of "active development [of Coreboot] in AMD CLient and Embedded space" and that the server product roadmap for using Coreboot is "trending post Venice", so again potentially for Zen 7.
As we move closer to AMD EPYC Venice timeline -- and new EPYC Turin server platforms ahead -- hopefully we'll be hearing more from other OEMs and ODMs about their work around AMD openSIL and Coreboot. For now MiTAC (Tyan) and Supermicro are among the early AMD partners already engaging with openSIL in proof-of-concept/experimental form.
AMD openSIL remains a very exciting AMD open-source project to watch over the coming months and years. I am super excited and have longed to see AMD embrace more open-source firmware like they used to do many years ago with open-source AGESA / Coreboot contributions and the like. It's also been very refreshing with newer AMD reference boards and even some partner servers running OpenBMC for their BMC software stack. AMD has also been doing more around Sound Open Firmware and other open-source firmware efforts like publishing SEV firmware as open-source. Exciting times ahead.
| 29
| 1,760,718,868.397632
|
https://www.phoronix.com/news/GCC-15-Lands-More-Zen-5-Tuning
|
More AMD Zen 5 Tuning/Optimizations Merged For The GCC 15 Compiler
|
Michael Larabel
|
Following yesterday's initial tuning of the "znver5" target for the AMD Zen 5 CPUs with the GCC 15 compiler, several more rounds of compiler tuning/optimizations were merged for benefiting the Ryzen AI 300 series, Ryzen 9000 series desktops, and upcoming EPYC Turin processors.
After yesterday's coverage of the first two Zen 5 tuning patches being merged to GCC Git by SUSE compiler engineer Jan Hubicka, he continued with several more patches for further enhancing the Znver5 compiler optimizations.
Part 3 landed and provided scheduler tweaks for the AMD Zen 5 target. Hubicka explained there:
"This patch adds support for new [fusion] in znver5 documented in the optimization manual:
The Zen5 microarchitecture adds support to fuse reg-reg MOV Instructions with certain ALU instructions. The following conditions need to be met for fusion to happen:
- The MOV should be reg-reg mov with Opcode 0x89 or 0x8B
- The MOV is followed by an ALU instruction where the MOV and ALU destination register match.
- The ALU instruction may source only registers or immediate data. There cannot be any memory source.
- The ALU instruction sources either the source or dest of MOV instruction.
- If ALU instruction has 2 reg sources, they should be different.
- The following ALU instructions can fuse with an older qualified MOV instruction: ADD ADC AND XOR OP SUB SBB INC DEC NOT SAL / SHL SHR SAR (I assume OP is OR)
I also increased issue rate from 4 to 6. Theoretically znver5 can do more, but with our model we can't realy use it. Increasing issue rate to 8 leads to infinite loop in scheduler.
Finally, I also enabled fuse_alu_and_branch since it is supported by znver5 (I think by earlier zens too)." That was followed by updating the re-association width:
"Zen5 has 6 instead of 4 ALUs and the integer multiplication can now execute in 3 of them. FP units can do 2 additions and 2 multiplications with latency 2 and 3. This patch updates reassociation width accordingly. This has potential of increasing register pressure but unlike while benchmarking znver1 tuning I did not noticed this actually causing problem on spec, so this patch bumps up reassociation width to 6 for everything except for integer vectors, where there are 4 units with typical latency of 1." And then as of writing now the fifth and last portion so far of the Zen 5 tuning for the GCC compiler is updating the instruction latencies for Zen 5 processors:
"There is nothing exciting in this patch. I measured latencies and also compared them with newly released optimization guide. There are no dramatic changes compared to zen4. One interesting new bit is that addss is faster and can be 2 cycles when fed by another addss.
I also increased the large insn bound since decoders seems no longer require instructions to be 8 bytes or less." That's it so far for this round of AMD Zen 5 tuning for the GNU Compiler Collection thanks to SUSE engineering.
These patches are all in GCC Git for the GCC 15.1 compiler to be released in March~April 2025. These patches might also be picked up for the next GCC 14 point release in the coming months for reaching a stable compiler version soon. In an ideal world this tuning would have happened all pre-launch given the annual-focused GCC compiler release cycles and the time it typically takes Linux distributions to adopt new GCC releases.
Once the Znver5 optimizations settle down I'll be through a fresh round of GCC compiler benchmarking the performance impact with current Ryzen 9000 series desktop processors.
| 4
| 1,760,718,869.246314
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https://www.phoronix.com/news/AMD-Zen-5-Tuning-Part-2-GCC
|
AMD Zen 5 Tuning "Part Two" Merged For GCC Compiler
|
Michael Larabel
|
Merged today for the GCC 15 compiler in development and potentially for back-porting to the next GCC 14 point release is a second round of AMD Zen 5 "znver5" tuning.
GNU Compiler Collection (GCC) expert Jan Hubicka of SUSE's compiler team worked out this latest round of compiler tuning for benefiting the Ryzen AI 300 series, Ryzen 9000 series desktops, and upcoming EPYC Turin processors. As with past generations of Zen processors, AMD has largely relied on SUSE's compiler talent for working out much of the compiler enablement and tuning for this leading open-source compiler.
With this "round 2" tuning of AMD Znver5 compiler support, it's focused on disabling gather and scatter support by default. Similar to past AMD Zen tuning for GCC, disabling gather and scatter instructions by default is done in the name of overall performance.
Jan Hubicka explained with today's patch to the GCC compiler:
"We disable gathers for zen4. It seems that gather has improved a bit compared to zen4 and Zen5 optimization manual suggests "Avoid GATHER instructions when the indices are known ahead of time. Vector loads followed by shuffles result in a higher load bandwidth." however the situation seems to be more complicated.
gather is 5-10% loss on parest benchmark as well as 30% loss on sparse dot products in TSVC. Curiously enough breaking these out into microbenchmark reversed the situation and it turns out that the performance depends on how indices are distributed. gather is loss if indices are sequential, neutral if they are random and win for some strides (4, 8).
This seems to be similar to earlier zens, so I think (especially for backporting znver5 support) that it makes sense to be conistent and disable gather unless we work out a good heuristics on when to use it. Since we typically do not know the indices in advance, I don't see how that can be done."
This GCC bug report was opened today for tracking the gather instructions performance on Zen CPUs. In response to a question from another developer when the gather instructions are a win: "it is mysterious.."
Part 1 of the optimizations to Znver5 were to avoid FMA chains since they don't work well on Zen 5 processors compared to Znver4.
Hopefully we'll see more AMD Zen 5 compiler tuning soon for GCC. We are also still waiting on Znver5 enablement to come for the LLVM/Clang compiler. As of writing the Znver5 support hasn't landed in LLVM Git nor are there any open pull requests from AMD or their partners in providing that support. That's particularly unfortunate with AMD Ryzen AI 300 and Ryzen 9000 series processors already shipping and LLVM 19 being released in the coming days.
| 3
| 1,760,718,869.307397
|
https://www.phoronix.com/news/AMD-PMC-Linux-6.11-More-Zen-5
|
AMD PMC Driver Patches Submitted To Linux 6.11 Prepare For More Upcoming Zen 5 SoCs
|
Michael Larabel
|
The AMD PMC driver used for the SoC power management controller already supports the initial AMD Zen 5 SoCs but new patches coming in as "fixes" for the Linux 6.11 kernel extend the coverage for some upcoming AMD platforms.
Today's batch of platform-drivers-x86 fixes for the Linux 6.11 kernel "Extend support for PMC features on new AMD platform" and "Fix SMU command submission path on new AMD platform."
This "new" AMD platform support is for covering AMD Family 1Ah Model 60h series processors. The 60h series doesn't belong to the recently launched Strix Point (Ryzen AI 3000 series) and Granite Ridge (Ryzen 9000 series desktop CPUs) but is a newer model range that's been appearing in Linux source code in recent months. Whether these model 60h series parts is for Strix Halo, Kraken Point, some custom parts, or some other refresh parts is yet to be figured out.
The AMD PMC driver earlier in the Linux 6.11 cycle began adding the new models while today's pull request gets that new support sorted out.
Whatever these new Family 1Ah Model 60h parts ends up being, it's good as usual seeing AMD getting the Linux support squared away ahead of time. These latest AMD PMC driver patches can be found via this morning's platform-drivers-x86 pull request. That code will likely be merged within the next day or so and be part of the Linux 6.11-rc6 kernel on Sunday.
| 3
| 1,760,718,870.279905
|
https://www.phoronix.com/news/AMD-Heterogeneous-Core-Driver
|
AMD Developing New Heterogeneous CPU Core Driver For Linux Systems
|
Michael Larabel
|
AMD for months has already been working on heterogeneous core topology optimizations for Linux within the AMD P-State CPUFreq driver and other heterogeneous CPU topology improvements for dealing with Ryzen systems sporting a mix of "classic" (full) cores with the denser "C" cores. Today though they've announced a brand new "Heterogeneous Core Driver" for further enhancing Linux support for AMD platforms sporting a combination of core types.
The AMD Heterogeneous Core Driver makes use of the Hardware Feedback Interface to provide for more detailed knowledge to the kernel about the core performance/power capabilities to help better with deciding where a thread (task) should be placed. Intel similarly makes use of the Hardware Feedback Interface (HFI) as part of their P vs. E core handling on Linux.
With today's first patch series presenting this open-source AMD Heterogeneous Core Driver for Linux, the patch cover letter explains:
"The AMD Heterogeneous core design and Hardware Feedback Interface (HFI) provide behavioral classification and a dynamically updated ranking table for the scheduler to use when choosing cores for tasks.
Threads are classified during runtime into enumerated classes. Currently, the driver supports 3 classes (0 through 2). These classes represent thread performance/power characteristics that may benefit from special scheduling behaviors. The real-time thread classification is consumed by the operating system and is used to inform the scheduler of where the thread should be placed for optimal performance or energy efficiency.
The thread classification helps to select CPU from a ranking table that describes an efficiency and performance ranking for each classification from two dimensions.
The ranking data provided by the ranking table are numbers ranging from 0 to 255, where a higher performance value indicates higher performance capability and a higher efficiency value indicates greater efficiency. All the CPU cores are ranked into different class IDs. Within each class ranking, the cores may have different ranking values. Therefore, picking from each classification ID allows the scheduler to select the best core while threads are classified into the specified workload class. The cores ranking table is provided with PCCT subspace type 4 shared memory, which includes the memory base address and length."
This patch series has the initial ~860 lines of code making up this AMD HFI driver. A healthy chunk of that is the new documentation that explains the classic and dense cores, the amd_hfi driver handling, and how the thread classification and ranking is carried out.
As part of this driver is adding a new X86_FEATURE_WORKLOAD_CLASS "workload classification" feature bit. This is used for indicating workload-based heuristic feedback to the operating system for scheduling decisions.
This new "AMD_HFI" driver is now undergoing code review. Given the Linux v6.12 merge window is opening up in just a few weeks, it's unlikely the driver will be deemed reviewed, tested, and ready for merging by then. Thus at the earliest we're likely looking at the driver potentially being ready for Linux v6.13 that in turn will reach a stable release in early 2025. I'll be running some benchmarks on my side with these new AMD heterogeneous core driver patches to see if they help further enhance the likes of Strix Point on Linux.Separately, a different patch series was posted on Monday for tuning the AMD Preferred Core detection in the AMD P-State driver. The initial AMD Preferred Core support for Linux systems was merged back in Linux 6.9 and now being further refined so that it's more reliable and robust.
| 4
| 1,760,718,871.31306
|
https://www.phoronix.com/news/AMD-PM-Linux-6.11-rc6
|
AMD Preferred Core Fix Lands Ahead Of Linux 6.11-rc6
|
Michael Larabel
|
This week's batch of power management fixes for the Linux 6.11 kernel are just a set of three patches for AMD processors.
Of the AMD power management fixes for Linux 6.11-rc6, one is worth pointing out and it's a fix for the AMD Preferred Core handling. AMD Preferred Core was introduced in Linux 6.9 as a feature that's been around since Zen 2 processors for being able to indicate via ACPI CPPC the CPU cores that are preferred -- capable of reaching a higher maximum frequency or otherwise capable of performing better than the other cores.
With Linux 6.11-rc6 is a fix to remove checks for the highest performance match on AMD Preferred Cores when updating the preferred core ranking within the AMD P-State driver.
The AMD power management fixes have been merged via this pull request ahead of the Linux 6.11-rc6 kernel test release debuting tomorrow. The stable Linux 6.11 kernel should be out around mid-September.
Frustratingly, this one line patch that is a straight forward addition to "fix" the missing CPU power reporting for AMD Zen 5 processors has yet to be picked up by the mainline kernel... Thus looking like it will wait until the Linux 6.12 merge window.
| 7
| 1,760,718,871.456495
|
https://www.phoronix.com/news/AMD-ACP-7.0-SOF-Driver
|
AMD Prepares Sound Open Firmware Driver For ACP7.0 Hardware
|
Michael Larabel
|
As part of catering to Google requirements around Google Chromebooks, AMD has been supporting Sound Open Firmware as the Intel-initiated open-source project across their APUs/SoCs. Sent out today was the patch for enabling ACP 7.0 SOF support for their newest SoCs like Strix Point to have Sound Open Firmware support.
The Linux kernel already has sound support on ACP 7.0 while the SOF support has only been up to the ACP 6.3 IP. Now in patch form on the mailing list is an ACP 7.0 SOF sound driver.
This patch series introduces the pci-acp70 driver for supporting Sound Open Firmware on the AMD Audio Co-Processor 7.0 IP. There is also this SOF project pull request as part of bringing up the AMD ACP 7.0 support. That code was merged to the SOF codebase this week ahead of the project's next release.
The initial user of AMD Audio Co-Processor 7.0 IP appears to be the RDNA3.5 graphics with Strix Point / Ryzen AI 300 series. With time more AMD ACP 7.x hardware will come.
| 4
| 1,760,718,872.67938
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https://www.phoronix.com/news/Linux-6.11-AMD-Ryzen-9-9950X
|
Linux 6.11 Kernel Performance On The AMD Ryzen 9 9000 Series
|
Michael Larabel
|
If you are picking up one of the new AMD Ryzen 9000 series desktop processors soon for Linux use, you may be wondering whether it's worthwhile or even necessary moving to the latest Linux kernel code compared to the likes of Ubuntu 24.04 LTS that are shipping a Linux 6.8 derived kernel. Here are some quick benchmarks in looking at that question.
The AMD Ryzen 9600X / 9700X / 9900X / 9950X can work out fine using the stock Linux 6.8 based kernel on Ubuntu 24.04 LTS. As mentioned in my earlier Linux reviews of these new AMD "Granite Ridge" CPUs, the main caveats are around the CPU power consumption monitoring (RAPL / PowerCap) with a one-liner still missing for supporting the Family 1Ah processors. There have been some other AMD Family 1Ah additions in the 6.9 through 6.11 kernels, but mostly for benefit on the AMD EPYC server processor side and for the Ryzen AI 300 series mobile/laptop processors. Using Linux 6.8 can work out just fine on the AMD Ryzen 9000 series desktops.
For those wondering if there are any performance gains to find if going for Linux 6.11 (currently in Git) versus the Linux 6.8 kernel on Ubuntu 24.04 LTS, I ran some quick benchmarks to explore that area.
On the AMD Ryzen 9 9950X desktop I ran some benchmarks using the stock Ubuntu 24.04 LTS kernel and then repeated using the latest Ubuntu Mainline Kernel PPA daily image of the Linux 6.11 Git kernel.
In a few of the heavier workloads like renders and video encoding, there were some very slight advantages of using Linux 6.11 Git compared to the stock Linux 6.8 kernel on this current Ubuntu Long Term Support release. It was typically 2% or less difference but consistently with a very slight edge for Linux 6.11. But for lighter workloads and other cases there was no measurable difference at all. All those flat results not shown but here's the geo mean across the many different workloads tested:
Moving to Linux 6.11 (or 6.10 stable) can be worthwhile for enjoying other new kernel features, driver improvements like to the AMD Radeon graphics stack, or other areas, but as far as the AMD Ryzen 9 9950X performance there was no major difference over the stock Ubuntu 24.04 LTS kernel.
| 1
| 1,760,718,872.77001
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https://www.phoronix.com/news/AMD-Acquiring-ZT-Systems
|
AMD Acquiring Another Company To Bolster Its AI Play
|
Michael Larabel
|
AMD just announced that they have entered into a definitive agreement to acquire ZT Systems, a hyperscale solutions provider focused on AI.
ZT Systems is a provider of AI and general purpose compute infrastructure and is engaged with the big name hyperscalers. AMD is acquiring ZT Systems for expertise to complement the AMD hardware and software capabilities. ZT Systems sells purpose-built server solutions, high performance accelerator solutions, integrated rack offerings, various HPC solutions, and is an OCP Gold Member.
AMD is acquiring ZT Systems in a cash and stock deal valued at $4.9 billion USD. AMD expects the deal to close in H1'2025.
More details on AMD's plans to acquire ZT Systems via this morning's press release.
This follows other recent acquisitions by AMD with an AI mindset such as Silo AI and Nod.ai.
| 35
| 1,760,718,873.553756
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https://www.phoronix.com/news/AMD-Open-Source-FW-Strategy
|
AMD To Provide Update On Long-Term Strategy For Open-Source Firmware
|
Michael Larabel
|
Next month AMD will be providing an update on their long-term strategy for open-source firmware. Central to their open-source firmware plans is their OpenSIL effort that remains in development for eventually replacing AGESA on future generations of Ryzen and EPYC platforms.
Happening from 3 to 5 September is the Open-Source Firmware Conference (OSFC) taking place in Bochum, Germany. Among the interesting talks for this event will be AMD firmware engineer Paul Grimes talking about AMD's long-term strategy for open-source firmware. The talk abstract reads:
"AMD has an enduring commitment to advance the state of the art through contributions to open-source firmware and software. As such, this presentation aims to provide an in-depth look at AMD's long-term open source firmware strategy, focusing on the evolution of the AMD openSIL project, a high level overview of validation and quality assurance processes, and the expansion of AMD’s presence in Tianocore.
We will discuss: the addition of AMD openSIL features in the AMD EPYC™ Genoa and Turin POC and early POR project phases; the effort of validating and upstreaming AMD openSIL and its supporting Host FW; and how this fits into AMD's overall strategy for releasing firmware in the future.
By providing insight into AMD’s long-term commitment and plans for open source firmware, we aim to foster understanding and collaboration within the open source firmware community." AMD has long talked about their OpenSIL proof-of-concept implementation for AMD EPYC Genoa while this will be their first time talking about OpenSIL running on EPYC Turin (Zen 5). It will be interesting to see what more they reveal about AMD OpenSIL and if there are any new road-map plans that they'll be publicly sharing.
It's previously been noted that around 2026 they hope OpenSIL will be ready for production and spanning both client and server platforms. Exciting times ahead and stay tuned to Phoronix for the latest AMD OpenSIL details in September.
More details on the Open-Source Firmware Conference in general can be found at OSFC.io.
| 22
| 1,760,718,874.494671
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https://www.phoronix.com/news/AMD-EPYC-SDCI-Cache-Injection
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AMD Preparing Linux For Smart Data Cache Injection With "Upcoming" CPUs
|
Michael Larabel
|
AMD Linux engineers are preparing the kernel for Smart Data Cache Injection (SDCI) as a feature for AMD EPYC server processors. Smart Data Cache Injection is a nifty new feature that allows for direct insertion of data from I/O devices into the CPU's L2/L3 cache.
Sent out today was a new patch series in preparing the Linux kernel's resource control "resctrl" functionality for L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE). That new patch series explains of SDCI and SDCIAE:
"Upcoming AMD hardware implements Smart Data Cache Injection (SDCI). Smart Data Cache Injection (SDCI) is a mechanism that enables direct insertion of data from I/O devices into the L3 cache. By directly caching data from I/O devices rather than first storing the I/O data in DRAM, SDCI reduces demands on DRAM bandwidth and reduces latency to the processor consuming the I/O data. The SDCIAE (SDCI Allocation Enforcement) PQE feature allows system software to limit the portion of the L3 cache used for SDCI."
The AMD Smart Data Cache Injection support depends in turn upon PCI Express TLP Processing Hints (TPH) that were covered on Phoronix a few months ago when AMD engineers posted patches there. PCI Express TLP Processing Hints are hints that can be injected for improving latency and lowering traffic congestion when there are several possible cache locations in the system to indicate the optimal location of a Transaction Layer Packet (TLP).
The patches indicate "upcoming" and "new" AMD hardware will support Smart Data Cache Injection. But SDCI was announced as a feature originally back for AMD EPYC Genoa(X) / Bergamo. Since then we haven't heard much about SDCI and are only seeing these Linux kernel patches now. The timing is also a bit peculiar ahead of the AMD EPYC Zen 5 "Turin" launch. So given the current messaging, it's not clear if this SDCI support is for existing EPYC Bergamo/Genoa(X) server processors or only for upcoming platforms if there ends up being a significant difference in the SDCI implementation or not.
SDCI has appeared in AMD programmer documentation since last year while the Linux kernel patches are only surfacing now and building off the recent PCIe TPH work. AMD SDCI is able to let DMA data be pre-fetched into the cache of target CCXs rather than going first into DRAM, in order to help lower latency, increase performance, and conserve memory bandwidth. In digging deeper into the AMD Linux efforts around SDCI, at least the initial drivers (SDCI users) in mind for this functionality are around Linux network drivers.
| 31
| 1,760,718,874.986965
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https://www.phoronix.com/news/AMD-Bus-Lock-Detect-Coming
|
AMD Bus Lock Detect Positioned Ahead Of Linux 6.12
|
Michael Larabel
|
Going back four years ago Intel engineers worked out bus lock detection for the Linux kernel to benefit their processors able to detect bus locks and then notify the kernel, given the negative performance implications associated with bus locks. That Intel support was merged in Linux 5.13 back in 2021 while now AMD has their equivalent ready for mainlining in the Linux kernel.
The Linux kernel bus lock detection is being extended to support AMD's Bus Lock Trap feature being introduced with the Zen 5 processors.With AMD Bus Lock Trap, a #DB exception is raised when a bus lock occurs.
AMD Linux engineers have had their Bus Lock Detect / Bus Lock Trap patches out for a few months while the code has now been queued into TIP/TIP.GIT's x86/splitlock Git branch. With the AMD support working its way into a TIP branch, it should be submitted for the upcoming Linux 6.12 merge window opening in mid-September.
The AMD Bus Lock Trap support for Linux re-uses the infrastructure established by Intel with their Bus Lock Detect code and now sharing the same X86_BUS_LOCK_DETECT Kconfig option and related code.
| 7
| 1,760,718,875.435048
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https://www.phoronix.com/news/AMDXDNA-Linux-Driver-v2
|
AMD XDNA Linux Kernel Driver For Ryzen AI Updated
|
Michael Larabel
|
At the start of the year AMD posted an open-source XDNA Linux driver to GitHub for supporting the Ryzen API NPU IP found within their newest Ryzen mobile SoCs. It wasn't until last month though in mid-July that AMD began the process of submitting the driver for review so that it can work its way toward the mainline Linux kernel within the "accel" accelerator subsystem. Today brings a second revision to that driver.
AMDXDNA v2 was posted a few minutes ago as the revised patches for supporting the AMD Ryzen AI NPUs. The v2 iteration has some minor code changes and some other minor work as a result of early code review collected over the past three weeks.
"NPU (Neural Processing Unit) is an AI inference accelerator integrated into AMD client CPUs. NPU enables efficient execution of Machine Learning applications like CNNs, LLMs, etc. NPU is based on AMD XDNA architecture.
AMD NPU consists of the following components:
- Tiled array of AMD AI Engine processors.
- Micro Controller which runs the NPU Firmware responsible for command processing, AIE array configuration, and execution management.
- PCI EP for host control of the NPU device.
- Interconnect for connecting the NPU components together.
- SRAM for use by the NPU Firmware.
- Address translation hardware for protected host memory access by the NPU.
NPU supports multiple concurrent fully isolated contexts. Concurrent contexts may be bound to AI Engine array spatially and or temporarily.
The driver is licensed under GPL-2.0 except for UAPI header which is licensed GPL-2.0 WITH Linux-syscall-note." So far the AMDXDNA Linux kernel driver has open-source user-space software supporting it of the Xilinx XRT and AMD AIE Plugin for IREE. Eventually the AMD Unified AI Software Stack will come.
We'll see how the v2 patches are reviewed. Hopefully this AMDXDNA kernel driver will be deemed ready for merging the next cycle, which would be Linux 6.12 and also happens to be this year's Long Term Support (LTS) kernel. The Linux 6.12 merge window opens in September but the stable release won't be out until around late November, which sadly puts AMDXDNA out of reach for the likes of Ubuntu 24.10 for having out-of-the-box Ryzen AI NPU support. Long story short, hopefully in 2025 we'll be seeing a more robust and out-of-the-box AMD NPU/AI experience on Linux.
| 3
| 1,760,718,876.442921
|
https://www.phoronix.com/news/Linux-6.11-rc2-More-AMD-Zen-5
|
Linux 6.11-rc2 To Recognize More AMD Zen 5 CPUs
|
Michael Larabel
|
Ahead of the Linux 6.11-rc2 kernel due for release later today there is the weekly "x86/urgent" material to merge.
The x86/urgent churn this week includes a deadlock fix in the aperf/mperf driver and some other fixes. Arguably most notable is adding some missing AMD Zen 5 CPU model numbers.
The AMD Linux code has been treating Zen 5 as Family 1Ah processors with model IDs between 0x00 to 0x2f, 0x40 to 0x4f, and 0x70 to 0x7f. But it turns out that it should be 0x60 to 0x7f as recognized Zen 5 models... That 0x60 to 0x6F model range were not covered by the current Linux kernel (models 96 to 111).
Current AMD Ryzen AI 300 "Strix Point" processors are Family 26 Model 36 and the upcoming Ryzen 9000 "Granite Ridge" are Family 26 Model 68. So the kernel's shortcoming of not recognizing the entire range of Zen 5 isn't immediately pressing but presumably some additional parts will eventually be released in that newly expanded range.
So far Family 26 (1Ah) is just used by Zen 5 processors and in some areas like the LLVM Clang compiler is treating all Family 26 processors with models 128 or less as Zen 5. If traditions hold, Family 26 may end up being shared with Zen 6 too before moving onto a different family ID.
Anyhow, today's x86/urgent pull request for merging before the Linux 6.11-rc2 release tonight has that expanded range of AMD Zen 5 model numbers.
| 0
| 1,760,718,877.300783
|
https://www.phoronix.com/news/AMD-HDMI-Audio-Fix-Linux-6.11
|
Linux 6.11 Addressing "Long-Time Regression" Of Buggy AMD HDMI Audio
|
Michael Larabel
|
For those that have experienced a buggy AMD HDMI audio experience when using recent versions of the Linux kernel, a fix has been submitted today for Linux 6.11 and in turn for back-porting to stable series in addressing "another long-time regression fix for AMD HDMI."
The fix to the Linux HDA audio driver is to only conditionally use snooping for AMD HDMI hardware. It's a regression fix to a change that was made to the Linux kernel back in March of 2022 that dropped CONFIG_DMA_REMAP. Leading to action now on this buggy HDMI audio was this recent bug report citing AMD HDMI audio with a Navi graphics card citing audio skipping, stuttering, and white noise. That bug reporter also bisected the problem that led to quick action in resolving the situation.
"I am having severe audio issues when using ALSA and HDMI audio which include skipping, stuttering and white noise. This can be reproduced by playing a flac music file with mpv where increased even minor CPU usage greatly affects audio quality. For example opening a web browser (Firefox) will break the sound momentarily and normal usage with many programs open will cause the audio to be entirely broken. If only mpv is running with no other usage including changing focus in the window manager then audio is mostly okay." Takashi Iwai of SUSE and the longtime Linux sound subsystem maintainer worked through a fix where he explained:
"The recent regression report revealed that the use of WC pages for AMD HDMI device together with AMD IOMMU leads to unexpected truncation or noises. The issue seems triggered by the change in the kernel core memory allocation that enables IOMMU driver to use always S/G buffers. Meanwhile, the use of WC pages has been a workaround for the similar issue with standard pages in the past. So, now we need to apply the workaround conditionally, namely, only when IOMMU isn't in place.
This patch modifies the workaround code to check the DMA ops at first and apply the snoop-off only when needed." That fix is now on its way to Linux 6.11 Git this morning as part of the week's sound fixes pull request and from there can be back-ported to stable kernel series.
Today's pull request also happens to address a long-time regression around Linux's Firewire audio support. Those Firewire problems have been around since the 2021 kernel code.
| 6
| 1,760,718,878.266699
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https://www.phoronix.com/news/Ryzen-AI-Heterogeneous-Core-Top
|
Testing The AMD Heterogeneous Core Topology Linux Patches On Ryzen AI 300 Series
|
Michael Larabel
|
Now that I am through with my testing of the initial Ryzen AI 9 HX 370 and Ryzen AI 9 365 Linux performance benchmarking and support exploration, I've begun diving in to other areas of the Linux support/performance for these Zen 5 "Strix Point" SoCs. The area for a quick look today is with the yet-to-be-merged AMD Heterogeneous Core Topology patches.
As I wrote about back in May, AMD Linux engineers have posted patches for Heterogeneous Core Topology for the AMD P-State driver to help with processors that boast a mix of core types like Zen 5 and Zen 5C. Those patches were updated in June but as of writing have yet to be merged to the mainline Linux kernel. They weren't submitted for the recent Linux 6.11 merge window and thus as short of flagging it as a "fix", the earliest we'll now see that code merged is for the Linux 6.12 kernel cycle that will end out the year.
With the current Linux kernel, indeed on the AMD Ryzen 9 365 there was no differentiation between the Zen 5 and Zen 5C cores on the Ryzen AI 9 365 (and HX 370). Both the same max frequency and highest performance state (ACPI CPPC value) were uniformally reported across all processor cores... Even though the Ryzen AI 9 365 has four Zen 5 cores and six Zen 5C cores that max out at different frequencies.
When taking the AMD heterogeneous core topology patches from June and making some slight adjustments so that they would apply cleanly against Linux 6.11 Git, that kernel build then indeed switched over to reporting different capabilities between the Zen 5 and Zen 5C cores:
With the yet to be merged patches, the amd_pstate_highest_perf values were differentiated: 196 for the Zen 5 cores and the lower priority 132 on the Zen 5C cores. The maximum clock frequencies were also now properly reported: 5.09GHz for the Zen 5 cores and 3.4GHz for the Zen 5C cores.
So now they are properly differentiated, but at least in my initial testing of several dozen benchmarks and also monitoring the CPU/SoC power use, there wasn't much of a resulting performance difference. In the end it was just a 1~2% spread that may be easily eaten by noise / system heat in laptop form factor. So for the single-threaded workloads at least, Linux is seeming still getting lucky enough placing the tasks on the Zen 5 cores. We'll see if more optimizations come for the AMD heterogeneous core type handling on Linux or if it's already just "good enough", but that's where things are at today.
| 21
| 1,760,718,879.193838
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https://www.phoronix.com/news/AMD-Ryzen-3000-P-State-Quirk
|
Ryzen 3000 Series Gain Workaround For AMD P-State Linux Driver
|
Michael Larabel
|
For those still running an AMD Ryzen 3000 series "Zen 2" desktop it really ought to be time to upgrade soon for better performance and power efficiency given the Zen 5 performance benchmarks thus far, but for those still planning to use the Ryzen 3000 series for some time, a quirk/workaround is on the way for enabling more of those older platforms to work with the AMD P-State Linux driver.
The AMD P-State driver can allow for better performance and power efficiency than the generic ACPI CPUFreq driver. However, for Zen 2 where ACPI CPPC support was originally introduced, a number of Ryzen 3000 systems have missing nominal frequency (nominal_freq) and lowest frequency (lowest_freq) parameters in their ACPI tables. That missing data in turn has caused issues when trying to use the AMD P-State driver.
This patch should fix things up for the Ryzen 3000 series as the quirk will fall-back to using static values for the lowest frequency and nominal frequency parameters. The patch is currently being reviewed and could be picked up for the Linux v6.12 cycle later in the year.
| 19
| 1,760,718,879.578055
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https://www.phoronix.com/news/Unified-AI-Software-MLIR-SPIR-V
|
AMD's Unified AI Software Stack Might Be A Boon For Other Vulkan/SPIR-V Hardware Too
|
Michael Larabel
|
Earlier this month AMD talked more about their Unified AI Software Stack plans for debuting in the coming months to provide a unified software view where AI work can be seamlessly offloaded to Ryzen processors, AMD graphics, or AMD Ryzen AI NPU hardware. Another possible and exciting prospect came to mind when going through the LLVM/Clang 19 changes this week.
As talked about in the prior article on the AMD Unified AI Software Stack, the center piece of it is using LLVM's MLIR intermediate representation before this unified software decides which device to offload the AI work to. It makes sense given the robust capabilities of MLIR, it being more suited for AI than other IRs, their acquired MLIR talent, etc.
AMD has talked up this Unified AI Software Stack just in the context of AMD's different hardware devices. But then what struck me this week was remembering that for LLVM/Clang 19 an AMD AI compiler engineer began landing a generic MLIR to SPIR-V pass. That member of AMD's AI compiler team began upstreaming work to allow converting the Multi-Level Intermediate Representation into SPIR-V, as the IR that can be consumed by Vulkan drivers along with modern OpenGL and OpenCL drivers.
There has been continued work since on the generic "convert-to-spirv" pass for MLIR. Just yesterday for example was a merge request opened for LLVM to support vector unrolling with the pass. And again it comes from an AMD AI compiler engineer.
It remains to be seen if this MLIR to SPIR-V pass being worked on by AMD AI compiler engineers is indeed for the Unified AI Software Stack, but the timing is interesting and it would fit rather well with AMD's "unified" software plans. Once this pass is full-featured enough, in theory the generic MLIR-to-SPIR-V pass could be used for targeting other Vulkan and OpenCL/OpenGL supported graphics cards / devices. SPIR-V is a common IR and not specific to AMD. So if this convert-to-spirv pass becomes viable enough, it could potentially open the door to the AMD Unified AI Software Stack working for other non-AMD GPUs. This would be convenient if it becomes a reality but there may be some limitations around other AI support libraries and the like making up the rest of AMD's AI compute stack.
This might also be useful in cases of Radeon GPUs of having their Vulkan/SPIR-V support but not having ROCm compute libraries installed or available to instead go through SPIR-V. There's also routes to execute SPIR-V on the CPU and other possibilities once the MLIR is transitioned to the Khronos Group backed IR.
In any event after the recent Unified AI Software Stack talk from the AMD Tech Day and then remembering AMD AI compiler engineers have recently been working on the generic MLIR to SPIR-V pass for upstream LLVM, very interesting and innovative software times for AMD may be ahead.
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| 1,760,718,880.306023
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https://www.phoronix.com/news/AMD-I3C-HCI-Linux-Driver
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New AMD Linux Driver Patches Enable I3C HCI Support
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Michael Larabel
|
One of the newest patch series out from AMD this week is on providing I3C HCI driver support for their MIPI I3C IP block found within their latest processors.
MIPI's I3C is the successor to I2C for a low-power, two-wire utility and control bus interface to connect the processor to different peripheral devices. The I3C and I3C HCI (Host Controller Interface) specifications retain backwards compatibility with legacy I2C. I3C has a range of uses from embedded/IoT up through server platforms and other devices. I3C support is found on AMD processors going back to Zen 4.
The Linux support for I3C is provided by the "mipi-i3c-hci" driver for the host controller interface and after all it's designed to be re-used across hardware platforms and adaptable. The MIPI I3C HCI driver was mainlined back in 2020 but now for supporting the AMD I3C IP block some alterations are needed.
The MIPI I3C HCI driver to this point has catered to platforms using DeviceTree bindings while with AMD's new patches it extends the support to work on ACPI-enabled x86 systems. Besides allowing the ACPI matching via the MIPI0100 ACPI device ID, some changes to the driver were also warranted to address defects in the AMD I3C IP:
"The AMD SoC includes an I3C IP block as part of the Fusion Controller Hub (FCH). This series introduces the initial driver support to enable the I3C IP block on AMD's latest processors.
Currently, the code is closely tied to dt-bindings. This initial set aims to decouple some of these bindings by adding the MIPI ID, allowing the current driver to support ACPI-enabled x86 systems.
It was discovered that the AMD I3C controller has several hardware issues, including:
- Non-functional DMA mode (defaulting to PIO mode)
- Issues with Open-Drain (OD) and Push-Pull (PP) timing parameters
- Command response buffer threshold values
All of these issues have been addressed in this series."
So for those interested in I3C, this patch series gets the AMD I3C HCI support ironed out and is currently under review on the Linux kernel mailing list.
| 1
| 1,760,718,881.223354
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https://www.phoronix.com/news/AMD-Ryzen-9000-Series-Delay
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AMD Ryzen 9000 Series Launch Delayed To August
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Michael Larabel
|
While we have been super eager for the AMD Ryzen 9000 series "Zen 5" desktop processor launch that's been set for 31 July, AMD has issued a last minute delay. Instead the processors will launch in two stages in August.
AMD emailed over the following statement a few minutes ago regarding the Ryzen 9000 series launch delay:
"We appreciate the excitement around Ryzen 9000 series processors. During final checks, we found the initial production units that were shipped to our channel partners did not meet our full quality expectations. Out of an abundance of caution and to maintain the highest quality experiences for every Ryzen user, we are working with our channel partners to replace the initial production units with fresh units. As a result, there will be a short delay in retail availability. The Ryzen 7 9700X and Ryzen 5 9600X processors will now go on sale on August 8th and the Ryzen 9 9950X and Ryzen 9 9900X processors will go on sale on August 15th. We pride ourselves in providing a high-quality experience for every Ryzen user, and we look forward to our fans having a great experience with the new Ryzen 9000 series."
That's a bummer but at least it's only a slip by one week on the lower tier parts and then roughly two weeks on the higher-end Ryzen 9 9900X and Ryzen 9 9950X processors. At least AMD is taking the cautious approach to verify all parts hitting retail are in good shape.
See AMD Zen 5 Overview With Ryzen 9000 Series & Ryzen AI 300 and AMD Reveals More Zen 5 CPU Core Details for more information on the forthcoming AMD Zen 5 products.
In any case stay tuned to Phoronix for the eventual Linux reviews and benchmarking of the Ryzen 9000 series processors. The AMD Ryzen AI 300 series SoCs for laptops is not impacted and still set for launch on 28 July.
| 85
| 1,760,718,881.264293
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https://www.phoronix.com/news/AMD-SEV-SNP-SVSM-Linux-6.11
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AMD Advances Confidential Computing In Linux 6.11 With SEV-SNP + SVSM Guest Support
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Michael Larabel
|
The AMD Secure Encrypted Virtualization (SEV) changes have been submitted for the recently opened Linux 6.11 merge window. Notable this cycle is getting support in the mainline kernel for SEV-SNP guest support over a Secure VM Service Module (SVSM).
As reported on a few months back, the mainline kernel support around Secure Encrypted Virtualization Secure Nested Paging (SEV-SNP) was nearing "the ultimate goal of the AMD confidential computing side, providing the most comprehensive confidential computing environment up to date." While the hope then was to have it all buttoned up for Linux 6.10, now with Linux 6.11 it appears to be that way with the SEV-SNP guest bits landing.
AMD Linux engineer Borislav Petkov today sent out the x86/sev pull request and explained:
"Add support for running the kernel in a SEV-SNP guest, over a Secure VM Service Module (SVSM).
When running over a SVSM, different services can run at different protection levels, apart from the guest OS but still within the secure SNP environment. They can provide services to the guest, like a vTPM, for example.
This series adds the required facilities to interface with such a SVSM module." That pull as of minutes ago was merged to Linux 6.11 Git.
Additionally, to be sent in separately as part of the KVM updates for Linux 6.11 is the long-awaited SEV-SNP KVM guest support for the mainline kernel. That's been a long time coming and up to now maintained out-of-tree by AMD while it went through the lengthy review process.
For the Secure VM Service Module, AMD does maintain this repository providing a Linux SVSM module for secure x86 virtualization in Rust and their newer solution is the COCONUT SVSM for confidential VMs.
SEV-SNP is found with AMD EPYC processors since the EPYC 7003 "Milan" series for providing greater security for virtual machines.
| 26
| 1,760,718,882.795378
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https://www.phoronix.com/news/AMD-XDNA-Ryzen-AI-Driver-Patch
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AMD XDNA Ryzen AI Linux Kernel Driver Posted For Review
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Michael Larabel
|
Back in January AMD quietly posted an XDNA Linux kernel driver for enabling the Ryzen AI NPUs. The driver has been maintained within that GitHub repository since but without any clear effort for getting this accelerator driver reviewed and merged into the upstream Linux kernel. Today that first step is finally being taken with the Ryzen AI XDNA Linux kernel driver patches posted to the Linux kernel mailing list and dri-devel to begin facilitating the upstream review process for getting this AI accelerator driver in the mainline kernel.
It's unfortunate that it has taken so long to get the XDNA Linux driver out there in the first place considering the Ryzen 7040 series with Ryzen AI have been out for the past year. And then another half-year after open-sourcing the driver publicly to begin the review process. In any event, at least today's milestone has finally arrived.
AMD engineer Lizhi Hou posted the set of ten patches implementing the "AMDXDNA" Linux kernel driver for review and to live within the accelerator "accel" area of the kernel. In current form the kernel driver is 8,177 lines of new code. Lizhi Hou wrote of the initial XDNA Linux driver:
"This patchset introduces a new Linux Kernel Driver, amdxdna for AMD NPUs. The driver is based on Linux accel subsystem.
NPU (Neural Processing Unit) is an AI inference accelerator integrated into AMD client CPUs. NPU enables efficient execution of Machine Learning applications like CNNs, LLMs, etc. NPU is based on AMD XDNA architecture.
AMD NPU consists of the following components:
- Tiled array of AMD AI Engine processors.
- Micro Controller which runs the NPU Firmware responsible for command processing, AIE array configuration, and execution management.
- PCI EP for host control of the NPU device.
- Interconnect for connecting the NPU components together.
- SRAM for use by the NPU Firmware.
- Address translation hardware for protected host memory access by the NPU.
NPU supports multiple concurrent fully isolated contexts. Concurrent contexts may be bound to AI Engine array spatially and or temporarily.
The driver is licensed under GPL-2.0 except for UAPI header which is licensed GPL-2.0 WITH Linux-syscall-note." The Ryzen AI NPU does depend upon closed-source firmware binaries for this driver to function. Going along with the kernel driver over in user-space the Xilinx XRT and AMD AIE Plugin for IREE are the initial open-source users that can interface with this NPU kernel driver.
There is other user-space work ongoing for embracing AMD XDNA such as the Unified AI Software Stack and Peano LLVM compiler.
The AMD XDNA Linux driver patch series currently out for upstream kernel developer review can be found on the mailing list. Here's to hoping that the code review process goes smoothly and quickly. The Linux 6.11 merge window is currently ongoing and while it's possible for new drivers to be merged post-merge-window, typically it doesn't happen too often. Thus at the earliest we would see the AMD XDNA driver integrated into the mainline Linux kernel would potentially be the v6.12 cycle if the review process is punctual. Linux 6.12 is likely to be this year's LTS release but unfortunate for the timing as v6.11 will likely be the kernel powering Ubuntu 24.10 and other autumn Linux distributions. In any event the AMD XDNA driver is also available out-of-tree from AMD's GitHub repository for those interested.
| 20
| 1,760,718,882.807453
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https://www.phoronix.com/news/AMD-July-2024-CPU-Microcode
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AMD Provides Updated Zen 1/2/3/4 CPU Microcode For Linux Users
|
Michael Larabel
|
Updated AMD CPU microcode was published today and subsequently merged into linux-firmware.git for all Family 17h and Family 19h processors, spanning Zen 1 through Zen 4 models.
This is the first time since last December that the Family 17h (Zen 1, Zen 1+, Zen 2) microcode has been updated in linux-firmware.git. Family 19h (Zen 3 and 4) is seeing its first linux-firmware.git CPU microcode update since January. As is typically the case though, they do not publish any change-log for outlining what has changed in the CPU microcode updates.
Today's commit simply notes:
* Update AMD cpu microcode for processor family 17h
* Update AMD cpu microcode for processor family 19h
Key Name = AMD Microcode Signing Key (for signing microcode container files only)
Key ID = F328AE73
Key Fingerprint = FC7C 6C50 5DAF CC14 7183 57CA E4BE 5339 F328 AE73 But long story short, it's likely to integrate various functional and security fixes that have come up over the past half year.
With these firmware binaries now upstream in linux-firmware.git, they should soon be working their way down to downstream Linux distribution "linux-firmware" package updates and the like.
| 94
| 1,760,718,883.622172
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https://www.phoronix.com/news/AMD-Acquires-Silo-AI
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AMD Acquires Another AI Company To Expand Its Enterprise AI Solutions
|
Michael Larabel
|
Following their acquisition last year of open-source AI provider Nod.ai and other AI investments, AMD today announced they are acquiring Silo AI.
Silo AI is Europe's largest private AI lab focused on collaborating with various organizations around enterprise AI needs. AMD is acquiring Silo AI for approximately $665 million USD with the acquisition expected to close in H2'2024.
"The agreement represents another significant step in the company’s strategy to deliver end-to-end AI solutions based on open standards and in strong partnership with the global AI ecosystem. The Silo AI team consists of world-class AI scientists and engineers with extensive experience developing tailored AI models, platforms and solutions for leading enterprises spanning cloud, embedded and endpoint computing markets.
...
Based in Helsinki, Finland, with operations in Europe and North America, Silo AI specializes in end-to-end AI-driven solutions that help customers integrate AI quickly and easily into their products, services and operations. Their work spans diverse markets, with customers including Allianz, Philips, Rolls-Royce and Unilever. Silo AI also creates state-of-the-art open source multilingual LLMs, such as Poro and Viking, on AMD platforms in addition to its SiloGen model platform." More details on AMD's acquisition of Silo AI via this morning's press release.
| 79
| 1,760,718,884.601421
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https://www.phoronix.com/news/AMD-Unified-AI-Software-Stack
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AMD Unified AI Software Stack Has The Potential To Be A Very Big Deal
|
Michael Larabel
|
Alongside all of the exciting Ryzen 9000 and Ryzen AI 300 series details shared last week at the AMD Tech Day in Los Angeles, what I also found to be very interesting was AMD sharing a bit more about a "Unified AI Software Stack" they are working to release in the coming quarters.
AMD is working to introduce a Unified AI Software Stack around the end of the calendar year. Simply put, it aims to ensure a performant and optimally accelerated AI experience whether it means tasking your CPU cores, NPU, or GPU(s) with AI workloads. Details were relatively light at this point as there's still months to go until its debut, but it's a very interesting topic and I wish they would have had a session dedicated entirely on it -- but presumably we'll be learning much more as the actual software release nears. This also isn't the first time we've heard AMD bring up a "Unified AI Software Stack" as back in 2022 and then in 2023 briefly mentioned such plans, but now it looks like it's finally coming to fruition.
This isn't a replacement to ROCm or other existing AMD AI software efforts but from the sounds of it at least will serve as sort of an AI workload scheduler and other libraries to help in a unified offloading interface to AMD's heterogeneous products. Developers targeting the AMD Unified AI Software Stack will target LLVM's wonderful MLIR intermediate representation. From there the Unified AI Software Stack will evaluate the MLIR characteristics and determine whether to send the work off to the CPU, GPU, or NPU for execution. At least that's how it was summed up rather simply when brought up last week in LA. So taking into account the MLIR for execution and each AMD device's capabilities (hardware features, current resource utilization, etc), the Unified AI Software Stack will be able to make an informed choice over where to place the workload for execution.
Focusing on MLIR (the Multi-Level Intermediate Representation) as the IR makes sense given it's a great intermediate representation and has a lot of usage around the LLVM community/developers. It also makes sense given AMD's acquisition last year of Nod.ai with all of their MLIR developer talent. Unlike LLVM IR and some alternative forms of intermediate representation, MLIR is able to represent data-flow graphs such as with TensorFlow as well as a variety of other features to help with deep learning workloads and better handling hardware-specific operations.
I wasn't able to get a direct answer last week in LA but I brought up the fact that a few weeks early I spotted the new Peano LLVM-based compiler for AMD NPUs. Presumably this AMD Peano compiler will be part of this Unified AI Software Stack for taking the MLIR to NPU (AMD XDNA) execution path.
This does also leave open questions on whether Xilinx / XDNA will see ROCm support... Phoronix readers may recall that back in 2020 ROCm was going to support Xilinx FPGAs but since then there hasn't been much on the topic of ROCm for Xilinx and in turn the XDNA IP now making up their NPUs. We'll see if this Unified AI Software Stack ends up making it unnecessary thanks to the new Peano compiler and the like at least on the XDNA side and focusing on MLIR as the common denominator for the AMD AI compute ecosystem.
It will also be interesting to see if this Unified AI Software Stack ends up working out well for any non-AMD products given the number of different LLVM back-ends out there and the focus on common MLIR. Likewise, it will be interesting to see how well this offload manager / job scheduler works for non-AI workloads given that MLIR can handle much more than just AI workloads but at the same time is limited by each backends exposed capabilities.
It's also possible -- and likely -- the AMD Unified AI Software Stack will introduce more than just this new scheduler / decision maker (execution manager) bits, so we'll see when the time comes what else AMD may introduce to ease the ISV developer experience. At the same time expect ROCm to continue to mature and advance for AI workloads (and more) on GPUs for compute and AMD's other library and compiler improvements. From the sounds of it, the AMD Unified AI Software Stack will be open-source just as they are with their other software components. The slide on Unified AI Software Stack seems to indicate that new optimization utilities and compiler tech may come as part of this new software offering.
For now there are many more questions than answers about the AMD Unified AI Software Stack, but I am hopeful it will lead to many new and interesting AMD AI opportunities over the coming months. At the very least it will hopefully help ISVs juggle their AI workload management between AMD CPUs, GPUs, and NPUs on systems. At the same time though it's unfortunate that such workload partitioner / execution scheduler wasn't available from the start when AMD first introduced Ryzen AI NPUs or even in advance with a CPU+GPU+Xilinx focus to help prepare the developer community for being able to take advantage of AMD's heterogeneous compute offerings. Instead by the time it publicly arrives Ryzen AI NPUs will have been in the marketplace for the better part of two years. But as they say, better late than never and hopefully as 2024 continues on and moving into 2025 we see more continued serious software investments by AMD.
| 18
| 1,760,718,885.465384
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https://www.phoronix.com/news/AMD-Core-Perf-Boost-Linux-6.11
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AMD P-State Core Performance Boost To Be Merged For Linux 6.11
|
Michael Larabel
|
Linux 6.11 is shaping up to be an exciting summertime kernel cycle for AMD Ryzen owners. The newest feature now being queued ahead of next month's merge window is Core Performance Boost support within the AMD P-State CPU frequency scaling driver.
The AMD P-State CPUFreq driver is seeing a number of new features with Linux 6.11. Already queued up within the power management subsystem's "-next" branch for Linux 6.11 are AMD Fast CPPC for enhancing power efficiency in some configurations and various other amd-pstate improvements. Now on Thursday the AMD Core Performance Boost support was submitted.
These patches have been under review the past several months and allow for toggling Core Performance Boost under Linux for opting in/out of utilizing the processor's turbo/boost frequency range. This includes the ability to individually control Core Performance Boost on a per-CPU core basis.
This Core Performance Boost (CPB) support for the AMD P-State driver took fifteen rounds of revising the patches while now are ready for the mainline kernel. This pull request stages the AMD P-State CPB support ahead of the Linux 6.11 merge window opening in mid-July.
Linux 6.11 for AMD users is also set to deliver more RDNA4 GPU enablement, upstreaming AMD SEV-SNP KVM guest support, and faster AES-GCM crypto among other general kernel improvements.
| 27
| 1,760,718,885.64651
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https://www.phoronix.com/news/AMD-AOMP-19.0-2-Compiler
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AMD's AOMP 19.0-2 Compiler Brings Zero-Copy For CPU-GPU Unified Shared Memory
|
Michael Larabel
|
AMD compiler engineers have released AOMP 19.0-2 as the newest version of their downstream LLVM/Clang compiler that carries all of their latest work around OpenMP/AOCC GPU device offloading to Radeon and Instinct hardware. With this updated AOMP compiler is now run-time support for zero-copy with CPU-GPU unified shared memory and various other new features for this GPU/accelerator-focused compiler.
The big new feature of AOMP 19.0-2 is "significant" run-time feature work for supporting zero-copy for CPU-GPU unified shared memory. Implicit zero-copy can be done most optimally with OpenMP parallel programming on the AMD Instinct MI300A APUs. Implicit zero-copy can also be done on the MI200/MI300X and other discrete AMD GPUs by running the application(s) in an XNACK-enabled environment and setting the "HSA_XNACK=1 OMPX_APU_MAPS=1" environment variables.
AOMP 19.0-2 also re-bases against the latest LLVM 19 Git codebase, builds from the ROCm 6.1.2 sources, and has "significant" improvements to its gpurun utility. The gpurun helper CLI program now supports multiple accelerators/GPUs, heterogeneous devices, and other features. AOMP 19.0-2 is also now capable of handling FP16 and BFloat16 reductions.
The AOMP 19.0-2 source code can be downloaded as well as pre-built Ubuntu / RHEL / SUSE Linux Enterprise binaries of this compiler. More details over on GitHub.
| 28
| 1,760,718,886.851486
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https://www.phoronix.com/news/AMD-P-State-Linux-6.11-Round-2
|
More AMD P-State Driver Improvements Queued For Linux 6.11
|
Michael Larabel
|
Earlier this month AMD Fast CPPC support was queued into the Linux power management subsystem's "-next" codebase ahead of the Linux 6.11 cycle. Additional AMD P-State driver enhancements are now deemed ready and submitted for staging ahead of next month's Linux 6.11 cycle kicking off.
AMD Linux engineer Mario Limonciello has sent out a second set of AMD P-State CPU frequency scaling driver improvements for Linux 6.11.
These latest "amd_pstate" driver changes include enabling amd-pstate by default in "shared memory" designs without a
dedicated MSR, extra infrastructure for debugging purposes, and various bug fixes. The driver also now honors a "default" Energy Performance Preference (EPP) value for those wanting to reset their EPP preference to the platform default.
As for now enabling AMD P-State driver use on shared memory type systems by default, that patch message explains:
"The amd-pstate-epp driver has been implemented and resolves the performance drop issue seen in passive mode. Users who enable the active mode driver will not experience a performance drop compared to the passive mode driver. Therefore, the EPP driver should be loaded by default at system boot." Previously some CPU performance regressions were noted by SUSE and in turn preferred ACPI CPUFreq instead but those issues should now be resolved.
More details on these latest AMD P-State driver improvements via this pull request. Still being worked on for the AMD P-State driver meanwhile is the Core Performance Boost and better heterogeneous CPU handling.
| 16
| 1,760,718,887.235329
|
https://www.phoronix.com/news/AMD-ROCm-6.1.3-Announced
|
AMD Announces ROCm 6.1.3 With Better Multi-GPU Support, Beta-Level WSL2
|
Michael Larabel
|
AMD today announced the ROCm 6.1.3 open-source GPU compute stack. While a point release, this new ROCm revision comes with several notable refinements.
ROCm 6.1.3 contains improved multi-GPU support and will now work with up to four Radeon RX or Radeon PRO graphics cards. This multi-GPU support is "AI Optimized". Multiple GPUs already have been supported by the AMDGPU and AMDKFD kernel drivers while this effort appears to be on enhancing ROCm for better leveraging workloads across multiple GPUs concurrently with an emphasis on benefiting AI inference workloads.
With ROCm 6.1.3, AMD is also declaring now that their Windows Subsystem for Linux (WSL2) support has reached "beta level" support for those wishing to use ROCm ultimately under Windows 11.
The third pillar of the ROCm 6.1.3 release is TensorFlow Framework qualification support. AMD is also now officially supporting the new Radeon PRO W7900 Dual Slot graphics card with this release.
Overall it's a nice release for being a point release and coming just two weeks after ROCm 6.1.2. Unfortunately though Ubuntu 22.04 LTS is their primary Linux support target and there doesn't appear to be any official support yet for Ubuntu 24.04 LTS that debuted back in April.
The ROCm 6.1.3 announcement was made this morning on community.amd.com. As of writing though the ROCm on GitHub is still pointing to v6.1.2 as the latest. So it looks like the actual ROCm 6.1.3 software release isn't quite out yet but will hopefully be today or later this week otherwise.
| 6
| 1,760,718,888.604516
|
https://www.phoronix.com/news/AMD-SEV-SNP-Fedora-41-Plan
|
Fedora 41 Aims To Ship AMD SEV-SNP Confidential Virtualization Host Support
|
Michael Larabel
|
With the release of Fedora 41 in October, this Red Hat sponsored Linux distribution is hoping to have all the software bits aligned that its AMD SEV-SNP virtualization stack will be all squared away for this latest iteration of Secure Encrypted Virtualization.
If all goes according to newly-filed plans, Fedora 41 this autumn should be shipping with confidential virtualization host support for AMD SEV-SNP. This is coming about as all of the relevant upstream pieces are finally coming together. As noted recently on Phoronix, Linux 6.11 will bring the AMD SEV-SNP KVM guest bits. QEMU 9.1 is working its way toward release in the coming months and it has the SEV-SNP feature integration complete. Libvirt is also having its SEV-SNP support cross the finish line this summer. Fedora 41 is also planning to ship updated Coconut SVSM, iVGM, and EDK2 packages for rounding out the SEV-SNP support.
The change proposal was posted today to the Fedora Wiki for having this SEV-SNP support in Fedora 41:
"This enables Fedora virtualization hosts to launch confidential virtual machines using AMD's SEV-SNP technology. Confidential virtualization prevents admins with root shell access, or a compromised host software stack, from accessing memory of any running guest. SEV-SNP is an evolution of previously provided SEV and SEV-ES technologies providing stronger protection and unlocking new features such as a secure virtual TPM.
...
Fedora has provided support for launching confidential virtual machines using KVM on x86_64 hosts for several years, using the SEV and SEV-ES technologies available from AMD CPUs. These technologies have a number of design limitations, however, that make them less secure than is desired, and prevent exposure of desirable features such as secure TPMs. The SEV-SNP technology is a significant design enhancement and architectural change to addresses the key gaps, increasing security and unlocking more powerful use cases for confidential virtual machines." SEV-SNP is indeed a nice upgrade over the earlier SEV and SEV-ES capabilities:
It's great seeing all the upstream software bits finally coming together with SEV-SNP that is supported with AMD EPYC server processors since the EPYC 7003 "Milan" series. Other Q3~Q4 Linux distributions and later in turn should also be able to tap into this upstream support for the newest Secure Encrypted Virtualization functionality.
| 0
| 1,760,718,888.721482
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https://www.phoronix.com/news/AMD-Fast-CPPC-For-Linux-6.11
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AMD Fast CPPC To Be Merged For Linux 6.11
|
Michael Larabel
|
The AMD Fast CPPC feature enablement for the "amd_pstate" driver has been submitted to the power management subsystem ahead of next month's Linux 6.11 merge window.
As covered on Phoronix back in April, the AMD Fast CPPC functionality allows for better performance and power efficiency for some CPUs such as recent Ryzen (Zen 4) mobile processors. AMD Fast CPPC when supported by the CPU/platform allows for operating a tighter loop within the amd_pstate passive mode for more responsive CPU frequency / power state handling.
The Fast CPPC feature relies on architectural improvements with the processor to allow for higher performance at the same power level. The posted kernel patches allow the CPU frequency transition delay to be lowered from 1000 us to 600 us on systems with fast CPPC support. In turn depending upon the workload this can commonly lead to 0~2% better performance. On a performance-per-Watt basis some workloads can see as much as a 6% improvement. AMD's tests have been done for Fast CPPC using a Ryzen 7 7840HS APU. This Fast CPPC support on capable platforms is automatically utilized when upgrading to a kernel with the necessary support.
The AMD Fast CPPC support was submitted by AMD engineer Mario Limonciello for queuing in the power management "-next" branch ahead of the Linux 6.11 cycle. Not part of this pull request but separately are other AMD P-State driver improvements still pending such as improving support for heterogeneous CPU types that we're still waiting to see if will cross the finish line in time for the Linux 6.11 cycle too.
| 7
| 1,760,718,889.825738
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https://www.phoronix.com/news/AMD-P-State-Hetero-v3
|
AMD P-State Linux Patches Updated For Heterogeneous CPUs
|
Michael Larabel
|
Last month AMD Linux engineers posted ap atch series for better handling heterogeneous core type CPUs. This is for enhancing the P-State CPU frequency scaling on CPUs featuring a mix of conventional cores and efficiency cores, e.g. Zen 4 and Zen 4C. A third iteration of these patches were posted today.
AMD engineer Perry Yuan explains of this "amd_pstate" driver patch series:
"This patchset addresses critical issues and enhances performance settings for CPUs with heterogeneous core types in the AMD pstate driver. Specifically, it resolves problems related to calculating the highest performance and frequency on the latest CPUs with preferred cores. Additionally, the patchset includes documentation improvements in amd-pstate.rst, offering a comprehensive guide covering topics such as recommended reboot requirements during driver switching, debugging procedures for driver loading failures." Most interesting of the series is this one for heterogeneous core topology for highest performance initialization:
"Introduces an optimization to the AMD-Pstate driver by implementing a heterogeneous core topology for the initialization of the highest performance value while driver loading. There are two type cores designed including performance core and Efficiency Core. Each core type has different highest performance and frequency values configured by the platform. The `amd_pstate` driver needs to identify the type of core to correctly set an appropriate highest perf value.
X86_FEATURE_HETERO_CORE_TOPOLOGY is used to identify whether the processor support heterogeneous core type by reading CPUID leaf Fn_0x80000026_EAX and bit 30. if the bit is set as one, then amd_pstate driver will check EBX 30:28 bits to get the core type." With the v3 patches, additional code review has been carried out, they have been re-based against the latest Linux power management tree, more testing has completed, and various fixes.
Hopefully we'll see these AMD P-State driver patches ready for the Linux v6.11 kernel cycle later this summer.
| 2
| 1,760,718,890.687737
|
https://www.phoronix.com/news/Linux-6.10-rc4-PM-Ryzen-NVMe
|
New Linux Change Helps Ensure AMD Ryzen With NVMe Works After Resuming From Suspend
|
Michael Larabel
|
A Linux power management change merged on Friday aims to help ensure AMD Ryzen systems with NVMe solid-state drive storage will work properly when resuming from suspend.
Merged ahead of the Linux 6.10-rc4 kernel release tomorrow is a patch to help ensure more AMD Ryzen laptops/desktops put their NVMe storage devices into D3 mode at suspend time so that they will come back up properly on resume. The past year or two AMD has been dealing with power management quirks with some AMD Ryzen laptops losing NVMe on resume from s2idle suspend among other s2idle quirks/bugs under Linux.
Modern AMD systems require that the NVMe controller is put into D3 over a modern standby / suspend-to-idle cycle but some system firmware/BIOS aren't properly handling things. So the Linux ACPI code had been checking for AMD CPU IDs and forcing it for Picasso / Renoir / Lucienne / Cezanne platforms. But rather than limiting this behavior to specific CPU IDs, to make it more future-proof and robust the change ahead of Linux 6.10-rc4 is forcing the storage D3 functionality for AMD Zen CPUs where low-power idle support is also detected.
AMD Linux engineer Mario Limonciello explained in the patch:
"A Rembrandt-based HP thin client is reported to have problems where the NVME disk isn't present after resume from s2idle.
This is because the NVME disk wasn't put into D3 at suspend, and that happened because the StorageD3Enable _DSD was missing in the BIOS.
As AMD's architecture requires that the NVME is in D3 for s2idle, adjust the criteria for force_storage_d3 to match *all* Zen SoCs when the FADT advertises low power idle support.
This will ensure that any future products with this BIOS deficiency don't need to be added to the allow list of overrides." That change was merged on Friday as part of the ACPI material for Linux 6.10-rc4. This will be found in Sunday's Linux 6.10-rc4 release while it's also marked for back-porting and thus will appear in the stable Linux kernel series over the coming days.
| 16
| 1,760,718,890.926329
|
https://www.phoronix.com/news/AMD-Linux-PMU-Power-Per-Core
|
AMD Posts New Linux Patches For Per-Core CPU Energy Counters
|
Michael Larabel
|
After an attempt in early 2023 didn't pan out, today an AMD Linux engineer posted a new kernel patch series for enabling per-core RAPL energy counter support for AMD processors. With this patch series when using Linux's venerable perf utility it's now possible for reading the power use on a per CPU core basis using a new "power_per_core" PMU.
The patch series posted on Monday morning by AMD's Dhananjay Ugwekar adds a new "power_per_core" PMU metric as a per-core energy counter. Ugwekar explained in the patch series:
"Currently the energy-cores event in the power PMU aggregates energy consumption data at a package level. On the other hand the core energy RAPL counter in AMD CPUs has a core scope (which means the energy consumption is recorded separately for each core). Earlier efforts to add the core event in the power PMU had failed, due to the difference in the scope of these two events. Hence, there is a need for a new core scope PMU.
This patchset adds a new "power_per_core" PMU alongside the existing "power" PMU, which will be responsible for collecting the new "energy-per-core" event." With this there's the ability to now see on a per-core basis the energy use to complement the existing socket/package-level use.
The patches for this per-core energy counter support are now out for review and will hopefully make it to the mainline kernel now that it works around last year's obstacle to the support.
| 4
| 1,760,718,891.721598
|
https://www.phoronix.com/news/Linux-611-AMD-SEV-SNP-KVM-Guest
|
Linux 6.11 To Merge Support For Running AMD SEV-SNP KVM Guests
|
Michael Larabel
|
The patches have been years in the making around AMD SEV-SNP encrypted virtualization and various elements have been upstreamed in prior kernel versions while for the upcoming Linux 6.11 cycle are finally the Kernel-based Virtual Machine (KVM) bits for launching SEV-SNP protected guest virtual machines.
After going through 14 rounds of review on the SEV-SNP hypervisor support dating back two years, the KVM bits were queued this week into the KVM "next" branch ahead of the Linux 6.11 merge window opening in July. AMD has long maintained the SEV patches out-of-tree while going through the lengthy journey of getting all of the bits upstreamed. Secure Encrypted Virtualization Secure Nested Paging (SEV-SNP) is found with AMD EPYC 7003 "Milan" server processors and newer. SEV-SNP can help prevent malicious hypervisor-based attacks and more security protections compared to the earlier SEV base support and SEV-ES. This code was characterized back during the Linux 6.9 cycle as being for "the ultimate goal of the AMD confidential computing" with:
"Add the x86 part of the SEV-SNP host support. This will allow the kernel to be used as a KVM hypervisor capable of running SNP (Secure Nested Paging) guests. Roughly speaking, SEV-SNP is the ultimate goal of the AMD confidential computing side, providing the most comprehensive confidential computing environment up to date.
This is the x86 part and there is a KVM part which did not get ready in time for the merge window so latter will be forthcoming in the next cycle."
That KVM code didn't end up being ready for the Linux 6.10 cycle, but now it is for Linux 6.11.
This merge to KVM's "next" branch this week is the nearly two thousand lines of code getting the KVM SEV-SNP support for guests all in order.
As noted in the merge message, the attestation support is still to come later. Those wishing to learn more about AMD SEV in general can see the developer page.
| 0
| 1,760,718,892.663378
|
https://www.phoronix.com/news/AMD-Peano-LLVM-Ryzen-AI
|
AMD's Newest Open-Source Surprise: "Peano" - An LLVM Compiler For Ryzen AI NPUs
|
Michael Larabel
|
There was a very exciting Friday evening code drop out of AMD... They announced a new project called Peano that serves as an open-source LLVM compiler back-end for AMD/Xilinx AI engine processors with a particular focus on the Ryzen AI SOCs with existing Phoenix and Hawk Point hardware as well as the upcoming XDNA2 found with the forthcoming Ryzen AI 300 series.
AMD's Ryzen AI NPU on Linux is finally getting interesting! Back in January out of the blue was AMD posting an open-source XDNA Linux kernel driver for supporting the Ryzen AI hardware. That kernel driver though remains out-of-tree and AMD hasn't been entirely clear with the community about its plans, etc. More recently I've begun hearing word that they will work toward upstreaming it in the Linux kernel but to date they haven't sent out any patches for review or go through those other formalities. There also hasn't been much in the way of user-space software or details about Ryzen AI on Linux... So imagine my surprise and joy while working on Friday night and noticing their subtle announcement of this new AMD Peano project.
"Peano" is the apparent name for their new LLVM compiler back-end supporting the Ryzen AI SoCs and other AMD/Xilinx AI engines. Stephen Neuendorffer of AMD/Xilinx and part of the "Peano team" announced this new back-end to LLVM developers. He explained of AMD Peano in the announcement on LLVM's Discourse:
"On behalf of AMD, I’m pleased to announce the open sourcing of an LLVM backend for AMD/Xilinx AI Engine processors. These processors exist in a number of devices including RyzenAI SoCs. The repository currently focuses on supporting the AIE2 architecture implemented by the XDNA accelerators in “Phoenix” and “Hawk Point” devices.
...
Note that these accelerators include an array of processors, while the LLVM backend only supports a single processor. Support for devices as a whole is available in open source tools based on MLIR.
...
In addition to support for LLVM code generation, the repository also includes support for Clang, LLD, binutils (e.g. ‘llvm-objdump’), Compiler-RT, and LLVM-LIBC.
...
Generally speaking, AI Engine processors are in-order, exposed-pipeline VLIW processors. Each VLIW instruction bundle specifies the behavior of one or more functional units, which begin executing a new instruction at the same time. The processor pipeline does not include stall logic to enforce data dependencies, and instructions will continue executing in order regardless of other instructions in the pipeline. As a result, the compiler is able to schedule machine instructions which access the same register in ways that potentially overlap.
Other key architectural characteristics include varying width instruction slots between different instruction encodings and relatively small address spaces (20-bit pointer registers). The presence of varying-width instruction slots implies some code alignment restrictions for instructions which are branch or return targets."
AMD will be working to upstream the relevant code into the LLVM codebase. For now this Peano AI engine fork is hosted via Xilinx/llvm-aie on GitHub. The XDNA Phoenix / Hawk Point support is fully in place while the XDNA2 support for upcoming Ryzen AI 300 "Strix Point" hardware is still being developed.
Having this open-source compiler back-end for Ryzen AI NPUs is significant in making the accelerators more useful under Linux. Phoronix readers need not be reminded in the versatility and widespread use of the LLVM compiler infrastructure. This open-source user-space code is also important for facilitating the upstreaming of their open-source XDNA driver into the Linux kernel.
AMD does have documentation on writing a basic code sample now for targeting the Ryzen AI NPU using the XDNA kernel driver and LLVM AIE/Peano compiler.
I'm still going through this code and announcement with yesterday marking the first time I heard of this AMD Peano project. As for the "Peano" name for this compiler, it looks like it might be a play out of NVIDIA's playbook of mathematician/scientist codenames... Giuseppe Peano was a prominent Italian mathematician who died in Turin in 1932.This is a great milestone to see albeit something that should have happened months ago... Ryzen AI as a reminder debuted a year ago with the Ryzen 7040 series. As a reminder for comparison, Intel had their IVPU kernel driver upstreamed into the Linux kernel for their NPU even before Meteor Lake shipped. Intel's IVPU driver also already has Arrow Lake and Lunar Lake support upstream. Intel also has their open-source NPU plug-in within OpenVINO, their NPU Python acceleration library, and other code available. Intel's NPU Linux support has been much more punctual than AMD. In any event having this open-source compiler backend should be useful in beginning to jump start the Linux ecosystem/support around leveraging the growing number of Ryzen AI SoCs.Next up, seeing the AMD XDNA driver in the mainline Linux kernel? In any event a nice (coincidental) birthday surprise with Phoronix turning 20 years old this week of advocating for open-source and Linux hardware support while having this AMD Peano open-source code drop to end out the week.
| 23
| 1,760,718,892.735048
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https://www.phoronix.com/news/Ryzen-AI-300-Laptop-Shopping
|
Shopping For A Launch-Day AMD Ryzen AI 300 Series Laptop For Linux Testing
|
Michael Larabel
|
With this week's Computex announcement by AMD of the Ryzen AI 300 series laptop processors built atop Zen 5, one of the pleasant aspects has been several laptop models being announced already to be powered by either the Ryzen AI 9 365 or Ryzen AI 9 HX 370 flagship models. Some models are also already available for pre-order ahead of launch day. This is quite nice compared to in the past there was often at times quite a delay between the initial AMD Ryzen mobile announcements and being able to (pre)order any hardware. And thus I've already been looking around to coordinate near launch day Linux testing of the new AMD Zen 5 powered Ryzen AI 300 series hardware.
I've been evaluating the different announced AMD Ryzen AI 300 series laptops to decide on what to pre-order to provide punctual support for Linux support testing and performance benchmarking of the first RDNA 3.5 + Zen 5 laptop processors. As is typically the case, I resort to usually buying one or two laptops each (interesting) Intel/AMD generation retail due to most major laptop vendors not being particularly concerned about Linux support nor their marketing budgets for review samples catering to the small percentage of Linux consumers. AMD also typically hasn't been helpful in providing any hardware on the laptop side for Linux testing. In the months ahead there will almost surely be new Linux-minded laptops from the likes of Framework, System76, and TUXEDO, but to be able to provide timely insight to the Linux support and performance at launch, it's typically left to whatever hardware I am able to afford in providing prompt testing for the Linux community.
Thus this week I've been looking at the announced AMD Ryzen AI 300 series laptops in deciding what model to pre-order. Most (all?) of the laptops available to pre-order for launch day availability so far are from ASUS. I haven't bought an ASUS laptop since I think the Intel Haswell days and there's been some discontent by readers and others around ASUS support and warranties more recently, but looks like I may end up buying an ASUS laptop to provide punctual Ryzen AI 300 series Linux testing in July. At least the ASUS laptop support on Linux has been improving a lot thanks to the work of Luke Jones on the ASUS WMI driver.
Of the ASUS laptops available to pre-order, all of the AMD Ryzen AI 9 HX 370 series laptops have been with NVIDIA GeForce RTX graphics. That doesn't really interest me as I'd much prefer the integrated graphics only for Linux testing. Plus the hybrid graphics under Linux can at times be problematic and ultimately the NVIDIA RTX dGPU just leads to an increased price tag. It's a bummer that there aren't any Ryzen AI 9 HX 370 laptops yet with just integrated RDNA 3.5 graphics, but the lower tier AMD Ryzen AI 9 365 there is.
The ASUS Zenbook S 16 3K OLED Touch Screen Laptop (6584435 / UM5606WA-S16.R3651TB) with AMD Ryzen AI 9 365 has just the RDNA 3.5 integrated graphics. The ASUS Zenbook S UM5606WA-S16 has the 10-core Ryzen AI 9 365 with 24GB of LPDDR5X RAM, 1TB NVMe SSD, 3840 x 2400 OLED 120Hz display, and relies on the Radeon 880M integrated graphics. The price-tag on the laptop is $1399 USD.
Plus this ASUS Zenbook with Ryzen AI 9 365 is expected to be available on 15 July while some models won't be out until 28 July.
So for lack of other options available with the Ryzen AI 9 365 / Ryzen AI 9 HX 370 using just the integrated graphics, it's likely this ASUS Zenbook S I'll be pre-ordering for Linux testing. If anyone sees any other options available in the coming days, please let me know. Thanks to those subscribing to Phoronix Premium (special thanks to those making the leap in joining as part of the Phoronix 20th birthday special) or viewing the site without ad-blockers for making this purchase possible for providing the Linux insight into these next-generation AMD Ryzen laptop SoCs.
So with that said, within a few days of ~15 July, I should be able to deliver these first AMD Ryzen AI 300 series Linux laptop support information/compatibility and performance benchmarks of the new Zen 5 cores. I'm soon beginning my re-testing of existing laptops on hand atop the freshest Linux software stack. My expectation is that using Linux 6.10 Git and Mesa 24.2-devel should be primed for success on the RDNA 3.5 + Zen 5 laptop SoCs... Perhaps Linux 6.9 and Mesa 24.1 will be good enough too, but as there's still been a flow of new patches in recent weeks, I'll first start with the leading-edge software stack. In any case AMD engineers have been busy both on the Zen 5 CPU side and polishing of RDNA 3.5 while also preparing for next-gen RDNA 4 discrete graphics. The main sore spot with the Ryzen AI 300 series will likely come down to the Ryzen AI NPU. Since earlier this year AMD has published the XDNA open-source Linux kernel driver for AMD NPU acceleration but that kernel driver isn't yet upstream and AMD's been quiet on the NPU Linux side about their plans or expanding their user-space software support. At least it was mentioned in the forums a few days ago that AMD is indeed working toward eventually having that NPU kernel driver upstreamed.
| 27
| 1,760,718,894.067441
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https://www.phoronix.com/news/Linux-6.10-cpupower-Zen-5-Freq
|
Linux 6.10 Fixes AMD Zen 5 CPU Frequency Reporting With cpupower
|
Michael Larabel
|
This week's pull request of power management fixes for the Linux 6.10 kernel has an important change for the in-tree cpupower utility to fix P-State frequency reporting on upcoming Zen 5 (Family 1Ah) processors.
Now merged as part of the power management fixes is updating the cpupower utility to properly report P-State frequencies on AMD Zen 5 processors. This fix is for when using the ACPI CPUFreq driver. With newer AMD Ryzen processors defaulting to the AMD P-State driver, this change primarily is for AMD 5th Gen EPYC servers or others not opting to use the AMD P-State driver.
As AMD CEO Dr. Lisa Su announced at Computex this week, look for 5th Gen EPYC servers in H2'2024 with up to 192 cores per socket.
Due to some MSR changes with AMD Family 1Ah and beyond, the cpupower driver needs some small changes to properly account for the P-State frequency.
The fix was merged to Linux 6.10 Git as part of this pull request. Presumably it will be back-ported as well to the stable kernel series. That pull also has a fix for the AMD P-State driver due to an inconsistency in the maximum frequency reported. The "scaling_max_freq" value was reported in MHz while the minimum and current frequencies are reported in KHz. Now the AMD P-State driver is changing scaling_max_freq to report in KHz as well so it matches the other sysfs values.
| 0
| 1,760,718,894.861432
|
https://www.phoronix.com/news/AMD-Ryzen-9000-Series-Zen-5
|
AMD Ryzen 9000 Series Announced - Zen 5 Showing Big Generational Uplift
|
Michael Larabel
|
Arguably most exciting out of AMD's slew of Computex 2024 announcements is finally making official the Ryzen 9000 "Granite Ridge" processors built atop the new Zen 5 cores.
AMD Ryzen 9000 series processors will begin shipping in July along with the Ryzen AI 300 mobile series as the first Zen 5 products. The Zen 5 core is bringing improved branch prediction accuracy and latency, higher throughput with wider pipelines and vectors, and a deeper window size.
AMD is talking up to 2x the instruction bandwidth, data bandwidth, and AI performance -- including better AVX-512 throughput compared to Zen 4 where AVX-512 was originally introduced on the AMD side.
Across games, web browsers, and creator workloads, AMD is talking up around a 16% IPC uplift with Zen 5 compared to Zen 4. With Blender, for example, the open-source rendering software is seeing around 23% higher performance over Zen 4.
The flagship SKU announced at Computex is the AMD Ryzen 9 9950X that is 16 cores / 32 threads with a 5.7GHz boost frequency and 80MB L2+L3 cache while having a 170 Watt TDP. AMD's benchmarks under Windows showing the Ryzen 9 9950X far exceeding the Intel Core i9 14900K... Of course, we'll be putting the new AMD Ryzen 9000 series under the Linux microscope at Phoronix when the time comes.
With the Ryzen 9000 series also comes the new X870/X870E chipsets as a new option while existing AM5 motherboards with a BIOS flash can work with the new processors. Going for the X870/X870E motherboards means USB 4.0 is standard across all of them, PCIe Gen 5 on graphics and NVMe for all motherboards, and higher AMD EXPO memory support.
Alongside the AMD Ryzen 9 9950X flagship, the 12-core Ryzen 9 9900X, 8-core Ryzen 9 9700X, and 6-core Ryzen 5 9600X are also releasing in July. Stay tuned for Linux performance tests and benchmarks of these new AMD Ryzen 9000 series (Zen 5) desktop processors. AMD isn't announcing any 3D V-Cache "X3D" processor models yet based on Zen 5 but will likely do so in the months ahead.
Exciting times ahead and the figures shown by AMD are exciting for the Zen 5 uplift over Zen 4. I am very eager to get my hands on Zen 5 and begin the Linux support exploration and benchmarking. AMD also announced some of the basic details on the upcoming AMD 5th Gen EPYC "Turin" processors coming in H2'2024.
| 67
| 1,760,718,895.468104
|
https://www.phoronix.com/news/AMD-5th-Gen-EPYC-Turin-192-Core
|
AMD Previews 5th Gen EPYC With Up To 192 Cores Per Socket
|
Michael Larabel
|
In addition to all of the AMD client-side news during Lisa Su's keynote at Computex 2024 (see AMD Ryzen 9000 Series and AMD's Ryzen AI 300 Series Mobile APUs), the AMD CEO also teased the upcoming 5th Gen EPYC processors. AMD 5th Gen EPYC "Turin" processors are still on the way for releasing in H2'2024.
The 5th Gen AMD EPYC processors are built atop Zen 5 and will come in designs up to 192 cores / 384 threads per socket! Presumably the 192 core processors will be leveraging Zen 5C cores. The 192 cores for 5th Gen EPYC has been previously rumored and a nice bump from the 128 cores / 256 threads found with the EPYC 9754 Bergamo processor. The 192 cores is also great given Intel's upcoming 144-core Sierra Forest processors and the elusive AmpereOne processors.
The 4th Gen AMD EPYC Genoa(X) / Bergamo processors continue to perform very well against the competition while I am very eager to see the 5th Gen EPYC performance uplift across a wide range of workloads. Given the AMD Ryzen 9000 (Zen 5) details shared during the Computex keynote, I am very excited for AMD EPYC Turin. More details on the Zen 5 improvements can be found in the Ryzen 9000 series introduction, with those desktop CPUs debuting in July.
For now that's it for the brief 5th Gen EYPC teaser from Computex Taipei. Stay tuned to Phoronix for more on 5th Gen EPYC when the time comes and, of course, a lot of benchmarking.
| 15
| 1,760,718,896.251772
|
https://www.phoronix.com/news/AMD-Instinct-MI325X-MI350-MI400
|
AMD Roadmaps Instinct MI325X Accelerator For Q4, Instinct MI350 In 2025
|
Michael Larabel
|
At Computex 2024, AMD confirmed the Instinct MI325X will be released in Q4'2024 as the successor to the MI300X accelerator. Next year will be the AMD Instinct MI350 series based on the new CFNA 4 architecture. AMD is committing to an annual Instinct accelerator roadmap moving forward as they further up their AI game.
AMD's Instinct MI325X accelerator will feature 288GB of HBM3E memory with 6TB/s of memory bandwidth. The MI325X continues to rely on the CDNA 3 architecture. AMD is talking up 1.3x better compute performance than the competition for the Instinct MI325X.
With the AMD Instinct MI350 series in 2025, AMD is aiming for up to a 35x increase in AI inference performance over current Instinct MI300 series hardware. AMD CDNA 4 is promising big gains over CDNA 3 but in the advanced briefings around their Instinct plans they were light on not revealing too many architectural details.
Meanwhile in 2026, AMD will introduce the Instinct MI400 series built atop the CDNA "Next" architecture.
AMD is committing to an annual roadmap for the Instinct accelerators as it ramps up competition against NVIDIA while also concurrently working on more software improvements too for ROCm and related software components.
| 4
| 1,760,718,898.946805
|
https://www.phoronix.com/news/Linux-cpupower-Fix-AMD-Zen-5
|
Linux cpupower Tool Fix Coming For AMD Zen 5 CPUs
|
Michael Larabel
|
Sent out today as a fix for the Linux kernel's in-tree "cpupower" utility is properly handling P-State frequency reporting for upcoming AMD Zen 5 processors.
The Linux cpupower utility lives within the kernel's source tree and is used for displaying processor power related values. It turns out the existing cpupower utility isn't properly calibrated for Zen 5 (Family 1Ah) with some differing static values and other changes compared to the existing AMD processor support within cpupower.
As the sole patch of today's cpupower pull request for the Linux 6.10 kernel -- and may be back-ported to existing stable kernels -- is fixing cpupower so it can correctly report the P-State frequency information on AMD Zen 5 (Family 1Ah) processors. So just an important little tid-bit of news should you be a cpupower fan and will be using it with the upcoming generation of AMD Ryzen / EPYC processors. Overall though it does appear that the AMD Zen 5 CPU support is largely in order already for Linux aside from a few lingering fixes coming about and any other yet to be announced features that may not yet be wired up.
| 0
| 1,760,718,903.928145
|
https://www.phoronix.com/news/AMD-Fast-CPPC-v4-Linux
|
Updated Patches For AMD "Fast CPPC" To Yield Higher Performance At Same Power Level
|
Michael Larabel
|
One of the patch series that sadly was not ready in time for the Linux 6.10 merge window and thus will need to wait a few months for at least the next kernel is enabling AMD Fast CPPC support for Zen 4 processors. Fast CPPC aims to allow the processor to deliver higher performance at the same power consumption.
Earlier this year I wrote about AMD's work on enabling Fast CPPC for Linux as a feature new to existing Zen 4 processors. The AMD P-State CPU frequency scaling driver makes use of the ACPI Collaborative Processor Performance Control (CPPC) data for describing performance scales and attributes on a per-CPU basis and in turn the kernel requesting desired performance levels. With some AMD processors beginning with current Zen 4 models, there is the notion of "fast CPPC". The Fast CPPC feature when indicated by a CPU bit allows for a faster CPPC loop thanks to architectural enhancements. In turn leveraging AMD Fast CPPC can make for higher performance at the same power level.
Posted this weekend were the AMD Fast CPPC v4 patches now out for kernel review. The patch series simply sums it up as:
"Some AMD Zen 4 processors support a new feature FAST CPPC which allows for a faster CPPC loop due to internal architectural enhancements. The goal of this faster loop is higher performance at the same power consumption." The patches when tested on an AMD Ryzen 7 7840HS have pointed to Fast CPPC allowing 0~2% better performance while the performance-per-Watt can see as much as a ~6% benefit.
Here's to hoping this AMD Fast CPPC support for the AMD P-State driver will be ready in time for the Linux 6.11 kernel later in the summer. AMD Core Performance Boost support is another feature also still undergoing review for the AMD P-State Linux driver.
| 7
| 1,760,718,905.317863
|
https://www.phoronix.com/news/ASRock-Rack-EPYC-4004-BIOS
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ASRock Rack Releases BIOS Update For EPYC 4004 Support With AM5 Ryzen Boards
|
Michael Larabel
|
As a follow-up to this morning's AMD EPYC 4004 review and benchmarks, Supermicro, ASRock Rack, Giga Computing, Tyan, and others have announced new motherboards/servers for these entry-level EPYC servers. In addition with the likes of ASRock Rack they have already published BIOS updates enabling existing AM5 Ryzen server boards to officially support the EPYC 4004 series processors.
ASRock Rack announced this morning that they have published BIOS updates for their AM5 Ryzen motherboards and server platforms to extend them to covering the EPYC 4004 series. Not too surprising given the commonality between the Ryzen 7000 series and EPYC 4004 series. As noted in this morning's EPYC 4004 review:
"Speaking of Ryzen for Server and EPYC, you may be wondering... What happens if trying to install an EPYC 4004 in an existing AM5 consumer motherboard? Or a Ryzen CPU in a new EPYC 4004 motherboard? Given the platform commonality and same AGESA, it does work but is not officially supported." Still having a ASRockRack 1U4LW-B650/2L2T B650D4U-2L2T/BCM around, I decided to try it out. From the ASRockRack 1U4LW-B650/2L2T page there wasn't any new BIOS update but when navigating to the B650D4U-2L2T/BCM motherboard page there was indeed a new BIOS release today enabling EPYC 4004 series support.
The ASRockRack 1U4LW-B650/2L2T B650D4U-2L2T/BCM is the platform I used for the prior AMD Ryzen 7000 series server testing and has been a great 1U server platform.
Indeed with the new BIOS release and then installing an AMD EPYC 4584PX 16-core 3D V-Cache server processor, indeed it worked out fine.
Nice seeing this work out and allowing for the EPYC 4004 processors to deploy in new EPYC 4004 minded servers/motherboards as well as existing AM5 platforms from the major server OEMs/ODMs. Thus rather robust availability for those looking to assemble an entry-level/SMB server.
If you didn't have a chance yet, continue on reading the AMD EPYC 4004 series review/benchmarks and how these EPYC Zen 4 processors annihilate the Intel Xeon E-2400 series competition.
| 10
| 1,760,718,907.7768
|
https://www.phoronix.com/news/AMD-Supermicro-OSFF
|
AMD & Supermicro Collaborating On Open-Source Firmware With The OSFF
|
Michael Larabel
|
As more positive indications around AMD's OpenSIL effort for open-source CPU silicon initialization to eventually replace AGESA, both AMD and Supermicro are now collaborating with the Open-Source Firmware Foundation. Supermicro has also publicly shown off a platform with OpenSIL+Coreboot and is said to be exploring OpenBMC for future hardware.
The Open-Source Firmware Foundation was established in 2022 by founding members 9elements Cyber Security and Mullvad VPN. LinuxBoot and Coreboot since joined the Open-Source Firmware Foundation (OSFF).
With AMD working more on open-source firmware these days due to customer demand, OpenSIL eventually set to replace AGESA around 2026, their new reference motherboards leveraging OpenBMC, AMD Chromebooks supporting Coreboot per Google requirements, etc, it's the logical next step they join with the Open-Source Firmware Foundation to increase collaborations. The OSFF announced today that both AMD and Supermicro have "aligned" with the Open-Source Firmware Foundation to promote open-source firmware.
At the recent OCP Regional Summit, Supermicro and AMD showed off the Supermicro H13SSL-N with AMD 4th Gen EPYC CPU running atop AMD OpenSIL and using Tianocore and Coreboot/LinuxBoot. Great to see Supermicro already adapting and exploring OpenSIL/Coreboot integration as with the OpenSIL efforts publicly up to this stage it all appeared centered around AMD's reference motherboards.
Supermicro is also said to be exploring OpenBMC use in their future motherboards/servers.
More details on this Open-Source Firmware Foundation collaboration with AMD and Supermicro via the OSFF blog.
| 4
| 1,760,718,909.180268
|
https://www.phoronix.com/news/Linux-6.10-AMD-P-State
|
Linux 6.10 AMD P-State To Deliver Fixes, Better Support On Older Zen CPUs
|
Michael Larabel
|
The recent AMD P-State Linux driver patches for heterogeneous core CPU topology, Fast CPPC, and Core Performance Boost haven't made it to the Linux power management's "-next" branch ahead of the imminent Linux 6.10 cycle. Thus it looks like those features won't be ready to make it for v6.10 unless by chance being deemed ready in the coming days and then sent in as part of a secondary set of merge window changes. However, some other AMD P-State fixes/improvements are queued up.
For the AMD P-State CPU frequency scaling driver in Linux 6.10, queued up earlier this month were the driver updates:
"- Enable CPPC v2 for certain processors in the family 17H, as requested by TR40 processor users who expect improved performance and lower system temperature.
- Change latency and delay values to be read from platform firmware firstly for more accurate timing.
- A new quirk is introduced for supporting amd-pstate on legacy processors which either lack CPPC capability, or only only have CPPC v2 capability." Those changes are ready to go for AMD P-State in Linux 6.10.
Plus this patch was queued in at the end of this week. This fixes an issue with the highest frequency state could limit the performance:
"To address the performance drop issue, an optimization has been implemented. The incorrect highest performance value previously set by the low-level power firmware for AMD CPUs with Family ID 0x19 and Model ID ranging from 0x70 to 0x7F series has been identified as the cause.
To resolve this, a check has been implemented to accurately determine the CPU family and model ID. The correct highest performance value is now set and the performance drop caused by the incorrect highest performance value are eliminated.
Before the fix, the highest frequency was set to 4200MHz, now it is set to 4971MHz which is correct." This was a regression with Linux 6.9 for some hardware when introducing the AMD P-State Preferred Core support.
| 5
| 1,760,718,911.750286
|
https://www.phoronix.com/news/Linux-6.9-One-More-Zen-5-PCI-ID
|
Another AMD Zen 5 PCI ID Squeezing Into Linux 6.9
|
Michael Larabel
|
The Linux 6.9 kernel should debut as stable later today unless Linus Torvalds has second thoughts and decides to delay it by issuing a v6.9-rc8 kernel instead that would then push out the official release by an extra week. In any event, as a last-minute "x86/urgent" pull request is another Zen 5 PCI ID being added.
As part of the many AMD (and Intel) changes in Linux 6.9 there is continued enablement around upcoming Zen 5 mobile/desktop/server processors. Beyond the feature material back during the Linux 6.9 merge window, there's been a follow-up patch adding More AMD Zen 5 model IDs as part of Family 1Ah (Family 26). Now on this potential last day of the Linux 6.9 cycle, another patch has been sent in via x86/urgent for adding a PCI ID belonging to some Family 26 Zen 5 CPUs.
The newest patch is adding the 0x12bb PCI ID that is present for AMD Family 1Ah Model 70h series processors. The patch message simply notes:
"Add the new PCI Device IDs to the MISC IDs list to support new generation of AMD 1Ah family 70h Models of processors." That additional AMD Zen 5 PCI ID patch was sent in as part of this morning's x86/urgent for v6.9. There is a second patch too and that is a common fix for the AMD topology code rework that is new to Linux 6.9. That x86 AMD topology fix is for ensuring the last level cache ID is properly set for all cases.
It's looking like Linux ~6.9 is hopefully in good shape as a baseline for upcoming AMD Zen 5 processors at least as far as critical support is concerned. There are other features still to land like Bus Lock Trap and PCIe TPH support but with trying to get these IDs in order ahead of Linux 6.9 stable is hopefully a good sign that at least all the basic Zen 5 support is working on this kernel.
| 2
| 1,760,718,912.860607
|
https://www.phoronix.com/news/AMD-AMF-FFmpeg-Better-2024
|
AMD Aims For AMF Decode In FFmpeg, Questioned Over Vulkan Video Commitment
|
Michael Larabel
|
AMD last week sent out a set of patches to enhance the open-source FFmpeg multimedia library with integration around the AMD Advanced Media Framework (AMF). The AMF SDK allows for "optimal" access to AMD GPUs for multimedia processing but this patch series questioned the need in an era of Vulkan Video APIs beginning to see adoption.
The newest AMD FFmpeg patch series for AMF is on adding hardware context "hwcontext_amf" support along with AMF-based H.264, HEVC, and AV1 decoders. The patches also enable AMD SmartAccess Video (SAV) functionality for AMF encoders. SAV enables the parallelization of encode/decode streams across multiple VCN hardware instances. There are also two AMF filters initially proposed for FFmpeg: "vpp_amf" for simple scaling and color conversion and then "sr_amf" for advanced scaling algorithms like FSR. There is already FFmpeg AMF support on the encode side.
Dmitrii Ovchinnikov explained with the patch series:
"Adds hwcontext_amf, which allows to use shared AMF context for the encoder, decoder and AMF-based filters, without copy to the host memory. It will also allow you to use some optimizations in the interaction of components (for example, SAV) and make a more
manageable and optimal setup for using GPU devices with AMF in the case of a fully AMF pipeline. It will be a significant performance uplift when full AMF pipeline with filters is used."
FFmpeg developer Lynne who has done a lot of the Vulkan Video enablement for this dominant open-source library questioned though why AMD is still working so much on AMF when they could leverage the more open Vulkan Video ecosystem. Lynne wrote in the messaging exchange:
"Vulkan encode is quite soon going to get all features needed to allow for all vendor-specific optimizations to be exposed, though I think you should already be in the loop. Is there a reason to add this code in now? AMF is still hardly that used, at least in the Linux world, as it isn't really packaged everywhere, and on Windows, D3D12 is gaining more traction.
AMD has also already released all FSR-based code for upscaling."
To which the response was sadly:
"DX12 and Vulkan native encoders will expose less features compare to AMF, at least in foreseeable feature. The missing features include low latency, PreAnalysis including look-ahead etc. AMF context on Windows allows fully enable SAV - ability to utilize VCNs in dGPU and APU in a single session. Eventually specialized multimedia AMD cards could be added seamlessly to FFmpeg with AMF integration. AMF FSR(VSR) includes YUV version with focus on videos which is not available in AMD FSR aimed for gaming."
FFmpeg developer Lynne still isn't convinced though whether this AMD AMF update should be merged into FFmpeg:
"Do you really not talk with each other over there? You should. This is a lot of vendor-specific code for which an overlap
with a standard API already exists, and I'd just prefer to know why this should be merged and maintained now, as Vulkan video adoption is finally starting."
The latest patches can be found here. So far the patch series hasn't been merged to upstream FFmpeg, so we'll see if it's ultimately accepted or if it's rejected in favor of encouraging more open / industry standard APIs in 2024.
| 61
| 1,760,718,915.452781
|
https://www.phoronix.com/news/LLVM-Slower-With-AMD-Opts
|
LLVM Dealing With Slower Performance On AMD CPUs When Targeting AMD Zen Optimizations
|
Michael Larabel
|
Recently there was an LLVM bug report of "Worse runtime performance on Zen CPU when optimizing for Zen." Well, that's not good... Fortunately, that bug is now fixed with the latest LLVM Clang compiler code but other deficiencies in the AMD CPU optimization targeting remain.
Opened last week was the bug report of "[X86] Worse runtime performance on Zen CPU when optimizing for Zen" With a sample code snippet it demonstrated that using "-march=znver4" targeting on an AMD Ryzen 9 7950X processor ended up generating around 25% slower performance than when using the more generic "-march=x86-64-v4" or even the "-march=x86-64" baseline.
As of today this bug report has been closed thanks to this LLVM commit: [X86] Enable TuningSlowDivide64 on Barcelona/Bobcat/Bulldozer/Ryzen Families. That commit message explained:
"Despite most AMD cpus having a lower latency for i64 divisions that converge early, we are still better off testing for values representable as i32 and performing a i32 division if possible.
All AMD cpus appear to have been missed when we added the "idivq-to-divl" attribute - this patch now matches Intel cpu behaviour (and the x86-64/v2/3/4 levels)."
While it's good that original bug report over slower performance when engaging AMD Zen 4 (znver4) tuning is closed, that's not the end of story. Another bug report has since opened for LLVM: "[X86] Worse runtime performance on Zen 4 CPU when optimizing for znver4 or skylake."
"The following code runs around 300% slower on Zen 4 when optimized for znver4 or skylake than when optimized for znver3 or other targets."
That newer bug report found a code snippet that is 300% slower on Zen 4 when using "-march=znver4" (or even the common "-march=skylake" baseline) than when optimized for Zen 3 (-march=znver3) or other CPU targets. An AMD compiler engineer has been assigned to that bug so hopefully it will be root-caused and addressed soon.
AMD has been working a lot on their AMD Optimizing C/C++ Compiler (AOCC) downstream of LLVM but with upstream LLVM/Clang and GCC is where AMD could benefit from greater investment. While traditionally they were very slow in their open-source compiler upstreaming of new CPU targets, with GCC 14 they did provide early Zen 5 (znver5) support ahead of launch. That at least enables all of the new Zen 5 CPU ISA extensions but it doesn't yet provide any new cost table with it still being carried over from Znver4. With upstream LLVM there isn't yet any Znver5 support but at least there it isn't quite as pressing thanks to frequent point releases and six-month feature releases being a big improvement over GCC's infrequent release cadence (months between point releases and annual feature releases). It's still behind Intel's open-source compiler punctuality where with GCC 14 there are Intel CPU targets introduced for Lunar Lake, Panther Lake, Clearwater Forest, and other CPU cores further out than Zen 5.With compiler bugs like these noted, there's still a lot of potential for additional performance gains if AMD would continue ramping up their GCC and LLVM/Clang upstream engineering especially as EPYC continues enjoying great HPC adoption where compiler optimizations tend to be more common place, developers continue embracing Ryzen and Threadripper processors for their boxes, and high core count servers like with AMD EPYC "Bergamo" make for great CI/CD deployments with speedy build times.
| 15
| 1,760,718,916.823016
|
https://www.phoronix.com/news/AMD-PCIe-TPH-Linux-Patches
|
AMD Preparing PCIe TPH Support For Upcoming CPUs
|
Michael Larabel
|
A new patch series sent out today by AMD Linux engineers confirm that PCIe TPH will be supported with "upcoming AMD hardware" as a nice performance optimization feature for PCI Express.
The PCI Express TLP Processing Hints (TPH) are hints that can be injected for improving latency and lowering traffic congestion when there are several possible cache locations in the system. The TLP Processing Hints can note the optimal location of a Transaction Layer Packet (TLP). Sent out today were a set of Linux kernel patches from AMD for implementing PCIe TPH and confirming that this will be supported with upcoming AMD hardware... Given the timing of these patches and AMD tending to not work on Linux enablement multiple generations out, this is presumably for Zen 5 processors. Whether it's for all Zen 5 processors or limited to AMD EPYC Zen 5 processors where it will be most beneficial isn't clear from today's patches.
The AMD patch series cover letter further explains:
"TPH (TLP Processing Hints) is a PCIe feature that allows endpoint devices to provide optimization hints for requests that target memory space. These hints, in a format called steering tag (ST), are provided in the requester's TLP headers and allow the system hardware, including the Root Complex, to optimize the utilization of platform resources for the requests.
Upcoming AMD hardware implement a new Cache Injection feature that leverages TPH. Cache Injection allows PCIe endpoints to inject I/O Coherent DMA writes directly into an L2 within the CCX (core complex) closest to the CPU core that will consume it. The technology is targeted at applications whose performance is sensitive to the latency of inbound writes as seen by a CPU core. The applications include networking and storage applications.
This series implements generic TPH support in Linux. It allows STs to be retrieved from ACPI _DSM (defined by ACPI) and used by PCIe end-point drivers as needed. As a demo, it includes an usage example in Broadcom BNXT driver. When running on Broadcom NICs with proper firmware, Cache Injection shows substantial memory bandwidth saving using real-world benchmarks."
Exciting feature! There are 9 patches out for review implementing the kernel-side functionality. Hopefully it will be upstreamed soon in time for that upcoming AMD hardware with the PCIe TPH support. With this patch series besides the core PCIe TPH enablement in the Linux kernel, only the Broadcom BNXT "bnxt_en" network driver is initially modified for making use of PCIe TPH support but hopefully other driver adaptations will come in time now that hardware support will be rolling out.
| 9
| 1,760,718,918.985639
|
https://www.phoronix.com/news/AMD-Ryzen-AI-300-Series-Zen-5
|
AMD's Ryzen AI 300 Series Mobile APUs Should Be Interesting For Next-Gen Laptops
|
Michael Larabel
|
In addition to announcing the AMD Ryzen 9000 series desktop processors powered by Zen 5, Lisa Su at Computex 2024 also announced the AMD Ryzen AI 300 series as the next-generation mobile processors powered by Zen 5 CPU cores while sporting RDNA 3.5 (also referred to as RDNA 3+ and RDNA3 refresh) integrated graphics and an XDNA 2 NPU.
The new AMD Ryzen AI 300 series is quite exciting on the mobile side for further enhancing its capabilities over current Intel Core Ultra "Meteor Lake" mobile processors and getting ready to battle the Intel Lunar Lake processors due out in Q3.
AMD Ryzen AI 300 series will feature up to 12 Zen 5 CPU cores for a total of 24 threads in the top-end SKUs. There is RDNA 3.5 graphics for an upgraded integrated graphics experience with up to 16 compute units. And the new XDNA 2 NPU is rated for delivering 50 TOPS performance for very competitive AI performance.
The top-end model announced for Computex 2024 is the AMD Ryzen AI 9 HX 370 with 12 cores / 24 threads, a 5.1GHz maximum boost frequency, 36MB cache, 50 TOPS NPU, and Radeon 890M graphics. The AMD Ryzen AI 9 365 was also announced as a 10-core / 20-thread Zen 5 mobile APU with 5.0GHz maximum boost frequency, 34MB cache, 50 TOPS NPU, and Radeon 880M Graphics.
With the AMD XDNA 2 neural processing unit, AMD is talking up big gains with up to 5x the compute capacity and up to 2x the power efficiency. AMD is claiming that their 3rd Gen AMD Ryzen AI will be able to outperform not only the Intel Meteor Lake by wide margins but also the Apple M4, the anticipated performance of Intel Lunar Lake, and also the Qualcomm Snapdragon Elite X.
AMD Ryzen AI 300 series laptops should begin appearing in July.
AMD XDNA 2 sounds quite interesting but the level of Linux support is still less than desirable. Earlier this year AMD did publish an XDNA Linux driver but it's not mainlined in the Linux kernel, there's been no attempt to upstream it yet, and no clear roadmap plans yet shared by AMD. The user-space software support for the AMD XDNA Linux driver is also limited. So while AMD is known for their great CPU and GPU support on Linux, their NPU/XDNA effort has been off to a slower start. Meanwhile Intel already has upstreamed their iVPU driver for supporting their NPU found in Meteor Lake as well as already having Arrow Lake and Lunar Lake support in the upstream kernel. User-space software like OpenVINO is working fine with the iVPU kernel driver.
AMD is talking up the AMD Ryzen AI 9 HX 370 as having much better performance than the Apple M3 and Intel Core Ultra 155H. Of course, their benchmarks were with Microsoft Windows 11... And they talked up Windows Copilot+ and "next-gen Windows AI PCs" heavily in the presentation. We'll see how the Linux performance is overall once getting AMD Ryzen AI 300 series hardware in the Phoronix lab.
The RDNA 3.5 integrated graphics and Zen 5 CPU support should be in good shape right now for Linux use if using the very latest open-source upstream software. The main caveat is the less than ideal state of the XDNA Linux driver for the XDNA 2 NPU, which will hopefully be improving with time. That's all for now until seeing hardware for testing in the coming month(s) to deliver a first-hand Linux report.
| 14
| 1,760,718,920.193038
|
https://www.phoronix.com/news/AMD-Linux-perf-schedstat-Tool
|
AMD Linux Engineers Introduce New "schedstat" Tool
|
Michael Larabel
|
AMD Linux engineers have introduced a new perf tool called "schedstat" that aims to be less resource intensive and convenient than the existing "perf sched" tool for profiling kernel scheduler behavior.
The schedstat tool conveniently reports the time elapsed in jiffies and other CPU scheduling statistics. The intent of the tool is to be lighter-weight and used by developers and others profiling Linux kernel scheduler changes.
AMD engineer Ravi Bangoria explained of the schedstat tool:
"Existing `perf sched` is quite exhaustive and provides lot of insights into scheduler behavior but it quickly becomes impractical to use for long running or scheduler intensive workload. For ex, `perf sched record` has ~7.77% overhead on hackbench (with 25 groups each running 700K loops on a 2-socket 128 Cores 256 Threads 3rd Generation EPYC Server), and it generates huge 56G perf.data for which perf takes ~137 mins to prepare and write it to disk.
Unlike `perf sched record`, which hooks onto set of scheduler tracepoints and generates samples on a tracepoint hit, `perf sched schedstat record` takes snapshot of the /proc/schedstat file before and after the workload, i.e. there is zero interference on workload run. Also, it takes very minimal time to parse /proc/schedstat, convert it into perf samples and save those samples into perf.data file. Result perf.data file is much smaller. So, overall `perf sched schedstat record` is much more light-weight compare to `perf sched record`.
We, internally at AMD, have been using this (a variant of this, known as "sched-scoreboard") and found it to be very useful to analyse impact of any scheduler code changes.
Please note that, this is not a replacement of perf sched record/report. The intended users of the new tool are scheduler developers, not regular users." Schedstat sounds like a great fit and complementary tool to the common "perf sched" functionality and a nice evolution of their earlier sched-scoreboard tool.
AMD's schedstat tool was presented today on the Linux kernel mailing list as part of this patch series seeking comments from other developers on interest and upstreaming this code into the perf tools within the Linux kernel source tree.
| 3
| 1,760,718,920.255203
|
https://www.phoronix.com/news/AMD-Heterogeneous-P-State-Linux
|
AMD Posts Patches For Improving Heterogeneous Core Type CPUs On Linux
|
Michael Larabel
|
AMD engineers posted a new set of Linux driver patches on Tuesday that "addresses critical issues and enhances performance settings for CPUs with heterogeneous core types" while using the AMD P-State CPU frequency scaling driver.
AMD has yet more amd_pstate driver patches on the way for the Linux kernel. AMD Linux engineer Perry Yuan explained of the new patches:
"This patchset addresses critical issues and enhances performance settings for CPUs with heterogeneous core types in the AMD pstate driver. Specifically, it resolves problems related to calculating the highest performance and frequency on the latest CPUs with preferred cores. Additionally, the patchset includes documentation improvements in amd-pstate.rst, offering a comprehensive guide covering topics such as recommended reboot requirements during driver switching, debugging procedures for driver loading failures." The patches help improve the debugging when encountering broken ACPI CPPC tables, making use of a CPU bit for detecting AMD heterogeneous core topology, This AMD heterogeneous core topology is for CPUs that have a mix of say Zen 4 and Zen 4C cores.
This patch series is noted to fix the AMD Ryzen 7 7840HS never boosting to max frequency and related problems like amd_pstate not loading on some hardware.
| 4
| 1,760,718,921.515738
|
https://www.phoronix.com/news/AMD-Core-Perf-Boost-Per-CPU
|
AMD Core Performance Boost For Linux Getting Per-CPU Core Controls
|
Michael Larabel
|
For the past several months AMD Linux engineers have been working on AMD Core Performance Boost support for their P-State CPU frequency scaling driver. The ninth iteration of these patches were posted on Monday and besides the global enabling/disabling support for Core Performance Boost, it's now possible to selectively toggle the feature on a per-CPU core basis.
These patches have been for handling Core Performance Boost within the AMD P-State driver and also the ability to toggle the feature via the /sys/devices/system/cpu/amd_pstate/cpb_boost interface. Core Performance Boost is for allowing the AMD CPUs to operate within their turbo/boost frequency range. Most users will want to keep Core Performance Boost (Turbo Core) enabled, but those wanting to dynamically reduce/limit their processor power consumption will be able to toggle the support with these pending driver patches.
With the new "v9" patches, the AMD CPB P-State patches have been re-based against the latest Linux power management kernel code, various minor alterations, and now the ability to toggle per-CPU boost control. This new addition lets users toggle individual CPU cores for having Core Performance Boost or not. The new interface is under /sys/devices/system/cpu/cpuX/cpufreq/amd_pstate_boost_cpb for each CPU core. Thus users can tune whether particular CPU cores are boosted above the base frequency.
These newest AMD CPB Linux patches are out for review on the Linux power management mailing list.
| 12
| 1,760,718,922.641052
|
https://www.phoronix.com/news/Ubuntu-24.04-AMD-EPYC-Milan
|
AMD 3rd Gen EPYC "Milan" Sees Some Performance Benefits To Ubuntu 24.04 LTS
|
Michael Larabel
|
With the recently released Ubuntu 24.04 LTS I've shown various benchmarks how it can deliver nice performance gains over both Ubuntu 23.10 and the existing Ubuntu 22.04 LTS on different platforms. Those benchmarks have tended to focus on the latest-generation processors/platforms given that's where the excitement is these days. But for those on older platforms like AMD 3rd Gen EPYC "Milan" servers, here are some benchmarks looking at the performance impact of an Ubuntu 24.04 LTS upgrade.
For those wondering about the Ubuntu 22.04 LTS vs. 24.04 LTS performance difference for more mature platforms than the other Ubuntu 24.04 benchmarks I've carried out recently, this quick article is for you. Using a dual socket AMD EPYC 7303 server I recently carried out some benchmarks to see what differences there are going from Ubuntu 22.04 LTS with the latest hardware enablement stack to the brand new Ubuntu 24.04 LTS.
With Ubuntu 24.04 LTS comes the new Linux 6.8 kernel, the GCC 13 compiler as a significant upgrade over GCC 11 on Ubuntu 22.04, and many other package updates introduced over the past two years.
The OpenJDK Java performance is looking rather nice on Ubuntu 24.04 LTS even for this older EPYC 7003 series server.
Software build times increasing aren't of surprise. Newer GNU Compiler Collection versions tend to build slower as a result of new optimization passes and other additions to increase the performance of the resulting binaries or other features at the expensive of slower build times.
In some general CPU workloads there were wins here and there collected on Ubuntu 24.04 LTS for this AMD EPYC 7303 2P server but far less differences than when running the very newest Intel Xeon and AMD EPYC servers with Ubuntu 24.04.
HPC workloads were commonly delivering slight performance advantages when running on Ubuntu 24.04 LTS with this AMD EPYC server.
Occasional I/O workloads were showing some uplift but for the most part was flat.
Overall there were some wins to using Ubuntu 24.04 LTS on this more mature AMD EPYC 7003 series server but not nearly as much of a difference for the very latest Intel and AMD hardware on Ubuntu 22.04 vs. 24.04 LTS for performance.
| 0
| 1,760,718,922.651492
|
https://www.phoronix.com/news/AMD-Bus-Lock-Trap-Detect-Linux
|
AMD Prepares Linux For "Bus Lock Trap" Feature On Upcoming CPUs
|
Michael Larabel
|
An upcoming AMD micro-architecture (presumably Zen 5 given the timing and history around AMD's Linux hardware enablement...) is introducing Bus Lock Trap as a feature matching Intel's existing split/bus lock detection functionality.
Patches sent out today by AMD Linux engineers prepare for an "upcoming AMD uarch" that will support this Bus Lock Trap feature. When AMD Bus Lock Trap is enabled, it will raise an exception if a bus lock occurs outside of the kernel (above ring zero).
One of the patches does confirm that the AMD Bus Lock Trap feature "functionally works identical to Intel." Intel has long supported this split lock and bus lock functionality under Linux while now with presumably Zen 5 the support is there for AMD processors.
Several years ago Intel engineers did a lot of the Linux kernel preparations for split lock detection with their processors to warn or kill offending applications. Similarly has been the bus lock detection feature too. Both of these aim to warn/kill offending software due to performance penalties or even potential denial of service issues.
AMD's new patches build off that prior Intel split/bus lock code and adding in the AMD processor support. There is also support for Bus Lock Detect on AMD processors for software running within KVM virtual machines.
This isn't the most exciting of features for (presumably) Zen 5 but a nice minor addition for also matching the capabilities of Intel processors for allowing the kernel to better report/handle such locks for performance and denial of service reasons. On the Zen 5 micro-architecture front it's also known publicly about the notable ISA additions as confirmed with the GCC Znver5 patch. Various other Zen 5 processor enablement for the Linux kernel remains ongoing as we await to see the next-gen Ryzen and EPYC processors later this year.
| 0
| 1,760,718,924.122989
|
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